1 /*
2 * Copyright (c) 2018-2019, Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 //!
24 //! \file media_sku_wa_g12.cpp
25 //!
26
27 #include "igfxfmid.h"
28 #include "linux_system_info.h"
29 #include "skuwa_factory.h"
30 #include "linux_skuwa_debug.h"
31 #include "linux_media_skuwa.h"
32 #include "mos_utilities.h"
33
34 #define GEN12_VEBOX2_SUBSLICES 24
35
36 //extern template class DeviceInfoFactory<GfxDeviceInfo>;
37 typedef DeviceInfoFactory<LinuxDeviceInit> DeviceInit;
38
39 static struct LinuxCodecInfo tglCodecInfo =
40 {
41 .avcDecoding = 1,
42 .mpeg2Decoding = 1,
43 .vp8Decoding = 0,
44 .vc1Decoding = SET_STATUS_BY_FULL_OPEN_SOURCE(1, 0),
45 .jpegDecoding = 1,
46 .avcEncoding = SET_STATUS_BY_FULL_OPEN_SOURCE(1, 0),
47 .mpeg2Encoding = SET_STATUS_BY_FULL_OPEN_SOURCE(1, 0),
48 .hevcDecoding = 1,
49 .hevcEncoding = SET_STATUS_BY_FULL_OPEN_SOURCE(1, 0),
50 .jpegEncoding = 1,
51 .avcVdenc = 1,
52 .vp9Decoding = 1,
53 .hevc10Decoding = 1,
54 .vp9b10Decoding = 1,
55 .hevc10Encoding = SET_STATUS_BY_FULL_OPEN_SOURCE(1, 0),
56 .hevc12Encoding = SET_STATUS_BY_FULL_OPEN_SOURCE(1, 0),
57 .vp8Encoding = 0,
58 .hevcVdenc = 1,
59 .vp9Vdenc = 1,
60 };
61
InitTglMediaSku(struct GfxDeviceInfo * devInfo,MediaFeatureTable * skuTable,struct LinuxDriverInfo * drvInfo)62 static bool InitTglMediaSku(struct GfxDeviceInfo *devInfo,
63 MediaFeatureTable *skuTable,
64 struct LinuxDriverInfo *drvInfo)
65 {
66 if ((devInfo == nullptr) || (skuTable == nullptr) || (drvInfo == nullptr))
67 {
68 DEVINFO_ERROR("null ptr is passed\n");
69 return false;
70 }
71
72 if (drvInfo->hasBsd)
73 {
74 LinuxCodecInfo *codecInfo = &tglCodecInfo;
75
76 MEDIA_WR_SKU(skuTable, FtrAVCVLDLongDecoding, codecInfo->avcDecoding);
77 MEDIA_WR_SKU(skuTable, FtrMPEG2VLDDecoding, codecInfo->mpeg2Decoding);
78 MEDIA_WR_SKU(skuTable, FtrIntelVP8VLDDecoding, codecInfo->vp8Decoding);
79 MEDIA_WR_SKU(skuTable, FtrVC1VLDDecoding, codecInfo->vc1Decoding);
80 MEDIA_WR_SKU(skuTable, FtrIntelJPEGDecoding, codecInfo->jpegDecoding);
81 MEDIA_WR_SKU(skuTable, FtrEncodeAVC, codecInfo->avcEncoding);
82 MEDIA_WR_SKU(skuTable, FtrEncodeMPEG2, codecInfo->mpeg2Encoding);
83 MEDIA_WR_SKU(skuTable, FtrIntelHEVCVLDMainDecoding, codecInfo->hevcDecoding);
84 MEDIA_WR_SKU(skuTable, FtrIntelHEVCVLDMain10Decoding, codecInfo->hevc10Decoding);
85
86 MEDIA_WR_SKU(skuTable, FtrEncodeHEVC, codecInfo->hevcEncoding);
87 MEDIA_WR_SKU(skuTable, FtrEncodeHEVC10bit, codecInfo->hevc10Encoding);
88 MEDIA_WR_SKU(skuTable, FtrEncodeHEVC12bit, codecInfo->hevc12Encoding);
89 MEDIA_WR_SKU(skuTable, FtrEncodeHEVC10bit422, codecInfo->hevc10Encoding);
90 MEDIA_WR_SKU(skuTable, FtrEncodeHEVC12bit422, codecInfo->hevc12Encoding);
91 MEDIA_WR_SKU(skuTable, FtrEncodeJPEG, codecInfo->jpegEncoding);
92 MEDIA_WR_SKU(skuTable, FtrEncodeAVCVdenc, codecInfo->avcVdenc);
93 MEDIA_WR_SKU(skuTable, FtrVP9VLDDecoding, codecInfo->vp9Decoding);
94 MEDIA_WR_SKU(skuTable, FtrIntelVP9VLDProfile0Decoding8bit420, codecInfo->vp9Decoding);
95 MEDIA_WR_SKU(skuTable, FtrVP9VLD10bProfile2Decoding, codecInfo->vp9b10Decoding);
96 MEDIA_WR_SKU(skuTable, FtrIntelVP9VLDProfile2Decoding, codecInfo->vp9b10Decoding);
97
98 /* VP8 enc */
99 MEDIA_WR_SKU(skuTable, FtrEncodeVP8, codecInfo->vp8Encoding);
100
101 /* HEVC VDENC */
102 MEDIA_WR_SKU(skuTable, FtrEncodeHEVCVdencMain, codecInfo->hevcVdenc);
103 MEDIA_WR_SKU(skuTable, FtrEncodeHEVCVdencMain10, codecInfo->hevcVdenc);
104
105 /* Vp9 VDENC */
106 MEDIA_WR_SKU(skuTable, FtrEncodeVP9Vdenc, codecInfo->vp9Vdenc);
107
108 /* HEVC Main8/10bit-422/444 Decoding. Currently it is enabled. */
109 MEDIA_WR_SKU(skuTable, FtrIntelHEVCVLD42210bitDecoding, 1);
110 MEDIA_WR_SKU(skuTable, FtrIntelHEVCVLD4448bitDecoding, 1);
111 MEDIA_WR_SKU(skuTable, FtrIntelHEVCVLD44410bitDecoding, 1);
112
113 /* SFC Histogram Streamout. */
114 MEDIA_WR_SKU(skuTable, FtrSFCHistogramStreamOut, 1);
115
116 /* Subset buffer for realtile decoding. */
117 MEDIA_WR_SKU(skuTable, FtrIntelHEVCVLDDecodingSubsetBuffer, 1);
118
119 /* HEVC Main8/10bit-420/422/444 Scc Decoding. Currently it is enabled. */
120 MEDIA_WR_SKU(skuTable, FtrIntelHEVCVLDMain8bit420SCC, 1);
121 MEDIA_WR_SKU(skuTable, FtrIntelHEVCVLDMain10bit420SCC, 1);
122 MEDIA_WR_SKU(skuTable, FtrIntelHEVCVLDMain8bit444SCC, 1);
123 MEDIA_WR_SKU(skuTable, FtrIntelHEVCVLDMain10bit444SCC, 1);
124
125 /* HEVC VDENC Main8/10 422/444 Encoding. */
126 MEDIA_WR_SKU(skuTable, FtrEncodeHEVCVdencMain444, codecInfo->hevcVdenc);
127 MEDIA_WR_SKU(skuTable, FtrEncodeHEVCVdencMain10, codecInfo->hevcVdenc);
128 MEDIA_WR_SKU(skuTable, FtrEncodeHEVCVdencMain10bit422, codecInfo->hevcVdenc);
129 MEDIA_WR_SKU(skuTable, FtrEncodeHEVCVdencMain10bit444, codecInfo->hevcVdenc);
130
131 /* HEVC 12bit Decoding. Currently it is enabled */
132 MEDIA_WR_SKU(skuTable, FtrIntelHEVCVLDMain12bit420Decoding, 1);
133 MEDIA_WR_SKU(skuTable, FtrIntelHEVCVLDMain12bit422Decoding, 1);
134 MEDIA_WR_SKU(skuTable, FtrIntelHEVCVLDMain12bit444Decoding, 1);
135
136 /* VP9 8 bit 444 */
137 MEDIA_WR_SKU(skuTable, FtrIntelVP9VLDProfile1Decoding8bit444, 1);
138 /* VP9 10 Bit 444*/
139 MEDIA_WR_SKU(skuTable, FtrIntelVP9VLDProfile3Decoding10bit444, 1);
140 /* VP9 12 bit 420/444 */
141 MEDIA_WR_SKU(skuTable, FtrIntelVP9VLDProfile2Decoding12bit420, 1);
142 MEDIA_WR_SKU(skuTable, FtrIntelVP9VLDProfile3Decoding12bit444, 1);
143
144 /* VP9 VDENC 8Bit 444 */
145 MEDIA_WR_SKU(skuTable, FtrEncodeVP9Vdenc8bit444, codecInfo->vp9Vdenc);
146 /* VP9 VDENC 10Bit 420/444 */
147 MEDIA_WR_SKU(skuTable, FtrEncodeVP9Vdenc10bit420, codecInfo->vp9Vdenc);
148 MEDIA_WR_SKU(skuTable, FtrEncodeVP9Vdenc10bit444, codecInfo->vp9Vdenc);
149
150 }
151
152 MEDIA_WR_SKU(skuTable, FtrEnableMediaKernels, drvInfo->hasHuc);
153
154 if (devInfo->eGTType == GTTYPE_GT1)
155 {
156 MEDIA_WR_SKU(skuTable, FtrGT1, 1);
157 }
158 else if (devInfo->eGTType == GTTYPE_GT1_5)
159 {
160 MEDIA_WR_SKU(skuTable, FtrGT1_5, 1);
161 }
162 else if (devInfo->eGTType == GTTYPE_GT2)
163 {
164 MEDIA_WR_SKU(skuTable, FtrGT2, 1);
165 }
166 else if (devInfo->eGTType == GTTYPE_GT3)
167 {
168 MEDIA_WR_SKU(skuTable, FtrGT3, 1);
169 }
170 else if (devInfo->eGTType == GTTYPE_GT4)
171 {
172 MEDIA_WR_SKU(skuTable, FtrGT4, 1);
173 }
174 else
175 {
176 /* GT1 is by default */
177 MEDIA_WR_SKU(skuTable, FtrGT1, 1);
178 }
179
180 MEDIA_WR_SKU(skuTable, FtrVERing, drvInfo->hasVebox);
181 MEDIA_WR_SKU(skuTable, FtrPPGTT, drvInfo->hasPpgtt);
182 MEDIA_WR_SKU(skuTable, FtrEDram, devInfo->hasERAM);
183
184 /* Virtual VDBOX ring is used on Gen12 */
185 MEDIA_WR_SKU(skuTable, FtrVcs2, 0);
186
187 MEDIA_WR_SKU(skuTable, FtrSingleVeboxSlice, 1);
188 if (devInfo->SubSliceCount >= GEN12_VEBOX2_SUBSLICES)
189 {
190 MEDIA_WR_SKU(skuTable, FtrSingleVeboxSlice, 0);
191 }
192
193 MEDIA_WR_SKU(skuTable, FtrSFCPipe, 1);
194 MEDIA_WR_SKU(skuTable, FtrHCP2SFCPipe, 1);
195 MEDIA_WR_SKU(skuTable, FtrSSEUPowerGating, 1);
196 MEDIA_WR_SKU(skuTable, FtrSSEUPowerGatingControlByUMD, 1);
197
198 MEDIA_WR_SKU(skuTable, FtrPerCtxtPreemptionGranularityControl, 1);
199
200 /* It is disabled by default. It can be enabled based on HW */
201 MEDIA_WR_SKU(skuTable, FtrMemoryCompression, 0);
202 MEDIA_WR_SKU(skuTable, FtrHcpDecMemoryCompression, 0);
203 MEDIA_WR_SKU(skuTable, Ftr10bitDecMemoryCompression, 0);
204
205 MEDIA_WR_SKU(skuTable, FtrCCSNode, 1);
206
207 MEDIA_WR_SKU(skuTable, FtrVpP010Output, 1);
208 MEDIA_WR_SKU(skuTable, FtrVp10BitSupport, 1);
209 MEDIA_WR_SKU(skuTable, FtrVp16BitSupport, 1);
210
211 MEDIA_WR_SKU(skuTable, FtrContextBasedScheduling, 1);
212 MEDIA_WR_SKU(skuTable, FtrSfcScalability, 1);
213 // Enable context based scheduling when vebox scalabilitiy enable due to KMD didn't support GUC submission yet
214 MOS_USER_FEATURE_VALUE_DATA userFeatureData;
215 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
216 MOS_UserFeature_ReadValue_ID(
217 nullptr,
218 __MEDIA_USER_FEATURE_VALUE_ENABLE_VEBOX_SCALABILITY_MODE_ID,
219 &userFeatureData);
220 if (userFeatureData.i32Data)
221 {
222 MEDIA_WR_SKU(skuTable, FtrContextBasedScheduling, 1);
223 }
224
225 MEDIA_WR_SKU(skuTable, FtrTileY, 1);
226
227 bool enableCodecMMC = false;
228 bool enableVPMMC = false;
229 bool disableMMC = false;
230 MEDIA_WR_SKU(skuTable, FtrE2ECompression, 1);
231 // Disable MMC for all components if set reg key
232 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
233 MOS_UserFeature_ReadValue_ID(
234 nullptr,
235 __MEDIA_USER_FEATURE_VALUE_DISABLE_MMC_ID,
236 &userFeatureData);
237 if (userFeatureData.bData)
238 {
239 disableMMC = true;
240 }
241
242 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
243 MOS_UserFeature_ReadValue_ID(
244 nullptr,
245 __VPHAL_ENABLE_MMC_ID,
246 &userFeatureData);
247 if (userFeatureData.bData)
248 {
249 enableVPMMC = true;
250 }
251
252 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
253 MOS_UserFeature_ReadValue_ID(
254 nullptr,
255 __MEDIA_USER_FEATURE_VALUE_CODEC_MMC_ENABLE_ID,
256 &userFeatureData);
257 if (userFeatureData.bData)
258 {
259 enableCodecMMC = true;
260 }
261
262 if (disableMMC)
263 {
264 MEDIA_WR_SKU(skuTable, FtrE2ECompression, 0);
265 }else
266 {
267 if(!enableCodecMMC && !enableVPMMC)
268 {
269 MEDIA_WR_SKU(skuTable, FtrE2ECompression, 0);
270 }
271 }
272
273 MEDIA_WR_SKU(skuTable, FtrLinearCCS, 1);
274
275 MEDIA_WR_SKU(skuTable, FtrUseSwSwizzling, 1);
276
277 return true;
278 }
279
InitTglMediaWa(struct GfxDeviceInfo * devInfo,MediaWaTable * waTable,struct LinuxDriverInfo * drvInfo)280 static bool InitTglMediaWa(struct GfxDeviceInfo *devInfo,
281 MediaWaTable *waTable,
282 struct LinuxDriverInfo *drvInfo)
283 {
284 if ((devInfo == nullptr) || (waTable == nullptr) || (drvInfo == nullptr))
285 {
286 DEVINFO_ERROR("null ptr is passed\n");
287 return false;
288 }
289
290 MEDIA_WR_WA(waTable, WaForceGlobalGTT, !drvInfo->hasPpgtt);
291 MEDIA_WR_WA(waTable, WaMidBatchPreemption, 0);
292 MEDIA_WR_WA(waTable, WaArbitraryNumMbsInSlice, 1);
293
294 MEDIA_WR_WA(waTable, WaSuperSliceHeaderPacking, 1);
295
296 MEDIA_WR_WA(waTable, WaSFC270DegreeRotation, 0);
297
298 MEDIA_WR_WA(waTable, WaEnableYV12BugFixInHalfSliceChicken7, 1);
299
300 MOS_USER_FEATURE_VALUE_DATA userFeatureData;
301 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
302 MOS_UserFeature_ReadValue_ID(
303 nullptr,
304 __MEDIA_USER_FEATURE_VALUE_AUX_TABLE_16K_GRANULAR_ID,
305 &userFeatureData);
306
307 MEDIA_WR_WA(waTable, WaDummyReference, 1);
308
309 MEDIA_WR_WA(waTable, Wa16KInputHeightNV12Planar420, 1);
310
311 /*software wa to disable calculate the UV offset by gmmlib
312 CPU blt call will add/remove padding on the platform*/
313 MEDIA_WR_WA(waTable, WaDisableGmmLibOffsetInDeriveImage, 1);
314
315 return true;
316 }
317
318 static struct LinuxDeviceInit tgllpDeviceInit =
319 {
320 .productFamily = IGFX_TIGERLAKE_LP,
321 .InitMediaFeature = InitTglMediaSku,
322 .InitMediaWa = InitTglMediaWa,
323 };
324
325 static bool tgllpDeviceRegister = DeviceInfoFactory<LinuxDeviceInit>::
326 RegisterDevice(IGFX_TIGERLAKE_LP, &tgllpDeviceInit);
327