1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * gsc_hpdi.c
4 * Comedi driver the General Standards Corporation
5 * High Speed Parallel Digital Interface rs485 boards.
6 *
7 * Author: Frank Mori Hess <fmhess@users.sourceforge.net>
8 * Copyright (C) 2003 Coherent Imaging Systems
9 *
10 * COMEDI - Linux Control and Measurement Device Interface
11 * Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
12 */
13
14 /*
15 * Driver: gsc_hpdi
16 * Description: General Standards Corporation High
17 * Speed Parallel Digital Interface rs485 boards
18 * Author: Frank Mori Hess <fmhess@users.sourceforge.net>
19 * Status: only receive mode works, transmit not supported
20 * Updated: Thu, 01 Nov 2012 16:17:38 +0000
21 * Devices: [General Standards Corporation] PCI-HPDI32 (gsc_hpdi),
22 * PMC-HPDI32
23 *
24 * Configuration options:
25 * None.
26 *
27 * Manual configuration of supported devices is not supported; they are
28 * configured automatically.
29 *
30 * There are some additional hpdi models available from GSC for which
31 * support could be added to this driver.
32 */
33
34 #include <linux/module.h>
35 #include <linux/delay.h>
36 #include <linux/interrupt.h>
37
38 #include "../comedi_pci.h"
39
40 #include "plx9080.h"
41
42 /*
43 * PCI BAR2 Register map (dev->mmio)
44 */
45 #define FIRMWARE_REV_REG 0x00
46 #define FEATURES_REG_PRESENT_BIT BIT(15)
47 #define BOARD_CONTROL_REG 0x04
48 #define BOARD_RESET_BIT BIT(0)
49 #define TX_FIFO_RESET_BIT BIT(1)
50 #define RX_FIFO_RESET_BIT BIT(2)
51 #define TX_ENABLE_BIT BIT(4)
52 #define RX_ENABLE_BIT BIT(5)
53 #define DEMAND_DMA_DIRECTION_TX_BIT BIT(6) /* ch 0 only */
54 #define LINE_VALID_ON_STATUS_VALID_BIT BIT(7)
55 #define START_TX_BIT BIT(8)
56 #define CABLE_THROTTLE_ENABLE_BIT BIT(9)
57 #define TEST_MODE_ENABLE_BIT BIT(31)
58 #define BOARD_STATUS_REG 0x08
59 #define COMMAND_LINE_STATUS_MASK (0x7f << 0)
60 #define TX_IN_PROGRESS_BIT BIT(7)
61 #define TX_NOT_EMPTY_BIT BIT(8)
62 #define TX_NOT_ALMOST_EMPTY_BIT BIT(9)
63 #define TX_NOT_ALMOST_FULL_BIT BIT(10)
64 #define TX_NOT_FULL_BIT BIT(11)
65 #define RX_NOT_EMPTY_BIT BIT(12)
66 #define RX_NOT_ALMOST_EMPTY_BIT BIT(13)
67 #define RX_NOT_ALMOST_FULL_BIT BIT(14)
68 #define RX_NOT_FULL_BIT BIT(15)
69 #define BOARD_JUMPER0_INSTALLED_BIT BIT(16)
70 #define BOARD_JUMPER1_INSTALLED_BIT BIT(17)
71 #define TX_OVERRUN_BIT BIT(21)
72 #define RX_UNDERRUN_BIT BIT(22)
73 #define RX_OVERRUN_BIT BIT(23)
74 #define TX_PROG_ALMOST_REG 0x0c
75 #define RX_PROG_ALMOST_REG 0x10
76 #define ALMOST_EMPTY_BITS(x) (((x) & 0xffff) << 0)
77 #define ALMOST_FULL_BITS(x) (((x) & 0xff) << 16)
78 #define FEATURES_REG 0x14
79 #define FIFO_SIZE_PRESENT_BIT BIT(0)
80 #define FIFO_WORDS_PRESENT_BIT BIT(1)
81 #define LEVEL_EDGE_INTERRUPTS_PRESENT_BIT BIT(2)
82 #define GPIO_SUPPORTED_BIT BIT(3)
83 #define PLX_DMA_CH1_SUPPORTED_BIT BIT(4)
84 #define OVERRUN_UNDERRUN_SUPPORTED_BIT BIT(5)
85 #define FIFO_REG 0x18
86 #define TX_STATUS_COUNT_REG 0x1c
87 #define TX_LINE_VALID_COUNT_REG 0x20,
88 #define TX_LINE_INVALID_COUNT_REG 0x24
89 #define RX_STATUS_COUNT_REG 0x28
90 #define RX_LINE_COUNT_REG 0x2c
91 #define INTERRUPT_CONTROL_REG 0x30
92 #define FRAME_VALID_START_INTR BIT(0)
93 #define FRAME_VALID_END_INTR BIT(1)
94 #define TX_FIFO_EMPTY_INTR BIT(8)
95 #define TX_FIFO_ALMOST_EMPTY_INTR BIT(9)
96 #define TX_FIFO_ALMOST_FULL_INTR BIT(10)
97 #define TX_FIFO_FULL_INTR BIT(11)
98 #define RX_EMPTY_INTR BIT(12)
99 #define RX_ALMOST_EMPTY_INTR BIT(13)
100 #define RX_ALMOST_FULL_INTR BIT(14)
101 #define RX_FULL_INTR BIT(15)
102 #define INTERRUPT_STATUS_REG 0x34
103 #define TX_CLOCK_DIVIDER_REG 0x38
104 #define TX_FIFO_SIZE_REG 0x40
105 #define RX_FIFO_SIZE_REG 0x44
106 #define FIFO_SIZE_MASK (0xfffff << 0)
107 #define TX_FIFO_WORDS_REG 0x48
108 #define RX_FIFO_WORDS_REG 0x4c
109 #define INTERRUPT_EDGE_LEVEL_REG 0x50
110 #define INTERRUPT_POLARITY_REG 0x54
111
112 #define TIMER_BASE 50 /* 20MHz master clock */
113 #define DMA_BUFFER_SIZE 0x10000
114 #define NUM_DMA_BUFFERS 4
115 #define NUM_DMA_DESCRIPTORS 256
116
117 struct hpdi_private {
118 void __iomem *plx9080_mmio;
119 u32 *dio_buffer[NUM_DMA_BUFFERS]; /* dma buffers */
120 /* physical addresses of dma buffers */
121 dma_addr_t dio_buffer_phys_addr[NUM_DMA_BUFFERS];
122 /*
123 * array of dma descriptors read by plx9080, allocated to get proper
124 * alignment
125 */
126 struct plx_dma_desc *dma_desc;
127 /* physical address of dma descriptor array */
128 dma_addr_t dma_desc_phys_addr;
129 unsigned int num_dma_descriptors;
130 /* pointer to start of buffers indexed by descriptor */
131 u32 *desc_dio_buffer[NUM_DMA_DESCRIPTORS];
132 /* index of the dma descriptor that is currently being used */
133 unsigned int dma_desc_index;
134 unsigned int tx_fifo_size;
135 unsigned int rx_fifo_size;
136 unsigned long dio_count;
137 /* number of bytes at which to generate COMEDI_CB_BLOCK events */
138 unsigned int block_size;
139 };
140
gsc_hpdi_drain_dma(struct comedi_device * dev,unsigned int channel)141 static void gsc_hpdi_drain_dma(struct comedi_device *dev, unsigned int channel)
142 {
143 struct hpdi_private *devpriv = dev->private;
144 struct comedi_subdevice *s = dev->read_subdev;
145 struct comedi_cmd *cmd = &s->async->cmd;
146 unsigned int idx;
147 unsigned int start;
148 unsigned int desc;
149 unsigned int size;
150 unsigned int next;
151
152 next = readl(devpriv->plx9080_mmio + PLX_REG_DMAPADR(channel));
153
154 idx = devpriv->dma_desc_index;
155 start = le32_to_cpu(devpriv->dma_desc[idx].pci_start_addr);
156 /* loop until we have read all the full buffers */
157 for (desc = 0; (next < start || next >= start + devpriv->block_size) &&
158 desc < devpriv->num_dma_descriptors; desc++) {
159 /* transfer data from dma buffer to comedi buffer */
160 size = devpriv->block_size / sizeof(u32);
161 if (cmd->stop_src == TRIG_COUNT) {
162 if (size > devpriv->dio_count)
163 size = devpriv->dio_count;
164 devpriv->dio_count -= size;
165 }
166 comedi_buf_write_samples(s, devpriv->desc_dio_buffer[idx],
167 size);
168 idx++;
169 idx %= devpriv->num_dma_descriptors;
170 start = le32_to_cpu(devpriv->dma_desc[idx].pci_start_addr);
171
172 devpriv->dma_desc_index = idx;
173 }
174 /* XXX check for buffer overrun somehow */
175 }
176
gsc_hpdi_interrupt(int irq,void * d)177 static irqreturn_t gsc_hpdi_interrupt(int irq, void *d)
178 {
179 struct comedi_device *dev = d;
180 struct hpdi_private *devpriv = dev->private;
181 struct comedi_subdevice *s = dev->read_subdev;
182 struct comedi_async *async = s->async;
183 u32 hpdi_intr_status, hpdi_board_status;
184 u32 plx_status;
185 u32 plx_bits;
186 u8 dma0_status, dma1_status;
187 unsigned long flags;
188
189 if (!dev->attached)
190 return IRQ_NONE;
191
192 plx_status = readl(devpriv->plx9080_mmio + PLX_REG_INTCSR);
193 if ((plx_status &
194 (PLX_INTCSR_DMA0IA | PLX_INTCSR_DMA1IA | PLX_INTCSR_PLIA)) == 0)
195 return IRQ_NONE;
196
197 hpdi_intr_status = readl(dev->mmio + INTERRUPT_STATUS_REG);
198 hpdi_board_status = readl(dev->mmio + BOARD_STATUS_REG);
199
200 if (hpdi_intr_status)
201 writel(hpdi_intr_status, dev->mmio + INTERRUPT_STATUS_REG);
202
203 /* spin lock makes sure no one else changes plx dma control reg */
204 spin_lock_irqsave(&dev->spinlock, flags);
205 dma0_status = readb(devpriv->plx9080_mmio + PLX_REG_DMACSR0);
206 if (plx_status & PLX_INTCSR_DMA0IA) {
207 /* dma chan 0 interrupt */
208 writeb((dma0_status & PLX_DMACSR_ENABLE) | PLX_DMACSR_CLEARINTR,
209 devpriv->plx9080_mmio + PLX_REG_DMACSR0);
210
211 if (dma0_status & PLX_DMACSR_ENABLE)
212 gsc_hpdi_drain_dma(dev, 0);
213 }
214 spin_unlock_irqrestore(&dev->spinlock, flags);
215
216 /* spin lock makes sure no one else changes plx dma control reg */
217 spin_lock_irqsave(&dev->spinlock, flags);
218 dma1_status = readb(devpriv->plx9080_mmio + PLX_REG_DMACSR1);
219 if (plx_status & PLX_INTCSR_DMA1IA) {
220 /* XXX */ /* dma chan 1 interrupt */
221 writeb((dma1_status & PLX_DMACSR_ENABLE) | PLX_DMACSR_CLEARINTR,
222 devpriv->plx9080_mmio + PLX_REG_DMACSR1);
223 }
224 spin_unlock_irqrestore(&dev->spinlock, flags);
225
226 /* clear possible plx9080 interrupt sources */
227 if (plx_status & PLX_INTCSR_LDBIA) {
228 /* clear local doorbell interrupt */
229 plx_bits = readl(devpriv->plx9080_mmio + PLX_REG_L2PDBELL);
230 writel(plx_bits, devpriv->plx9080_mmio + PLX_REG_L2PDBELL);
231 }
232
233 if (hpdi_board_status & RX_OVERRUN_BIT) {
234 dev_err(dev->class_dev, "rx fifo overrun\n");
235 async->events |= COMEDI_CB_ERROR;
236 }
237
238 if (hpdi_board_status & RX_UNDERRUN_BIT) {
239 dev_err(dev->class_dev, "rx fifo underrun\n");
240 async->events |= COMEDI_CB_ERROR;
241 }
242
243 if (devpriv->dio_count == 0)
244 async->events |= COMEDI_CB_EOA;
245
246 comedi_handle_events(dev, s);
247
248 return IRQ_HANDLED;
249 }
250
gsc_hpdi_abort_dma(struct comedi_device * dev,unsigned int channel)251 static void gsc_hpdi_abort_dma(struct comedi_device *dev, unsigned int channel)
252 {
253 struct hpdi_private *devpriv = dev->private;
254 unsigned long flags;
255
256 /* spinlock for plx dma control/status reg */
257 spin_lock_irqsave(&dev->spinlock, flags);
258
259 plx9080_abort_dma(devpriv->plx9080_mmio, channel);
260
261 spin_unlock_irqrestore(&dev->spinlock, flags);
262 }
263
gsc_hpdi_cancel(struct comedi_device * dev,struct comedi_subdevice * s)264 static int gsc_hpdi_cancel(struct comedi_device *dev,
265 struct comedi_subdevice *s)
266 {
267 writel(0, dev->mmio + BOARD_CONTROL_REG);
268 writel(0, dev->mmio + INTERRUPT_CONTROL_REG);
269
270 gsc_hpdi_abort_dma(dev, 0);
271
272 return 0;
273 }
274
gsc_hpdi_cmd(struct comedi_device * dev,struct comedi_subdevice * s)275 static int gsc_hpdi_cmd(struct comedi_device *dev,
276 struct comedi_subdevice *s)
277 {
278 struct hpdi_private *devpriv = dev->private;
279 struct comedi_async *async = s->async;
280 struct comedi_cmd *cmd = &async->cmd;
281 unsigned long flags;
282 u32 bits;
283
284 if (s->io_bits)
285 return -EINVAL;
286
287 writel(RX_FIFO_RESET_BIT, dev->mmio + BOARD_CONTROL_REG);
288
289 gsc_hpdi_abort_dma(dev, 0);
290
291 devpriv->dma_desc_index = 0;
292
293 /*
294 * These register are supposedly unused during chained dma,
295 * but I have found that left over values from last operation
296 * occasionally cause problems with transfer of first dma
297 * block. Initializing them to zero seems to fix the problem.
298 */
299 writel(0, devpriv->plx9080_mmio + PLX_REG_DMASIZ0);
300 writel(0, devpriv->plx9080_mmio + PLX_REG_DMAPADR0);
301 writel(0, devpriv->plx9080_mmio + PLX_REG_DMALADR0);
302
303 /* give location of first dma descriptor */
304 bits = devpriv->dma_desc_phys_addr | PLX_DMADPR_DESCPCI |
305 PLX_DMADPR_TCINTR | PLX_DMADPR_XFERL2P;
306 writel(bits, devpriv->plx9080_mmio + PLX_REG_DMADPR0);
307
308 /* enable dma transfer */
309 spin_lock_irqsave(&dev->spinlock, flags);
310 writeb(PLX_DMACSR_ENABLE | PLX_DMACSR_START | PLX_DMACSR_CLEARINTR,
311 devpriv->plx9080_mmio + PLX_REG_DMACSR0);
312 spin_unlock_irqrestore(&dev->spinlock, flags);
313
314 if (cmd->stop_src == TRIG_COUNT)
315 devpriv->dio_count = cmd->stop_arg;
316 else
317 devpriv->dio_count = 1;
318
319 /* clear over/under run status flags */
320 writel(RX_UNDERRUN_BIT | RX_OVERRUN_BIT, dev->mmio + BOARD_STATUS_REG);
321
322 /* enable interrupts */
323 writel(RX_FULL_INTR, dev->mmio + INTERRUPT_CONTROL_REG);
324
325 writel(RX_ENABLE_BIT, dev->mmio + BOARD_CONTROL_REG);
326
327 return 0;
328 }
329
gsc_hpdi_check_chanlist(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_cmd * cmd)330 static int gsc_hpdi_check_chanlist(struct comedi_device *dev,
331 struct comedi_subdevice *s,
332 struct comedi_cmd *cmd)
333 {
334 int i;
335
336 for (i = 0; i < cmd->chanlist_len; i++) {
337 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
338
339 if (chan != i) {
340 dev_dbg(dev->class_dev,
341 "chanlist must be ch 0 to 31 in order\n");
342 return -EINVAL;
343 }
344 }
345
346 return 0;
347 }
348
gsc_hpdi_cmd_test(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_cmd * cmd)349 static int gsc_hpdi_cmd_test(struct comedi_device *dev,
350 struct comedi_subdevice *s,
351 struct comedi_cmd *cmd)
352 {
353 int err = 0;
354
355 if (s->io_bits)
356 return -EINVAL;
357
358 /* Step 1 : check if triggers are trivially valid */
359
360 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_NOW);
361 err |= comedi_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
362 err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
363 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
364 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
365
366 if (err)
367 return 1;
368
369 /* Step 2a : make sure trigger sources are unique */
370
371 err |= comedi_check_trigger_is_unique(cmd->stop_src);
372
373 /* Step 2b : and mutually compatible */
374
375 if (err)
376 return 2;
377
378 /* Step 3: check if arguments are trivially valid */
379
380 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
381
382 if (!cmd->chanlist_len || !cmd->chanlist) {
383 cmd->chanlist_len = 32;
384 err |= -EINVAL;
385 }
386 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
387 cmd->chanlist_len);
388
389 if (cmd->stop_src == TRIG_COUNT)
390 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
391 else /* TRIG_NONE */
392 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
393
394 if (err)
395 return 3;
396
397 /* Step 4: fix up any arguments */
398
399 /* Step 5: check channel list if it exists */
400
401 if (cmd->chanlist && cmd->chanlist_len > 0)
402 err |= gsc_hpdi_check_chanlist(dev, s, cmd);
403
404 if (err)
405 return 5;
406
407 return 0;
408 }
409
410 /* setup dma descriptors so a link completes every 'len' bytes */
gsc_hpdi_setup_dma_descriptors(struct comedi_device * dev,unsigned int len)411 static int gsc_hpdi_setup_dma_descriptors(struct comedi_device *dev,
412 unsigned int len)
413 {
414 struct hpdi_private *devpriv = dev->private;
415 dma_addr_t phys_addr = devpriv->dma_desc_phys_addr;
416 u32 next_bits = PLX_DMADPR_DESCPCI | PLX_DMADPR_TCINTR |
417 PLX_DMADPR_XFERL2P;
418 unsigned int offset = 0;
419 unsigned int idx = 0;
420 unsigned int i;
421
422 if (len > DMA_BUFFER_SIZE)
423 len = DMA_BUFFER_SIZE;
424 len -= len % sizeof(u32);
425 if (len == 0)
426 return -EINVAL;
427
428 for (i = 0; i < NUM_DMA_DESCRIPTORS && idx < NUM_DMA_BUFFERS; i++) {
429 devpriv->dma_desc[i].pci_start_addr =
430 cpu_to_le32(devpriv->dio_buffer_phys_addr[idx] + offset);
431 devpriv->dma_desc[i].local_start_addr = cpu_to_le32(FIFO_REG);
432 devpriv->dma_desc[i].transfer_size = cpu_to_le32(len);
433 devpriv->dma_desc[i].next = cpu_to_le32((phys_addr +
434 (i + 1) * sizeof(devpriv->dma_desc[0])) | next_bits);
435
436 devpriv->desc_dio_buffer[i] = devpriv->dio_buffer[idx] +
437 (offset / sizeof(u32));
438
439 offset += len;
440 if (len + offset > DMA_BUFFER_SIZE) {
441 offset = 0;
442 idx++;
443 }
444 }
445 devpriv->num_dma_descriptors = i;
446 /* fix last descriptor to point back to first */
447 devpriv->dma_desc[i - 1].next = cpu_to_le32(phys_addr | next_bits);
448
449 devpriv->block_size = len;
450
451 return len;
452 }
453
gsc_hpdi_dio_insn_config(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)454 static int gsc_hpdi_dio_insn_config(struct comedi_device *dev,
455 struct comedi_subdevice *s,
456 struct comedi_insn *insn,
457 unsigned int *data)
458 {
459 int ret;
460
461 switch (data[0]) {
462 case INSN_CONFIG_BLOCK_SIZE:
463 ret = gsc_hpdi_setup_dma_descriptors(dev, data[1]);
464 if (ret)
465 return ret;
466
467 data[1] = ret;
468 break;
469 default:
470 ret = comedi_dio_insn_config(dev, s, insn, data, 0xffffffff);
471 if (ret)
472 return ret;
473 break;
474 }
475
476 return insn->n;
477 }
478
gsc_hpdi_free_dma(struct comedi_device * dev)479 static void gsc_hpdi_free_dma(struct comedi_device *dev)
480 {
481 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
482 struct hpdi_private *devpriv = dev->private;
483 int i;
484
485 if (!devpriv)
486 return;
487
488 /* free pci dma buffers */
489 for (i = 0; i < NUM_DMA_BUFFERS; i++) {
490 if (devpriv->dio_buffer[i])
491 dma_free_coherent(&pcidev->dev,
492 DMA_BUFFER_SIZE,
493 devpriv->dio_buffer[i],
494 devpriv->dio_buffer_phys_addr[i]);
495 }
496 /* free dma descriptors */
497 if (devpriv->dma_desc)
498 dma_free_coherent(&pcidev->dev,
499 sizeof(struct plx_dma_desc) *
500 NUM_DMA_DESCRIPTORS,
501 devpriv->dma_desc,
502 devpriv->dma_desc_phys_addr);
503 }
504
gsc_hpdi_init(struct comedi_device * dev)505 static int gsc_hpdi_init(struct comedi_device *dev)
506 {
507 struct hpdi_private *devpriv = dev->private;
508 u32 plx_intcsr_bits;
509
510 /* wait 10usec after reset before accessing fifos */
511 writel(BOARD_RESET_BIT, dev->mmio + BOARD_CONTROL_REG);
512 usleep_range(10, 1000);
513
514 writel(ALMOST_EMPTY_BITS(32) | ALMOST_FULL_BITS(32),
515 dev->mmio + RX_PROG_ALMOST_REG);
516 writel(ALMOST_EMPTY_BITS(32) | ALMOST_FULL_BITS(32),
517 dev->mmio + TX_PROG_ALMOST_REG);
518
519 devpriv->tx_fifo_size = readl(dev->mmio + TX_FIFO_SIZE_REG) &
520 FIFO_SIZE_MASK;
521 devpriv->rx_fifo_size = readl(dev->mmio + RX_FIFO_SIZE_REG) &
522 FIFO_SIZE_MASK;
523
524 writel(0, dev->mmio + INTERRUPT_CONTROL_REG);
525
526 /* enable interrupts */
527 plx_intcsr_bits =
528 PLX_INTCSR_LSEABORTEN | PLX_INTCSR_LSEPARITYEN | PLX_INTCSR_PIEN |
529 PLX_INTCSR_PLIEN | PLX_INTCSR_PABORTIEN | PLX_INTCSR_LIOEN |
530 PLX_INTCSR_DMA0IEN;
531 writel(plx_intcsr_bits, devpriv->plx9080_mmio + PLX_REG_INTCSR);
532
533 return 0;
534 }
535
gsc_hpdi_init_plx9080(struct comedi_device * dev)536 static void gsc_hpdi_init_plx9080(struct comedi_device *dev)
537 {
538 struct hpdi_private *devpriv = dev->private;
539 u32 bits;
540 void __iomem *plx_iobase = devpriv->plx9080_mmio;
541
542 #ifdef __BIG_ENDIAN
543 bits = PLX_BIGEND_DMA0 | PLX_BIGEND_DMA1;
544 #else
545 bits = 0;
546 #endif
547 writel(bits, devpriv->plx9080_mmio + PLX_REG_BIGEND);
548
549 writel(0, devpriv->plx9080_mmio + PLX_REG_INTCSR);
550
551 gsc_hpdi_abort_dma(dev, 0);
552 gsc_hpdi_abort_dma(dev, 1);
553
554 /* configure dma0 mode */
555 bits = 0;
556 /* enable ready input */
557 bits |= PLX_DMAMODE_READYIEN;
558 /* enable dma chaining */
559 bits |= PLX_DMAMODE_CHAINEN;
560 /*
561 * enable interrupt on dma done
562 * (probably don't need this, since chain never finishes)
563 */
564 bits |= PLX_DMAMODE_DONEIEN;
565 /*
566 * don't increment local address during transfers
567 * (we are transferring from a fixed fifo register)
568 */
569 bits |= PLX_DMAMODE_LACONST;
570 /* route dma interrupt to pci bus */
571 bits |= PLX_DMAMODE_INTRPCI;
572 /* enable demand mode */
573 bits |= PLX_DMAMODE_DEMAND;
574 /* enable local burst mode */
575 bits |= PLX_DMAMODE_BURSTEN;
576 bits |= PLX_DMAMODE_WIDTH_32;
577 writel(bits, plx_iobase + PLX_REG_DMAMODE0);
578 }
579
gsc_hpdi_auto_attach(struct comedi_device * dev,unsigned long context_unused)580 static int gsc_hpdi_auto_attach(struct comedi_device *dev,
581 unsigned long context_unused)
582 {
583 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
584 struct hpdi_private *devpriv;
585 struct comedi_subdevice *s;
586 int i;
587 int retval;
588
589 dev->board_name = "pci-hpdi32";
590
591 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
592 if (!devpriv)
593 return -ENOMEM;
594
595 retval = comedi_pci_enable(dev);
596 if (retval)
597 return retval;
598 pci_set_master(pcidev);
599
600 devpriv->plx9080_mmio = pci_ioremap_bar(pcidev, 0);
601 dev->mmio = pci_ioremap_bar(pcidev, 2);
602 if (!devpriv->plx9080_mmio || !dev->mmio) {
603 dev_warn(dev->class_dev, "failed to remap io memory\n");
604 return -ENOMEM;
605 }
606
607 gsc_hpdi_init_plx9080(dev);
608
609 /* get irq */
610 if (request_irq(pcidev->irq, gsc_hpdi_interrupt, IRQF_SHARED,
611 dev->board_name, dev)) {
612 dev_warn(dev->class_dev,
613 "unable to allocate irq %u\n", pcidev->irq);
614 return -EINVAL;
615 }
616 dev->irq = pcidev->irq;
617
618 dev_dbg(dev->class_dev, " irq %u\n", dev->irq);
619
620 /* allocate pci dma buffers */
621 for (i = 0; i < NUM_DMA_BUFFERS; i++) {
622 devpriv->dio_buffer[i] =
623 dma_alloc_coherent(&pcidev->dev, DMA_BUFFER_SIZE,
624 &devpriv->dio_buffer_phys_addr[i],
625 GFP_KERNEL);
626 if (!devpriv->dio_buffer[i]) {
627 dev_warn(dev->class_dev,
628 "failed to allocate DMA buffer\n");
629 return -ENOMEM;
630 }
631 }
632 /* allocate dma descriptors */
633 devpriv->dma_desc = dma_alloc_coherent(&pcidev->dev,
634 sizeof(struct plx_dma_desc) *
635 NUM_DMA_DESCRIPTORS,
636 &devpriv->dma_desc_phys_addr,
637 GFP_KERNEL);
638 if (!devpriv->dma_desc) {
639 dev_warn(dev->class_dev,
640 "failed to allocate DMA descriptors\n");
641 return -ENOMEM;
642 }
643 if (devpriv->dma_desc_phys_addr & 0xf) {
644 dev_warn(dev->class_dev,
645 " dma descriptors not quad-word aligned (bug)\n");
646 return -EIO;
647 }
648
649 retval = gsc_hpdi_setup_dma_descriptors(dev, 0x1000);
650 if (retval < 0)
651 return retval;
652
653 retval = comedi_alloc_subdevices(dev, 1);
654 if (retval)
655 return retval;
656
657 /* Digital I/O subdevice */
658 s = &dev->subdevices[0];
659 dev->read_subdev = s;
660 s->type = COMEDI_SUBD_DIO;
661 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL |
662 SDF_CMD_READ;
663 s->n_chan = 32;
664 s->len_chanlist = 32;
665 s->maxdata = 1;
666 s->range_table = &range_digital;
667 s->insn_config = gsc_hpdi_dio_insn_config;
668 s->do_cmd = gsc_hpdi_cmd;
669 s->do_cmdtest = gsc_hpdi_cmd_test;
670 s->cancel = gsc_hpdi_cancel;
671
672 return gsc_hpdi_init(dev);
673 }
674
gsc_hpdi_detach(struct comedi_device * dev)675 static void gsc_hpdi_detach(struct comedi_device *dev)
676 {
677 struct hpdi_private *devpriv = dev->private;
678
679 if (dev->irq)
680 free_irq(dev->irq, dev);
681 if (devpriv) {
682 if (devpriv->plx9080_mmio) {
683 writel(0, devpriv->plx9080_mmio + PLX_REG_INTCSR);
684 iounmap(devpriv->plx9080_mmio);
685 }
686 if (dev->mmio)
687 iounmap(dev->mmio);
688 }
689 comedi_pci_disable(dev);
690 gsc_hpdi_free_dma(dev);
691 }
692
693 static struct comedi_driver gsc_hpdi_driver = {
694 .driver_name = "gsc_hpdi",
695 .module = THIS_MODULE,
696 .auto_attach = gsc_hpdi_auto_attach,
697 .detach = gsc_hpdi_detach,
698 };
699
gsc_hpdi_pci_probe(struct pci_dev * dev,const struct pci_device_id * id)700 static int gsc_hpdi_pci_probe(struct pci_dev *dev,
701 const struct pci_device_id *id)
702 {
703 return comedi_pci_auto_config(dev, &gsc_hpdi_driver, id->driver_data);
704 }
705
706 static const struct pci_device_id gsc_hpdi_pci_table[] = {
707 { PCI_DEVICE_SUB(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9080,
708 PCI_VENDOR_ID_PLX, 0x2400) },
709 { 0 }
710 };
711 MODULE_DEVICE_TABLE(pci, gsc_hpdi_pci_table);
712
713 static struct pci_driver gsc_hpdi_pci_driver = {
714 .name = "gsc_hpdi",
715 .id_table = gsc_hpdi_pci_table,
716 .probe = gsc_hpdi_pci_probe,
717 .remove = comedi_pci_auto_unconfig,
718 };
719 module_comedi_pci_driver(gsc_hpdi_driver, gsc_hpdi_pci_driver);
720
721 MODULE_AUTHOR("Comedi https://www.comedi.org");
722 MODULE_DESCRIPTION("Comedi driver for General Standards PCI-HPDI32/PMC-HPDI32");
723 MODULE_LICENSE("GPL");
724