1 /*
2 * Copyright 2020 Mauro Rossi <issor.oruam@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include <linux/slab.h>
27
28 #include "dce/dce_6_0_d.h"
29 #include "dce/dce_6_0_sh_mask.h"
30
31 #include "dm_services.h"
32
33 #include "link_encoder.h"
34 #include "stream_encoder.h"
35
36 #include "resource.h"
37 #include "include/irq_service_interface.h"
38 #include "irq/dce60/irq_service_dce60.h"
39 #include "dce110/dce110_timing_generator.h"
40 #include "dce110/dce110_resource.h"
41 #include "dce60/dce60_timing_generator.h"
42 #include "dce/dce_mem_input.h"
43 #include "dce/dce_link_encoder.h"
44 #include "dce/dce_stream_encoder.h"
45 #include "dce/dce_ipp.h"
46 #include "dce/dce_transform.h"
47 #include "dce/dce_opp.h"
48 #include "dce/dce_clock_source.h"
49 #include "dce/dce_audio.h"
50 #include "dce/dce_hwseq.h"
51 #include "dce60/dce60_hw_sequencer.h"
52 #include "dce100/dce100_resource.h"
53 #include "dce/dce_panel_cntl.h"
54
55 #include "reg_helper.h"
56
57 #include "dce/dce_dmcu.h"
58 #include "dce/dce_aux.h"
59 #include "dce/dce_abm.h"
60 #include "dce/dce_i2c.h"
61 /* TODO remove this include */
62
63 #include "dce60_resource.h"
64
65 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
66 #include "gmc/gmc_6_0_d.h"
67 #include "gmc/gmc_6_0_sh_mask.h"
68 #endif
69
70 #ifndef mmDP_DPHY_INTERNAL_CTRL
71 #define mmDP_DPHY_INTERNAL_CTRL 0x1CDE
72 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x1CDE
73 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x1FDE
74 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x42DE
75 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x45DE
76 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x48DE
77 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4BDE
78 #endif
79
80
81 #ifndef mmBIOS_SCRATCH_2
82 #define mmBIOS_SCRATCH_2 0x05CB
83 #define mmBIOS_SCRATCH_3 0x05CC
84 #define mmBIOS_SCRATCH_6 0x05CF
85 #endif
86
87 #ifndef mmDP_DPHY_FAST_TRAINING
88 #define mmDP_DPHY_FAST_TRAINING 0x1CCE
89 #define mmDP0_DP_DPHY_FAST_TRAINING 0x1CCE
90 #define mmDP1_DP_DPHY_FAST_TRAINING 0x1FCE
91 #define mmDP2_DP_DPHY_FAST_TRAINING 0x42CE
92 #define mmDP3_DP_DPHY_FAST_TRAINING 0x45CE
93 #define mmDP4_DP_DPHY_FAST_TRAINING 0x48CE
94 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4BCE
95 #endif
96
97
98 #ifndef mmHPD_DC_HPD_CONTROL
99 #define mmHPD_DC_HPD_CONTROL 0x189A
100 #define mmHPD0_DC_HPD_CONTROL 0x189A
101 #define mmHPD1_DC_HPD_CONTROL 0x18A2
102 #define mmHPD2_DC_HPD_CONTROL 0x18AA
103 #define mmHPD3_DC_HPD_CONTROL 0x18B2
104 #define mmHPD4_DC_HPD_CONTROL 0x18BA
105 #define mmHPD5_DC_HPD_CONTROL 0x18C2
106 #endif
107
108 #define DCE11_DIG_FE_CNTL 0x4a00
109 #define DCE11_DIG_BE_CNTL 0x4a47
110 #define DCE11_DP_SEC 0x4ac3
111
112 static const struct dce110_timing_generator_offsets dce60_tg_offsets[] = {
113 {
114 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
115 .dcp = (mmGRPH_CONTROL - mmGRPH_CONTROL),
116 .dmif = (mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL3
117 - mmDPG_PIPE_ARBITRATION_CONTROL3),
118 },
119 {
120 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
121 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
122 .dmif = (mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL3
123 - mmDPG_PIPE_ARBITRATION_CONTROL3),
124 },
125 {
126 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
127 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
128 .dmif = (mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL3
129 - mmDPG_PIPE_ARBITRATION_CONTROL3),
130 },
131 {
132 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
133 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
134 .dmif = (mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL3
135 - mmDPG_PIPE_ARBITRATION_CONTROL3),
136 },
137 {
138 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
139 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
140 .dmif = (mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL3
141 - mmDPG_PIPE_ARBITRATION_CONTROL3),
142 },
143 {
144 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
145 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
146 .dmif = (mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL3
147 - mmDPG_PIPE_ARBITRATION_CONTROL3),
148 }
149 };
150
151 /* set register offset */
152 #define SR(reg_name)\
153 .reg_name = mm ## reg_name
154
155 /* set register offset with instance */
156 #define SRI(reg_name, block, id)\
157 .reg_name = mm ## block ## id ## _ ## reg_name
158
159 #define ipp_regs(id)\
160 [id] = {\
161 IPP_COMMON_REG_LIST_DCE_BASE(id)\
162 }
163
164 static const struct dce_ipp_registers ipp_regs[] = {
165 ipp_regs(0),
166 ipp_regs(1),
167 ipp_regs(2),
168 ipp_regs(3),
169 ipp_regs(4),
170 ipp_regs(5)
171 };
172
173 static const struct dce_ipp_shift ipp_shift = {
174 IPP_DCE60_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
175 };
176
177 static const struct dce_ipp_mask ipp_mask = {
178 IPP_DCE60_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
179 };
180
181 #define transform_regs(id)\
182 [id] = {\
183 XFM_COMMON_REG_LIST_DCE60(id)\
184 }
185
186 static const struct dce_transform_registers xfm_regs[] = {
187 transform_regs(0),
188 transform_regs(1),
189 transform_regs(2),
190 transform_regs(3),
191 transform_regs(4),
192 transform_regs(5)
193 };
194
195 static const struct dce_transform_shift xfm_shift = {
196 XFM_COMMON_MASK_SH_LIST_DCE60(__SHIFT)
197 };
198
199 static const struct dce_transform_mask xfm_mask = {
200 XFM_COMMON_MASK_SH_LIST_DCE60(_MASK)
201 };
202
203 #define aux_regs(id)\
204 [id] = {\
205 AUX_REG_LIST(id)\
206 }
207
208 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
209 aux_regs(0),
210 aux_regs(1),
211 aux_regs(2),
212 aux_regs(3),
213 aux_regs(4),
214 aux_regs(5)
215 };
216
217 #define hpd_regs(id)\
218 [id] = {\
219 HPD_REG_LIST(id)\
220 }
221
222 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
223 hpd_regs(0),
224 hpd_regs(1),
225 hpd_regs(2),
226 hpd_regs(3),
227 hpd_regs(4),
228 hpd_regs(5)
229 };
230
231 #define link_regs(id)\
232 [id] = {\
233 LE_DCE60_REG_LIST(id)\
234 }
235
236 static const struct dce110_link_enc_registers link_enc_regs[] = {
237 link_regs(0),
238 link_regs(1),
239 link_regs(2),
240 link_regs(3),
241 link_regs(4),
242 link_regs(5)
243 };
244
245 #define stream_enc_regs(id)\
246 [id] = {\
247 SE_COMMON_REG_LIST_DCE_BASE(id),\
248 .AFMT_CNTL = 0,\
249 }
250
251 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
252 stream_enc_regs(0),
253 stream_enc_regs(1),
254 stream_enc_regs(2),
255 stream_enc_regs(3),
256 stream_enc_regs(4),
257 stream_enc_regs(5)
258 };
259
260 static const struct dce_stream_encoder_shift se_shift = {
261 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT)
262 };
263
264 static const struct dce_stream_encoder_mask se_mask = {
265 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK)
266 };
267
268 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
269 { DCE_PANEL_CNTL_REG_LIST() }
270 };
271
272 static const struct dce_panel_cntl_shift panel_cntl_shift = {
273 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
274 };
275
276 static const struct dce_panel_cntl_mask panel_cntl_mask = {
277 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
278 };
279
280 #define opp_regs(id)\
281 [id] = {\
282 OPP_DCE_60_REG_LIST(id),\
283 }
284
285 static const struct dce_opp_registers opp_regs[] = {
286 opp_regs(0),
287 opp_regs(1),
288 opp_regs(2),
289 opp_regs(3),
290 opp_regs(4),
291 opp_regs(5)
292 };
293
294 static const struct dce_opp_shift opp_shift = {
295 OPP_COMMON_MASK_SH_LIST_DCE_60(__SHIFT)
296 };
297
298 static const struct dce_opp_mask opp_mask = {
299 OPP_COMMON_MASK_SH_LIST_DCE_60(_MASK)
300 };
301
302 static const struct dce110_aux_registers_shift aux_shift = {
303 DCE10_AUX_MASK_SH_LIST(__SHIFT)
304 };
305
306 static const struct dce110_aux_registers_mask aux_mask = {
307 DCE10_AUX_MASK_SH_LIST(_MASK)
308 };
309
310 #define aux_engine_regs(id)\
311 [id] = {\
312 AUX_COMMON_REG_LIST(id), \
313 .AUX_RESET_MASK = 0 \
314 }
315
316 static const struct dce110_aux_registers aux_engine_regs[] = {
317 aux_engine_regs(0),
318 aux_engine_regs(1),
319 aux_engine_regs(2),
320 aux_engine_regs(3),
321 aux_engine_regs(4),
322 aux_engine_regs(5)
323 };
324
325 #define audio_regs(id)\
326 [id] = {\
327 AUD_COMMON_REG_LIST(id)\
328 }
329
330 static const struct dce_audio_registers audio_regs[] = {
331 audio_regs(0),
332 audio_regs(1),
333 audio_regs(2),
334 audio_regs(3),
335 audio_regs(4),
336 audio_regs(5),
337 };
338
339 static const struct dce_audio_shift audio_shift = {
340 AUD_DCE60_MASK_SH_LIST(__SHIFT)
341 };
342
343 static const struct dce_audio_mask audio_mask = {
344 AUD_DCE60_MASK_SH_LIST(_MASK)
345 };
346
347 #define clk_src_regs(id)\
348 [id] = {\
349 CS_COMMON_REG_LIST_DCE_80(id),\
350 }
351
352
353 static const struct dce110_clk_src_regs clk_src_regs[] = {
354 clk_src_regs(0),
355 clk_src_regs(1),
356 clk_src_regs(2)
357 };
358
359 static const struct dce110_clk_src_shift cs_shift = {
360 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
361 };
362
363 static const struct dce110_clk_src_mask cs_mask = {
364 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
365 };
366
367 static const struct bios_registers bios_regs = {
368 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3,
369 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
370 };
371
372 static const struct resource_caps res_cap = {
373 .num_timing_generator = 6,
374 .num_audio = 6,
375 .num_stream_encoder = 6,
376 .num_pll = 2,
377 .num_ddc = 6,
378 };
379
380 static const struct resource_caps res_cap_61 = {
381 .num_timing_generator = 4,
382 .num_audio = 6,
383 .num_stream_encoder = 6,
384 .num_pll = 3,
385 .num_ddc = 6,
386 };
387
388 static const struct resource_caps res_cap_64 = {
389 .num_timing_generator = 2,
390 .num_audio = 2,
391 .num_stream_encoder = 2,
392 .num_pll = 2,
393 .num_ddc = 2,
394 };
395
396 static const struct dc_plane_cap plane_cap = {
397 .type = DC_PLANE_TYPE_DCE_RGB,
398
399 .pixel_format_support = {
400 .argb8888 = true,
401 .nv12 = false,
402 .fp16 = false
403 },
404
405 .max_upscale_factor = {
406 .argb8888 = 16000,
407 .nv12 = 1,
408 .fp16 = 1
409 },
410
411 .max_downscale_factor = {
412 .argb8888 = 250,
413 .nv12 = 1,
414 .fp16 = 1
415 }
416 };
417
418 static const struct dce_dmcu_registers dmcu_regs = {
419 DMCU_DCE60_REG_LIST()
420 };
421
422 static const struct dce_dmcu_shift dmcu_shift = {
423 DMCU_MASK_SH_LIST_DCE60(__SHIFT)
424 };
425
426 static const struct dce_dmcu_mask dmcu_mask = {
427 DMCU_MASK_SH_LIST_DCE60(_MASK)
428 };
429 static const struct dce_abm_registers abm_regs = {
430 ABM_DCE110_COMMON_REG_LIST()
431 };
432
433 static const struct dce_abm_shift abm_shift = {
434 ABM_MASK_SH_LIST_DCE110(__SHIFT)
435 };
436
437 static const struct dce_abm_mask abm_mask = {
438 ABM_MASK_SH_LIST_DCE110(_MASK)
439 };
440
441 #define CTX ctx
442 #define REG(reg) mm ## reg
443
444 #ifndef mmCC_DC_HDMI_STRAPS
445 #define mmCC_DC_HDMI_STRAPS 0x1918
446 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
447 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
448 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
449 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
450 #endif
451
map_transmitter_id_to_phy_instance(enum transmitter transmitter)452 static int map_transmitter_id_to_phy_instance(
453 enum transmitter transmitter)
454 {
455 switch (transmitter) {
456 case TRANSMITTER_UNIPHY_A:
457 return 0;
458 case TRANSMITTER_UNIPHY_B:
459 return 1;
460 case TRANSMITTER_UNIPHY_C:
461 return 2;
462 case TRANSMITTER_UNIPHY_D:
463 return 3;
464 case TRANSMITTER_UNIPHY_E:
465 return 4;
466 case TRANSMITTER_UNIPHY_F:
467 return 5;
468 case TRANSMITTER_UNIPHY_G:
469 return 6;
470 default:
471 ASSERT(0);
472 return 0;
473 }
474 }
475
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)476 static void read_dce_straps(
477 struct dc_context *ctx,
478 struct resource_straps *straps)
479 {
480 REG_GET_2(CC_DC_HDMI_STRAPS,
481 HDMI_DISABLE, &straps->hdmi_disable,
482 AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
483
484 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
485 }
486
create_audio(struct dc_context * ctx,unsigned int inst)487 static struct audio *create_audio(
488 struct dc_context *ctx, unsigned int inst)
489 {
490 return dce60_audio_create(ctx, inst,
491 &audio_regs[inst], &audio_shift, &audio_mask);
492 }
493
dce60_timing_generator_create(struct dc_context * ctx,uint32_t instance,const struct dce110_timing_generator_offsets * offsets)494 static struct timing_generator *dce60_timing_generator_create(
495 struct dc_context *ctx,
496 uint32_t instance,
497 const struct dce110_timing_generator_offsets *offsets)
498 {
499 struct dce110_timing_generator *tg110 =
500 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
501
502 if (!tg110)
503 return NULL;
504
505 dce60_timing_generator_construct(tg110, ctx, instance, offsets);
506 return &tg110->base;
507 }
508
dce60_opp_create(struct dc_context * ctx,uint32_t inst)509 static struct output_pixel_processor *dce60_opp_create(
510 struct dc_context *ctx,
511 uint32_t inst)
512 {
513 struct dce110_opp *opp =
514 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
515
516 if (!opp)
517 return NULL;
518
519 dce60_opp_construct(opp,
520 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
521 return &opp->base;
522 }
523
dce60_aux_engine_create(struct dc_context * ctx,uint32_t inst)524 static struct dce_aux *dce60_aux_engine_create(
525 struct dc_context *ctx,
526 uint32_t inst)
527 {
528 struct aux_engine_dce110 *aux_engine =
529 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
530
531 if (!aux_engine)
532 return NULL;
533
534 dce110_aux_engine_construct(aux_engine, ctx, inst,
535 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
536 &aux_engine_regs[inst],
537 &aux_mask,
538 &aux_shift,
539 ctx->dc->caps.extended_aux_timeout_support);
540
541 return &aux_engine->base;
542 }
543 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
544
545 static const struct dce_i2c_registers i2c_hw_regs[] = {
546 i2c_inst_regs(1),
547 i2c_inst_regs(2),
548 i2c_inst_regs(3),
549 i2c_inst_regs(4),
550 i2c_inst_regs(5),
551 i2c_inst_regs(6),
552 };
553
554 static const struct dce_i2c_shift i2c_shifts = {
555 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
556 };
557
558 static const struct dce_i2c_mask i2c_masks = {
559 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
560 };
561
dce60_i2c_hw_create(struct dc_context * ctx,uint32_t inst)562 static struct dce_i2c_hw *dce60_i2c_hw_create(
563 struct dc_context *ctx,
564 uint32_t inst)
565 {
566 struct dce_i2c_hw *dce_i2c_hw =
567 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
568
569 if (!dce_i2c_hw)
570 return NULL;
571
572 dce_i2c_hw_construct(dce_i2c_hw, ctx, inst,
573 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
574
575 return dce_i2c_hw;
576 }
577
dce60_i2c_sw_create(struct dc_context * ctx)578 static struct dce_i2c_sw *dce60_i2c_sw_create(
579 struct dc_context *ctx)
580 {
581 struct dce_i2c_sw *dce_i2c_sw =
582 kzalloc(sizeof(struct dce_i2c_sw), GFP_KERNEL);
583
584 if (!dce_i2c_sw)
585 return NULL;
586
587 dce_i2c_sw_construct(dce_i2c_sw, ctx);
588
589 return dce_i2c_sw;
590 }
dce60_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)591 static struct stream_encoder *dce60_stream_encoder_create(
592 enum engine_id eng_id,
593 struct dc_context *ctx)
594 {
595 struct dce110_stream_encoder *enc110 =
596 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
597
598 if (!enc110)
599 return NULL;
600
601 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
602 &stream_enc_regs[eng_id],
603 &se_shift, &se_mask);
604 return &enc110->base;
605 }
606
607 #define SRII(reg_name, block, id)\
608 .reg_name[id] = mm ## block ## id ## _ ## reg_name
609
610 static const struct dce_hwseq_registers hwseq_reg = {
611 HWSEQ_DCE6_REG_LIST()
612 };
613
614 static const struct dce_hwseq_shift hwseq_shift = {
615 HWSEQ_DCE6_MASK_SH_LIST(__SHIFT)
616 };
617
618 static const struct dce_hwseq_mask hwseq_mask = {
619 HWSEQ_DCE6_MASK_SH_LIST(_MASK)
620 };
621
dce60_hwseq_create(struct dc_context * ctx)622 static struct dce_hwseq *dce60_hwseq_create(
623 struct dc_context *ctx)
624 {
625 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
626
627 if (hws) {
628 hws->ctx = ctx;
629 hws->regs = &hwseq_reg;
630 hws->shifts = &hwseq_shift;
631 hws->masks = &hwseq_mask;
632 }
633 return hws;
634 }
635
636 static const struct resource_create_funcs res_create_funcs = {
637 .read_dce_straps = read_dce_straps,
638 .create_audio = create_audio,
639 .create_stream_encoder = dce60_stream_encoder_create,
640 .create_hwseq = dce60_hwseq_create,
641 };
642
643 #define mi_inst_regs(id) { \
644 MI_DCE6_REG_LIST(id), \
645 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
646 }
647 static const struct dce_mem_input_registers mi_regs[] = {
648 mi_inst_regs(0),
649 mi_inst_regs(1),
650 mi_inst_regs(2),
651 mi_inst_regs(3),
652 mi_inst_regs(4),
653 mi_inst_regs(5),
654 };
655
656 static const struct dce_mem_input_shift mi_shifts = {
657 MI_DCE6_MASK_SH_LIST(__SHIFT),
658 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
659 };
660
661 static const struct dce_mem_input_mask mi_masks = {
662 MI_DCE6_MASK_SH_LIST(_MASK),
663 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
664 };
665
dce60_mem_input_create(struct dc_context * ctx,uint32_t inst)666 static struct mem_input *dce60_mem_input_create(
667 struct dc_context *ctx,
668 uint32_t inst)
669 {
670 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
671 GFP_KERNEL);
672
673 if (!dce_mi) {
674 BREAK_TO_DEBUGGER();
675 return NULL;
676 }
677
678 dce60_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
679 dce_mi->wa.single_head_rdreq_dmif_limit = 2;
680 return &dce_mi->base;
681 }
682
dce60_transform_destroy(struct transform ** xfm)683 static void dce60_transform_destroy(struct transform **xfm)
684 {
685 kfree(TO_DCE_TRANSFORM(*xfm));
686 *xfm = NULL;
687 }
688
dce60_transform_create(struct dc_context * ctx,uint32_t inst)689 static struct transform *dce60_transform_create(
690 struct dc_context *ctx,
691 uint32_t inst)
692 {
693 struct dce_transform *transform =
694 kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
695
696 if (!transform)
697 return NULL;
698
699 dce60_transform_construct(transform, ctx, inst,
700 &xfm_regs[inst], &xfm_shift, &xfm_mask);
701 transform->prescaler_on = false;
702 return &transform->base;
703 }
704
705 static const struct encoder_feature_support link_enc_feature = {
706 .max_hdmi_deep_color = COLOR_DEPTH_121212,
707 .max_hdmi_pixel_clock = 297000,
708 .flags.bits.IS_HBR2_CAPABLE = true,
709 .flags.bits.IS_TPS3_CAPABLE = true
710 };
711
dce60_link_encoder_create(const struct encoder_init_data * enc_init_data)712 static struct link_encoder *dce60_link_encoder_create(
713 const struct encoder_init_data *enc_init_data)
714 {
715 struct dce110_link_encoder *enc110 =
716 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
717 int link_regs_id;
718
719 if (!enc110)
720 return NULL;
721
722 link_regs_id =
723 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
724
725 dce60_link_encoder_construct(enc110,
726 enc_init_data,
727 &link_enc_feature,
728 &link_enc_regs[link_regs_id],
729 &link_enc_aux_regs[enc_init_data->channel - 1],
730 &link_enc_hpd_regs[enc_init_data->hpd_source]);
731 return &enc110->base;
732 }
733
dce60_panel_cntl_create(const struct panel_cntl_init_data * init_data)734 static struct panel_cntl *dce60_panel_cntl_create(const struct panel_cntl_init_data *init_data)
735 {
736 struct dce_panel_cntl *panel_cntl =
737 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
738
739 if (!panel_cntl)
740 return NULL;
741
742 dce_panel_cntl_construct(panel_cntl,
743 init_data,
744 &panel_cntl_regs[init_data->inst],
745 &panel_cntl_shift,
746 &panel_cntl_mask);
747
748 return &panel_cntl->base;
749 }
750
dce60_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)751 static struct clock_source *dce60_clock_source_create(
752 struct dc_context *ctx,
753 struct dc_bios *bios,
754 enum clock_source_id id,
755 const struct dce110_clk_src_regs *regs,
756 bool dp_clk_src)
757 {
758 struct dce110_clk_src *clk_src =
759 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
760
761 if (!clk_src)
762 return NULL;
763
764 if (dce110_clk_src_construct(clk_src, ctx, bios, id,
765 regs, &cs_shift, &cs_mask)) {
766 clk_src->base.dp_clk_src = dp_clk_src;
767 return &clk_src->base;
768 }
769
770 kfree(clk_src);
771 BREAK_TO_DEBUGGER();
772 return NULL;
773 }
774
dce60_clock_source_destroy(struct clock_source ** clk_src)775 static void dce60_clock_source_destroy(struct clock_source **clk_src)
776 {
777 kfree(TO_DCE110_CLK_SRC(*clk_src));
778 *clk_src = NULL;
779 }
780
dce60_ipp_create(struct dc_context * ctx,uint32_t inst)781 static struct input_pixel_processor *dce60_ipp_create(
782 struct dc_context *ctx, uint32_t inst)
783 {
784 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
785
786 if (!ipp) {
787 BREAK_TO_DEBUGGER();
788 return NULL;
789 }
790
791 dce60_ipp_construct(ipp, ctx, inst,
792 &ipp_regs[inst], &ipp_shift, &ipp_mask);
793 return &ipp->base;
794 }
795
dce60_resource_destruct(struct dce110_resource_pool * pool)796 static void dce60_resource_destruct(struct dce110_resource_pool *pool)
797 {
798 unsigned int i;
799
800 for (i = 0; i < pool->base.pipe_count; i++) {
801 if (pool->base.opps[i] != NULL)
802 dce110_opp_destroy(&pool->base.opps[i]);
803
804 if (pool->base.transforms[i] != NULL)
805 dce60_transform_destroy(&pool->base.transforms[i]);
806
807 if (pool->base.ipps[i] != NULL)
808 dce_ipp_destroy(&pool->base.ipps[i]);
809
810 if (pool->base.mis[i] != NULL) {
811 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
812 pool->base.mis[i] = NULL;
813 }
814
815 if (pool->base.timing_generators[i] != NULL) {
816 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
817 pool->base.timing_generators[i] = NULL;
818 }
819 }
820
821 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
822 if (pool->base.engines[i] != NULL)
823 dce110_engine_destroy(&pool->base.engines[i]);
824 if (pool->base.hw_i2cs[i] != NULL) {
825 kfree(pool->base.hw_i2cs[i]);
826 pool->base.hw_i2cs[i] = NULL;
827 }
828 if (pool->base.sw_i2cs[i] != NULL) {
829 kfree(pool->base.sw_i2cs[i]);
830 pool->base.sw_i2cs[i] = NULL;
831 }
832 }
833
834 for (i = 0; i < pool->base.stream_enc_count; i++) {
835 if (pool->base.stream_enc[i] != NULL)
836 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
837 }
838
839 for (i = 0; i < pool->base.clk_src_count; i++) {
840 if (pool->base.clock_sources[i] != NULL) {
841 dce60_clock_source_destroy(&pool->base.clock_sources[i]);
842 }
843 }
844
845 if (pool->base.abm != NULL)
846 dce_abm_destroy(&pool->base.abm);
847
848 if (pool->base.dmcu != NULL)
849 dce_dmcu_destroy(&pool->base.dmcu);
850
851 if (pool->base.dp_clock_source != NULL)
852 dce60_clock_source_destroy(&pool->base.dp_clock_source);
853
854 for (i = 0; i < pool->base.audio_count; i++) {
855 if (pool->base.audios[i] != NULL) {
856 dce_aud_destroy(&pool->base.audios[i]);
857 }
858 }
859
860 if (pool->base.irqs != NULL) {
861 dal_irq_service_destroy(&pool->base.irqs);
862 }
863 }
864
dce60_validate_bandwidth(struct dc * dc,struct dc_state * context,bool fast_validate)865 static bool dce60_validate_bandwidth(
866 struct dc *dc,
867 struct dc_state *context,
868 bool fast_validate)
869 {
870 int i;
871 bool at_least_one_pipe = false;
872
873 for (i = 0; i < dc->res_pool->pipe_count; i++) {
874 if (context->res_ctx.pipe_ctx[i].stream)
875 at_least_one_pipe = true;
876 }
877
878 if (at_least_one_pipe) {
879 /* TODO implement when needed but for now hardcode max value*/
880 context->bw_ctx.bw.dce.dispclk_khz = 681000;
881 context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ;
882 } else {
883 context->bw_ctx.bw.dce.dispclk_khz = 0;
884 context->bw_ctx.bw.dce.yclk_khz = 0;
885 }
886
887 return true;
888 }
889
dce60_validate_surface_sets(struct dc_state * context)890 static bool dce60_validate_surface_sets(
891 struct dc_state *context)
892 {
893 int i;
894
895 for (i = 0; i < context->stream_count; i++) {
896 if (context->stream_status[i].plane_count == 0)
897 continue;
898
899 if (context->stream_status[i].plane_count > 1)
900 return false;
901
902 if (context->stream_status[i].plane_states[0]->format
903 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
904 return false;
905 }
906
907 return true;
908 }
909
dce60_validate_global(struct dc * dc,struct dc_state * context)910 static enum dc_status dce60_validate_global(
911 struct dc *dc,
912 struct dc_state *context)
913 {
914 if (!dce60_validate_surface_sets(context))
915 return DC_FAIL_SURFACE_VALIDATE;
916
917 return DC_OK;
918 }
919
dce60_destroy_resource_pool(struct resource_pool ** pool)920 static void dce60_destroy_resource_pool(struct resource_pool **pool)
921 {
922 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
923
924 dce60_resource_destruct(dce110_pool);
925 kfree(dce110_pool);
926 *pool = NULL;
927 }
928
929 static const struct resource_funcs dce60_res_pool_funcs = {
930 .destroy = dce60_destroy_resource_pool,
931 .link_enc_create = dce60_link_encoder_create,
932 .panel_cntl_create = dce60_panel_cntl_create,
933 .validate_bandwidth = dce60_validate_bandwidth,
934 .validate_plane = dce100_validate_plane,
935 .add_stream_to_ctx = dce100_add_stream_to_ctx,
936 .validate_global = dce60_validate_global,
937 .find_first_free_match_stream_enc_for_link = dce100_find_first_free_match_stream_enc_for_link
938 };
939
dce60_construct(uint8_t num_virtual_links,struct dc * dc,struct dce110_resource_pool * pool)940 static bool dce60_construct(
941 uint8_t num_virtual_links,
942 struct dc *dc,
943 struct dce110_resource_pool *pool)
944 {
945 unsigned int i;
946 struct dc_context *ctx = dc->ctx;
947 struct dc_bios *bp;
948
949 ctx->dc_bios->regs = &bios_regs;
950
951 pool->base.res_cap = &res_cap;
952 pool->base.funcs = &dce60_res_pool_funcs;
953
954
955 /*************************************************
956 * Resource + asic cap harcoding *
957 *************************************************/
958 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
959 pool->base.pipe_count = res_cap.num_timing_generator;
960 pool->base.timing_generator_count = res_cap.num_timing_generator;
961 dc->caps.max_downscale_ratio = 200;
962 dc->caps.i2c_speed_in_khz = 40;
963 dc->caps.max_cursor_size = 64;
964 dc->caps.dual_link_dvi = true;
965 dc->caps.extended_aux_timeout_support = false;
966
967 /*************************************************
968 * Create resources *
969 *************************************************/
970
971 bp = ctx->dc_bios;
972
973 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
974 pool->base.dp_clock_source =
975 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
976
977 pool->base.clock_sources[0] =
978 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
979 pool->base.clock_sources[1] =
980 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
981 pool->base.clk_src_count = 2;
982
983 } else {
984 pool->base.dp_clock_source =
985 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
986
987 pool->base.clock_sources[0] =
988 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
989 pool->base.clk_src_count = 1;
990 }
991
992 if (pool->base.dp_clock_source == NULL) {
993 dm_error("DC: failed to create dp clock source!\n");
994 BREAK_TO_DEBUGGER();
995 goto res_create_fail;
996 }
997
998 for (i = 0; i < pool->base.clk_src_count; i++) {
999 if (pool->base.clock_sources[i] == NULL) {
1000 dm_error("DC: failed to create clock sources!\n");
1001 BREAK_TO_DEBUGGER();
1002 goto res_create_fail;
1003 }
1004 }
1005
1006 pool->base.dmcu = dce_dmcu_create(ctx,
1007 &dmcu_regs,
1008 &dmcu_shift,
1009 &dmcu_mask);
1010 if (pool->base.dmcu == NULL) {
1011 dm_error("DC: failed to create dmcu!\n");
1012 BREAK_TO_DEBUGGER();
1013 goto res_create_fail;
1014 }
1015
1016 pool->base.abm = dce_abm_create(ctx,
1017 &abm_regs,
1018 &abm_shift,
1019 &abm_mask);
1020 if (pool->base.abm == NULL) {
1021 dm_error("DC: failed to create abm!\n");
1022 BREAK_TO_DEBUGGER();
1023 goto res_create_fail;
1024 }
1025
1026 {
1027 struct irq_service_init_data init_data;
1028 init_data.ctx = dc->ctx;
1029 pool->base.irqs = dal_irq_service_dce60_create(&init_data);
1030 if (!pool->base.irqs)
1031 goto res_create_fail;
1032 }
1033
1034 for (i = 0; i < pool->base.pipe_count; i++) {
1035 pool->base.timing_generators[i] = dce60_timing_generator_create(
1036 ctx, i, &dce60_tg_offsets[i]);
1037 if (pool->base.timing_generators[i] == NULL) {
1038 BREAK_TO_DEBUGGER();
1039 dm_error("DC: failed to create tg!\n");
1040 goto res_create_fail;
1041 }
1042
1043 pool->base.mis[i] = dce60_mem_input_create(ctx, i);
1044 if (pool->base.mis[i] == NULL) {
1045 BREAK_TO_DEBUGGER();
1046 dm_error("DC: failed to create memory input!\n");
1047 goto res_create_fail;
1048 }
1049
1050 pool->base.ipps[i] = dce60_ipp_create(ctx, i);
1051 if (pool->base.ipps[i] == NULL) {
1052 BREAK_TO_DEBUGGER();
1053 dm_error("DC: failed to create input pixel processor!\n");
1054 goto res_create_fail;
1055 }
1056
1057 pool->base.transforms[i] = dce60_transform_create(ctx, i);
1058 if (pool->base.transforms[i] == NULL) {
1059 BREAK_TO_DEBUGGER();
1060 dm_error("DC: failed to create transform!\n");
1061 goto res_create_fail;
1062 }
1063
1064 pool->base.opps[i] = dce60_opp_create(ctx, i);
1065 if (pool->base.opps[i] == NULL) {
1066 BREAK_TO_DEBUGGER();
1067 dm_error("DC: failed to create output pixel processor!\n");
1068 goto res_create_fail;
1069 }
1070 }
1071
1072 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1073 pool->base.engines[i] = dce60_aux_engine_create(ctx, i);
1074 if (pool->base.engines[i] == NULL) {
1075 BREAK_TO_DEBUGGER();
1076 dm_error(
1077 "DC:failed to create aux engine!!\n");
1078 goto res_create_fail;
1079 }
1080 pool->base.hw_i2cs[i] = dce60_i2c_hw_create(ctx, i);
1081 if (pool->base.hw_i2cs[i] == NULL) {
1082 BREAK_TO_DEBUGGER();
1083 dm_error(
1084 "DC:failed to create i2c engine!!\n");
1085 goto res_create_fail;
1086 }
1087 pool->base.sw_i2cs[i] = dce60_i2c_sw_create(ctx);
1088 if (pool->base.sw_i2cs[i] == NULL) {
1089 BREAK_TO_DEBUGGER();
1090 dm_error(
1091 "DC:failed to create sw i2c!!\n");
1092 goto res_create_fail;
1093 }
1094 }
1095
1096 dc->caps.max_planes = pool->base.pipe_count;
1097
1098 for (i = 0; i < dc->caps.max_planes; ++i)
1099 dc->caps.planes[i] = plane_cap;
1100
1101 dc->caps.disable_dp_clk_share = true;
1102
1103 if (!resource_construct(num_virtual_links, dc, &pool->base,
1104 &res_create_funcs))
1105 goto res_create_fail;
1106
1107 /* Create hardware sequencer */
1108 dce60_hw_sequencer_construct(dc);
1109
1110 return true;
1111
1112 res_create_fail:
1113 dce60_resource_destruct(pool);
1114 return false;
1115 }
1116
dce60_create_resource_pool(uint8_t num_virtual_links,struct dc * dc)1117 struct resource_pool *dce60_create_resource_pool(
1118 uint8_t num_virtual_links,
1119 struct dc *dc)
1120 {
1121 struct dce110_resource_pool *pool =
1122 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1123
1124 if (!pool)
1125 return NULL;
1126
1127 if (dce60_construct(num_virtual_links, dc, pool))
1128 return &pool->base;
1129
1130 BREAK_TO_DEBUGGER();
1131 return NULL;
1132 }
1133
dce61_construct(uint8_t num_virtual_links,struct dc * dc,struct dce110_resource_pool * pool)1134 static bool dce61_construct(
1135 uint8_t num_virtual_links,
1136 struct dc *dc,
1137 struct dce110_resource_pool *pool)
1138 {
1139 unsigned int i;
1140 struct dc_context *ctx = dc->ctx;
1141 struct dc_bios *bp;
1142
1143 ctx->dc_bios->regs = &bios_regs;
1144
1145 pool->base.res_cap = &res_cap_61;
1146 pool->base.funcs = &dce60_res_pool_funcs;
1147
1148
1149 /*************************************************
1150 * Resource + asic cap harcoding *
1151 *************************************************/
1152 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1153 pool->base.pipe_count = res_cap_61.num_timing_generator;
1154 pool->base.timing_generator_count = res_cap_61.num_timing_generator;
1155 dc->caps.max_downscale_ratio = 200;
1156 dc->caps.i2c_speed_in_khz = 40;
1157 dc->caps.max_cursor_size = 64;
1158 dc->caps.is_apu = true;
1159
1160 /*************************************************
1161 * Create resources *
1162 *************************************************/
1163
1164 bp = ctx->dc_bios;
1165
1166 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
1167 pool->base.dp_clock_source =
1168 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
1169
1170 pool->base.clock_sources[0] =
1171 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
1172 pool->base.clock_sources[1] =
1173 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1174 pool->base.clock_sources[2] =
1175 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1176 pool->base.clk_src_count = 3;
1177
1178 } else {
1179 pool->base.dp_clock_source =
1180 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
1181
1182 pool->base.clock_sources[0] =
1183 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1184 pool->base.clock_sources[1] =
1185 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1186 pool->base.clk_src_count = 2;
1187 }
1188
1189 if (pool->base.dp_clock_source == NULL) {
1190 dm_error("DC: failed to create dp clock source!\n");
1191 BREAK_TO_DEBUGGER();
1192 goto res_create_fail;
1193 }
1194
1195 for (i = 0; i < pool->base.clk_src_count; i++) {
1196 if (pool->base.clock_sources[i] == NULL) {
1197 dm_error("DC: failed to create clock sources!\n");
1198 BREAK_TO_DEBUGGER();
1199 goto res_create_fail;
1200 }
1201 }
1202
1203 pool->base.dmcu = dce_dmcu_create(ctx,
1204 &dmcu_regs,
1205 &dmcu_shift,
1206 &dmcu_mask);
1207 if (pool->base.dmcu == NULL) {
1208 dm_error("DC: failed to create dmcu!\n");
1209 BREAK_TO_DEBUGGER();
1210 goto res_create_fail;
1211 }
1212
1213 pool->base.abm = dce_abm_create(ctx,
1214 &abm_regs,
1215 &abm_shift,
1216 &abm_mask);
1217 if (pool->base.abm == NULL) {
1218 dm_error("DC: failed to create abm!\n");
1219 BREAK_TO_DEBUGGER();
1220 goto res_create_fail;
1221 }
1222
1223 {
1224 struct irq_service_init_data init_data;
1225 init_data.ctx = dc->ctx;
1226 pool->base.irqs = dal_irq_service_dce60_create(&init_data);
1227 if (!pool->base.irqs)
1228 goto res_create_fail;
1229 }
1230
1231 for (i = 0; i < pool->base.pipe_count; i++) {
1232 pool->base.timing_generators[i] = dce60_timing_generator_create(
1233 ctx, i, &dce60_tg_offsets[i]);
1234 if (pool->base.timing_generators[i] == NULL) {
1235 BREAK_TO_DEBUGGER();
1236 dm_error("DC: failed to create tg!\n");
1237 goto res_create_fail;
1238 }
1239
1240 pool->base.mis[i] = dce60_mem_input_create(ctx, i);
1241 if (pool->base.mis[i] == NULL) {
1242 BREAK_TO_DEBUGGER();
1243 dm_error("DC: failed to create memory input!\n");
1244 goto res_create_fail;
1245 }
1246
1247 pool->base.ipps[i] = dce60_ipp_create(ctx, i);
1248 if (pool->base.ipps[i] == NULL) {
1249 BREAK_TO_DEBUGGER();
1250 dm_error("DC: failed to create input pixel processor!\n");
1251 goto res_create_fail;
1252 }
1253
1254 pool->base.transforms[i] = dce60_transform_create(ctx, i);
1255 if (pool->base.transforms[i] == NULL) {
1256 BREAK_TO_DEBUGGER();
1257 dm_error("DC: failed to create transform!\n");
1258 goto res_create_fail;
1259 }
1260
1261 pool->base.opps[i] = dce60_opp_create(ctx, i);
1262 if (pool->base.opps[i] == NULL) {
1263 BREAK_TO_DEBUGGER();
1264 dm_error("DC: failed to create output pixel processor!\n");
1265 goto res_create_fail;
1266 }
1267 }
1268
1269 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1270 pool->base.engines[i] = dce60_aux_engine_create(ctx, i);
1271 if (pool->base.engines[i] == NULL) {
1272 BREAK_TO_DEBUGGER();
1273 dm_error(
1274 "DC:failed to create aux engine!!\n");
1275 goto res_create_fail;
1276 }
1277 pool->base.hw_i2cs[i] = dce60_i2c_hw_create(ctx, i);
1278 if (pool->base.hw_i2cs[i] == NULL) {
1279 BREAK_TO_DEBUGGER();
1280 dm_error(
1281 "DC:failed to create i2c engine!!\n");
1282 goto res_create_fail;
1283 }
1284 pool->base.sw_i2cs[i] = dce60_i2c_sw_create(ctx);
1285 if (pool->base.sw_i2cs[i] == NULL) {
1286 BREAK_TO_DEBUGGER();
1287 dm_error(
1288 "DC:failed to create sw i2c!!\n");
1289 goto res_create_fail;
1290 }
1291 }
1292
1293 dc->caps.max_planes = pool->base.pipe_count;
1294
1295 for (i = 0; i < dc->caps.max_planes; ++i)
1296 dc->caps.planes[i] = plane_cap;
1297
1298 dc->caps.disable_dp_clk_share = true;
1299
1300 if (!resource_construct(num_virtual_links, dc, &pool->base,
1301 &res_create_funcs))
1302 goto res_create_fail;
1303
1304 /* Create hardware sequencer */
1305 dce60_hw_sequencer_construct(dc);
1306
1307 return true;
1308
1309 res_create_fail:
1310 dce60_resource_destruct(pool);
1311 return false;
1312 }
1313
dce61_create_resource_pool(uint8_t num_virtual_links,struct dc * dc)1314 struct resource_pool *dce61_create_resource_pool(
1315 uint8_t num_virtual_links,
1316 struct dc *dc)
1317 {
1318 struct dce110_resource_pool *pool =
1319 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1320
1321 if (!pool)
1322 return NULL;
1323
1324 if (dce61_construct(num_virtual_links, dc, pool))
1325 return &pool->base;
1326
1327 BREAK_TO_DEBUGGER();
1328 return NULL;
1329 }
1330
dce64_construct(uint8_t num_virtual_links,struct dc * dc,struct dce110_resource_pool * pool)1331 static bool dce64_construct(
1332 uint8_t num_virtual_links,
1333 struct dc *dc,
1334 struct dce110_resource_pool *pool)
1335 {
1336 unsigned int i;
1337 struct dc_context *ctx = dc->ctx;
1338 struct dc_bios *bp;
1339
1340 ctx->dc_bios->regs = &bios_regs;
1341
1342 pool->base.res_cap = &res_cap_64;
1343 pool->base.funcs = &dce60_res_pool_funcs;
1344
1345
1346 /*************************************************
1347 * Resource + asic cap harcoding *
1348 *************************************************/
1349 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1350 pool->base.pipe_count = res_cap_64.num_timing_generator;
1351 pool->base.timing_generator_count = res_cap_64.num_timing_generator;
1352 dc->caps.max_downscale_ratio = 200;
1353 dc->caps.i2c_speed_in_khz = 40;
1354 dc->caps.max_cursor_size = 64;
1355 dc->caps.is_apu = true;
1356
1357 /*************************************************
1358 * Create resources *
1359 *************************************************/
1360
1361 bp = ctx->dc_bios;
1362
1363 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
1364 pool->base.dp_clock_source =
1365 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
1366
1367 pool->base.clock_sources[0] =
1368 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], false);
1369 pool->base.clock_sources[1] =
1370 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
1371 pool->base.clk_src_count = 2;
1372
1373 } else {
1374 pool->base.dp_clock_source =
1375 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], true);
1376
1377 pool->base.clock_sources[0] =
1378 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
1379 pool->base.clk_src_count = 1;
1380 }
1381
1382 if (pool->base.dp_clock_source == NULL) {
1383 dm_error("DC: failed to create dp clock source!\n");
1384 BREAK_TO_DEBUGGER();
1385 goto res_create_fail;
1386 }
1387
1388 for (i = 0; i < pool->base.clk_src_count; i++) {
1389 if (pool->base.clock_sources[i] == NULL) {
1390 dm_error("DC: failed to create clock sources!\n");
1391 BREAK_TO_DEBUGGER();
1392 goto res_create_fail;
1393 }
1394 }
1395
1396 pool->base.dmcu = dce_dmcu_create(ctx,
1397 &dmcu_regs,
1398 &dmcu_shift,
1399 &dmcu_mask);
1400 if (pool->base.dmcu == NULL) {
1401 dm_error("DC: failed to create dmcu!\n");
1402 BREAK_TO_DEBUGGER();
1403 goto res_create_fail;
1404 }
1405
1406 pool->base.abm = dce_abm_create(ctx,
1407 &abm_regs,
1408 &abm_shift,
1409 &abm_mask);
1410 if (pool->base.abm == NULL) {
1411 dm_error("DC: failed to create abm!\n");
1412 BREAK_TO_DEBUGGER();
1413 goto res_create_fail;
1414 }
1415
1416 {
1417 struct irq_service_init_data init_data;
1418 init_data.ctx = dc->ctx;
1419 pool->base.irqs = dal_irq_service_dce60_create(&init_data);
1420 if (!pool->base.irqs)
1421 goto res_create_fail;
1422 }
1423
1424 for (i = 0; i < pool->base.pipe_count; i++) {
1425 pool->base.timing_generators[i] = dce60_timing_generator_create(
1426 ctx, i, &dce60_tg_offsets[i]);
1427 if (pool->base.timing_generators[i] == NULL) {
1428 BREAK_TO_DEBUGGER();
1429 dm_error("DC: failed to create tg!\n");
1430 goto res_create_fail;
1431 }
1432
1433 pool->base.mis[i] = dce60_mem_input_create(ctx, i);
1434 if (pool->base.mis[i] == NULL) {
1435 BREAK_TO_DEBUGGER();
1436 dm_error("DC: failed to create memory input!\n");
1437 goto res_create_fail;
1438 }
1439
1440 pool->base.ipps[i] = dce60_ipp_create(ctx, i);
1441 if (pool->base.ipps[i] == NULL) {
1442 BREAK_TO_DEBUGGER();
1443 dm_error("DC: failed to create input pixel processor!\n");
1444 goto res_create_fail;
1445 }
1446
1447 pool->base.transforms[i] = dce60_transform_create(ctx, i);
1448 if (pool->base.transforms[i] == NULL) {
1449 BREAK_TO_DEBUGGER();
1450 dm_error("DC: failed to create transform!\n");
1451 goto res_create_fail;
1452 }
1453
1454 pool->base.opps[i] = dce60_opp_create(ctx, i);
1455 if (pool->base.opps[i] == NULL) {
1456 BREAK_TO_DEBUGGER();
1457 dm_error("DC: failed to create output pixel processor!\n");
1458 goto res_create_fail;
1459 }
1460 }
1461
1462 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1463 pool->base.engines[i] = dce60_aux_engine_create(ctx, i);
1464 if (pool->base.engines[i] == NULL) {
1465 BREAK_TO_DEBUGGER();
1466 dm_error(
1467 "DC:failed to create aux engine!!\n");
1468 goto res_create_fail;
1469 }
1470 pool->base.hw_i2cs[i] = dce60_i2c_hw_create(ctx, i);
1471 if (pool->base.hw_i2cs[i] == NULL) {
1472 BREAK_TO_DEBUGGER();
1473 dm_error(
1474 "DC:failed to create i2c engine!!\n");
1475 goto res_create_fail;
1476 }
1477 pool->base.sw_i2cs[i] = dce60_i2c_sw_create(ctx);
1478 if (pool->base.sw_i2cs[i] == NULL) {
1479 BREAK_TO_DEBUGGER();
1480 dm_error(
1481 "DC:failed to create sw i2c!!\n");
1482 goto res_create_fail;
1483 }
1484 }
1485
1486 dc->caps.max_planes = pool->base.pipe_count;
1487
1488 for (i = 0; i < dc->caps.max_planes; ++i)
1489 dc->caps.planes[i] = plane_cap;
1490
1491 dc->caps.disable_dp_clk_share = true;
1492
1493 if (!resource_construct(num_virtual_links, dc, &pool->base,
1494 &res_create_funcs))
1495 goto res_create_fail;
1496
1497 /* Create hardware sequencer */
1498 dce60_hw_sequencer_construct(dc);
1499
1500 return true;
1501
1502 res_create_fail:
1503 dce60_resource_destruct(pool);
1504 return false;
1505 }
1506
dce64_create_resource_pool(uint8_t num_virtual_links,struct dc * dc)1507 struct resource_pool *dce64_create_resource_pool(
1508 uint8_t num_virtual_links,
1509 struct dc *dc)
1510 {
1511 struct dce110_resource_pool *pool =
1512 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1513
1514 if (!pool)
1515 return NULL;
1516
1517 if (dce64_construct(num_virtual_links, dc, pool))
1518 return &pool->base;
1519
1520 BREAK_TO_DEBUGGER();
1521 return NULL;
1522 }
1523