1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __SMU11_DRIVER_IF_SIENNA_CICHLID_H__ 25 #define __SMU11_DRIVER_IF_SIENNA_CICHLID_H__ 26 27 // *** IMPORTANT *** 28 // SMU TEAM: Always increment the interface version if 29 // any structure is changed in this file 30 #define SMU11_DRIVER_IF_VERSION 0x3B 31 32 #define PPTABLE_Sienna_Cichlid_SMU_VERSION 7 33 34 #define NUM_GFXCLK_DPM_LEVELS 16 35 #define NUM_SMNCLK_DPM_LEVELS 2 36 #define NUM_SOCCLK_DPM_LEVELS 8 37 #define NUM_MP0CLK_DPM_LEVELS 2 38 #define NUM_DCLK_DPM_LEVELS 8 39 #define NUM_VCLK_DPM_LEVELS 8 40 #define NUM_DCEFCLK_DPM_LEVELS 8 41 #define NUM_PHYCLK_DPM_LEVELS 8 42 #define NUM_DISPCLK_DPM_LEVELS 8 43 #define NUM_PIXCLK_DPM_LEVELS 8 44 #define NUM_DTBCLK_DPM_LEVELS 8 45 #define NUM_UCLK_DPM_LEVELS 4 46 #define NUM_MP1CLK_DPM_LEVELS 2 47 #define NUM_LINK_LEVELS 2 48 #define NUM_FCLK_DPM_LEVELS 8 49 #define NUM_XGMI_LEVELS 2 50 #define NUM_XGMI_PSTATE_LEVELS 4 51 #define NUM_OD_FAN_MAX_POINTS 6 52 53 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1) 54 #define MAX_SMNCLK_DPM_LEVEL (NUM_SMNCLK_DPM_LEVELS - 1) 55 #define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1) 56 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1) 57 #define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1) 58 #define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1) 59 #define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1) 60 #define MAX_DISPCLK_DPM_LEVEL (NUM_DISPCLK_DPM_LEVELS - 1) 61 #define MAX_PIXCLK_DPM_LEVEL (NUM_PIXCLK_DPM_LEVELS - 1) 62 #define MAX_PHYCLK_DPM_LEVEL (NUM_PHYCLK_DPM_LEVELS - 1) 63 #define MAX_DTBCLK_DPM_LEVEL (NUM_DTBCLK_DPM_LEVELS - 1) 64 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1) 65 #define MAX_MP1CLK_DPM_LEVEL (NUM_MP1CLK_DPM_LEVELS - 1) 66 #define MAX_LINK_LEVEL (NUM_LINK_LEVELS - 1) 67 #define MAX_FCLK_DPM_LEVEL (NUM_FCLK_DPM_LEVELS - 1) 68 69 //Gemini Modes 70 #define PPSMC_GeminiModeNone 0 //Single GPU board 71 #define PPSMC_GeminiModeMaster 1 //Master GPU on a Gemini board 72 #define PPSMC_GeminiModeSlave 2 //Slave GPU on a Gemini board 73 74 // Feature Control Defines 75 // DPM 76 #define FEATURE_DPM_PREFETCHER_BIT 0 77 #define FEATURE_DPM_GFXCLK_BIT 1 78 #define FEATURE_DPM_GFX_GPO_BIT 2 79 #define FEATURE_DPM_UCLK_BIT 3 80 #define FEATURE_DPM_FCLK_BIT 4 81 #define FEATURE_DPM_SOCCLK_BIT 5 82 #define FEATURE_DPM_MP0CLK_BIT 6 83 #define FEATURE_DPM_LINK_BIT 7 84 #define FEATURE_DPM_DCEFCLK_BIT 8 85 #define FEATURE_DPM_XGMI_BIT 9 86 #define FEATURE_MEM_VDDCI_SCALING_BIT 10 87 #define FEATURE_MEM_MVDD_SCALING_BIT 11 88 89 //Idle 90 #define FEATURE_DS_GFXCLK_BIT 12 91 #define FEATURE_DS_SOCCLK_BIT 13 92 #define FEATURE_DS_FCLK_BIT 14 93 #define FEATURE_DS_LCLK_BIT 15 94 #define FEATURE_DS_DCEFCLK_BIT 16 95 #define FEATURE_DS_UCLK_BIT 17 96 #define FEATURE_GFX_ULV_BIT 18 97 #define FEATURE_FW_DSTATE_BIT 19 98 #define FEATURE_GFXOFF_BIT 20 99 #define FEATURE_BACO_BIT 21 100 #define FEATURE_MM_DPM_PG_BIT 22 101 #define FEATURE_SPARE_23_BIT 23 102 //Throttler/Response 103 #define FEATURE_PPT_BIT 24 104 #define FEATURE_TDC_BIT 25 105 #define FEATURE_APCC_PLUS_BIT 26 106 #define FEATURE_GTHR_BIT 27 107 #define FEATURE_ACDC_BIT 28 108 #define FEATURE_VR0HOT_BIT 29 109 #define FEATURE_VR1HOT_BIT 30 110 #define FEATURE_FW_CTF_BIT 31 111 #define FEATURE_FAN_CONTROL_BIT 32 112 #define FEATURE_THERMAL_BIT 33 113 #define FEATURE_GFX_DCS_BIT 34 114 //VF 115 #define FEATURE_RM_BIT 35 116 #define FEATURE_LED_DISPLAY_BIT 36 117 //Other 118 #define FEATURE_GFX_SS_BIT 37 119 #define FEATURE_OUT_OF_BAND_MONITOR_BIT 38 120 #define FEATURE_TEMP_DEPENDENT_VMIN_BIT 39 121 122 #define FEATURE_MMHUB_PG_BIT 40 123 #define FEATURE_ATHUB_PG_BIT 41 124 #define FEATURE_APCC_DFLL_BIT 42 125 #define FEATURE_DF_SUPERV_BIT 43 126 #define FEATURE_RSMU_SMN_CG_BIT 44 127 #define FEATURE_DF_CSTATE_BIT 45 128 #define FEATURE_2_STEP_PSTATE_BIT 46 129 #define FEATURE_SMNCLK_DPM_BIT 47 130 #define FEATURE_PERLINK_GMIDOWN_BIT 48 131 #define FEATURE_GFX_EDC_BIT 49 132 #define FEATURE_SPARE_50_BIT 50 133 #define FEATURE_SPARE_51_BIT 51 134 #define FEATURE_SPARE_52_BIT 52 135 #define FEATURE_SPARE_53_BIT 53 136 #define FEATURE_SPARE_54_BIT 54 137 #define FEATURE_SPARE_55_BIT 55 138 #define FEATURE_SPARE_56_BIT 56 139 #define FEATURE_SPARE_57_BIT 57 140 #define FEATURE_SPARE_58_BIT 58 141 #define FEATURE_SPARE_59_BIT 59 142 #define FEATURE_SPARE_60_BIT 60 143 #define FEATURE_SPARE_61_BIT 61 144 #define FEATURE_SPARE_62_BIT 62 145 #define FEATURE_SPARE_63_BIT 63 146 #define NUM_FEATURES 64 147 148 //For use with feature control messages 149 typedef enum { 150 FEATURE_PWR_ALL, 151 FEATURE_PWR_S5, 152 FEATURE_PWR_BACO, 153 FEATURE_PWR_SOC, 154 FEATURE_PWR_GFX, 155 FEATURE_PWR_DOMAIN_COUNT, 156 } FEATURE_PWR_DOMAIN_e; 157 158 159 // Debug Overrides Bitmask 160 #define DPM_OVERRIDE_DISABLE_FCLK_PID 0x00000001 161 #define DPM_OVERRIDE_DISABLE_UCLK_PID 0x00000002 162 #define DPM_OVERRIDE_DISABLE_VOLT_LINK_VCN_FCLK 0x00000004 163 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_VCLK_FCLK 0x00000008 164 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_DCLK_FCLK 0x00000010 165 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_GFXCLK_SOCCLK 0x00000020 166 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_GFXCLK_UCLK 0x00000040 167 #define DPM_OVERRIDE_DISABLE_VOLT_LINK_DCE_FCLK 0x00000080 168 #define DPM_OVERRIDE_DISABLE_VOLT_LINK_MP0_SOCCLK 0x00000100 169 #define DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN 0x00000200 170 #define DPM_OVERRIDE_DISABLE_MEMORY_TEMPERATURE_READ 0x00000400 171 #define DPM_OVERRIDE_DISABLE_VOLT_LINK_VCN_DCEFCLK 0x00000800 172 #define DPM_OVERRIDE_DISABLE_FAST_FCLK_TIMER 0x00001000 173 #define DPM_OVERRIDE_DISABLE_VCN_PG 0x00002000 174 #define DPM_OVERRIDE_DISABLE_FMAX_VMAX 0x00004000 175 176 // VR Mapping Bit Defines 177 #define VR_MAPPING_VR_SELECT_MASK 0x01 178 #define VR_MAPPING_VR_SELECT_SHIFT 0x00 179 180 #define VR_MAPPING_PLANE_SELECT_MASK 0x02 181 #define VR_MAPPING_PLANE_SELECT_SHIFT 0x01 182 183 // PSI Bit Defines 184 #define PSI_SEL_VR0_PLANE0_PSI0 0x01 185 #define PSI_SEL_VR0_PLANE0_PSI1 0x02 186 #define PSI_SEL_VR0_PLANE1_PSI0 0x04 187 #define PSI_SEL_VR0_PLANE1_PSI1 0x08 188 #define PSI_SEL_VR1_PLANE0_PSI0 0x10 189 #define PSI_SEL_VR1_PLANE0_PSI1 0x20 190 #define PSI_SEL_VR1_PLANE1_PSI0 0x40 191 #define PSI_SEL_VR1_PLANE1_PSI1 0x80 192 193 // Throttler Control/Status Bits 194 #define THROTTLER_PADDING_BIT 0 195 #define THROTTLER_TEMP_EDGE_BIT 1 196 #define THROTTLER_TEMP_HOTSPOT_BIT 2 197 #define THROTTLER_TEMP_MEM_BIT 3 198 #define THROTTLER_TEMP_VR_GFX_BIT 4 199 #define THROTTLER_TEMP_VR_MEM0_BIT 5 200 #define THROTTLER_TEMP_VR_MEM1_BIT 6 201 #define THROTTLER_TEMP_VR_SOC_BIT 7 202 #define THROTTLER_TEMP_LIQUID0_BIT 8 203 #define THROTTLER_TEMP_LIQUID1_BIT 9 204 #define THROTTLER_TEMP_PLX_BIT 10 205 #define THROTTLER_TDC_GFX_BIT 11 206 #define THROTTLER_TDC_SOC_BIT 12 207 #define THROTTLER_PPT0_BIT 13 208 #define THROTTLER_PPT1_BIT 14 209 #define THROTTLER_PPT2_BIT 15 210 #define THROTTLER_PPT3_BIT 16 211 #define THROTTLER_FIT_BIT 17 212 #define THROTTLER_PPM_BIT 18 213 #define THROTTLER_APCC_BIT 19 214 215 // FW DState Features Control Bits 216 // FW DState Features Control Bits 217 #define FW_DSTATE_SOC_ULV_BIT 0 218 #define FW_DSTATE_G6_HSR_BIT 1 219 #define FW_DSTATE_G6_PHY_VDDCI_OFF_BIT 2 220 #define FW_DSTATE_MP0_DS_BIT 3 221 #define FW_DSTATE_SMN_DS_BIT 4 222 #define FW_DSTATE_MP1_DS_BIT 5 223 #define FW_DSTATE_MP1_WHISPER_MODE_BIT 6 224 #define FW_DSTATE_SOC_LIV_MIN_BIT 7 225 #define FW_DSTATE_SOC_PLL_PWRDN_BIT 8 226 #define FW_DSTATE_MEM_PLL_PWRDN_BIT 9 227 #define FW_DSTATE_OPTIMIZE_MALL_REFRESH_BIT 10 228 #define FW_DSTATE_MEM_PSI_BIT 11 229 #define FW_DSTATE_HSR_NON_STROBE_BIT 12 230 #define FW_DSTATE_MP0_ENTER_WFI_BIT 13 231 232 #define FW_DSTATE_SOC_ULV_MASK (1 << FW_DSTATE_SOC_ULV_BIT ) 233 #define FW_DSTATE_G6_HSR_MASK (1 << FW_DSTATE_G6_HSR_BIT ) 234 #define FW_DSTATE_G6_PHY_VDDCI_OFF_MASK (1 << FW_DSTATE_G6_PHY_VDDCI_OFF_BIT ) 235 #define FW_DSTATE_MP1_DS_MASK (1 << FW_DSTATE_MP1_DS_BIT ) 236 #define FW_DSTATE_MP0_DS_MASK (1 << FW_DSTATE_MP0_DS_BIT ) 237 #define FW_DSTATE_SMN_DS_MASK (1 << FW_DSTATE_SMN_DS_BIT ) 238 #define FW_DSTATE_MP1_WHISPER_MODE_MASK (1 << FW_DSTATE_MP1_WHISPER_MODE_BIT ) 239 #define FW_DSTATE_SOC_LIV_MIN_MASK (1 << FW_DSTATE_SOC_LIV_MIN_BIT ) 240 #define FW_DSTATE_SOC_PLL_PWRDN_MASK (1 << FW_DSTATE_SOC_PLL_PWRDN_BIT ) 241 #define FW_DSTATE_MEM_PLL_PWRDN_MASK (1 << FW_DSTATE_MEM_PLL_PWRDN_BIT ) 242 #define FW_DSTATE_OPTIMIZE_MALL_REFRESH_MASK (1 << FW_DSTATE_OPTIMIZE_MALL_REFRESH_BIT ) 243 #define FW_DSTATE_MEM_PSI_MASK (1 << FW_DSTATE_MEM_PSI_BIT ) 244 #define FW_DSTATE_HSR_NON_STROBE_MASK (1 << FW_DSTATE_HSR_NON_STROBE_BIT ) 245 #define FW_DSTATE_MP0_ENTER_WFI_MASK (1 << FW_DSTATE_MP0_ENTER_WFI_BIT ) 246 247 // GFX GPO Feature Contains PACE and DEM sub features 248 #define GFX_GPO_PACE_BIT 0 249 #define GFX_GPO_DEM_BIT 1 250 251 #define GFX_GPO_PACE_MASK (1 << GFX_GPO_PACE_BIT) 252 #define GFX_GPO_DEM_MASK (1 << GFX_GPO_DEM_BIT ) 253 254 #define GPO_UPDATE_REQ_UCLKDPM_MASK 0x1 255 #define GPO_UPDATE_REQ_FCLKDPM_MASK 0x2 256 #define GPO_UPDATE_REQ_MALLHIT_MASK 0x4 257 258 259 //LED Display Mask & Control Bits 260 #define LED_DISPLAY_GFX_DPM_BIT 0 261 #define LED_DISPLAY_PCIE_BIT 1 262 #define LED_DISPLAY_ERROR_BIT 2 263 264 //RLC Pace Table total number of levels 265 #define RLC_PACE_TABLE_NUM_LEVELS 16 266 267 typedef enum { 268 DRAM_BIT_WIDTH_DISABLED = 0, 269 DRAM_BIT_WIDTH_X_8, 270 DRAM_BIT_WIDTH_X_16, 271 DRAM_BIT_WIDTH_X_32, 272 DRAM_BIT_WIDTH_X_64, // NOT USED. 273 DRAM_BIT_WIDTH_X_128, 274 DRAM_BIT_WIDTH_COUNT, 275 } DRAM_BIT_WIDTH_TYPE_e; 276 277 //I2C Interface 278 #define NUM_I2C_CONTROLLERS 16 279 280 #define I2C_CONTROLLER_ENABLED 1 281 #define I2C_CONTROLLER_DISABLED 0 282 283 #define MAX_SW_I2C_COMMANDS 24 284 285 typedef enum { 286 I2C_CONTROLLER_PORT_0 = 0, //CKSVII2C0 287 I2C_CONTROLLER_PORT_1 = 1, //CKSVII2C1 288 I2C_CONTROLLER_PORT_COUNT, 289 } I2cControllerPort_e; 290 291 typedef enum { 292 I2C_CONTROLLER_NAME_VR_GFX = 0, 293 I2C_CONTROLLER_NAME_VR_SOC, 294 I2C_CONTROLLER_NAME_VR_VDDCI, 295 I2C_CONTROLLER_NAME_VR_MVDD, 296 I2C_CONTROLLER_NAME_LIQUID0, 297 I2C_CONTROLLER_NAME_LIQUID1, 298 I2C_CONTROLLER_NAME_PLX, 299 I2C_CONTROLLER_NAME_OTHER, 300 I2C_CONTROLLER_NAME_COUNT, 301 } I2cControllerName_e; 302 303 typedef enum { 304 I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0, 305 I2C_CONTROLLER_THROTTLER_VR_GFX, 306 I2C_CONTROLLER_THROTTLER_VR_SOC, 307 I2C_CONTROLLER_THROTTLER_VR_VDDCI, 308 I2C_CONTROLLER_THROTTLER_VR_MVDD, 309 I2C_CONTROLLER_THROTTLER_LIQUID0, 310 I2C_CONTROLLER_THROTTLER_LIQUID1, 311 I2C_CONTROLLER_THROTTLER_PLX, 312 I2C_CONTROLLER_THROTTLER_INA3221, 313 I2C_CONTROLLER_THROTTLER_COUNT, 314 } I2cControllerThrottler_e; 315 316 typedef enum { 317 I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5, 318 I2C_CONTROLLER_PROTOCOL_VR_IR35217, 319 I2C_CONTROLLER_PROTOCOL_TMP_TMP102A, 320 I2C_CONTROLLER_PROTOCOL_INA3221, 321 I2C_CONTROLLER_PROTOCOL_COUNT, 322 } I2cControllerProtocol_e; 323 324 typedef struct { 325 uint8_t Enabled; 326 uint8_t Speed; 327 uint8_t SlaveAddress; 328 uint8_t ControllerPort; 329 uint8_t ControllerName; 330 uint8_t ThermalThrotter; 331 uint8_t I2cProtocol; 332 uint8_t PaddingConfig; 333 } I2cControllerConfig_t; 334 335 typedef enum { 336 I2C_PORT_SVD_SCL = 0, 337 I2C_PORT_GPIO, 338 } I2cPort_e; 339 340 typedef enum { 341 I2C_SPEED_FAST_50K = 0, //50 Kbits/s 342 I2C_SPEED_FAST_100K, //100 Kbits/s 343 I2C_SPEED_FAST_400K, //400 Kbits/s 344 I2C_SPEED_FAST_PLUS_1M, //1 Mbits/s (in fast mode) 345 I2C_SPEED_HIGH_1M, //1 Mbits/s (in high speed mode) 346 I2C_SPEED_HIGH_2M, //2.3 Mbits/s 347 I2C_SPEED_COUNT, 348 } I2cSpeed_e; 349 350 typedef enum { 351 I2C_CMD_READ = 0, 352 I2C_CMD_WRITE, 353 I2C_CMD_COUNT, 354 } I2cCmdType_e; 355 356 typedef enum { 357 FAN_MODE_AUTO = 0, 358 FAN_MODE_MANUAL_LINEAR, 359 } FanMode_e; 360 361 #define CMDCONFIG_STOP_BIT 0 362 #define CMDCONFIG_RESTART_BIT 1 363 #define CMDCONFIG_READWRITE_BIT 2 //bit should be 0 for read, 1 for write 364 365 #define CMDCONFIG_STOP_MASK (1 << CMDCONFIG_STOP_BIT) 366 #define CMDCONFIG_RESTART_MASK (1 << CMDCONFIG_RESTART_BIT) 367 #define CMDCONFIG_READWRITE_MASK (1 << CMDCONFIG_READWRITE_BIT) 368 369 typedef struct { 370 uint8_t ReadWriteData; //Return data for read. Data to send for write 371 uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command, and is a read or write 372 } SwI2cCmd_t; //SW I2C Command Table 373 374 typedef struct { 375 uint8_t I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1) 376 uint8_t I2CSpeed; //Use I2cSpeed_e to indicate speed to select 377 uint8_t SlaveAddress; //Slave address of device 378 uint8_t NumCmds; //Number of commands 379 380 SwI2cCmd_t SwI2cCmds[MAX_SW_I2C_COMMANDS]; 381 } SwI2cRequest_t; // SW I2C Request Table 382 383 typedef struct { 384 SwI2cRequest_t SwI2cRequest; 385 386 uint32_t Spare[8]; 387 uint32_t MmHubPadding[8]; // SMU internal use 388 } SwI2cRequestExternal_t; 389 390 //D3HOT sequences 391 typedef enum { 392 BACO_SEQUENCE, 393 MSR_SEQUENCE, 394 BAMACO_SEQUENCE, 395 ULPS_SEQUENCE, 396 D3HOT_SEQUENCE_COUNT, 397 } D3HOTSequence_e; 398 399 //THis is aligned with RSMU PGFSM Register Mapping 400 typedef enum { 401 PG_DYNAMIC_MODE = 0, 402 PG_STATIC_MODE, 403 } PowerGatingMode_e; 404 405 //This is aligned with RSMU PGFSM Register Mapping 406 typedef enum { 407 PG_POWER_DOWN = 0, 408 PG_POWER_UP, 409 } PowerGatingSettings_e; 410 411 typedef struct { 412 uint32_t a; // store in IEEE float format in this variable 413 uint32_t b; // store in IEEE float format in this variable 414 uint32_t c; // store in IEEE float format in this variable 415 } QuadraticInt_t; 416 417 typedef struct { 418 uint32_t a; // store in fixed point, [31:20] signed integer, [19:0] fractional bits 419 uint32_t b; // store in fixed point, [31:20] signed integer, [19:0] fractional bits 420 uint32_t c; // store in fixed point, [31:20] signed integer, [19:0] fractional bits 421 } QuadraticFixedPoint_t; 422 423 typedef struct { 424 uint32_t m; // store in IEEE float format in this variable 425 uint32_t b; // store in IEEE float format in this variable 426 } LinearInt_t; 427 428 typedef struct { 429 uint32_t a; // store in IEEE float format in this variable 430 uint32_t b; // store in IEEE float format in this variable 431 uint32_t c; // store in IEEE float format in this variable 432 } DroopInt_t; 433 434 //Piecewise linear droop model, Sienna_Cichlid currently used only for GFX DFLL 435 #define NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS 5 436 typedef enum { 437 PIECEWISE_LINEAR_FUSED_MODEL = 0, 438 PIECEWISE_LINEAR_PP_MODEL, 439 QUADRATIC_PP_MODEL, 440 PERPART_PIECEWISE_LINEAR_PP_MODEL, 441 } DfllDroopModelSelect_e; 442 443 typedef struct { 444 uint32_t Fset[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //in GHz, store in IEEE float format 445 uint32_t Vdroop[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //in V , store in IEEE float format 446 }PiecewiseLinearDroopInt_t; 447 448 typedef enum { 449 GFXCLK_SOURCE_PLL = 0, 450 GFXCLK_SOURCE_DFLL, 451 GFXCLK_SOURCE_COUNT, 452 } GFXCLK_SOURCE_e; 453 454 //Only Clks that have DPM descriptors are listed here 455 typedef enum { 456 PPCLK_GFXCLK = 0, 457 PPCLK_SOCCLK, 458 PPCLK_UCLK, 459 PPCLK_FCLK, 460 PPCLK_DCLK_0, 461 PPCLK_VCLK_0, 462 PPCLK_DCLK_1, 463 PPCLK_VCLK_1, 464 PPCLK_DCEFCLK, 465 PPCLK_DISPCLK, 466 PPCLK_PIXCLK, 467 PPCLK_PHYCLK, 468 PPCLK_DTBCLK, 469 PPCLK_COUNT, 470 } PPCLK_e; 471 472 typedef enum { 473 VOLTAGE_MODE_AVFS = 0, 474 VOLTAGE_MODE_AVFS_SS, 475 VOLTAGE_MODE_SS, 476 VOLTAGE_MODE_COUNT, 477 } VOLTAGE_MODE_e; 478 479 480 typedef enum { 481 AVFS_VOLTAGE_GFX = 0, 482 AVFS_VOLTAGE_SOC, 483 AVFS_VOLTAGE_COUNT, 484 } AVFS_VOLTAGE_TYPE_e; 485 486 typedef enum { 487 UCLK_DIV_BY_1 = 0, 488 UCLK_DIV_BY_2, 489 UCLK_DIV_BY_4, 490 UCLK_DIV_BY_8, 491 } UCLK_DIV_e; 492 493 typedef enum { 494 GPIO_INT_POLARITY_ACTIVE_LOW = 0, 495 GPIO_INT_POLARITY_ACTIVE_HIGH, 496 } GpioIntPolarity_e; 497 498 typedef enum { 499 PWR_CONFIG_TDP = 0, 500 PWR_CONFIG_TGP, 501 PWR_CONFIG_TCP_ESTIMATED, 502 PWR_CONFIG_TCP_MEASURED, 503 } PwrConfig_e; 504 505 typedef enum { 506 XGMI_LINK_RATE_2 = 2, // 2Gbps 507 XGMI_LINK_RATE_4 = 4, // 4Gbps 508 XGMI_LINK_RATE_8 = 8, // 8Gbps 509 XGMI_LINK_RATE_12 = 12, // 12Gbps 510 XGMI_LINK_RATE_16 = 16, // 16Gbps 511 XGMI_LINK_RATE_17 = 17, // 17Gbps 512 XGMI_LINK_RATE_18 = 18, // 18Gbps 513 XGMI_LINK_RATE_19 = 19, // 19Gbps 514 XGMI_LINK_RATE_20 = 20, // 20Gbps 515 XGMI_LINK_RATE_21 = 21, // 21Gbps 516 XGMI_LINK_RATE_22 = 22, // 22Gbps 517 XGMI_LINK_RATE_23 = 23, // 23Gbps 518 XGMI_LINK_RATE_24 = 24, // 24Gbps 519 XGMI_LINK_RATE_25 = 25, // 25Gbps 520 XGMI_LINK_RATE_COUNT 521 } XGMI_LINK_RATE_e; 522 523 typedef enum { 524 XGMI_LINK_WIDTH_1 = 0, // x1 525 XGMI_LINK_WIDTH_2, // x2 526 XGMI_LINK_WIDTH_4, // x4 527 XGMI_LINK_WIDTH_8, // x8 528 XGMI_LINK_WIDTH_9, // x9 529 XGMI_LINK_WIDTH_16, // x16 530 XGMI_LINK_WIDTH_COUNT 531 } XGMI_LINK_WIDTH_e; 532 533 typedef struct { 534 uint8_t VoltageMode; // 0 - AVFS only, 1- min(AVFS,SS), 2-SS only 535 uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM 536 uint8_t NumDiscreteLevels; // Set to 2 (Fmin, Fmax) when using fine grained DPM, otherwise set to # discrete levels used 537 uint8_t Padding; 538 LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz) 539 QuadraticInt_t SsCurve; // Slow-slow curve (GHz->V) 540 uint16_t SsFmin; // Fmin for SS curve. If SS curve is selected, will use V@SSFmin for F <= Fmin 541 uint16_t Padding16; 542 } DpmDescriptor_t; 543 544 typedef enum { 545 PPT_THROTTLER_PPT0, 546 PPT_THROTTLER_PPT1, 547 PPT_THROTTLER_PPT2, 548 PPT_THROTTLER_PPT3, 549 PPT_THROTTLER_COUNT 550 } PPT_THROTTLER_e; 551 552 typedef enum { 553 TEMP_EDGE, 554 TEMP_HOTSPOT, 555 TEMP_MEM, 556 TEMP_VR_GFX, 557 TEMP_VR_MEM0, 558 TEMP_VR_MEM1, 559 TEMP_VR_SOC, 560 TEMP_LIQUID0, 561 TEMP_LIQUID1, 562 TEMP_PLX, 563 TEMP_COUNT, 564 } TEMP_e; 565 566 typedef enum { 567 TDC_THROTTLER_GFX, 568 TDC_THROTTLER_SOC, 569 TDC_THROTTLER_COUNT 570 } TDC_THROTTLER_e; 571 572 typedef enum { 573 CUSTOMER_VARIANT_ROW, 574 CUSTOMER_VARIANT_FALCON, 575 CUSTOMER_VARIANT_COUNT, 576 } CUSTOMER_VARIANT_e; 577 578 // Used for 2-step UCLK DPM change workaround 579 typedef struct { 580 uint16_t Fmin; 581 uint16_t Fmax; 582 } UclkDpmChangeRange_t; 583 584 typedef struct { 585 // MAJOR SECTION: SKU PARAMETERS 586 587 uint32_t Version; 588 589 // SECTION: Feature Enablement 590 uint32_t FeaturesToRun[NUM_FEATURES / 32]; 591 592 // SECTION: Infrastructure Limits 593 uint16_t SocketPowerLimitAc[PPT_THROTTLER_COUNT]; // Watts 594 uint16_t SocketPowerLimitAcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms 595 uint16_t SocketPowerLimitDc[PPT_THROTTLER_COUNT]; // Watts 596 uint16_t SocketPowerLimitDcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms 597 598 uint16_t TdcLimit[TDC_THROTTLER_COUNT]; // Amps 599 uint16_t TdcLimitTau[TDC_THROTTLER_COUNT]; // Time constant of LPF in ms 600 601 uint16_t TemperatureLimit[TEMP_COUNT]; // Celcius 602 603 uint32_t FitLimit; // Failures in time (failures per million parts over the defined lifetime) 604 605 // SECTION: Power Configuration 606 uint8_t TotalPowerConfig; //0-TDP, 1-TGP, 2-TCP Estimated, 3-TCP Measured. Use defines from PwrConfig_e 607 uint8_t TotalPowerPadding[3]; 608 609 // SECTION: APCC Settings 610 uint32_t ApccPlusResidencyLimit; 611 612 //SECTION: SMNCLK DPM 613 uint16_t SmnclkDpmFreq [NUM_SMNCLK_DPM_LEVELS]; // in MHz 614 uint16_t SmnclkDpmVoltage [NUM_SMNCLK_DPM_LEVELS]; // mV(Q2) 615 616 uint32_t PaddingAPCC; 617 uint16_t PerPartDroopVsetGfxDfll[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //In mV(Q2) 618 uint16_t PaddingPerPartDroop; 619 620 // SECTION: Throttler settings 621 uint32_t ThrottlerControlMask; // See Throtter masks defines 622 623 // SECTION: FW DSTATE Settings 624 uint32_t FwDStateMask; // See FW DState masks defines 625 626 // SECTION: ULV Settings 627 uint16_t UlvVoltageOffsetSoc; // In mV(Q2) 628 uint16_t UlvVoltageOffsetGfx; // In mV(Q2) 629 630 uint16_t MinVoltageUlvGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX in ULV mode 631 uint16_t MinVoltageUlvSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC in ULV mode 632 633 uint16_t SocLIVmin; // In mV(Q2) Long Idle Vmin (deep ULV), for VDD_SOC 634 uint16_t PaddingLIVmin; 635 636 uint8_t GceaLinkMgrIdleThreshold; //Set by SMU FW during enablment of GFXOFF. Controls delay for GFX SDP port disconnection during idle events 637 uint8_t paddingRlcUlvParams[3]; 638 639 // SECTION: Voltage Control Parameters 640 uint16_t MinVoltageGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX 641 uint16_t MinVoltageSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC 642 uint16_t MaxVoltageGfx; // In mV(Q2) Maximum Voltage allowable of VDD_GFX 643 uint16_t MaxVoltageSoc; // In mV(Q2) Maximum Voltage allowable of VDD_SOC 644 645 uint16_t LoadLineResistanceGfx; // In mOhms with 8 fractional bits 646 uint16_t LoadLineResistanceSoc; // In mOhms with 8 fractional bits 647 648 // SECTION: Temperature Dependent Vmin 649 uint16_t VDDGFX_TVmin; //Celcius 650 uint16_t VDDSOC_TVmin; //Celcius 651 uint16_t VDDGFX_Vmin_HiTemp; // mV Q2 652 uint16_t VDDGFX_Vmin_LoTemp; // mV Q2 653 uint16_t VDDSOC_Vmin_HiTemp; // mV Q2 654 uint16_t VDDSOC_Vmin_LoTemp; // mV Q2 655 656 uint16_t VDDGFX_TVminHystersis; // Celcius 657 uint16_t VDDSOC_TVminHystersis; // Celcius 658 659 //SECTION: DPM Config 1 660 DpmDescriptor_t DpmDescriptor[PPCLK_COUNT]; 661 662 uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz 663 uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz 664 uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz 665 uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz 666 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 667 uint16_t FreqTableDcefclk [NUM_DCEFCLK_DPM_LEVELS ]; // In MHz 668 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz 669 uint16_t FreqTablePixclk [NUM_PIXCLK_DPM_LEVELS ]; // In MHz 670 uint16_t FreqTablePhyclk [NUM_PHYCLK_DPM_LEVELS ]; // In MHz 671 uint16_t FreqTableDtbclk [NUM_DTBCLK_DPM_LEVELS ]; // In MHz 672 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz 673 uint32_t Paddingclks; 674 675 DroopInt_t PerPartDroopModelGfxDfll[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //GHz ->Vstore in IEEE float format 676 677 uint32_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz 678 679 uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:Div-1/8 680 681 // Used for MALL performance boost 682 uint16_t FclkBoostFreq; // In Mhz 683 uint16_t FclkParamPadding; 684 685 // SECTION: DPM Config 2 686 uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS]; // in MHz 687 uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS]; // mV(Q2) 688 uint16_t MemVddciVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 689 uint16_t MemMvddVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 690 // GFXCLK DPM 691 uint16_t GfxclkFgfxoffEntry; // in Mhz 692 uint16_t GfxclkFinit; // in Mhz 693 uint16_t GfxclkFidle; // in MHz 694 uint8_t GfxclkSource; // 0 = PLL, 1 = DFLL 695 uint8_t GfxclkPadding; 696 697 // GFX GPO 698 uint8_t GfxGpoSubFeatureMask; // bit 0 = PACE, bit 1 = DEM 699 uint8_t GfxGpoEnabledWorkPolicyMask; //Any policy that GPO can be enabled 700 uint8_t GfxGpoDisabledWorkPolicyMask; //Any policy that GPO can be disabled 701 uint8_t GfxGpoPadding[1]; 702 uint32_t GfxGpoVotingAllow; //For indicating which feature changes should result in a GPO table recalculation 703 704 uint32_t GfxGpoPadding32[4]; 705 706 uint16_t GfxDcsFopt; // Optimal GFXCLK for DCS in Mhz 707 uint16_t GfxDcsFclkFopt; // Optimal FCLK for DCS in Mhz 708 uint16_t GfxDcsUclkFopt; // Optimal UCLK for DCS in Mhz 709 710 uint16_t DcsGfxOffVoltage; //Voltage in mV(Q2) applied to VDDGFX when entering DCS GFXOFF phase 711 712 uint16_t DcsMinGfxOffTime; //Minimum amount of time PMFW shuts GFX OFF as part of GFX DCS phase 713 uint16_t DcsMaxGfxOffTime; //Maximum amount of time PMFW can shut GFX OFF as part of GFX DCS phase at a stretch. 714 715 uint32_t DcsMinCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS. 716 717 uint16_t DcsExitHysteresis; //The min amount of time power credit accumulator should have a value > 0 before SMU exits the DCS throttling phase. 718 uint16_t DcsTimeout; //This is the amount of time SMU FW waits for RLC to put GFX into GFXOFF before reverting to the fallback mechanism of throttling GFXCLK to Fmin. 719 720 uint32_t DcsParamPadding[5]; 721 722 uint16_t FlopsPerByteTable[RLC_PACE_TABLE_NUM_LEVELS]; // Q8.8 723 724 // UCLK section 725 uint8_t LowestUclkReservedForUlv; // Set this to 1 if UCLK DPM0 is reserved for ULV-mode only 726 uint8_t PaddingMem[3]; 727 728 uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 4 DPM states, 0-P0, 1-P1, 2-P2, 3-P3. 729 730 // Used for 2-Step UCLK change workaround 731 UclkDpmChangeRange_t UclkDpmSrcFreqRange; // In Mhz 732 UclkDpmChangeRange_t UclkDpmTargFreqRange; // In Mhz 733 uint16_t UclkDpmMidstepFreq; // In Mhz 734 uint16_t UclkMidstepPadding; 735 736 // Link DPM Settings 737 uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4 738 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 739 uint16_t LclkFreq[NUM_LINK_LEVELS]; 740 741 // SECTION: Fan Control 742 uint16_t FanStopTemp; //Celcius 743 uint16_t FanStartTemp; //Celcius 744 745 uint16_t FanGain[TEMP_COUNT]; 746 747 uint16_t FanPwmMin; 748 uint16_t FanAcousticLimitRpm; 749 uint16_t FanThrottlingRpm; 750 uint16_t FanMaximumRpm; 751 uint16_t MGpuFanBoostLimitRpm; 752 uint16_t FanTargetTemperature; 753 uint16_t FanTargetGfxclk; 754 uint16_t FanPadding16; 755 uint8_t FanTempInputSelect; 756 uint8_t FanPadding; 757 uint8_t FanZeroRpmEnable; 758 uint8_t FanTachEdgePerRev; 759 760 // The following are AFC override parameters. Leave at 0 to use FW defaults. 761 int16_t FuzzyFan_ErrorSetDelta; 762 int16_t FuzzyFan_ErrorRateSetDelta; 763 int16_t FuzzyFan_PwmSetDelta; 764 uint16_t FuzzyFan_Reserved; 765 766 // SECTION: AVFS 767 // Overrides 768 uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT]; 769 uint8_t dBtcGbGfxDfllModelSelect; //0 -> fused piece-wise model, 1 -> piece-wise linear(PPTable), 2 -> quadratic model(PPTable) 770 uint8_t Padding8_Avfs; 771 772 QuadraticInt_t qAvfsGb[AVFS_VOLTAGE_COUNT]; // GHz->V Override of fused curve 773 DroopInt_t dBtcGbGfxPll; // GHz->V BtcGb 774 DroopInt_t dBtcGbGfxDfll; // GHz->V BtcGb 775 DroopInt_t dBtcGbSoc; // GHz->V BtcGb 776 LinearInt_t qAgingGb[AVFS_VOLTAGE_COUNT]; // GHz->V 777 778 PiecewiseLinearDroopInt_t PiecewiseLinearDroopIntGfxDfll; //GHz ->Vstore in IEEE float format 779 780 QuadraticInt_t qStaticVoltageOffset[AVFS_VOLTAGE_COUNT]; // GHz->V 781 782 uint16_t DcTol[AVFS_VOLTAGE_COUNT]; // mV Q2 783 784 uint8_t DcBtcEnabled[AVFS_VOLTAGE_COUNT]; 785 uint8_t Padding8_GfxBtc[2]; 786 787 uint16_t DcBtcMin[AVFS_VOLTAGE_COUNT]; // mV Q2 788 uint16_t DcBtcMax[AVFS_VOLTAGE_COUNT]; // mV Q2 789 790 uint16_t DcBtcGb[AVFS_VOLTAGE_COUNT]; // mV Q2 791 792 // SECTION: XGMI 793 uint8_t XgmiDpmPstates[NUM_XGMI_LEVELS]; // 2 DPM states, high and low. 0-P0, 1-P1, 2-P2, 3-P3. 794 uint8_t XgmiDpmSpare[2]; 795 796 // SECTION: Advanced Options 797 uint32_t DebugOverrides; 798 QuadraticInt_t ReservedEquation0; 799 QuadraticInt_t ReservedEquation1; 800 QuadraticInt_t ReservedEquation2; 801 QuadraticInt_t ReservedEquation3; 802 803 // SECTION: Sku Reserved 804 uint8_t CustomerVariant; 805 806 //VC BTC parameters are only applicable to VDD_GFX domain 807 uint8_t VcBtcEnabled; 808 uint16_t VcBtcVminT0; // T0_VMIN 809 uint16_t VcBtcFixedVminAgingOffset; // FIXED_VMIN_AGING_OFFSET 810 uint16_t VcBtcVmin2PsmDegrationGb; // VMIN_TO_PSM_DEGRADATION_GB 811 uint32_t VcBtcPsmA; // A_PSM 812 uint32_t VcBtcPsmB; // B_PSM 813 uint32_t VcBtcVminA; // A_VMIN 814 uint32_t VcBtcVminB; // B_VMIN 815 816 //GPIO Board feature 817 uint16_t LedGpio; //GeneriA GPIO flag used to control the radeon LEDs 818 uint16_t GfxPowerStagesGpio; //Genlk_vsync GPIO flag used to control gfx power stages 819 820 uint32_t SkuReserved[8]; 821 822 823 // MAJOR SECTION: BOARD PARAMETERS 824 825 //SECTION: Gaming Clocks 826 uint32_t GamingClk[6]; 827 828 // SECTION: I2C Control 829 I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS]; 830 831 uint8_t GpioScl; // GPIO Number for SCL Line, used only for CKSVII2C1 832 uint8_t GpioSda; // GPIO Number for SDA Line, used only for CKSVII2C1 833 uint8_t FchUsbPdSlaveAddr; //For requesting USB PD controller S-states via FCH I2C when entering PME turn off 834 uint8_t I2cSpare[1]; 835 836 // SECTION: SVI2 Board Parameters 837 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 838 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 839 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 840 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 841 842 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 843 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 844 uint8_t VddciUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 845 uint8_t MvddUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 846 847 // SECTION: Telemetry Settings 848 uint16_t GfxMaxCurrent; // in Amps 849 int8_t GfxOffset; // in Amps 850 uint8_t Padding_TelemetryGfx; 851 852 uint16_t SocMaxCurrent; // in Amps 853 int8_t SocOffset; // in Amps 854 uint8_t Padding_TelemetrySoc; 855 856 uint16_t Mem0MaxCurrent; // in Amps 857 int8_t Mem0Offset; // in Amps 858 uint8_t Padding_TelemetryMem0; 859 860 uint16_t Mem1MaxCurrent; // in Amps 861 int8_t Mem1Offset; // in Amps 862 uint8_t Padding_TelemetryMem1; 863 864 uint32_t MvddRatio; // This is used for MVDD Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16) 865 866 // SECTION: GPIO Settings 867 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 868 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 869 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 870 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 871 872 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 873 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 874 uint8_t GthrGpio; // GPIO pin configured for GTHR Event 875 uint8_t GthrPolarity; // replace GPIO polarity for GTHR 876 877 // LED Display Settings 878 uint8_t LedPin0; // GPIO number for LedPin[0] 879 uint8_t LedPin1; // GPIO number for LedPin[1] 880 uint8_t LedPin2; // GPIO number for LedPin[2] 881 uint8_t LedEnableMask; 882 883 uint8_t LedPcie; // GPIO number for PCIE results 884 uint8_t LedError; // GPIO number for Error Cases 885 uint8_t LedSpare1[2]; 886 887 // SECTION: Clock Spread Spectrum 888 889 // GFXCLK PLL Spread Spectrum 890 uint8_t PllGfxclkSpreadEnabled; // on or off 891 uint8_t PllGfxclkSpreadPercent; // Q4.4 892 uint16_t PllGfxclkSpreadFreq; // kHz 893 894 // GFXCLK DFLL Spread Spectrum 895 uint8_t DfllGfxclkSpreadEnabled; // on or off 896 uint8_t DfllGfxclkSpreadPercent; // Q4.4 897 uint16_t DfllGfxclkSpreadFreq; // kHz 898 899 // UCLK Spread Spectrum 900 uint16_t UclkSpreadPadding; 901 uint16_t UclkSpreadFreq; // kHz 902 903 // FCLK Spread Spectrum 904 uint8_t FclkSpreadEnabled; // on or off 905 uint8_t FclkSpreadPercent; // Q4.4 906 uint16_t FclkSpreadFreq; // kHz 907 908 // Section: Memory Config 909 uint32_t MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask. 910 911 uint8_t DramBitWidth; // For DRAM use only. See Dram Bit width type defines 912 uint8_t PaddingMem1[3]; 913 914 // Section: Total Board Power 915 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power 916 uint16_t BoardPowerPadding; 917 918 // SECTION: XGMI Training 919 uint8_t XgmiLinkSpeed [NUM_XGMI_PSTATE_LEVELS]; 920 uint8_t XgmiLinkWidth [NUM_XGMI_PSTATE_LEVELS]; 921 922 uint16_t XgmiFclkFreq [NUM_XGMI_PSTATE_LEVELS]; 923 uint16_t XgmiSocVoltage [NUM_XGMI_PSTATE_LEVELS]; 924 925 // SECTION: UMC feature flags 926 uint8_t HsrEnabled; 927 uint8_t VddqOffEnabled; 928 uint8_t PaddingUmcFlags[2]; 929 930 // UCLK Spread Spectrum 931 uint8_t UclkSpreadPercent[16]; 932 933 // SECTION: Board Reserved 934 uint32_t BoardReserved[11]; 935 936 // SECTION: Structure Padding 937 938 // Padding for MMHUB - do not modify this 939 uint32_t MmHubPadding[8]; // SMU internal use 940 941 } PPTable_t; 942 943 typedef struct { 944 // Time constant parameters for clock averages in ms 945 uint16_t GfxclkAverageLpfTau; 946 uint16_t FclkAverageLpfTau; 947 uint16_t UclkAverageLpfTau; 948 uint16_t GfxActivityLpfTau; 949 uint16_t UclkActivityLpfTau; 950 uint16_t SocketPowerLpfTau; 951 uint16_t VcnClkAverageLpfTau; 952 uint16_t padding16; 953 } DriverSmuConfig_t; 954 955 typedef struct { 956 DriverSmuConfig_t DriverSmuConfig; 957 958 uint32_t Spare[7]; 959 // Padding - ignore 960 uint32_t MmHubPadding[8]; // SMU internal use 961 } DriverSmuConfigExternal_t; 962 963 typedef struct { 964 uint16_t GfxclkFmin; // MHz 965 uint16_t GfxclkFmax; // MHz 966 QuadraticInt_t CustomGfxVfCurve; // a: mV/MHz^2, b: mv/MHz, c: mV 967 uint16_t CustomCurveFmin; // MHz 968 uint16_t UclkFmin; // MHz 969 uint16_t UclkFmax; // MHz 970 int16_t OverDrivePct; // % 971 uint16_t FanMaximumRpm; 972 uint16_t FanMinimumPwm; 973 uint16_t FanAcousticLimitRpm; 974 uint16_t FanTargetTemperature; // Degree Celcius 975 uint8_t FanLinearPwmPoints[NUM_OD_FAN_MAX_POINTS]; 976 uint8_t FanLinearTempPoints[NUM_OD_FAN_MAX_POINTS]; 977 uint16_t MaxOpTemp; // Degree Celcius 978 int16_t VddGfxOffset; // in mV 979 uint8_t FanZeroRpmEnable; 980 uint8_t FanZeroRpmStopTemp; 981 uint8_t FanMode; 982 uint8_t Padding[1]; 983 } OverDriveTable_t; 984 985 typedef struct { 986 OverDriveTable_t OverDriveTable; 987 uint32_t Spare[8]; 988 989 uint32_t MmHubPadding[8]; // SMU internal use 990 } OverDriveTableExternal_t; 991 992 typedef struct { 993 uint32_t CurrClock[PPCLK_COUNT]; 994 995 uint16_t AverageGfxclkFrequencyPreDs; 996 uint16_t AverageGfxclkFrequencyPostDs; 997 uint16_t AverageFclkFrequencyPreDs; 998 uint16_t AverageFclkFrequencyPostDs; 999 uint16_t AverageUclkFrequencyPreDs ; 1000 uint16_t AverageUclkFrequencyPostDs ; 1001 1002 1003 uint16_t AverageGfxActivity ; 1004 uint16_t AverageUclkActivity ; 1005 uint8_t CurrSocVoltageOffset ; 1006 uint8_t CurrGfxVoltageOffset ; 1007 uint8_t CurrMemVidOffset ; 1008 uint8_t Padding8 ; 1009 uint16_t AverageSocketPower ; 1010 uint16_t TemperatureEdge ; 1011 uint16_t TemperatureHotspot ; 1012 uint16_t TemperatureMem ; 1013 uint16_t TemperatureVrGfx ; 1014 uint16_t TemperatureVrMem0 ; 1015 uint16_t TemperatureVrMem1 ; 1016 uint16_t TemperatureVrSoc ; 1017 uint16_t TemperatureLiquid0 ; 1018 uint16_t TemperatureLiquid1 ; 1019 uint16_t TemperaturePlx ; 1020 uint16_t Padding16 ; 1021 uint32_t ThrottlerStatus ; 1022 1023 uint8_t LinkDpmLevel; 1024 uint8_t CurrFanPwm; 1025 uint16_t CurrFanSpeed; 1026 1027 //BACO metrics, PMFW-1721 1028 //metrics for D3hot entry/exit and driver ARM msgs 1029 uint8_t D3HotEntryCountPerMode[D3HOT_SEQUENCE_COUNT]; 1030 uint8_t D3HotExitCountPerMode[D3HOT_SEQUENCE_COUNT]; 1031 uint8_t ArmMsgReceivedCountPerMode[D3HOT_SEQUENCE_COUNT]; 1032 1033 //PMFW-4362 1034 uint32_t EnergyAccumulator; 1035 uint16_t AverageVclk0Frequency ; 1036 uint16_t AverageDclk0Frequency ; 1037 uint16_t AverageVclk1Frequency ; 1038 uint16_t AverageDclk1Frequency ; 1039 uint16_t VcnActivityPercentage ; //place holder, David N. to provide full sequence 1040 uint8_t PcieRate ; 1041 uint8_t PcieWidth ; 1042 uint16_t AverageGfxclkFrequencyTarget; 1043 uint16_t Padding16_2; 1044 1045 } SmuMetrics_t; 1046 1047 typedef struct { 1048 SmuMetrics_t SmuMetrics; 1049 uint32_t Spare[1]; 1050 1051 // Padding - ignore 1052 uint32_t MmHubPadding[8]; // SMU internal use 1053 } SmuMetricsExternal_t; 1054 1055 typedef struct { 1056 uint16_t MinClock; // This is either DCEFCLK or SOCCLK (in MHz) 1057 uint16_t MaxClock; // This is either DCEFCLK or SOCCLK (in MHz) 1058 uint16_t MinUclk; 1059 uint16_t MaxUclk; 1060 1061 uint8_t WmSetting; 1062 uint8_t Flags; 1063 uint8_t Padding[2]; 1064 1065 } WatermarkRowGeneric_t; 1066 1067 #define NUM_WM_RANGES 4 1068 1069 typedef enum { 1070 WM_SOCCLK = 0, 1071 WM_DCEFCLK, 1072 WM_COUNT, 1073 } WM_CLOCK_e; 1074 1075 typedef enum { 1076 WATERMARKS_CLOCK_RANGE = 0, 1077 WATERMARKS_DUMMY_PSTATE, 1078 WATERMARKS_MALL, 1079 WATERMARKS_COUNT, 1080 } WATERMARKS_FLAGS_e; 1081 1082 typedef struct { 1083 // Watermarks 1084 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; 1085 } Watermarks_t; 1086 1087 typedef struct { 1088 Watermarks_t Watermarks; 1089 1090 uint32_t MmHubPadding[8]; // SMU internal use 1091 } WatermarksExternal_t; 1092 1093 typedef struct { 1094 uint16_t avgPsmCount[67]; 1095 uint16_t minPsmCount[67]; 1096 float avgPsmVoltage[67]; 1097 float minPsmVoltage[67]; 1098 } AvfsDebugTable_t; 1099 1100 typedef struct { 1101 AvfsDebugTable_t AvfsDebugTable; 1102 1103 uint32_t MmHubPadding[8]; // SMU internal use 1104 } AvfsDebugTableExternal_t; 1105 1106 typedef struct { 1107 uint8_t AvfsVersion; 1108 uint8_t Padding; 1109 1110 uint8_t AvfsEn[AVFS_VOLTAGE_COUNT]; 1111 1112 uint8_t OverrideVFT[AVFS_VOLTAGE_COUNT]; 1113 uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT]; 1114 1115 uint8_t OverrideTemperatures[AVFS_VOLTAGE_COUNT]; 1116 uint8_t OverrideVInversion[AVFS_VOLTAGE_COUNT]; 1117 uint8_t OverrideP2V[AVFS_VOLTAGE_COUNT]; 1118 uint8_t OverrideP2VCharzFreq[AVFS_VOLTAGE_COUNT]; 1119 1120 int32_t VFT0_m1[AVFS_VOLTAGE_COUNT]; // Q8.24 1121 int32_t VFT0_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 1122 int32_t VFT0_b[AVFS_VOLTAGE_COUNT]; // Q32 1123 1124 int32_t VFT1_m1[AVFS_VOLTAGE_COUNT]; // Q8.16 1125 int32_t VFT1_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 1126 int32_t VFT1_b[AVFS_VOLTAGE_COUNT]; // Q32 1127 1128 int32_t VFT2_m1[AVFS_VOLTAGE_COUNT]; // Q8.16 1129 int32_t VFT2_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 1130 int32_t VFT2_b[AVFS_VOLTAGE_COUNT]; // Q32 1131 1132 int32_t AvfsGb0_m1[AVFS_VOLTAGE_COUNT]; // Q8.24 1133 int32_t AvfsGb0_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 1134 int32_t AvfsGb0_b[AVFS_VOLTAGE_COUNT]; // Q32 1135 1136 int32_t AcBtcGb_m1[AVFS_VOLTAGE_COUNT]; // Q8.24 1137 int32_t AcBtcGb_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 1138 int32_t AcBtcGb_b[AVFS_VOLTAGE_COUNT]; // Q32 1139 1140 uint32_t AvfsTempCold[AVFS_VOLTAGE_COUNT]; 1141 uint32_t AvfsTempMid[AVFS_VOLTAGE_COUNT]; 1142 uint32_t AvfsTempHot[AVFS_VOLTAGE_COUNT]; 1143 1144 uint32_t VInversion[AVFS_VOLTAGE_COUNT]; // in mV with 2 fractional bits 1145 1146 1147 int32_t P2V_m1[AVFS_VOLTAGE_COUNT]; // Q8.24 1148 int32_t P2V_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 1149 int32_t P2V_b[AVFS_VOLTAGE_COUNT]; // Q32 1150 1151 uint32_t P2VCharzFreq[AVFS_VOLTAGE_COUNT]; // in 10KHz units 1152 1153 uint32_t EnabledAvfsModules[3]; //Sienna_Cichlid - 67 AVFS modules 1154 } AvfsFuseOverride_t; 1155 1156 typedef struct { 1157 AvfsFuseOverride_t AvfsFuseOverride; 1158 1159 uint32_t MmHubPadding[8]; // SMU internal use 1160 } AvfsFuseOverrideExternal_t; 1161 1162 typedef struct { 1163 uint8_t Gfx_ActiveHystLimit; 1164 uint8_t Gfx_IdleHystLimit; 1165 uint8_t Gfx_FPS; 1166 uint8_t Gfx_MinActiveFreqType; 1167 uint8_t Gfx_BoosterFreqType; 1168 uint8_t Gfx_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock. 1169 uint16_t Gfx_MinActiveFreq; // MHz 1170 uint16_t Gfx_BoosterFreq; // MHz 1171 uint16_t Gfx_PD_Data_time_constant; // Time constant of PD controller in ms 1172 uint32_t Gfx_PD_Data_limit_a; // Q16 1173 uint32_t Gfx_PD_Data_limit_b; // Q16 1174 uint32_t Gfx_PD_Data_limit_c; // Q16 1175 uint32_t Gfx_PD_Data_error_coeff; // Q16 1176 uint32_t Gfx_PD_Data_error_rate_coeff; // Q16 1177 1178 uint8_t Fclk_ActiveHystLimit; 1179 uint8_t Fclk_IdleHystLimit; 1180 uint8_t Fclk_FPS; 1181 uint8_t Fclk_MinActiveFreqType; 1182 uint8_t Fclk_BoosterFreqType; 1183 uint8_t Fclk_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock. 1184 uint16_t Fclk_MinActiveFreq; // MHz 1185 uint16_t Fclk_BoosterFreq; // MHz 1186 uint16_t Fclk_PD_Data_time_constant; // Time constant of PD controller in ms 1187 uint32_t Fclk_PD_Data_limit_a; // Q16 1188 uint32_t Fclk_PD_Data_limit_b; // Q16 1189 uint32_t Fclk_PD_Data_limit_c; // Q16 1190 uint32_t Fclk_PD_Data_error_coeff; // Q16 1191 uint32_t Fclk_PD_Data_error_rate_coeff; // Q16 1192 1193 uint8_t Mem_ActiveHystLimit; 1194 uint8_t Mem_IdleHystLimit; 1195 uint8_t Mem_FPS; 1196 uint8_t Mem_MinActiveFreqType; 1197 uint8_t Mem_BoosterFreqType; 1198 uint8_t Mem_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock. 1199 uint16_t Mem_MinActiveFreq; // MHz 1200 uint16_t Mem_BoosterFreq; // MHz 1201 uint16_t Mem_PD_Data_time_constant; // Time constant of PD controller in ms 1202 uint32_t Mem_PD_Data_limit_a; // Q16 1203 uint32_t Mem_PD_Data_limit_b; // Q16 1204 uint32_t Mem_PD_Data_limit_c; // Q16 1205 uint32_t Mem_PD_Data_error_coeff; // Q16 1206 uint32_t Mem_PD_Data_error_rate_coeff; // Q16 1207 1208 uint32_t Mem_UpThreshold_Limit; // Q16 1209 uint8_t Mem_UpHystLimit; 1210 uint8_t Mem_DownHystLimit; 1211 uint16_t Mem_Fps; 1212 1213 } DpmActivityMonitorCoeffInt_t; 1214 1215 1216 typedef struct { 1217 DpmActivityMonitorCoeffInt_t DpmActivityMonitorCoeffInt; 1218 uint32_t MmHubPadding[8]; // SMU internal use 1219 } DpmActivityMonitorCoeffIntExternal_t; 1220 1221 // Workload bits 1222 #define WORKLOAD_PPLIB_DEFAULT_BIT 0 1223 #define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1 1224 #define WORKLOAD_PPLIB_POWER_SAVING_BIT 2 1225 #define WORKLOAD_PPLIB_VIDEO_BIT 3 1226 #define WORKLOAD_PPLIB_VR_BIT 4 1227 #define WORKLOAD_PPLIB_COMPUTE_BIT 5 1228 #define WORKLOAD_PPLIB_CUSTOM_BIT 6 1229 #define WORKLOAD_PPLIB_W3D_BIT 7 1230 #define WORKLOAD_PPLIB_COUNT 8 1231 1232 1233 // These defines are used with the following messages: 1234 // SMC_MSG_TransferTableDram2Smu 1235 // SMC_MSG_TransferTableSmu2Dram 1236 1237 // Table transfer status 1238 #define TABLE_TRANSFER_OK 0x0 1239 #define TABLE_TRANSFER_FAILED 0xFF 1240 1241 // Table types 1242 #define TABLE_PPTABLE 0 1243 #define TABLE_WATERMARKS 1 1244 #define TABLE_AVFS_PSM_DEBUG 2 1245 #define TABLE_AVFS_FUSE_OVERRIDE 3 1246 #define TABLE_PMSTATUSLOG 4 1247 #define TABLE_SMU_METRICS 5 1248 #define TABLE_DRIVER_SMU_CONFIG 6 1249 #define TABLE_ACTIVITY_MONITOR_COEFF 7 1250 #define TABLE_OVERDRIVE 8 1251 #define TABLE_I2C_COMMANDS 9 1252 #define TABLE_PACE 10 1253 #define TABLE_COUNT 11 1254 1255 typedef struct { 1256 float FlopsPerByteTable[RLC_PACE_TABLE_NUM_LEVELS]; 1257 } RlcPaceFlopsPerByteOverride_t; 1258 1259 typedef struct { 1260 RlcPaceFlopsPerByteOverride_t RlcPaceFlopsPerByteOverride; 1261 1262 uint32_t MmHubPadding[8]; // SMU internal use 1263 } RlcPaceFlopsPerByteOverrideExternal_t; 1264 1265 // These defines are used with the SMC_MSG_SetUclkFastSwitch message. 1266 #define UCLK_SWITCH_SLOW 0 1267 #define UCLK_SWITCH_FAST 1 1268 #endif 1269