1 /*******************************************************************************
2 *
3 * Copyright (c) 2015-2016 Intel Corporation. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenFabrics.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 *
33 *******************************************************************************/
34
35 #include "i40iw_osdep.h"
36 #include "i40iw_register.h"
37 #include "i40iw_status.h"
38 #include "i40iw_hmc.h"
39
40 #include "i40iw_d.h"
41 #include "i40iw_type.h"
42 #include "i40iw_p.h"
43 #include "i40iw_vf.h"
44 #include "i40iw_virtchnl.h"
45
46 /**
47 * i40iw_insert_wqe_hdr - write wqe header
48 * @wqe: cqp wqe for header
49 * @header: header for the cqp wqe
50 */
i40iw_insert_wqe_hdr(u64 * wqe,u64 header)51 void i40iw_insert_wqe_hdr(u64 *wqe, u64 header)
52 {
53 wmb(); /* make sure WQE is populated before polarity is set */
54 set_64bit_val(wqe, 24, header);
55 }
56
i40iw_check_cqp_progress(struct i40iw_cqp_timeout * cqp_timeout,struct i40iw_sc_dev * dev)57 void i40iw_check_cqp_progress(struct i40iw_cqp_timeout *cqp_timeout, struct i40iw_sc_dev *dev)
58 {
59 if (cqp_timeout->compl_cqp_cmds != dev->cqp_cmd_stats[OP_COMPLETED_COMMANDS]) {
60 cqp_timeout->compl_cqp_cmds = dev->cqp_cmd_stats[OP_COMPLETED_COMMANDS];
61 cqp_timeout->count = 0;
62 } else {
63 if (dev->cqp_cmd_stats[OP_REQUESTED_COMMANDS] != cqp_timeout->compl_cqp_cmds)
64 cqp_timeout->count++;
65 }
66 }
67
68 /**
69 * i40iw_get_cqp_reg_info - get head and tail for cqp using registers
70 * @cqp: struct for cqp hw
71 * @val: cqp tail register value
72 * @tail:wqtail register value
73 * @error: cqp processing err
74 */
i40iw_get_cqp_reg_info(struct i40iw_sc_cqp * cqp,u32 * val,u32 * tail,u32 * error)75 static inline void i40iw_get_cqp_reg_info(struct i40iw_sc_cqp *cqp,
76 u32 *val,
77 u32 *tail,
78 u32 *error)
79 {
80 if (cqp->dev->is_pf) {
81 *val = i40iw_rd32(cqp->dev->hw, I40E_PFPE_CQPTAIL);
82 *tail = RS_32(*val, I40E_PFPE_CQPTAIL_WQTAIL);
83 *error = RS_32(*val, I40E_PFPE_CQPTAIL_CQP_OP_ERR);
84 } else {
85 *val = i40iw_rd32(cqp->dev->hw, I40E_VFPE_CQPTAIL1);
86 *tail = RS_32(*val, I40E_VFPE_CQPTAIL_WQTAIL);
87 *error = RS_32(*val, I40E_VFPE_CQPTAIL_CQP_OP_ERR);
88 }
89 }
90
91 /**
92 * i40iw_cqp_poll_registers - poll cqp registers
93 * @cqp: struct for cqp hw
94 * @tail:wqtail register value
95 * @count: how many times to try for completion
96 */
i40iw_cqp_poll_registers(struct i40iw_sc_cqp * cqp,u32 tail,u32 count)97 static enum i40iw_status_code i40iw_cqp_poll_registers(
98 struct i40iw_sc_cqp *cqp,
99 u32 tail,
100 u32 count)
101 {
102 u32 i = 0;
103 u32 newtail, error, val;
104
105 while (i < count) {
106 i++;
107 i40iw_get_cqp_reg_info(cqp, &val, &newtail, &error);
108 if (error) {
109 error = (cqp->dev->is_pf) ?
110 i40iw_rd32(cqp->dev->hw, I40E_PFPE_CQPERRCODES) :
111 i40iw_rd32(cqp->dev->hw, I40E_VFPE_CQPERRCODES1);
112 return I40IW_ERR_CQP_COMPL_ERROR;
113 }
114 if (newtail != tail) {
115 /* SUCCESS */
116 I40IW_RING_MOVE_TAIL(cqp->sq_ring);
117 cqp->dev->cqp_cmd_stats[OP_COMPLETED_COMMANDS]++;
118 return 0;
119 }
120 udelay(I40IW_SLEEP_COUNT);
121 }
122 return I40IW_ERR_TIMEOUT;
123 }
124
125 /**
126 * i40iw_sc_parse_fpm_commit_buf - parse fpm commit buffer
127 * @buf: ptr to fpm commit buffer
128 * @info: ptr to i40iw_hmc_obj_info struct
129 * @sd: number of SDs for HMC objects
130 *
131 * parses fpm commit info and copy base value
132 * of hmc objects in hmc_info
133 */
i40iw_sc_parse_fpm_commit_buf(u64 * buf,struct i40iw_hmc_obj_info * info,u32 * sd)134 static enum i40iw_status_code i40iw_sc_parse_fpm_commit_buf(
135 u64 *buf,
136 struct i40iw_hmc_obj_info *info,
137 u32 *sd)
138 {
139 u64 temp;
140 u64 size;
141 u64 base = 0;
142 u32 i, j;
143 u32 k = 0;
144
145 /* copy base values in obj_info */
146 for (i = I40IW_HMC_IW_QP, j = 0; i <= I40IW_HMC_IW_PBLE; i++, j += 8) {
147 if ((i == I40IW_HMC_IW_SRQ) ||
148 (i == I40IW_HMC_IW_FSIMC) ||
149 (i == I40IW_HMC_IW_FSIAV)) {
150 info[i].base = 0;
151 info[i].cnt = 0;
152 continue;
153 }
154 get_64bit_val(buf, j, &temp);
155 info[i].base = RS_64_1(temp, 32) * 512;
156 if (info[i].base > base) {
157 base = info[i].base;
158 k = i;
159 }
160 if (i == I40IW_HMC_IW_APBVT_ENTRY) {
161 info[i].cnt = 1;
162 continue;
163 }
164 if (i == I40IW_HMC_IW_QP)
165 info[i].cnt = (u32)RS_64(temp, I40IW_QUERY_FPM_MAX_QPS);
166 else if (i == I40IW_HMC_IW_CQ)
167 info[i].cnt = (u32)RS_64(temp, I40IW_QUERY_FPM_MAX_CQS);
168 else
169 info[i].cnt = (u32)(temp);
170 }
171 size = info[k].cnt * info[k].size + info[k].base;
172 if (size & 0x1FFFFF)
173 *sd = (u32)((size >> 21) + 1); /* add 1 for remainder */
174 else
175 *sd = (u32)(size >> 21);
176
177 return 0;
178 }
179
180 /**
181 * i40iw_sc_decode_fpm_query() - Decode a 64 bit value into max count and size
182 * @buf: ptr to fpm query buffer
183 * @buf_idx: index into buf
184 * @obj_info: ptr to i40iw_hmc_obj_info struct
185 * @rsrc_idx: resource index into info
186 *
187 * Decode a 64 bit value from fpm query buffer into max count and size
188 */
i40iw_sc_decode_fpm_query(u64 * buf,u32 buf_idx,struct i40iw_hmc_obj_info * obj_info,u32 rsrc_idx)189 static u64 i40iw_sc_decode_fpm_query(u64 *buf,
190 u32 buf_idx,
191 struct i40iw_hmc_obj_info *obj_info,
192 u32 rsrc_idx)
193 {
194 u64 temp;
195 u32 size;
196
197 get_64bit_val(buf, buf_idx, &temp);
198 obj_info[rsrc_idx].max_cnt = (u32)temp;
199 size = (u32)RS_64_1(temp, 32);
200 obj_info[rsrc_idx].size = LS_64_1(1, size);
201
202 return temp;
203 }
204
205 /**
206 * i40iw_sc_parse_fpm_query_buf() - parses fpm query buffer
207 * @buf: ptr to fpm query buffer
208 * @hmc_info: ptr to i40iw_hmc_obj_info struct
209 * @hmc_fpm_misc: ptr to fpm data
210 *
211 * parses fpm query buffer and copy max_cnt and
212 * size value of hmc objects in hmc_info
213 */
i40iw_sc_parse_fpm_query_buf(u64 * buf,struct i40iw_hmc_info * hmc_info,struct i40iw_hmc_fpm_misc * hmc_fpm_misc)214 static enum i40iw_status_code i40iw_sc_parse_fpm_query_buf(
215 u64 *buf,
216 struct i40iw_hmc_info *hmc_info,
217 struct i40iw_hmc_fpm_misc *hmc_fpm_misc)
218 {
219 struct i40iw_hmc_obj_info *obj_info;
220 u64 temp;
221 u32 size;
222 u16 max_pe_sds;
223
224 obj_info = hmc_info->hmc_obj;
225
226 get_64bit_val(buf, 0, &temp);
227 hmc_info->first_sd_index = (u16)RS_64(temp, I40IW_QUERY_FPM_FIRST_PE_SD_INDEX);
228 max_pe_sds = (u16)RS_64(temp, I40IW_QUERY_FPM_MAX_PE_SDS);
229
230 /* Reduce SD count for VFs by 1 to account for PBLE backing page rounding */
231 if (hmc_info->hmc_fn_id >= I40IW_FIRST_VF_FPM_ID)
232 max_pe_sds--;
233 hmc_fpm_misc->max_sds = max_pe_sds;
234 hmc_info->sd_table.sd_cnt = max_pe_sds + hmc_info->first_sd_index;
235
236 get_64bit_val(buf, 8, &temp);
237 obj_info[I40IW_HMC_IW_QP].max_cnt = (u32)RS_64(temp, I40IW_QUERY_FPM_MAX_QPS);
238 size = (u32)RS_64_1(temp, 32);
239 obj_info[I40IW_HMC_IW_QP].size = LS_64_1(1, size);
240
241 get_64bit_val(buf, 16, &temp);
242 obj_info[I40IW_HMC_IW_CQ].max_cnt = (u32)RS_64(temp, I40IW_QUERY_FPM_MAX_CQS);
243 size = (u32)RS_64_1(temp, 32);
244 obj_info[I40IW_HMC_IW_CQ].size = LS_64_1(1, size);
245
246 i40iw_sc_decode_fpm_query(buf, 32, obj_info, I40IW_HMC_IW_HTE);
247 i40iw_sc_decode_fpm_query(buf, 40, obj_info, I40IW_HMC_IW_ARP);
248
249 obj_info[I40IW_HMC_IW_APBVT_ENTRY].size = 8192;
250 obj_info[I40IW_HMC_IW_APBVT_ENTRY].max_cnt = 1;
251
252 i40iw_sc_decode_fpm_query(buf, 48, obj_info, I40IW_HMC_IW_MR);
253 i40iw_sc_decode_fpm_query(buf, 56, obj_info, I40IW_HMC_IW_XF);
254
255 get_64bit_val(buf, 64, &temp);
256 obj_info[I40IW_HMC_IW_XFFL].max_cnt = (u32)temp;
257 obj_info[I40IW_HMC_IW_XFFL].size = 4;
258 hmc_fpm_misc->xf_block_size = RS_64(temp, I40IW_QUERY_FPM_XFBLOCKSIZE);
259 if (!hmc_fpm_misc->xf_block_size)
260 return I40IW_ERR_INVALID_SIZE;
261
262 i40iw_sc_decode_fpm_query(buf, 72, obj_info, I40IW_HMC_IW_Q1);
263
264 get_64bit_val(buf, 80, &temp);
265 obj_info[I40IW_HMC_IW_Q1FL].max_cnt = (u32)temp;
266 obj_info[I40IW_HMC_IW_Q1FL].size = 4;
267 hmc_fpm_misc->q1_block_size = RS_64(temp, I40IW_QUERY_FPM_Q1BLOCKSIZE);
268 if (!hmc_fpm_misc->q1_block_size)
269 return I40IW_ERR_INVALID_SIZE;
270
271 i40iw_sc_decode_fpm_query(buf, 88, obj_info, I40IW_HMC_IW_TIMER);
272
273 get_64bit_val(buf, 112, &temp);
274 obj_info[I40IW_HMC_IW_PBLE].max_cnt = (u32)temp;
275 obj_info[I40IW_HMC_IW_PBLE].size = 8;
276
277 get_64bit_val(buf, 120, &temp);
278 hmc_fpm_misc->max_ceqs = (u8)RS_64(temp, I40IW_QUERY_FPM_MAX_CEQS);
279 hmc_fpm_misc->ht_multiplier = RS_64(temp, I40IW_QUERY_FPM_HTMULTIPLIER);
280 hmc_fpm_misc->timer_bucket = RS_64(temp, I40IW_QUERY_FPM_TIMERBUCKET);
281
282 return 0;
283 }
284
285 /**
286 * i40iw_fill_qos_list - Change all unknown qs handles to available ones
287 * @qs_list: list of qs_handles to be fixed with valid qs_handles
288 */
i40iw_fill_qos_list(u16 * qs_list)289 static void i40iw_fill_qos_list(u16 *qs_list)
290 {
291 u16 qshandle = qs_list[0];
292 int i;
293
294 for (i = 0; i < I40IW_MAX_USER_PRIORITY; i++) {
295 if (qs_list[i] == QS_HANDLE_UNKNOWN)
296 qs_list[i] = qshandle;
297 else
298 qshandle = qs_list[i];
299 }
300 }
301
302 /**
303 * i40iw_qp_from_entry - Given entry, get to the qp structure
304 * @entry: Points to list of qp structure
305 */
i40iw_qp_from_entry(struct list_head * entry)306 static struct i40iw_sc_qp *i40iw_qp_from_entry(struct list_head *entry)
307 {
308 if (!entry)
309 return NULL;
310
311 return (struct i40iw_sc_qp *)((char *)entry - offsetof(struct i40iw_sc_qp, list));
312 }
313
314 /**
315 * i40iw_get_qp - get the next qp from the list given current qp
316 * @head: Listhead of qp's
317 * @qp: current qp
318 */
i40iw_get_qp(struct list_head * head,struct i40iw_sc_qp * qp)319 static struct i40iw_sc_qp *i40iw_get_qp(struct list_head *head, struct i40iw_sc_qp *qp)
320 {
321 struct list_head *entry = NULL;
322 struct list_head *lastentry;
323
324 if (list_empty(head))
325 return NULL;
326
327 if (!qp) {
328 entry = head->next;
329 } else {
330 lastentry = &qp->list;
331 entry = (lastentry != head) ? lastentry->next : NULL;
332 }
333
334 return i40iw_qp_from_entry(entry);
335 }
336
337 /**
338 * i40iw_change_l2params - given the new l2 parameters, change all qp
339 * @vsi: pointer to the vsi structure
340 * @l2params: New paramaters from l2
341 */
i40iw_change_l2params(struct i40iw_sc_vsi * vsi,struct i40iw_l2params * l2params)342 void i40iw_change_l2params(struct i40iw_sc_vsi *vsi, struct i40iw_l2params *l2params)
343 {
344 struct i40iw_sc_dev *dev = vsi->dev;
345 struct i40iw_sc_qp *qp = NULL;
346 bool qs_handle_change = false;
347 unsigned long flags;
348 u16 qs_handle;
349 int i;
350
351 if (vsi->mtu != l2params->mtu) {
352 vsi->mtu = l2params->mtu;
353 i40iw_reinitialize_ieq(dev);
354 }
355
356 i40iw_fill_qos_list(l2params->qs_handle_list);
357 for (i = 0; i < I40IW_MAX_USER_PRIORITY; i++) {
358 qs_handle = l2params->qs_handle_list[i];
359 if (vsi->qos[i].qs_handle != qs_handle)
360 qs_handle_change = true;
361 spin_lock_irqsave(&vsi->qos[i].lock, flags);
362 qp = i40iw_get_qp(&vsi->qos[i].qplist, qp);
363 while (qp) {
364 if (qs_handle_change) {
365 qp->qs_handle = qs_handle;
366 /* issue cqp suspend command */
367 i40iw_qp_suspend_resume(dev, qp, true);
368 }
369 qp = i40iw_get_qp(&vsi->qos[i].qplist, qp);
370 }
371 spin_unlock_irqrestore(&vsi->qos[i].lock, flags);
372 vsi->qos[i].qs_handle = qs_handle;
373 }
374 }
375
376 /**
377 * i40iw_qp_rem_qos - remove qp from qos lists during destroy qp
378 * @qp: qp to be removed from qos
379 */
i40iw_qp_rem_qos(struct i40iw_sc_qp * qp)380 void i40iw_qp_rem_qos(struct i40iw_sc_qp *qp)
381 {
382 struct i40iw_sc_vsi *vsi = qp->vsi;
383 unsigned long flags;
384
385 if (!qp->on_qoslist)
386 return;
387 spin_lock_irqsave(&vsi->qos[qp->user_pri].lock, flags);
388 list_del(&qp->list);
389 spin_unlock_irqrestore(&vsi->qos[qp->user_pri].lock, flags);
390 }
391
392 /**
393 * i40iw_qp_add_qos - called during setctx fot qp to be added to qos
394 * @qp: qp to be added to qos
395 */
i40iw_qp_add_qos(struct i40iw_sc_qp * qp)396 void i40iw_qp_add_qos(struct i40iw_sc_qp *qp)
397 {
398 struct i40iw_sc_vsi *vsi = qp->vsi;
399 unsigned long flags;
400
401 if (qp->on_qoslist)
402 return;
403 spin_lock_irqsave(&vsi->qos[qp->user_pri].lock, flags);
404 qp->qs_handle = vsi->qos[qp->user_pri].qs_handle;
405 list_add(&qp->list, &vsi->qos[qp->user_pri].qplist);
406 qp->on_qoslist = true;
407 spin_unlock_irqrestore(&vsi->qos[qp->user_pri].lock, flags);
408 }
409
410 /**
411 * i40iw_sc_pd_init - initialize sc pd struct
412 * @dev: sc device struct
413 * @pd: sc pd ptr
414 * @pd_id: pd_id for allocated pd
415 * @abi_ver: ABI version from user context, -1 if not valid
416 */
i40iw_sc_pd_init(struct i40iw_sc_dev * dev,struct i40iw_sc_pd * pd,u16 pd_id,int abi_ver)417 static void i40iw_sc_pd_init(struct i40iw_sc_dev *dev,
418 struct i40iw_sc_pd *pd,
419 u16 pd_id,
420 int abi_ver)
421 {
422 pd->size = sizeof(*pd);
423 pd->pd_id = pd_id;
424 pd->abi_ver = abi_ver;
425 pd->dev = dev;
426 }
427
428 /**
429 * i40iw_get_encoded_wqe_size - given wq size, returns hardware encoded size
430 * @wqsize: size of the wq (sq, rq, srq) to encoded_size
431 * @cqpsq: encoded size for sq for cqp as its encoded size is 1+ other wq's
432 */
i40iw_get_encoded_wqe_size(u32 wqsize,bool cqpsq)433 u8 i40iw_get_encoded_wqe_size(u32 wqsize, bool cqpsq)
434 {
435 u8 encoded_size = 0;
436
437 /* cqp sq's hw coded value starts from 1 for size of 4
438 * while it starts from 0 for qp' wq's.
439 */
440 if (cqpsq)
441 encoded_size = 1;
442 wqsize >>= 2;
443 while (wqsize >>= 1)
444 encoded_size++;
445 return encoded_size;
446 }
447
448 /**
449 * i40iw_sc_cqp_init - Initialize buffers for a control Queue Pair
450 * @cqp: IWARP control queue pair pointer
451 * @info: IWARP control queue pair init info pointer
452 *
453 * Initializes the object and context buffers for a control Queue Pair.
454 */
i40iw_sc_cqp_init(struct i40iw_sc_cqp * cqp,struct i40iw_cqp_init_info * info)455 static enum i40iw_status_code i40iw_sc_cqp_init(struct i40iw_sc_cqp *cqp,
456 struct i40iw_cqp_init_info *info)
457 {
458 u8 hw_sq_size;
459
460 if ((info->sq_size > I40IW_CQP_SW_SQSIZE_2048) ||
461 (info->sq_size < I40IW_CQP_SW_SQSIZE_4) ||
462 ((info->sq_size & (info->sq_size - 1))))
463 return I40IW_ERR_INVALID_SIZE;
464
465 hw_sq_size = i40iw_get_encoded_wqe_size(info->sq_size, true);
466 cqp->size = sizeof(*cqp);
467 cqp->sq_size = info->sq_size;
468 cqp->hw_sq_size = hw_sq_size;
469 cqp->sq_base = info->sq;
470 cqp->host_ctx = info->host_ctx;
471 cqp->sq_pa = info->sq_pa;
472 cqp->host_ctx_pa = info->host_ctx_pa;
473 cqp->dev = info->dev;
474 cqp->struct_ver = info->struct_ver;
475 cqp->scratch_array = info->scratch_array;
476 cqp->polarity = 0;
477 cqp->en_datacenter_tcp = info->en_datacenter_tcp;
478 cqp->enabled_vf_count = info->enabled_vf_count;
479 cqp->hmc_profile = info->hmc_profile;
480 info->dev->cqp = cqp;
481
482 I40IW_RING_INIT(cqp->sq_ring, cqp->sq_size);
483 cqp->dev->cqp_cmd_stats[OP_REQUESTED_COMMANDS] = 0;
484 cqp->dev->cqp_cmd_stats[OP_COMPLETED_COMMANDS] = 0;
485 INIT_LIST_HEAD(&cqp->dev->cqp_cmd_head); /* for the cqp commands backlog. */
486
487 i40iw_wr32(cqp->dev->hw, I40E_PFPE_CQPTAIL, 0);
488 i40iw_wr32(cqp->dev->hw, I40E_PFPE_CQPDB, 0);
489
490 i40iw_debug(cqp->dev, I40IW_DEBUG_WQE,
491 "%s: sq_size[%04d] hw_sq_size[%04d] sq_base[%p] sq_pa[%llxh] cqp[%p] polarity[x%04X]\n",
492 __func__, cqp->sq_size, cqp->hw_sq_size,
493 cqp->sq_base, cqp->sq_pa, cqp, cqp->polarity);
494 return 0;
495 }
496
497 /**
498 * i40iw_sc_cqp_create - create cqp during bringup
499 * @cqp: struct for cqp hw
500 * @maj_err: If error, major err number
501 * @min_err: If error, minor err number
502 */
i40iw_sc_cqp_create(struct i40iw_sc_cqp * cqp,u16 * maj_err,u16 * min_err)503 static enum i40iw_status_code i40iw_sc_cqp_create(struct i40iw_sc_cqp *cqp,
504 u16 *maj_err,
505 u16 *min_err)
506 {
507 u64 temp;
508 u32 cnt = 0, p1, p2, val = 0, err_code;
509 enum i40iw_status_code ret_code;
510
511 *maj_err = 0;
512 *min_err = 0;
513
514 ret_code = i40iw_allocate_dma_mem(cqp->dev->hw,
515 &cqp->sdbuf,
516 I40IW_UPDATE_SD_BUF_SIZE * cqp->sq_size,
517 I40IW_SD_BUF_ALIGNMENT);
518
519 if (ret_code)
520 goto exit;
521
522 temp = LS_64(cqp->hw_sq_size, I40IW_CQPHC_SQSIZE) |
523 LS_64(cqp->struct_ver, I40IW_CQPHC_SVER);
524
525 set_64bit_val(cqp->host_ctx, 0, temp);
526 set_64bit_val(cqp->host_ctx, 8, cqp->sq_pa);
527 temp = LS_64(cqp->enabled_vf_count, I40IW_CQPHC_ENABLED_VFS) |
528 LS_64(cqp->hmc_profile, I40IW_CQPHC_HMC_PROFILE);
529 set_64bit_val(cqp->host_ctx, 16, temp);
530 set_64bit_val(cqp->host_ctx, 24, (uintptr_t)cqp);
531 set_64bit_val(cqp->host_ctx, 32, 0);
532 set_64bit_val(cqp->host_ctx, 40, 0);
533 set_64bit_val(cqp->host_ctx, 48, 0);
534 set_64bit_val(cqp->host_ctx, 56, 0);
535
536 i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "CQP_HOST_CTX",
537 cqp->host_ctx, I40IW_CQP_CTX_SIZE * 8);
538
539 p1 = RS_32_1(cqp->host_ctx_pa, 32);
540 p2 = (u32)cqp->host_ctx_pa;
541
542 if (cqp->dev->is_pf) {
543 i40iw_wr32(cqp->dev->hw, I40E_PFPE_CCQPHIGH, p1);
544 i40iw_wr32(cqp->dev->hw, I40E_PFPE_CCQPLOW, p2);
545 } else {
546 i40iw_wr32(cqp->dev->hw, I40E_VFPE_CCQPHIGH1, p1);
547 i40iw_wr32(cqp->dev->hw, I40E_VFPE_CCQPLOW1, p2);
548 }
549 do {
550 if (cnt++ > I40IW_DONE_COUNT) {
551 i40iw_free_dma_mem(cqp->dev->hw, &cqp->sdbuf);
552 ret_code = I40IW_ERR_TIMEOUT;
553 /*
554 * read PFPE_CQPERRORCODES register to get the minor
555 * and major error code
556 */
557 if (cqp->dev->is_pf)
558 err_code = i40iw_rd32(cqp->dev->hw, I40E_PFPE_CQPERRCODES);
559 else
560 err_code = i40iw_rd32(cqp->dev->hw, I40E_VFPE_CQPERRCODES1);
561 *min_err = RS_32(err_code, I40E_PFPE_CQPERRCODES_CQP_MINOR_CODE);
562 *maj_err = RS_32(err_code, I40E_PFPE_CQPERRCODES_CQP_MAJOR_CODE);
563 goto exit;
564 }
565 udelay(I40IW_SLEEP_COUNT);
566 if (cqp->dev->is_pf)
567 val = i40iw_rd32(cqp->dev->hw, I40E_PFPE_CCQPSTATUS);
568 else
569 val = i40iw_rd32(cqp->dev->hw, I40E_VFPE_CCQPSTATUS1);
570 } while (!val);
571
572 exit:
573 if (!ret_code)
574 cqp->process_cqp_sds = i40iw_update_sds_noccq;
575 return ret_code;
576 }
577
578 /**
579 * i40iw_sc_cqp_post_sq - post of cqp's sq
580 * @cqp: struct for cqp hw
581 */
i40iw_sc_cqp_post_sq(struct i40iw_sc_cqp * cqp)582 void i40iw_sc_cqp_post_sq(struct i40iw_sc_cqp *cqp)
583 {
584 if (cqp->dev->is_pf)
585 i40iw_wr32(cqp->dev->hw, I40E_PFPE_CQPDB, I40IW_RING_GETCURRENT_HEAD(cqp->sq_ring));
586 else
587 i40iw_wr32(cqp->dev->hw, I40E_VFPE_CQPDB1, I40IW_RING_GETCURRENT_HEAD(cqp->sq_ring));
588
589 i40iw_debug(cqp->dev,
590 I40IW_DEBUG_WQE,
591 "%s: HEAD_TAIL[%04d,%04d,%04d]\n",
592 __func__,
593 cqp->sq_ring.head,
594 cqp->sq_ring.tail,
595 cqp->sq_ring.size);
596 }
597
598 /**
599 * i40iw_sc_cqp_get_next_send_wqe_idx - get next WQE on CQP SQ and pass back the index
600 * @cqp: pointer to CQP structure
601 * @scratch: private data for CQP WQE
602 * @wqe_idx: WQE index for next WQE on CQP SQ
603 */
i40iw_sc_cqp_get_next_send_wqe_idx(struct i40iw_sc_cqp * cqp,u64 scratch,u32 * wqe_idx)604 static u64 *i40iw_sc_cqp_get_next_send_wqe_idx(struct i40iw_sc_cqp *cqp,
605 u64 scratch, u32 *wqe_idx)
606 {
607 u64 *wqe = NULL;
608 enum i40iw_status_code ret_code;
609
610 if (I40IW_RING_FULL_ERR(cqp->sq_ring)) {
611 i40iw_debug(cqp->dev,
612 I40IW_DEBUG_WQE,
613 "%s: ring is full head %x tail %x size %x\n",
614 __func__,
615 cqp->sq_ring.head,
616 cqp->sq_ring.tail,
617 cqp->sq_ring.size);
618 return NULL;
619 }
620 I40IW_ATOMIC_RING_MOVE_HEAD(cqp->sq_ring, *wqe_idx, ret_code);
621 cqp->dev->cqp_cmd_stats[OP_REQUESTED_COMMANDS]++;
622 if (ret_code)
623 return NULL;
624 if (!*wqe_idx)
625 cqp->polarity = !cqp->polarity;
626
627 wqe = cqp->sq_base[*wqe_idx].elem;
628 cqp->scratch_array[*wqe_idx] = scratch;
629 I40IW_CQP_INIT_WQE(wqe);
630
631 return wqe;
632 }
633
634 /**
635 * i40iw_sc_cqp_get_next_send_wqe - get next wqe on cqp sq
636 * @cqp: struct for cqp hw
637 * @scratch: private data for CQP WQE
638 */
i40iw_sc_cqp_get_next_send_wqe(struct i40iw_sc_cqp * cqp,u64 scratch)639 u64 *i40iw_sc_cqp_get_next_send_wqe(struct i40iw_sc_cqp *cqp, u64 scratch)
640 {
641 u32 wqe_idx;
642
643 return i40iw_sc_cqp_get_next_send_wqe_idx(cqp, scratch, &wqe_idx);
644 }
645
646 /**
647 * i40iw_sc_cqp_destroy - destroy cqp during close
648 * @cqp: struct for cqp hw
649 */
i40iw_sc_cqp_destroy(struct i40iw_sc_cqp * cqp)650 static enum i40iw_status_code i40iw_sc_cqp_destroy(struct i40iw_sc_cqp *cqp)
651 {
652 u32 cnt = 0, val = 1;
653 enum i40iw_status_code ret_code = 0;
654 u32 cqpstat_addr;
655
656 if (cqp->dev->is_pf) {
657 i40iw_wr32(cqp->dev->hw, I40E_PFPE_CCQPHIGH, 0);
658 i40iw_wr32(cqp->dev->hw, I40E_PFPE_CCQPLOW, 0);
659 cqpstat_addr = I40E_PFPE_CCQPSTATUS;
660 } else {
661 i40iw_wr32(cqp->dev->hw, I40E_VFPE_CCQPHIGH1, 0);
662 i40iw_wr32(cqp->dev->hw, I40E_VFPE_CCQPLOW1, 0);
663 cqpstat_addr = I40E_VFPE_CCQPSTATUS1;
664 }
665 do {
666 if (cnt++ > I40IW_DONE_COUNT) {
667 ret_code = I40IW_ERR_TIMEOUT;
668 break;
669 }
670 udelay(I40IW_SLEEP_COUNT);
671 val = i40iw_rd32(cqp->dev->hw, cqpstat_addr);
672 } while (val);
673
674 i40iw_free_dma_mem(cqp->dev->hw, &cqp->sdbuf);
675 return ret_code;
676 }
677
678 /**
679 * i40iw_sc_ccq_arm - enable intr for control cq
680 * @ccq: ccq sc struct
681 */
i40iw_sc_ccq_arm(struct i40iw_sc_cq * ccq)682 static void i40iw_sc_ccq_arm(struct i40iw_sc_cq *ccq)
683 {
684 u64 temp_val;
685 u16 sw_cq_sel;
686 u8 arm_next_se;
687 u8 arm_seq_num;
688
689 /* write to cq doorbell shadow area */
690 /* arm next se should always be zero */
691 get_64bit_val(ccq->cq_uk.shadow_area, 32, &temp_val);
692
693 sw_cq_sel = (u16)RS_64(temp_val, I40IW_CQ_DBSA_SW_CQ_SELECT);
694 arm_next_se = (u8)RS_64(temp_val, I40IW_CQ_DBSA_ARM_NEXT_SE);
695
696 arm_seq_num = (u8)RS_64(temp_val, I40IW_CQ_DBSA_ARM_SEQ_NUM);
697 arm_seq_num++;
698
699 temp_val = LS_64(arm_seq_num, I40IW_CQ_DBSA_ARM_SEQ_NUM) |
700 LS_64(sw_cq_sel, I40IW_CQ_DBSA_SW_CQ_SELECT) |
701 LS_64(arm_next_se, I40IW_CQ_DBSA_ARM_NEXT_SE) |
702 LS_64(1, I40IW_CQ_DBSA_ARM_NEXT);
703
704 set_64bit_val(ccq->cq_uk.shadow_area, 32, temp_val);
705
706 wmb(); /* make sure shadow area is updated before arming */
707
708 if (ccq->dev->is_pf)
709 i40iw_wr32(ccq->dev->hw, I40E_PFPE_CQARM, ccq->cq_uk.cq_id);
710 else
711 i40iw_wr32(ccq->dev->hw, I40E_VFPE_CQARM1, ccq->cq_uk.cq_id);
712 }
713
714 /**
715 * i40iw_sc_ccq_get_cqe_info - get ccq's cq entry
716 * @ccq: ccq sc struct
717 * @info: completion q entry to return
718 */
i40iw_sc_ccq_get_cqe_info(struct i40iw_sc_cq * ccq,struct i40iw_ccq_cqe_info * info)719 static enum i40iw_status_code i40iw_sc_ccq_get_cqe_info(
720 struct i40iw_sc_cq *ccq,
721 struct i40iw_ccq_cqe_info *info)
722 {
723 u64 qp_ctx, temp, temp1;
724 u64 *cqe;
725 struct i40iw_sc_cqp *cqp;
726 u32 wqe_idx;
727 u8 polarity;
728 enum i40iw_status_code ret_code = 0;
729
730 if (ccq->cq_uk.avoid_mem_cflct)
731 cqe = (u64 *)I40IW_GET_CURRENT_EXTENDED_CQ_ELEMENT(&ccq->cq_uk);
732 else
733 cqe = (u64 *)I40IW_GET_CURRENT_CQ_ELEMENT(&ccq->cq_uk);
734
735 get_64bit_val(cqe, 24, &temp);
736 polarity = (u8)RS_64(temp, I40IW_CQ_VALID);
737 if (polarity != ccq->cq_uk.polarity)
738 return I40IW_ERR_QUEUE_EMPTY;
739
740 get_64bit_val(cqe, 8, &qp_ctx);
741 cqp = (struct i40iw_sc_cqp *)(unsigned long)qp_ctx;
742 info->error = (bool)RS_64(temp, I40IW_CQ_ERROR);
743 info->min_err_code = (u16)RS_64(temp, I40IW_CQ_MINERR);
744 if (info->error) {
745 info->maj_err_code = (u16)RS_64(temp, I40IW_CQ_MAJERR);
746 info->min_err_code = (u16)RS_64(temp, I40IW_CQ_MINERR);
747 }
748 wqe_idx = (u32)RS_64(temp, I40IW_CQ_WQEIDX);
749 info->scratch = cqp->scratch_array[wqe_idx];
750
751 get_64bit_val(cqe, 16, &temp1);
752 info->op_ret_val = (u32)RS_64(temp1, I40IW_CCQ_OPRETVAL);
753 get_64bit_val(cqp->sq_base[wqe_idx].elem, 24, &temp1);
754 info->op_code = (u8)RS_64(temp1, I40IW_CQPSQ_OPCODE);
755 info->cqp = cqp;
756
757 /* move the head for cq */
758 I40IW_RING_MOVE_HEAD(ccq->cq_uk.cq_ring, ret_code);
759 if (I40IW_RING_GETCURRENT_HEAD(ccq->cq_uk.cq_ring) == 0)
760 ccq->cq_uk.polarity ^= 1;
761
762 /* update cq tail in cq shadow memory also */
763 I40IW_RING_MOVE_TAIL(ccq->cq_uk.cq_ring);
764 set_64bit_val(ccq->cq_uk.shadow_area,
765 0,
766 I40IW_RING_GETCURRENT_HEAD(ccq->cq_uk.cq_ring));
767 wmb(); /* write shadow area before tail */
768 I40IW_RING_MOVE_TAIL(cqp->sq_ring);
769 ccq->dev->cqp_cmd_stats[OP_COMPLETED_COMMANDS]++;
770
771 return ret_code;
772 }
773
774 /**
775 * i40iw_sc_poll_for_cqp_op_done - Waits for last write to complete in CQP SQ
776 * @cqp: struct for cqp hw
777 * @op_code: cqp opcode for completion
778 * @compl_info: completion q entry to return
779 */
i40iw_sc_poll_for_cqp_op_done(struct i40iw_sc_cqp * cqp,u8 op_code,struct i40iw_ccq_cqe_info * compl_info)780 static enum i40iw_status_code i40iw_sc_poll_for_cqp_op_done(
781 struct i40iw_sc_cqp *cqp,
782 u8 op_code,
783 struct i40iw_ccq_cqe_info *compl_info)
784 {
785 struct i40iw_ccq_cqe_info info;
786 struct i40iw_sc_cq *ccq;
787 enum i40iw_status_code ret_code = 0;
788 u32 cnt = 0;
789
790 memset(&info, 0, sizeof(info));
791 ccq = cqp->dev->ccq;
792 while (1) {
793 if (cnt++ > I40IW_DONE_COUNT)
794 return I40IW_ERR_TIMEOUT;
795
796 if (i40iw_sc_ccq_get_cqe_info(ccq, &info)) {
797 udelay(I40IW_SLEEP_COUNT);
798 continue;
799 }
800
801 if (info.error) {
802 ret_code = I40IW_ERR_CQP_COMPL_ERROR;
803 break;
804 }
805 /* check if opcode is cq create */
806 if (op_code != info.op_code) {
807 i40iw_debug(cqp->dev, I40IW_DEBUG_WQE,
808 "%s: opcode mismatch for my op code 0x%x, returned opcode %x\n",
809 __func__, op_code, info.op_code);
810 }
811 /* success, exit out of the loop */
812 if (op_code == info.op_code)
813 break;
814 }
815
816 if (compl_info)
817 memcpy(compl_info, &info, sizeof(*compl_info));
818
819 return ret_code;
820 }
821
822 /**
823 * i40iw_sc_manage_hmc_pm_func_table - manage of function table
824 * @cqp: struct for cqp hw
825 * @scratch: u64 saved to be used during cqp completion
826 * @vf_index: vf index for cqp
827 * @free_pm_fcn: function number
828 * @post_sq: flag for cqp db to ring
829 */
i40iw_sc_manage_hmc_pm_func_table(struct i40iw_sc_cqp * cqp,u64 scratch,u8 vf_index,bool free_pm_fcn,bool post_sq)830 static enum i40iw_status_code i40iw_sc_manage_hmc_pm_func_table(
831 struct i40iw_sc_cqp *cqp,
832 u64 scratch,
833 u8 vf_index,
834 bool free_pm_fcn,
835 bool post_sq)
836 {
837 u64 *wqe;
838 u64 header;
839
840 if (vf_index >= I40IW_MAX_VF_PER_PF)
841 return I40IW_ERR_INVALID_VF_ID;
842 wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
843 if (!wqe)
844 return I40IW_ERR_RING_FULL;
845
846 header = LS_64(vf_index, I40IW_CQPSQ_MHMC_VFIDX) |
847 LS_64(I40IW_CQP_OP_MANAGE_HMC_PM_FUNC_TABLE, I40IW_CQPSQ_OPCODE) |
848 LS_64(free_pm_fcn, I40IW_CQPSQ_MHMC_FREEPMFN) |
849 LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
850
851 i40iw_insert_wqe_hdr(wqe, header);
852 i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "MANAGE_HMC_PM_FUNC_TABLE WQE",
853 wqe, I40IW_CQP_WQE_SIZE * 8);
854 if (post_sq)
855 i40iw_sc_cqp_post_sq(cqp);
856 return 0;
857 }
858
859 /**
860 * i40iw_sc_set_hmc_resource_profile - cqp wqe for hmc profile
861 * @cqp: struct for cqp hw
862 * @scratch: u64 saved to be used during cqp completion
863 * @hmc_profile_type: type of profile to set
864 * @vf_num: vf number for profile
865 * @post_sq: flag for cqp db to ring
866 * @poll_registers: flag to poll register for cqp completion
867 */
i40iw_sc_set_hmc_resource_profile(struct i40iw_sc_cqp * cqp,u64 scratch,u8 hmc_profile_type,u8 vf_num,bool post_sq,bool poll_registers)868 static enum i40iw_status_code i40iw_sc_set_hmc_resource_profile(
869 struct i40iw_sc_cqp *cqp,
870 u64 scratch,
871 u8 hmc_profile_type,
872 u8 vf_num, bool post_sq,
873 bool poll_registers)
874 {
875 u64 *wqe;
876 u64 header;
877 u32 val, tail, error;
878 enum i40iw_status_code ret_code = 0;
879
880 wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
881 if (!wqe)
882 return I40IW_ERR_RING_FULL;
883
884 set_64bit_val(wqe, 16,
885 (LS_64(hmc_profile_type, I40IW_CQPSQ_SHMCRP_HMC_PROFILE) |
886 LS_64(vf_num, I40IW_CQPSQ_SHMCRP_VFNUM)));
887
888 header = LS_64(I40IW_CQP_OP_SET_HMC_RESOURCE_PROFILE, I40IW_CQPSQ_OPCODE) |
889 LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
890
891 i40iw_insert_wqe_hdr(wqe, header);
892
893 i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "MANAGE_HMC_PM_FUNC_TABLE WQE",
894 wqe, I40IW_CQP_WQE_SIZE * 8);
895
896 i40iw_get_cqp_reg_info(cqp, &val, &tail, &error);
897 if (error)
898 return I40IW_ERR_CQP_COMPL_ERROR;
899
900 if (post_sq) {
901 i40iw_sc_cqp_post_sq(cqp);
902 if (poll_registers)
903 ret_code = i40iw_cqp_poll_registers(cqp, tail, 1000000);
904 else
905 ret_code = i40iw_sc_poll_for_cqp_op_done(cqp,
906 I40IW_CQP_OP_SHMC_PAGES_ALLOCATED,
907 NULL);
908 }
909
910 return ret_code;
911 }
912
913 /**
914 * i40iw_sc_manage_hmc_pm_func_table_done - wait for cqp wqe completion for function table
915 * @cqp: struct for cqp hw
916 */
i40iw_sc_manage_hmc_pm_func_table_done(struct i40iw_sc_cqp * cqp)917 static enum i40iw_status_code i40iw_sc_manage_hmc_pm_func_table_done(struct i40iw_sc_cqp *cqp)
918 {
919 return i40iw_sc_poll_for_cqp_op_done(cqp, I40IW_CQP_OP_MANAGE_HMC_PM_FUNC_TABLE, NULL);
920 }
921
922 /**
923 * i40iw_sc_commit_fpm_values_done - wait for cqp eqe completion for fpm commit
924 * @cqp: struct for cqp hw
925 */
i40iw_sc_commit_fpm_values_done(struct i40iw_sc_cqp * cqp)926 static enum i40iw_status_code i40iw_sc_commit_fpm_values_done(struct i40iw_sc_cqp *cqp)
927 {
928 return i40iw_sc_poll_for_cqp_op_done(cqp, I40IW_CQP_OP_COMMIT_FPM_VALUES, NULL);
929 }
930
931 /**
932 * i40iw_sc_commit_fpm_values - cqp wqe for commit fpm values
933 * @cqp: struct for cqp hw
934 * @scratch: u64 saved to be used during cqp completion
935 * @hmc_fn_id: hmc function id
936 * @commit_fpm_mem: Memory for fpm values
937 * @post_sq: flag for cqp db to ring
938 * @wait_type: poll ccq or cqp registers for cqp completion
939 */
i40iw_sc_commit_fpm_values(struct i40iw_sc_cqp * cqp,u64 scratch,u8 hmc_fn_id,struct i40iw_dma_mem * commit_fpm_mem,bool post_sq,u8 wait_type)940 static enum i40iw_status_code i40iw_sc_commit_fpm_values(
941 struct i40iw_sc_cqp *cqp,
942 u64 scratch,
943 u8 hmc_fn_id,
944 struct i40iw_dma_mem *commit_fpm_mem,
945 bool post_sq,
946 u8 wait_type)
947 {
948 u64 *wqe;
949 u64 header;
950 u32 tail, val, error;
951 enum i40iw_status_code ret_code = 0;
952
953 wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
954 if (!wqe)
955 return I40IW_ERR_RING_FULL;
956
957 set_64bit_val(wqe, 16, hmc_fn_id);
958 set_64bit_val(wqe, 32, commit_fpm_mem->pa);
959
960 header = LS_64(I40IW_CQP_OP_COMMIT_FPM_VALUES, I40IW_CQPSQ_OPCODE) |
961 LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
962
963 i40iw_insert_wqe_hdr(wqe, header);
964
965 i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "COMMIT_FPM_VALUES WQE",
966 wqe, I40IW_CQP_WQE_SIZE * 8);
967
968 i40iw_get_cqp_reg_info(cqp, &val, &tail, &error);
969 if (error)
970 return I40IW_ERR_CQP_COMPL_ERROR;
971
972 if (post_sq) {
973 i40iw_sc_cqp_post_sq(cqp);
974
975 if (wait_type == I40IW_CQP_WAIT_POLL_REGS)
976 ret_code = i40iw_cqp_poll_registers(cqp, tail, I40IW_DONE_COUNT);
977 else if (wait_type == I40IW_CQP_WAIT_POLL_CQ)
978 ret_code = i40iw_sc_commit_fpm_values_done(cqp);
979 }
980
981 return ret_code;
982 }
983
984 /**
985 * i40iw_sc_query_rdma_features_done - poll cqp for query features done
986 * @cqp: struct for cqp hw
987 */
988 static enum i40iw_status_code
i40iw_sc_query_rdma_features_done(struct i40iw_sc_cqp * cqp)989 i40iw_sc_query_rdma_features_done(struct i40iw_sc_cqp *cqp)
990 {
991 return i40iw_sc_poll_for_cqp_op_done(
992 cqp, I40IW_CQP_OP_QUERY_RDMA_FEATURES, NULL);
993 }
994
995 /**
996 * i40iw_sc_query_rdma_features - query rdma features
997 * @cqp: struct for cqp hw
998 * @feat_mem: holds PA for HW to use
999 * @scratch: u64 saved to be used during cqp completion
1000 */
1001 static enum i40iw_status_code
i40iw_sc_query_rdma_features(struct i40iw_sc_cqp * cqp,struct i40iw_dma_mem * feat_mem,u64 scratch)1002 i40iw_sc_query_rdma_features(struct i40iw_sc_cqp *cqp,
1003 struct i40iw_dma_mem *feat_mem, u64 scratch)
1004 {
1005 u64 *wqe;
1006 u64 header;
1007
1008 wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
1009 if (!wqe)
1010 return I40IW_ERR_RING_FULL;
1011
1012 set_64bit_val(wqe, 32, feat_mem->pa);
1013
1014 header = LS_64(I40IW_CQP_OP_QUERY_RDMA_FEATURES, I40IW_CQPSQ_OPCODE) |
1015 LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID) | feat_mem->size;
1016
1017 i40iw_insert_wqe_hdr(wqe, header);
1018
1019 i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "QUERY RDMA FEATURES WQE",
1020 wqe, I40IW_CQP_WQE_SIZE * 8);
1021
1022 i40iw_sc_cqp_post_sq(cqp);
1023
1024 return 0;
1025 }
1026
1027 /**
1028 * i40iw_get_rdma_features - get RDMA features
1029 * @dev: sc device struct
1030 */
i40iw_get_rdma_features(struct i40iw_sc_dev * dev)1031 enum i40iw_status_code i40iw_get_rdma_features(struct i40iw_sc_dev *dev)
1032 {
1033 enum i40iw_status_code ret_code;
1034 struct i40iw_dma_mem feat_buf;
1035 u64 temp;
1036 u16 byte_idx, feat_type, feat_cnt;
1037
1038 ret_code = i40iw_allocate_dma_mem(dev->hw, &feat_buf,
1039 I40IW_FEATURE_BUF_SIZE,
1040 I40IW_FEATURE_BUF_ALIGNMENT);
1041
1042 if (ret_code)
1043 return I40IW_ERR_NO_MEMORY;
1044
1045 ret_code = i40iw_sc_query_rdma_features(dev->cqp, &feat_buf, 0);
1046 if (!ret_code)
1047 ret_code = i40iw_sc_query_rdma_features_done(dev->cqp);
1048
1049 if (ret_code)
1050 goto exit;
1051
1052 get_64bit_val(feat_buf.va, 0, &temp);
1053 feat_cnt = RS_64(temp, I40IW_FEATURE_CNT);
1054 if (feat_cnt < I40IW_MAX_FEATURES) {
1055 ret_code = I40IW_ERR_INVALID_FEAT_CNT;
1056 goto exit;
1057 } else if (feat_cnt > I40IW_MAX_FEATURES) {
1058 i40iw_debug(dev, I40IW_DEBUG_CQP,
1059 "features buf size insufficient\n");
1060 }
1061
1062 for (byte_idx = 0, feat_type = 0; feat_type < I40IW_MAX_FEATURES;
1063 feat_type++, byte_idx += 8) {
1064 get_64bit_val((u64 *)feat_buf.va, byte_idx, &temp);
1065 dev->feature_info[feat_type] = RS_64(temp, I40IW_FEATURE_INFO);
1066 }
1067 exit:
1068 i40iw_free_dma_mem(dev->hw, &feat_buf);
1069
1070 return ret_code;
1071 }
1072
1073 /**
1074 * i40iw_sc_query_fpm_values_done - poll for cqp wqe completion for query fpm
1075 * @cqp: struct for cqp hw
1076 */
i40iw_sc_query_fpm_values_done(struct i40iw_sc_cqp * cqp)1077 static enum i40iw_status_code i40iw_sc_query_fpm_values_done(struct i40iw_sc_cqp *cqp)
1078 {
1079 return i40iw_sc_poll_for_cqp_op_done(cqp, I40IW_CQP_OP_QUERY_FPM_VALUES, NULL);
1080 }
1081
1082 /**
1083 * i40iw_sc_query_fpm_values - cqp wqe query fpm values
1084 * @cqp: struct for cqp hw
1085 * @scratch: u64 saved to be used during cqp completion
1086 * @hmc_fn_id: hmc function id
1087 * @query_fpm_mem: memory for return fpm values
1088 * @post_sq: flag for cqp db to ring
1089 * @wait_type: poll ccq or cqp registers for cqp completion
1090 */
i40iw_sc_query_fpm_values(struct i40iw_sc_cqp * cqp,u64 scratch,u8 hmc_fn_id,struct i40iw_dma_mem * query_fpm_mem,bool post_sq,u8 wait_type)1091 static enum i40iw_status_code i40iw_sc_query_fpm_values(
1092 struct i40iw_sc_cqp *cqp,
1093 u64 scratch,
1094 u8 hmc_fn_id,
1095 struct i40iw_dma_mem *query_fpm_mem,
1096 bool post_sq,
1097 u8 wait_type)
1098 {
1099 u64 *wqe;
1100 u64 header;
1101 u32 tail, val, error;
1102 enum i40iw_status_code ret_code = 0;
1103
1104 wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
1105 if (!wqe)
1106 return I40IW_ERR_RING_FULL;
1107
1108 set_64bit_val(wqe, 16, hmc_fn_id);
1109 set_64bit_val(wqe, 32, query_fpm_mem->pa);
1110
1111 header = LS_64(I40IW_CQP_OP_QUERY_FPM_VALUES, I40IW_CQPSQ_OPCODE) |
1112 LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
1113
1114 i40iw_insert_wqe_hdr(wqe, header);
1115
1116 i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "QUERY_FPM WQE",
1117 wqe, I40IW_CQP_WQE_SIZE * 8);
1118
1119 /* read the tail from CQP_TAIL register */
1120 i40iw_get_cqp_reg_info(cqp, &val, &tail, &error);
1121
1122 if (error)
1123 return I40IW_ERR_CQP_COMPL_ERROR;
1124
1125 if (post_sq) {
1126 i40iw_sc_cqp_post_sq(cqp);
1127 if (wait_type == I40IW_CQP_WAIT_POLL_REGS)
1128 ret_code = i40iw_cqp_poll_registers(cqp, tail, I40IW_DONE_COUNT);
1129 else if (wait_type == I40IW_CQP_WAIT_POLL_CQ)
1130 ret_code = i40iw_sc_query_fpm_values_done(cqp);
1131 }
1132
1133 return ret_code;
1134 }
1135
1136 /**
1137 * i40iw_sc_add_arp_cache_entry - cqp wqe add arp cache entry
1138 * @cqp: struct for cqp hw
1139 * @info: arp entry information
1140 * @scratch: u64 saved to be used during cqp completion
1141 * @post_sq: flag for cqp db to ring
1142 */
i40iw_sc_add_arp_cache_entry(struct i40iw_sc_cqp * cqp,struct i40iw_add_arp_cache_entry_info * info,u64 scratch,bool post_sq)1143 static enum i40iw_status_code i40iw_sc_add_arp_cache_entry(
1144 struct i40iw_sc_cqp *cqp,
1145 struct i40iw_add_arp_cache_entry_info *info,
1146 u64 scratch,
1147 bool post_sq)
1148 {
1149 u64 *wqe;
1150 u64 temp, header;
1151
1152 wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
1153 if (!wqe)
1154 return I40IW_ERR_RING_FULL;
1155 set_64bit_val(wqe, 8, info->reach_max);
1156
1157 temp = info->mac_addr[5] |
1158 LS_64_1(info->mac_addr[4], 8) |
1159 LS_64_1(info->mac_addr[3], 16) |
1160 LS_64_1(info->mac_addr[2], 24) |
1161 LS_64_1(info->mac_addr[1], 32) |
1162 LS_64_1(info->mac_addr[0], 40);
1163
1164 set_64bit_val(wqe, 16, temp);
1165
1166 header = info->arp_index |
1167 LS_64(I40IW_CQP_OP_MANAGE_ARP, I40IW_CQPSQ_OPCODE) |
1168 LS_64((info->permanent ? 1 : 0), I40IW_CQPSQ_MAT_PERMANENT) |
1169 LS_64(1, I40IW_CQPSQ_MAT_ENTRYVALID) |
1170 LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
1171
1172 i40iw_insert_wqe_hdr(wqe, header);
1173
1174 i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "ARP_CACHE_ENTRY WQE",
1175 wqe, I40IW_CQP_WQE_SIZE * 8);
1176
1177 if (post_sq)
1178 i40iw_sc_cqp_post_sq(cqp);
1179 return 0;
1180 }
1181
1182 /**
1183 * i40iw_sc_del_arp_cache_entry - dele arp cache entry
1184 * @cqp: struct for cqp hw
1185 * @scratch: u64 saved to be used during cqp completion
1186 * @arp_index: arp index to delete arp entry
1187 * @post_sq: flag for cqp db to ring
1188 */
i40iw_sc_del_arp_cache_entry(struct i40iw_sc_cqp * cqp,u64 scratch,u16 arp_index,bool post_sq)1189 static enum i40iw_status_code i40iw_sc_del_arp_cache_entry(
1190 struct i40iw_sc_cqp *cqp,
1191 u64 scratch,
1192 u16 arp_index,
1193 bool post_sq)
1194 {
1195 u64 *wqe;
1196 u64 header;
1197
1198 wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
1199 if (!wqe)
1200 return I40IW_ERR_RING_FULL;
1201
1202 header = arp_index |
1203 LS_64(I40IW_CQP_OP_MANAGE_ARP, I40IW_CQPSQ_OPCODE) |
1204 LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
1205 i40iw_insert_wqe_hdr(wqe, header);
1206
1207 i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "ARP_CACHE_DEL_ENTRY WQE",
1208 wqe, I40IW_CQP_WQE_SIZE * 8);
1209
1210 if (post_sq)
1211 i40iw_sc_cqp_post_sq(cqp);
1212 return 0;
1213 }
1214
1215 /**
1216 * i40iw_sc_query_arp_cache_entry - cqp wqe to query arp and arp index
1217 * @cqp: struct for cqp hw
1218 * @scratch: u64 saved to be used during cqp completion
1219 * @arp_index: arp index to delete arp entry
1220 * @post_sq: flag for cqp db to ring
1221 */
i40iw_sc_query_arp_cache_entry(struct i40iw_sc_cqp * cqp,u64 scratch,u16 arp_index,bool post_sq)1222 static enum i40iw_status_code i40iw_sc_query_arp_cache_entry(
1223 struct i40iw_sc_cqp *cqp,
1224 u64 scratch,
1225 u16 arp_index,
1226 bool post_sq)
1227 {
1228 u64 *wqe;
1229 u64 header;
1230
1231 wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
1232 if (!wqe)
1233 return I40IW_ERR_RING_FULL;
1234
1235 header = arp_index |
1236 LS_64(I40IW_CQP_OP_MANAGE_ARP, I40IW_CQPSQ_OPCODE) |
1237 LS_64(1, I40IW_CQPSQ_MAT_QUERY) |
1238 LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
1239
1240 i40iw_insert_wqe_hdr(wqe, header);
1241
1242 i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "QUERY_ARP_CACHE_ENTRY WQE",
1243 wqe, I40IW_CQP_WQE_SIZE * 8);
1244
1245 if (post_sq)
1246 i40iw_sc_cqp_post_sq(cqp);
1247 return 0;
1248 }
1249
1250 /**
1251 * i40iw_sc_manage_apbvt_entry - for adding and deleting apbvt entries
1252 * @cqp: struct for cqp hw
1253 * @info: info for apbvt entry to add or delete
1254 * @scratch: u64 saved to be used during cqp completion
1255 * @post_sq: flag for cqp db to ring
1256 */
i40iw_sc_manage_apbvt_entry(struct i40iw_sc_cqp * cqp,struct i40iw_apbvt_info * info,u64 scratch,bool post_sq)1257 static enum i40iw_status_code i40iw_sc_manage_apbvt_entry(
1258 struct i40iw_sc_cqp *cqp,
1259 struct i40iw_apbvt_info *info,
1260 u64 scratch,
1261 bool post_sq)
1262 {
1263 u64 *wqe;
1264 u64 header;
1265
1266 wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
1267 if (!wqe)
1268 return I40IW_ERR_RING_FULL;
1269
1270 set_64bit_val(wqe, 16, info->port);
1271
1272 header = LS_64(I40IW_CQP_OP_MANAGE_APBVT, I40IW_CQPSQ_OPCODE) |
1273 LS_64(info->add, I40IW_CQPSQ_MAPT_ADDPORT) |
1274 LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
1275
1276 i40iw_insert_wqe_hdr(wqe, header);
1277
1278 i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "MANAGE_APBVT WQE",
1279 wqe, I40IW_CQP_WQE_SIZE * 8);
1280
1281 if (post_sq)
1282 i40iw_sc_cqp_post_sq(cqp);
1283 return 0;
1284 }
1285
1286 /**
1287 * i40iw_sc_manage_qhash_table_entry - manage quad hash entries
1288 * @cqp: struct for cqp hw
1289 * @info: info for quad hash to manage
1290 * @scratch: u64 saved to be used during cqp completion
1291 * @post_sq: flag for cqp db to ring
1292 *
1293 * This is called before connection establishment is started. For passive connections, when
1294 * listener is created, it will call with entry type of I40IW_QHASH_TYPE_TCP_SYN with local
1295 * ip address and tcp port. When SYN is received (passive connections) or
1296 * sent (active connections), this routine is called with entry type of
1297 * I40IW_QHASH_TYPE_TCP_ESTABLISHED and quad is passed in info.
1298 *
1299 * When iwarp connection is done and its state moves to RTS, the quad hash entry in
1300 * the hardware will point to iwarp's qp number and requires no calls from the driver.
1301 */
i40iw_sc_manage_qhash_table_entry(struct i40iw_sc_cqp * cqp,struct i40iw_qhash_table_info * info,u64 scratch,bool post_sq)1302 static enum i40iw_status_code i40iw_sc_manage_qhash_table_entry(
1303 struct i40iw_sc_cqp *cqp,
1304 struct i40iw_qhash_table_info *info,
1305 u64 scratch,
1306 bool post_sq)
1307 {
1308 u64 *wqe;
1309 u64 qw1 = 0;
1310 u64 qw2 = 0;
1311 u64 temp;
1312 struct i40iw_sc_vsi *vsi = info->vsi;
1313
1314 wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
1315 if (!wqe)
1316 return I40IW_ERR_RING_FULL;
1317
1318 temp = info->mac_addr[5] |
1319 LS_64_1(info->mac_addr[4], 8) |
1320 LS_64_1(info->mac_addr[3], 16) |
1321 LS_64_1(info->mac_addr[2], 24) |
1322 LS_64_1(info->mac_addr[1], 32) |
1323 LS_64_1(info->mac_addr[0], 40);
1324
1325 set_64bit_val(wqe, 0, temp);
1326
1327 qw1 = LS_64(info->qp_num, I40IW_CQPSQ_QHASH_QPN) |
1328 LS_64(info->dest_port, I40IW_CQPSQ_QHASH_DEST_PORT);
1329 if (info->ipv4_valid) {
1330 set_64bit_val(wqe,
1331 48,
1332 LS_64(info->dest_ip[0], I40IW_CQPSQ_QHASH_ADDR3));
1333 } else {
1334 set_64bit_val(wqe,
1335 56,
1336 LS_64(info->dest_ip[0], I40IW_CQPSQ_QHASH_ADDR0) |
1337 LS_64(info->dest_ip[1], I40IW_CQPSQ_QHASH_ADDR1));
1338
1339 set_64bit_val(wqe,
1340 48,
1341 LS_64(info->dest_ip[2], I40IW_CQPSQ_QHASH_ADDR2) |
1342 LS_64(info->dest_ip[3], I40IW_CQPSQ_QHASH_ADDR3));
1343 }
1344 qw2 = LS_64(vsi->qos[info->user_pri].qs_handle, I40IW_CQPSQ_QHASH_QS_HANDLE);
1345 if (info->vlan_valid)
1346 qw2 |= LS_64(info->vlan_id, I40IW_CQPSQ_QHASH_VLANID);
1347 set_64bit_val(wqe, 16, qw2);
1348 if (info->entry_type == I40IW_QHASH_TYPE_TCP_ESTABLISHED) {
1349 qw1 |= LS_64(info->src_port, I40IW_CQPSQ_QHASH_SRC_PORT);
1350 if (!info->ipv4_valid) {
1351 set_64bit_val(wqe,
1352 40,
1353 LS_64(info->src_ip[0], I40IW_CQPSQ_QHASH_ADDR0) |
1354 LS_64(info->src_ip[1], I40IW_CQPSQ_QHASH_ADDR1));
1355 set_64bit_val(wqe,
1356 32,
1357 LS_64(info->src_ip[2], I40IW_CQPSQ_QHASH_ADDR2) |
1358 LS_64(info->src_ip[3], I40IW_CQPSQ_QHASH_ADDR3));
1359 } else {
1360 set_64bit_val(wqe,
1361 32,
1362 LS_64(info->src_ip[0], I40IW_CQPSQ_QHASH_ADDR3));
1363 }
1364 }
1365
1366 set_64bit_val(wqe, 8, qw1);
1367 temp = LS_64(cqp->polarity, I40IW_CQPSQ_QHASH_WQEVALID) |
1368 LS_64(I40IW_CQP_OP_MANAGE_QUAD_HASH_TABLE_ENTRY, I40IW_CQPSQ_QHASH_OPCODE) |
1369 LS_64(info->manage, I40IW_CQPSQ_QHASH_MANAGE) |
1370 LS_64(info->ipv4_valid, I40IW_CQPSQ_QHASH_IPV4VALID) |
1371 LS_64(info->vlan_valid, I40IW_CQPSQ_QHASH_VLANVALID) |
1372 LS_64(info->entry_type, I40IW_CQPSQ_QHASH_ENTRYTYPE);
1373
1374 i40iw_insert_wqe_hdr(wqe, temp);
1375
1376 i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "MANAGE_QHASH WQE",
1377 wqe, I40IW_CQP_WQE_SIZE * 8);
1378
1379 if (post_sq)
1380 i40iw_sc_cqp_post_sq(cqp);
1381 return 0;
1382 }
1383
1384 /**
1385 * i40iw_sc_alloc_local_mac_ipaddr_entry - cqp wqe for loc mac entry
1386 * @cqp: struct for cqp hw
1387 * @scratch: u64 saved to be used during cqp completion
1388 * @post_sq: flag for cqp db to ring
1389 */
i40iw_sc_alloc_local_mac_ipaddr_entry(struct i40iw_sc_cqp * cqp,u64 scratch,bool post_sq)1390 static enum i40iw_status_code i40iw_sc_alloc_local_mac_ipaddr_entry(
1391 struct i40iw_sc_cqp *cqp,
1392 u64 scratch,
1393 bool post_sq)
1394 {
1395 u64 *wqe;
1396 u64 header;
1397
1398 wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
1399 if (!wqe)
1400 return I40IW_ERR_RING_FULL;
1401 header = LS_64(I40IW_CQP_OP_ALLOCATE_LOC_MAC_IP_TABLE_ENTRY, I40IW_CQPSQ_OPCODE) |
1402 LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
1403
1404 i40iw_insert_wqe_hdr(wqe, header);
1405 i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "ALLOCATE_LOCAL_MAC_IPADDR WQE",
1406 wqe, I40IW_CQP_WQE_SIZE * 8);
1407 if (post_sq)
1408 i40iw_sc_cqp_post_sq(cqp);
1409 return 0;
1410 }
1411
1412 /**
1413 * i40iw_sc_add_local_mac_ipaddr_entry - add mac enry
1414 * @cqp: struct for cqp hw
1415 * @info:mac addr info
1416 * @scratch: u64 saved to be used during cqp completion
1417 * @post_sq: flag for cqp db to ring
1418 */
i40iw_sc_add_local_mac_ipaddr_entry(struct i40iw_sc_cqp * cqp,struct i40iw_local_mac_ipaddr_entry_info * info,u64 scratch,bool post_sq)1419 static enum i40iw_status_code i40iw_sc_add_local_mac_ipaddr_entry(
1420 struct i40iw_sc_cqp *cqp,
1421 struct i40iw_local_mac_ipaddr_entry_info *info,
1422 u64 scratch,
1423 bool post_sq)
1424 {
1425 u64 *wqe;
1426 u64 temp, header;
1427
1428 wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
1429 if (!wqe)
1430 return I40IW_ERR_RING_FULL;
1431 temp = info->mac_addr[5] |
1432 LS_64_1(info->mac_addr[4], 8) |
1433 LS_64_1(info->mac_addr[3], 16) |
1434 LS_64_1(info->mac_addr[2], 24) |
1435 LS_64_1(info->mac_addr[1], 32) |
1436 LS_64_1(info->mac_addr[0], 40);
1437
1438 set_64bit_val(wqe, 32, temp);
1439
1440 header = LS_64(info->entry_idx, I40IW_CQPSQ_MLIPA_IPTABLEIDX) |
1441 LS_64(I40IW_CQP_OP_MANAGE_LOC_MAC_IP_TABLE, I40IW_CQPSQ_OPCODE) |
1442 LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
1443
1444 i40iw_insert_wqe_hdr(wqe, header);
1445
1446 i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "ADD_LOCAL_MAC_IPADDR WQE",
1447 wqe, I40IW_CQP_WQE_SIZE * 8);
1448
1449 if (post_sq)
1450 i40iw_sc_cqp_post_sq(cqp);
1451 return 0;
1452 }
1453
1454 /**
1455 * i40iw_sc_del_local_mac_ipaddr_entry - cqp wqe to dele local mac
1456 * @cqp: struct for cqp hw
1457 * @scratch: u64 saved to be used during cqp completion
1458 * @entry_idx: index of mac entry
1459 * @ignore_ref_count: to force mac adde delete
1460 * @post_sq: flag for cqp db to ring
1461 */
i40iw_sc_del_local_mac_ipaddr_entry(struct i40iw_sc_cqp * cqp,u64 scratch,u8 entry_idx,u8 ignore_ref_count,bool post_sq)1462 static enum i40iw_status_code i40iw_sc_del_local_mac_ipaddr_entry(
1463 struct i40iw_sc_cqp *cqp,
1464 u64 scratch,
1465 u8 entry_idx,
1466 u8 ignore_ref_count,
1467 bool post_sq)
1468 {
1469 u64 *wqe;
1470 u64 header;
1471
1472 wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
1473 if (!wqe)
1474 return I40IW_ERR_RING_FULL;
1475 header = LS_64(entry_idx, I40IW_CQPSQ_MLIPA_IPTABLEIDX) |
1476 LS_64(I40IW_CQP_OP_MANAGE_LOC_MAC_IP_TABLE, I40IW_CQPSQ_OPCODE) |
1477 LS_64(1, I40IW_CQPSQ_MLIPA_FREEENTRY) |
1478 LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID) |
1479 LS_64(ignore_ref_count, I40IW_CQPSQ_MLIPA_IGNORE_REF_CNT);
1480
1481 i40iw_insert_wqe_hdr(wqe, header);
1482
1483 i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "DEL_LOCAL_MAC_IPADDR WQE",
1484 wqe, I40IW_CQP_WQE_SIZE * 8);
1485
1486 if (post_sq)
1487 i40iw_sc_cqp_post_sq(cqp);
1488 return 0;
1489 }
1490
1491 /**
1492 * i40iw_sc_cqp_nop - send a nop wqe
1493 * @cqp: struct for cqp hw
1494 * @scratch: u64 saved to be used during cqp completion
1495 * @post_sq: flag for cqp db to ring
1496 */
i40iw_sc_cqp_nop(struct i40iw_sc_cqp * cqp,u64 scratch,bool post_sq)1497 static enum i40iw_status_code i40iw_sc_cqp_nop(struct i40iw_sc_cqp *cqp,
1498 u64 scratch,
1499 bool post_sq)
1500 {
1501 u64 *wqe;
1502 u64 header;
1503
1504 wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
1505 if (!wqe)
1506 return I40IW_ERR_RING_FULL;
1507 header = LS_64(I40IW_CQP_OP_NOP, I40IW_CQPSQ_OPCODE) |
1508 LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
1509 i40iw_insert_wqe_hdr(wqe, header);
1510 i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "NOP WQE",
1511 wqe, I40IW_CQP_WQE_SIZE * 8);
1512
1513 if (post_sq)
1514 i40iw_sc_cqp_post_sq(cqp);
1515 return 0;
1516 }
1517
1518 /**
1519 * i40iw_sc_ceq_init - initialize ceq
1520 * @ceq: ceq sc structure
1521 * @info: ceq initialization info
1522 */
i40iw_sc_ceq_init(struct i40iw_sc_ceq * ceq,struct i40iw_ceq_init_info * info)1523 static enum i40iw_status_code i40iw_sc_ceq_init(struct i40iw_sc_ceq *ceq,
1524 struct i40iw_ceq_init_info *info)
1525 {
1526 u32 pble_obj_cnt;
1527
1528 if ((info->elem_cnt < I40IW_MIN_CEQ_ENTRIES) ||
1529 (info->elem_cnt > I40IW_MAX_CEQ_ENTRIES))
1530 return I40IW_ERR_INVALID_SIZE;
1531
1532 if (info->ceq_id >= I40IW_MAX_CEQID)
1533 return I40IW_ERR_INVALID_CEQ_ID;
1534
1535 pble_obj_cnt = info->dev->hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt;
1536
1537 if (info->virtual_map && (info->first_pm_pbl_idx >= pble_obj_cnt))
1538 return I40IW_ERR_INVALID_PBLE_INDEX;
1539
1540 ceq->size = sizeof(*ceq);
1541 ceq->ceqe_base = (struct i40iw_ceqe *)info->ceqe_base;
1542 ceq->ceq_id = info->ceq_id;
1543 ceq->dev = info->dev;
1544 ceq->elem_cnt = info->elem_cnt;
1545 ceq->ceq_elem_pa = info->ceqe_pa;
1546 ceq->virtual_map = info->virtual_map;
1547
1548 ceq->pbl_chunk_size = (ceq->virtual_map ? info->pbl_chunk_size : 0);
1549 ceq->first_pm_pbl_idx = (ceq->virtual_map ? info->first_pm_pbl_idx : 0);
1550 ceq->pbl_list = (ceq->virtual_map ? info->pbl_list : NULL);
1551
1552 ceq->tph_en = info->tph_en;
1553 ceq->tph_val = info->tph_val;
1554 ceq->polarity = 1;
1555 I40IW_RING_INIT(ceq->ceq_ring, ceq->elem_cnt);
1556 ceq->dev->ceq[info->ceq_id] = ceq;
1557
1558 return 0;
1559 }
1560
1561 /**
1562 * i40iw_sc_ceq_create - create ceq wqe
1563 * @ceq: ceq sc structure
1564 * @scratch: u64 saved to be used during cqp completion
1565 * @post_sq: flag for cqp db to ring
1566 */
i40iw_sc_ceq_create(struct i40iw_sc_ceq * ceq,u64 scratch,bool post_sq)1567 static enum i40iw_status_code i40iw_sc_ceq_create(struct i40iw_sc_ceq *ceq,
1568 u64 scratch,
1569 bool post_sq)
1570 {
1571 struct i40iw_sc_cqp *cqp;
1572 u64 *wqe;
1573 u64 header;
1574
1575 cqp = ceq->dev->cqp;
1576 wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
1577 if (!wqe)
1578 return I40IW_ERR_RING_FULL;
1579 set_64bit_val(wqe, 16, ceq->elem_cnt);
1580 set_64bit_val(wqe, 32, (ceq->virtual_map ? 0 : ceq->ceq_elem_pa));
1581 set_64bit_val(wqe, 48, (ceq->virtual_map ? ceq->first_pm_pbl_idx : 0));
1582 set_64bit_val(wqe, 56, LS_64(ceq->tph_val, I40IW_CQPSQ_TPHVAL));
1583
1584 header = ceq->ceq_id |
1585 LS_64(I40IW_CQP_OP_CREATE_CEQ, I40IW_CQPSQ_OPCODE) |
1586 LS_64(ceq->pbl_chunk_size, I40IW_CQPSQ_CEQ_LPBLSIZE) |
1587 LS_64(ceq->virtual_map, I40IW_CQPSQ_CEQ_VMAP) |
1588 LS_64(ceq->tph_en, I40IW_CQPSQ_TPHEN) |
1589 LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
1590
1591 i40iw_insert_wqe_hdr(wqe, header);
1592
1593 i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "CEQ_CREATE WQE",
1594 wqe, I40IW_CQP_WQE_SIZE * 8);
1595
1596 if (post_sq)
1597 i40iw_sc_cqp_post_sq(cqp);
1598 return 0;
1599 }
1600
1601 /**
1602 * i40iw_sc_cceq_create_done - poll for control ceq wqe to complete
1603 * @ceq: ceq sc structure
1604 */
i40iw_sc_cceq_create_done(struct i40iw_sc_ceq * ceq)1605 static enum i40iw_status_code i40iw_sc_cceq_create_done(struct i40iw_sc_ceq *ceq)
1606 {
1607 struct i40iw_sc_cqp *cqp;
1608
1609 cqp = ceq->dev->cqp;
1610 return i40iw_sc_poll_for_cqp_op_done(cqp, I40IW_CQP_OP_CREATE_CEQ, NULL);
1611 }
1612
1613 /**
1614 * i40iw_sc_cceq_destroy_done - poll for destroy cceq to complete
1615 * @ceq: ceq sc structure
1616 */
i40iw_sc_cceq_destroy_done(struct i40iw_sc_ceq * ceq)1617 static enum i40iw_status_code i40iw_sc_cceq_destroy_done(struct i40iw_sc_ceq *ceq)
1618 {
1619 struct i40iw_sc_cqp *cqp;
1620
1621 cqp = ceq->dev->cqp;
1622 cqp->process_cqp_sds = i40iw_update_sds_noccq;
1623 return i40iw_sc_poll_for_cqp_op_done(cqp, I40IW_CQP_OP_DESTROY_CEQ, NULL);
1624 }
1625
1626 /**
1627 * i40iw_sc_cceq_create - create cceq
1628 * @ceq: ceq sc structure
1629 * @scratch: u64 saved to be used during cqp completion
1630 */
i40iw_sc_cceq_create(struct i40iw_sc_ceq * ceq,u64 scratch)1631 static enum i40iw_status_code i40iw_sc_cceq_create(struct i40iw_sc_ceq *ceq, u64 scratch)
1632 {
1633 enum i40iw_status_code ret_code;
1634
1635 ret_code = i40iw_sc_ceq_create(ceq, scratch, true);
1636 if (!ret_code)
1637 ret_code = i40iw_sc_cceq_create_done(ceq);
1638 return ret_code;
1639 }
1640
1641 /**
1642 * i40iw_sc_ceq_destroy - destroy ceq
1643 * @ceq: ceq sc structure
1644 * @scratch: u64 saved to be used during cqp completion
1645 * @post_sq: flag for cqp db to ring
1646 */
i40iw_sc_ceq_destroy(struct i40iw_sc_ceq * ceq,u64 scratch,bool post_sq)1647 static enum i40iw_status_code i40iw_sc_ceq_destroy(struct i40iw_sc_ceq *ceq,
1648 u64 scratch,
1649 bool post_sq)
1650 {
1651 struct i40iw_sc_cqp *cqp;
1652 u64 *wqe;
1653 u64 header;
1654
1655 cqp = ceq->dev->cqp;
1656 wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
1657 if (!wqe)
1658 return I40IW_ERR_RING_FULL;
1659 set_64bit_val(wqe, 16, ceq->elem_cnt);
1660 set_64bit_val(wqe, 48, ceq->first_pm_pbl_idx);
1661 header = ceq->ceq_id |
1662 LS_64(I40IW_CQP_OP_DESTROY_CEQ, I40IW_CQPSQ_OPCODE) |
1663 LS_64(ceq->pbl_chunk_size, I40IW_CQPSQ_CEQ_LPBLSIZE) |
1664 LS_64(ceq->virtual_map, I40IW_CQPSQ_CEQ_VMAP) |
1665 LS_64(ceq->tph_en, I40IW_CQPSQ_TPHEN) |
1666 LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
1667 i40iw_insert_wqe_hdr(wqe, header);
1668 i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "CEQ_DESTROY WQE",
1669 wqe, I40IW_CQP_WQE_SIZE * 8);
1670
1671 if (post_sq)
1672 i40iw_sc_cqp_post_sq(cqp);
1673 return 0;
1674 }
1675
1676 /**
1677 * i40iw_sc_process_ceq - process ceq
1678 * @dev: sc device struct
1679 * @ceq: ceq sc structure
1680 */
i40iw_sc_process_ceq(struct i40iw_sc_dev * dev,struct i40iw_sc_ceq * ceq)1681 static void *i40iw_sc_process_ceq(struct i40iw_sc_dev *dev, struct i40iw_sc_ceq *ceq)
1682 {
1683 u64 temp;
1684 u64 *ceqe;
1685 struct i40iw_sc_cq *cq = NULL;
1686 u8 polarity;
1687
1688 ceqe = (u64 *)I40IW_GET_CURRENT_CEQ_ELEMENT(ceq);
1689 get_64bit_val(ceqe, 0, &temp);
1690 polarity = (u8)RS_64(temp, I40IW_CEQE_VALID);
1691 if (polarity != ceq->polarity)
1692 return cq;
1693
1694 cq = (struct i40iw_sc_cq *)(unsigned long)LS_64_1(temp, 1);
1695
1696 I40IW_RING_MOVE_TAIL(ceq->ceq_ring);
1697 if (I40IW_RING_GETCURRENT_TAIL(ceq->ceq_ring) == 0)
1698 ceq->polarity ^= 1;
1699
1700 if (dev->is_pf)
1701 i40iw_wr32(dev->hw, I40E_PFPE_CQACK, cq->cq_uk.cq_id);
1702 else
1703 i40iw_wr32(dev->hw, I40E_VFPE_CQACK1, cq->cq_uk.cq_id);
1704
1705 return cq;
1706 }
1707
1708 /**
1709 * i40iw_sc_aeq_init - initialize aeq
1710 * @aeq: aeq structure ptr
1711 * @info: aeq initialization info
1712 */
i40iw_sc_aeq_init(struct i40iw_sc_aeq * aeq,struct i40iw_aeq_init_info * info)1713 static enum i40iw_status_code i40iw_sc_aeq_init(struct i40iw_sc_aeq *aeq,
1714 struct i40iw_aeq_init_info *info)
1715 {
1716 u32 pble_obj_cnt;
1717
1718 if ((info->elem_cnt < I40IW_MIN_AEQ_ENTRIES) ||
1719 (info->elem_cnt > I40IW_MAX_AEQ_ENTRIES))
1720 return I40IW_ERR_INVALID_SIZE;
1721 pble_obj_cnt = info->dev->hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt;
1722
1723 if (info->virtual_map && (info->first_pm_pbl_idx >= pble_obj_cnt))
1724 return I40IW_ERR_INVALID_PBLE_INDEX;
1725
1726 aeq->size = sizeof(*aeq);
1727 aeq->polarity = 1;
1728 aeq->aeqe_base = (struct i40iw_sc_aeqe *)info->aeqe_base;
1729 aeq->dev = info->dev;
1730 aeq->elem_cnt = info->elem_cnt;
1731
1732 aeq->aeq_elem_pa = info->aeq_elem_pa;
1733 I40IW_RING_INIT(aeq->aeq_ring, aeq->elem_cnt);
1734 info->dev->aeq = aeq;
1735
1736 aeq->virtual_map = info->virtual_map;
1737 aeq->pbl_list = (aeq->virtual_map ? info->pbl_list : NULL);
1738 aeq->pbl_chunk_size = (aeq->virtual_map ? info->pbl_chunk_size : 0);
1739 aeq->first_pm_pbl_idx = (aeq->virtual_map ? info->first_pm_pbl_idx : 0);
1740 info->dev->aeq = aeq;
1741 return 0;
1742 }
1743
1744 /**
1745 * i40iw_sc_aeq_create - create aeq
1746 * @aeq: aeq structure ptr
1747 * @scratch: u64 saved to be used during cqp completion
1748 * @post_sq: flag for cqp db to ring
1749 */
i40iw_sc_aeq_create(struct i40iw_sc_aeq * aeq,u64 scratch,bool post_sq)1750 static enum i40iw_status_code i40iw_sc_aeq_create(struct i40iw_sc_aeq *aeq,
1751 u64 scratch,
1752 bool post_sq)
1753 {
1754 u64 *wqe;
1755 struct i40iw_sc_cqp *cqp;
1756 u64 header;
1757
1758 cqp = aeq->dev->cqp;
1759 wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
1760 if (!wqe)
1761 return I40IW_ERR_RING_FULL;
1762 set_64bit_val(wqe, 16, aeq->elem_cnt);
1763 set_64bit_val(wqe, 32,
1764 (aeq->virtual_map ? 0 : aeq->aeq_elem_pa));
1765 set_64bit_val(wqe, 48,
1766 (aeq->virtual_map ? aeq->first_pm_pbl_idx : 0));
1767
1768 header = LS_64(I40IW_CQP_OP_CREATE_AEQ, I40IW_CQPSQ_OPCODE) |
1769 LS_64(aeq->pbl_chunk_size, I40IW_CQPSQ_AEQ_LPBLSIZE) |
1770 LS_64(aeq->virtual_map, I40IW_CQPSQ_AEQ_VMAP) |
1771 LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
1772
1773 i40iw_insert_wqe_hdr(wqe, header);
1774 i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "AEQ_CREATE WQE",
1775 wqe, I40IW_CQP_WQE_SIZE * 8);
1776 if (post_sq)
1777 i40iw_sc_cqp_post_sq(cqp);
1778 return 0;
1779 }
1780
1781 /**
1782 * i40iw_sc_aeq_destroy - destroy aeq during close
1783 * @aeq: aeq structure ptr
1784 * @scratch: u64 saved to be used during cqp completion
1785 * @post_sq: flag for cqp db to ring
1786 */
i40iw_sc_aeq_destroy(struct i40iw_sc_aeq * aeq,u64 scratch,bool post_sq)1787 static enum i40iw_status_code i40iw_sc_aeq_destroy(struct i40iw_sc_aeq *aeq,
1788 u64 scratch,
1789 bool post_sq)
1790 {
1791 u64 *wqe;
1792 struct i40iw_sc_cqp *cqp;
1793 u64 header;
1794
1795 cqp = aeq->dev->cqp;
1796 wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
1797 if (!wqe)
1798 return I40IW_ERR_RING_FULL;
1799 set_64bit_val(wqe, 16, aeq->elem_cnt);
1800 set_64bit_val(wqe, 48, aeq->first_pm_pbl_idx);
1801 header = LS_64(I40IW_CQP_OP_DESTROY_AEQ, I40IW_CQPSQ_OPCODE) |
1802 LS_64(aeq->pbl_chunk_size, I40IW_CQPSQ_AEQ_LPBLSIZE) |
1803 LS_64(aeq->virtual_map, I40IW_CQPSQ_AEQ_VMAP) |
1804 LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
1805 i40iw_insert_wqe_hdr(wqe, header);
1806
1807 i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "AEQ_DESTROY WQE",
1808 wqe, I40IW_CQP_WQE_SIZE * 8);
1809 if (post_sq)
1810 i40iw_sc_cqp_post_sq(cqp);
1811 return 0;
1812 }
1813
1814 /**
1815 * i40iw_sc_get_next_aeqe - get next aeq entry
1816 * @aeq: aeq structure ptr
1817 * @info: aeqe info to be returned
1818 */
i40iw_sc_get_next_aeqe(struct i40iw_sc_aeq * aeq,struct i40iw_aeqe_info * info)1819 static enum i40iw_status_code i40iw_sc_get_next_aeqe(struct i40iw_sc_aeq *aeq,
1820 struct i40iw_aeqe_info *info)
1821 {
1822 u64 temp, compl_ctx;
1823 u64 *aeqe;
1824 u16 wqe_idx;
1825 u8 ae_src;
1826 u8 polarity;
1827
1828 aeqe = (u64 *)I40IW_GET_CURRENT_AEQ_ELEMENT(aeq);
1829 get_64bit_val(aeqe, 0, &compl_ctx);
1830 get_64bit_val(aeqe, 8, &temp);
1831 polarity = (u8)RS_64(temp, I40IW_AEQE_VALID);
1832
1833 if (aeq->polarity != polarity)
1834 return I40IW_ERR_QUEUE_EMPTY;
1835
1836 i40iw_debug_buf(aeq->dev, I40IW_DEBUG_WQE, "AEQ_ENTRY", aeqe, 16);
1837
1838 ae_src = (u8)RS_64(temp, I40IW_AEQE_AESRC);
1839 wqe_idx = (u16)RS_64(temp, I40IW_AEQE_WQDESCIDX);
1840 info->qp_cq_id = (u32)RS_64(temp, I40IW_AEQE_QPCQID);
1841 info->ae_id = (u16)RS_64(temp, I40IW_AEQE_AECODE);
1842 info->tcp_state = (u8)RS_64(temp, I40IW_AEQE_TCPSTATE);
1843 info->iwarp_state = (u8)RS_64(temp, I40IW_AEQE_IWSTATE);
1844 info->q2_data_written = (u8)RS_64(temp, I40IW_AEQE_Q2DATA);
1845 info->aeqe_overflow = (bool)RS_64(temp, I40IW_AEQE_OVERFLOW);
1846
1847 switch (info->ae_id) {
1848 case I40IW_AE_PRIV_OPERATION_DENIED:
1849 case I40IW_AE_UDA_XMIT_DGRAM_TOO_LONG:
1850 case I40IW_AE_UDA_XMIT_DGRAM_TOO_SHORT:
1851 case I40IW_AE_BAD_CLOSE:
1852 case I40IW_AE_RDMAP_ROE_BAD_LLP_CLOSE:
1853 case I40IW_AE_RDMA_READ_WHILE_ORD_ZERO:
1854 case I40IW_AE_STAG_ZERO_INVALID:
1855 case I40IW_AE_IB_RREQ_AND_Q1_FULL:
1856 case I40IW_AE_WQE_UNEXPECTED_OPCODE:
1857 case I40IW_AE_DDP_UBE_INVALID_DDP_VERSION:
1858 case I40IW_AE_DDP_UBE_INVALID_MO:
1859 case I40IW_AE_DDP_UBE_INVALID_QN:
1860 case I40IW_AE_DDP_NO_L_BIT:
1861 case I40IW_AE_RDMAP_ROE_INVALID_RDMAP_VERSION:
1862 case I40IW_AE_RDMAP_ROE_UNEXPECTED_OPCODE:
1863 case I40IW_AE_ROE_INVALID_RDMA_READ_REQUEST:
1864 case I40IW_AE_ROE_INVALID_RDMA_WRITE_OR_READ_RESP:
1865 case I40IW_AE_INVALID_ARP_ENTRY:
1866 case I40IW_AE_INVALID_TCP_OPTION_RCVD:
1867 case I40IW_AE_STALE_ARP_ENTRY:
1868 case I40IW_AE_LLP_CLOSE_COMPLETE:
1869 case I40IW_AE_LLP_CONNECTION_RESET:
1870 case I40IW_AE_LLP_FIN_RECEIVED:
1871 case I40IW_AE_LLP_RECEIVED_MPA_CRC_ERROR:
1872 case I40IW_AE_LLP_SEGMENT_TOO_SMALL:
1873 case I40IW_AE_LLP_SYN_RECEIVED:
1874 case I40IW_AE_LLP_TERMINATE_RECEIVED:
1875 case I40IW_AE_LLP_TOO_MANY_RETRIES:
1876 case I40IW_AE_LLP_DOUBT_REACHABILITY:
1877 case I40IW_AE_RESET_SENT:
1878 case I40IW_AE_TERMINATE_SENT:
1879 case I40IW_AE_RESET_NOT_SENT:
1880 case I40IW_AE_LCE_QP_CATASTROPHIC:
1881 case I40IW_AE_QP_SUSPEND_COMPLETE:
1882 info->qp = true;
1883 info->compl_ctx = compl_ctx;
1884 ae_src = I40IW_AE_SOURCE_RSVD;
1885 break;
1886 case I40IW_AE_LCE_CQ_CATASTROPHIC:
1887 info->cq = true;
1888 info->compl_ctx = LS_64_1(compl_ctx, 1);
1889 ae_src = I40IW_AE_SOURCE_RSVD;
1890 break;
1891 }
1892
1893 switch (ae_src) {
1894 case I40IW_AE_SOURCE_RQ:
1895 case I40IW_AE_SOURCE_RQ_0011:
1896 info->qp = true;
1897 info->wqe_idx = wqe_idx;
1898 info->compl_ctx = compl_ctx;
1899 break;
1900 case I40IW_AE_SOURCE_CQ:
1901 case I40IW_AE_SOURCE_CQ_0110:
1902 case I40IW_AE_SOURCE_CQ_1010:
1903 case I40IW_AE_SOURCE_CQ_1110:
1904 info->cq = true;
1905 info->compl_ctx = LS_64_1(compl_ctx, 1);
1906 break;
1907 case I40IW_AE_SOURCE_SQ:
1908 case I40IW_AE_SOURCE_SQ_0111:
1909 info->qp = true;
1910 info->sq = true;
1911 info->wqe_idx = wqe_idx;
1912 info->compl_ctx = compl_ctx;
1913 break;
1914 case I40IW_AE_SOURCE_IN_RR_WR:
1915 case I40IW_AE_SOURCE_IN_RR_WR_1011:
1916 info->qp = true;
1917 info->compl_ctx = compl_ctx;
1918 info->in_rdrsp_wr = true;
1919 break;
1920 case I40IW_AE_SOURCE_OUT_RR:
1921 case I40IW_AE_SOURCE_OUT_RR_1111:
1922 info->qp = true;
1923 info->compl_ctx = compl_ctx;
1924 info->out_rdrsp = true;
1925 break;
1926 case I40IW_AE_SOURCE_RSVD:
1927 default:
1928 break;
1929 }
1930 I40IW_RING_MOVE_TAIL(aeq->aeq_ring);
1931 if (I40IW_RING_GETCURRENT_TAIL(aeq->aeq_ring) == 0)
1932 aeq->polarity ^= 1;
1933 return 0;
1934 }
1935
1936 /**
1937 * i40iw_sc_repost_aeq_entries - repost completed aeq entries
1938 * @dev: sc device struct
1939 * @count: allocate count
1940 */
i40iw_sc_repost_aeq_entries(struct i40iw_sc_dev * dev,u32 count)1941 static enum i40iw_status_code i40iw_sc_repost_aeq_entries(struct i40iw_sc_dev *dev,
1942 u32 count)
1943 {
1944
1945 if (dev->is_pf)
1946 i40iw_wr32(dev->hw, I40E_PFPE_AEQALLOC, count);
1947 else
1948 i40iw_wr32(dev->hw, I40E_VFPE_AEQALLOC1, count);
1949
1950 return 0;
1951 }
1952
1953 /**
1954 * i40iw_sc_aeq_create_done - create aeq
1955 * @aeq: aeq structure ptr
1956 */
i40iw_sc_aeq_create_done(struct i40iw_sc_aeq * aeq)1957 static enum i40iw_status_code i40iw_sc_aeq_create_done(struct i40iw_sc_aeq *aeq)
1958 {
1959 struct i40iw_sc_cqp *cqp;
1960
1961 cqp = aeq->dev->cqp;
1962 return i40iw_sc_poll_for_cqp_op_done(cqp, I40IW_CQP_OP_CREATE_AEQ, NULL);
1963 }
1964
1965 /**
1966 * i40iw_sc_aeq_destroy_done - destroy of aeq during close
1967 * @aeq: aeq structure ptr
1968 */
i40iw_sc_aeq_destroy_done(struct i40iw_sc_aeq * aeq)1969 static enum i40iw_status_code i40iw_sc_aeq_destroy_done(struct i40iw_sc_aeq *aeq)
1970 {
1971 struct i40iw_sc_cqp *cqp;
1972
1973 cqp = aeq->dev->cqp;
1974 return i40iw_sc_poll_for_cqp_op_done(cqp, I40IW_CQP_OP_DESTROY_AEQ, NULL);
1975 }
1976
1977 /**
1978 * i40iw_sc_ccq_init - initialize control cq
1979 * @cq: sc's cq ctruct
1980 * @info: info for control cq initialization
1981 */
i40iw_sc_ccq_init(struct i40iw_sc_cq * cq,struct i40iw_ccq_init_info * info)1982 static enum i40iw_status_code i40iw_sc_ccq_init(struct i40iw_sc_cq *cq,
1983 struct i40iw_ccq_init_info *info)
1984 {
1985 u32 pble_obj_cnt;
1986
1987 if (info->num_elem < I40IW_MIN_CQ_SIZE || info->num_elem > I40IW_MAX_CQ_SIZE)
1988 return I40IW_ERR_INVALID_SIZE;
1989
1990 if (info->ceq_id > I40IW_MAX_CEQID)
1991 return I40IW_ERR_INVALID_CEQ_ID;
1992
1993 pble_obj_cnt = info->dev->hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt;
1994
1995 if (info->virtual_map && (info->first_pm_pbl_idx >= pble_obj_cnt))
1996 return I40IW_ERR_INVALID_PBLE_INDEX;
1997
1998 cq->cq_pa = info->cq_pa;
1999 cq->cq_uk.cq_base = info->cq_base;
2000 cq->shadow_area_pa = info->shadow_area_pa;
2001 cq->cq_uk.shadow_area = info->shadow_area;
2002 cq->shadow_read_threshold = info->shadow_read_threshold;
2003 cq->dev = info->dev;
2004 cq->ceq_id = info->ceq_id;
2005 cq->cq_uk.cq_size = info->num_elem;
2006 cq->cq_type = I40IW_CQ_TYPE_CQP;
2007 cq->ceqe_mask = info->ceqe_mask;
2008 I40IW_RING_INIT(cq->cq_uk.cq_ring, info->num_elem);
2009
2010 cq->cq_uk.cq_id = 0; /* control cq is id 0 always */
2011 cq->ceq_id_valid = info->ceq_id_valid;
2012 cq->tph_en = info->tph_en;
2013 cq->tph_val = info->tph_val;
2014 cq->cq_uk.avoid_mem_cflct = info->avoid_mem_cflct;
2015
2016 cq->pbl_list = info->pbl_list;
2017 cq->virtual_map = info->virtual_map;
2018 cq->pbl_chunk_size = info->pbl_chunk_size;
2019 cq->first_pm_pbl_idx = info->first_pm_pbl_idx;
2020 cq->cq_uk.polarity = true;
2021
2022 /* following are only for iw cqs so initialize them to zero */
2023 cq->cq_uk.cqe_alloc_reg = NULL;
2024 info->dev->ccq = cq;
2025 return 0;
2026 }
2027
2028 /**
2029 * i40iw_sc_ccq_create_done - poll cqp for ccq create
2030 * @ccq: ccq sc struct
2031 */
i40iw_sc_ccq_create_done(struct i40iw_sc_cq * ccq)2032 static enum i40iw_status_code i40iw_sc_ccq_create_done(struct i40iw_sc_cq *ccq)
2033 {
2034 struct i40iw_sc_cqp *cqp;
2035
2036 cqp = ccq->dev->cqp;
2037 return i40iw_sc_poll_for_cqp_op_done(cqp, I40IW_CQP_OP_CREATE_CQ, NULL);
2038 }
2039
2040 /**
2041 * i40iw_sc_ccq_create - create control cq
2042 * @ccq: ccq sc struct
2043 * @scratch: u64 saved to be used during cqp completion
2044 * @check_overflow: overlow flag for ccq
2045 * @post_sq: flag for cqp db to ring
2046 */
i40iw_sc_ccq_create(struct i40iw_sc_cq * ccq,u64 scratch,bool check_overflow,bool post_sq)2047 static enum i40iw_status_code i40iw_sc_ccq_create(struct i40iw_sc_cq *ccq,
2048 u64 scratch,
2049 bool check_overflow,
2050 bool post_sq)
2051 {
2052 u64 *wqe;
2053 struct i40iw_sc_cqp *cqp;
2054 u64 header;
2055 enum i40iw_status_code ret_code;
2056
2057 cqp = ccq->dev->cqp;
2058 wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
2059 if (!wqe)
2060 return I40IW_ERR_RING_FULL;
2061 set_64bit_val(wqe, 0, ccq->cq_uk.cq_size);
2062 set_64bit_val(wqe, 8, RS_64_1(ccq, 1));
2063 set_64bit_val(wqe, 16,
2064 LS_64(ccq->shadow_read_threshold, I40IW_CQPSQ_CQ_SHADOW_READ_THRESHOLD));
2065 set_64bit_val(wqe, 32, (ccq->virtual_map ? 0 : ccq->cq_pa));
2066 set_64bit_val(wqe, 40, ccq->shadow_area_pa);
2067 set_64bit_val(wqe, 48,
2068 (ccq->virtual_map ? ccq->first_pm_pbl_idx : 0));
2069 set_64bit_val(wqe, 56,
2070 LS_64(ccq->tph_val, I40IW_CQPSQ_TPHVAL));
2071
2072 header = ccq->cq_uk.cq_id |
2073 LS_64((ccq->ceq_id_valid ? ccq->ceq_id : 0), I40IW_CQPSQ_CQ_CEQID) |
2074 LS_64(I40IW_CQP_OP_CREATE_CQ, I40IW_CQPSQ_OPCODE) |
2075 LS_64(ccq->pbl_chunk_size, I40IW_CQPSQ_CQ_LPBLSIZE) |
2076 LS_64(check_overflow, I40IW_CQPSQ_CQ_CHKOVERFLOW) |
2077 LS_64(ccq->virtual_map, I40IW_CQPSQ_CQ_VIRTMAP) |
2078 LS_64(ccq->ceqe_mask, I40IW_CQPSQ_CQ_ENCEQEMASK) |
2079 LS_64(ccq->ceq_id_valid, I40IW_CQPSQ_CQ_CEQIDVALID) |
2080 LS_64(ccq->tph_en, I40IW_CQPSQ_TPHEN) |
2081 LS_64(ccq->cq_uk.avoid_mem_cflct, I40IW_CQPSQ_CQ_AVOIDMEMCNFLCT) |
2082 LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
2083
2084 i40iw_insert_wqe_hdr(wqe, header);
2085
2086 i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "CCQ_CREATE WQE",
2087 wqe, I40IW_CQP_WQE_SIZE * 8);
2088
2089 if (post_sq) {
2090 i40iw_sc_cqp_post_sq(cqp);
2091 ret_code = i40iw_sc_ccq_create_done(ccq);
2092 if (ret_code)
2093 return ret_code;
2094 }
2095 cqp->process_cqp_sds = i40iw_cqp_sds_cmd;
2096
2097 return 0;
2098 }
2099
2100 /**
2101 * i40iw_sc_ccq_destroy - destroy ccq during close
2102 * @ccq: ccq sc struct
2103 * @scratch: u64 saved to be used during cqp completion
2104 * @post_sq: flag for cqp db to ring
2105 */
i40iw_sc_ccq_destroy(struct i40iw_sc_cq * ccq,u64 scratch,bool post_sq)2106 static enum i40iw_status_code i40iw_sc_ccq_destroy(struct i40iw_sc_cq *ccq,
2107 u64 scratch,
2108 bool post_sq)
2109 {
2110 struct i40iw_sc_cqp *cqp;
2111 u64 *wqe;
2112 u64 header;
2113 enum i40iw_status_code ret_code = 0;
2114 u32 tail, val, error;
2115
2116 cqp = ccq->dev->cqp;
2117 wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
2118 if (!wqe)
2119 return I40IW_ERR_RING_FULL;
2120 set_64bit_val(wqe, 0, ccq->cq_uk.cq_size);
2121 set_64bit_val(wqe, 8, RS_64_1(ccq, 1));
2122 set_64bit_val(wqe, 40, ccq->shadow_area_pa);
2123
2124 header = ccq->cq_uk.cq_id |
2125 LS_64((ccq->ceq_id_valid ? ccq->ceq_id : 0), I40IW_CQPSQ_CQ_CEQID) |
2126 LS_64(I40IW_CQP_OP_DESTROY_CQ, I40IW_CQPSQ_OPCODE) |
2127 LS_64(ccq->ceqe_mask, I40IW_CQPSQ_CQ_ENCEQEMASK) |
2128 LS_64(ccq->ceq_id_valid, I40IW_CQPSQ_CQ_CEQIDVALID) |
2129 LS_64(ccq->tph_en, I40IW_CQPSQ_TPHEN) |
2130 LS_64(ccq->cq_uk.avoid_mem_cflct, I40IW_CQPSQ_CQ_AVOIDMEMCNFLCT) |
2131 LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
2132
2133 i40iw_insert_wqe_hdr(wqe, header);
2134
2135 i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "CCQ_DESTROY WQE",
2136 wqe, I40IW_CQP_WQE_SIZE * 8);
2137
2138 i40iw_get_cqp_reg_info(cqp, &val, &tail, &error);
2139 if (error)
2140 return I40IW_ERR_CQP_COMPL_ERROR;
2141
2142 if (post_sq) {
2143 i40iw_sc_cqp_post_sq(cqp);
2144 ret_code = i40iw_cqp_poll_registers(cqp, tail, 1000);
2145 }
2146
2147 cqp->process_cqp_sds = i40iw_update_sds_noccq;
2148
2149 return ret_code;
2150 }
2151
2152 /**
2153 * i40iw_sc_cq_init - initialize completion q
2154 * @cq: cq struct
2155 * @info: cq initialization info
2156 */
i40iw_sc_cq_init(struct i40iw_sc_cq * cq,struct i40iw_cq_init_info * info)2157 static enum i40iw_status_code i40iw_sc_cq_init(struct i40iw_sc_cq *cq,
2158 struct i40iw_cq_init_info *info)
2159 {
2160 u32 __iomem *cqe_alloc_reg = NULL;
2161 enum i40iw_status_code ret_code;
2162 u32 pble_obj_cnt;
2163 u32 arm_offset;
2164
2165 pble_obj_cnt = info->dev->hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt;
2166
2167 if (info->virtual_map && (info->first_pm_pbl_idx >= pble_obj_cnt))
2168 return I40IW_ERR_INVALID_PBLE_INDEX;
2169
2170 cq->cq_pa = info->cq_base_pa;
2171 cq->dev = info->dev;
2172 cq->ceq_id = info->ceq_id;
2173 arm_offset = (info->dev->is_pf) ? I40E_PFPE_CQARM : I40E_VFPE_CQARM1;
2174 if (i40iw_get_hw_addr(cq->dev))
2175 cqe_alloc_reg = (u32 __iomem *)(i40iw_get_hw_addr(cq->dev) +
2176 arm_offset);
2177 info->cq_uk_init_info.cqe_alloc_reg = cqe_alloc_reg;
2178 ret_code = i40iw_cq_uk_init(&cq->cq_uk, &info->cq_uk_init_info);
2179 if (ret_code)
2180 return ret_code;
2181 cq->virtual_map = info->virtual_map;
2182 cq->pbl_chunk_size = info->pbl_chunk_size;
2183 cq->ceqe_mask = info->ceqe_mask;
2184 cq->cq_type = (info->type) ? info->type : I40IW_CQ_TYPE_IWARP;
2185
2186 cq->shadow_area_pa = info->shadow_area_pa;
2187 cq->shadow_read_threshold = info->shadow_read_threshold;
2188
2189 cq->ceq_id_valid = info->ceq_id_valid;
2190 cq->tph_en = info->tph_en;
2191 cq->tph_val = info->tph_val;
2192
2193 cq->first_pm_pbl_idx = info->first_pm_pbl_idx;
2194
2195 return 0;
2196 }
2197
2198 /**
2199 * i40iw_sc_cq_create - create completion q
2200 * @cq: cq struct
2201 * @scratch: u64 saved to be used during cqp completion
2202 * @check_overflow: flag for overflow check
2203 * @post_sq: flag for cqp db to ring
2204 */
i40iw_sc_cq_create(struct i40iw_sc_cq * cq,u64 scratch,bool check_overflow,bool post_sq)2205 static enum i40iw_status_code i40iw_sc_cq_create(struct i40iw_sc_cq *cq,
2206 u64 scratch,
2207 bool check_overflow,
2208 bool post_sq)
2209 {
2210 u64 *wqe;
2211 struct i40iw_sc_cqp *cqp;
2212 u64 header;
2213
2214 if (cq->cq_uk.cq_id > I40IW_MAX_CQID)
2215 return I40IW_ERR_INVALID_CQ_ID;
2216
2217 if (cq->ceq_id > I40IW_MAX_CEQID)
2218 return I40IW_ERR_INVALID_CEQ_ID;
2219
2220 cqp = cq->dev->cqp;
2221 wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
2222 if (!wqe)
2223 return I40IW_ERR_RING_FULL;
2224
2225 set_64bit_val(wqe, 0, cq->cq_uk.cq_size);
2226 set_64bit_val(wqe, 8, RS_64_1(cq, 1));
2227 set_64bit_val(wqe,
2228 16,
2229 LS_64(cq->shadow_read_threshold, I40IW_CQPSQ_CQ_SHADOW_READ_THRESHOLD));
2230
2231 set_64bit_val(wqe, 32, (cq->virtual_map ? 0 : cq->cq_pa));
2232
2233 set_64bit_val(wqe, 40, cq->shadow_area_pa);
2234 set_64bit_val(wqe, 48, (cq->virtual_map ? cq->first_pm_pbl_idx : 0));
2235 set_64bit_val(wqe, 56, LS_64(cq->tph_val, I40IW_CQPSQ_TPHVAL));
2236
2237 header = cq->cq_uk.cq_id |
2238 LS_64((cq->ceq_id_valid ? cq->ceq_id : 0), I40IW_CQPSQ_CQ_CEQID) |
2239 LS_64(I40IW_CQP_OP_CREATE_CQ, I40IW_CQPSQ_OPCODE) |
2240 LS_64(cq->pbl_chunk_size, I40IW_CQPSQ_CQ_LPBLSIZE) |
2241 LS_64(check_overflow, I40IW_CQPSQ_CQ_CHKOVERFLOW) |
2242 LS_64(cq->virtual_map, I40IW_CQPSQ_CQ_VIRTMAP) |
2243 LS_64(cq->ceqe_mask, I40IW_CQPSQ_CQ_ENCEQEMASK) |
2244 LS_64(cq->ceq_id_valid, I40IW_CQPSQ_CQ_CEQIDVALID) |
2245 LS_64(cq->tph_en, I40IW_CQPSQ_TPHEN) |
2246 LS_64(cq->cq_uk.avoid_mem_cflct, I40IW_CQPSQ_CQ_AVOIDMEMCNFLCT) |
2247 LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
2248
2249 i40iw_insert_wqe_hdr(wqe, header);
2250
2251 i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "CQ_CREATE WQE",
2252 wqe, I40IW_CQP_WQE_SIZE * 8);
2253
2254 if (post_sq)
2255 i40iw_sc_cqp_post_sq(cqp);
2256 return 0;
2257 }
2258
2259 /**
2260 * i40iw_sc_cq_destroy - destroy completion q
2261 * @cq: cq struct
2262 * @scratch: u64 saved to be used during cqp completion
2263 * @post_sq: flag for cqp db to ring
2264 */
i40iw_sc_cq_destroy(struct i40iw_sc_cq * cq,u64 scratch,bool post_sq)2265 static enum i40iw_status_code i40iw_sc_cq_destroy(struct i40iw_sc_cq *cq,
2266 u64 scratch,
2267 bool post_sq)
2268 {
2269 struct i40iw_sc_cqp *cqp;
2270 u64 *wqe;
2271 u64 header;
2272
2273 cqp = cq->dev->cqp;
2274 wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
2275 if (!wqe)
2276 return I40IW_ERR_RING_FULL;
2277 set_64bit_val(wqe, 0, cq->cq_uk.cq_size);
2278 set_64bit_val(wqe, 8, RS_64_1(cq, 1));
2279 set_64bit_val(wqe, 40, cq->shadow_area_pa);
2280 set_64bit_val(wqe, 48, (cq->virtual_map ? cq->first_pm_pbl_idx : 0));
2281
2282 header = cq->cq_uk.cq_id |
2283 LS_64((cq->ceq_id_valid ? cq->ceq_id : 0), I40IW_CQPSQ_CQ_CEQID) |
2284 LS_64(I40IW_CQP_OP_DESTROY_CQ, I40IW_CQPSQ_OPCODE) |
2285 LS_64(cq->pbl_chunk_size, I40IW_CQPSQ_CQ_LPBLSIZE) |
2286 LS_64(cq->virtual_map, I40IW_CQPSQ_CQ_VIRTMAP) |
2287 LS_64(cq->ceqe_mask, I40IW_CQPSQ_CQ_ENCEQEMASK) |
2288 LS_64(cq->ceq_id_valid, I40IW_CQPSQ_CQ_CEQIDVALID) |
2289 LS_64(cq->tph_en, I40IW_CQPSQ_TPHEN) |
2290 LS_64(cq->cq_uk.avoid_mem_cflct, I40IW_CQPSQ_CQ_AVOIDMEMCNFLCT) |
2291 LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
2292
2293 i40iw_insert_wqe_hdr(wqe, header);
2294
2295 i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "CQ_DESTROY WQE",
2296 wqe, I40IW_CQP_WQE_SIZE * 8);
2297
2298 if (post_sq)
2299 i40iw_sc_cqp_post_sq(cqp);
2300 return 0;
2301 }
2302
2303 /**
2304 * i40iw_sc_cq_modify - modify a Completion Queue
2305 * @cq: cq struct
2306 * @info: modification info struct
2307 * @scratch: u64 saved to be used during cqp completion
2308 * @post_sq: flag to post to sq
2309 */
i40iw_sc_cq_modify(struct i40iw_sc_cq * cq,struct i40iw_modify_cq_info * info,u64 scratch,bool post_sq)2310 static enum i40iw_status_code i40iw_sc_cq_modify(struct i40iw_sc_cq *cq,
2311 struct i40iw_modify_cq_info *info,
2312 u64 scratch,
2313 bool post_sq)
2314 {
2315 struct i40iw_sc_cqp *cqp;
2316 u64 *wqe;
2317 u64 header;
2318 u32 cq_size, ceq_id, first_pm_pbl_idx;
2319 u8 pbl_chunk_size;
2320 bool virtual_map, ceq_id_valid, check_overflow;
2321 u32 pble_obj_cnt;
2322
2323 if (info->ceq_valid && (info->ceq_id > I40IW_MAX_CEQID))
2324 return I40IW_ERR_INVALID_CEQ_ID;
2325
2326 pble_obj_cnt = cq->dev->hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt;
2327
2328 if (info->cq_resize && info->virtual_map &&
2329 (info->first_pm_pbl_idx >= pble_obj_cnt))
2330 return I40IW_ERR_INVALID_PBLE_INDEX;
2331
2332 cqp = cq->dev->cqp;
2333 wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
2334 if (!wqe)
2335 return I40IW_ERR_RING_FULL;
2336
2337 cq->pbl_list = info->pbl_list;
2338 cq->cq_pa = info->cq_pa;
2339 cq->first_pm_pbl_idx = info->first_pm_pbl_idx;
2340
2341 cq_size = info->cq_resize ? info->cq_size : cq->cq_uk.cq_size;
2342 if (info->ceq_change) {
2343 ceq_id_valid = true;
2344 ceq_id = info->ceq_id;
2345 } else {
2346 ceq_id_valid = cq->ceq_id_valid;
2347 ceq_id = ceq_id_valid ? cq->ceq_id : 0;
2348 }
2349 virtual_map = info->cq_resize ? info->virtual_map : cq->virtual_map;
2350 first_pm_pbl_idx = (info->cq_resize ?
2351 (info->virtual_map ? info->first_pm_pbl_idx : 0) :
2352 (cq->virtual_map ? cq->first_pm_pbl_idx : 0));
2353 pbl_chunk_size = (info->cq_resize ?
2354 (info->virtual_map ? info->pbl_chunk_size : 0) :
2355 (cq->virtual_map ? cq->pbl_chunk_size : 0));
2356 check_overflow = info->check_overflow_change ? info->check_overflow :
2357 cq->check_overflow;
2358 cq->cq_uk.cq_size = cq_size;
2359 cq->ceq_id_valid = ceq_id_valid;
2360 cq->ceq_id = ceq_id;
2361 cq->virtual_map = virtual_map;
2362 cq->first_pm_pbl_idx = first_pm_pbl_idx;
2363 cq->pbl_chunk_size = pbl_chunk_size;
2364 cq->check_overflow = check_overflow;
2365
2366 set_64bit_val(wqe, 0, cq_size);
2367 set_64bit_val(wqe, 8, RS_64_1(cq, 1));
2368 set_64bit_val(wqe, 16,
2369 LS_64(info->shadow_read_threshold, I40IW_CQPSQ_CQ_SHADOW_READ_THRESHOLD));
2370 set_64bit_val(wqe, 32, (cq->virtual_map ? 0 : cq->cq_pa));
2371 set_64bit_val(wqe, 40, cq->shadow_area_pa);
2372 set_64bit_val(wqe, 48, (cq->virtual_map ? first_pm_pbl_idx : 0));
2373 set_64bit_val(wqe, 56, LS_64(cq->tph_val, I40IW_CQPSQ_TPHVAL));
2374
2375 header = cq->cq_uk.cq_id |
2376 LS_64(ceq_id, I40IW_CQPSQ_CQ_CEQID) |
2377 LS_64(I40IW_CQP_OP_MODIFY_CQ, I40IW_CQPSQ_OPCODE) |
2378 LS_64(info->cq_resize, I40IW_CQPSQ_CQ_CQRESIZE) |
2379 LS_64(pbl_chunk_size, I40IW_CQPSQ_CQ_LPBLSIZE) |
2380 LS_64(check_overflow, I40IW_CQPSQ_CQ_CHKOVERFLOW) |
2381 LS_64(virtual_map, I40IW_CQPSQ_CQ_VIRTMAP) |
2382 LS_64(cq->ceqe_mask, I40IW_CQPSQ_CQ_ENCEQEMASK) |
2383 LS_64(ceq_id_valid, I40IW_CQPSQ_CQ_CEQIDVALID) |
2384 LS_64(cq->tph_en, I40IW_CQPSQ_TPHEN) |
2385 LS_64(cq->cq_uk.avoid_mem_cflct, I40IW_CQPSQ_CQ_AVOIDMEMCNFLCT) |
2386 LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
2387
2388 i40iw_insert_wqe_hdr(wqe, header);
2389
2390 i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "CQ_MODIFY WQE",
2391 wqe, I40IW_CQP_WQE_SIZE * 8);
2392
2393 if (post_sq)
2394 i40iw_sc_cqp_post_sq(cqp);
2395 return 0;
2396 }
2397
2398 /**
2399 * i40iw_sc_qp_init - initialize qp
2400 * @qp: sc qp
2401 * @info: initialization qp info
2402 */
i40iw_sc_qp_init(struct i40iw_sc_qp * qp,struct i40iw_qp_init_info * info)2403 static enum i40iw_status_code i40iw_sc_qp_init(struct i40iw_sc_qp *qp,
2404 struct i40iw_qp_init_info *info)
2405 {
2406 u32 __iomem *wqe_alloc_reg = NULL;
2407 enum i40iw_status_code ret_code;
2408 u32 pble_obj_cnt;
2409 u8 wqe_size;
2410 u32 offset;
2411
2412 qp->dev = info->pd->dev;
2413 qp->vsi = info->vsi;
2414 qp->sq_pa = info->sq_pa;
2415 qp->rq_pa = info->rq_pa;
2416 qp->hw_host_ctx_pa = info->host_ctx_pa;
2417 qp->q2_pa = info->q2_pa;
2418 qp->shadow_area_pa = info->shadow_area_pa;
2419
2420 qp->q2_buf = info->q2;
2421 qp->pd = info->pd;
2422 qp->hw_host_ctx = info->host_ctx;
2423 offset = (qp->pd->dev->is_pf) ? I40E_PFPE_WQEALLOC : I40E_VFPE_WQEALLOC1;
2424 if (i40iw_get_hw_addr(qp->pd->dev))
2425 wqe_alloc_reg = (u32 __iomem *)(i40iw_get_hw_addr(qp->pd->dev) +
2426 offset);
2427
2428 info->qp_uk_init_info.wqe_alloc_reg = wqe_alloc_reg;
2429 info->qp_uk_init_info.abi_ver = qp->pd->abi_ver;
2430 ret_code = i40iw_qp_uk_init(&qp->qp_uk, &info->qp_uk_init_info);
2431 if (ret_code)
2432 return ret_code;
2433 qp->virtual_map = info->virtual_map;
2434
2435 pble_obj_cnt = info->pd->dev->hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt;
2436
2437 if ((info->virtual_map && (info->sq_pa >= pble_obj_cnt)) ||
2438 (info->virtual_map && (info->rq_pa >= pble_obj_cnt)))
2439 return I40IW_ERR_INVALID_PBLE_INDEX;
2440
2441 qp->llp_stream_handle = (void *)(-1);
2442 qp->qp_type = (info->type) ? info->type : I40IW_QP_TYPE_IWARP;
2443
2444 qp->hw_sq_size = i40iw_get_encoded_wqe_size(qp->qp_uk.sq_ring.size,
2445 false);
2446 i40iw_debug(qp->dev, I40IW_DEBUG_WQE, "%s: hw_sq_size[%04d] sq_ring.size[%04d]\n",
2447 __func__, qp->hw_sq_size, qp->qp_uk.sq_ring.size);
2448
2449 switch (qp->pd->abi_ver) {
2450 case 4:
2451 ret_code = i40iw_fragcnt_to_wqesize_rq(qp->qp_uk.max_rq_frag_cnt,
2452 &wqe_size);
2453 if (ret_code)
2454 return ret_code;
2455 break;
2456 case 5: /* fallthrough until next ABI version */
2457 default:
2458 if (qp->qp_uk.max_rq_frag_cnt > I40IW_MAX_WQ_FRAGMENT_COUNT)
2459 return I40IW_ERR_INVALID_FRAG_COUNT;
2460 wqe_size = I40IW_MAX_WQE_SIZE_RQ;
2461 break;
2462 }
2463 qp->hw_rq_size = i40iw_get_encoded_wqe_size(qp->qp_uk.rq_size *
2464 (wqe_size / I40IW_QP_WQE_MIN_SIZE), false);
2465 i40iw_debug(qp->dev, I40IW_DEBUG_WQE,
2466 "%s: hw_rq_size[%04d] qp_uk.rq_size[%04d] wqe_size[%04d]\n",
2467 __func__, qp->hw_rq_size, qp->qp_uk.rq_size, wqe_size);
2468 qp->sq_tph_val = info->sq_tph_val;
2469 qp->rq_tph_val = info->rq_tph_val;
2470 qp->sq_tph_en = info->sq_tph_en;
2471 qp->rq_tph_en = info->rq_tph_en;
2472 qp->rcv_tph_en = info->rcv_tph_en;
2473 qp->xmit_tph_en = info->xmit_tph_en;
2474 qp->qs_handle = qp->vsi->qos[qp->user_pri].qs_handle;
2475
2476 return 0;
2477 }
2478
2479 /**
2480 * i40iw_sc_qp_create - create qp
2481 * @qp: sc qp
2482 * @info: qp create info
2483 * @scratch: u64 saved to be used during cqp completion
2484 * @post_sq: flag for cqp db to ring
2485 */
i40iw_sc_qp_create(struct i40iw_sc_qp * qp,struct i40iw_create_qp_info * info,u64 scratch,bool post_sq)2486 static enum i40iw_status_code i40iw_sc_qp_create(
2487 struct i40iw_sc_qp *qp,
2488 struct i40iw_create_qp_info *info,
2489 u64 scratch,
2490 bool post_sq)
2491 {
2492 struct i40iw_sc_cqp *cqp;
2493 u64 *wqe;
2494 u64 header;
2495
2496 if ((qp->qp_uk.qp_id < I40IW_MIN_IW_QP_ID) ||
2497 (qp->qp_uk.qp_id > I40IW_MAX_IW_QP_ID))
2498 return I40IW_ERR_INVALID_QP_ID;
2499
2500 cqp = qp->pd->dev->cqp;
2501 wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
2502 if (!wqe)
2503 return I40IW_ERR_RING_FULL;
2504
2505 set_64bit_val(wqe, 16, qp->hw_host_ctx_pa);
2506
2507 set_64bit_val(wqe, 40, qp->shadow_area_pa);
2508
2509 header = qp->qp_uk.qp_id |
2510 LS_64(I40IW_CQP_OP_CREATE_QP, I40IW_CQPSQ_OPCODE) |
2511 LS_64((info->ord_valid ? 1 : 0), I40IW_CQPSQ_QP_ORDVALID) |
2512 LS_64(info->tcp_ctx_valid, I40IW_CQPSQ_QP_TOECTXVALID) |
2513 LS_64(qp->qp_type, I40IW_CQPSQ_QP_QPTYPE) |
2514 LS_64(qp->virtual_map, I40IW_CQPSQ_QP_VQ) |
2515 LS_64(info->cq_num_valid, I40IW_CQPSQ_QP_CQNUMVALID) |
2516 LS_64(info->arp_cache_idx_valid, I40IW_CQPSQ_QP_ARPTABIDXVALID) |
2517 LS_64(info->next_iwarp_state, I40IW_CQPSQ_QP_NEXTIWSTATE) |
2518 LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
2519
2520 i40iw_insert_wqe_hdr(wqe, header);
2521 i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "QP_CREATE WQE",
2522 wqe, I40IW_CQP_WQE_SIZE * 8);
2523
2524 if (post_sq)
2525 i40iw_sc_cqp_post_sq(cqp);
2526 return 0;
2527 }
2528
2529 /**
2530 * i40iw_sc_qp_modify - modify qp cqp wqe
2531 * @qp: sc qp
2532 * @info: modify qp info
2533 * @scratch: u64 saved to be used during cqp completion
2534 * @post_sq: flag for cqp db to ring
2535 */
i40iw_sc_qp_modify(struct i40iw_sc_qp * qp,struct i40iw_modify_qp_info * info,u64 scratch,bool post_sq)2536 static enum i40iw_status_code i40iw_sc_qp_modify(
2537 struct i40iw_sc_qp *qp,
2538 struct i40iw_modify_qp_info *info,
2539 u64 scratch,
2540 bool post_sq)
2541 {
2542 u64 *wqe;
2543 struct i40iw_sc_cqp *cqp;
2544 u64 header;
2545 u8 term_actions = 0;
2546 u8 term_len = 0;
2547
2548 cqp = qp->pd->dev->cqp;
2549 wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
2550 if (!wqe)
2551 return I40IW_ERR_RING_FULL;
2552 if (info->next_iwarp_state == I40IW_QP_STATE_TERMINATE) {
2553 if (info->dont_send_fin)
2554 term_actions += I40IWQP_TERM_SEND_TERM_ONLY;
2555 if (info->dont_send_term)
2556 term_actions += I40IWQP_TERM_SEND_FIN_ONLY;
2557 if ((term_actions == I40IWQP_TERM_SEND_TERM_AND_FIN) ||
2558 (term_actions == I40IWQP_TERM_SEND_TERM_ONLY))
2559 term_len = info->termlen;
2560 }
2561
2562 set_64bit_val(wqe,
2563 8,
2564 LS_64(term_len, I40IW_CQPSQ_QP_TERMLEN));
2565
2566 set_64bit_val(wqe, 16, qp->hw_host_ctx_pa);
2567 set_64bit_val(wqe, 40, qp->shadow_area_pa);
2568
2569 header = qp->qp_uk.qp_id |
2570 LS_64(I40IW_CQP_OP_MODIFY_QP, I40IW_CQPSQ_OPCODE) |
2571 LS_64(info->ord_valid, I40IW_CQPSQ_QP_ORDVALID) |
2572 LS_64(info->tcp_ctx_valid, I40IW_CQPSQ_QP_TOECTXVALID) |
2573 LS_64(info->cached_var_valid, I40IW_CQPSQ_QP_CACHEDVARVALID) |
2574 LS_64(qp->virtual_map, I40IW_CQPSQ_QP_VQ) |
2575 LS_64(info->cq_num_valid, I40IW_CQPSQ_QP_CQNUMVALID) |
2576 LS_64(info->force_loopback, I40IW_CQPSQ_QP_FORCELOOPBACK) |
2577 LS_64(qp->qp_type, I40IW_CQPSQ_QP_QPTYPE) |
2578 LS_64(info->remove_hash_idx, I40IW_CQPSQ_QP_REMOVEHASHENTRY) |
2579 LS_64(term_actions, I40IW_CQPSQ_QP_TERMACT) |
2580 LS_64(info->reset_tcp_conn, I40IW_CQPSQ_QP_RESETCON) |
2581 LS_64(info->arp_cache_idx_valid, I40IW_CQPSQ_QP_ARPTABIDXVALID) |
2582 LS_64(info->next_iwarp_state, I40IW_CQPSQ_QP_NEXTIWSTATE) |
2583 LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
2584
2585 i40iw_insert_wqe_hdr(wqe, header);
2586
2587 i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "QP_MODIFY WQE",
2588 wqe, I40IW_CQP_WQE_SIZE * 8);
2589
2590 if (post_sq)
2591 i40iw_sc_cqp_post_sq(cqp);
2592 return 0;
2593 }
2594
2595 /**
2596 * i40iw_sc_qp_destroy - cqp destroy qp
2597 * @qp: sc qp
2598 * @scratch: u64 saved to be used during cqp completion
2599 * @remove_hash_idx: flag if to remove hash idx
2600 * @ignore_mw_bnd: memory window bind flag
2601 * @post_sq: flag for cqp db to ring
2602 */
i40iw_sc_qp_destroy(struct i40iw_sc_qp * qp,u64 scratch,bool remove_hash_idx,bool ignore_mw_bnd,bool post_sq)2603 static enum i40iw_status_code i40iw_sc_qp_destroy(
2604 struct i40iw_sc_qp *qp,
2605 u64 scratch,
2606 bool remove_hash_idx,
2607 bool ignore_mw_bnd,
2608 bool post_sq)
2609 {
2610 u64 *wqe;
2611 struct i40iw_sc_cqp *cqp;
2612 u64 header;
2613
2614 i40iw_qp_rem_qos(qp);
2615 cqp = qp->pd->dev->cqp;
2616 wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
2617 if (!wqe)
2618 return I40IW_ERR_RING_FULL;
2619 set_64bit_val(wqe, 16, qp->hw_host_ctx_pa);
2620 set_64bit_val(wqe, 40, qp->shadow_area_pa);
2621
2622 header = qp->qp_uk.qp_id |
2623 LS_64(I40IW_CQP_OP_DESTROY_QP, I40IW_CQPSQ_OPCODE) |
2624 LS_64(qp->qp_type, I40IW_CQPSQ_QP_QPTYPE) |
2625 LS_64(ignore_mw_bnd, I40IW_CQPSQ_QP_IGNOREMWBOUND) |
2626 LS_64(remove_hash_idx, I40IW_CQPSQ_QP_REMOVEHASHENTRY) |
2627 LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
2628
2629 i40iw_insert_wqe_hdr(wqe, header);
2630 i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "QP_DESTROY WQE",
2631 wqe, I40IW_CQP_WQE_SIZE * 8);
2632
2633 if (post_sq)
2634 i40iw_sc_cqp_post_sq(cqp);
2635 return 0;
2636 }
2637
2638 /**
2639 * i40iw_sc_qp_flush_wqes - flush qp's wqe
2640 * @qp: sc qp
2641 * @info: dlush information
2642 * @scratch: u64 saved to be used during cqp completion
2643 * @post_sq: flag for cqp db to ring
2644 */
i40iw_sc_qp_flush_wqes(struct i40iw_sc_qp * qp,struct i40iw_qp_flush_info * info,u64 scratch,bool post_sq)2645 static enum i40iw_status_code i40iw_sc_qp_flush_wqes(
2646 struct i40iw_sc_qp *qp,
2647 struct i40iw_qp_flush_info *info,
2648 u64 scratch,
2649 bool post_sq)
2650 {
2651 u64 temp = 0;
2652 u64 *wqe;
2653 struct i40iw_sc_cqp *cqp;
2654 u64 header;
2655 bool flush_sq = false, flush_rq = false;
2656
2657 if (info->rq && !qp->flush_rq)
2658 flush_rq = true;
2659
2660 if (info->sq && !qp->flush_sq)
2661 flush_sq = true;
2662
2663 qp->flush_sq |= flush_sq;
2664 qp->flush_rq |= flush_rq;
2665 if (!flush_sq && !flush_rq)
2666 return 0;
2667
2668 cqp = qp->pd->dev->cqp;
2669 wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
2670 if (!wqe)
2671 return I40IW_ERR_RING_FULL;
2672 if (info->userflushcode) {
2673 if (flush_rq) {
2674 temp |= LS_64(info->rq_minor_code, I40IW_CQPSQ_FWQE_RQMNERR) |
2675 LS_64(info->rq_major_code, I40IW_CQPSQ_FWQE_RQMJERR);
2676 }
2677 if (flush_sq) {
2678 temp |= LS_64(info->sq_minor_code, I40IW_CQPSQ_FWQE_SQMNERR) |
2679 LS_64(info->sq_major_code, I40IW_CQPSQ_FWQE_SQMJERR);
2680 }
2681 }
2682 set_64bit_val(wqe, 16, temp);
2683
2684 temp = (info->generate_ae) ?
2685 info->ae_code | LS_64(info->ae_source, I40IW_CQPSQ_FWQE_AESOURCE) : 0;
2686
2687 set_64bit_val(wqe, 8, temp);
2688
2689 header = qp->qp_uk.qp_id |
2690 LS_64(I40IW_CQP_OP_FLUSH_WQES, I40IW_CQPSQ_OPCODE) |
2691 LS_64(info->generate_ae, I40IW_CQPSQ_FWQE_GENERATE_AE) |
2692 LS_64(info->userflushcode, I40IW_CQPSQ_FWQE_USERFLCODE) |
2693 LS_64(flush_sq, I40IW_CQPSQ_FWQE_FLUSHSQ) |
2694 LS_64(flush_rq, I40IW_CQPSQ_FWQE_FLUSHRQ) |
2695 LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
2696
2697 i40iw_insert_wqe_hdr(wqe, header);
2698
2699 i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "QP_FLUSH WQE",
2700 wqe, I40IW_CQP_WQE_SIZE * 8);
2701
2702 if (post_sq)
2703 i40iw_sc_cqp_post_sq(cqp);
2704 return 0;
2705 }
2706
2707 /**
2708 * i40iw_sc_gen_ae - generate AE, currently uses flush WQE CQP OP
2709 * @qp: sc qp
2710 * @info: gen ae information
2711 * @scratch: u64 saved to be used during cqp completion
2712 * @post_sq: flag for cqp db to ring
2713 */
i40iw_sc_gen_ae(struct i40iw_sc_qp * qp,struct i40iw_gen_ae_info * info,u64 scratch,bool post_sq)2714 static enum i40iw_status_code i40iw_sc_gen_ae(
2715 struct i40iw_sc_qp *qp,
2716 struct i40iw_gen_ae_info *info,
2717 u64 scratch,
2718 bool post_sq)
2719 {
2720 u64 temp;
2721 u64 *wqe;
2722 struct i40iw_sc_cqp *cqp;
2723 u64 header;
2724
2725 cqp = qp->pd->dev->cqp;
2726 wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
2727 if (!wqe)
2728 return I40IW_ERR_RING_FULL;
2729
2730 temp = info->ae_code |
2731 LS_64(info->ae_source, I40IW_CQPSQ_FWQE_AESOURCE);
2732
2733 set_64bit_val(wqe, 8, temp);
2734
2735 header = qp->qp_uk.qp_id |
2736 LS_64(I40IW_CQP_OP_GEN_AE, I40IW_CQPSQ_OPCODE) |
2737 LS_64(1, I40IW_CQPSQ_FWQE_GENERATE_AE) |
2738 LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
2739
2740 i40iw_insert_wqe_hdr(wqe, header);
2741
2742 i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "GEN_AE WQE",
2743 wqe, I40IW_CQP_WQE_SIZE * 8);
2744
2745 if (post_sq)
2746 i40iw_sc_cqp_post_sq(cqp);
2747 return 0;
2748 }
2749
2750 /**
2751 * i40iw_sc_qp_upload_context - upload qp's context
2752 * @dev: sc device struct
2753 * @info: upload context info ptr for return
2754 * @scratch: u64 saved to be used during cqp completion
2755 * @post_sq: flag for cqp db to ring
2756 */
i40iw_sc_qp_upload_context(struct i40iw_sc_dev * dev,struct i40iw_upload_context_info * info,u64 scratch,bool post_sq)2757 static enum i40iw_status_code i40iw_sc_qp_upload_context(
2758 struct i40iw_sc_dev *dev,
2759 struct i40iw_upload_context_info *info,
2760 u64 scratch,
2761 bool post_sq)
2762 {
2763 u64 *wqe;
2764 struct i40iw_sc_cqp *cqp;
2765 u64 header;
2766
2767 cqp = dev->cqp;
2768 wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
2769 if (!wqe)
2770 return I40IW_ERR_RING_FULL;
2771 set_64bit_val(wqe, 16, info->buf_pa);
2772
2773 header = LS_64(info->qp_id, I40IW_CQPSQ_UCTX_QPID) |
2774 LS_64(I40IW_CQP_OP_UPLOAD_CONTEXT, I40IW_CQPSQ_OPCODE) |
2775 LS_64(info->qp_type, I40IW_CQPSQ_UCTX_QPTYPE) |
2776 LS_64(info->raw_format, I40IW_CQPSQ_UCTX_RAWFORMAT) |
2777 LS_64(info->freeze_qp, I40IW_CQPSQ_UCTX_FREEZEQP) |
2778 LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
2779
2780 i40iw_insert_wqe_hdr(wqe, header);
2781
2782 i40iw_debug_buf(dev, I40IW_DEBUG_WQE, "QP_UPLOAD_CTX WQE",
2783 wqe, I40IW_CQP_WQE_SIZE * 8);
2784
2785 if (post_sq)
2786 i40iw_sc_cqp_post_sq(cqp);
2787 return 0;
2788 }
2789
2790 /**
2791 * i40iw_sc_qp_setctx - set qp's context
2792 * @qp: sc qp
2793 * @qp_ctx: context ptr
2794 * @info: ctx info
2795 */
i40iw_sc_qp_setctx(struct i40iw_sc_qp * qp,u64 * qp_ctx,struct i40iw_qp_host_ctx_info * info)2796 static enum i40iw_status_code i40iw_sc_qp_setctx(
2797 struct i40iw_sc_qp *qp,
2798 u64 *qp_ctx,
2799 struct i40iw_qp_host_ctx_info *info)
2800 {
2801 struct i40iwarp_offload_info *iw;
2802 struct i40iw_tcp_offload_info *tcp;
2803 struct i40iw_sc_vsi *vsi;
2804 struct i40iw_sc_dev *dev;
2805 u64 qw0, qw3, qw7 = 0;
2806
2807 iw = info->iwarp_info;
2808 tcp = info->tcp_info;
2809 vsi = qp->vsi;
2810 dev = qp->dev;
2811 if (info->add_to_qoslist) {
2812 qp->user_pri = info->user_pri;
2813 i40iw_qp_add_qos(qp);
2814 i40iw_debug(qp->dev, I40IW_DEBUG_DCB, "%s qp[%d] UP[%d] qset[%d]\n",
2815 __func__, qp->qp_uk.qp_id, qp->user_pri, qp->qs_handle);
2816 }
2817 qw0 = LS_64(qp->qp_uk.rq_wqe_size, I40IWQPC_RQWQESIZE) |
2818 LS_64(info->err_rq_idx_valid, I40IWQPC_ERR_RQ_IDX_VALID) |
2819 LS_64(qp->rcv_tph_en, I40IWQPC_RCVTPHEN) |
2820 LS_64(qp->xmit_tph_en, I40IWQPC_XMITTPHEN) |
2821 LS_64(qp->rq_tph_en, I40IWQPC_RQTPHEN) |
2822 LS_64(qp->sq_tph_en, I40IWQPC_SQTPHEN);
2823
2824 set_64bit_val(qp_ctx, 8, qp->sq_pa);
2825 set_64bit_val(qp_ctx, 16, qp->rq_pa);
2826
2827 qw3 = LS_64(qp->src_mac_addr_idx, I40IWQPC_SRCMACADDRIDX) |
2828 LS_64(qp->hw_rq_size, I40IWQPC_RQSIZE) |
2829 LS_64(qp->hw_sq_size, I40IWQPC_SQSIZE);
2830
2831 set_64bit_val(qp_ctx,
2832 128,
2833 LS_64(info->err_rq_idx, I40IWQPC_ERR_RQ_IDX));
2834
2835 set_64bit_val(qp_ctx,
2836 136,
2837 LS_64(info->send_cq_num, I40IWQPC_TXCQNUM) |
2838 LS_64(info->rcv_cq_num, I40IWQPC_RXCQNUM));
2839
2840 set_64bit_val(qp_ctx,
2841 168,
2842 LS_64(info->qp_compl_ctx, I40IWQPC_QPCOMPCTX));
2843 set_64bit_val(qp_ctx,
2844 176,
2845 LS_64(qp->sq_tph_val, I40IWQPC_SQTPHVAL) |
2846 LS_64(qp->rq_tph_val, I40IWQPC_RQTPHVAL) |
2847 LS_64(qp->qs_handle, I40IWQPC_QSHANDLE) |
2848 LS_64(vsi->exception_lan_queue, I40IWQPC_EXCEPTION_LAN_QUEUE));
2849
2850 if (info->iwarp_info_valid) {
2851 qw0 |= LS_64(iw->ddp_ver, I40IWQPC_DDP_VER) |
2852 LS_64(iw->rdmap_ver, I40IWQPC_RDMAP_VER);
2853
2854 qw7 |= LS_64(iw->pd_id, I40IWQPC_PDIDX);
2855 set_64bit_val(qp_ctx,
2856 144,
2857 LS_64(qp->q2_pa, I40IWQPC_Q2ADDR) |
2858 LS_64(vsi->fcn_id, I40IWQPC_STAT_INDEX));
2859 set_64bit_val(qp_ctx,
2860 152,
2861 LS_64(iw->last_byte_sent, I40IWQPC_LASTBYTESENT));
2862
2863 set_64bit_val(qp_ctx,
2864 160,
2865 LS_64(iw->ord_size, I40IWQPC_ORDSIZE) |
2866 LS_64(iw->ird_size, I40IWQPC_IRDSIZE) |
2867 LS_64(iw->wr_rdresp_en, I40IWQPC_WRRDRSPOK) |
2868 LS_64(iw->rd_enable, I40IWQPC_RDOK) |
2869 LS_64(iw->snd_mark_en, I40IWQPC_SNDMARKERS) |
2870 LS_64(iw->bind_en, I40IWQPC_BINDEN) |
2871 LS_64(iw->fast_reg_en, I40IWQPC_FASTREGEN) |
2872 LS_64(iw->priv_mode_en, I40IWQPC_PRIVEN) |
2873 LS_64((((vsi->stats_fcn_id_alloc) &&
2874 (dev->is_pf) && (vsi->fcn_id >= I40IW_FIRST_NON_PF_STAT)) ? 1 : 0),
2875 I40IWQPC_USESTATSINSTANCE) |
2876 LS_64(1, I40IWQPC_IWARPMODE) |
2877 LS_64(iw->rcv_mark_en, I40IWQPC_RCVMARKERS) |
2878 LS_64(iw->align_hdrs, I40IWQPC_ALIGNHDRS) |
2879 LS_64(iw->rcv_no_mpa_crc, I40IWQPC_RCVNOMPACRC) |
2880 LS_64(iw->rcv_mark_offset, I40IWQPC_RCVMARKOFFSET) |
2881 LS_64(iw->snd_mark_offset, I40IWQPC_SNDMARKOFFSET));
2882 }
2883 if (info->tcp_info_valid) {
2884 qw0 |= LS_64(tcp->ipv4, I40IWQPC_IPV4) |
2885 LS_64(tcp->no_nagle, I40IWQPC_NONAGLE) |
2886 LS_64(tcp->insert_vlan_tag, I40IWQPC_INSERTVLANTAG) |
2887 LS_64(tcp->time_stamp, I40IWQPC_TIMESTAMP) |
2888 LS_64(tcp->cwnd_inc_limit, I40IWQPC_LIMIT) |
2889 LS_64(tcp->drop_ooo_seg, I40IWQPC_DROPOOOSEG) |
2890 LS_64(tcp->dup_ack_thresh, I40IWQPC_DUPACK_THRESH);
2891
2892 qw3 |= LS_64(tcp->ttl, I40IWQPC_TTL) |
2893 LS_64(tcp->src_mac_addr_idx, I40IWQPC_SRCMACADDRIDX) |
2894 LS_64(tcp->avoid_stretch_ack, I40IWQPC_AVOIDSTRETCHACK) |
2895 LS_64(tcp->tos, I40IWQPC_TOS) |
2896 LS_64(tcp->src_port, I40IWQPC_SRCPORTNUM) |
2897 LS_64(tcp->dst_port, I40IWQPC_DESTPORTNUM);
2898
2899 qp->src_mac_addr_idx = tcp->src_mac_addr_idx;
2900 set_64bit_val(qp_ctx,
2901 32,
2902 LS_64(tcp->dest_ip_addr2, I40IWQPC_DESTIPADDR2) |
2903 LS_64(tcp->dest_ip_addr3, I40IWQPC_DESTIPADDR3));
2904
2905 set_64bit_val(qp_ctx,
2906 40,
2907 LS_64(tcp->dest_ip_addr0, I40IWQPC_DESTIPADDR0) |
2908 LS_64(tcp->dest_ip_addr1, I40IWQPC_DESTIPADDR1));
2909
2910 set_64bit_val(qp_ctx,
2911 48,
2912 LS_64(tcp->snd_mss, I40IWQPC_SNDMSS) |
2913 LS_64(tcp->vlan_tag, I40IWQPC_VLANTAG) |
2914 LS_64(tcp->arp_idx, I40IWQPC_ARPIDX));
2915
2916 qw7 |= LS_64(tcp->flow_label, I40IWQPC_FLOWLABEL) |
2917 LS_64(tcp->wscale, I40IWQPC_WSCALE) |
2918 LS_64(tcp->ignore_tcp_opt, I40IWQPC_IGNORE_TCP_OPT) |
2919 LS_64(tcp->ignore_tcp_uns_opt, I40IWQPC_IGNORE_TCP_UNS_OPT) |
2920 LS_64(tcp->tcp_state, I40IWQPC_TCPSTATE) |
2921 LS_64(tcp->rcv_wscale, I40IWQPC_RCVSCALE) |
2922 LS_64(tcp->snd_wscale, I40IWQPC_SNDSCALE);
2923
2924 set_64bit_val(qp_ctx,
2925 72,
2926 LS_64(tcp->time_stamp_recent, I40IWQPC_TIMESTAMP_RECENT) |
2927 LS_64(tcp->time_stamp_age, I40IWQPC_TIMESTAMP_AGE));
2928 set_64bit_val(qp_ctx,
2929 80,
2930 LS_64(tcp->snd_nxt, I40IWQPC_SNDNXT) |
2931 LS_64(tcp->snd_wnd, I40IWQPC_SNDWND));
2932
2933 set_64bit_val(qp_ctx,
2934 88,
2935 LS_64(tcp->rcv_nxt, I40IWQPC_RCVNXT) |
2936 LS_64(tcp->rcv_wnd, I40IWQPC_RCVWND));
2937 set_64bit_val(qp_ctx,
2938 96,
2939 LS_64(tcp->snd_max, I40IWQPC_SNDMAX) |
2940 LS_64(tcp->snd_una, I40IWQPC_SNDUNA));
2941 set_64bit_val(qp_ctx,
2942 104,
2943 LS_64(tcp->srtt, I40IWQPC_SRTT) |
2944 LS_64(tcp->rtt_var, I40IWQPC_RTTVAR));
2945 set_64bit_val(qp_ctx,
2946 112,
2947 LS_64(tcp->ss_thresh, I40IWQPC_SSTHRESH) |
2948 LS_64(tcp->cwnd, I40IWQPC_CWND));
2949 set_64bit_val(qp_ctx,
2950 120,
2951 LS_64(tcp->snd_wl1, I40IWQPC_SNDWL1) |
2952 LS_64(tcp->snd_wl2, I40IWQPC_SNDWL2));
2953 set_64bit_val(qp_ctx,
2954 128,
2955 LS_64(tcp->max_snd_window, I40IWQPC_MAXSNDWND) |
2956 LS_64(tcp->rexmit_thresh, I40IWQPC_REXMIT_THRESH));
2957 set_64bit_val(qp_ctx,
2958 184,
2959 LS_64(tcp->local_ipaddr3, I40IWQPC_LOCAL_IPADDR3) |
2960 LS_64(tcp->local_ipaddr2, I40IWQPC_LOCAL_IPADDR2));
2961 set_64bit_val(qp_ctx,
2962 192,
2963 LS_64(tcp->local_ipaddr1, I40IWQPC_LOCAL_IPADDR1) |
2964 LS_64(tcp->local_ipaddr0, I40IWQPC_LOCAL_IPADDR0));
2965 }
2966
2967 set_64bit_val(qp_ctx, 0, qw0);
2968 set_64bit_val(qp_ctx, 24, qw3);
2969 set_64bit_val(qp_ctx, 56, qw7);
2970
2971 i40iw_debug_buf(qp->dev, I40IW_DEBUG_WQE, "QP_HOST)CTX WQE",
2972 qp_ctx, I40IW_QP_CTX_SIZE);
2973 return 0;
2974 }
2975
2976 /**
2977 * i40iw_sc_alloc_stag - mr stag alloc
2978 * @dev: sc device struct
2979 * @info: stag info
2980 * @scratch: u64 saved to be used during cqp completion
2981 * @post_sq: flag for cqp db to ring
2982 */
i40iw_sc_alloc_stag(struct i40iw_sc_dev * dev,struct i40iw_allocate_stag_info * info,u64 scratch,bool post_sq)2983 static enum i40iw_status_code i40iw_sc_alloc_stag(
2984 struct i40iw_sc_dev *dev,
2985 struct i40iw_allocate_stag_info *info,
2986 u64 scratch,
2987 bool post_sq)
2988 {
2989 u64 *wqe;
2990 struct i40iw_sc_cqp *cqp;
2991 u64 header;
2992 enum i40iw_page_size page_size;
2993
2994 page_size = (info->page_size == 0x200000) ? I40IW_PAGE_SIZE_2M : I40IW_PAGE_SIZE_4K;
2995 cqp = dev->cqp;
2996 wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
2997 if (!wqe)
2998 return I40IW_ERR_RING_FULL;
2999 set_64bit_val(wqe,
3000 8,
3001 LS_64(info->pd_id, I40IW_CQPSQ_STAG_PDID) |
3002 LS_64(info->total_len, I40IW_CQPSQ_STAG_STAGLEN));
3003 set_64bit_val(wqe,
3004 16,
3005 LS_64(info->stag_idx, I40IW_CQPSQ_STAG_IDX));
3006 set_64bit_val(wqe,
3007 40,
3008 LS_64(info->hmc_fcn_index, I40IW_CQPSQ_STAG_HMCFNIDX));
3009
3010 header = LS_64(I40IW_CQP_OP_ALLOC_STAG, I40IW_CQPSQ_OPCODE) |
3011 LS_64(1, I40IW_CQPSQ_STAG_MR) |
3012 LS_64(info->access_rights, I40IW_CQPSQ_STAG_ARIGHTS) |
3013 LS_64(info->chunk_size, I40IW_CQPSQ_STAG_LPBLSIZE) |
3014 LS_64(page_size, I40IW_CQPSQ_STAG_HPAGESIZE) |
3015 LS_64(info->remote_access, I40IW_CQPSQ_STAG_REMACCENABLED) |
3016 LS_64(info->use_hmc_fcn_index, I40IW_CQPSQ_STAG_USEHMCFNIDX) |
3017 LS_64(info->use_pf_rid, I40IW_CQPSQ_STAG_USEPFRID) |
3018 LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
3019
3020 i40iw_insert_wqe_hdr(wqe, header);
3021
3022 i40iw_debug_buf(dev, I40IW_DEBUG_WQE, "ALLOC_STAG WQE",
3023 wqe, I40IW_CQP_WQE_SIZE * 8);
3024
3025 if (post_sq)
3026 i40iw_sc_cqp_post_sq(cqp);
3027 return 0;
3028 }
3029
3030 /**
3031 * i40iw_sc_mr_reg_non_shared - non-shared mr registration
3032 * @dev: sc device struct
3033 * @info: mr info
3034 * @scratch: u64 saved to be used during cqp completion
3035 * @post_sq: flag for cqp db to ring
3036 */
i40iw_sc_mr_reg_non_shared(struct i40iw_sc_dev * dev,struct i40iw_reg_ns_stag_info * info,u64 scratch,bool post_sq)3037 static enum i40iw_status_code i40iw_sc_mr_reg_non_shared(
3038 struct i40iw_sc_dev *dev,
3039 struct i40iw_reg_ns_stag_info *info,
3040 u64 scratch,
3041 bool post_sq)
3042 {
3043 u64 *wqe;
3044 u64 temp;
3045 struct i40iw_sc_cqp *cqp;
3046 u64 header;
3047 u32 pble_obj_cnt;
3048 bool remote_access;
3049 u8 addr_type;
3050 enum i40iw_page_size page_size;
3051
3052 page_size = (info->page_size == 0x200000) ? I40IW_PAGE_SIZE_2M : I40IW_PAGE_SIZE_4K;
3053 if (info->access_rights & (I40IW_ACCESS_FLAGS_REMOTEREAD_ONLY |
3054 I40IW_ACCESS_FLAGS_REMOTEWRITE_ONLY))
3055 remote_access = true;
3056 else
3057 remote_access = false;
3058
3059 pble_obj_cnt = dev->hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt;
3060
3061 if (info->chunk_size && (info->first_pm_pbl_index >= pble_obj_cnt))
3062 return I40IW_ERR_INVALID_PBLE_INDEX;
3063
3064 cqp = dev->cqp;
3065 wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
3066 if (!wqe)
3067 return I40IW_ERR_RING_FULL;
3068
3069 temp = (info->addr_type == I40IW_ADDR_TYPE_VA_BASED) ? (uintptr_t)info->va : info->fbo;
3070 set_64bit_val(wqe, 0, temp);
3071
3072 set_64bit_val(wqe,
3073 8,
3074 LS_64(info->total_len, I40IW_CQPSQ_STAG_STAGLEN) |
3075 LS_64(info->pd_id, I40IW_CQPSQ_STAG_PDID));
3076
3077 set_64bit_val(wqe,
3078 16,
3079 LS_64(info->stag_key, I40IW_CQPSQ_STAG_KEY) |
3080 LS_64(info->stag_idx, I40IW_CQPSQ_STAG_IDX));
3081 if (!info->chunk_size) {
3082 set_64bit_val(wqe, 32, info->reg_addr_pa);
3083 set_64bit_val(wqe, 48, 0);
3084 } else {
3085 set_64bit_val(wqe, 32, 0);
3086 set_64bit_val(wqe, 48, info->first_pm_pbl_index);
3087 }
3088 set_64bit_val(wqe, 40, info->hmc_fcn_index);
3089 set_64bit_val(wqe, 56, 0);
3090
3091 addr_type = (info->addr_type == I40IW_ADDR_TYPE_VA_BASED) ? 1 : 0;
3092 header = LS_64(I40IW_CQP_OP_REG_MR, I40IW_CQPSQ_OPCODE) |
3093 LS_64(1, I40IW_CQPSQ_STAG_MR) |
3094 LS_64(info->chunk_size, I40IW_CQPSQ_STAG_LPBLSIZE) |
3095 LS_64(page_size, I40IW_CQPSQ_STAG_HPAGESIZE) |
3096 LS_64(info->access_rights, I40IW_CQPSQ_STAG_ARIGHTS) |
3097 LS_64(remote_access, I40IW_CQPSQ_STAG_REMACCENABLED) |
3098 LS_64(addr_type, I40IW_CQPSQ_STAG_VABASEDTO) |
3099 LS_64(info->use_hmc_fcn_index, I40IW_CQPSQ_STAG_USEHMCFNIDX) |
3100 LS_64(info->use_pf_rid, I40IW_CQPSQ_STAG_USEPFRID) |
3101 LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
3102
3103 i40iw_insert_wqe_hdr(wqe, header);
3104
3105 i40iw_debug_buf(dev, I40IW_DEBUG_WQE, "MR_REG_NS WQE",
3106 wqe, I40IW_CQP_WQE_SIZE * 8);
3107
3108 if (post_sq)
3109 i40iw_sc_cqp_post_sq(cqp);
3110 return 0;
3111 }
3112
3113 /**
3114 * i40iw_sc_mr_reg_shared - registered shared memory region
3115 * @dev: sc device struct
3116 * @info: info for shared memory registeration
3117 * @scratch: u64 saved to be used during cqp completion
3118 * @post_sq: flag for cqp db to ring
3119 */
i40iw_sc_mr_reg_shared(struct i40iw_sc_dev * dev,struct i40iw_register_shared_stag * info,u64 scratch,bool post_sq)3120 static enum i40iw_status_code i40iw_sc_mr_reg_shared(
3121 struct i40iw_sc_dev *dev,
3122 struct i40iw_register_shared_stag *info,
3123 u64 scratch,
3124 bool post_sq)
3125 {
3126 u64 *wqe;
3127 struct i40iw_sc_cqp *cqp;
3128 u64 temp, va64, fbo, header;
3129 u32 va32;
3130 bool remote_access;
3131 u8 addr_type;
3132
3133 if (info->access_rights & (I40IW_ACCESS_FLAGS_REMOTEREAD_ONLY |
3134 I40IW_ACCESS_FLAGS_REMOTEWRITE_ONLY))
3135 remote_access = true;
3136 else
3137 remote_access = false;
3138 cqp = dev->cqp;
3139 wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
3140 if (!wqe)
3141 return I40IW_ERR_RING_FULL;
3142 va64 = (uintptr_t)(info->va);
3143 va32 = (u32)(va64 & 0x00000000FFFFFFFF);
3144 fbo = (u64)(va32 & (4096 - 1));
3145
3146 set_64bit_val(wqe,
3147 0,
3148 (info->addr_type == I40IW_ADDR_TYPE_VA_BASED ? (uintptr_t)info->va : fbo));
3149
3150 set_64bit_val(wqe,
3151 8,
3152 LS_64(info->pd_id, I40IW_CQPSQ_STAG_PDID));
3153 temp = LS_64(info->new_stag_key, I40IW_CQPSQ_STAG_KEY) |
3154 LS_64(info->new_stag_idx, I40IW_CQPSQ_STAG_IDX) |
3155 LS_64(info->parent_stag_idx, I40IW_CQPSQ_STAG_PARENTSTAGIDX);
3156 set_64bit_val(wqe, 16, temp);
3157
3158 addr_type = (info->addr_type == I40IW_ADDR_TYPE_VA_BASED) ? 1 : 0;
3159 header = LS_64(I40IW_CQP_OP_REG_SMR, I40IW_CQPSQ_OPCODE) |
3160 LS_64(1, I40IW_CQPSQ_STAG_MR) |
3161 LS_64(info->access_rights, I40IW_CQPSQ_STAG_ARIGHTS) |
3162 LS_64(remote_access, I40IW_CQPSQ_STAG_REMACCENABLED) |
3163 LS_64(addr_type, I40IW_CQPSQ_STAG_VABASEDTO) |
3164 LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
3165
3166 i40iw_insert_wqe_hdr(wqe, header);
3167
3168 i40iw_debug_buf(dev, I40IW_DEBUG_WQE, "MR_REG_SHARED WQE",
3169 wqe, I40IW_CQP_WQE_SIZE * 8);
3170
3171 if (post_sq)
3172 i40iw_sc_cqp_post_sq(cqp);
3173 return 0;
3174 }
3175
3176 /**
3177 * i40iw_sc_dealloc_stag - deallocate stag
3178 * @dev: sc device struct
3179 * @info: dealloc stag info
3180 * @scratch: u64 saved to be used during cqp completion
3181 * @post_sq: flag for cqp db to ring
3182 */
i40iw_sc_dealloc_stag(struct i40iw_sc_dev * dev,struct i40iw_dealloc_stag_info * info,u64 scratch,bool post_sq)3183 static enum i40iw_status_code i40iw_sc_dealloc_stag(
3184 struct i40iw_sc_dev *dev,
3185 struct i40iw_dealloc_stag_info *info,
3186 u64 scratch,
3187 bool post_sq)
3188 {
3189 u64 header;
3190 u64 *wqe;
3191 struct i40iw_sc_cqp *cqp;
3192
3193 cqp = dev->cqp;
3194 wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
3195 if (!wqe)
3196 return I40IW_ERR_RING_FULL;
3197 set_64bit_val(wqe,
3198 8,
3199 LS_64(info->pd_id, I40IW_CQPSQ_STAG_PDID));
3200 set_64bit_val(wqe,
3201 16,
3202 LS_64(info->stag_idx, I40IW_CQPSQ_STAG_IDX));
3203
3204 header = LS_64(I40IW_CQP_OP_DEALLOC_STAG, I40IW_CQPSQ_OPCODE) |
3205 LS_64(info->mr, I40IW_CQPSQ_STAG_MR) |
3206 LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
3207
3208 i40iw_insert_wqe_hdr(wqe, header);
3209
3210 i40iw_debug_buf(dev, I40IW_DEBUG_WQE, "DEALLOC_STAG WQE",
3211 wqe, I40IW_CQP_WQE_SIZE * 8);
3212
3213 if (post_sq)
3214 i40iw_sc_cqp_post_sq(cqp);
3215 return 0;
3216 }
3217
3218 /**
3219 * i40iw_sc_query_stag - query hardware for stag
3220 * @dev: sc device struct
3221 * @scratch: u64 saved to be used during cqp completion
3222 * @stag_index: stag index for query
3223 * @post_sq: flag for cqp db to ring
3224 */
i40iw_sc_query_stag(struct i40iw_sc_dev * dev,u64 scratch,u32 stag_index,bool post_sq)3225 static enum i40iw_status_code i40iw_sc_query_stag(struct i40iw_sc_dev *dev,
3226 u64 scratch,
3227 u32 stag_index,
3228 bool post_sq)
3229 {
3230 u64 header;
3231 u64 *wqe;
3232 struct i40iw_sc_cqp *cqp;
3233
3234 cqp = dev->cqp;
3235 wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
3236 if (!wqe)
3237 return I40IW_ERR_RING_FULL;
3238 set_64bit_val(wqe,
3239 16,
3240 LS_64(stag_index, I40IW_CQPSQ_QUERYSTAG_IDX));
3241
3242 header = LS_64(I40IW_CQP_OP_QUERY_STAG, I40IW_CQPSQ_OPCODE) |
3243 LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
3244
3245 i40iw_insert_wqe_hdr(wqe, header);
3246
3247 i40iw_debug_buf(dev, I40IW_DEBUG_WQE, "QUERY_STAG WQE",
3248 wqe, I40IW_CQP_WQE_SIZE * 8);
3249
3250 if (post_sq)
3251 i40iw_sc_cqp_post_sq(cqp);
3252 return 0;
3253 }
3254
3255 /**
3256 * i40iw_sc_mw_alloc - mw allocate
3257 * @dev: sc device struct
3258 * @scratch: u64 saved to be used during cqp completion
3259 * @mw_stag_index:stag index
3260 * @pd_id: pd is for this mw
3261 * @post_sq: flag for cqp db to ring
3262 */
i40iw_sc_mw_alloc(struct i40iw_sc_dev * dev,u64 scratch,u32 mw_stag_index,u16 pd_id,bool post_sq)3263 static enum i40iw_status_code i40iw_sc_mw_alloc(
3264 struct i40iw_sc_dev *dev,
3265 u64 scratch,
3266 u32 mw_stag_index,
3267 u16 pd_id,
3268 bool post_sq)
3269 {
3270 u64 header;
3271 struct i40iw_sc_cqp *cqp;
3272 u64 *wqe;
3273
3274 cqp = dev->cqp;
3275 wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
3276 if (!wqe)
3277 return I40IW_ERR_RING_FULL;
3278 set_64bit_val(wqe, 8, LS_64(pd_id, I40IW_CQPSQ_STAG_PDID));
3279 set_64bit_val(wqe,
3280 16,
3281 LS_64(mw_stag_index, I40IW_CQPSQ_STAG_IDX));
3282
3283 header = LS_64(I40IW_CQP_OP_ALLOC_STAG, I40IW_CQPSQ_OPCODE) |
3284 LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
3285
3286 i40iw_insert_wqe_hdr(wqe, header);
3287
3288 i40iw_debug_buf(dev, I40IW_DEBUG_WQE, "MW_ALLOC WQE",
3289 wqe, I40IW_CQP_WQE_SIZE * 8);
3290
3291 if (post_sq)
3292 i40iw_sc_cqp_post_sq(cqp);
3293 return 0;
3294 }
3295
3296 /**
3297 * i40iw_sc_mr_fast_register - Posts RDMA fast register mr WR to iwarp qp
3298 * @qp: sc qp struct
3299 * @info: fast mr info
3300 * @post_sq: flag for cqp db to ring
3301 */
i40iw_sc_mr_fast_register(struct i40iw_sc_qp * qp,struct i40iw_fast_reg_stag_info * info,bool post_sq)3302 enum i40iw_status_code i40iw_sc_mr_fast_register(
3303 struct i40iw_sc_qp *qp,
3304 struct i40iw_fast_reg_stag_info *info,
3305 bool post_sq)
3306 {
3307 u64 temp, header;
3308 u64 *wqe;
3309 u32 wqe_idx;
3310 enum i40iw_page_size page_size;
3311
3312 page_size = (info->page_size == 0x200000) ? I40IW_PAGE_SIZE_2M : I40IW_PAGE_SIZE_4K;
3313 wqe = i40iw_qp_get_next_send_wqe(&qp->qp_uk, &wqe_idx, I40IW_QP_WQE_MIN_SIZE,
3314 0, info->wr_id);
3315 if (!wqe)
3316 return I40IW_ERR_QP_TOOMANY_WRS_POSTED;
3317
3318 i40iw_debug(qp->dev, I40IW_DEBUG_MR, "%s: wr_id[%llxh] wqe_idx[%04d] location[%p]\n",
3319 __func__, info->wr_id, wqe_idx,
3320 &qp->qp_uk.sq_wrtrk_array[wqe_idx].wrid);
3321 temp = (info->addr_type == I40IW_ADDR_TYPE_VA_BASED) ? (uintptr_t)info->va : info->fbo;
3322 set_64bit_val(wqe, 0, temp);
3323
3324 temp = RS_64(info->first_pm_pbl_index >> 16, I40IWQPSQ_FIRSTPMPBLIDXHI);
3325 set_64bit_val(wqe,
3326 8,
3327 LS_64(temp, I40IWQPSQ_FIRSTPMPBLIDXHI) |
3328 LS_64(info->reg_addr_pa >> I40IWQPSQ_PBLADDR_SHIFT, I40IWQPSQ_PBLADDR));
3329
3330 set_64bit_val(wqe,
3331 16,
3332 info->total_len |
3333 LS_64(info->first_pm_pbl_index, I40IWQPSQ_FIRSTPMPBLIDXLO));
3334
3335 header = LS_64(info->stag_key, I40IWQPSQ_STAGKEY) |
3336 LS_64(info->stag_idx, I40IWQPSQ_STAGINDEX) |
3337 LS_64(I40IWQP_OP_FAST_REGISTER, I40IWQPSQ_OPCODE) |
3338 LS_64(info->chunk_size, I40IWQPSQ_LPBLSIZE) |
3339 LS_64(page_size, I40IWQPSQ_HPAGESIZE) |
3340 LS_64(info->access_rights, I40IWQPSQ_STAGRIGHTS) |
3341 LS_64(info->addr_type, I40IWQPSQ_VABASEDTO) |
3342 LS_64(info->read_fence, I40IWQPSQ_READFENCE) |
3343 LS_64(info->local_fence, I40IWQPSQ_LOCALFENCE) |
3344 LS_64(info->signaled, I40IWQPSQ_SIGCOMPL) |
3345 LS_64(qp->qp_uk.swqe_polarity, I40IWQPSQ_VALID);
3346
3347 i40iw_insert_wqe_hdr(wqe, header);
3348
3349 i40iw_debug_buf(qp->dev, I40IW_DEBUG_WQE, "FAST_REG WQE",
3350 wqe, I40IW_QP_WQE_MIN_SIZE);
3351
3352 if (post_sq)
3353 i40iw_qp_post_wr(&qp->qp_uk);
3354 return 0;
3355 }
3356
3357 /**
3358 * i40iw_sc_send_lsmm - send last streaming mode message
3359 * @qp: sc qp struct
3360 * @lsmm_buf: buffer with lsmm message
3361 * @size: size of lsmm buffer
3362 * @stag: stag of lsmm buffer
3363 */
i40iw_sc_send_lsmm(struct i40iw_sc_qp * qp,void * lsmm_buf,u32 size,i40iw_stag stag)3364 static void i40iw_sc_send_lsmm(struct i40iw_sc_qp *qp,
3365 void *lsmm_buf,
3366 u32 size,
3367 i40iw_stag stag)
3368 {
3369 u64 *wqe;
3370 u64 header;
3371 struct i40iw_qp_uk *qp_uk;
3372
3373 qp_uk = &qp->qp_uk;
3374 wqe = qp_uk->sq_base->elem;
3375
3376 set_64bit_val(wqe, 0, (uintptr_t)lsmm_buf);
3377
3378 set_64bit_val(wqe, 8, (size | LS_64(stag, I40IWQPSQ_FRAG_STAG)));
3379
3380 set_64bit_val(wqe, 16, 0);
3381
3382 header = LS_64(I40IWQP_OP_RDMA_SEND, I40IWQPSQ_OPCODE) |
3383 LS_64(1, I40IWQPSQ_STREAMMODE) |
3384 LS_64(1, I40IWQPSQ_WAITFORRCVPDU) |
3385 LS_64(qp->qp_uk.swqe_polarity, I40IWQPSQ_VALID);
3386
3387 i40iw_insert_wqe_hdr(wqe, header);
3388
3389 i40iw_debug_buf(qp->dev, I40IW_DEBUG_QP, "SEND_LSMM WQE",
3390 wqe, I40IW_QP_WQE_MIN_SIZE);
3391 }
3392
3393 /**
3394 * i40iw_sc_send_lsmm_nostag - for privilege qp
3395 * @qp: sc qp struct
3396 * @lsmm_buf: buffer with lsmm message
3397 * @size: size of lsmm buffer
3398 */
i40iw_sc_send_lsmm_nostag(struct i40iw_sc_qp * qp,void * lsmm_buf,u32 size)3399 static void i40iw_sc_send_lsmm_nostag(struct i40iw_sc_qp *qp,
3400 void *lsmm_buf,
3401 u32 size)
3402 {
3403 u64 *wqe;
3404 u64 header;
3405 struct i40iw_qp_uk *qp_uk;
3406
3407 qp_uk = &qp->qp_uk;
3408 wqe = qp_uk->sq_base->elem;
3409
3410 set_64bit_val(wqe, 0, (uintptr_t)lsmm_buf);
3411
3412 set_64bit_val(wqe, 8, size);
3413
3414 set_64bit_val(wqe, 16, 0);
3415
3416 header = LS_64(I40IWQP_OP_RDMA_SEND, I40IWQPSQ_OPCODE) |
3417 LS_64(1, I40IWQPSQ_STREAMMODE) |
3418 LS_64(1, I40IWQPSQ_WAITFORRCVPDU) |
3419 LS_64(qp->qp_uk.swqe_polarity, I40IWQPSQ_VALID);
3420
3421 i40iw_insert_wqe_hdr(wqe, header);
3422
3423 i40iw_debug_buf(qp->dev, I40IW_DEBUG_WQE, "SEND_LSMM_NOSTAG WQE",
3424 wqe, I40IW_QP_WQE_MIN_SIZE);
3425 }
3426
3427 /**
3428 * i40iw_sc_send_rtt - send last read0 or write0
3429 * @qp: sc qp struct
3430 * @read: Do read0 or write0
3431 */
i40iw_sc_send_rtt(struct i40iw_sc_qp * qp,bool read)3432 static void i40iw_sc_send_rtt(struct i40iw_sc_qp *qp, bool read)
3433 {
3434 u64 *wqe;
3435 u64 header;
3436 struct i40iw_qp_uk *qp_uk;
3437
3438 qp_uk = &qp->qp_uk;
3439 wqe = qp_uk->sq_base->elem;
3440
3441 set_64bit_val(wqe, 0, 0);
3442 set_64bit_val(wqe, 8, 0);
3443 set_64bit_val(wqe, 16, 0);
3444 if (read) {
3445 header = LS_64(0x1234, I40IWQPSQ_REMSTAG) |
3446 LS_64(I40IWQP_OP_RDMA_READ, I40IWQPSQ_OPCODE) |
3447 LS_64(qp->qp_uk.swqe_polarity, I40IWQPSQ_VALID);
3448 set_64bit_val(wqe, 8, ((u64)0xabcd << 32));
3449 } else {
3450 header = LS_64(I40IWQP_OP_RDMA_WRITE, I40IWQPSQ_OPCODE) |
3451 LS_64(qp->qp_uk.swqe_polarity, I40IWQPSQ_VALID);
3452 }
3453
3454 i40iw_insert_wqe_hdr(wqe, header);
3455
3456 i40iw_debug_buf(qp->dev, I40IW_DEBUG_WQE, "RTR WQE",
3457 wqe, I40IW_QP_WQE_MIN_SIZE);
3458 }
3459
3460 /**
3461 * i40iw_sc_post_wqe0 - send wqe with opcode
3462 * @qp: sc qp struct
3463 * @opcode: opcode to use for wqe0
3464 */
i40iw_sc_post_wqe0(struct i40iw_sc_qp * qp,u8 opcode)3465 static enum i40iw_status_code i40iw_sc_post_wqe0(struct i40iw_sc_qp *qp, u8 opcode)
3466 {
3467 u64 *wqe;
3468 u64 header;
3469 struct i40iw_qp_uk *qp_uk;
3470
3471 qp_uk = &qp->qp_uk;
3472 wqe = qp_uk->sq_base->elem;
3473
3474 if (!wqe)
3475 return I40IW_ERR_QP_TOOMANY_WRS_POSTED;
3476 switch (opcode) {
3477 case I40IWQP_OP_NOP:
3478 set_64bit_val(wqe, 0, 0);
3479 set_64bit_val(wqe, 8, 0);
3480 set_64bit_val(wqe, 16, 0);
3481 header = LS_64(I40IWQP_OP_NOP, I40IWQPSQ_OPCODE) |
3482 LS_64(qp->qp_uk.swqe_polarity, I40IWQPSQ_VALID);
3483
3484 i40iw_insert_wqe_hdr(wqe, header);
3485 break;
3486 case I40IWQP_OP_RDMA_SEND:
3487 set_64bit_val(wqe, 0, 0);
3488 set_64bit_val(wqe, 8, 0);
3489 set_64bit_val(wqe, 16, 0);
3490 header = LS_64(I40IWQP_OP_RDMA_SEND, I40IWQPSQ_OPCODE) |
3491 LS_64(qp->qp_uk.swqe_polarity, I40IWQPSQ_VALID) |
3492 LS_64(1, I40IWQPSQ_STREAMMODE) |
3493 LS_64(1, I40IWQPSQ_WAITFORRCVPDU);
3494
3495 i40iw_insert_wqe_hdr(wqe, header);
3496 break;
3497 default:
3498 i40iw_debug(qp->dev, I40IW_DEBUG_QP, "%s: Invalid WQE zero opcode\n",
3499 __func__);
3500 break;
3501 }
3502 return 0;
3503 }
3504
3505 /**
3506 * i40iw_sc_init_iw_hmc() - queries fpm values using cqp and populates hmc_info
3507 * @dev : ptr to i40iw_dev struct
3508 * @hmc_fn_id: hmc function id
3509 */
i40iw_sc_init_iw_hmc(struct i40iw_sc_dev * dev,u8 hmc_fn_id)3510 enum i40iw_status_code i40iw_sc_init_iw_hmc(struct i40iw_sc_dev *dev, u8 hmc_fn_id)
3511 {
3512 struct i40iw_hmc_info *hmc_info;
3513 struct i40iw_dma_mem query_fpm_mem;
3514 struct i40iw_virt_mem virt_mem;
3515 struct i40iw_vfdev *vf_dev = NULL;
3516 u32 mem_size;
3517 enum i40iw_status_code ret_code = 0;
3518 bool poll_registers = true;
3519 u16 iw_vf_idx;
3520 u8 wait_type;
3521
3522 if (hmc_fn_id >= I40IW_MAX_VF_FPM_ID ||
3523 (dev->hmc_fn_id != hmc_fn_id && hmc_fn_id < I40IW_FIRST_VF_FPM_ID))
3524 return I40IW_ERR_INVALID_HMCFN_ID;
3525
3526 i40iw_debug(dev, I40IW_DEBUG_HMC, "hmc_fn_id %u, dev->hmc_fn_id %u\n", hmc_fn_id,
3527 dev->hmc_fn_id);
3528 if (hmc_fn_id == dev->hmc_fn_id) {
3529 hmc_info = dev->hmc_info;
3530 query_fpm_mem.pa = dev->fpm_query_buf_pa;
3531 query_fpm_mem.va = dev->fpm_query_buf;
3532 } else {
3533 vf_dev = i40iw_vfdev_from_fpm(dev, hmc_fn_id);
3534 if (!vf_dev)
3535 return I40IW_ERR_INVALID_VF_ID;
3536
3537 hmc_info = &vf_dev->hmc_info;
3538 iw_vf_idx = vf_dev->iw_vf_idx;
3539 i40iw_debug(dev, I40IW_DEBUG_HMC, "vf_dev %p, hmc_info %p, hmc_obj %p\n", vf_dev,
3540 hmc_info, hmc_info->hmc_obj);
3541 if (!vf_dev->fpm_query_buf) {
3542 if (!dev->vf_fpm_query_buf[iw_vf_idx].va) {
3543 ret_code = i40iw_alloc_query_fpm_buf(dev,
3544 &dev->vf_fpm_query_buf[iw_vf_idx]);
3545 if (ret_code)
3546 return ret_code;
3547 }
3548 vf_dev->fpm_query_buf = dev->vf_fpm_query_buf[iw_vf_idx].va;
3549 vf_dev->fpm_query_buf_pa = dev->vf_fpm_query_buf[iw_vf_idx].pa;
3550 }
3551 query_fpm_mem.pa = vf_dev->fpm_query_buf_pa;
3552 query_fpm_mem.va = vf_dev->fpm_query_buf;
3553 /**
3554 * It is HARDWARE specific:
3555 * this call is done by PF for VF and
3556 * i40iw_sc_query_fpm_values needs ccq poll
3557 * because PF ccq is already created.
3558 */
3559 poll_registers = false;
3560 }
3561
3562 hmc_info->hmc_fn_id = hmc_fn_id;
3563
3564 if (hmc_fn_id != dev->hmc_fn_id) {
3565 ret_code =
3566 i40iw_cqp_query_fpm_values_cmd(dev, &query_fpm_mem, hmc_fn_id);
3567 } else {
3568 wait_type = poll_registers ? (u8)I40IW_CQP_WAIT_POLL_REGS :
3569 (u8)I40IW_CQP_WAIT_POLL_CQ;
3570
3571 ret_code = i40iw_sc_query_fpm_values(
3572 dev->cqp,
3573 0,
3574 hmc_info->hmc_fn_id,
3575 &query_fpm_mem,
3576 true,
3577 wait_type);
3578 }
3579 if (ret_code)
3580 return ret_code;
3581
3582 /* parse the fpm_query_buf and fill hmc obj info */
3583 ret_code =
3584 i40iw_sc_parse_fpm_query_buf((u64 *)query_fpm_mem.va,
3585 hmc_info,
3586 &dev->hmc_fpm_misc);
3587 if (ret_code)
3588 return ret_code;
3589 i40iw_debug_buf(dev, I40IW_DEBUG_HMC, "QUERY FPM BUFFER",
3590 query_fpm_mem.va, I40IW_QUERY_FPM_BUF_SIZE);
3591
3592 if (hmc_fn_id != dev->hmc_fn_id) {
3593 i40iw_cqp_commit_fpm_values_cmd(dev, &query_fpm_mem, hmc_fn_id);
3594
3595 /* parse the fpm_commit_buf and fill hmc obj info */
3596 i40iw_sc_parse_fpm_commit_buf((u64 *)query_fpm_mem.va, hmc_info->hmc_obj, &hmc_info->sd_table.sd_cnt);
3597 mem_size = sizeof(struct i40iw_hmc_sd_entry) *
3598 (hmc_info->sd_table.sd_cnt + hmc_info->first_sd_index);
3599 ret_code = i40iw_allocate_virt_mem(dev->hw, &virt_mem, mem_size);
3600 if (ret_code)
3601 return ret_code;
3602 hmc_info->sd_table.sd_entry = virt_mem.va;
3603 }
3604
3605 return ret_code;
3606 }
3607
3608 /**
3609 * i40iw_sc_configure_iw_fpm() - commits hmc obj cnt values using cqp command and
3610 * populates fpm base address in hmc_info
3611 * @dev : ptr to i40iw_dev struct
3612 * @hmc_fn_id: hmc function id
3613 */
i40iw_sc_configure_iw_fpm(struct i40iw_sc_dev * dev,u8 hmc_fn_id)3614 static enum i40iw_status_code i40iw_sc_configure_iw_fpm(struct i40iw_sc_dev *dev,
3615 u8 hmc_fn_id)
3616 {
3617 struct i40iw_hmc_info *hmc_info;
3618 struct i40iw_hmc_obj_info *obj_info;
3619 u64 *buf;
3620 struct i40iw_dma_mem commit_fpm_mem;
3621 u32 i, j;
3622 enum i40iw_status_code ret_code = 0;
3623 bool poll_registers = true;
3624 u8 wait_type;
3625
3626 if (hmc_fn_id >= I40IW_MAX_VF_FPM_ID ||
3627 (dev->hmc_fn_id != hmc_fn_id && hmc_fn_id < I40IW_FIRST_VF_FPM_ID))
3628 return I40IW_ERR_INVALID_HMCFN_ID;
3629
3630 if (hmc_fn_id == dev->hmc_fn_id) {
3631 hmc_info = dev->hmc_info;
3632 } else {
3633 hmc_info = i40iw_vf_hmcinfo_from_fpm(dev, hmc_fn_id);
3634 poll_registers = false;
3635 }
3636 if (!hmc_info)
3637 return I40IW_ERR_BAD_PTR;
3638
3639 obj_info = hmc_info->hmc_obj;
3640 buf = dev->fpm_commit_buf;
3641
3642 /* copy cnt values in commit buf */
3643 for (i = I40IW_HMC_IW_QP, j = 0; i <= I40IW_HMC_IW_PBLE;
3644 i++, j += 8)
3645 set_64bit_val(buf, j, (u64)obj_info[i].cnt);
3646
3647 set_64bit_val(buf, 40, 0); /* APBVT rsvd */
3648
3649 commit_fpm_mem.pa = dev->fpm_commit_buf_pa;
3650 commit_fpm_mem.va = dev->fpm_commit_buf;
3651 wait_type = poll_registers ? (u8)I40IW_CQP_WAIT_POLL_REGS :
3652 (u8)I40IW_CQP_WAIT_POLL_CQ;
3653 ret_code = i40iw_sc_commit_fpm_values(
3654 dev->cqp,
3655 0,
3656 hmc_info->hmc_fn_id,
3657 &commit_fpm_mem,
3658 true,
3659 wait_type);
3660
3661 /* parse the fpm_commit_buf and fill hmc obj info */
3662 if (!ret_code)
3663 ret_code = i40iw_sc_parse_fpm_commit_buf(dev->fpm_commit_buf,
3664 hmc_info->hmc_obj,
3665 &hmc_info->sd_table.sd_cnt);
3666
3667 i40iw_debug_buf(dev, I40IW_DEBUG_HMC, "COMMIT FPM BUFFER",
3668 commit_fpm_mem.va, I40IW_COMMIT_FPM_BUF_SIZE);
3669
3670 return ret_code;
3671 }
3672
3673 /**
3674 * cqp_sds_wqe_fill - fill cqp wqe doe sd
3675 * @cqp: struct for cqp hw
3676 * @info: sd info for wqe
3677 * @scratch: u64 saved to be used during cqp completion
3678 */
cqp_sds_wqe_fill(struct i40iw_sc_cqp * cqp,struct i40iw_update_sds_info * info,u64 scratch)3679 static enum i40iw_status_code cqp_sds_wqe_fill(struct i40iw_sc_cqp *cqp,
3680 struct i40iw_update_sds_info *info,
3681 u64 scratch)
3682 {
3683 u64 data;
3684 u64 header;
3685 u64 *wqe;
3686 int mem_entries, wqe_entries;
3687 struct i40iw_dma_mem *sdbuf = &cqp->sdbuf;
3688 u64 offset;
3689 u32 wqe_idx;
3690
3691 wqe = i40iw_sc_cqp_get_next_send_wqe_idx(cqp, scratch, &wqe_idx);
3692 if (!wqe)
3693 return I40IW_ERR_RING_FULL;
3694
3695 I40IW_CQP_INIT_WQE(wqe);
3696 wqe_entries = (info->cnt > 3) ? 3 : info->cnt;
3697 mem_entries = info->cnt - wqe_entries;
3698
3699 header = LS_64(I40IW_CQP_OP_UPDATE_PE_SDS, I40IW_CQPSQ_OPCODE) |
3700 LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID) |
3701 LS_64(mem_entries, I40IW_CQPSQ_UPESD_ENTRY_COUNT);
3702
3703 if (mem_entries) {
3704 offset = wqe_idx * I40IW_UPDATE_SD_BUF_SIZE;
3705 memcpy((char *)sdbuf->va + offset, &info->entry[3],
3706 mem_entries << 4);
3707 data = (u64)sdbuf->pa + offset;
3708 } else {
3709 data = 0;
3710 }
3711 data |= LS_64(info->hmc_fn_id, I40IW_CQPSQ_UPESD_HMCFNID);
3712
3713 set_64bit_val(wqe, 16, data);
3714
3715 switch (wqe_entries) {
3716 case 3:
3717 set_64bit_val(wqe, 48,
3718 (LS_64(info->entry[2].cmd, I40IW_CQPSQ_UPESD_SDCMD) |
3719 LS_64(1, I40IW_CQPSQ_UPESD_ENTRY_VALID)));
3720
3721 set_64bit_val(wqe, 56, info->entry[2].data);
3722 fallthrough;
3723 case 2:
3724 set_64bit_val(wqe, 32,
3725 (LS_64(info->entry[1].cmd, I40IW_CQPSQ_UPESD_SDCMD) |
3726 LS_64(1, I40IW_CQPSQ_UPESD_ENTRY_VALID)));
3727
3728 set_64bit_val(wqe, 40, info->entry[1].data);
3729 fallthrough;
3730 case 1:
3731 set_64bit_val(wqe, 0,
3732 LS_64(info->entry[0].cmd, I40IW_CQPSQ_UPESD_SDCMD));
3733
3734 set_64bit_val(wqe, 8, info->entry[0].data);
3735 break;
3736 default:
3737 break;
3738 }
3739
3740 i40iw_insert_wqe_hdr(wqe, header);
3741
3742 i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "UPDATE_PE_SDS WQE",
3743 wqe, I40IW_CQP_WQE_SIZE * 8);
3744 return 0;
3745 }
3746
3747 /**
3748 * i40iw_update_pe_sds - cqp wqe for sd
3749 * @dev: ptr to i40iw_dev struct
3750 * @info: sd info for sd's
3751 * @scratch: u64 saved to be used during cqp completion
3752 */
i40iw_update_pe_sds(struct i40iw_sc_dev * dev,struct i40iw_update_sds_info * info,u64 scratch)3753 static enum i40iw_status_code i40iw_update_pe_sds(struct i40iw_sc_dev *dev,
3754 struct i40iw_update_sds_info *info,
3755 u64 scratch)
3756 {
3757 struct i40iw_sc_cqp *cqp = dev->cqp;
3758 enum i40iw_status_code ret_code;
3759
3760 ret_code = cqp_sds_wqe_fill(cqp, info, scratch);
3761 if (!ret_code)
3762 i40iw_sc_cqp_post_sq(cqp);
3763
3764 return ret_code;
3765 }
3766
3767 /**
3768 * i40iw_update_sds_noccq - update sd before ccq created
3769 * @dev: sc device struct
3770 * @info: sd info for sd's
3771 */
i40iw_update_sds_noccq(struct i40iw_sc_dev * dev,struct i40iw_update_sds_info * info)3772 enum i40iw_status_code i40iw_update_sds_noccq(struct i40iw_sc_dev *dev,
3773 struct i40iw_update_sds_info *info)
3774 {
3775 u32 error, val, tail;
3776 struct i40iw_sc_cqp *cqp = dev->cqp;
3777 enum i40iw_status_code ret_code;
3778
3779 ret_code = cqp_sds_wqe_fill(cqp, info, 0);
3780 if (ret_code)
3781 return ret_code;
3782 i40iw_get_cqp_reg_info(cqp, &val, &tail, &error);
3783 if (error)
3784 return I40IW_ERR_CQP_COMPL_ERROR;
3785
3786 i40iw_sc_cqp_post_sq(cqp);
3787 ret_code = i40iw_cqp_poll_registers(cqp, tail, I40IW_DONE_COUNT);
3788
3789 return ret_code;
3790 }
3791
3792 /**
3793 * i40iw_sc_suspend_qp - suspend qp for param change
3794 * @cqp: struct for cqp hw
3795 * @qp: sc qp struct
3796 * @scratch: u64 saved to be used during cqp completion
3797 */
i40iw_sc_suspend_qp(struct i40iw_sc_cqp * cqp,struct i40iw_sc_qp * qp,u64 scratch)3798 enum i40iw_status_code i40iw_sc_suspend_qp(struct i40iw_sc_cqp *cqp,
3799 struct i40iw_sc_qp *qp,
3800 u64 scratch)
3801 {
3802 u64 header;
3803 u64 *wqe;
3804
3805 wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
3806 if (!wqe)
3807 return I40IW_ERR_RING_FULL;
3808 header = LS_64(qp->qp_uk.qp_id, I40IW_CQPSQ_SUSPENDQP_QPID) |
3809 LS_64(I40IW_CQP_OP_SUSPEND_QP, I40IW_CQPSQ_OPCODE) |
3810 LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
3811
3812 i40iw_insert_wqe_hdr(wqe, header);
3813
3814 i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "SUSPEND_QP WQE",
3815 wqe, I40IW_CQP_WQE_SIZE * 8);
3816
3817 i40iw_sc_cqp_post_sq(cqp);
3818 return 0;
3819 }
3820
3821 /**
3822 * i40iw_sc_resume_qp - resume qp after suspend
3823 * @cqp: struct for cqp hw
3824 * @qp: sc qp struct
3825 * @scratch: u64 saved to be used during cqp completion
3826 */
i40iw_sc_resume_qp(struct i40iw_sc_cqp * cqp,struct i40iw_sc_qp * qp,u64 scratch)3827 enum i40iw_status_code i40iw_sc_resume_qp(struct i40iw_sc_cqp *cqp,
3828 struct i40iw_sc_qp *qp,
3829 u64 scratch)
3830 {
3831 u64 header;
3832 u64 *wqe;
3833
3834 wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
3835 if (!wqe)
3836 return I40IW_ERR_RING_FULL;
3837 set_64bit_val(wqe,
3838 16,
3839 LS_64(qp->qs_handle, I40IW_CQPSQ_RESUMEQP_QSHANDLE));
3840
3841 header = LS_64(qp->qp_uk.qp_id, I40IW_CQPSQ_RESUMEQP_QPID) |
3842 LS_64(I40IW_CQP_OP_RESUME_QP, I40IW_CQPSQ_OPCODE) |
3843 LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
3844
3845 i40iw_insert_wqe_hdr(wqe, header);
3846
3847 i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "RESUME_QP WQE",
3848 wqe, I40IW_CQP_WQE_SIZE * 8);
3849
3850 i40iw_sc_cqp_post_sq(cqp);
3851 return 0;
3852 }
3853
3854 /**
3855 * i40iw_sc_static_hmc_pages_allocated - cqp wqe to allocate hmc pages
3856 * @cqp: struct for cqp hw
3857 * @scratch: u64 saved to be used during cqp completion
3858 * @hmc_fn_id: hmc function id
3859 * @post_sq: flag for cqp db to ring
3860 * @poll_registers: flag to poll register for cqp completion
3861 */
i40iw_sc_static_hmc_pages_allocated(struct i40iw_sc_cqp * cqp,u64 scratch,u8 hmc_fn_id,bool post_sq,bool poll_registers)3862 enum i40iw_status_code i40iw_sc_static_hmc_pages_allocated(
3863 struct i40iw_sc_cqp *cqp,
3864 u64 scratch,
3865 u8 hmc_fn_id,
3866 bool post_sq,
3867 bool poll_registers)
3868 {
3869 u64 header;
3870 u64 *wqe;
3871 u32 tail, val, error;
3872 enum i40iw_status_code ret_code = 0;
3873
3874 wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
3875 if (!wqe)
3876 return I40IW_ERR_RING_FULL;
3877 set_64bit_val(wqe,
3878 16,
3879 LS_64(hmc_fn_id, I40IW_SHMC_PAGE_ALLOCATED_HMC_FN_ID));
3880
3881 header = LS_64(I40IW_CQP_OP_SHMC_PAGES_ALLOCATED, I40IW_CQPSQ_OPCODE) |
3882 LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
3883
3884 i40iw_insert_wqe_hdr(wqe, header);
3885
3886 i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "SHMC_PAGES_ALLOCATED WQE",
3887 wqe, I40IW_CQP_WQE_SIZE * 8);
3888 i40iw_get_cqp_reg_info(cqp, &val, &tail, &error);
3889 if (error) {
3890 ret_code = I40IW_ERR_CQP_COMPL_ERROR;
3891 return ret_code;
3892 }
3893 if (post_sq) {
3894 i40iw_sc_cqp_post_sq(cqp);
3895 if (poll_registers)
3896 /* check for cqp sq tail update */
3897 ret_code = i40iw_cqp_poll_registers(cqp, tail, 1000);
3898 else
3899 ret_code = i40iw_sc_poll_for_cqp_op_done(cqp,
3900 I40IW_CQP_OP_SHMC_PAGES_ALLOCATED,
3901 NULL);
3902 }
3903
3904 return ret_code;
3905 }
3906
3907 /**
3908 * i40iw_ring_full - check if cqp ring is full
3909 * @cqp: struct for cqp hw
3910 */
i40iw_ring_full(struct i40iw_sc_cqp * cqp)3911 static bool i40iw_ring_full(struct i40iw_sc_cqp *cqp)
3912 {
3913 return I40IW_RING_FULL_ERR(cqp->sq_ring);
3914 }
3915
3916 /**
3917 * i40iw_est_sd - returns approximate number of SDs for HMC
3918 * @dev: sc device struct
3919 * @hmc_info: hmc structure, size and count for HMC objects
3920 */
i40iw_est_sd(struct i40iw_sc_dev * dev,struct i40iw_hmc_info * hmc_info)3921 static u64 i40iw_est_sd(struct i40iw_sc_dev *dev, struct i40iw_hmc_info *hmc_info)
3922 {
3923 int i;
3924 u64 size = 0;
3925 u64 sd;
3926
3927 for (i = I40IW_HMC_IW_QP; i < I40IW_HMC_IW_PBLE; i++)
3928 size += hmc_info->hmc_obj[i].cnt * hmc_info->hmc_obj[i].size;
3929
3930 if (dev->is_pf)
3931 size += hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt * hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].size;
3932
3933 if (size & 0x1FFFFF)
3934 sd = (size >> 21) + 1; /* add 1 for remainder */
3935 else
3936 sd = size >> 21;
3937
3938 if (!dev->is_pf) {
3939 /* 2MB alignment for VF PBLE HMC */
3940 size = hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt * hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].size;
3941 if (size & 0x1FFFFF)
3942 sd += (size >> 21) + 1; /* add 1 for remainder */
3943 else
3944 sd += size >> 21;
3945 }
3946
3947 return sd;
3948 }
3949
3950 /**
3951 * i40iw_config_fpm_values - configure HMC objects
3952 * @dev: sc device struct
3953 * @qp_count: desired qp count
3954 */
i40iw_config_fpm_values(struct i40iw_sc_dev * dev,u32 qp_count)3955 enum i40iw_status_code i40iw_config_fpm_values(struct i40iw_sc_dev *dev, u32 qp_count)
3956 {
3957 struct i40iw_virt_mem virt_mem;
3958 u32 i, mem_size;
3959 u32 qpwantedoriginal, qpwanted, mrwanted, pblewanted;
3960 u64 sd_needed;
3961 u32 loop_count = 0;
3962
3963 struct i40iw_hmc_info *hmc_info;
3964 struct i40iw_hmc_fpm_misc *hmc_fpm_misc;
3965 enum i40iw_status_code ret_code = 0;
3966
3967 hmc_info = dev->hmc_info;
3968 hmc_fpm_misc = &dev->hmc_fpm_misc;
3969
3970 ret_code = i40iw_sc_init_iw_hmc(dev, dev->hmc_fn_id);
3971 if (ret_code) {
3972 i40iw_debug(dev, I40IW_DEBUG_HMC,
3973 "i40iw_sc_init_iw_hmc returned error_code = %d\n",
3974 ret_code);
3975 return ret_code;
3976 }
3977
3978 for (i = I40IW_HMC_IW_QP; i < I40IW_HMC_IW_MAX; i++)
3979 hmc_info->hmc_obj[i].cnt = hmc_info->hmc_obj[i].max_cnt;
3980 sd_needed = i40iw_est_sd(dev, hmc_info);
3981 i40iw_debug(dev, I40IW_DEBUG_HMC,
3982 "%s: FW initial max sd_count[%08lld] first_sd_index[%04d]\n",
3983 __func__, sd_needed, hmc_info->first_sd_index);
3984 i40iw_debug(dev, I40IW_DEBUG_HMC,
3985 "%s: sd count %d where max sd is %d\n",
3986 __func__, hmc_info->sd_table.sd_cnt,
3987 hmc_fpm_misc->max_sds);
3988
3989 qpwanted = min(qp_count, hmc_info->hmc_obj[I40IW_HMC_IW_QP].max_cnt);
3990 qpwantedoriginal = qpwanted;
3991 mrwanted = hmc_info->hmc_obj[I40IW_HMC_IW_MR].max_cnt;
3992 pblewanted = hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].max_cnt;
3993
3994 i40iw_debug(dev, I40IW_DEBUG_HMC,
3995 "req_qp=%d max_sd=%d, max_qp = %d, max_cq=%d, max_mr=%d, max_pble=%d\n",
3996 qp_count, hmc_fpm_misc->max_sds,
3997 hmc_info->hmc_obj[I40IW_HMC_IW_QP].max_cnt,
3998 hmc_info->hmc_obj[I40IW_HMC_IW_CQ].max_cnt,
3999 hmc_info->hmc_obj[I40IW_HMC_IW_MR].max_cnt,
4000 hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].max_cnt);
4001
4002 do {
4003 ++loop_count;
4004 hmc_info->hmc_obj[I40IW_HMC_IW_QP].cnt = qpwanted;
4005 hmc_info->hmc_obj[I40IW_HMC_IW_CQ].cnt =
4006 min(2 * qpwanted, hmc_info->hmc_obj[I40IW_HMC_IW_CQ].cnt);
4007 hmc_info->hmc_obj[I40IW_HMC_IW_SRQ].cnt = 0x00; /* Reserved */
4008 hmc_info->hmc_obj[I40IW_HMC_IW_HTE].cnt =
4009 qpwanted * hmc_fpm_misc->ht_multiplier;
4010 hmc_info->hmc_obj[I40IW_HMC_IW_ARP].cnt =
4011 hmc_info->hmc_obj[I40IW_HMC_IW_ARP].max_cnt;
4012 hmc_info->hmc_obj[I40IW_HMC_IW_APBVT_ENTRY].cnt = 1;
4013 hmc_info->hmc_obj[I40IW_HMC_IW_MR].cnt = mrwanted;
4014
4015 hmc_info->hmc_obj[I40IW_HMC_IW_XF].cnt =
4016 roundup_pow_of_two(I40IW_MAX_WQ_ENTRIES * qpwanted);
4017 hmc_info->hmc_obj[I40IW_HMC_IW_Q1].cnt =
4018 roundup_pow_of_two(2 * I40IW_MAX_IRD_SIZE * qpwanted);
4019 hmc_info->hmc_obj[I40IW_HMC_IW_XFFL].cnt =
4020 hmc_info->hmc_obj[I40IW_HMC_IW_XF].cnt / hmc_fpm_misc->xf_block_size;
4021 hmc_info->hmc_obj[I40IW_HMC_IW_Q1FL].cnt =
4022 hmc_info->hmc_obj[I40IW_HMC_IW_Q1].cnt / hmc_fpm_misc->q1_block_size;
4023 hmc_info->hmc_obj[I40IW_HMC_IW_TIMER].cnt =
4024 ((qpwanted) / 512 + 1) * hmc_fpm_misc->timer_bucket;
4025 hmc_info->hmc_obj[I40IW_HMC_IW_FSIMC].cnt = 0x00;
4026 hmc_info->hmc_obj[I40IW_HMC_IW_FSIAV].cnt = 0x00;
4027 hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt = pblewanted;
4028
4029 /* How much memory is needed for all the objects. */
4030 sd_needed = i40iw_est_sd(dev, hmc_info);
4031 if ((loop_count > 1000) ||
4032 ((!(loop_count % 10)) &&
4033 (qpwanted > qpwantedoriginal * 2 / 3))) {
4034 if (qpwanted > FPM_MULTIPLIER)
4035 qpwanted = roundup_pow_of_two(qpwanted -
4036 FPM_MULTIPLIER);
4037 qpwanted >>= 1;
4038 }
4039 if (mrwanted > FPM_MULTIPLIER * 10)
4040 mrwanted -= FPM_MULTIPLIER * 10;
4041 if (pblewanted > FPM_MULTIPLIER * 1000)
4042 pblewanted -= FPM_MULTIPLIER * 1000;
4043 } while (sd_needed > hmc_fpm_misc->max_sds && loop_count < 2000);
4044
4045 i40iw_debug(dev, I40IW_DEBUG_HMC,
4046 "loop_cnt=%d, sd_needed=%lld, qpcnt = %d, cqcnt=%d, mrcnt=%d, pblecnt=%d\n",
4047 loop_count, sd_needed,
4048 hmc_info->hmc_obj[I40IW_HMC_IW_QP].cnt,
4049 hmc_info->hmc_obj[I40IW_HMC_IW_CQ].cnt,
4050 hmc_info->hmc_obj[I40IW_HMC_IW_MR].cnt,
4051 hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt);
4052
4053 ret_code = i40iw_sc_configure_iw_fpm(dev, dev->hmc_fn_id);
4054 if (ret_code) {
4055 i40iw_debug(dev, I40IW_DEBUG_HMC,
4056 "configure_iw_fpm returned error_code[x%08X]\n",
4057 i40iw_rd32(dev->hw, dev->is_pf ? I40E_PFPE_CQPERRCODES : I40E_VFPE_CQPERRCODES1));
4058 return ret_code;
4059 }
4060
4061 mem_size = sizeof(struct i40iw_hmc_sd_entry) *
4062 (hmc_info->sd_table.sd_cnt + hmc_info->first_sd_index + 1);
4063 ret_code = i40iw_allocate_virt_mem(dev->hw, &virt_mem, mem_size);
4064 if (ret_code) {
4065 i40iw_debug(dev, I40IW_DEBUG_HMC,
4066 "%s: failed to allocate memory for sd_entry buffer\n",
4067 __func__);
4068 return ret_code;
4069 }
4070 hmc_info->sd_table.sd_entry = virt_mem.va;
4071
4072 return ret_code;
4073 }
4074
4075 /**
4076 * i40iw_exec_cqp_cmd - execute cqp cmd when wqe are available
4077 * @dev: rdma device
4078 * @pcmdinfo: cqp command info
4079 */
i40iw_exec_cqp_cmd(struct i40iw_sc_dev * dev,struct cqp_commands_info * pcmdinfo)4080 static enum i40iw_status_code i40iw_exec_cqp_cmd(struct i40iw_sc_dev *dev,
4081 struct cqp_commands_info *pcmdinfo)
4082 {
4083 enum i40iw_status_code status;
4084 struct i40iw_dma_mem values_mem;
4085
4086 dev->cqp_cmd_stats[pcmdinfo->cqp_cmd]++;
4087 switch (pcmdinfo->cqp_cmd) {
4088 case OP_DELETE_LOCAL_MAC_IPADDR_ENTRY:
4089 status = i40iw_sc_del_local_mac_ipaddr_entry(
4090 pcmdinfo->in.u.del_local_mac_ipaddr_entry.cqp,
4091 pcmdinfo->in.u.del_local_mac_ipaddr_entry.scratch,
4092 pcmdinfo->in.u.del_local_mac_ipaddr_entry.entry_idx,
4093 pcmdinfo->in.u.del_local_mac_ipaddr_entry.ignore_ref_count,
4094 pcmdinfo->post_sq);
4095 break;
4096 case OP_CEQ_DESTROY:
4097 status = i40iw_sc_ceq_destroy(pcmdinfo->in.u.ceq_destroy.ceq,
4098 pcmdinfo->in.u.ceq_destroy.scratch,
4099 pcmdinfo->post_sq);
4100 break;
4101 case OP_AEQ_DESTROY:
4102 status = i40iw_sc_aeq_destroy(pcmdinfo->in.u.aeq_destroy.aeq,
4103 pcmdinfo->in.u.aeq_destroy.scratch,
4104 pcmdinfo->post_sq);
4105
4106 break;
4107 case OP_DELETE_ARP_CACHE_ENTRY:
4108 status = i40iw_sc_del_arp_cache_entry(
4109 pcmdinfo->in.u.del_arp_cache_entry.cqp,
4110 pcmdinfo->in.u.del_arp_cache_entry.scratch,
4111 pcmdinfo->in.u.del_arp_cache_entry.arp_index,
4112 pcmdinfo->post_sq);
4113 break;
4114 case OP_MANAGE_APBVT_ENTRY:
4115 status = i40iw_sc_manage_apbvt_entry(
4116 pcmdinfo->in.u.manage_apbvt_entry.cqp,
4117 &pcmdinfo->in.u.manage_apbvt_entry.info,
4118 pcmdinfo->in.u.manage_apbvt_entry.scratch,
4119 pcmdinfo->post_sq);
4120 break;
4121 case OP_CEQ_CREATE:
4122 status = i40iw_sc_ceq_create(pcmdinfo->in.u.ceq_create.ceq,
4123 pcmdinfo->in.u.ceq_create.scratch,
4124 pcmdinfo->post_sq);
4125 break;
4126 case OP_AEQ_CREATE:
4127 status = i40iw_sc_aeq_create(pcmdinfo->in.u.aeq_create.aeq,
4128 pcmdinfo->in.u.aeq_create.scratch,
4129 pcmdinfo->post_sq);
4130 break;
4131 case OP_ALLOC_LOCAL_MAC_IPADDR_ENTRY:
4132 status = i40iw_sc_alloc_local_mac_ipaddr_entry(
4133 pcmdinfo->in.u.alloc_local_mac_ipaddr_entry.cqp,
4134 pcmdinfo->in.u.alloc_local_mac_ipaddr_entry.scratch,
4135 pcmdinfo->post_sq);
4136 break;
4137 case OP_ADD_LOCAL_MAC_IPADDR_ENTRY:
4138 status = i40iw_sc_add_local_mac_ipaddr_entry(
4139 pcmdinfo->in.u.add_local_mac_ipaddr_entry.cqp,
4140 &pcmdinfo->in.u.add_local_mac_ipaddr_entry.info,
4141 pcmdinfo->in.u.add_local_mac_ipaddr_entry.scratch,
4142 pcmdinfo->post_sq);
4143 break;
4144 case OP_MANAGE_QHASH_TABLE_ENTRY:
4145 status = i40iw_sc_manage_qhash_table_entry(
4146 pcmdinfo->in.u.manage_qhash_table_entry.cqp,
4147 &pcmdinfo->in.u.manage_qhash_table_entry.info,
4148 pcmdinfo->in.u.manage_qhash_table_entry.scratch,
4149 pcmdinfo->post_sq);
4150
4151 break;
4152 case OP_QP_MODIFY:
4153 status = i40iw_sc_qp_modify(
4154 pcmdinfo->in.u.qp_modify.qp,
4155 &pcmdinfo->in.u.qp_modify.info,
4156 pcmdinfo->in.u.qp_modify.scratch,
4157 pcmdinfo->post_sq);
4158
4159 break;
4160 case OP_QP_UPLOAD_CONTEXT:
4161 status = i40iw_sc_qp_upload_context(
4162 pcmdinfo->in.u.qp_upload_context.dev,
4163 &pcmdinfo->in.u.qp_upload_context.info,
4164 pcmdinfo->in.u.qp_upload_context.scratch,
4165 pcmdinfo->post_sq);
4166
4167 break;
4168 case OP_CQ_CREATE:
4169 status = i40iw_sc_cq_create(
4170 pcmdinfo->in.u.cq_create.cq,
4171 pcmdinfo->in.u.cq_create.scratch,
4172 pcmdinfo->in.u.cq_create.check_overflow,
4173 pcmdinfo->post_sq);
4174 break;
4175 case OP_CQ_DESTROY:
4176 status = i40iw_sc_cq_destroy(
4177 pcmdinfo->in.u.cq_destroy.cq,
4178 pcmdinfo->in.u.cq_destroy.scratch,
4179 pcmdinfo->post_sq);
4180
4181 break;
4182 case OP_QP_CREATE:
4183 status = i40iw_sc_qp_create(
4184 pcmdinfo->in.u.qp_create.qp,
4185 &pcmdinfo->in.u.qp_create.info,
4186 pcmdinfo->in.u.qp_create.scratch,
4187 pcmdinfo->post_sq);
4188 break;
4189 case OP_QP_DESTROY:
4190 status = i40iw_sc_qp_destroy(
4191 pcmdinfo->in.u.qp_destroy.qp,
4192 pcmdinfo->in.u.qp_destroy.scratch,
4193 pcmdinfo->in.u.qp_destroy.remove_hash_idx,
4194 pcmdinfo->in.u.qp_destroy.
4195 ignore_mw_bnd,
4196 pcmdinfo->post_sq);
4197
4198 break;
4199 case OP_ALLOC_STAG:
4200 status = i40iw_sc_alloc_stag(
4201 pcmdinfo->in.u.alloc_stag.dev,
4202 &pcmdinfo->in.u.alloc_stag.info,
4203 pcmdinfo->in.u.alloc_stag.scratch,
4204 pcmdinfo->post_sq);
4205 break;
4206 case OP_MR_REG_NON_SHARED:
4207 status = i40iw_sc_mr_reg_non_shared(
4208 pcmdinfo->in.u.mr_reg_non_shared.dev,
4209 &pcmdinfo->in.u.mr_reg_non_shared.info,
4210 pcmdinfo->in.u.mr_reg_non_shared.scratch,
4211 pcmdinfo->post_sq);
4212
4213 break;
4214 case OP_DEALLOC_STAG:
4215 status = i40iw_sc_dealloc_stag(
4216 pcmdinfo->in.u.dealloc_stag.dev,
4217 &pcmdinfo->in.u.dealloc_stag.info,
4218 pcmdinfo->in.u.dealloc_stag.scratch,
4219 pcmdinfo->post_sq);
4220
4221 break;
4222 case OP_MW_ALLOC:
4223 status = i40iw_sc_mw_alloc(
4224 pcmdinfo->in.u.mw_alloc.dev,
4225 pcmdinfo->in.u.mw_alloc.scratch,
4226 pcmdinfo->in.u.mw_alloc.mw_stag_index,
4227 pcmdinfo->in.u.mw_alloc.pd_id,
4228 pcmdinfo->post_sq);
4229
4230 break;
4231 case OP_QP_FLUSH_WQES:
4232 status = i40iw_sc_qp_flush_wqes(
4233 pcmdinfo->in.u.qp_flush_wqes.qp,
4234 &pcmdinfo->in.u.qp_flush_wqes.info,
4235 pcmdinfo->in.u.qp_flush_wqes.
4236 scratch, pcmdinfo->post_sq);
4237 break;
4238 case OP_GEN_AE:
4239 status = i40iw_sc_gen_ae(
4240 pcmdinfo->in.u.gen_ae.qp,
4241 &pcmdinfo->in.u.gen_ae.info,
4242 pcmdinfo->in.u.gen_ae.scratch,
4243 pcmdinfo->post_sq);
4244 break;
4245 case OP_ADD_ARP_CACHE_ENTRY:
4246 status = i40iw_sc_add_arp_cache_entry(
4247 pcmdinfo->in.u.add_arp_cache_entry.cqp,
4248 &pcmdinfo->in.u.add_arp_cache_entry.info,
4249 pcmdinfo->in.u.add_arp_cache_entry.scratch,
4250 pcmdinfo->post_sq);
4251 break;
4252 case OP_UPDATE_PE_SDS:
4253 /* case I40IW_CQP_OP_UPDATE_PE_SDS */
4254 status = i40iw_update_pe_sds(
4255 pcmdinfo->in.u.update_pe_sds.dev,
4256 &pcmdinfo->in.u.update_pe_sds.info,
4257 pcmdinfo->in.u.update_pe_sds.
4258 scratch);
4259
4260 break;
4261 case OP_MANAGE_HMC_PM_FUNC_TABLE:
4262 status = i40iw_sc_manage_hmc_pm_func_table(
4263 pcmdinfo->in.u.manage_hmc_pm.dev->cqp,
4264 pcmdinfo->in.u.manage_hmc_pm.scratch,
4265 (u8)pcmdinfo->in.u.manage_hmc_pm.info.vf_id,
4266 pcmdinfo->in.u.manage_hmc_pm.info.free_fcn,
4267 true);
4268 break;
4269 case OP_SUSPEND:
4270 status = i40iw_sc_suspend_qp(
4271 pcmdinfo->in.u.suspend_resume.cqp,
4272 pcmdinfo->in.u.suspend_resume.qp,
4273 pcmdinfo->in.u.suspend_resume.scratch);
4274 break;
4275 case OP_RESUME:
4276 status = i40iw_sc_resume_qp(
4277 pcmdinfo->in.u.suspend_resume.cqp,
4278 pcmdinfo->in.u.suspend_resume.qp,
4279 pcmdinfo->in.u.suspend_resume.scratch);
4280 break;
4281 case OP_MANAGE_VF_PBLE_BP:
4282 status = i40iw_manage_vf_pble_bp(
4283 pcmdinfo->in.u.manage_vf_pble_bp.cqp,
4284 &pcmdinfo->in.u.manage_vf_pble_bp.info,
4285 pcmdinfo->in.u.manage_vf_pble_bp.scratch, true);
4286 break;
4287 case OP_QUERY_FPM_VALUES:
4288 values_mem.pa = pcmdinfo->in.u.query_fpm_values.fpm_values_pa;
4289 values_mem.va = pcmdinfo->in.u.query_fpm_values.fpm_values_va;
4290 status = i40iw_sc_query_fpm_values(
4291 pcmdinfo->in.u.query_fpm_values.cqp,
4292 pcmdinfo->in.u.query_fpm_values.scratch,
4293 pcmdinfo->in.u.query_fpm_values.hmc_fn_id,
4294 &values_mem, true, I40IW_CQP_WAIT_EVENT);
4295 break;
4296 case OP_COMMIT_FPM_VALUES:
4297 values_mem.pa = pcmdinfo->in.u.commit_fpm_values.fpm_values_pa;
4298 values_mem.va = pcmdinfo->in.u.commit_fpm_values.fpm_values_va;
4299 status = i40iw_sc_commit_fpm_values(
4300 pcmdinfo->in.u.commit_fpm_values.cqp,
4301 pcmdinfo->in.u.commit_fpm_values.scratch,
4302 pcmdinfo->in.u.commit_fpm_values.hmc_fn_id,
4303 &values_mem,
4304 true,
4305 I40IW_CQP_WAIT_EVENT);
4306 break;
4307 case OP_QUERY_RDMA_FEATURES:
4308 values_mem.pa = pcmdinfo->in.u.query_rdma_features.cap_pa;
4309 values_mem.va = pcmdinfo->in.u.query_rdma_features.cap_va;
4310 status = i40iw_sc_query_rdma_features(
4311 pcmdinfo->in.u.query_rdma_features.cqp, &values_mem,
4312 pcmdinfo->in.u.query_rdma_features.scratch);
4313 break;
4314 default:
4315 status = I40IW_NOT_SUPPORTED;
4316 break;
4317 }
4318
4319 return status;
4320 }
4321
4322 /**
4323 * i40iw_process_cqp_cmd - process all cqp commands
4324 * @dev: sc device struct
4325 * @pcmdinfo: cqp command info
4326 */
i40iw_process_cqp_cmd(struct i40iw_sc_dev * dev,struct cqp_commands_info * pcmdinfo)4327 enum i40iw_status_code i40iw_process_cqp_cmd(struct i40iw_sc_dev *dev,
4328 struct cqp_commands_info *pcmdinfo)
4329 {
4330 enum i40iw_status_code status = 0;
4331 unsigned long flags;
4332
4333 spin_lock_irqsave(&dev->cqp_lock, flags);
4334 if (list_empty(&dev->cqp_cmd_head) && !i40iw_ring_full(dev->cqp))
4335 status = i40iw_exec_cqp_cmd(dev, pcmdinfo);
4336 else
4337 list_add_tail(&pcmdinfo->cqp_cmd_entry, &dev->cqp_cmd_head);
4338 spin_unlock_irqrestore(&dev->cqp_lock, flags);
4339 return status;
4340 }
4341
4342 /**
4343 * i40iw_process_bh - called from tasklet for cqp list
4344 * @dev: sc device struct
4345 */
i40iw_process_bh(struct i40iw_sc_dev * dev)4346 enum i40iw_status_code i40iw_process_bh(struct i40iw_sc_dev *dev)
4347 {
4348 enum i40iw_status_code status = 0;
4349 struct cqp_commands_info *pcmdinfo;
4350 unsigned long flags;
4351
4352 spin_lock_irqsave(&dev->cqp_lock, flags);
4353 while (!list_empty(&dev->cqp_cmd_head) && !i40iw_ring_full(dev->cqp)) {
4354 pcmdinfo = (struct cqp_commands_info *)i40iw_remove_head(&dev->cqp_cmd_head);
4355
4356 status = i40iw_exec_cqp_cmd(dev, pcmdinfo);
4357 if (status)
4358 break;
4359 }
4360 spin_unlock_irqrestore(&dev->cqp_lock, flags);
4361 return status;
4362 }
4363
4364 /**
4365 * i40iw_iwarp_opcode - determine if incoming is rdma layer
4366 * @info: aeq info for the packet
4367 * @pkt: packet for error
4368 */
i40iw_iwarp_opcode(struct i40iw_aeqe_info * info,u8 * pkt)4369 static u32 i40iw_iwarp_opcode(struct i40iw_aeqe_info *info, u8 *pkt)
4370 {
4371 __be16 *mpa;
4372 u32 opcode = 0xffffffff;
4373
4374 if (info->q2_data_written) {
4375 mpa = (__be16 *)pkt;
4376 opcode = ntohs(mpa[1]) & 0xf;
4377 }
4378 return opcode;
4379 }
4380
4381 /**
4382 * i40iw_locate_mpa - return pointer to mpa in the pkt
4383 * @pkt: packet with data
4384 */
i40iw_locate_mpa(u8 * pkt)4385 static u8 *i40iw_locate_mpa(u8 *pkt)
4386 {
4387 /* skip over ethernet header */
4388 pkt += I40IW_MAC_HLEN;
4389
4390 /* Skip over IP and TCP headers */
4391 pkt += 4 * (pkt[0] & 0x0f);
4392 pkt += 4 * ((pkt[12] >> 4) & 0x0f);
4393 return pkt;
4394 }
4395
4396 /**
4397 * i40iw_setup_termhdr - termhdr for terminate pkt
4398 * @qp: sc qp ptr for pkt
4399 * @hdr: term hdr
4400 * @opcode: flush opcode for termhdr
4401 * @layer_etype: error layer + error type
4402 * @err: error cod ein the header
4403 */
i40iw_setup_termhdr(struct i40iw_sc_qp * qp,struct i40iw_terminate_hdr * hdr,enum i40iw_flush_opcode opcode,u8 layer_etype,u8 err)4404 static void i40iw_setup_termhdr(struct i40iw_sc_qp *qp,
4405 struct i40iw_terminate_hdr *hdr,
4406 enum i40iw_flush_opcode opcode,
4407 u8 layer_etype,
4408 u8 err)
4409 {
4410 qp->flush_code = opcode;
4411 hdr->layer_etype = layer_etype;
4412 hdr->error_code = err;
4413 }
4414
4415 /**
4416 * i40iw_bld_terminate_hdr - build terminate message header
4417 * @qp: qp associated with received terminate AE
4418 * @info: the struct contiaing AE information
4419 */
i40iw_bld_terminate_hdr(struct i40iw_sc_qp * qp,struct i40iw_aeqe_info * info)4420 static int i40iw_bld_terminate_hdr(struct i40iw_sc_qp *qp,
4421 struct i40iw_aeqe_info *info)
4422 {
4423 u8 *pkt = qp->q2_buf + Q2_BAD_FRAME_OFFSET;
4424 u16 ddp_seg_len;
4425 int copy_len = 0;
4426 u8 is_tagged = 0;
4427 u32 opcode;
4428 struct i40iw_terminate_hdr *termhdr;
4429
4430 termhdr = (struct i40iw_terminate_hdr *)qp->q2_buf;
4431 memset(termhdr, 0, Q2_BAD_FRAME_OFFSET);
4432
4433 if (info->q2_data_written) {
4434 /* Use data from offending packet to fill in ddp & rdma hdrs */
4435 pkt = i40iw_locate_mpa(pkt);
4436 ddp_seg_len = ntohs(*(__be16 *)pkt);
4437 if (ddp_seg_len) {
4438 copy_len = 2;
4439 termhdr->hdrct = DDP_LEN_FLAG;
4440 if (pkt[2] & 0x80) {
4441 is_tagged = 1;
4442 if (ddp_seg_len >= TERM_DDP_LEN_TAGGED) {
4443 copy_len += TERM_DDP_LEN_TAGGED;
4444 termhdr->hdrct |= DDP_HDR_FLAG;
4445 }
4446 } else {
4447 if (ddp_seg_len >= TERM_DDP_LEN_UNTAGGED) {
4448 copy_len += TERM_DDP_LEN_UNTAGGED;
4449 termhdr->hdrct |= DDP_HDR_FLAG;
4450 }
4451
4452 if (ddp_seg_len >= (TERM_DDP_LEN_UNTAGGED + TERM_RDMA_LEN)) {
4453 if ((pkt[3] & RDMA_OPCODE_MASK) == RDMA_READ_REQ_OPCODE) {
4454 copy_len += TERM_RDMA_LEN;
4455 termhdr->hdrct |= RDMA_HDR_FLAG;
4456 }
4457 }
4458 }
4459 }
4460 }
4461
4462 opcode = i40iw_iwarp_opcode(info, pkt);
4463
4464 switch (info->ae_id) {
4465 case I40IW_AE_AMP_UNALLOCATED_STAG:
4466 qp->eventtype = TERM_EVENT_QP_ACCESS_ERR;
4467 if (opcode == I40IW_OP_TYPE_RDMA_WRITE)
4468 i40iw_setup_termhdr(qp, termhdr, FLUSH_PROT_ERR,
4469 (LAYER_DDP << 4) | DDP_TAGGED_BUFFER, DDP_TAGGED_INV_STAG);
4470 else
4471 i40iw_setup_termhdr(qp, termhdr, FLUSH_REM_ACCESS_ERR,
4472 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, RDMAP_INV_STAG);
4473 break;
4474 case I40IW_AE_AMP_BOUNDS_VIOLATION:
4475 qp->eventtype = TERM_EVENT_QP_ACCESS_ERR;
4476 if (info->q2_data_written)
4477 i40iw_setup_termhdr(qp, termhdr, FLUSH_PROT_ERR,
4478 (LAYER_DDP << 4) | DDP_TAGGED_BUFFER, DDP_TAGGED_BOUNDS);
4479 else
4480 i40iw_setup_termhdr(qp, termhdr, FLUSH_REM_ACCESS_ERR,
4481 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, RDMAP_INV_BOUNDS);
4482 break;
4483 case I40IW_AE_AMP_BAD_PD:
4484 switch (opcode) {
4485 case I40IW_OP_TYPE_RDMA_WRITE:
4486 i40iw_setup_termhdr(qp, termhdr, FLUSH_PROT_ERR,
4487 (LAYER_DDP << 4) | DDP_TAGGED_BUFFER, DDP_TAGGED_UNASSOC_STAG);
4488 break;
4489 case I40IW_OP_TYPE_SEND_INV:
4490 case I40IW_OP_TYPE_SEND_SOL_INV:
4491 i40iw_setup_termhdr(qp, termhdr, FLUSH_REM_ACCESS_ERR,
4492 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, RDMAP_CANT_INV_STAG);
4493 break;
4494 default:
4495 i40iw_setup_termhdr(qp, termhdr, FLUSH_REM_ACCESS_ERR,
4496 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, RDMAP_UNASSOC_STAG);
4497 }
4498 break;
4499 case I40IW_AE_AMP_INVALID_STAG:
4500 qp->eventtype = TERM_EVENT_QP_ACCESS_ERR;
4501 i40iw_setup_termhdr(qp, termhdr, FLUSH_REM_ACCESS_ERR,
4502 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, RDMAP_INV_STAG);
4503 break;
4504 case I40IW_AE_AMP_BAD_QP:
4505 i40iw_setup_termhdr(qp, termhdr, FLUSH_LOC_QP_OP_ERR,
4506 (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER, DDP_UNTAGGED_INV_QN);
4507 break;
4508 case I40IW_AE_AMP_BAD_STAG_KEY:
4509 case I40IW_AE_AMP_BAD_STAG_INDEX:
4510 qp->eventtype = TERM_EVENT_QP_ACCESS_ERR;
4511 switch (opcode) {
4512 case I40IW_OP_TYPE_SEND_INV:
4513 case I40IW_OP_TYPE_SEND_SOL_INV:
4514 i40iw_setup_termhdr(qp, termhdr, FLUSH_REM_OP_ERR,
4515 (LAYER_RDMA << 4) | RDMAP_REMOTE_OP, RDMAP_CANT_INV_STAG);
4516 break;
4517 default:
4518 i40iw_setup_termhdr(qp, termhdr, FLUSH_REM_ACCESS_ERR,
4519 (LAYER_RDMA << 4) | RDMAP_REMOTE_OP, RDMAP_INV_STAG);
4520 }
4521 break;
4522 case I40IW_AE_AMP_RIGHTS_VIOLATION:
4523 case I40IW_AE_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS:
4524 case I40IW_AE_PRIV_OPERATION_DENIED:
4525 qp->eventtype = TERM_EVENT_QP_ACCESS_ERR;
4526 i40iw_setup_termhdr(qp, termhdr, FLUSH_REM_ACCESS_ERR,
4527 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, RDMAP_ACCESS);
4528 break;
4529 case I40IW_AE_AMP_TO_WRAP:
4530 qp->eventtype = TERM_EVENT_QP_ACCESS_ERR;
4531 i40iw_setup_termhdr(qp, termhdr, FLUSH_REM_ACCESS_ERR,
4532 (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, RDMAP_TO_WRAP);
4533 break;
4534 case I40IW_AE_LLP_RECEIVED_MPA_CRC_ERROR:
4535 i40iw_setup_termhdr(qp, termhdr, FLUSH_GENERAL_ERR,
4536 (LAYER_MPA << 4) | DDP_LLP, MPA_CRC);
4537 break;
4538 case I40IW_AE_LLP_SEGMENT_TOO_LARGE:
4539 case I40IW_AE_LLP_SEGMENT_TOO_SMALL:
4540 i40iw_setup_termhdr(qp, termhdr, FLUSH_LOC_LEN_ERR,
4541 (LAYER_DDP << 4) | DDP_CATASTROPHIC, DDP_CATASTROPHIC_LOCAL);
4542 break;
4543 case I40IW_AE_LCE_QP_CATASTROPHIC:
4544 case I40IW_AE_DDP_NO_L_BIT:
4545 i40iw_setup_termhdr(qp, termhdr, FLUSH_FATAL_ERR,
4546 (LAYER_DDP << 4) | DDP_CATASTROPHIC, DDP_CATASTROPHIC_LOCAL);
4547 break;
4548 case I40IW_AE_DDP_INVALID_MSN_GAP_IN_MSN:
4549 i40iw_setup_termhdr(qp, termhdr, FLUSH_GENERAL_ERR,
4550 (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER, DDP_UNTAGGED_INV_MSN_RANGE);
4551 break;
4552 case I40IW_AE_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER:
4553 qp->eventtype = TERM_EVENT_QP_ACCESS_ERR;
4554 i40iw_setup_termhdr(qp, termhdr, FLUSH_LOC_LEN_ERR,
4555 (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER, DDP_UNTAGGED_INV_TOO_LONG);
4556 break;
4557 case I40IW_AE_DDP_UBE_INVALID_DDP_VERSION:
4558 if (is_tagged)
4559 i40iw_setup_termhdr(qp, termhdr, FLUSH_GENERAL_ERR,
4560 (LAYER_DDP << 4) | DDP_TAGGED_BUFFER, DDP_TAGGED_INV_DDP_VER);
4561 else
4562 i40iw_setup_termhdr(qp, termhdr, FLUSH_GENERAL_ERR,
4563 (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER, DDP_UNTAGGED_INV_DDP_VER);
4564 break;
4565 case I40IW_AE_DDP_UBE_INVALID_MO:
4566 i40iw_setup_termhdr(qp, termhdr, FLUSH_GENERAL_ERR,
4567 (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER, DDP_UNTAGGED_INV_MO);
4568 break;
4569 case I40IW_AE_DDP_UBE_INVALID_MSN_NO_BUFFER_AVAILABLE:
4570 i40iw_setup_termhdr(qp, termhdr, FLUSH_REM_OP_ERR,
4571 (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER, DDP_UNTAGGED_INV_MSN_NO_BUF);
4572 break;
4573 case I40IW_AE_DDP_UBE_INVALID_QN:
4574 i40iw_setup_termhdr(qp, termhdr, FLUSH_GENERAL_ERR,
4575 (LAYER_DDP << 4) | DDP_UNTAGGED_BUFFER, DDP_UNTAGGED_INV_QN);
4576 break;
4577 case I40IW_AE_RDMAP_ROE_INVALID_RDMAP_VERSION:
4578 i40iw_setup_termhdr(qp, termhdr, FLUSH_GENERAL_ERR,
4579 (LAYER_RDMA << 4) | RDMAP_REMOTE_OP, RDMAP_INV_RDMAP_VER);
4580 break;
4581 case I40IW_AE_RDMAP_ROE_UNEXPECTED_OPCODE:
4582 i40iw_setup_termhdr(qp, termhdr, FLUSH_LOC_QP_OP_ERR,
4583 (LAYER_RDMA << 4) | RDMAP_REMOTE_OP, RDMAP_UNEXPECTED_OP);
4584 break;
4585 default:
4586 i40iw_setup_termhdr(qp, termhdr, FLUSH_FATAL_ERR,
4587 (LAYER_RDMA << 4) | RDMAP_REMOTE_OP, RDMAP_UNSPECIFIED);
4588 break;
4589 }
4590
4591 if (copy_len)
4592 memcpy(termhdr + 1, pkt, copy_len);
4593
4594 return sizeof(struct i40iw_terminate_hdr) + copy_len;
4595 }
4596
4597 /**
4598 * i40iw_terminate_send_fin() - Send fin for terminate message
4599 * @qp: qp associated with received terminate AE
4600 */
i40iw_terminate_send_fin(struct i40iw_sc_qp * qp)4601 void i40iw_terminate_send_fin(struct i40iw_sc_qp *qp)
4602 {
4603 /* Send the fin only */
4604 i40iw_term_modify_qp(qp,
4605 I40IW_QP_STATE_TERMINATE,
4606 I40IWQP_TERM_SEND_FIN_ONLY,
4607 0);
4608 }
4609
4610 /**
4611 * i40iw_terminate_connection() - Bad AE and send terminate to remote QP
4612 * @qp: qp associated with received terminate AE
4613 * @info: the struct contiaing AE information
4614 */
i40iw_terminate_connection(struct i40iw_sc_qp * qp,struct i40iw_aeqe_info * info)4615 void i40iw_terminate_connection(struct i40iw_sc_qp *qp, struct i40iw_aeqe_info *info)
4616 {
4617 u8 termlen = 0;
4618
4619 if (qp->term_flags & I40IW_TERM_SENT)
4620 return; /* Sanity check */
4621
4622 /* Eventtype can change from bld_terminate_hdr */
4623 qp->eventtype = TERM_EVENT_QP_FATAL;
4624 termlen = i40iw_bld_terminate_hdr(qp, info);
4625 i40iw_terminate_start_timer(qp);
4626 qp->term_flags |= I40IW_TERM_SENT;
4627 i40iw_term_modify_qp(qp, I40IW_QP_STATE_TERMINATE,
4628 I40IWQP_TERM_SEND_TERM_ONLY, termlen);
4629 }
4630
4631 /**
4632 * i40iw_terminate_received - handle terminate received AE
4633 * @qp: qp associated with received terminate AE
4634 * @info: the struct contiaing AE information
4635 */
i40iw_terminate_received(struct i40iw_sc_qp * qp,struct i40iw_aeqe_info * info)4636 void i40iw_terminate_received(struct i40iw_sc_qp *qp, struct i40iw_aeqe_info *info)
4637 {
4638 u8 *pkt = qp->q2_buf + Q2_BAD_FRAME_OFFSET;
4639 __be32 *mpa;
4640 u8 ddp_ctl;
4641 u8 rdma_ctl;
4642 u16 aeq_id = 0;
4643 struct i40iw_terminate_hdr *termhdr;
4644
4645 mpa = (__be32 *)i40iw_locate_mpa(pkt);
4646 if (info->q2_data_written) {
4647 /* did not validate the frame - do it now */
4648 ddp_ctl = (ntohl(mpa[0]) >> 8) & 0xff;
4649 rdma_ctl = ntohl(mpa[0]) & 0xff;
4650 if ((ddp_ctl & 0xc0) != 0x40)
4651 aeq_id = I40IW_AE_LCE_QP_CATASTROPHIC;
4652 else if ((ddp_ctl & 0x03) != 1)
4653 aeq_id = I40IW_AE_DDP_UBE_INVALID_DDP_VERSION;
4654 else if (ntohl(mpa[2]) != 2)
4655 aeq_id = I40IW_AE_DDP_UBE_INVALID_QN;
4656 else if (ntohl(mpa[3]) != 1)
4657 aeq_id = I40IW_AE_DDP_INVALID_MSN_GAP_IN_MSN;
4658 else if (ntohl(mpa[4]) != 0)
4659 aeq_id = I40IW_AE_DDP_UBE_INVALID_MO;
4660 else if ((rdma_ctl & 0xc0) != 0x40)
4661 aeq_id = I40IW_AE_RDMAP_ROE_INVALID_RDMAP_VERSION;
4662
4663 info->ae_id = aeq_id;
4664 if (info->ae_id) {
4665 /* Bad terminate recvd - send back a terminate */
4666 i40iw_terminate_connection(qp, info);
4667 return;
4668 }
4669 }
4670
4671 qp->term_flags |= I40IW_TERM_RCVD;
4672 qp->eventtype = TERM_EVENT_QP_FATAL;
4673 termhdr = (struct i40iw_terminate_hdr *)&mpa[5];
4674 if (termhdr->layer_etype == RDMAP_REMOTE_PROT ||
4675 termhdr->layer_etype == RDMAP_REMOTE_OP) {
4676 i40iw_terminate_done(qp, 0);
4677 } else {
4678 i40iw_terminate_start_timer(qp);
4679 i40iw_terminate_send_fin(qp);
4680 }
4681 }
4682
4683 /**
4684 * i40iw_sc_vsi_init - Initialize virtual device
4685 * @vsi: pointer to the vsi structure
4686 * @info: parameters to initialize vsi
4687 **/
i40iw_sc_vsi_init(struct i40iw_sc_vsi * vsi,struct i40iw_vsi_init_info * info)4688 void i40iw_sc_vsi_init(struct i40iw_sc_vsi *vsi, struct i40iw_vsi_init_info *info)
4689 {
4690 int i;
4691
4692 vsi->dev = info->dev;
4693 vsi->back_vsi = info->back_vsi;
4694 vsi->mtu = info->params->mtu;
4695 vsi->exception_lan_queue = info->exception_lan_queue;
4696 i40iw_fill_qos_list(info->params->qs_handle_list);
4697
4698 for (i = 0; i < I40IW_MAX_USER_PRIORITY; i++) {
4699 vsi->qos[i].qs_handle = info->params->qs_handle_list[i];
4700 i40iw_debug(vsi->dev, I40IW_DEBUG_DCB, "qset[%d]: %d\n", i,
4701 vsi->qos[i].qs_handle);
4702 spin_lock_init(&vsi->qos[i].lock);
4703 INIT_LIST_HEAD(&vsi->qos[i].qplist);
4704 }
4705 }
4706
4707 /**
4708 * i40iw_hw_stats_init - Initiliaze HW stats table
4709 * @stats: pestat struct
4710 * @fcn_idx: PCI fn id
4711 * @is_pf: Is it a PF?
4712 *
4713 * Populate the HW stats table with register offset addr for each
4714 * stats. And start the perioidic stats timer.
4715 */
i40iw_hw_stats_init(struct i40iw_vsi_pestat * stats,u8 fcn_idx,bool is_pf)4716 void i40iw_hw_stats_init(struct i40iw_vsi_pestat *stats, u8 fcn_idx, bool is_pf)
4717 {
4718 u32 stats_reg_offset;
4719 u32 stats_index;
4720 struct i40iw_dev_hw_stats_offsets *stats_table =
4721 &stats->hw_stats_offsets;
4722 struct i40iw_dev_hw_stats *last_rd_stats = &stats->last_read_hw_stats;
4723
4724 if (is_pf) {
4725 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP4RXDISCARD] =
4726 I40E_GLPES_PFIP4RXDISCARD(fcn_idx);
4727 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP4RXTRUNC] =
4728 I40E_GLPES_PFIP4RXTRUNC(fcn_idx);
4729 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP4TXNOROUTE] =
4730 I40E_GLPES_PFIP4TXNOROUTE(fcn_idx);
4731 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP6RXDISCARD] =
4732 I40E_GLPES_PFIP6RXDISCARD(fcn_idx);
4733 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP6RXTRUNC] =
4734 I40E_GLPES_PFIP6RXTRUNC(fcn_idx);
4735 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP6TXNOROUTE] =
4736 I40E_GLPES_PFIP6TXNOROUTE(fcn_idx);
4737 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_TCPRTXSEG] =
4738 I40E_GLPES_PFTCPRTXSEG(fcn_idx);
4739 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_TCPRXOPTERR] =
4740 I40E_GLPES_PFTCPRXOPTERR(fcn_idx);
4741 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_TCPRXPROTOERR] =
4742 I40E_GLPES_PFTCPRXPROTOERR(fcn_idx);
4743
4744 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4RXOCTS] =
4745 I40E_GLPES_PFIP4RXOCTSLO(fcn_idx);
4746 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4RXPKTS] =
4747 I40E_GLPES_PFIP4RXPKTSLO(fcn_idx);
4748 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4RXFRAGS] =
4749 I40E_GLPES_PFIP4RXFRAGSLO(fcn_idx);
4750 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4RXMCPKTS] =
4751 I40E_GLPES_PFIP4RXMCPKTSLO(fcn_idx);
4752 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4TXOCTS] =
4753 I40E_GLPES_PFIP4TXOCTSLO(fcn_idx);
4754 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4TXPKTS] =
4755 I40E_GLPES_PFIP4TXPKTSLO(fcn_idx);
4756 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4TXFRAGS] =
4757 I40E_GLPES_PFIP4TXFRAGSLO(fcn_idx);
4758 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4TXMCPKTS] =
4759 I40E_GLPES_PFIP4TXMCPKTSLO(fcn_idx);
4760 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6RXOCTS] =
4761 I40E_GLPES_PFIP6RXOCTSLO(fcn_idx);
4762 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6RXPKTS] =
4763 I40E_GLPES_PFIP6RXPKTSLO(fcn_idx);
4764 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6RXFRAGS] =
4765 I40E_GLPES_PFIP6RXFRAGSLO(fcn_idx);
4766 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6RXMCPKTS] =
4767 I40E_GLPES_PFIP6RXMCPKTSLO(fcn_idx);
4768 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6TXOCTS] =
4769 I40E_GLPES_PFIP6TXOCTSLO(fcn_idx);
4770 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6TXPKTS] =
4771 I40E_GLPES_PFIP6TXPKTSLO(fcn_idx);
4772 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6TXPKTS] =
4773 I40E_GLPES_PFIP6TXPKTSLO(fcn_idx);
4774 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6TXFRAGS] =
4775 I40E_GLPES_PFIP6TXFRAGSLO(fcn_idx);
4776 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_TCPRXSEGS] =
4777 I40E_GLPES_PFTCPRXSEGSLO(fcn_idx);
4778 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_TCPTXSEG] =
4779 I40E_GLPES_PFTCPTXSEGLO(fcn_idx);
4780 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMARXRDS] =
4781 I40E_GLPES_PFRDMARXRDSLO(fcn_idx);
4782 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMARXSNDS] =
4783 I40E_GLPES_PFRDMARXSNDSLO(fcn_idx);
4784 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMARXWRS] =
4785 I40E_GLPES_PFRDMARXWRSLO(fcn_idx);
4786 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMATXRDS] =
4787 I40E_GLPES_PFRDMATXRDSLO(fcn_idx);
4788 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMATXSNDS] =
4789 I40E_GLPES_PFRDMATXSNDSLO(fcn_idx);
4790 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMATXWRS] =
4791 I40E_GLPES_PFRDMATXWRSLO(fcn_idx);
4792 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMAVBND] =
4793 I40E_GLPES_PFRDMAVBNDLO(fcn_idx);
4794 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMAVINV] =
4795 I40E_GLPES_PFRDMAVINVLO(fcn_idx);
4796 } else {
4797 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP4RXDISCARD] =
4798 I40E_GLPES_VFIP4RXDISCARD(fcn_idx);
4799 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP4RXTRUNC] =
4800 I40E_GLPES_VFIP4RXTRUNC(fcn_idx);
4801 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP4TXNOROUTE] =
4802 I40E_GLPES_VFIP4TXNOROUTE(fcn_idx);
4803 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP6RXDISCARD] =
4804 I40E_GLPES_VFIP6RXDISCARD(fcn_idx);
4805 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP6RXTRUNC] =
4806 I40E_GLPES_VFIP6RXTRUNC(fcn_idx);
4807 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP6TXNOROUTE] =
4808 I40E_GLPES_VFIP6TXNOROUTE(fcn_idx);
4809 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_TCPRTXSEG] =
4810 I40E_GLPES_VFTCPRTXSEG(fcn_idx);
4811 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_TCPRXOPTERR] =
4812 I40E_GLPES_VFTCPRXOPTERR(fcn_idx);
4813 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_TCPRXPROTOERR] =
4814 I40E_GLPES_VFTCPRXPROTOERR(fcn_idx);
4815
4816 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4RXOCTS] =
4817 I40E_GLPES_VFIP4RXOCTSLO(fcn_idx);
4818 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4RXPKTS] =
4819 I40E_GLPES_VFIP4RXPKTSLO(fcn_idx);
4820 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4RXFRAGS] =
4821 I40E_GLPES_VFIP4RXFRAGSLO(fcn_idx);
4822 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4RXMCPKTS] =
4823 I40E_GLPES_VFIP4RXMCPKTSLO(fcn_idx);
4824 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4TXOCTS] =
4825 I40E_GLPES_VFIP4TXOCTSLO(fcn_idx);
4826 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4TXPKTS] =
4827 I40E_GLPES_VFIP4TXPKTSLO(fcn_idx);
4828 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4TXFRAGS] =
4829 I40E_GLPES_VFIP4TXFRAGSLO(fcn_idx);
4830 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4TXMCPKTS] =
4831 I40E_GLPES_VFIP4TXMCPKTSLO(fcn_idx);
4832 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6RXOCTS] =
4833 I40E_GLPES_VFIP6RXOCTSLO(fcn_idx);
4834 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6RXPKTS] =
4835 I40E_GLPES_VFIP6RXPKTSLO(fcn_idx);
4836 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6RXFRAGS] =
4837 I40E_GLPES_VFIP6RXFRAGSLO(fcn_idx);
4838 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6RXMCPKTS] =
4839 I40E_GLPES_VFIP6RXMCPKTSLO(fcn_idx);
4840 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6TXOCTS] =
4841 I40E_GLPES_VFIP6TXOCTSLO(fcn_idx);
4842 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6TXPKTS] =
4843 I40E_GLPES_VFIP6TXPKTSLO(fcn_idx);
4844 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6TXPKTS] =
4845 I40E_GLPES_VFIP6TXPKTSLO(fcn_idx);
4846 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6TXFRAGS] =
4847 I40E_GLPES_VFIP6TXFRAGSLO(fcn_idx);
4848 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_TCPRXSEGS] =
4849 I40E_GLPES_VFTCPRXSEGSLO(fcn_idx);
4850 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_TCPTXSEG] =
4851 I40E_GLPES_VFTCPTXSEGLO(fcn_idx);
4852 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMARXRDS] =
4853 I40E_GLPES_VFRDMARXRDSLO(fcn_idx);
4854 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMARXSNDS] =
4855 I40E_GLPES_VFRDMARXSNDSLO(fcn_idx);
4856 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMARXWRS] =
4857 I40E_GLPES_VFRDMARXWRSLO(fcn_idx);
4858 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMATXRDS] =
4859 I40E_GLPES_VFRDMATXRDSLO(fcn_idx);
4860 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMATXSNDS] =
4861 I40E_GLPES_VFRDMATXSNDSLO(fcn_idx);
4862 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMATXWRS] =
4863 I40E_GLPES_VFRDMATXWRSLO(fcn_idx);
4864 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMAVBND] =
4865 I40E_GLPES_VFRDMAVBNDLO(fcn_idx);
4866 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMAVINV] =
4867 I40E_GLPES_VFRDMAVINVLO(fcn_idx);
4868 }
4869
4870 for (stats_index = 0; stats_index < I40IW_HW_STAT_INDEX_MAX_64;
4871 stats_index++) {
4872 stats_reg_offset = stats_table->stats_offset_64[stats_index];
4873 last_rd_stats->stats_value_64[stats_index] =
4874 readq(stats->hw->hw_addr + stats_reg_offset);
4875 }
4876
4877 for (stats_index = 0; stats_index < I40IW_HW_STAT_INDEX_MAX_32;
4878 stats_index++) {
4879 stats_reg_offset = stats_table->stats_offset_32[stats_index];
4880 last_rd_stats->stats_value_32[stats_index] =
4881 i40iw_rd32(stats->hw, stats_reg_offset);
4882 }
4883 }
4884
4885 /**
4886 * i40iw_hw_stats_read_32 - Read 32-bit HW stats counters and accommodates for roll-overs.
4887 * @stats: pestat struct
4888 * @index: index in HW stats table which contains offset reg-addr
4889 * @value: hw stats value
4890 */
i40iw_hw_stats_read_32(struct i40iw_vsi_pestat * stats,enum i40iw_hw_stats_index_32b index,u64 * value)4891 void i40iw_hw_stats_read_32(struct i40iw_vsi_pestat *stats,
4892 enum i40iw_hw_stats_index_32b index,
4893 u64 *value)
4894 {
4895 struct i40iw_dev_hw_stats_offsets *stats_table =
4896 &stats->hw_stats_offsets;
4897 struct i40iw_dev_hw_stats *last_rd_stats = &stats->last_read_hw_stats;
4898 struct i40iw_dev_hw_stats *hw_stats = &stats->hw_stats;
4899 u64 new_stats_value = 0;
4900 u32 stats_reg_offset = stats_table->stats_offset_32[index];
4901
4902 new_stats_value = i40iw_rd32(stats->hw, stats_reg_offset);
4903 /*roll-over case */
4904 if (new_stats_value < last_rd_stats->stats_value_32[index])
4905 hw_stats->stats_value_32[index] += new_stats_value;
4906 else
4907 hw_stats->stats_value_32[index] +=
4908 new_stats_value - last_rd_stats->stats_value_32[index];
4909 last_rd_stats->stats_value_32[index] = new_stats_value;
4910 *value = hw_stats->stats_value_32[index];
4911 }
4912
4913 /**
4914 * i40iw_hw_stats_read_64 - Read HW stats counters (greater than 32-bit) and accommodates for roll-overs.
4915 * @stats: pestat struct
4916 * @index: index in HW stats table which contains offset reg-addr
4917 * @value: hw stats value
4918 */
i40iw_hw_stats_read_64(struct i40iw_vsi_pestat * stats,enum i40iw_hw_stats_index_64b index,u64 * value)4919 void i40iw_hw_stats_read_64(struct i40iw_vsi_pestat *stats,
4920 enum i40iw_hw_stats_index_64b index,
4921 u64 *value)
4922 {
4923 struct i40iw_dev_hw_stats_offsets *stats_table =
4924 &stats->hw_stats_offsets;
4925 struct i40iw_dev_hw_stats *last_rd_stats = &stats->last_read_hw_stats;
4926 struct i40iw_dev_hw_stats *hw_stats = &stats->hw_stats;
4927 u64 new_stats_value = 0;
4928 u32 stats_reg_offset = stats_table->stats_offset_64[index];
4929
4930 new_stats_value = readq(stats->hw->hw_addr + stats_reg_offset);
4931 /*roll-over case */
4932 if (new_stats_value < last_rd_stats->stats_value_64[index])
4933 hw_stats->stats_value_64[index] += new_stats_value;
4934 else
4935 hw_stats->stats_value_64[index] +=
4936 new_stats_value - last_rd_stats->stats_value_64[index];
4937 last_rd_stats->stats_value_64[index] = new_stats_value;
4938 *value = hw_stats->stats_value_64[index];
4939 }
4940
4941 /**
4942 * i40iw_hw_stats_read_all - read all HW stat counters
4943 * @stats: pestat struct
4944 * @stats_values: hw stats structure
4945 *
4946 * Read all the HW stat counters and populates hw_stats structure
4947 * of passed-in vsi's pestat as well as copy created in stat_values.
4948 */
i40iw_hw_stats_read_all(struct i40iw_vsi_pestat * stats,struct i40iw_dev_hw_stats * stats_values)4949 void i40iw_hw_stats_read_all(struct i40iw_vsi_pestat *stats,
4950 struct i40iw_dev_hw_stats *stats_values)
4951 {
4952 u32 stats_index;
4953 unsigned long flags;
4954
4955 spin_lock_irqsave(&stats->lock, flags);
4956
4957 for (stats_index = 0; stats_index < I40IW_HW_STAT_INDEX_MAX_32;
4958 stats_index++)
4959 i40iw_hw_stats_read_32(stats, stats_index,
4960 &stats_values->stats_value_32[stats_index]);
4961 for (stats_index = 0; stats_index < I40IW_HW_STAT_INDEX_MAX_64;
4962 stats_index++)
4963 i40iw_hw_stats_read_64(stats, stats_index,
4964 &stats_values->stats_value_64[stats_index]);
4965 spin_unlock_irqrestore(&stats->lock, flags);
4966 }
4967
4968 /**
4969 * i40iw_hw_stats_refresh_all - Update all HW stats structs
4970 * @stats: pestat struct
4971 *
4972 * Read all the HW stats counters to refresh values in hw_stats structure
4973 * of passed-in dev's pestat
4974 */
i40iw_hw_stats_refresh_all(struct i40iw_vsi_pestat * stats)4975 void i40iw_hw_stats_refresh_all(struct i40iw_vsi_pestat *stats)
4976 {
4977 u64 stats_value;
4978 u32 stats_index;
4979 unsigned long flags;
4980
4981 spin_lock_irqsave(&stats->lock, flags);
4982
4983 for (stats_index = 0; stats_index < I40IW_HW_STAT_INDEX_MAX_32;
4984 stats_index++)
4985 i40iw_hw_stats_read_32(stats, stats_index, &stats_value);
4986 for (stats_index = 0; stats_index < I40IW_HW_STAT_INDEX_MAX_64;
4987 stats_index++)
4988 i40iw_hw_stats_read_64(stats, stats_index, &stats_value);
4989 spin_unlock_irqrestore(&stats->lock, flags);
4990 }
4991
4992 /**
4993 * i40iw_get_fcn_id - Return the function id
4994 * @dev: pointer to the device
4995 */
i40iw_get_fcn_id(struct i40iw_sc_dev * dev)4996 static u8 i40iw_get_fcn_id(struct i40iw_sc_dev *dev)
4997 {
4998 u8 fcn_id = I40IW_INVALID_FCN_ID;
4999 u8 i;
5000
5001 for (i = I40IW_FIRST_NON_PF_STAT; i < I40IW_MAX_STATS_COUNT; i++)
5002 if (!dev->fcn_id_array[i]) {
5003 fcn_id = i;
5004 dev->fcn_id_array[i] = true;
5005 break;
5006 }
5007 return fcn_id;
5008 }
5009
5010 /**
5011 * i40iw_vsi_stats_init - Initialize the vsi statistics
5012 * @vsi: pointer to the vsi structure
5013 * @info: The info structure used for initialization
5014 */
i40iw_vsi_stats_init(struct i40iw_sc_vsi * vsi,struct i40iw_vsi_stats_info * info)5015 enum i40iw_status_code i40iw_vsi_stats_init(struct i40iw_sc_vsi *vsi, struct i40iw_vsi_stats_info *info)
5016 {
5017 u8 fcn_id = info->fcn_id;
5018
5019 if (info->alloc_fcn_id)
5020 fcn_id = i40iw_get_fcn_id(vsi->dev);
5021
5022 if (fcn_id == I40IW_INVALID_FCN_ID)
5023 return I40IW_ERR_NOT_READY;
5024
5025 vsi->pestat = info->pestat;
5026 vsi->pestat->hw = vsi->dev->hw;
5027 vsi->pestat->vsi = vsi;
5028
5029 if (info->stats_initialize) {
5030 i40iw_hw_stats_init(vsi->pestat, fcn_id, true);
5031 spin_lock_init(&vsi->pestat->lock);
5032 i40iw_hw_stats_start_timer(vsi);
5033 }
5034 vsi->stats_fcn_id_alloc = info->alloc_fcn_id;
5035 vsi->fcn_id = fcn_id;
5036 return I40IW_SUCCESS;
5037 }
5038
5039 /**
5040 * i40iw_vsi_stats_free - Free the vsi stats
5041 * @vsi: pointer to the vsi structure
5042 */
i40iw_vsi_stats_free(struct i40iw_sc_vsi * vsi)5043 void i40iw_vsi_stats_free(struct i40iw_sc_vsi *vsi)
5044 {
5045 u8 fcn_id = vsi->fcn_id;
5046
5047 if (vsi->stats_fcn_id_alloc && fcn_id < I40IW_MAX_STATS_COUNT)
5048 vsi->dev->fcn_id_array[fcn_id] = false;
5049 i40iw_hw_stats_stop_timer(vsi);
5050 }
5051
5052 static const struct i40iw_cqp_ops iw_cqp_ops = {
5053 .cqp_init = i40iw_sc_cqp_init,
5054 .cqp_create = i40iw_sc_cqp_create,
5055 .cqp_post_sq = i40iw_sc_cqp_post_sq,
5056 .cqp_get_next_send_wqe = i40iw_sc_cqp_get_next_send_wqe,
5057 .cqp_destroy = i40iw_sc_cqp_destroy,
5058 .poll_for_cqp_op_done = i40iw_sc_poll_for_cqp_op_done
5059 };
5060
5061 static const struct i40iw_ccq_ops iw_ccq_ops = {
5062 .ccq_init = i40iw_sc_ccq_init,
5063 .ccq_create = i40iw_sc_ccq_create,
5064 .ccq_destroy = i40iw_sc_ccq_destroy,
5065 .ccq_create_done = i40iw_sc_ccq_create_done,
5066 .ccq_get_cqe_info = i40iw_sc_ccq_get_cqe_info,
5067 .ccq_arm = i40iw_sc_ccq_arm
5068 };
5069
5070 static const struct i40iw_ceq_ops iw_ceq_ops = {
5071 .ceq_init = i40iw_sc_ceq_init,
5072 .ceq_create = i40iw_sc_ceq_create,
5073 .cceq_create_done = i40iw_sc_cceq_create_done,
5074 .cceq_destroy_done = i40iw_sc_cceq_destroy_done,
5075 .cceq_create = i40iw_sc_cceq_create,
5076 .ceq_destroy = i40iw_sc_ceq_destroy,
5077 .process_ceq = i40iw_sc_process_ceq
5078 };
5079
5080 static const struct i40iw_aeq_ops iw_aeq_ops = {
5081 .aeq_init = i40iw_sc_aeq_init,
5082 .aeq_create = i40iw_sc_aeq_create,
5083 .aeq_destroy = i40iw_sc_aeq_destroy,
5084 .get_next_aeqe = i40iw_sc_get_next_aeqe,
5085 .repost_aeq_entries = i40iw_sc_repost_aeq_entries,
5086 .aeq_create_done = i40iw_sc_aeq_create_done,
5087 .aeq_destroy_done = i40iw_sc_aeq_destroy_done
5088 };
5089
5090 /* iwarp pd ops */
5091 static const struct i40iw_pd_ops iw_pd_ops = {
5092 .pd_init = i40iw_sc_pd_init,
5093 };
5094
5095 static const struct i40iw_priv_qp_ops iw_priv_qp_ops = {
5096 .qp_init = i40iw_sc_qp_init,
5097 .qp_create = i40iw_sc_qp_create,
5098 .qp_modify = i40iw_sc_qp_modify,
5099 .qp_destroy = i40iw_sc_qp_destroy,
5100 .qp_flush_wqes = i40iw_sc_qp_flush_wqes,
5101 .qp_upload_context = i40iw_sc_qp_upload_context,
5102 .qp_setctx = i40iw_sc_qp_setctx,
5103 .qp_send_lsmm = i40iw_sc_send_lsmm,
5104 .qp_send_lsmm_nostag = i40iw_sc_send_lsmm_nostag,
5105 .qp_send_rtt = i40iw_sc_send_rtt,
5106 .qp_post_wqe0 = i40iw_sc_post_wqe0,
5107 .iw_mr_fast_register = i40iw_sc_mr_fast_register
5108 };
5109
5110 static const struct i40iw_priv_cq_ops iw_priv_cq_ops = {
5111 .cq_init = i40iw_sc_cq_init,
5112 .cq_create = i40iw_sc_cq_create,
5113 .cq_destroy = i40iw_sc_cq_destroy,
5114 .cq_modify = i40iw_sc_cq_modify,
5115 };
5116
5117 static const struct i40iw_mr_ops iw_mr_ops = {
5118 .alloc_stag = i40iw_sc_alloc_stag,
5119 .mr_reg_non_shared = i40iw_sc_mr_reg_non_shared,
5120 .mr_reg_shared = i40iw_sc_mr_reg_shared,
5121 .dealloc_stag = i40iw_sc_dealloc_stag,
5122 .query_stag = i40iw_sc_query_stag,
5123 .mw_alloc = i40iw_sc_mw_alloc
5124 };
5125
5126 static const struct i40iw_cqp_misc_ops iw_cqp_misc_ops = {
5127 .manage_hmc_pm_func_table = i40iw_sc_manage_hmc_pm_func_table,
5128 .set_hmc_resource_profile = i40iw_sc_set_hmc_resource_profile,
5129 .commit_fpm_values = i40iw_sc_commit_fpm_values,
5130 .query_fpm_values = i40iw_sc_query_fpm_values,
5131 .static_hmc_pages_allocated = i40iw_sc_static_hmc_pages_allocated,
5132 .add_arp_cache_entry = i40iw_sc_add_arp_cache_entry,
5133 .del_arp_cache_entry = i40iw_sc_del_arp_cache_entry,
5134 .query_arp_cache_entry = i40iw_sc_query_arp_cache_entry,
5135 .manage_apbvt_entry = i40iw_sc_manage_apbvt_entry,
5136 .manage_qhash_table_entry = i40iw_sc_manage_qhash_table_entry,
5137 .alloc_local_mac_ipaddr_table_entry = i40iw_sc_alloc_local_mac_ipaddr_entry,
5138 .add_local_mac_ipaddr_entry = i40iw_sc_add_local_mac_ipaddr_entry,
5139 .del_local_mac_ipaddr_entry = i40iw_sc_del_local_mac_ipaddr_entry,
5140 .cqp_nop = i40iw_sc_cqp_nop,
5141 .commit_fpm_values_done = i40iw_sc_commit_fpm_values_done,
5142 .query_fpm_values_done = i40iw_sc_query_fpm_values_done,
5143 .manage_hmc_pm_func_table_done = i40iw_sc_manage_hmc_pm_func_table_done,
5144 .update_suspend_qp = i40iw_sc_suspend_qp,
5145 .update_resume_qp = i40iw_sc_resume_qp
5146 };
5147
5148 static const struct i40iw_hmc_ops iw_hmc_ops = {
5149 .init_iw_hmc = i40iw_sc_init_iw_hmc,
5150 .parse_fpm_query_buf = i40iw_sc_parse_fpm_query_buf,
5151 .configure_iw_fpm = i40iw_sc_configure_iw_fpm,
5152 .parse_fpm_commit_buf = i40iw_sc_parse_fpm_commit_buf,
5153 .create_hmc_object = i40iw_sc_create_hmc_obj,
5154 .del_hmc_object = i40iw_sc_del_hmc_obj
5155 };
5156
5157 /**
5158 * i40iw_device_init - Initialize IWARP device
5159 * @dev: IWARP device pointer
5160 * @info: IWARP init info
5161 */
i40iw_device_init(struct i40iw_sc_dev * dev,struct i40iw_device_init_info * info)5162 enum i40iw_status_code i40iw_device_init(struct i40iw_sc_dev *dev,
5163 struct i40iw_device_init_info *info)
5164 {
5165 u32 val;
5166 u32 vchnl_ver = 0;
5167 u16 hmc_fcn = 0;
5168 enum i40iw_status_code ret_code = 0;
5169 u8 db_size;
5170
5171 spin_lock_init(&dev->cqp_lock);
5172
5173 i40iw_device_init_uk(&dev->dev_uk);
5174
5175 dev->debug_mask = info->debug_mask;
5176
5177 dev->hmc_fn_id = info->hmc_fn_id;
5178 dev->is_pf = info->is_pf;
5179
5180 dev->fpm_query_buf_pa = info->fpm_query_buf_pa;
5181 dev->fpm_query_buf = info->fpm_query_buf;
5182
5183 dev->fpm_commit_buf_pa = info->fpm_commit_buf_pa;
5184 dev->fpm_commit_buf = info->fpm_commit_buf;
5185
5186 dev->hw = info->hw;
5187 dev->hw->hw_addr = info->bar0;
5188
5189 if (dev->is_pf) {
5190 val = i40iw_rd32(dev->hw, I40E_GLPCI_DREVID);
5191 dev->hw_rev = (u8)RS_32(val, I40E_GLPCI_DREVID_DEFAULT_REVID);
5192
5193 val = i40iw_rd32(dev->hw, I40E_GLPCI_LBARCTRL);
5194 db_size = (u8)RS_32(val, I40E_GLPCI_LBARCTRL_PE_DB_SIZE);
5195 if ((db_size != I40IW_PE_DB_SIZE_4M) &&
5196 (db_size != I40IW_PE_DB_SIZE_8M)) {
5197 i40iw_debug(dev, I40IW_DEBUG_DEV,
5198 "%s: PE doorbell is not enabled in CSR val 0x%x\n",
5199 __func__, val);
5200 ret_code = I40IW_ERR_PE_DOORBELL_NOT_ENABLED;
5201 return ret_code;
5202 }
5203 dev->db_addr = dev->hw->hw_addr + I40IW_DB_ADDR_OFFSET;
5204 dev->vchnl_if.vchnl_recv = i40iw_vchnl_recv_pf;
5205 } else {
5206 dev->db_addr = dev->hw->hw_addr + I40IW_VF_DB_ADDR_OFFSET;
5207 }
5208
5209 dev->cqp_ops = &iw_cqp_ops;
5210 dev->ccq_ops = &iw_ccq_ops;
5211 dev->ceq_ops = &iw_ceq_ops;
5212 dev->aeq_ops = &iw_aeq_ops;
5213 dev->cqp_misc_ops = &iw_cqp_misc_ops;
5214 dev->iw_pd_ops = &iw_pd_ops;
5215 dev->iw_priv_qp_ops = &iw_priv_qp_ops;
5216 dev->iw_priv_cq_ops = &iw_priv_cq_ops;
5217 dev->mr_ops = &iw_mr_ops;
5218 dev->hmc_ops = &iw_hmc_ops;
5219 dev->vchnl_if.vchnl_send = info->vchnl_send;
5220 if (dev->vchnl_if.vchnl_send)
5221 dev->vchnl_up = true;
5222 else
5223 dev->vchnl_up = false;
5224 if (!dev->is_pf) {
5225 dev->vchnl_if.vchnl_recv = i40iw_vchnl_recv_vf;
5226 ret_code = i40iw_vchnl_vf_get_ver(dev, &vchnl_ver);
5227 if (!ret_code) {
5228 i40iw_debug(dev, I40IW_DEBUG_DEV,
5229 "%s: Get Channel version rc = 0x%0x, version is %u\n",
5230 __func__, ret_code, vchnl_ver);
5231 ret_code = i40iw_vchnl_vf_get_hmc_fcn(dev, &hmc_fcn);
5232 if (!ret_code) {
5233 i40iw_debug(dev, I40IW_DEBUG_DEV,
5234 "%s Get HMC function rc = 0x%0x, hmc fcn is %u\n",
5235 __func__, ret_code, hmc_fcn);
5236 dev->hmc_fn_id = (u8)hmc_fcn;
5237 }
5238 }
5239 }
5240 dev->iw_vf_cqp_ops = &iw_vf_cqp_ops;
5241
5242 return ret_code;
5243 }
5244