1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2 /*
3 * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved.
4 * Copyright (c) 2020, Intel Corporation. All rights reserved.
5 */
6
7 #include <linux/debugfs.h>
8 #include <linux/highmem.h>
9 #include <linux/module.h>
10 #include <linux/init.h>
11 #include <linux/errno.h>
12 #include <linux/pci.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/slab.h>
15 #include <linux/bitmap.h>
16 #include <linux/sched.h>
17 #include <linux/sched/mm.h>
18 #include <linux/sched/task.h>
19 #include <linux/delay.h>
20 #include <rdma/ib_user_verbs.h>
21 #include <rdma/ib_addr.h>
22 #include <rdma/ib_cache.h>
23 #include <linux/mlx5/port.h>
24 #include <linux/mlx5/vport.h>
25 #include <linux/mlx5/fs.h>
26 #include <linux/mlx5/eswitch.h>
27 #include <linux/list.h>
28 #include <rdma/ib_smi.h>
29 #include <rdma/ib_umem.h>
30 #include <rdma/lag.h>
31 #include <linux/in.h>
32 #include <linux/etherdevice.h>
33 #include "mlx5_ib.h"
34 #include "ib_rep.h"
35 #include "cmd.h"
36 #include "devx.h"
37 #include "dm.h"
38 #include "fs.h"
39 #include "srq.h"
40 #include "qp.h"
41 #include "wr.h"
42 #include "restrack.h"
43 #include "counters.h"
44 #include <linux/mlx5/accel.h>
45 #include <rdma/uverbs_std_types.h>
46 #include <rdma/uverbs_ioctl.h>
47 #include <rdma/mlx5_user_ioctl_verbs.h>
48 #include <rdma/mlx5_user_ioctl_cmds.h>
49 #include <rdma/ib_umem_odp.h>
50
51 #define UVERBS_MODULE_NAME mlx5_ib
52 #include <rdma/uverbs_named_ioctl.h>
53
54 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
55 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) IB driver");
56 MODULE_LICENSE("Dual BSD/GPL");
57
58 struct mlx5_ib_event_work {
59 struct work_struct work;
60 union {
61 struct mlx5_ib_dev *dev;
62 struct mlx5_ib_multiport_info *mpi;
63 };
64 bool is_slave;
65 unsigned int event;
66 void *param;
67 };
68
69 enum {
70 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
71 };
72
73 static struct workqueue_struct *mlx5_ib_event_wq;
74 static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
75 static LIST_HEAD(mlx5_ib_dev_list);
76 /*
77 * This mutex should be held when accessing either of the above lists
78 */
79 static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
80
mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info * mpi)81 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
82 {
83 struct mlx5_ib_dev *dev;
84
85 mutex_lock(&mlx5_ib_multiport_mutex);
86 dev = mpi->ibdev;
87 mutex_unlock(&mlx5_ib_multiport_mutex);
88 return dev;
89 }
90
91 static enum rdma_link_layer
mlx5_port_type_cap_to_rdma_ll(int port_type_cap)92 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
93 {
94 switch (port_type_cap) {
95 case MLX5_CAP_PORT_TYPE_IB:
96 return IB_LINK_LAYER_INFINIBAND;
97 case MLX5_CAP_PORT_TYPE_ETH:
98 return IB_LINK_LAYER_ETHERNET;
99 default:
100 return IB_LINK_LAYER_UNSPECIFIED;
101 }
102 }
103
104 static enum rdma_link_layer
mlx5_ib_port_link_layer(struct ib_device * device,u32 port_num)105 mlx5_ib_port_link_layer(struct ib_device *device, u32 port_num)
106 {
107 struct mlx5_ib_dev *dev = to_mdev(device);
108 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
109
110 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
111 }
112
get_port_state(struct ib_device * ibdev,u32 port_num,enum ib_port_state * state)113 static int get_port_state(struct ib_device *ibdev,
114 u32 port_num,
115 enum ib_port_state *state)
116 {
117 struct ib_port_attr attr;
118 int ret;
119
120 memset(&attr, 0, sizeof(attr));
121 ret = ibdev->ops.query_port(ibdev, port_num, &attr);
122 if (!ret)
123 *state = attr.state;
124 return ret;
125 }
126
mlx5_get_rep_roce(struct mlx5_ib_dev * dev,struct net_device * ndev,u32 * port_num)127 static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev,
128 struct net_device *ndev,
129 u32 *port_num)
130 {
131 struct net_device *rep_ndev;
132 struct mlx5_ib_port *port;
133 int i;
134
135 for (i = 0; i < dev->num_ports; i++) {
136 port = &dev->port[i];
137 if (!port->rep)
138 continue;
139
140 read_lock(&port->roce.netdev_lock);
141 rep_ndev = mlx5_ib_get_rep_netdev(port->rep->esw,
142 port->rep->vport);
143 if (rep_ndev == ndev) {
144 read_unlock(&port->roce.netdev_lock);
145 *port_num = i + 1;
146 return &port->roce;
147 }
148 read_unlock(&port->roce.netdev_lock);
149 }
150
151 return NULL;
152 }
153
mlx5_netdev_event(struct notifier_block * this,unsigned long event,void * ptr)154 static int mlx5_netdev_event(struct notifier_block *this,
155 unsigned long event, void *ptr)
156 {
157 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
158 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
159 u32 port_num = roce->native_port_num;
160 struct mlx5_core_dev *mdev;
161 struct mlx5_ib_dev *ibdev;
162
163 ibdev = roce->dev;
164 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
165 if (!mdev)
166 return NOTIFY_DONE;
167
168 switch (event) {
169 case NETDEV_REGISTER:
170 /* Should already be registered during the load */
171 if (ibdev->is_rep)
172 break;
173 write_lock(&roce->netdev_lock);
174 if (ndev->dev.parent == mdev->device)
175 roce->netdev = ndev;
176 write_unlock(&roce->netdev_lock);
177 break;
178
179 case NETDEV_UNREGISTER:
180 /* In case of reps, ib device goes away before the netdevs */
181 write_lock(&roce->netdev_lock);
182 if (roce->netdev == ndev)
183 roce->netdev = NULL;
184 write_unlock(&roce->netdev_lock);
185 break;
186
187 case NETDEV_CHANGE:
188 case NETDEV_UP:
189 case NETDEV_DOWN: {
190 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
191 struct net_device *upper = NULL;
192
193 if (lag_ndev) {
194 upper = netdev_master_upper_dev_get(lag_ndev);
195 dev_put(lag_ndev);
196 }
197
198 if (ibdev->is_rep)
199 roce = mlx5_get_rep_roce(ibdev, ndev, &port_num);
200 if (!roce)
201 return NOTIFY_DONE;
202 if ((upper == ndev || (!upper && ndev == roce->netdev))
203 && ibdev->ib_active) {
204 struct ib_event ibev = { };
205 enum ib_port_state port_state;
206
207 if (get_port_state(&ibdev->ib_dev, port_num,
208 &port_state))
209 goto done;
210
211 if (roce->last_port_state == port_state)
212 goto done;
213
214 roce->last_port_state = port_state;
215 ibev.device = &ibdev->ib_dev;
216 if (port_state == IB_PORT_DOWN)
217 ibev.event = IB_EVENT_PORT_ERR;
218 else if (port_state == IB_PORT_ACTIVE)
219 ibev.event = IB_EVENT_PORT_ACTIVE;
220 else
221 goto done;
222
223 ibev.element.port_num = port_num;
224 ib_dispatch_event(&ibev);
225 }
226 break;
227 }
228
229 default:
230 break;
231 }
232 done:
233 mlx5_ib_put_native_port_mdev(ibdev, port_num);
234 return NOTIFY_DONE;
235 }
236
mlx5_ib_get_netdev(struct ib_device * device,u32 port_num)237 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
238 u32 port_num)
239 {
240 struct mlx5_ib_dev *ibdev = to_mdev(device);
241 struct net_device *ndev;
242 struct mlx5_core_dev *mdev;
243
244 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
245 if (!mdev)
246 return NULL;
247
248 ndev = mlx5_lag_get_roce_netdev(mdev);
249 if (ndev)
250 goto out;
251
252 /* Ensure ndev does not disappear before we invoke dev_hold()
253 */
254 read_lock(&ibdev->port[port_num - 1].roce.netdev_lock);
255 ndev = ibdev->port[port_num - 1].roce.netdev;
256 if (ndev)
257 dev_hold(ndev);
258 read_unlock(&ibdev->port[port_num - 1].roce.netdev_lock);
259
260 out:
261 mlx5_ib_put_native_port_mdev(ibdev, port_num);
262 return ndev;
263 }
264
mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev * ibdev,u32 ib_port_num,u32 * native_port_num)265 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
266 u32 ib_port_num,
267 u32 *native_port_num)
268 {
269 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
270 ib_port_num);
271 struct mlx5_core_dev *mdev = NULL;
272 struct mlx5_ib_multiport_info *mpi;
273 struct mlx5_ib_port *port;
274
275 if (!mlx5_core_mp_enabled(ibdev->mdev) ||
276 ll != IB_LINK_LAYER_ETHERNET) {
277 if (native_port_num)
278 *native_port_num = ib_port_num;
279 return ibdev->mdev;
280 }
281
282 if (native_port_num)
283 *native_port_num = 1;
284
285 port = &ibdev->port[ib_port_num - 1];
286 spin_lock(&port->mp.mpi_lock);
287 mpi = ibdev->port[ib_port_num - 1].mp.mpi;
288 if (mpi && !mpi->unaffiliate) {
289 mdev = mpi->mdev;
290 /* If it's the master no need to refcount, it'll exist
291 * as long as the ib_dev exists.
292 */
293 if (!mpi->is_master)
294 mpi->mdev_refcnt++;
295 }
296 spin_unlock(&port->mp.mpi_lock);
297
298 return mdev;
299 }
300
mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev * ibdev,u32 port_num)301 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u32 port_num)
302 {
303 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
304 port_num);
305 struct mlx5_ib_multiport_info *mpi;
306 struct mlx5_ib_port *port;
307
308 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
309 return;
310
311 port = &ibdev->port[port_num - 1];
312
313 spin_lock(&port->mp.mpi_lock);
314 mpi = ibdev->port[port_num - 1].mp.mpi;
315 if (mpi->is_master)
316 goto out;
317
318 mpi->mdev_refcnt--;
319 if (mpi->unaffiliate)
320 complete(&mpi->unref_comp);
321 out:
322 spin_unlock(&port->mp.mpi_lock);
323 }
324
translate_eth_legacy_proto_oper(u32 eth_proto_oper,u16 * active_speed,u8 * active_width)325 static int translate_eth_legacy_proto_oper(u32 eth_proto_oper,
326 u16 *active_speed, u8 *active_width)
327 {
328 switch (eth_proto_oper) {
329 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
330 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
331 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
332 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
333 *active_width = IB_WIDTH_1X;
334 *active_speed = IB_SPEED_SDR;
335 break;
336 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
337 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
338 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
339 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
340 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
341 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
342 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
343 *active_width = IB_WIDTH_1X;
344 *active_speed = IB_SPEED_QDR;
345 break;
346 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
347 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
348 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
349 *active_width = IB_WIDTH_1X;
350 *active_speed = IB_SPEED_EDR;
351 break;
352 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
353 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
354 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
355 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
356 *active_width = IB_WIDTH_4X;
357 *active_speed = IB_SPEED_QDR;
358 break;
359 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
360 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
361 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
362 *active_width = IB_WIDTH_1X;
363 *active_speed = IB_SPEED_HDR;
364 break;
365 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
366 *active_width = IB_WIDTH_4X;
367 *active_speed = IB_SPEED_FDR;
368 break;
369 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
370 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
371 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
372 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
373 *active_width = IB_WIDTH_4X;
374 *active_speed = IB_SPEED_EDR;
375 break;
376 default:
377 return -EINVAL;
378 }
379
380 return 0;
381 }
382
translate_eth_ext_proto_oper(u32 eth_proto_oper,u16 * active_speed,u8 * active_width)383 static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u16 *active_speed,
384 u8 *active_width)
385 {
386 switch (eth_proto_oper) {
387 case MLX5E_PROT_MASK(MLX5E_SGMII_100M):
388 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII):
389 *active_width = IB_WIDTH_1X;
390 *active_speed = IB_SPEED_SDR;
391 break;
392 case MLX5E_PROT_MASK(MLX5E_5GBASE_R):
393 *active_width = IB_WIDTH_1X;
394 *active_speed = IB_SPEED_DDR;
395 break;
396 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1):
397 *active_width = IB_WIDTH_1X;
398 *active_speed = IB_SPEED_QDR;
399 break;
400 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4):
401 *active_width = IB_WIDTH_4X;
402 *active_speed = IB_SPEED_QDR;
403 break;
404 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR):
405 *active_width = IB_WIDTH_1X;
406 *active_speed = IB_SPEED_EDR;
407 break;
408 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2):
409 *active_width = IB_WIDTH_2X;
410 *active_speed = IB_SPEED_EDR;
411 break;
412 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR):
413 *active_width = IB_WIDTH_1X;
414 *active_speed = IB_SPEED_HDR;
415 break;
416 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4):
417 *active_width = IB_WIDTH_4X;
418 *active_speed = IB_SPEED_EDR;
419 break;
420 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2):
421 *active_width = IB_WIDTH_2X;
422 *active_speed = IB_SPEED_HDR;
423 break;
424 case MLX5E_PROT_MASK(MLX5E_100GAUI_1_100GBASE_CR_KR):
425 *active_width = IB_WIDTH_1X;
426 *active_speed = IB_SPEED_NDR;
427 break;
428 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4):
429 *active_width = IB_WIDTH_4X;
430 *active_speed = IB_SPEED_HDR;
431 break;
432 case MLX5E_PROT_MASK(MLX5E_200GAUI_2_200GBASE_CR2_KR2):
433 *active_width = IB_WIDTH_2X;
434 *active_speed = IB_SPEED_NDR;
435 break;
436 case MLX5E_PROT_MASK(MLX5E_400GAUI_4_400GBASE_CR4_KR4):
437 *active_width = IB_WIDTH_4X;
438 *active_speed = IB_SPEED_NDR;
439 break;
440 default:
441 return -EINVAL;
442 }
443
444 return 0;
445 }
446
translate_eth_proto_oper(u32 eth_proto_oper,u16 * active_speed,u8 * active_width,bool ext)447 static int translate_eth_proto_oper(u32 eth_proto_oper, u16 *active_speed,
448 u8 *active_width, bool ext)
449 {
450 return ext ?
451 translate_eth_ext_proto_oper(eth_proto_oper, active_speed,
452 active_width) :
453 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed,
454 active_width);
455 }
456
mlx5_query_port_roce(struct ib_device * device,u32 port_num,struct ib_port_attr * props)457 static int mlx5_query_port_roce(struct ib_device *device, u32 port_num,
458 struct ib_port_attr *props)
459 {
460 struct mlx5_ib_dev *dev = to_mdev(device);
461 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
462 struct mlx5_core_dev *mdev;
463 struct net_device *ndev, *upper;
464 enum ib_mtu ndev_ib_mtu;
465 bool put_mdev = true;
466 u32 eth_prot_oper;
467 u32 mdev_port_num;
468 bool ext;
469 int err;
470
471 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
472 if (!mdev) {
473 /* This means the port isn't affiliated yet. Get the
474 * info for the master port instead.
475 */
476 put_mdev = false;
477 mdev = dev->mdev;
478 mdev_port_num = 1;
479 port_num = 1;
480 }
481
482 /* Possible bad flows are checked before filling out props so in case
483 * of an error it will still be zeroed out.
484 * Use native port in case of reps
485 */
486 if (dev->is_rep)
487 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
488 1);
489 else
490 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
491 mdev_port_num);
492 if (err)
493 goto out;
494 ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability);
495 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper);
496
497 props->active_width = IB_WIDTH_4X;
498 props->active_speed = IB_SPEED_QDR;
499
500 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
501 &props->active_width, ext);
502
503 if (!dev->is_rep && dev->mdev->roce.roce_en) {
504 u16 qkey_viol_cntr;
505
506 props->port_cap_flags |= IB_PORT_CM_SUP;
507 props->ip_gids = true;
508 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
509 roce_address_table_size);
510 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
511 props->qkey_viol_cntr = qkey_viol_cntr;
512 }
513 props->max_mtu = IB_MTU_4096;
514 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
515 props->pkey_tbl_len = 1;
516 props->state = IB_PORT_DOWN;
517 props->phys_state = IB_PORT_PHYS_STATE_DISABLED;
518
519 /* If this is a stub query for an unaffiliated port stop here */
520 if (!put_mdev)
521 goto out;
522
523 ndev = mlx5_ib_get_netdev(device, port_num);
524 if (!ndev)
525 goto out;
526
527 if (dev->lag_active) {
528 rcu_read_lock();
529 upper = netdev_master_upper_dev_get_rcu(ndev);
530 if (upper) {
531 dev_put(ndev);
532 ndev = upper;
533 dev_hold(ndev);
534 }
535 rcu_read_unlock();
536 }
537
538 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
539 props->state = IB_PORT_ACTIVE;
540 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP;
541 }
542
543 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
544
545 dev_put(ndev);
546
547 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
548 out:
549 if (put_mdev)
550 mlx5_ib_put_native_port_mdev(dev, port_num);
551 return err;
552 }
553
set_roce_addr(struct mlx5_ib_dev * dev,u32 port_num,unsigned int index,const union ib_gid * gid,const struct ib_gid_attr * attr)554 static int set_roce_addr(struct mlx5_ib_dev *dev, u32 port_num,
555 unsigned int index, const union ib_gid *gid,
556 const struct ib_gid_attr *attr)
557 {
558 enum ib_gid_type gid_type;
559 u16 vlan_id = 0xffff;
560 u8 roce_version = 0;
561 u8 roce_l3_type = 0;
562 u8 mac[ETH_ALEN];
563 int ret;
564
565 gid_type = attr->gid_type;
566 if (gid) {
567 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]);
568 if (ret)
569 return ret;
570 }
571
572 switch (gid_type) {
573 case IB_GID_TYPE_ROCE:
574 roce_version = MLX5_ROCE_VERSION_1;
575 break;
576 case IB_GID_TYPE_ROCE_UDP_ENCAP:
577 roce_version = MLX5_ROCE_VERSION_2;
578 if (gid && ipv6_addr_v4mapped((void *)gid))
579 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
580 else
581 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
582 break;
583
584 default:
585 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
586 }
587
588 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
589 roce_l3_type, gid->raw, mac,
590 vlan_id < VLAN_CFI_MASK, vlan_id,
591 port_num);
592 }
593
mlx5_ib_add_gid(const struct ib_gid_attr * attr,__always_unused void ** context)594 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr,
595 __always_unused void **context)
596 {
597 return set_roce_addr(to_mdev(attr->device), attr->port_num,
598 attr->index, &attr->gid, attr);
599 }
600
mlx5_ib_del_gid(const struct ib_gid_attr * attr,__always_unused void ** context)601 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
602 __always_unused void **context)
603 {
604 return set_roce_addr(to_mdev(attr->device), attr->port_num,
605 attr->index, NULL, attr);
606 }
607
mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev * dev,const struct ib_gid_attr * attr)608 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev,
609 const struct ib_gid_attr *attr)
610 {
611 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
612 return 0;
613
614 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
615 }
616
mlx5_use_mad_ifc(struct mlx5_ib_dev * dev)617 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
618 {
619 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
620 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
621 return 0;
622 }
623
624 enum {
625 MLX5_VPORT_ACCESS_METHOD_MAD,
626 MLX5_VPORT_ACCESS_METHOD_HCA,
627 MLX5_VPORT_ACCESS_METHOD_NIC,
628 };
629
mlx5_get_vport_access_method(struct ib_device * ibdev)630 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
631 {
632 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
633 return MLX5_VPORT_ACCESS_METHOD_MAD;
634
635 if (mlx5_ib_port_link_layer(ibdev, 1) ==
636 IB_LINK_LAYER_ETHERNET)
637 return MLX5_VPORT_ACCESS_METHOD_NIC;
638
639 return MLX5_VPORT_ACCESS_METHOD_HCA;
640 }
641
get_atomic_caps(struct mlx5_ib_dev * dev,u8 atomic_size_qp,struct ib_device_attr * props)642 static void get_atomic_caps(struct mlx5_ib_dev *dev,
643 u8 atomic_size_qp,
644 struct ib_device_attr *props)
645 {
646 u8 tmp;
647 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
648 u8 atomic_req_8B_endianness_mode =
649 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
650
651 /* Check if HW supports 8 bytes standard atomic operations and capable
652 * of host endianness respond
653 */
654 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
655 if (((atomic_operations & tmp) == tmp) &&
656 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
657 (atomic_req_8B_endianness_mode)) {
658 props->atomic_cap = IB_ATOMIC_HCA;
659 } else {
660 props->atomic_cap = IB_ATOMIC_NONE;
661 }
662 }
663
get_atomic_caps_qp(struct mlx5_ib_dev * dev,struct ib_device_attr * props)664 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
665 struct ib_device_attr *props)
666 {
667 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
668
669 get_atomic_caps(dev, atomic_size_qp, props);
670 }
671
mlx5_query_system_image_guid(struct ib_device * ibdev,__be64 * sys_image_guid)672 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
673 __be64 *sys_image_guid)
674 {
675 struct mlx5_ib_dev *dev = to_mdev(ibdev);
676 struct mlx5_core_dev *mdev = dev->mdev;
677 u64 tmp;
678 int err;
679
680 switch (mlx5_get_vport_access_method(ibdev)) {
681 case MLX5_VPORT_ACCESS_METHOD_MAD:
682 return mlx5_query_mad_ifc_system_image_guid(ibdev,
683 sys_image_guid);
684
685 case MLX5_VPORT_ACCESS_METHOD_HCA:
686 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
687 break;
688
689 case MLX5_VPORT_ACCESS_METHOD_NIC:
690 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
691 break;
692
693 default:
694 return -EINVAL;
695 }
696
697 if (!err)
698 *sys_image_guid = cpu_to_be64(tmp);
699
700 return err;
701
702 }
703
mlx5_query_max_pkeys(struct ib_device * ibdev,u16 * max_pkeys)704 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
705 u16 *max_pkeys)
706 {
707 struct mlx5_ib_dev *dev = to_mdev(ibdev);
708 struct mlx5_core_dev *mdev = dev->mdev;
709
710 switch (mlx5_get_vport_access_method(ibdev)) {
711 case MLX5_VPORT_ACCESS_METHOD_MAD:
712 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
713
714 case MLX5_VPORT_ACCESS_METHOD_HCA:
715 case MLX5_VPORT_ACCESS_METHOD_NIC:
716 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
717 pkey_table_size));
718 return 0;
719
720 default:
721 return -EINVAL;
722 }
723 }
724
mlx5_query_vendor_id(struct ib_device * ibdev,u32 * vendor_id)725 static int mlx5_query_vendor_id(struct ib_device *ibdev,
726 u32 *vendor_id)
727 {
728 struct mlx5_ib_dev *dev = to_mdev(ibdev);
729
730 switch (mlx5_get_vport_access_method(ibdev)) {
731 case MLX5_VPORT_ACCESS_METHOD_MAD:
732 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
733
734 case MLX5_VPORT_ACCESS_METHOD_HCA:
735 case MLX5_VPORT_ACCESS_METHOD_NIC:
736 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
737
738 default:
739 return -EINVAL;
740 }
741 }
742
mlx5_query_node_guid(struct mlx5_ib_dev * dev,__be64 * node_guid)743 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
744 __be64 *node_guid)
745 {
746 u64 tmp;
747 int err;
748
749 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
750 case MLX5_VPORT_ACCESS_METHOD_MAD:
751 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
752
753 case MLX5_VPORT_ACCESS_METHOD_HCA:
754 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
755 break;
756
757 case MLX5_VPORT_ACCESS_METHOD_NIC:
758 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
759 break;
760
761 default:
762 return -EINVAL;
763 }
764
765 if (!err)
766 *node_guid = cpu_to_be64(tmp);
767
768 return err;
769 }
770
771 struct mlx5_reg_node_desc {
772 u8 desc[IB_DEVICE_NODE_DESC_MAX];
773 };
774
mlx5_query_node_desc(struct mlx5_ib_dev * dev,char * node_desc)775 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
776 {
777 struct mlx5_reg_node_desc in;
778
779 if (mlx5_use_mad_ifc(dev))
780 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
781
782 memset(&in, 0, sizeof(in));
783
784 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
785 sizeof(struct mlx5_reg_node_desc),
786 MLX5_REG_NODE_DESC, 0, 0);
787 }
788
mlx5_ib_query_device(struct ib_device * ibdev,struct ib_device_attr * props,struct ib_udata * uhw)789 static int mlx5_ib_query_device(struct ib_device *ibdev,
790 struct ib_device_attr *props,
791 struct ib_udata *uhw)
792 {
793 size_t uhw_outlen = (uhw) ? uhw->outlen : 0;
794 struct mlx5_ib_dev *dev = to_mdev(ibdev);
795 struct mlx5_core_dev *mdev = dev->mdev;
796 int err = -ENOMEM;
797 int max_sq_desc;
798 int max_rq_sg;
799 int max_sq_sg;
800 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
801 bool raw_support = !mlx5_core_mp_enabled(mdev);
802 struct mlx5_ib_query_device_resp resp = {};
803 size_t resp_len;
804 u64 max_tso;
805
806 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
807 if (uhw_outlen && uhw_outlen < resp_len)
808 return -EINVAL;
809
810 resp.response_length = resp_len;
811
812 if (uhw && uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
813 return -EINVAL;
814
815 memset(props, 0, sizeof(*props));
816 err = mlx5_query_system_image_guid(ibdev,
817 &props->sys_image_guid);
818 if (err)
819 return err;
820
821 props->max_pkeys = dev->pkey_table_len;
822
823 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
824 if (err)
825 return err;
826
827 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
828 (fw_rev_min(dev->mdev) << 16) |
829 fw_rev_sub(dev->mdev);
830 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
831 IB_DEVICE_PORT_ACTIVE_EVENT |
832 IB_DEVICE_SYS_IMAGE_GUID |
833 IB_DEVICE_RC_RNR_NAK_GEN;
834
835 if (MLX5_CAP_GEN(mdev, pkv))
836 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
837 if (MLX5_CAP_GEN(mdev, qkv))
838 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
839 if (MLX5_CAP_GEN(mdev, apm))
840 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
841 if (MLX5_CAP_GEN(mdev, xrc))
842 props->device_cap_flags |= IB_DEVICE_XRC;
843 if (MLX5_CAP_GEN(mdev, imaicl)) {
844 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
845 IB_DEVICE_MEM_WINDOW_TYPE_2B;
846 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
847 /* We support 'Gappy' memory registration too */
848 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
849 }
850 /* IB_WR_REG_MR always requires changing the entity size with UMR */
851 if (!MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled))
852 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
853 if (MLX5_CAP_GEN(mdev, sho)) {
854 props->device_cap_flags |= IB_DEVICE_INTEGRITY_HANDOVER;
855 /* At this stage no support for signature handover */
856 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
857 IB_PROT_T10DIF_TYPE_2 |
858 IB_PROT_T10DIF_TYPE_3;
859 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
860 IB_GUARD_T10DIF_CSUM;
861 }
862 if (MLX5_CAP_GEN(mdev, block_lb_mc))
863 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
864
865 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
866 if (MLX5_CAP_ETH(mdev, csum_cap)) {
867 /* Legacy bit to support old userspace libraries */
868 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
869 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
870 }
871
872 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
873 props->raw_packet_caps |=
874 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
875
876 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) {
877 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
878 if (max_tso) {
879 resp.tso_caps.max_tso = 1 << max_tso;
880 resp.tso_caps.supported_qpts |=
881 1 << IB_QPT_RAW_PACKET;
882 resp.response_length += sizeof(resp.tso_caps);
883 }
884 }
885
886 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) {
887 resp.rss_caps.rx_hash_function =
888 MLX5_RX_HASH_FUNC_TOEPLITZ;
889 resp.rss_caps.rx_hash_fields_mask =
890 MLX5_RX_HASH_SRC_IPV4 |
891 MLX5_RX_HASH_DST_IPV4 |
892 MLX5_RX_HASH_SRC_IPV6 |
893 MLX5_RX_HASH_DST_IPV6 |
894 MLX5_RX_HASH_SRC_PORT_TCP |
895 MLX5_RX_HASH_DST_PORT_TCP |
896 MLX5_RX_HASH_SRC_PORT_UDP |
897 MLX5_RX_HASH_DST_PORT_UDP |
898 MLX5_RX_HASH_INNER;
899 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
900 MLX5_ACCEL_IPSEC_CAP_DEVICE)
901 resp.rss_caps.rx_hash_fields_mask |=
902 MLX5_RX_HASH_IPSEC_SPI;
903 resp.response_length += sizeof(resp.rss_caps);
904 }
905 } else {
906 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen)
907 resp.response_length += sizeof(resp.tso_caps);
908 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen)
909 resp.response_length += sizeof(resp.rss_caps);
910 }
911
912 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
913 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
914 props->device_cap_flags |= IB_DEVICE_UD_TSO;
915 }
916
917 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
918 MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
919 raw_support)
920 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
921
922 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
923 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
924 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
925
926 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
927 MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
928 raw_support) {
929 /* Legacy bit to support old userspace libraries */
930 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
931 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
932 }
933
934 if (MLX5_CAP_DEV_MEM(mdev, memic)) {
935 props->max_dm_size =
936 MLX5_CAP_DEV_MEM(mdev, max_memic_size);
937 }
938
939 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
940 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
941
942 if (MLX5_CAP_GEN(mdev, end_pad))
943 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
944
945 props->vendor_part_id = mdev->pdev->device;
946 props->hw_ver = mdev->pdev->revision;
947
948 props->max_mr_size = ~0ull;
949 props->page_size_cap = ~(min_page_size - 1);
950 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
951 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
952 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
953 sizeof(struct mlx5_wqe_data_seg);
954 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
955 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
956 sizeof(struct mlx5_wqe_raddr_seg)) /
957 sizeof(struct mlx5_wqe_data_seg);
958 props->max_send_sge = max_sq_sg;
959 props->max_recv_sge = max_rq_sg;
960 props->max_sge_rd = MLX5_MAX_SGE_RD;
961 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
962 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
963 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
964 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
965 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
966 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
967 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
968 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
969 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
970 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
971 props->max_srq_sge = max_rq_sg - 1;
972 props->max_fast_reg_page_list_len =
973 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
974 props->max_pi_fast_reg_page_list_len =
975 props->max_fast_reg_page_list_len / 2;
976 props->max_sgl_rd =
977 MLX5_CAP_GEN(mdev, max_sgl_for_optimized_performance);
978 get_atomic_caps_qp(dev, props);
979 props->masked_atomic_cap = IB_ATOMIC_NONE;
980 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
981 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
982 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
983 props->max_mcast_grp;
984 props->max_ah = INT_MAX;
985 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
986 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
987
988 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
989 if (dev->odp_caps.general_caps & IB_ODP_SUPPORT)
990 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
991 props->odp_caps = dev->odp_caps;
992 if (!uhw) {
993 /* ODP for kernel QPs is not implemented for receive
994 * WQEs and SRQ WQEs
995 */
996 props->odp_caps.per_transport_caps.rc_odp_caps &=
997 ~(IB_ODP_SUPPORT_READ |
998 IB_ODP_SUPPORT_SRQ_RECV);
999 props->odp_caps.per_transport_caps.uc_odp_caps &=
1000 ~(IB_ODP_SUPPORT_READ |
1001 IB_ODP_SUPPORT_SRQ_RECV);
1002 props->odp_caps.per_transport_caps.ud_odp_caps &=
1003 ~(IB_ODP_SUPPORT_READ |
1004 IB_ODP_SUPPORT_SRQ_RECV);
1005 props->odp_caps.per_transport_caps.xrc_odp_caps &=
1006 ~(IB_ODP_SUPPORT_READ |
1007 IB_ODP_SUPPORT_SRQ_RECV);
1008 }
1009 }
1010
1011 if (MLX5_CAP_GEN(mdev, cd))
1012 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
1013
1014 if (mlx5_core_is_vf(mdev))
1015 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
1016
1017 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1018 IB_LINK_LAYER_ETHERNET && raw_support) {
1019 props->rss_caps.max_rwq_indirection_tables =
1020 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
1021 props->rss_caps.max_rwq_indirection_table_size =
1022 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
1023 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
1024 props->max_wq_type_rq =
1025 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
1026 }
1027
1028 if (MLX5_CAP_GEN(mdev, tag_matching)) {
1029 props->tm_caps.max_num_tags =
1030 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
1031 props->tm_caps.max_ops =
1032 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1033 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
1034 }
1035
1036 if (MLX5_CAP_GEN(mdev, tag_matching) &&
1037 MLX5_CAP_GEN(mdev, rndv_offload_rc)) {
1038 props->tm_caps.flags = IB_TM_CAP_RNDV_RC;
1039 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
1040 }
1041
1042 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
1043 props->cq_caps.max_cq_moderation_count =
1044 MLX5_MAX_CQ_COUNT;
1045 props->cq_caps.max_cq_moderation_period =
1046 MLX5_MAX_CQ_PERIOD;
1047 }
1048
1049 if (offsetofend(typeof(resp), cqe_comp_caps) <= uhw_outlen) {
1050 resp.response_length += sizeof(resp.cqe_comp_caps);
1051
1052 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) {
1053 resp.cqe_comp_caps.max_num =
1054 MLX5_CAP_GEN(dev->mdev,
1055 cqe_compression_max_num);
1056
1057 resp.cqe_comp_caps.supported_format =
1058 MLX5_IB_CQE_RES_FORMAT_HASH |
1059 MLX5_IB_CQE_RES_FORMAT_CSUM;
1060
1061 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
1062 resp.cqe_comp_caps.supported_format |=
1063 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX;
1064 }
1065 }
1066
1067 if (offsetofend(typeof(resp), packet_pacing_caps) <= uhw_outlen &&
1068 raw_support) {
1069 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
1070 MLX5_CAP_GEN(mdev, qos)) {
1071 resp.packet_pacing_caps.qp_rate_limit_max =
1072 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
1073 resp.packet_pacing_caps.qp_rate_limit_min =
1074 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
1075 resp.packet_pacing_caps.supported_qpts |=
1076 1 << IB_QPT_RAW_PACKET;
1077 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
1078 MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
1079 resp.packet_pacing_caps.cap_flags |=
1080 MLX5_IB_PP_SUPPORT_BURST;
1081 }
1082 resp.response_length += sizeof(resp.packet_pacing_caps);
1083 }
1084
1085 if (offsetofend(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes) <=
1086 uhw_outlen) {
1087 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
1088 resp.mlx5_ib_support_multi_pkt_send_wqes =
1089 MLX5_IB_ALLOW_MPW;
1090
1091 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1092 resp.mlx5_ib_support_multi_pkt_send_wqes |=
1093 MLX5_IB_SUPPORT_EMPW;
1094
1095 resp.response_length +=
1096 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
1097 }
1098
1099 if (offsetofend(typeof(resp), flags) <= uhw_outlen) {
1100 resp.response_length += sizeof(resp.flags);
1101
1102 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1103 resp.flags |=
1104 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
1105
1106 if (MLX5_CAP_GEN(mdev, cqe_128_always))
1107 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
1108 if (MLX5_CAP_GEN(mdev, qp_packet_based))
1109 resp.flags |=
1110 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE;
1111
1112 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT;
1113 }
1114
1115 if (offsetofend(typeof(resp), sw_parsing_caps) <= uhw_outlen) {
1116 resp.response_length += sizeof(resp.sw_parsing_caps);
1117 if (MLX5_CAP_ETH(mdev, swp)) {
1118 resp.sw_parsing_caps.sw_parsing_offloads |=
1119 MLX5_IB_SW_PARSING;
1120
1121 if (MLX5_CAP_ETH(mdev, swp_csum))
1122 resp.sw_parsing_caps.sw_parsing_offloads |=
1123 MLX5_IB_SW_PARSING_CSUM;
1124
1125 if (MLX5_CAP_ETH(mdev, swp_lso))
1126 resp.sw_parsing_caps.sw_parsing_offloads |=
1127 MLX5_IB_SW_PARSING_LSO;
1128
1129 if (resp.sw_parsing_caps.sw_parsing_offloads)
1130 resp.sw_parsing_caps.supported_qpts =
1131 BIT(IB_QPT_RAW_PACKET);
1132 }
1133 }
1134
1135 if (offsetofend(typeof(resp), striding_rq_caps) <= uhw_outlen &&
1136 raw_support) {
1137 resp.response_length += sizeof(resp.striding_rq_caps);
1138 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1139 resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1140 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1141 resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1142 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1143 if (MLX5_CAP_GEN(dev->mdev, ext_stride_num_range))
1144 resp.striding_rq_caps
1145 .min_single_wqe_log_num_of_strides =
1146 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1147 else
1148 resp.striding_rq_caps
1149 .min_single_wqe_log_num_of_strides =
1150 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1151 resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1152 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1153 resp.striding_rq_caps.supported_qpts =
1154 BIT(IB_QPT_RAW_PACKET);
1155 }
1156 }
1157
1158 if (offsetofend(typeof(resp), tunnel_offloads_caps) <= uhw_outlen) {
1159 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1160 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1161 resp.tunnel_offloads_caps |=
1162 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1163 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1164 resp.tunnel_offloads_caps |=
1165 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1166 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1167 resp.tunnel_offloads_caps |=
1168 MLX5_IB_TUNNELED_OFFLOADS_GRE;
1169 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre))
1170 resp.tunnel_offloads_caps |=
1171 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE;
1172 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_udp))
1173 resp.tunnel_offloads_caps |=
1174 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP;
1175 }
1176
1177 if (uhw_outlen) {
1178 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1179
1180 if (err)
1181 return err;
1182 }
1183
1184 return 0;
1185 }
1186
translate_active_width(struct ib_device * ibdev,u16 active_width,u8 * ib_width)1187 static void translate_active_width(struct ib_device *ibdev, u16 active_width,
1188 u8 *ib_width)
1189 {
1190 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1191
1192 if (active_width & MLX5_PTYS_WIDTH_1X)
1193 *ib_width = IB_WIDTH_1X;
1194 else if (active_width & MLX5_PTYS_WIDTH_2X)
1195 *ib_width = IB_WIDTH_2X;
1196 else if (active_width & MLX5_PTYS_WIDTH_4X)
1197 *ib_width = IB_WIDTH_4X;
1198 else if (active_width & MLX5_PTYS_WIDTH_8X)
1199 *ib_width = IB_WIDTH_8X;
1200 else if (active_width & MLX5_PTYS_WIDTH_12X)
1201 *ib_width = IB_WIDTH_12X;
1202 else {
1203 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n",
1204 active_width);
1205 *ib_width = IB_WIDTH_4X;
1206 }
1207
1208 return;
1209 }
1210
mlx5_mtu_to_ib_mtu(int mtu)1211 static int mlx5_mtu_to_ib_mtu(int mtu)
1212 {
1213 switch (mtu) {
1214 case 256: return 1;
1215 case 512: return 2;
1216 case 1024: return 3;
1217 case 2048: return 4;
1218 case 4096: return 5;
1219 default:
1220 pr_warn("invalid mtu\n");
1221 return -1;
1222 }
1223 }
1224
1225 enum ib_max_vl_num {
1226 __IB_MAX_VL_0 = 1,
1227 __IB_MAX_VL_0_1 = 2,
1228 __IB_MAX_VL_0_3 = 3,
1229 __IB_MAX_VL_0_7 = 4,
1230 __IB_MAX_VL_0_14 = 5,
1231 };
1232
1233 enum mlx5_vl_hw_cap {
1234 MLX5_VL_HW_0 = 1,
1235 MLX5_VL_HW_0_1 = 2,
1236 MLX5_VL_HW_0_2 = 3,
1237 MLX5_VL_HW_0_3 = 4,
1238 MLX5_VL_HW_0_4 = 5,
1239 MLX5_VL_HW_0_5 = 6,
1240 MLX5_VL_HW_0_6 = 7,
1241 MLX5_VL_HW_0_7 = 8,
1242 MLX5_VL_HW_0_14 = 15
1243 };
1244
translate_max_vl_num(struct ib_device * ibdev,u8 vl_hw_cap,u8 * max_vl_num)1245 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1246 u8 *max_vl_num)
1247 {
1248 switch (vl_hw_cap) {
1249 case MLX5_VL_HW_0:
1250 *max_vl_num = __IB_MAX_VL_0;
1251 break;
1252 case MLX5_VL_HW_0_1:
1253 *max_vl_num = __IB_MAX_VL_0_1;
1254 break;
1255 case MLX5_VL_HW_0_3:
1256 *max_vl_num = __IB_MAX_VL_0_3;
1257 break;
1258 case MLX5_VL_HW_0_7:
1259 *max_vl_num = __IB_MAX_VL_0_7;
1260 break;
1261 case MLX5_VL_HW_0_14:
1262 *max_vl_num = __IB_MAX_VL_0_14;
1263 break;
1264
1265 default:
1266 return -EINVAL;
1267 }
1268
1269 return 0;
1270 }
1271
mlx5_query_hca_port(struct ib_device * ibdev,u32 port,struct ib_port_attr * props)1272 static int mlx5_query_hca_port(struct ib_device *ibdev, u32 port,
1273 struct ib_port_attr *props)
1274 {
1275 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1276 struct mlx5_core_dev *mdev = dev->mdev;
1277 struct mlx5_hca_vport_context *rep;
1278 u16 max_mtu;
1279 u16 oper_mtu;
1280 int err;
1281 u16 ib_link_width_oper;
1282 u8 vl_hw_cap;
1283
1284 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1285 if (!rep) {
1286 err = -ENOMEM;
1287 goto out;
1288 }
1289
1290 /* props being zeroed by the caller, avoid zeroing it here */
1291
1292 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
1293 if (err)
1294 goto out;
1295
1296 props->lid = rep->lid;
1297 props->lmc = rep->lmc;
1298 props->sm_lid = rep->sm_lid;
1299 props->sm_sl = rep->sm_sl;
1300 props->state = rep->vport_state;
1301 props->phys_state = rep->port_physical_state;
1302 props->port_cap_flags = rep->cap_mask1;
1303 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1304 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1305 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1306 props->bad_pkey_cntr = rep->pkey_violation_counter;
1307 props->qkey_viol_cntr = rep->qkey_violation_counter;
1308 props->subnet_timeout = rep->subnet_timeout;
1309 props->init_type_reply = rep->init_type_reply;
1310
1311 if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP)
1312 props->port_cap_flags2 = rep->cap_mask2;
1313
1314 err = mlx5_query_ib_port_oper(mdev, &ib_link_width_oper,
1315 &props->active_speed, port);
1316 if (err)
1317 goto out;
1318
1319 translate_active_width(ibdev, ib_link_width_oper, &props->active_width);
1320
1321 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
1322
1323 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
1324
1325 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
1326
1327 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
1328
1329 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1330 if (err)
1331 goto out;
1332
1333 err = translate_max_vl_num(ibdev, vl_hw_cap,
1334 &props->max_vl_num);
1335 out:
1336 kfree(rep);
1337 return err;
1338 }
1339
mlx5_ib_query_port(struct ib_device * ibdev,u32 port,struct ib_port_attr * props)1340 int mlx5_ib_query_port(struct ib_device *ibdev, u32 port,
1341 struct ib_port_attr *props)
1342 {
1343 unsigned int count;
1344 int ret;
1345
1346 switch (mlx5_get_vport_access_method(ibdev)) {
1347 case MLX5_VPORT_ACCESS_METHOD_MAD:
1348 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1349 break;
1350
1351 case MLX5_VPORT_ACCESS_METHOD_HCA:
1352 ret = mlx5_query_hca_port(ibdev, port, props);
1353 break;
1354
1355 case MLX5_VPORT_ACCESS_METHOD_NIC:
1356 ret = mlx5_query_port_roce(ibdev, port, props);
1357 break;
1358
1359 default:
1360 ret = -EINVAL;
1361 }
1362
1363 if (!ret && props) {
1364 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1365 struct mlx5_core_dev *mdev;
1366 bool put_mdev = true;
1367
1368 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1369 if (!mdev) {
1370 /* If the port isn't affiliated yet query the master.
1371 * The master and slave will have the same values.
1372 */
1373 mdev = dev->mdev;
1374 port = 1;
1375 put_mdev = false;
1376 }
1377 count = mlx5_core_reserved_gids_count(mdev);
1378 if (put_mdev)
1379 mlx5_ib_put_native_port_mdev(dev, port);
1380 props->gid_tbl_len -= count;
1381 }
1382 return ret;
1383 }
1384
mlx5_ib_rep_query_port(struct ib_device * ibdev,u32 port,struct ib_port_attr * props)1385 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u32 port,
1386 struct ib_port_attr *props)
1387 {
1388 return mlx5_query_port_roce(ibdev, port, props);
1389 }
1390
mlx5_ib_rep_query_pkey(struct ib_device * ibdev,u32 port,u16 index,u16 * pkey)1391 static int mlx5_ib_rep_query_pkey(struct ib_device *ibdev, u32 port, u16 index,
1392 u16 *pkey)
1393 {
1394 /* Default special Pkey for representor device port as per the
1395 * IB specification 1.3 section 10.9.1.2.
1396 */
1397 *pkey = 0xffff;
1398 return 0;
1399 }
1400
mlx5_ib_query_gid(struct ib_device * ibdev,u32 port,int index,union ib_gid * gid)1401 static int mlx5_ib_query_gid(struct ib_device *ibdev, u32 port, int index,
1402 union ib_gid *gid)
1403 {
1404 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1405 struct mlx5_core_dev *mdev = dev->mdev;
1406
1407 switch (mlx5_get_vport_access_method(ibdev)) {
1408 case MLX5_VPORT_ACCESS_METHOD_MAD:
1409 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
1410
1411 case MLX5_VPORT_ACCESS_METHOD_HCA:
1412 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1413
1414 default:
1415 return -EINVAL;
1416 }
1417
1418 }
1419
mlx5_query_hca_nic_pkey(struct ib_device * ibdev,u32 port,u16 index,u16 * pkey)1420 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u32 port,
1421 u16 index, u16 *pkey)
1422 {
1423 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1424 struct mlx5_core_dev *mdev;
1425 bool put_mdev = true;
1426 u32 mdev_port_num;
1427 int err;
1428
1429 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1430 if (!mdev) {
1431 /* The port isn't affiliated yet, get the PKey from the master
1432 * port. For RoCE the PKey tables will be the same.
1433 */
1434 put_mdev = false;
1435 mdev = dev->mdev;
1436 mdev_port_num = 1;
1437 }
1438
1439 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1440 index, pkey);
1441 if (put_mdev)
1442 mlx5_ib_put_native_port_mdev(dev, port);
1443
1444 return err;
1445 }
1446
mlx5_ib_query_pkey(struct ib_device * ibdev,u32 port,u16 index,u16 * pkey)1447 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u32 port, u16 index,
1448 u16 *pkey)
1449 {
1450 switch (mlx5_get_vport_access_method(ibdev)) {
1451 case MLX5_VPORT_ACCESS_METHOD_MAD:
1452 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1453
1454 case MLX5_VPORT_ACCESS_METHOD_HCA:
1455 case MLX5_VPORT_ACCESS_METHOD_NIC:
1456 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1457 default:
1458 return -EINVAL;
1459 }
1460 }
1461
mlx5_ib_modify_device(struct ib_device * ibdev,int mask,struct ib_device_modify * props)1462 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1463 struct ib_device_modify *props)
1464 {
1465 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1466 struct mlx5_reg_node_desc in;
1467 struct mlx5_reg_node_desc out;
1468 int err;
1469
1470 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1471 return -EOPNOTSUPP;
1472
1473 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1474 return 0;
1475
1476 /*
1477 * If possible, pass node desc to FW, so it can generate
1478 * a 144 trap. If cmd fails, just ignore.
1479 */
1480 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1481 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
1482 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1483 if (err)
1484 return err;
1485
1486 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1487
1488 return err;
1489 }
1490
set_port_caps_atomic(struct mlx5_ib_dev * dev,u32 port_num,u32 mask,u32 value)1491 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u32 port_num, u32 mask,
1492 u32 value)
1493 {
1494 struct mlx5_hca_vport_context ctx = {};
1495 struct mlx5_core_dev *mdev;
1496 u32 mdev_port_num;
1497 int err;
1498
1499 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1500 if (!mdev)
1501 return -ENODEV;
1502
1503 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
1504 if (err)
1505 goto out;
1506
1507 if (~ctx.cap_mask1_perm & mask) {
1508 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1509 mask, ctx.cap_mask1_perm);
1510 err = -EINVAL;
1511 goto out;
1512 }
1513
1514 ctx.cap_mask1 = value;
1515 ctx.cap_mask1_perm = mask;
1516 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1517 0, &ctx);
1518
1519 out:
1520 mlx5_ib_put_native_port_mdev(dev, port_num);
1521
1522 return err;
1523 }
1524
mlx5_ib_modify_port(struct ib_device * ibdev,u32 port,int mask,struct ib_port_modify * props)1525 static int mlx5_ib_modify_port(struct ib_device *ibdev, u32 port, int mask,
1526 struct ib_port_modify *props)
1527 {
1528 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1529 struct ib_port_attr attr;
1530 u32 tmp;
1531 int err;
1532 u32 change_mask;
1533 u32 value;
1534 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1535 IB_LINK_LAYER_INFINIBAND);
1536
1537 /* CM layer calls ib_modify_port() regardless of the link layer. For
1538 * Ethernet ports, qkey violation and Port capabilities are meaningless.
1539 */
1540 if (!is_ib)
1541 return 0;
1542
1543 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1544 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1545 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1546 return set_port_caps_atomic(dev, port, change_mask, value);
1547 }
1548
1549 mutex_lock(&dev->cap_mask_mutex);
1550
1551 err = ib_query_port(ibdev, port, &attr);
1552 if (err)
1553 goto out;
1554
1555 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1556 ~props->clr_port_cap_mask;
1557
1558 err = mlx5_set_port_caps(dev->mdev, port, tmp);
1559
1560 out:
1561 mutex_unlock(&dev->cap_mask_mutex);
1562 return err;
1563 }
1564
print_lib_caps(struct mlx5_ib_dev * dev,u64 caps)1565 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1566 {
1567 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1568 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1569 }
1570
calc_dynamic_bfregs(int uars_per_sys_page)1571 static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1572 {
1573 /* Large page with non 4k uar support might limit the dynamic size */
1574 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096)
1575 return MLX5_MIN_DYN_BFREGS;
1576
1577 return MLX5_MAX_DYN_BFREGS;
1578 }
1579
calc_total_bfregs(struct mlx5_ib_dev * dev,bool lib_uar_4k,struct mlx5_ib_alloc_ucontext_req_v2 * req,struct mlx5_bfreg_info * bfregi)1580 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1581 struct mlx5_ib_alloc_ucontext_req_v2 *req,
1582 struct mlx5_bfreg_info *bfregi)
1583 {
1584 int uars_per_sys_page;
1585 int bfregs_per_sys_page;
1586 int ref_bfregs = req->total_num_bfregs;
1587
1588 if (req->total_num_bfregs == 0)
1589 return -EINVAL;
1590
1591 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1592 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1593
1594 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1595 return -ENOMEM;
1596
1597 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1598 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1599 /* This holds the required static allocation asked by the user */
1600 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1601 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1602 return -EINVAL;
1603
1604 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1605 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1606 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1607 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1608
1609 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
1610 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1611 lib_uar_4k ? "yes" : "no", ref_bfregs,
1612 req->total_num_bfregs, bfregi->total_num_bfregs,
1613 bfregi->num_sys_pages);
1614
1615 return 0;
1616 }
1617
allocate_uars(struct mlx5_ib_dev * dev,struct mlx5_ib_ucontext * context)1618 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1619 {
1620 struct mlx5_bfreg_info *bfregi;
1621 int err;
1622 int i;
1623
1624 bfregi = &context->bfregi;
1625 for (i = 0; i < bfregi->num_static_sys_pages; i++) {
1626 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1627 if (err)
1628 goto error;
1629
1630 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1631 }
1632
1633 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1634 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1635
1636 return 0;
1637
1638 error:
1639 for (--i; i >= 0; i--)
1640 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1641 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1642
1643 return err;
1644 }
1645
deallocate_uars(struct mlx5_ib_dev * dev,struct mlx5_ib_ucontext * context)1646 static void deallocate_uars(struct mlx5_ib_dev *dev,
1647 struct mlx5_ib_ucontext *context)
1648 {
1649 struct mlx5_bfreg_info *bfregi;
1650 int i;
1651
1652 bfregi = &context->bfregi;
1653 for (i = 0; i < bfregi->num_sys_pages; i++)
1654 if (i < bfregi->num_static_sys_pages ||
1655 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX)
1656 mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1657 }
1658
mlx5_ib_enable_lb(struct mlx5_ib_dev * dev,bool td,bool qp)1659 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
1660 {
1661 int err = 0;
1662
1663 mutex_lock(&dev->lb.mutex);
1664 if (td)
1665 dev->lb.user_td++;
1666 if (qp)
1667 dev->lb.qps++;
1668
1669 if (dev->lb.user_td == 2 ||
1670 dev->lb.qps == 1) {
1671 if (!dev->lb.enabled) {
1672 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1673 dev->lb.enabled = true;
1674 }
1675 }
1676
1677 mutex_unlock(&dev->lb.mutex);
1678
1679 return err;
1680 }
1681
mlx5_ib_disable_lb(struct mlx5_ib_dev * dev,bool td,bool qp)1682 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
1683 {
1684 mutex_lock(&dev->lb.mutex);
1685 if (td)
1686 dev->lb.user_td--;
1687 if (qp)
1688 dev->lb.qps--;
1689
1690 if (dev->lb.user_td == 1 &&
1691 dev->lb.qps == 0) {
1692 if (dev->lb.enabled) {
1693 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1694 dev->lb.enabled = false;
1695 }
1696 }
1697
1698 mutex_unlock(&dev->lb.mutex);
1699 }
1700
mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev * dev,u32 * tdn,u16 uid)1701 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn,
1702 u16 uid)
1703 {
1704 int err;
1705
1706 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1707 return 0;
1708
1709 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid);
1710 if (err)
1711 return err;
1712
1713 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1714 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1715 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1716 return err;
1717
1718 return mlx5_ib_enable_lb(dev, true, false);
1719 }
1720
mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev * dev,u32 tdn,u16 uid)1721 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn,
1722 u16 uid)
1723 {
1724 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1725 return;
1726
1727 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid);
1728
1729 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1730 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1731 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1732 return;
1733
1734 mlx5_ib_disable_lb(dev, true, false);
1735 }
1736
set_ucontext_resp(struct ib_ucontext * uctx,struct mlx5_ib_alloc_ucontext_resp * resp)1737 static int set_ucontext_resp(struct ib_ucontext *uctx,
1738 struct mlx5_ib_alloc_ucontext_resp *resp)
1739 {
1740 struct ib_device *ibdev = uctx->device;
1741 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1742 struct mlx5_ib_ucontext *context = to_mucontext(uctx);
1743 struct mlx5_bfreg_info *bfregi = &context->bfregi;
1744 int err;
1745
1746 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1747 err = mlx5_cmd_dump_fill_mkey(dev->mdev,
1748 &resp->dump_fill_mkey);
1749 if (err)
1750 return err;
1751 resp->comp_mask |=
1752 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY;
1753 }
1754
1755 resp->qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1756 if (dev->wc_support)
1757 resp->bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev,
1758 log_bf_reg_size);
1759 resp->cache_line_size = cache_line_size();
1760 resp->max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1761 resp->max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1762 resp->max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1763 resp->max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1764 resp->max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1765 resp->cqe_version = context->cqe_version;
1766 resp->log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1767 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1768 resp->num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1769 MLX5_CAP_GEN(dev->mdev,
1770 num_of_uars_per_page) : 1;
1771
1772 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
1773 MLX5_ACCEL_IPSEC_CAP_DEVICE) {
1774 if (mlx5_get_flow_namespace(dev->mdev,
1775 MLX5_FLOW_NAMESPACE_EGRESS))
1776 resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM;
1777 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
1778 MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA)
1779 resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA;
1780 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi))
1781 resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING;
1782 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
1783 MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN)
1784 resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN;
1785 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */
1786 }
1787
1788 resp->tot_bfregs = bfregi->lib_uar_dyn ? 0 :
1789 bfregi->total_num_bfregs - bfregi->num_dyn_bfregs;
1790 resp->num_ports = dev->num_ports;
1791 resp->cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1792 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1793
1794 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1795 mlx5_query_min_inline(dev->mdev, &resp->eth_min_inline);
1796 resp->eth_min_inline++;
1797 }
1798
1799 if (dev->mdev->clock_info)
1800 resp->clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1801
1802 /*
1803 * We don't want to expose information from the PCI bar that is located
1804 * after 4096 bytes, so if the arch only supports larger pages, let's
1805 * pretend we don't support reading the HCA's core clock. This is also
1806 * forced by mmap function.
1807 */
1808 if (PAGE_SIZE <= 4096) {
1809 resp->comp_mask |=
1810 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1811 resp->hca_core_clock_offset =
1812 offsetof(struct mlx5_init_seg,
1813 internal_timer_h) % PAGE_SIZE;
1814 }
1815
1816 if (MLX5_CAP_GEN(dev->mdev, ece_support))
1817 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE;
1818
1819 resp->num_dyn_bfregs = bfregi->num_dyn_bfregs;
1820 return 0;
1821 }
1822
mlx5_ib_alloc_ucontext(struct ib_ucontext * uctx,struct ib_udata * udata)1823 static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx,
1824 struct ib_udata *udata)
1825 {
1826 struct ib_device *ibdev = uctx->device;
1827 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1828 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1829 struct mlx5_ib_alloc_ucontext_resp resp = {};
1830 struct mlx5_ib_ucontext *context = to_mucontext(uctx);
1831 struct mlx5_bfreg_info *bfregi;
1832 int ver;
1833 int err;
1834 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1835 max_cqe_version);
1836 bool lib_uar_4k;
1837 bool lib_uar_dyn;
1838
1839 if (!dev->ib_active)
1840 return -EAGAIN;
1841
1842 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1843 ver = 0;
1844 else if (udata->inlen >= min_req_v2)
1845 ver = 2;
1846 else
1847 return -EINVAL;
1848
1849 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
1850 if (err)
1851 return err;
1852
1853 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX)
1854 return -EOPNOTSUPP;
1855
1856 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1857 return -EOPNOTSUPP;
1858
1859 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1860 MLX5_NON_FP_BFREGS_PER_UAR);
1861 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
1862 return -EINVAL;
1863
1864 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
1865 lib_uar_dyn = req.lib_caps & MLX5_LIB_CAP_DYN_UAR;
1866 bfregi = &context->bfregi;
1867
1868 if (lib_uar_dyn) {
1869 bfregi->lib_uar_dyn = lib_uar_dyn;
1870 goto uar_done;
1871 }
1872
1873 /* updates req->total_num_bfregs */
1874 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
1875 if (err)
1876 goto out_ctx;
1877
1878 mutex_init(&bfregi->lock);
1879 bfregi->lib_uar_4k = lib_uar_4k;
1880 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
1881 GFP_KERNEL);
1882 if (!bfregi->count) {
1883 err = -ENOMEM;
1884 goto out_ctx;
1885 }
1886
1887 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1888 sizeof(*bfregi->sys_pages),
1889 GFP_KERNEL);
1890 if (!bfregi->sys_pages) {
1891 err = -ENOMEM;
1892 goto out_count;
1893 }
1894
1895 err = allocate_uars(dev, context);
1896 if (err)
1897 goto out_sys_pages;
1898
1899 uar_done:
1900 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) {
1901 err = mlx5_ib_devx_create(dev, true);
1902 if (err < 0)
1903 goto out_uars;
1904 context->devx_uid = err;
1905 }
1906
1907 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn,
1908 context->devx_uid);
1909 if (err)
1910 goto out_devx;
1911
1912 INIT_LIST_HEAD(&context->db_page_list);
1913 mutex_init(&context->db_page_mutex);
1914
1915 context->cqe_version = min_t(__u8,
1916 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1917 req.max_cqe_version);
1918
1919 err = set_ucontext_resp(uctx, &resp);
1920 if (err)
1921 goto out_mdev;
1922
1923 resp.response_length = min(udata->outlen, sizeof(resp));
1924 err = ib_copy_to_udata(udata, &resp, resp.response_length);
1925 if (err)
1926 goto out_mdev;
1927
1928 bfregi->ver = ver;
1929 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
1930 context->lib_caps = req.lib_caps;
1931 print_lib_caps(dev, context->lib_caps);
1932
1933 if (mlx5_ib_lag_should_assign_affinity(dev)) {
1934 u32 port = mlx5_core_native_port_num(dev->mdev) - 1;
1935
1936 atomic_set(&context->tx_port_affinity,
1937 atomic_add_return(
1938 1, &dev->port[port].roce.tx_port_affinity));
1939 }
1940
1941 return 0;
1942
1943 out_mdev:
1944 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
1945 out_devx:
1946 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX)
1947 mlx5_ib_devx_destroy(dev, context->devx_uid);
1948
1949 out_uars:
1950 deallocate_uars(dev, context);
1951
1952 out_sys_pages:
1953 kfree(bfregi->sys_pages);
1954
1955 out_count:
1956 kfree(bfregi->count);
1957
1958 out_ctx:
1959 return err;
1960 }
1961
mlx5_ib_query_ucontext(struct ib_ucontext * ibcontext,struct uverbs_attr_bundle * attrs)1962 static int mlx5_ib_query_ucontext(struct ib_ucontext *ibcontext,
1963 struct uverbs_attr_bundle *attrs)
1964 {
1965 struct mlx5_ib_alloc_ucontext_resp uctx_resp = {};
1966 int ret;
1967
1968 ret = set_ucontext_resp(ibcontext, &uctx_resp);
1969 if (ret)
1970 return ret;
1971
1972 uctx_resp.response_length =
1973 min_t(size_t,
1974 uverbs_attr_get_len(attrs,
1975 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX),
1976 sizeof(uctx_resp));
1977
1978 ret = uverbs_copy_to_struct_or_zero(attrs,
1979 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX,
1980 &uctx_resp,
1981 sizeof(uctx_resp));
1982 return ret;
1983 }
1984
mlx5_ib_dealloc_ucontext(struct ib_ucontext * ibcontext)1985 static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1986 {
1987 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1988 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1989 struct mlx5_bfreg_info *bfregi;
1990
1991 bfregi = &context->bfregi;
1992 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
1993
1994 if (context->devx_uid)
1995 mlx5_ib_devx_destroy(dev, context->devx_uid);
1996
1997 deallocate_uars(dev, context);
1998 kfree(bfregi->sys_pages);
1999 kfree(bfregi->count);
2000 }
2001
uar_index2pfn(struct mlx5_ib_dev * dev,int uar_idx)2002 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
2003 int uar_idx)
2004 {
2005 int fw_uars_per_page;
2006
2007 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
2008
2009 return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
2010 }
2011
uar_index2paddress(struct mlx5_ib_dev * dev,int uar_idx)2012 static u64 uar_index2paddress(struct mlx5_ib_dev *dev,
2013 int uar_idx)
2014 {
2015 unsigned int fw_uars_per_page;
2016
2017 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
2018 MLX5_UARS_IN_PAGE : 1;
2019
2020 return (dev->mdev->bar_addr + (uar_idx / fw_uars_per_page) * PAGE_SIZE);
2021 }
2022
get_command(unsigned long offset)2023 static int get_command(unsigned long offset)
2024 {
2025 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
2026 }
2027
get_arg(unsigned long offset)2028 static int get_arg(unsigned long offset)
2029 {
2030 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
2031 }
2032
get_index(unsigned long offset)2033 static int get_index(unsigned long offset)
2034 {
2035 return get_arg(offset);
2036 }
2037
2038 /* Index resides in an extra byte to enable larger values than 255 */
get_extended_index(unsigned long offset)2039 static int get_extended_index(unsigned long offset)
2040 {
2041 return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
2042 }
2043
2044
mlx5_ib_disassociate_ucontext(struct ib_ucontext * ibcontext)2045 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
2046 {
2047 }
2048
mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)2049 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
2050 {
2051 switch (cmd) {
2052 case MLX5_IB_MMAP_WC_PAGE:
2053 return "WC";
2054 case MLX5_IB_MMAP_REGULAR_PAGE:
2055 return "best effort WC";
2056 case MLX5_IB_MMAP_NC_PAGE:
2057 return "NC";
2058 case MLX5_IB_MMAP_DEVICE_MEM:
2059 return "Device Memory";
2060 default:
2061 return NULL;
2062 }
2063 }
2064
mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev * dev,struct vm_area_struct * vma,struct mlx5_ib_ucontext * context)2065 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
2066 struct vm_area_struct *vma,
2067 struct mlx5_ib_ucontext *context)
2068 {
2069 if ((vma->vm_end - vma->vm_start != PAGE_SIZE) ||
2070 !(vma->vm_flags & VM_SHARED))
2071 return -EINVAL;
2072
2073 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
2074 return -EOPNOTSUPP;
2075
2076 if (vma->vm_flags & (VM_WRITE | VM_EXEC))
2077 return -EPERM;
2078 vma->vm_flags &= ~VM_MAYWRITE;
2079
2080 if (!dev->mdev->clock_info)
2081 return -EOPNOTSUPP;
2082
2083 return vm_insert_page(vma, vma->vm_start,
2084 virt_to_page(dev->mdev->clock_info));
2085 }
2086
mlx5_ib_mmap_free(struct rdma_user_mmap_entry * entry)2087 static void mlx5_ib_mmap_free(struct rdma_user_mmap_entry *entry)
2088 {
2089 struct mlx5_user_mmap_entry *mentry = to_mmmap(entry);
2090 struct mlx5_ib_dev *dev = to_mdev(entry->ucontext->device);
2091 struct mlx5_var_table *var_table = &dev->var_table;
2092
2093 switch (mentry->mmap_flag) {
2094 case MLX5_IB_MMAP_TYPE_MEMIC:
2095 case MLX5_IB_MMAP_TYPE_MEMIC_OP:
2096 mlx5_ib_dm_mmap_free(dev, mentry);
2097 break;
2098 case MLX5_IB_MMAP_TYPE_VAR:
2099 mutex_lock(&var_table->bitmap_lock);
2100 clear_bit(mentry->page_idx, var_table->bitmap);
2101 mutex_unlock(&var_table->bitmap_lock);
2102 kfree(mentry);
2103 break;
2104 case MLX5_IB_MMAP_TYPE_UAR_WC:
2105 case MLX5_IB_MMAP_TYPE_UAR_NC:
2106 mlx5_cmd_free_uar(dev->mdev, mentry->page_idx);
2107 kfree(mentry);
2108 break;
2109 default:
2110 WARN_ON(true);
2111 }
2112 }
2113
uar_mmap(struct mlx5_ib_dev * dev,enum mlx5_ib_mmap_cmd cmd,struct vm_area_struct * vma,struct mlx5_ib_ucontext * context)2114 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
2115 struct vm_area_struct *vma,
2116 struct mlx5_ib_ucontext *context)
2117 {
2118 struct mlx5_bfreg_info *bfregi = &context->bfregi;
2119 int err;
2120 unsigned long idx;
2121 phys_addr_t pfn;
2122 pgprot_t prot;
2123 u32 bfreg_dyn_idx = 0;
2124 u32 uar_index;
2125 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2126 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2127 bfregi->num_static_sys_pages;
2128
2129 if (bfregi->lib_uar_dyn)
2130 return -EINVAL;
2131
2132 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2133 return -EINVAL;
2134
2135 if (dyn_uar)
2136 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2137 else
2138 idx = get_index(vma->vm_pgoff);
2139
2140 if (idx >= max_valid_idx) {
2141 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2142 idx, max_valid_idx);
2143 return -EINVAL;
2144 }
2145
2146 switch (cmd) {
2147 case MLX5_IB_MMAP_WC_PAGE:
2148 case MLX5_IB_MMAP_ALLOC_WC:
2149 case MLX5_IB_MMAP_REGULAR_PAGE:
2150 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2151 prot = pgprot_writecombine(vma->vm_page_prot);
2152 break;
2153 case MLX5_IB_MMAP_NC_PAGE:
2154 prot = pgprot_noncached(vma->vm_page_prot);
2155 break;
2156 default:
2157 return -EINVAL;
2158 }
2159
2160 if (dyn_uar) {
2161 int uars_per_page;
2162
2163 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2164 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2165 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2166 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2167 bfreg_dyn_idx, bfregi->total_num_bfregs);
2168 return -EINVAL;
2169 }
2170
2171 mutex_lock(&bfregi->lock);
2172 /* Fail if uar already allocated, first bfreg index of each
2173 * page holds its count.
2174 */
2175 if (bfregi->count[bfreg_dyn_idx]) {
2176 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2177 mutex_unlock(&bfregi->lock);
2178 return -EINVAL;
2179 }
2180
2181 bfregi->count[bfreg_dyn_idx]++;
2182 mutex_unlock(&bfregi->lock);
2183
2184 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
2185 if (err) {
2186 mlx5_ib_warn(dev, "UAR alloc failed\n");
2187 goto free_bfreg;
2188 }
2189 } else {
2190 uar_index = bfregi->sys_pages[idx];
2191 }
2192
2193 pfn = uar_index2pfn(dev, uar_index);
2194 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2195
2196 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE,
2197 prot, NULL);
2198 if (err) {
2199 mlx5_ib_err(dev,
2200 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n",
2201 err, mmap_cmd2str(cmd));
2202 goto err;
2203 }
2204
2205 if (dyn_uar)
2206 bfregi->sys_pages[idx] = uar_index;
2207 return 0;
2208
2209 err:
2210 if (!dyn_uar)
2211 return err;
2212
2213 mlx5_cmd_free_uar(dev->mdev, idx);
2214
2215 free_bfreg:
2216 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2217
2218 return err;
2219 }
2220
mlx5_vma_to_pgoff(struct vm_area_struct * vma)2221 static unsigned long mlx5_vma_to_pgoff(struct vm_area_struct *vma)
2222 {
2223 unsigned long idx;
2224 u8 command;
2225
2226 command = get_command(vma->vm_pgoff);
2227 idx = get_extended_index(vma->vm_pgoff);
2228
2229 return (command << 16 | idx);
2230 }
2231
mlx5_ib_mmap_offset(struct mlx5_ib_dev * dev,struct vm_area_struct * vma,struct ib_ucontext * ucontext)2232 static int mlx5_ib_mmap_offset(struct mlx5_ib_dev *dev,
2233 struct vm_area_struct *vma,
2234 struct ib_ucontext *ucontext)
2235 {
2236 struct mlx5_user_mmap_entry *mentry;
2237 struct rdma_user_mmap_entry *entry;
2238 unsigned long pgoff;
2239 pgprot_t prot;
2240 phys_addr_t pfn;
2241 int ret;
2242
2243 pgoff = mlx5_vma_to_pgoff(vma);
2244 entry = rdma_user_mmap_entry_get_pgoff(ucontext, pgoff);
2245 if (!entry)
2246 return -EINVAL;
2247
2248 mentry = to_mmmap(entry);
2249 pfn = (mentry->address >> PAGE_SHIFT);
2250 if (mentry->mmap_flag == MLX5_IB_MMAP_TYPE_VAR ||
2251 mentry->mmap_flag == MLX5_IB_MMAP_TYPE_UAR_NC)
2252 prot = pgprot_noncached(vma->vm_page_prot);
2253 else
2254 prot = pgprot_writecombine(vma->vm_page_prot);
2255 ret = rdma_user_mmap_io(ucontext, vma, pfn,
2256 entry->npages * PAGE_SIZE,
2257 prot,
2258 entry);
2259 rdma_user_mmap_entry_put(&mentry->rdma_entry);
2260 return ret;
2261 }
2262
mlx5_entry_to_mmap_offset(struct mlx5_user_mmap_entry * entry)2263 static u64 mlx5_entry_to_mmap_offset(struct mlx5_user_mmap_entry *entry)
2264 {
2265 u64 cmd = (entry->rdma_entry.start_pgoff >> 16) & 0xFFFF;
2266 u64 index = entry->rdma_entry.start_pgoff & 0xFFFF;
2267
2268 return (((index >> 8) << 16) | (cmd << MLX5_IB_MMAP_CMD_SHIFT) |
2269 (index & 0xFF)) << PAGE_SHIFT;
2270 }
2271
mlx5_ib_mmap(struct ib_ucontext * ibcontext,struct vm_area_struct * vma)2272 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2273 {
2274 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2275 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
2276 unsigned long command;
2277 phys_addr_t pfn;
2278
2279 command = get_command(vma->vm_pgoff);
2280 switch (command) {
2281 case MLX5_IB_MMAP_WC_PAGE:
2282 case MLX5_IB_MMAP_ALLOC_WC:
2283 if (!dev->wc_support)
2284 return -EPERM;
2285 fallthrough;
2286 case MLX5_IB_MMAP_NC_PAGE:
2287 case MLX5_IB_MMAP_REGULAR_PAGE:
2288 return uar_mmap(dev, command, vma, context);
2289
2290 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2291 return -ENOSYS;
2292
2293 case MLX5_IB_MMAP_CORE_CLOCK:
2294 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2295 return -EINVAL;
2296
2297 if (vma->vm_flags & VM_WRITE)
2298 return -EPERM;
2299 vma->vm_flags &= ~VM_MAYWRITE;
2300
2301 /* Don't expose to user-space information it shouldn't have */
2302 if (PAGE_SIZE > 4096)
2303 return -EOPNOTSUPP;
2304
2305 pfn = (dev->mdev->iseg_base +
2306 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2307 PAGE_SHIFT;
2308 return rdma_user_mmap_io(&context->ibucontext, vma, pfn,
2309 PAGE_SIZE,
2310 pgprot_noncached(vma->vm_page_prot),
2311 NULL);
2312 case MLX5_IB_MMAP_CLOCK_INFO:
2313 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
2314
2315 default:
2316 return mlx5_ib_mmap_offset(dev, vma, ibcontext);
2317 }
2318
2319 return 0;
2320 }
2321
mlx5_ib_alloc_pd(struct ib_pd * ibpd,struct ib_udata * udata)2322 static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
2323 {
2324 struct mlx5_ib_pd *pd = to_mpd(ibpd);
2325 struct ib_device *ibdev = ibpd->device;
2326 struct mlx5_ib_alloc_pd_resp resp;
2327 int err;
2328 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {};
2329 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {};
2330 u16 uid = 0;
2331 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
2332 udata, struct mlx5_ib_ucontext, ibucontext);
2333
2334 uid = context ? context->devx_uid : 0;
2335 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2336 MLX5_SET(alloc_pd_in, in, uid, uid);
2337 err = mlx5_cmd_exec_inout(to_mdev(ibdev)->mdev, alloc_pd, in, out);
2338 if (err)
2339 return err;
2340
2341 pd->pdn = MLX5_GET(alloc_pd_out, out, pd);
2342 pd->uid = uid;
2343 if (udata) {
2344 resp.pdn = pd->pdn;
2345 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
2346 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid);
2347 return -EFAULT;
2348 }
2349 }
2350
2351 return 0;
2352 }
2353
mlx5_ib_dealloc_pd(struct ib_pd * pd,struct ib_udata * udata)2354 static int mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata)
2355 {
2356 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2357 struct mlx5_ib_pd *mpd = to_mpd(pd);
2358
2359 return mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid);
2360 }
2361
mlx5_ib_mcg_attach(struct ib_qp * ibqp,union ib_gid * gid,u16 lid)2362 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2363 {
2364 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2365 struct mlx5_ib_qp *mqp = to_mqp(ibqp);
2366 int err;
2367 u16 uid;
2368
2369 uid = ibqp->pd ?
2370 to_mpd(ibqp->pd)->uid : 0;
2371
2372 if (mqp->flags & IB_QP_CREATE_SOURCE_QPN) {
2373 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
2374 return -EOPNOTSUPP;
2375 }
2376
2377 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
2378 if (err)
2379 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2380 ibqp->qp_num, gid->raw);
2381
2382 return err;
2383 }
2384
mlx5_ib_mcg_detach(struct ib_qp * ibqp,union ib_gid * gid,u16 lid)2385 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2386 {
2387 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2388 int err;
2389 u16 uid;
2390
2391 uid = ibqp->pd ?
2392 to_mpd(ibqp->pd)->uid : 0;
2393 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
2394 if (err)
2395 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2396 ibqp->qp_num, gid->raw);
2397
2398 return err;
2399 }
2400
init_node_data(struct mlx5_ib_dev * dev)2401 static int init_node_data(struct mlx5_ib_dev *dev)
2402 {
2403 int err;
2404
2405 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
2406 if (err)
2407 return err;
2408
2409 dev->mdev->rev_id = dev->mdev->pdev->revision;
2410
2411 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
2412 }
2413
fw_pages_show(struct device * device,struct device_attribute * attr,char * buf)2414 static ssize_t fw_pages_show(struct device *device,
2415 struct device_attribute *attr, char *buf)
2416 {
2417 struct mlx5_ib_dev *dev =
2418 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2419
2420 return sysfs_emit(buf, "%d\n", dev->mdev->priv.fw_pages);
2421 }
2422 static DEVICE_ATTR_RO(fw_pages);
2423
reg_pages_show(struct device * device,struct device_attribute * attr,char * buf)2424 static ssize_t reg_pages_show(struct device *device,
2425 struct device_attribute *attr, char *buf)
2426 {
2427 struct mlx5_ib_dev *dev =
2428 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2429
2430 return sysfs_emit(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
2431 }
2432 static DEVICE_ATTR_RO(reg_pages);
2433
hca_type_show(struct device * device,struct device_attribute * attr,char * buf)2434 static ssize_t hca_type_show(struct device *device,
2435 struct device_attribute *attr, char *buf)
2436 {
2437 struct mlx5_ib_dev *dev =
2438 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2439
2440 return sysfs_emit(buf, "MT%d\n", dev->mdev->pdev->device);
2441 }
2442 static DEVICE_ATTR_RO(hca_type);
2443
hw_rev_show(struct device * device,struct device_attribute * attr,char * buf)2444 static ssize_t hw_rev_show(struct device *device,
2445 struct device_attribute *attr, char *buf)
2446 {
2447 struct mlx5_ib_dev *dev =
2448 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2449
2450 return sysfs_emit(buf, "%x\n", dev->mdev->rev_id);
2451 }
2452 static DEVICE_ATTR_RO(hw_rev);
2453
board_id_show(struct device * device,struct device_attribute * attr,char * buf)2454 static ssize_t board_id_show(struct device *device,
2455 struct device_attribute *attr, char *buf)
2456 {
2457 struct mlx5_ib_dev *dev =
2458 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2459
2460 return sysfs_emit(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
2461 dev->mdev->board_id);
2462 }
2463 static DEVICE_ATTR_RO(board_id);
2464
2465 static struct attribute *mlx5_class_attributes[] = {
2466 &dev_attr_hw_rev.attr,
2467 &dev_attr_hca_type.attr,
2468 &dev_attr_board_id.attr,
2469 &dev_attr_fw_pages.attr,
2470 &dev_attr_reg_pages.attr,
2471 NULL,
2472 };
2473
2474 static const struct attribute_group mlx5_attr_group = {
2475 .attrs = mlx5_class_attributes,
2476 };
2477
pkey_change_handler(struct work_struct * work)2478 static void pkey_change_handler(struct work_struct *work)
2479 {
2480 struct mlx5_ib_port_resources *ports =
2481 container_of(work, struct mlx5_ib_port_resources,
2482 pkey_change_work);
2483
2484 mlx5_ib_gsi_pkey_change(ports->gsi);
2485 }
2486
mlx5_ib_handle_internal_error(struct mlx5_ib_dev * ibdev)2487 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2488 {
2489 struct mlx5_ib_qp *mqp;
2490 struct mlx5_ib_cq *send_mcq, *recv_mcq;
2491 struct mlx5_core_cq *mcq;
2492 struct list_head cq_armed_list;
2493 unsigned long flags_qp;
2494 unsigned long flags_cq;
2495 unsigned long flags;
2496
2497 INIT_LIST_HEAD(&cq_armed_list);
2498
2499 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2500 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2501 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2502 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2503 if (mqp->sq.tail != mqp->sq.head) {
2504 send_mcq = to_mcq(mqp->ibqp.send_cq);
2505 spin_lock_irqsave(&send_mcq->lock, flags_cq);
2506 if (send_mcq->mcq.comp &&
2507 mqp->ibqp.send_cq->comp_handler) {
2508 if (!send_mcq->mcq.reset_notify_added) {
2509 send_mcq->mcq.reset_notify_added = 1;
2510 list_add_tail(&send_mcq->mcq.reset_notify,
2511 &cq_armed_list);
2512 }
2513 }
2514 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2515 }
2516 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2517 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2518 /* no handling is needed for SRQ */
2519 if (!mqp->ibqp.srq) {
2520 if (mqp->rq.tail != mqp->rq.head) {
2521 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2522 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2523 if (recv_mcq->mcq.comp &&
2524 mqp->ibqp.recv_cq->comp_handler) {
2525 if (!recv_mcq->mcq.reset_notify_added) {
2526 recv_mcq->mcq.reset_notify_added = 1;
2527 list_add_tail(&recv_mcq->mcq.reset_notify,
2528 &cq_armed_list);
2529 }
2530 }
2531 spin_unlock_irqrestore(&recv_mcq->lock,
2532 flags_cq);
2533 }
2534 }
2535 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2536 }
2537 /*At that point all inflight post send were put to be executed as of we
2538 * lock/unlock above locks Now need to arm all involved CQs.
2539 */
2540 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2541 mcq->comp(mcq, NULL);
2542 }
2543 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2544 }
2545
delay_drop_handler(struct work_struct * work)2546 static void delay_drop_handler(struct work_struct *work)
2547 {
2548 int err;
2549 struct mlx5_ib_delay_drop *delay_drop =
2550 container_of(work, struct mlx5_ib_delay_drop,
2551 delay_drop_work);
2552
2553 atomic_inc(&delay_drop->events_cnt);
2554
2555 mutex_lock(&delay_drop->lock);
2556 err = mlx5_core_set_delay_drop(delay_drop->dev, delay_drop->timeout);
2557 if (err) {
2558 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
2559 delay_drop->timeout);
2560 delay_drop->activate = false;
2561 }
2562 mutex_unlock(&delay_drop->lock);
2563 }
2564
handle_general_event(struct mlx5_ib_dev * ibdev,struct mlx5_eqe * eqe,struct ib_event * ibev)2565 static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
2566 struct ib_event *ibev)
2567 {
2568 u32 port = (eqe->data.port.port >> 4) & 0xf;
2569
2570 switch (eqe->sub_type) {
2571 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT:
2572 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2573 IB_LINK_LAYER_ETHERNET)
2574 schedule_work(&ibdev->delay_drop.delay_drop_work);
2575 break;
2576 default: /* do nothing */
2577 return;
2578 }
2579 }
2580
handle_port_change(struct mlx5_ib_dev * ibdev,struct mlx5_eqe * eqe,struct ib_event * ibev)2581 static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
2582 struct ib_event *ibev)
2583 {
2584 u32 port = (eqe->data.port.port >> 4) & 0xf;
2585
2586 ibev->element.port_num = port;
2587
2588 switch (eqe->sub_type) {
2589 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
2590 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
2591 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
2592 /* In RoCE, port up/down events are handled in
2593 * mlx5_netdev_event().
2594 */
2595 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2596 IB_LINK_LAYER_ETHERNET)
2597 return -EINVAL;
2598
2599 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ?
2600 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
2601 break;
2602
2603 case MLX5_PORT_CHANGE_SUBTYPE_LID:
2604 ibev->event = IB_EVENT_LID_CHANGE;
2605 break;
2606
2607 case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
2608 ibev->event = IB_EVENT_PKEY_CHANGE;
2609 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
2610 break;
2611
2612 case MLX5_PORT_CHANGE_SUBTYPE_GUID:
2613 ibev->event = IB_EVENT_GID_CHANGE;
2614 break;
2615
2616 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
2617 ibev->event = IB_EVENT_CLIENT_REREGISTER;
2618 break;
2619 default:
2620 return -EINVAL;
2621 }
2622
2623 return 0;
2624 }
2625
mlx5_ib_handle_event(struct work_struct * _work)2626 static void mlx5_ib_handle_event(struct work_struct *_work)
2627 {
2628 struct mlx5_ib_event_work *work =
2629 container_of(_work, struct mlx5_ib_event_work, work);
2630 struct mlx5_ib_dev *ibdev;
2631 struct ib_event ibev;
2632 bool fatal = false;
2633
2634 if (work->is_slave) {
2635 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi);
2636 if (!ibdev)
2637 goto out;
2638 } else {
2639 ibdev = work->dev;
2640 }
2641
2642 switch (work->event) {
2643 case MLX5_DEV_EVENT_SYS_ERROR:
2644 ibev.event = IB_EVENT_DEVICE_FATAL;
2645 mlx5_ib_handle_internal_error(ibdev);
2646 ibev.element.port_num = (u8)(unsigned long)work->param;
2647 fatal = true;
2648 break;
2649 case MLX5_EVENT_TYPE_PORT_CHANGE:
2650 if (handle_port_change(ibdev, work->param, &ibev))
2651 goto out;
2652 break;
2653 case MLX5_EVENT_TYPE_GENERAL_EVENT:
2654 handle_general_event(ibdev, work->param, &ibev);
2655 fallthrough;
2656 default:
2657 goto out;
2658 }
2659
2660 ibev.device = &ibdev->ib_dev;
2661
2662 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) {
2663 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num);
2664 goto out;
2665 }
2666
2667 if (ibdev->ib_active)
2668 ib_dispatch_event(&ibev);
2669
2670 if (fatal)
2671 ibdev->ib_active = false;
2672 out:
2673 kfree(work);
2674 }
2675
mlx5_ib_event(struct notifier_block * nb,unsigned long event,void * param)2676 static int mlx5_ib_event(struct notifier_block *nb,
2677 unsigned long event, void *param)
2678 {
2679 struct mlx5_ib_event_work *work;
2680
2681 work = kmalloc(sizeof(*work), GFP_ATOMIC);
2682 if (!work)
2683 return NOTIFY_DONE;
2684
2685 INIT_WORK(&work->work, mlx5_ib_handle_event);
2686 work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events);
2687 work->is_slave = false;
2688 work->param = param;
2689 work->event = event;
2690
2691 queue_work(mlx5_ib_event_wq, &work->work);
2692
2693 return NOTIFY_OK;
2694 }
2695
mlx5_ib_event_slave_port(struct notifier_block * nb,unsigned long event,void * param)2696 static int mlx5_ib_event_slave_port(struct notifier_block *nb,
2697 unsigned long event, void *param)
2698 {
2699 struct mlx5_ib_event_work *work;
2700
2701 work = kmalloc(sizeof(*work), GFP_ATOMIC);
2702 if (!work)
2703 return NOTIFY_DONE;
2704
2705 INIT_WORK(&work->work, mlx5_ib_handle_event);
2706 work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events);
2707 work->is_slave = true;
2708 work->param = param;
2709 work->event = event;
2710 queue_work(mlx5_ib_event_wq, &work->work);
2711
2712 return NOTIFY_OK;
2713 }
2714
set_has_smi_cap(struct mlx5_ib_dev * dev)2715 static int set_has_smi_cap(struct mlx5_ib_dev *dev)
2716 {
2717 struct mlx5_hca_vport_context vport_ctx;
2718 int err;
2719 int port;
2720
2721 for (port = 1; port <= ARRAY_SIZE(dev->port_caps); port++) {
2722 dev->port_caps[port - 1].has_smi = false;
2723 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
2724 MLX5_CAP_PORT_TYPE_IB) {
2725 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
2726 err = mlx5_query_hca_vport_context(dev->mdev, 0,
2727 port, 0,
2728 &vport_ctx);
2729 if (err) {
2730 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
2731 port, err);
2732 return err;
2733 }
2734 dev->port_caps[port - 1].has_smi =
2735 vport_ctx.has_smi;
2736 } else {
2737 dev->port_caps[port - 1].has_smi = true;
2738 }
2739 }
2740 }
2741 return 0;
2742 }
2743
get_ext_port_caps(struct mlx5_ib_dev * dev)2744 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2745 {
2746 unsigned int port;
2747
2748 rdma_for_each_port (&dev->ib_dev, port)
2749 mlx5_query_ext_port_caps(dev, port);
2750 }
2751
mlx5_get_umr_fence(u8 umr_fence_cap)2752 static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
2753 {
2754 switch (umr_fence_cap) {
2755 case MLX5_CAP_UMR_FENCE_NONE:
2756 return MLX5_FENCE_MODE_NONE;
2757 case MLX5_CAP_UMR_FENCE_SMALL:
2758 return MLX5_FENCE_MODE_INITIATOR_SMALL;
2759 default:
2760 return MLX5_FENCE_MODE_STRONG_ORDERING;
2761 }
2762 }
2763
mlx5_ib_dev_res_init(struct mlx5_ib_dev * dev)2764 static int mlx5_ib_dev_res_init(struct mlx5_ib_dev *dev)
2765 {
2766 struct mlx5_ib_resources *devr = &dev->devr;
2767 struct ib_srq_init_attr attr;
2768 struct ib_device *ibdev;
2769 struct ib_cq_init_attr cq_attr = {.cqe = 1};
2770 int port;
2771 int ret = 0;
2772
2773 ibdev = &dev->ib_dev;
2774
2775 if (!MLX5_CAP_GEN(dev->mdev, xrc))
2776 return -EOPNOTSUPP;
2777
2778 mutex_init(&devr->mutex);
2779
2780 devr->p0 = rdma_zalloc_drv_obj(ibdev, ib_pd);
2781 if (!devr->p0)
2782 return -ENOMEM;
2783
2784 devr->p0->device = ibdev;
2785 devr->p0->uobject = NULL;
2786 atomic_set(&devr->p0->usecnt, 0);
2787
2788 ret = mlx5_ib_alloc_pd(devr->p0, NULL);
2789 if (ret)
2790 goto error0;
2791
2792 devr->c0 = rdma_zalloc_drv_obj(ibdev, ib_cq);
2793 if (!devr->c0) {
2794 ret = -ENOMEM;
2795 goto error1;
2796 }
2797
2798 devr->c0->device = &dev->ib_dev;
2799 atomic_set(&devr->c0->usecnt, 0);
2800
2801 ret = mlx5_ib_create_cq(devr->c0, &cq_attr, NULL);
2802 if (ret)
2803 goto err_create_cq;
2804
2805 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn0, 0);
2806 if (ret)
2807 goto error2;
2808
2809 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn1, 0);
2810 if (ret)
2811 goto error3;
2812
2813 memset(&attr, 0, sizeof(attr));
2814 attr.attr.max_sge = 1;
2815 attr.attr.max_wr = 1;
2816 attr.srq_type = IB_SRQT_XRC;
2817 attr.ext.cq = devr->c0;
2818
2819 devr->s0 = rdma_zalloc_drv_obj(ibdev, ib_srq);
2820 if (!devr->s0) {
2821 ret = -ENOMEM;
2822 goto error4;
2823 }
2824
2825 devr->s0->device = &dev->ib_dev;
2826 devr->s0->pd = devr->p0;
2827 devr->s0->srq_type = IB_SRQT_XRC;
2828 devr->s0->ext.cq = devr->c0;
2829 ret = mlx5_ib_create_srq(devr->s0, &attr, NULL);
2830 if (ret)
2831 goto err_create;
2832
2833 atomic_inc(&devr->s0->ext.cq->usecnt);
2834 atomic_inc(&devr->p0->usecnt);
2835 atomic_set(&devr->s0->usecnt, 0);
2836
2837 memset(&attr, 0, sizeof(attr));
2838 attr.attr.max_sge = 1;
2839 attr.attr.max_wr = 1;
2840 attr.srq_type = IB_SRQT_BASIC;
2841 devr->s1 = rdma_zalloc_drv_obj(ibdev, ib_srq);
2842 if (!devr->s1) {
2843 ret = -ENOMEM;
2844 goto error5;
2845 }
2846
2847 devr->s1->device = &dev->ib_dev;
2848 devr->s1->pd = devr->p0;
2849 devr->s1->srq_type = IB_SRQT_BASIC;
2850 devr->s1->ext.cq = devr->c0;
2851
2852 ret = mlx5_ib_create_srq(devr->s1, &attr, NULL);
2853 if (ret)
2854 goto error6;
2855
2856 atomic_inc(&devr->p0->usecnt);
2857 atomic_set(&devr->s1->usecnt, 0);
2858
2859 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port)
2860 INIT_WORK(&devr->ports[port].pkey_change_work,
2861 pkey_change_handler);
2862
2863 return 0;
2864
2865 error6:
2866 kfree(devr->s1);
2867 error5:
2868 mlx5_ib_destroy_srq(devr->s0, NULL);
2869 err_create:
2870 kfree(devr->s0);
2871 error4:
2872 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0);
2873 error3:
2874 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0);
2875 error2:
2876 mlx5_ib_destroy_cq(devr->c0, NULL);
2877 err_create_cq:
2878 kfree(devr->c0);
2879 error1:
2880 mlx5_ib_dealloc_pd(devr->p0, NULL);
2881 error0:
2882 kfree(devr->p0);
2883 return ret;
2884 }
2885
mlx5_ib_dev_res_cleanup(struct mlx5_ib_dev * dev)2886 static void mlx5_ib_dev_res_cleanup(struct mlx5_ib_dev *dev)
2887 {
2888 struct mlx5_ib_resources *devr = &dev->devr;
2889 int port;
2890
2891 mlx5_ib_destroy_srq(devr->s1, NULL);
2892 kfree(devr->s1);
2893 mlx5_ib_destroy_srq(devr->s0, NULL);
2894 kfree(devr->s0);
2895 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0);
2896 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0);
2897 mlx5_ib_destroy_cq(devr->c0, NULL);
2898 kfree(devr->c0);
2899 mlx5_ib_dealloc_pd(devr->p0, NULL);
2900 kfree(devr->p0);
2901
2902 /* Make sure no change P_Key work items are still executing */
2903 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port)
2904 cancel_work_sync(&devr->ports[port].pkey_change_work);
2905 }
2906
get_core_cap_flags(struct ib_device * ibdev,struct mlx5_hca_vport_context * rep)2907 static u32 get_core_cap_flags(struct ib_device *ibdev,
2908 struct mlx5_hca_vport_context *rep)
2909 {
2910 struct mlx5_ib_dev *dev = to_mdev(ibdev);
2911 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
2912 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
2913 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
2914 bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
2915 u32 ret = 0;
2916
2917 if (rep->grh_required)
2918 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED;
2919
2920 if (ll == IB_LINK_LAYER_INFINIBAND)
2921 return ret | RDMA_CORE_PORT_IBA_IB;
2922
2923 if (raw_support)
2924 ret |= RDMA_CORE_PORT_RAW_PACKET;
2925
2926 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
2927 return ret;
2928
2929 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
2930 return ret;
2931
2932 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
2933 ret |= RDMA_CORE_PORT_IBA_ROCE;
2934
2935 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
2936 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
2937
2938 return ret;
2939 }
2940
mlx5_port_immutable(struct ib_device * ibdev,u32 port_num,struct ib_port_immutable * immutable)2941 static int mlx5_port_immutable(struct ib_device *ibdev, u32 port_num,
2942 struct ib_port_immutable *immutable)
2943 {
2944 struct ib_port_attr attr;
2945 struct mlx5_ib_dev *dev = to_mdev(ibdev);
2946 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
2947 struct mlx5_hca_vport_context rep = {0};
2948 int err;
2949
2950 err = ib_query_port(ibdev, port_num, &attr);
2951 if (err)
2952 return err;
2953
2954 if (ll == IB_LINK_LAYER_INFINIBAND) {
2955 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0,
2956 &rep);
2957 if (err)
2958 return err;
2959 }
2960
2961 immutable->pkey_tbl_len = attr.pkey_tbl_len;
2962 immutable->gid_tbl_len = attr.gid_tbl_len;
2963 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep);
2964 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
2965
2966 return 0;
2967 }
2968
mlx5_port_rep_immutable(struct ib_device * ibdev,u32 port_num,struct ib_port_immutable * immutable)2969 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u32 port_num,
2970 struct ib_port_immutable *immutable)
2971 {
2972 struct ib_port_attr attr;
2973 int err;
2974
2975 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
2976
2977 err = ib_query_port(ibdev, port_num, &attr);
2978 if (err)
2979 return err;
2980
2981 immutable->pkey_tbl_len = attr.pkey_tbl_len;
2982 immutable->gid_tbl_len = attr.gid_tbl_len;
2983 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
2984
2985 return 0;
2986 }
2987
get_dev_fw_str(struct ib_device * ibdev,char * str)2988 static void get_dev_fw_str(struct ib_device *ibdev, char *str)
2989 {
2990 struct mlx5_ib_dev *dev =
2991 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
2992 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
2993 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
2994 fw_rev_sub(dev->mdev));
2995 }
2996
mlx5_eth_lag_init(struct mlx5_ib_dev * dev)2997 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
2998 {
2999 struct mlx5_core_dev *mdev = dev->mdev;
3000 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
3001 MLX5_FLOW_NAMESPACE_LAG);
3002 struct mlx5_flow_table *ft;
3003 int err;
3004
3005 if (!ns || !mlx5_lag_is_roce(mdev))
3006 return 0;
3007
3008 err = mlx5_cmd_create_vport_lag(mdev);
3009 if (err)
3010 return err;
3011
3012 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
3013 if (IS_ERR(ft)) {
3014 err = PTR_ERR(ft);
3015 goto err_destroy_vport_lag;
3016 }
3017
3018 dev->flow_db->lag_demux_ft = ft;
3019 dev->lag_active = true;
3020 return 0;
3021
3022 err_destroy_vport_lag:
3023 mlx5_cmd_destroy_vport_lag(mdev);
3024 return err;
3025 }
3026
mlx5_eth_lag_cleanup(struct mlx5_ib_dev * dev)3027 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
3028 {
3029 struct mlx5_core_dev *mdev = dev->mdev;
3030
3031 if (dev->lag_active) {
3032 dev->lag_active = false;
3033
3034 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
3035 dev->flow_db->lag_demux_ft = NULL;
3036
3037 mlx5_cmd_destroy_vport_lag(mdev);
3038 }
3039 }
3040
mlx5_add_netdev_notifier(struct mlx5_ib_dev * dev,u32 port_num)3041 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u32 port_num)
3042 {
3043 int err;
3044
3045 dev->port[port_num].roce.nb.notifier_call = mlx5_netdev_event;
3046 err = register_netdevice_notifier(&dev->port[port_num].roce.nb);
3047 if (err) {
3048 dev->port[port_num].roce.nb.notifier_call = NULL;
3049 return err;
3050 }
3051
3052 return 0;
3053 }
3054
mlx5_remove_netdev_notifier(struct mlx5_ib_dev * dev,u32 port_num)3055 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u32 port_num)
3056 {
3057 if (dev->port[port_num].roce.nb.notifier_call) {
3058 unregister_netdevice_notifier(&dev->port[port_num].roce.nb);
3059 dev->port[port_num].roce.nb.notifier_call = NULL;
3060 }
3061 }
3062
mlx5_enable_eth(struct mlx5_ib_dev * dev)3063 static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
3064 {
3065 int err;
3066
3067 err = mlx5_nic_vport_enable_roce(dev->mdev);
3068 if (err)
3069 return err;
3070
3071 err = mlx5_eth_lag_init(dev);
3072 if (err)
3073 goto err_disable_roce;
3074
3075 return 0;
3076
3077 err_disable_roce:
3078 mlx5_nic_vport_disable_roce(dev->mdev);
3079
3080 return err;
3081 }
3082
mlx5_disable_eth(struct mlx5_ib_dev * dev)3083 static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
3084 {
3085 mlx5_eth_lag_cleanup(dev);
3086 mlx5_nic_vport_disable_roce(dev->mdev);
3087 }
3088
mlx5_ib_rn_get_params(struct ib_device * device,u32 port_num,enum rdma_netdev_t type,struct rdma_netdev_alloc_params * params)3089 static int mlx5_ib_rn_get_params(struct ib_device *device, u32 port_num,
3090 enum rdma_netdev_t type,
3091 struct rdma_netdev_alloc_params *params)
3092 {
3093 if (type != RDMA_NETDEV_IPOIB)
3094 return -EOPNOTSUPP;
3095
3096 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params);
3097 }
3098
delay_drop_timeout_read(struct file * filp,char __user * buf,size_t count,loff_t * pos)3099 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
3100 size_t count, loff_t *pos)
3101 {
3102 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
3103 char lbuf[20];
3104 int len;
3105
3106 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
3107 return simple_read_from_buffer(buf, count, pos, lbuf, len);
3108 }
3109
delay_drop_timeout_write(struct file * filp,const char __user * buf,size_t count,loff_t * pos)3110 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
3111 size_t count, loff_t *pos)
3112 {
3113 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
3114 u32 timeout;
3115 u32 var;
3116
3117 if (kstrtouint_from_user(buf, count, 0, &var))
3118 return -EFAULT;
3119
3120 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
3121 1000);
3122 if (timeout != var)
3123 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
3124 timeout);
3125
3126 delay_drop->timeout = timeout;
3127
3128 return count;
3129 }
3130
3131 static const struct file_operations fops_delay_drop_timeout = {
3132 .owner = THIS_MODULE,
3133 .open = simple_open,
3134 .write = delay_drop_timeout_write,
3135 .read = delay_drop_timeout_read,
3136 };
3137
mlx5_ib_unbind_slave_port(struct mlx5_ib_dev * ibdev,struct mlx5_ib_multiport_info * mpi)3138 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
3139 struct mlx5_ib_multiport_info *mpi)
3140 {
3141 u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
3142 struct mlx5_ib_port *port = &ibdev->port[port_num];
3143 int comps;
3144 int err;
3145 int i;
3146
3147 lockdep_assert_held(&mlx5_ib_multiport_mutex);
3148
3149 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
3150
3151 spin_lock(&port->mp.mpi_lock);
3152 if (!mpi->ibdev) {
3153 spin_unlock(&port->mp.mpi_lock);
3154 return;
3155 }
3156
3157 mpi->ibdev = NULL;
3158
3159 spin_unlock(&port->mp.mpi_lock);
3160 if (mpi->mdev_events.notifier_call)
3161 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events);
3162 mpi->mdev_events.notifier_call = NULL;
3163 mlx5_remove_netdev_notifier(ibdev, port_num);
3164 spin_lock(&port->mp.mpi_lock);
3165
3166 comps = mpi->mdev_refcnt;
3167 if (comps) {
3168 mpi->unaffiliate = true;
3169 init_completion(&mpi->unref_comp);
3170 spin_unlock(&port->mp.mpi_lock);
3171
3172 for (i = 0; i < comps; i++)
3173 wait_for_completion(&mpi->unref_comp);
3174
3175 spin_lock(&port->mp.mpi_lock);
3176 mpi->unaffiliate = false;
3177 }
3178
3179 port->mp.mpi = NULL;
3180
3181 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
3182
3183 spin_unlock(&port->mp.mpi_lock);
3184
3185 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
3186
3187 mlx5_ib_dbg(ibdev, "unaffiliated port %u\n", port_num + 1);
3188 /* Log an error, still needed to cleanup the pointers and add
3189 * it back to the list.
3190 */
3191 if (err)
3192 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
3193 port_num + 1);
3194
3195 ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN;
3196 }
3197
mlx5_ib_bind_slave_port(struct mlx5_ib_dev * ibdev,struct mlx5_ib_multiport_info * mpi)3198 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
3199 struct mlx5_ib_multiport_info *mpi)
3200 {
3201 u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
3202 int err;
3203
3204 lockdep_assert_held(&mlx5_ib_multiport_mutex);
3205
3206 spin_lock(&ibdev->port[port_num].mp.mpi_lock);
3207 if (ibdev->port[port_num].mp.mpi) {
3208 mlx5_ib_dbg(ibdev, "port %u already affiliated.\n",
3209 port_num + 1);
3210 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
3211 return false;
3212 }
3213
3214 ibdev->port[port_num].mp.mpi = mpi;
3215 mpi->ibdev = ibdev;
3216 mpi->mdev_events.notifier_call = NULL;
3217 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
3218
3219 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
3220 if (err)
3221 goto unbind;
3222
3223 err = mlx5_add_netdev_notifier(ibdev, port_num);
3224 if (err) {
3225 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
3226 port_num + 1);
3227 goto unbind;
3228 }
3229
3230 mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port;
3231 mlx5_notifier_register(mpi->mdev, &mpi->mdev_events);
3232
3233 mlx5_ib_init_cong_debugfs(ibdev, port_num);
3234
3235 return true;
3236
3237 unbind:
3238 mlx5_ib_unbind_slave_port(ibdev, mpi);
3239 return false;
3240 }
3241
mlx5_ib_init_multiport_master(struct mlx5_ib_dev * dev)3242 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
3243 {
3244 u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
3245 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
3246 port_num + 1);
3247 struct mlx5_ib_multiport_info *mpi;
3248 int err;
3249 u32 i;
3250
3251 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
3252 return 0;
3253
3254 err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
3255 &dev->sys_image_guid);
3256 if (err)
3257 return err;
3258
3259 err = mlx5_nic_vport_enable_roce(dev->mdev);
3260 if (err)
3261 return err;
3262
3263 mutex_lock(&mlx5_ib_multiport_mutex);
3264 for (i = 0; i < dev->num_ports; i++) {
3265 bool bound = false;
3266
3267 /* build a stub multiport info struct for the native port. */
3268 if (i == port_num) {
3269 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
3270 if (!mpi) {
3271 mutex_unlock(&mlx5_ib_multiport_mutex);
3272 mlx5_nic_vport_disable_roce(dev->mdev);
3273 return -ENOMEM;
3274 }
3275
3276 mpi->is_master = true;
3277 mpi->mdev = dev->mdev;
3278 mpi->sys_image_guid = dev->sys_image_guid;
3279 dev->port[i].mp.mpi = mpi;
3280 mpi->ibdev = dev;
3281 mpi = NULL;
3282 continue;
3283 }
3284
3285 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
3286 list) {
3287 if (dev->sys_image_guid == mpi->sys_image_guid &&
3288 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
3289 bound = mlx5_ib_bind_slave_port(dev, mpi);
3290 }
3291
3292 if (bound) {
3293 dev_dbg(mpi->mdev->device,
3294 "removing port from unaffiliated list.\n");
3295 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
3296 list_del(&mpi->list);
3297 break;
3298 }
3299 }
3300 if (!bound)
3301 mlx5_ib_dbg(dev, "no free port found for port %d\n",
3302 i + 1);
3303 }
3304
3305 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
3306 mutex_unlock(&mlx5_ib_multiport_mutex);
3307 return err;
3308 }
3309
mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev * dev)3310 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
3311 {
3312 u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
3313 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
3314 port_num + 1);
3315 u32 i;
3316
3317 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
3318 return;
3319
3320 mutex_lock(&mlx5_ib_multiport_mutex);
3321 for (i = 0; i < dev->num_ports; i++) {
3322 if (dev->port[i].mp.mpi) {
3323 /* Destroy the native port stub */
3324 if (i == port_num) {
3325 kfree(dev->port[i].mp.mpi);
3326 dev->port[i].mp.mpi = NULL;
3327 } else {
3328 mlx5_ib_dbg(dev, "unbinding port_num: %u\n",
3329 i + 1);
3330 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi);
3331 }
3332 }
3333 }
3334
3335 mlx5_ib_dbg(dev, "removing from devlist\n");
3336 list_del(&dev->ib_dev_list);
3337 mutex_unlock(&mlx5_ib_multiport_mutex);
3338
3339 mlx5_nic_vport_disable_roce(dev->mdev);
3340 }
3341
mmap_obj_cleanup(struct ib_uobject * uobject,enum rdma_remove_reason why,struct uverbs_attr_bundle * attrs)3342 static int mmap_obj_cleanup(struct ib_uobject *uobject,
3343 enum rdma_remove_reason why,
3344 struct uverbs_attr_bundle *attrs)
3345 {
3346 struct mlx5_user_mmap_entry *obj = uobject->object;
3347
3348 rdma_user_mmap_entry_remove(&obj->rdma_entry);
3349 return 0;
3350 }
3351
mlx5_rdma_user_mmap_entry_insert(struct mlx5_ib_ucontext * c,struct mlx5_user_mmap_entry * entry,size_t length)3352 static int mlx5_rdma_user_mmap_entry_insert(struct mlx5_ib_ucontext *c,
3353 struct mlx5_user_mmap_entry *entry,
3354 size_t length)
3355 {
3356 return rdma_user_mmap_entry_insert_range(
3357 &c->ibucontext, &entry->rdma_entry, length,
3358 (MLX5_IB_MMAP_OFFSET_START << 16),
3359 ((MLX5_IB_MMAP_OFFSET_END << 16) + (1UL << 16) - 1));
3360 }
3361
3362 static struct mlx5_user_mmap_entry *
alloc_var_entry(struct mlx5_ib_ucontext * c)3363 alloc_var_entry(struct mlx5_ib_ucontext *c)
3364 {
3365 struct mlx5_user_mmap_entry *entry;
3366 struct mlx5_var_table *var_table;
3367 u32 page_idx;
3368 int err;
3369
3370 var_table = &to_mdev(c->ibucontext.device)->var_table;
3371 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
3372 if (!entry)
3373 return ERR_PTR(-ENOMEM);
3374
3375 mutex_lock(&var_table->bitmap_lock);
3376 page_idx = find_first_zero_bit(var_table->bitmap,
3377 var_table->num_var_hw_entries);
3378 if (page_idx >= var_table->num_var_hw_entries) {
3379 err = -ENOSPC;
3380 mutex_unlock(&var_table->bitmap_lock);
3381 goto end;
3382 }
3383
3384 set_bit(page_idx, var_table->bitmap);
3385 mutex_unlock(&var_table->bitmap_lock);
3386
3387 entry->address = var_table->hw_start_addr +
3388 (page_idx * var_table->stride_size);
3389 entry->page_idx = page_idx;
3390 entry->mmap_flag = MLX5_IB_MMAP_TYPE_VAR;
3391
3392 err = mlx5_rdma_user_mmap_entry_insert(c, entry,
3393 var_table->stride_size);
3394 if (err)
3395 goto err_insert;
3396
3397 return entry;
3398
3399 err_insert:
3400 mutex_lock(&var_table->bitmap_lock);
3401 clear_bit(page_idx, var_table->bitmap);
3402 mutex_unlock(&var_table->bitmap_lock);
3403 end:
3404 kfree(entry);
3405 return ERR_PTR(err);
3406 }
3407
UVERBS_HANDLER(MLX5_IB_METHOD_VAR_OBJ_ALLOC)3408 static int UVERBS_HANDLER(MLX5_IB_METHOD_VAR_OBJ_ALLOC)(
3409 struct uverbs_attr_bundle *attrs)
3410 {
3411 struct ib_uobject *uobj = uverbs_attr_get_uobject(
3412 attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE);
3413 struct mlx5_ib_ucontext *c;
3414 struct mlx5_user_mmap_entry *entry;
3415 u64 mmap_offset;
3416 u32 length;
3417 int err;
3418
3419 c = to_mucontext(ib_uverbs_get_ucontext(attrs));
3420 if (IS_ERR(c))
3421 return PTR_ERR(c);
3422
3423 entry = alloc_var_entry(c);
3424 if (IS_ERR(entry))
3425 return PTR_ERR(entry);
3426
3427 mmap_offset = mlx5_entry_to_mmap_offset(entry);
3428 length = entry->rdma_entry.npages * PAGE_SIZE;
3429 uobj->object = entry;
3430 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE);
3431
3432 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET,
3433 &mmap_offset, sizeof(mmap_offset));
3434 if (err)
3435 return err;
3436
3437 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID,
3438 &entry->page_idx, sizeof(entry->page_idx));
3439 if (err)
3440 return err;
3441
3442 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH,
3443 &length, sizeof(length));
3444 return err;
3445 }
3446
3447 DECLARE_UVERBS_NAMED_METHOD(
3448 MLX5_IB_METHOD_VAR_OBJ_ALLOC,
3449 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE,
3450 MLX5_IB_OBJECT_VAR,
3451 UVERBS_ACCESS_NEW,
3452 UA_MANDATORY),
3453 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID,
3454 UVERBS_ATTR_TYPE(u32),
3455 UA_MANDATORY),
3456 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH,
3457 UVERBS_ATTR_TYPE(u32),
3458 UA_MANDATORY),
3459 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET,
3460 UVERBS_ATTR_TYPE(u64),
3461 UA_MANDATORY));
3462
3463 DECLARE_UVERBS_NAMED_METHOD_DESTROY(
3464 MLX5_IB_METHOD_VAR_OBJ_DESTROY,
3465 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_DESTROY_HANDLE,
3466 MLX5_IB_OBJECT_VAR,
3467 UVERBS_ACCESS_DESTROY,
3468 UA_MANDATORY));
3469
3470 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_VAR,
3471 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup),
3472 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_ALLOC),
3473 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_DESTROY));
3474
var_is_supported(struct ib_device * device)3475 static bool var_is_supported(struct ib_device *device)
3476 {
3477 struct mlx5_ib_dev *dev = to_mdev(device);
3478
3479 return (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
3480 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q);
3481 }
3482
3483 static struct mlx5_user_mmap_entry *
alloc_uar_entry(struct mlx5_ib_ucontext * c,enum mlx5_ib_uapi_uar_alloc_type alloc_type)3484 alloc_uar_entry(struct mlx5_ib_ucontext *c,
3485 enum mlx5_ib_uapi_uar_alloc_type alloc_type)
3486 {
3487 struct mlx5_user_mmap_entry *entry;
3488 struct mlx5_ib_dev *dev;
3489 u32 uar_index;
3490 int err;
3491
3492 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
3493 if (!entry)
3494 return ERR_PTR(-ENOMEM);
3495
3496 dev = to_mdev(c->ibucontext.device);
3497 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
3498 if (err)
3499 goto end;
3500
3501 entry->page_idx = uar_index;
3502 entry->address = uar_index2paddress(dev, uar_index);
3503 if (alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF)
3504 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_WC;
3505 else
3506 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_NC;
3507
3508 err = mlx5_rdma_user_mmap_entry_insert(c, entry, PAGE_SIZE);
3509 if (err)
3510 goto err_insert;
3511
3512 return entry;
3513
3514 err_insert:
3515 mlx5_cmd_free_uar(dev->mdev, uar_index);
3516 end:
3517 kfree(entry);
3518 return ERR_PTR(err);
3519 }
3520
UVERBS_HANDLER(MLX5_IB_METHOD_UAR_OBJ_ALLOC)3521 static int UVERBS_HANDLER(MLX5_IB_METHOD_UAR_OBJ_ALLOC)(
3522 struct uverbs_attr_bundle *attrs)
3523 {
3524 struct ib_uobject *uobj = uverbs_attr_get_uobject(
3525 attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE);
3526 enum mlx5_ib_uapi_uar_alloc_type alloc_type;
3527 struct mlx5_ib_ucontext *c;
3528 struct mlx5_user_mmap_entry *entry;
3529 u64 mmap_offset;
3530 u32 length;
3531 int err;
3532
3533 c = to_mucontext(ib_uverbs_get_ucontext(attrs));
3534 if (IS_ERR(c))
3535 return PTR_ERR(c);
3536
3537 err = uverbs_get_const(&alloc_type, attrs,
3538 MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE);
3539 if (err)
3540 return err;
3541
3542 if (alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF &&
3543 alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_NC)
3544 return -EOPNOTSUPP;
3545
3546 if (!to_mdev(c->ibucontext.device)->wc_support &&
3547 alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF)
3548 return -EOPNOTSUPP;
3549
3550 entry = alloc_uar_entry(c, alloc_type);
3551 if (IS_ERR(entry))
3552 return PTR_ERR(entry);
3553
3554 mmap_offset = mlx5_entry_to_mmap_offset(entry);
3555 length = entry->rdma_entry.npages * PAGE_SIZE;
3556 uobj->object = entry;
3557 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE);
3558
3559 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET,
3560 &mmap_offset, sizeof(mmap_offset));
3561 if (err)
3562 return err;
3563
3564 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID,
3565 &entry->page_idx, sizeof(entry->page_idx));
3566 if (err)
3567 return err;
3568
3569 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH,
3570 &length, sizeof(length));
3571 return err;
3572 }
3573
3574 DECLARE_UVERBS_NAMED_METHOD(
3575 MLX5_IB_METHOD_UAR_OBJ_ALLOC,
3576 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE,
3577 MLX5_IB_OBJECT_UAR,
3578 UVERBS_ACCESS_NEW,
3579 UA_MANDATORY),
3580 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE,
3581 enum mlx5_ib_uapi_uar_alloc_type,
3582 UA_MANDATORY),
3583 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID,
3584 UVERBS_ATTR_TYPE(u32),
3585 UA_MANDATORY),
3586 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH,
3587 UVERBS_ATTR_TYPE(u32),
3588 UA_MANDATORY),
3589 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET,
3590 UVERBS_ATTR_TYPE(u64),
3591 UA_MANDATORY));
3592
3593 DECLARE_UVERBS_NAMED_METHOD_DESTROY(
3594 MLX5_IB_METHOD_UAR_OBJ_DESTROY,
3595 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_DESTROY_HANDLE,
3596 MLX5_IB_OBJECT_UAR,
3597 UVERBS_ACCESS_DESTROY,
3598 UA_MANDATORY));
3599
3600 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_UAR,
3601 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup),
3602 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_ALLOC),
3603 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_DESTROY));
3604
3605 ADD_UVERBS_ATTRIBUTES_SIMPLE(
3606 mlx5_ib_flow_action,
3607 UVERBS_OBJECT_FLOW_ACTION,
3608 UVERBS_METHOD_FLOW_ACTION_ESP_CREATE,
3609 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
3610 enum mlx5_ib_uapi_flow_action_flags));
3611
3612 ADD_UVERBS_ATTRIBUTES_SIMPLE(
3613 mlx5_ib_query_context,
3614 UVERBS_OBJECT_DEVICE,
3615 UVERBS_METHOD_QUERY_CONTEXT,
3616 UVERBS_ATTR_PTR_OUT(
3617 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX,
3618 UVERBS_ATTR_STRUCT(struct mlx5_ib_alloc_ucontext_resp,
3619 dump_fill_mkey),
3620 UA_MANDATORY));
3621
3622 static const struct uapi_definition mlx5_ib_defs[] = {
3623 UAPI_DEF_CHAIN(mlx5_ib_devx_defs),
3624 UAPI_DEF_CHAIN(mlx5_ib_flow_defs),
3625 UAPI_DEF_CHAIN(mlx5_ib_qos_defs),
3626 UAPI_DEF_CHAIN(mlx5_ib_std_types_defs),
3627 UAPI_DEF_CHAIN(mlx5_ib_dm_defs),
3628
3629 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_FLOW_ACTION,
3630 &mlx5_ib_flow_action),
3631 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DEVICE, &mlx5_ib_query_context),
3632 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_VAR,
3633 UAPI_DEF_IS_OBJ_SUPPORTED(var_is_supported)),
3634 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_UAR),
3635 {}
3636 };
3637
mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev * dev)3638 static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
3639 {
3640 mlx5_ib_cleanup_multiport_master(dev);
3641 WARN_ON(!xa_empty(&dev->odp_mkeys));
3642 mutex_destroy(&dev->cap_mask_mutex);
3643 WARN_ON(!xa_empty(&dev->sig_mrs));
3644 WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES));
3645 }
3646
mlx5_ib_stage_init_init(struct mlx5_ib_dev * dev)3647 static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
3648 {
3649 struct mlx5_core_dev *mdev = dev->mdev;
3650 int err;
3651 int i;
3652
3653 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
3654 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
3655 dev->ib_dev.phys_port_cnt = dev->num_ports;
3656 dev->ib_dev.dev.parent = mdev->device;
3657 dev->ib_dev.lag_flags = RDMA_LAG_FLAGS_HASH_ALL_SLAVES;
3658
3659 for (i = 0; i < dev->num_ports; i++) {
3660 spin_lock_init(&dev->port[i].mp.mpi_lock);
3661 rwlock_init(&dev->port[i].roce.netdev_lock);
3662 dev->port[i].roce.dev = dev;
3663 dev->port[i].roce.native_port_num = i + 1;
3664 dev->port[i].roce.last_port_state = IB_PORT_DOWN;
3665 }
3666
3667 err = mlx5_ib_init_multiport_master(dev);
3668 if (err)
3669 return err;
3670
3671 err = set_has_smi_cap(dev);
3672 if (err)
3673 goto err_mp;
3674
3675 err = mlx5_query_max_pkeys(&dev->ib_dev, &dev->pkey_table_len);
3676 if (err)
3677 goto err_mp;
3678
3679 if (mlx5_use_mad_ifc(dev))
3680 get_ext_port_caps(dev);
3681
3682 dev->ib_dev.num_comp_vectors = mlx5_comp_vectors_count(mdev);
3683
3684 mutex_init(&dev->cap_mask_mutex);
3685 INIT_LIST_HEAD(&dev->qp_list);
3686 spin_lock_init(&dev->reset_flow_resource_lock);
3687 xa_init(&dev->odp_mkeys);
3688 xa_init(&dev->sig_mrs);
3689 atomic_set(&dev->mkey_var, 0);
3690
3691 spin_lock_init(&dev->dm.lock);
3692 dev->dm.dev = mdev;
3693 return 0;
3694
3695 err_mp:
3696 mlx5_ib_cleanup_multiport_master(dev);
3697 return err;
3698 }
3699
mlx5_ib_enable_driver(struct ib_device * dev)3700 static int mlx5_ib_enable_driver(struct ib_device *dev)
3701 {
3702 struct mlx5_ib_dev *mdev = to_mdev(dev);
3703 int ret;
3704
3705 ret = mlx5_ib_test_wc(mdev);
3706 mlx5_ib_dbg(mdev, "Write-Combining %s",
3707 mdev->wc_support ? "supported" : "not supported");
3708
3709 return ret;
3710 }
3711
3712 static const struct ib_device_ops mlx5_ib_dev_ops = {
3713 .owner = THIS_MODULE,
3714 .driver_id = RDMA_DRIVER_MLX5,
3715 .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION,
3716
3717 .add_gid = mlx5_ib_add_gid,
3718 .alloc_mr = mlx5_ib_alloc_mr,
3719 .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity,
3720 .alloc_pd = mlx5_ib_alloc_pd,
3721 .alloc_ucontext = mlx5_ib_alloc_ucontext,
3722 .attach_mcast = mlx5_ib_mcg_attach,
3723 .check_mr_status = mlx5_ib_check_mr_status,
3724 .create_ah = mlx5_ib_create_ah,
3725 .create_cq = mlx5_ib_create_cq,
3726 .create_qp = mlx5_ib_create_qp,
3727 .create_srq = mlx5_ib_create_srq,
3728 .create_user_ah = mlx5_ib_create_ah,
3729 .dealloc_pd = mlx5_ib_dealloc_pd,
3730 .dealloc_ucontext = mlx5_ib_dealloc_ucontext,
3731 .del_gid = mlx5_ib_del_gid,
3732 .dereg_mr = mlx5_ib_dereg_mr,
3733 .destroy_ah = mlx5_ib_destroy_ah,
3734 .destroy_cq = mlx5_ib_destroy_cq,
3735 .destroy_qp = mlx5_ib_destroy_qp,
3736 .destroy_srq = mlx5_ib_destroy_srq,
3737 .detach_mcast = mlx5_ib_mcg_detach,
3738 .disassociate_ucontext = mlx5_ib_disassociate_ucontext,
3739 .drain_rq = mlx5_ib_drain_rq,
3740 .drain_sq = mlx5_ib_drain_sq,
3741 .enable_driver = mlx5_ib_enable_driver,
3742 .get_dev_fw_str = get_dev_fw_str,
3743 .get_dma_mr = mlx5_ib_get_dma_mr,
3744 .get_link_layer = mlx5_ib_port_link_layer,
3745 .map_mr_sg = mlx5_ib_map_mr_sg,
3746 .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi,
3747 .mmap = mlx5_ib_mmap,
3748 .mmap_free = mlx5_ib_mmap_free,
3749 .modify_cq = mlx5_ib_modify_cq,
3750 .modify_device = mlx5_ib_modify_device,
3751 .modify_port = mlx5_ib_modify_port,
3752 .modify_qp = mlx5_ib_modify_qp,
3753 .modify_srq = mlx5_ib_modify_srq,
3754 .poll_cq = mlx5_ib_poll_cq,
3755 .post_recv = mlx5_ib_post_recv_nodrain,
3756 .post_send = mlx5_ib_post_send_nodrain,
3757 .post_srq_recv = mlx5_ib_post_srq_recv,
3758 .process_mad = mlx5_ib_process_mad,
3759 .query_ah = mlx5_ib_query_ah,
3760 .query_device = mlx5_ib_query_device,
3761 .query_gid = mlx5_ib_query_gid,
3762 .query_pkey = mlx5_ib_query_pkey,
3763 .query_qp = mlx5_ib_query_qp,
3764 .query_srq = mlx5_ib_query_srq,
3765 .query_ucontext = mlx5_ib_query_ucontext,
3766 .reg_user_mr = mlx5_ib_reg_user_mr,
3767 .reg_user_mr_dmabuf = mlx5_ib_reg_user_mr_dmabuf,
3768 .req_notify_cq = mlx5_ib_arm_cq,
3769 .rereg_user_mr = mlx5_ib_rereg_user_mr,
3770 .resize_cq = mlx5_ib_resize_cq,
3771
3772 INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah),
3773 INIT_RDMA_OBJ_SIZE(ib_counters, mlx5_ib_mcounters, ibcntrs),
3774 INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq),
3775 INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd),
3776 INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq),
3777 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext),
3778 };
3779
3780 static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = {
3781 .rdma_netdev_get_params = mlx5_ib_rn_get_params,
3782 };
3783
3784 static const struct ib_device_ops mlx5_ib_dev_sriov_ops = {
3785 .get_vf_config = mlx5_ib_get_vf_config,
3786 .get_vf_guid = mlx5_ib_get_vf_guid,
3787 .get_vf_stats = mlx5_ib_get_vf_stats,
3788 .set_vf_guid = mlx5_ib_set_vf_guid,
3789 .set_vf_link_state = mlx5_ib_set_vf_link_state,
3790 };
3791
3792 static const struct ib_device_ops mlx5_ib_dev_mw_ops = {
3793 .alloc_mw = mlx5_ib_alloc_mw,
3794 .dealloc_mw = mlx5_ib_dealloc_mw,
3795
3796 INIT_RDMA_OBJ_SIZE(ib_mw, mlx5_ib_mw, ibmw),
3797 };
3798
3799 static const struct ib_device_ops mlx5_ib_dev_xrc_ops = {
3800 .alloc_xrcd = mlx5_ib_alloc_xrcd,
3801 .dealloc_xrcd = mlx5_ib_dealloc_xrcd,
3802
3803 INIT_RDMA_OBJ_SIZE(ib_xrcd, mlx5_ib_xrcd, ibxrcd),
3804 };
3805
mlx5_ib_init_var_table(struct mlx5_ib_dev * dev)3806 static int mlx5_ib_init_var_table(struct mlx5_ib_dev *dev)
3807 {
3808 struct mlx5_core_dev *mdev = dev->mdev;
3809 struct mlx5_var_table *var_table = &dev->var_table;
3810 u8 log_doorbell_bar_size;
3811 u8 log_doorbell_stride;
3812 u64 bar_size;
3813
3814 log_doorbell_bar_size = MLX5_CAP_DEV_VDPA_EMULATION(mdev,
3815 log_doorbell_bar_size);
3816 log_doorbell_stride = MLX5_CAP_DEV_VDPA_EMULATION(mdev,
3817 log_doorbell_stride);
3818 var_table->hw_start_addr = dev->mdev->bar_addr +
3819 MLX5_CAP64_DEV_VDPA_EMULATION(mdev,
3820 doorbell_bar_offset);
3821 bar_size = (1ULL << log_doorbell_bar_size) * 4096;
3822 var_table->stride_size = 1ULL << log_doorbell_stride;
3823 var_table->num_var_hw_entries = div_u64(bar_size,
3824 var_table->stride_size);
3825 mutex_init(&var_table->bitmap_lock);
3826 var_table->bitmap = bitmap_zalloc(var_table->num_var_hw_entries,
3827 GFP_KERNEL);
3828 return (var_table->bitmap) ? 0 : -ENOMEM;
3829 }
3830
mlx5_ib_stage_caps_cleanup(struct mlx5_ib_dev * dev)3831 static void mlx5_ib_stage_caps_cleanup(struct mlx5_ib_dev *dev)
3832 {
3833 bitmap_free(dev->var_table.bitmap);
3834 }
3835
mlx5_ib_stage_caps_init(struct mlx5_ib_dev * dev)3836 static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
3837 {
3838 struct mlx5_core_dev *mdev = dev->mdev;
3839 int err;
3840
3841 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
3842 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB))
3843 ib_set_device_ops(&dev->ib_dev,
3844 &mlx5_ib_dev_ipoib_enhanced_ops);
3845
3846 if (mlx5_core_is_pf(mdev))
3847 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops);
3848
3849 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
3850
3851 if (MLX5_CAP_GEN(mdev, imaicl))
3852 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops);
3853
3854 if (MLX5_CAP_GEN(mdev, xrc))
3855 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops);
3856
3857 if (MLX5_CAP_DEV_MEM(mdev, memic) ||
3858 MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
3859 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM)
3860 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops);
3861
3862 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops);
3863
3864 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS))
3865 dev->ib_dev.driver_def = mlx5_ib_defs;
3866
3867 err = init_node_data(dev);
3868 if (err)
3869 return err;
3870
3871 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
3872 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
3873 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
3874 mutex_init(&dev->lb.mutex);
3875
3876 if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
3877 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) {
3878 err = mlx5_ib_init_var_table(dev);
3879 if (err)
3880 return err;
3881 }
3882
3883 dev->ib_dev.use_cq_dim = true;
3884
3885 return 0;
3886 }
3887
3888 static const struct ib_device_ops mlx5_ib_dev_port_ops = {
3889 .get_port_immutable = mlx5_port_immutable,
3890 .query_port = mlx5_ib_query_port,
3891 };
3892
mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev * dev)3893 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
3894 {
3895 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops);
3896 return 0;
3897 }
3898
3899 static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = {
3900 .get_port_immutable = mlx5_port_rep_immutable,
3901 .query_port = mlx5_ib_rep_query_port,
3902 .query_pkey = mlx5_ib_rep_query_pkey,
3903 };
3904
mlx5_ib_stage_raw_eth_non_default_cb(struct mlx5_ib_dev * dev)3905 static int mlx5_ib_stage_raw_eth_non_default_cb(struct mlx5_ib_dev *dev)
3906 {
3907 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops);
3908 return 0;
3909 }
3910
3911 static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = {
3912 .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table,
3913 .create_wq = mlx5_ib_create_wq,
3914 .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table,
3915 .destroy_wq = mlx5_ib_destroy_wq,
3916 .get_netdev = mlx5_ib_get_netdev,
3917 .modify_wq = mlx5_ib_modify_wq,
3918
3919 INIT_RDMA_OBJ_SIZE(ib_rwq_ind_table, mlx5_ib_rwq_ind_table,
3920 ib_rwq_ind_tbl),
3921 };
3922
mlx5_ib_roce_init(struct mlx5_ib_dev * dev)3923 static int mlx5_ib_roce_init(struct mlx5_ib_dev *dev)
3924 {
3925 struct mlx5_core_dev *mdev = dev->mdev;
3926 enum rdma_link_layer ll;
3927 int port_type_cap;
3928 u32 port_num = 0;
3929 int err;
3930
3931 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
3932 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
3933
3934 if (ll == IB_LINK_LAYER_ETHERNET) {
3935 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops);
3936
3937 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
3938
3939 /* Register only for native ports */
3940 err = mlx5_add_netdev_notifier(dev, port_num);
3941 if (err || dev->is_rep || !mlx5_is_roce_init_enabled(mdev))
3942 /*
3943 * We don't enable ETH interface for
3944 * 1. IB representors
3945 * 2. User disabled ROCE through devlink interface
3946 */
3947 return err;
3948
3949 err = mlx5_enable_eth(dev);
3950 if (err)
3951 goto cleanup;
3952 }
3953
3954 return 0;
3955 cleanup:
3956 mlx5_remove_netdev_notifier(dev, port_num);
3957 return err;
3958 }
3959
mlx5_ib_roce_cleanup(struct mlx5_ib_dev * dev)3960 static void mlx5_ib_roce_cleanup(struct mlx5_ib_dev *dev)
3961 {
3962 struct mlx5_core_dev *mdev = dev->mdev;
3963 enum rdma_link_layer ll;
3964 int port_type_cap;
3965 u32 port_num;
3966
3967 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
3968 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
3969
3970 if (ll == IB_LINK_LAYER_ETHERNET) {
3971 if (!dev->is_rep)
3972 mlx5_disable_eth(dev);
3973
3974 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
3975 mlx5_remove_netdev_notifier(dev, port_num);
3976 }
3977 }
3978
mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev * dev)3979 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
3980 {
3981 mlx5_ib_init_cong_debugfs(dev,
3982 mlx5_core_native_port_num(dev->mdev) - 1);
3983 return 0;
3984 }
3985
mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev * dev)3986 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
3987 {
3988 mlx5_ib_cleanup_cong_debugfs(dev,
3989 mlx5_core_native_port_num(dev->mdev) - 1);
3990 }
3991
mlx5_ib_stage_uar_init(struct mlx5_ib_dev * dev)3992 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
3993 {
3994 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
3995 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar);
3996 }
3997
mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev * dev)3998 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
3999 {
4000 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
4001 }
4002
mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev * dev)4003 static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
4004 {
4005 int err;
4006
4007 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
4008 if (err)
4009 return err;
4010
4011 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
4012 if (err)
4013 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
4014
4015 return err;
4016 }
4017
mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev * dev)4018 static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
4019 {
4020 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
4021 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
4022 }
4023
mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev * dev)4024 static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
4025 {
4026 const char *name;
4027
4028 rdma_set_device_sysfs_group(&dev->ib_dev, &mlx5_attr_group);
4029 if (!mlx5_lag_is_roce(dev->mdev))
4030 name = "mlx5_%d";
4031 else
4032 name = "mlx5_bond_%d";
4033 return ib_register_device(&dev->ib_dev, name, &dev->mdev->pdev->dev);
4034 }
4035
mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev * dev)4036 static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
4037 {
4038 int err;
4039
4040 err = mlx5_mr_cache_cleanup(dev);
4041 if (err)
4042 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
4043
4044 if (dev->umrc.qp)
4045 mlx5_ib_destroy_qp(dev->umrc.qp, NULL);
4046 if (dev->umrc.cq)
4047 ib_free_cq(dev->umrc.cq);
4048 if (dev->umrc.pd)
4049 ib_dealloc_pd(dev->umrc.pd);
4050 }
4051
mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev * dev)4052 static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
4053 {
4054 ib_unregister_device(&dev->ib_dev);
4055 }
4056
4057 enum {
4058 MAX_UMR_WR = 128,
4059 };
4060
mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev * dev)4061 static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
4062 {
4063 struct ib_qp_init_attr *init_attr = NULL;
4064 struct ib_qp_attr *attr = NULL;
4065 struct ib_pd *pd;
4066 struct ib_cq *cq;
4067 struct ib_qp *qp;
4068 int ret;
4069
4070 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
4071 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
4072 if (!attr || !init_attr) {
4073 ret = -ENOMEM;
4074 goto error_0;
4075 }
4076
4077 pd = ib_alloc_pd(&dev->ib_dev, 0);
4078 if (IS_ERR(pd)) {
4079 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
4080 ret = PTR_ERR(pd);
4081 goto error_0;
4082 }
4083
4084 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
4085 if (IS_ERR(cq)) {
4086 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
4087 ret = PTR_ERR(cq);
4088 goto error_2;
4089 }
4090
4091 init_attr->send_cq = cq;
4092 init_attr->recv_cq = cq;
4093 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
4094 init_attr->cap.max_send_wr = MAX_UMR_WR;
4095 init_attr->cap.max_send_sge = 1;
4096 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
4097 init_attr->port_num = 1;
4098 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
4099 if (IS_ERR(qp)) {
4100 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
4101 ret = PTR_ERR(qp);
4102 goto error_3;
4103 }
4104 qp->device = &dev->ib_dev;
4105 qp->real_qp = qp;
4106 qp->uobject = NULL;
4107 qp->qp_type = MLX5_IB_QPT_REG_UMR;
4108 qp->send_cq = init_attr->send_cq;
4109 qp->recv_cq = init_attr->recv_cq;
4110
4111 attr->qp_state = IB_QPS_INIT;
4112 attr->port_num = 1;
4113 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
4114 IB_QP_PORT, NULL);
4115 if (ret) {
4116 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
4117 goto error_4;
4118 }
4119
4120 memset(attr, 0, sizeof(*attr));
4121 attr->qp_state = IB_QPS_RTR;
4122 attr->path_mtu = IB_MTU_256;
4123
4124 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4125 if (ret) {
4126 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
4127 goto error_4;
4128 }
4129
4130 memset(attr, 0, sizeof(*attr));
4131 attr->qp_state = IB_QPS_RTS;
4132 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4133 if (ret) {
4134 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
4135 goto error_4;
4136 }
4137
4138 dev->umrc.qp = qp;
4139 dev->umrc.cq = cq;
4140 dev->umrc.pd = pd;
4141
4142 sema_init(&dev->umrc.sem, MAX_UMR_WR);
4143 ret = mlx5_mr_cache_init(dev);
4144 if (ret) {
4145 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
4146 goto error_4;
4147 }
4148
4149 kfree(attr);
4150 kfree(init_attr);
4151
4152 return 0;
4153
4154 error_4:
4155 mlx5_ib_destroy_qp(qp, NULL);
4156 dev->umrc.qp = NULL;
4157
4158 error_3:
4159 ib_free_cq(cq);
4160 dev->umrc.cq = NULL;
4161
4162 error_2:
4163 ib_dealloc_pd(pd);
4164 dev->umrc.pd = NULL;
4165
4166 error_0:
4167 kfree(attr);
4168 kfree(init_attr);
4169 return ret;
4170 }
4171
mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev * dev)4172 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
4173 {
4174 struct dentry *root;
4175
4176 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4177 return 0;
4178
4179 mutex_init(&dev->delay_drop.lock);
4180 dev->delay_drop.dev = dev;
4181 dev->delay_drop.activate = false;
4182 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
4183 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
4184 atomic_set(&dev->delay_drop.rqs_cnt, 0);
4185 atomic_set(&dev->delay_drop.events_cnt, 0);
4186
4187 if (!mlx5_debugfs_root)
4188 return 0;
4189
4190 root = debugfs_create_dir("delay_drop", dev->mdev->priv.dbg_root);
4191 dev->delay_drop.dir_debugfs = root;
4192
4193 debugfs_create_atomic_t("num_timeout_events", 0400, root,
4194 &dev->delay_drop.events_cnt);
4195 debugfs_create_atomic_t("num_rqs", 0400, root,
4196 &dev->delay_drop.rqs_cnt);
4197 debugfs_create_file("timeout", 0600, root, &dev->delay_drop,
4198 &fops_delay_drop_timeout);
4199 return 0;
4200 }
4201
mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev * dev)4202 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
4203 {
4204 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4205 return;
4206
4207 cancel_work_sync(&dev->delay_drop.delay_drop_work);
4208 if (!dev->delay_drop.dir_debugfs)
4209 return;
4210
4211 debugfs_remove_recursive(dev->delay_drop.dir_debugfs);
4212 dev->delay_drop.dir_debugfs = NULL;
4213 }
4214
mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev * dev)4215 static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev)
4216 {
4217 dev->mdev_events.notifier_call = mlx5_ib_event;
4218 mlx5_notifier_register(dev->mdev, &dev->mdev_events);
4219 return 0;
4220 }
4221
mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev * dev)4222 static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev)
4223 {
4224 mlx5_notifier_unregister(dev->mdev, &dev->mdev_events);
4225 }
4226
__mlx5_ib_remove(struct mlx5_ib_dev * dev,const struct mlx5_ib_profile * profile,int stage)4227 void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
4228 const struct mlx5_ib_profile *profile,
4229 int stage)
4230 {
4231 dev->ib_active = false;
4232
4233 /* Number of stages to cleanup */
4234 while (stage) {
4235 stage--;
4236 if (profile->stage[stage].cleanup)
4237 profile->stage[stage].cleanup(dev);
4238 }
4239
4240 kfree(dev->port);
4241 ib_dealloc_device(&dev->ib_dev);
4242 }
4243
__mlx5_ib_add(struct mlx5_ib_dev * dev,const struct mlx5_ib_profile * profile)4244 int __mlx5_ib_add(struct mlx5_ib_dev *dev,
4245 const struct mlx5_ib_profile *profile)
4246 {
4247 int err;
4248 int i;
4249
4250 dev->profile = profile;
4251
4252 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
4253 if (profile->stage[i].init) {
4254 err = profile->stage[i].init(dev);
4255 if (err)
4256 goto err_out;
4257 }
4258 }
4259
4260 dev->ib_active = true;
4261 return 0;
4262
4263 err_out:
4264 /* Clean up stages which were initialized */
4265 while (i) {
4266 i--;
4267 if (profile->stage[i].cleanup)
4268 profile->stage[i].cleanup(dev);
4269 }
4270 return -ENOMEM;
4271 }
4272
4273 static const struct mlx5_ib_profile pf_profile = {
4274 STAGE_CREATE(MLX5_IB_STAGE_INIT,
4275 mlx5_ib_stage_init_init,
4276 mlx5_ib_stage_init_cleanup),
4277 STAGE_CREATE(MLX5_IB_STAGE_FS,
4278 mlx5_ib_fs_init,
4279 mlx5_ib_fs_cleanup),
4280 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
4281 mlx5_ib_stage_caps_init,
4282 mlx5_ib_stage_caps_cleanup),
4283 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
4284 mlx5_ib_stage_non_default_cb,
4285 NULL),
4286 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
4287 mlx5_ib_roce_init,
4288 mlx5_ib_roce_cleanup),
4289 STAGE_CREATE(MLX5_IB_STAGE_QP,
4290 mlx5_init_qp_table,
4291 mlx5_cleanup_qp_table),
4292 STAGE_CREATE(MLX5_IB_STAGE_SRQ,
4293 mlx5_init_srq_table,
4294 mlx5_cleanup_srq_table),
4295 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
4296 mlx5_ib_dev_res_init,
4297 mlx5_ib_dev_res_cleanup),
4298 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
4299 mlx5_ib_stage_dev_notifier_init,
4300 mlx5_ib_stage_dev_notifier_cleanup),
4301 STAGE_CREATE(MLX5_IB_STAGE_ODP,
4302 mlx5_ib_odp_init_one,
4303 mlx5_ib_odp_cleanup_one),
4304 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
4305 mlx5_ib_counters_init,
4306 mlx5_ib_counters_cleanup),
4307 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
4308 mlx5_ib_stage_cong_debugfs_init,
4309 mlx5_ib_stage_cong_debugfs_cleanup),
4310 STAGE_CREATE(MLX5_IB_STAGE_UAR,
4311 mlx5_ib_stage_uar_init,
4312 mlx5_ib_stage_uar_cleanup),
4313 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
4314 mlx5_ib_stage_bfrag_init,
4315 mlx5_ib_stage_bfrag_cleanup),
4316 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
4317 NULL,
4318 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
4319 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
4320 mlx5_ib_devx_init,
4321 mlx5_ib_devx_cleanup),
4322 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
4323 mlx5_ib_stage_ib_reg_init,
4324 mlx5_ib_stage_ib_reg_cleanup),
4325 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
4326 mlx5_ib_stage_post_ib_reg_umr_init,
4327 NULL),
4328 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
4329 mlx5_ib_stage_delay_drop_init,
4330 mlx5_ib_stage_delay_drop_cleanup),
4331 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK,
4332 mlx5_ib_restrack_init,
4333 NULL),
4334 };
4335
4336 const struct mlx5_ib_profile raw_eth_profile = {
4337 STAGE_CREATE(MLX5_IB_STAGE_INIT,
4338 mlx5_ib_stage_init_init,
4339 mlx5_ib_stage_init_cleanup),
4340 STAGE_CREATE(MLX5_IB_STAGE_FS,
4341 mlx5_ib_fs_init,
4342 mlx5_ib_fs_cleanup),
4343 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
4344 mlx5_ib_stage_caps_init,
4345 mlx5_ib_stage_caps_cleanup),
4346 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
4347 mlx5_ib_stage_raw_eth_non_default_cb,
4348 NULL),
4349 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
4350 mlx5_ib_roce_init,
4351 mlx5_ib_roce_cleanup),
4352 STAGE_CREATE(MLX5_IB_STAGE_QP,
4353 mlx5_init_qp_table,
4354 mlx5_cleanup_qp_table),
4355 STAGE_CREATE(MLX5_IB_STAGE_SRQ,
4356 mlx5_init_srq_table,
4357 mlx5_cleanup_srq_table),
4358 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
4359 mlx5_ib_dev_res_init,
4360 mlx5_ib_dev_res_cleanup),
4361 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
4362 mlx5_ib_stage_dev_notifier_init,
4363 mlx5_ib_stage_dev_notifier_cleanup),
4364 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
4365 mlx5_ib_counters_init,
4366 mlx5_ib_counters_cleanup),
4367 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
4368 mlx5_ib_stage_cong_debugfs_init,
4369 mlx5_ib_stage_cong_debugfs_cleanup),
4370 STAGE_CREATE(MLX5_IB_STAGE_UAR,
4371 mlx5_ib_stage_uar_init,
4372 mlx5_ib_stage_uar_cleanup),
4373 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
4374 mlx5_ib_stage_bfrag_init,
4375 mlx5_ib_stage_bfrag_cleanup),
4376 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
4377 NULL,
4378 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
4379 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
4380 mlx5_ib_devx_init,
4381 mlx5_ib_devx_cleanup),
4382 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
4383 mlx5_ib_stage_ib_reg_init,
4384 mlx5_ib_stage_ib_reg_cleanup),
4385 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
4386 mlx5_ib_stage_post_ib_reg_umr_init,
4387 NULL),
4388 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK,
4389 mlx5_ib_restrack_init,
4390 NULL),
4391 };
4392
mlx5r_mp_probe(struct auxiliary_device * adev,const struct auxiliary_device_id * id)4393 static int mlx5r_mp_probe(struct auxiliary_device *adev,
4394 const struct auxiliary_device_id *id)
4395 {
4396 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev);
4397 struct mlx5_core_dev *mdev = idev->mdev;
4398 struct mlx5_ib_multiport_info *mpi;
4399 struct mlx5_ib_dev *dev;
4400 bool bound = false;
4401 int err;
4402
4403 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
4404 if (!mpi)
4405 return -ENOMEM;
4406
4407 mpi->mdev = mdev;
4408 err = mlx5_query_nic_vport_system_image_guid(mdev,
4409 &mpi->sys_image_guid);
4410 if (err) {
4411 kfree(mpi);
4412 return err;
4413 }
4414
4415 mutex_lock(&mlx5_ib_multiport_mutex);
4416 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
4417 if (dev->sys_image_guid == mpi->sys_image_guid)
4418 bound = mlx5_ib_bind_slave_port(dev, mpi);
4419
4420 if (bound) {
4421 rdma_roce_rescan_device(&dev->ib_dev);
4422 break;
4423 }
4424 }
4425
4426 if (!bound) {
4427 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
4428 dev_dbg(mdev->device,
4429 "no suitable IB device found to bind to, added to unaffiliated list.\n");
4430 }
4431 mutex_unlock(&mlx5_ib_multiport_mutex);
4432
4433 dev_set_drvdata(&adev->dev, mpi);
4434 return 0;
4435 }
4436
mlx5r_mp_remove(struct auxiliary_device * adev)4437 static void mlx5r_mp_remove(struct auxiliary_device *adev)
4438 {
4439 struct mlx5_ib_multiport_info *mpi;
4440
4441 mpi = dev_get_drvdata(&adev->dev);
4442 mutex_lock(&mlx5_ib_multiport_mutex);
4443 if (mpi->ibdev)
4444 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
4445 list_del(&mpi->list);
4446 mutex_unlock(&mlx5_ib_multiport_mutex);
4447 kfree(mpi);
4448 }
4449
mlx5r_probe(struct auxiliary_device * adev,const struct auxiliary_device_id * id)4450 static int mlx5r_probe(struct auxiliary_device *adev,
4451 const struct auxiliary_device_id *id)
4452 {
4453 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev);
4454 struct mlx5_core_dev *mdev = idev->mdev;
4455 const struct mlx5_ib_profile *profile;
4456 int port_type_cap, num_ports, ret;
4457 enum rdma_link_layer ll;
4458 struct mlx5_ib_dev *dev;
4459
4460 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
4461 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
4462
4463 num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
4464 MLX5_CAP_GEN(mdev, num_vhca_ports));
4465 dev = ib_alloc_device(mlx5_ib_dev, ib_dev);
4466 if (!dev)
4467 return -ENOMEM;
4468 dev->port = kcalloc(num_ports, sizeof(*dev->port),
4469 GFP_KERNEL);
4470 if (!dev->port) {
4471 ib_dealloc_device(&dev->ib_dev);
4472 return -ENOMEM;
4473 }
4474
4475 dev->mdev = mdev;
4476 dev->num_ports = num_ports;
4477
4478 if (ll == IB_LINK_LAYER_ETHERNET && !mlx5_is_roce_init_enabled(mdev))
4479 profile = &raw_eth_profile;
4480 else
4481 profile = &pf_profile;
4482
4483 ret = __mlx5_ib_add(dev, profile);
4484 if (ret) {
4485 kfree(dev->port);
4486 ib_dealloc_device(&dev->ib_dev);
4487 return ret;
4488 }
4489
4490 dev_set_drvdata(&adev->dev, dev);
4491 return 0;
4492 }
4493
mlx5r_remove(struct auxiliary_device * adev)4494 static void mlx5r_remove(struct auxiliary_device *adev)
4495 {
4496 struct mlx5_ib_dev *dev;
4497
4498 dev = dev_get_drvdata(&adev->dev);
4499 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
4500 }
4501
4502 static const struct auxiliary_device_id mlx5r_mp_id_table[] = {
4503 { .name = MLX5_ADEV_NAME ".multiport", },
4504 {},
4505 };
4506
4507 static const struct auxiliary_device_id mlx5r_id_table[] = {
4508 { .name = MLX5_ADEV_NAME ".rdma", },
4509 {},
4510 };
4511
4512 MODULE_DEVICE_TABLE(auxiliary, mlx5r_mp_id_table);
4513 MODULE_DEVICE_TABLE(auxiliary, mlx5r_id_table);
4514
4515 static struct auxiliary_driver mlx5r_mp_driver = {
4516 .name = "multiport",
4517 .probe = mlx5r_mp_probe,
4518 .remove = mlx5r_mp_remove,
4519 .id_table = mlx5r_mp_id_table,
4520 };
4521
4522 static struct auxiliary_driver mlx5r_driver = {
4523 .name = "rdma",
4524 .probe = mlx5r_probe,
4525 .remove = mlx5r_remove,
4526 .id_table = mlx5r_id_table,
4527 };
4528
mlx5_ib_init(void)4529 static int __init mlx5_ib_init(void)
4530 {
4531 int ret;
4532
4533 xlt_emergency_page = (void *)__get_free_page(GFP_KERNEL);
4534 if (!xlt_emergency_page)
4535 return -ENOMEM;
4536
4537 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
4538 if (!mlx5_ib_event_wq) {
4539 free_page((unsigned long)xlt_emergency_page);
4540 return -ENOMEM;
4541 }
4542
4543 mlx5_ib_odp_init();
4544 ret = mlx5r_rep_init();
4545 if (ret)
4546 goto rep_err;
4547 ret = auxiliary_driver_register(&mlx5r_mp_driver);
4548 if (ret)
4549 goto mp_err;
4550 ret = auxiliary_driver_register(&mlx5r_driver);
4551 if (ret)
4552 goto drv_err;
4553 return 0;
4554
4555 drv_err:
4556 auxiliary_driver_unregister(&mlx5r_mp_driver);
4557 mp_err:
4558 mlx5r_rep_cleanup();
4559 rep_err:
4560 destroy_workqueue(mlx5_ib_event_wq);
4561 free_page((unsigned long)xlt_emergency_page);
4562 return ret;
4563 }
4564
mlx5_ib_cleanup(void)4565 static void __exit mlx5_ib_cleanup(void)
4566 {
4567 auxiliary_driver_unregister(&mlx5r_driver);
4568 auxiliary_driver_unregister(&mlx5r_mp_driver);
4569 mlx5r_rep_cleanup();
4570
4571 destroy_workqueue(mlx5_ib_event_wq);
4572 free_page((unsigned long)xlt_emergency_page);
4573 }
4574
4575 module_init(mlx5_ib_init);
4576 module_exit(mlx5_ib_cleanup);
4577