1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * omap iommu: main structures
4  *
5  * Copyright (C) 2008-2009 Nokia Corporation
6  *
7  * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
8  */
9 
10 #ifndef _OMAP_IOMMU_H
11 #define _OMAP_IOMMU_H
12 
13 #include <linux/bitops.h>
14 #include <linux/iommu.h>
15 
16 #define for_each_iotlb_cr(obj, n, __i, cr)				\
17 	for (__i = 0;							\
18 	     (__i < (n)) && (cr = __iotlb_read_cr((obj), __i), true);	\
19 	     __i++)
20 
21 struct iotlb_entry {
22 	u32 da;
23 	u32 pa;
24 	u32 pgsz, prsvd, valid;
25 	u32 endian, elsz, mixed;
26 };
27 
28 /**
29  * struct omap_iommu_device - omap iommu device data
30  * @pgtable:	page table used by an omap iommu attached to a domain
31  * @iommu_dev:	pointer to store an omap iommu instance attached to a domain
32  */
33 struct omap_iommu_device {
34 	u32 *pgtable;
35 	struct omap_iommu *iommu_dev;
36 };
37 
38 /**
39  * struct omap_iommu_domain - omap iommu domain
40  * @num_iommus: number of iommus in this domain
41  * @iommus:	omap iommu device data for all iommus in this domain
42  * @dev:	Device using this domain.
43  * @lock:	domain lock, should be taken when attaching/detaching
44  * @domain:	generic domain handle used by iommu core code
45  */
46 struct omap_iommu_domain {
47 	u32 num_iommus;
48 	struct omap_iommu_device *iommus;
49 	struct device *dev;
50 	spinlock_t lock;
51 	struct iommu_domain domain;
52 };
53 
54 struct omap_iommu {
55 	const char	*name;
56 	void __iomem	*regbase;
57 	struct regmap	*syscfg;
58 	struct device	*dev;
59 	struct iommu_domain *domain;
60 	struct dentry	*debug_dir;
61 
62 	spinlock_t	iommu_lock;	/* global for this whole object */
63 
64 	/*
65 	 * We don't change iopgd for a situation like pgd for a task,
66 	 * but share it globally for each iommu.
67 	 */
68 	u32		*iopgd;
69 	spinlock_t	page_table_lock; /* protect iopgd */
70 	dma_addr_t	pd_dma;
71 
72 	int		nr_tlb_entries;
73 
74 	void *ctx; /* iommu context: registres saved area */
75 
76 	struct cr_regs *cr_ctx;
77 	u32 num_cr_ctx;
78 
79 	int has_bus_err_back;
80 	u32 id;
81 
82 	struct iommu_device iommu;
83 	struct iommu_group *group;
84 
85 	u8 pwrst;
86 };
87 
88 /**
89  * struct omap_iommu_arch_data - omap iommu private data
90  * @iommu_dev: handle of the OMAP iommu device
91  * @dev: handle of the iommu device
92  *
93  * This is an omap iommu private data object, which binds an iommu user
94  * to its iommu device. This object should be placed at the iommu user's
95  * dev_archdata so generic IOMMU API can be used without having to
96  * utilize omap-specific plumbing anymore.
97  */
98 struct omap_iommu_arch_data {
99 	struct omap_iommu *iommu_dev;
100 	struct device *dev;
101 };
102 
103 struct cr_regs {
104 	u32 cam;
105 	u32 ram;
106 };
107 
108 struct iotlb_lock {
109 	short base;
110 	short vict;
111 };
112 
113 /*
114  * MMU Register offsets
115  */
116 #define MMU_REVISION		0x00
117 #define MMU_IRQSTATUS		0x18
118 #define MMU_IRQENABLE		0x1c
119 #define MMU_WALKING_ST		0x40
120 #define MMU_CNTL		0x44
121 #define MMU_FAULT_AD		0x48
122 #define MMU_TTB			0x4c
123 #define MMU_LOCK		0x50
124 #define MMU_LD_TLB		0x54
125 #define MMU_CAM			0x58
126 #define MMU_RAM			0x5c
127 #define MMU_GFLUSH		0x60
128 #define MMU_FLUSH_ENTRY		0x64
129 #define MMU_READ_CAM		0x68
130 #define MMU_READ_RAM		0x6c
131 #define MMU_EMU_FAULT_AD	0x70
132 #define MMU_GP_REG		0x88
133 
134 #define MMU_REG_SIZE		256
135 
136 /*
137  * MMU Register bit definitions
138  */
139 /* IRQSTATUS & IRQENABLE */
140 #define MMU_IRQ_MULTIHITFAULT	BIT(4)
141 #define MMU_IRQ_TABLEWALKFAULT	BIT(3)
142 #define MMU_IRQ_EMUMISS		BIT(2)
143 #define MMU_IRQ_TRANSLATIONFAULT	BIT(1)
144 #define MMU_IRQ_TLBMISS		BIT(0)
145 
146 #define __MMU_IRQ_FAULT		\
147 	(MMU_IRQ_MULTIHITFAULT | MMU_IRQ_EMUMISS | MMU_IRQ_TRANSLATIONFAULT)
148 #define MMU_IRQ_MASK		\
149 	(__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_TLBMISS)
150 #define MMU_IRQ_TWL_MASK	(__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT)
151 #define MMU_IRQ_TLB_MISS_MASK	(__MMU_IRQ_FAULT | MMU_IRQ_TLBMISS)
152 
153 /* MMU_CNTL */
154 #define MMU_CNTL_SHIFT		1
155 #define MMU_CNTL_MASK		(7 << MMU_CNTL_SHIFT)
156 #define MMU_CNTL_EML_TLB	BIT(3)
157 #define MMU_CNTL_TWL_EN		BIT(2)
158 #define MMU_CNTL_MMU_EN		BIT(1)
159 
160 /* CAM */
161 #define MMU_CAM_VATAG_SHIFT	12
162 #define MMU_CAM_VATAG_MASK \
163 	((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT)
164 #define MMU_CAM_P		BIT(3)
165 #define MMU_CAM_V		BIT(2)
166 #define MMU_CAM_PGSZ_MASK	3
167 #define MMU_CAM_PGSZ_1M		(0 << 0)
168 #define MMU_CAM_PGSZ_64K	(1 << 0)
169 #define MMU_CAM_PGSZ_4K		(2 << 0)
170 #define MMU_CAM_PGSZ_16M	(3 << 0)
171 
172 /* RAM */
173 #define MMU_RAM_PADDR_SHIFT	12
174 #define MMU_RAM_PADDR_MASK \
175 	((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT)
176 
177 #define MMU_RAM_ENDIAN_SHIFT	9
178 #define MMU_RAM_ENDIAN_MASK	BIT(MMU_RAM_ENDIAN_SHIFT)
179 #define MMU_RAM_ENDIAN_LITTLE	(0 << MMU_RAM_ENDIAN_SHIFT)
180 #define MMU_RAM_ENDIAN_BIG	BIT(MMU_RAM_ENDIAN_SHIFT)
181 
182 #define MMU_RAM_ELSZ_SHIFT	7
183 #define MMU_RAM_ELSZ_MASK	(3 << MMU_RAM_ELSZ_SHIFT)
184 #define MMU_RAM_ELSZ_8		(0 << MMU_RAM_ELSZ_SHIFT)
185 #define MMU_RAM_ELSZ_16		(1 << MMU_RAM_ELSZ_SHIFT)
186 #define MMU_RAM_ELSZ_32		(2 << MMU_RAM_ELSZ_SHIFT)
187 #define MMU_RAM_ELSZ_NONE	(3 << MMU_RAM_ELSZ_SHIFT)
188 #define MMU_RAM_MIXED_SHIFT	6
189 #define MMU_RAM_MIXED_MASK	BIT(MMU_RAM_MIXED_SHIFT)
190 #define MMU_RAM_MIXED		MMU_RAM_MIXED_MASK
191 
192 #define MMU_GP_REG_BUS_ERR_BACK_EN	0x1
193 
194 #define get_cam_va_mask(pgsz)				\
195 	(((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff000000 :	\
196 	 ((pgsz) == MMU_CAM_PGSZ_1M)  ? 0xfff00000 :	\
197 	 ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 :	\
198 	 ((pgsz) == MMU_CAM_PGSZ_4K)  ? 0xfffff000 : 0)
199 
200 /*
201  * DSP_SYSTEM registers and bit definitions (applicable only for DRA7xx DSP)
202  */
203 #define DSP_SYS_REVISION		0x00
204 #define DSP_SYS_MMU_CONFIG		0x18
205 #define DSP_SYS_MMU_CONFIG_EN_SHIFT	4
206 
207 /*
208  * utilities for super page(16MB, 1MB, 64KB and 4KB)
209  */
210 
211 #define iopgsz_max(bytes)			\
212 	(((bytes) >= SZ_16M) ? SZ_16M :		\
213 	 ((bytes) >= SZ_1M)  ? SZ_1M  :		\
214 	 ((bytes) >= SZ_64K) ? SZ_64K :		\
215 	 ((bytes) >= SZ_4K)  ? SZ_4K  :	0)
216 
217 #define bytes_to_iopgsz(bytes)				\
218 	(((bytes) == SZ_16M) ? MMU_CAM_PGSZ_16M :	\
219 	 ((bytes) == SZ_1M)  ? MMU_CAM_PGSZ_1M  :	\
220 	 ((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K :	\
221 	 ((bytes) == SZ_4K)  ? MMU_CAM_PGSZ_4K  : -1)
222 
223 #define iopgsz_to_bytes(iopgsz)				\
224 	(((iopgsz) == MMU_CAM_PGSZ_16M)	? SZ_16M :	\
225 	 ((iopgsz) == MMU_CAM_PGSZ_1M)	? SZ_1M  :	\
226 	 ((iopgsz) == MMU_CAM_PGSZ_64K)	? SZ_64K :	\
227 	 ((iopgsz) == MMU_CAM_PGSZ_4K)	? SZ_4K  : 0)
228 
229 #define iopgsz_ok(bytes) (bytes_to_iopgsz(bytes) >= 0)
230 
231 /*
232  * global functions
233  */
234 
235 struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n);
236 void iotlb_lock_get(struct omap_iommu *obj, struct iotlb_lock *l);
237 void iotlb_lock_set(struct omap_iommu *obj, struct iotlb_lock *l);
238 
239 #ifdef CONFIG_OMAP_IOMMU_DEBUG
240 void omap_iommu_debugfs_init(void);
241 void omap_iommu_debugfs_exit(void);
242 
243 void omap_iommu_debugfs_add(struct omap_iommu *obj);
244 void omap_iommu_debugfs_remove(struct omap_iommu *obj);
245 #else
omap_iommu_debugfs_init(void)246 static inline void omap_iommu_debugfs_init(void) { }
omap_iommu_debugfs_exit(void)247 static inline void omap_iommu_debugfs_exit(void) { }
248 
omap_iommu_debugfs_add(struct omap_iommu * obj)249 static inline void omap_iommu_debugfs_add(struct omap_iommu *obj) { }
omap_iommu_debugfs_remove(struct omap_iommu * obj)250 static inline void omap_iommu_debugfs_remove(struct omap_iommu *obj) { }
251 #endif
252 
253 /*
254  * register accessors
255  */
iommu_read_reg(struct omap_iommu * obj,size_t offs)256 static inline u32 iommu_read_reg(struct omap_iommu *obj, size_t offs)
257 {
258 	return __raw_readl(obj->regbase + offs);
259 }
260 
iommu_write_reg(struct omap_iommu * obj,u32 val,size_t offs)261 static inline void iommu_write_reg(struct omap_iommu *obj, u32 val, size_t offs)
262 {
263 	__raw_writel(val, obj->regbase + offs);
264 }
265 
iotlb_cr_valid(struct cr_regs * cr)266 static inline int iotlb_cr_valid(struct cr_regs *cr)
267 {
268 	if (!cr)
269 		return -EINVAL;
270 
271 	return cr->cam & MMU_CAM_V;
272 }
273 
274 #endif /* _OMAP_IOMMU_H */
275