1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * isp.c
4 *
5 * TI OMAP3 ISP - Core
6 *
7 * Copyright (C) 2006-2010 Nokia Corporation
8 * Copyright (C) 2007-2009 Texas Instruments, Inc.
9 *
10 * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
11 * Sakari Ailus <sakari.ailus@iki.fi>
12 *
13 * Contributors:
14 * Laurent Pinchart <laurent.pinchart@ideasonboard.com>
15 * Sakari Ailus <sakari.ailus@iki.fi>
16 * David Cohen <dacohen@gmail.com>
17 * Stanimir Varbanov <svarbanov@mm-sol.com>
18 * Vimarsh Zutshi <vimarsh.zutshi@gmail.com>
19 * Tuukka Toivonen <tuukkat76@gmail.com>
20 * Sergio Aguirre <saaguirre@ti.com>
21 * Antti Koskipaa <akoskipa@gmail.com>
22 * Ivan T. Ivanov <iivanov@mm-sol.com>
23 * RaniSuneela <r-m@ti.com>
24 * Atanas Filipov <afilipov@mm-sol.com>
25 * Gjorgji Rosikopulos <grosikopulos@mm-sol.com>
26 * Hiroshi DOYU <hiroshi.doyu@nokia.com>
27 * Nayden Kanchev <nkanchev@mm-sol.com>
28 * Phil Carmody <ext-phil.2.carmody@nokia.com>
29 * Artem Bityutskiy <artem.bityutskiy@nokia.com>
30 * Dominic Curran <dcurran@ti.com>
31 * Ilkka Myllyperkio <ilkka.myllyperkio@sofica.fi>
32 * Pallavi Kulkarni <p-kulkarni@ti.com>
33 * Vaibhav Hiremath <hvaibhav@ti.com>
34 * Mohit Jalori <mjalori@ti.com>
35 * Sameer Venkatraman <sameerv@ti.com>
36 * Senthilvadivu Guruswamy <svadivu@ti.com>
37 * Thara Gopinath <thara@ti.com>
38 * Toni Leinonen <toni.leinonen@nokia.com>
39 * Troy Laramy <t-laramy@ti.com>
40 */
41
42 #include <linux/clk.h>
43 #include <linux/clkdev.h>
44 #include <linux/delay.h>
45 #include <linux/device.h>
46 #include <linux/dma-mapping.h>
47 #include <linux/i2c.h>
48 #include <linux/interrupt.h>
49 #include <linux/mfd/syscon.h>
50 #include <linux/module.h>
51 #include <linux/omap-iommu.h>
52 #include <linux/platform_device.h>
53 #include <linux/property.h>
54 #include <linux/regulator/consumer.h>
55 #include <linux/slab.h>
56 #include <linux/sched.h>
57 #include <linux/vmalloc.h>
58
59 #ifdef CONFIG_ARM_DMA_USE_IOMMU
60 #include <asm/dma-iommu.h>
61 #endif
62
63 #include <media/v4l2-common.h>
64 #include <media/v4l2-fwnode.h>
65 #include <media/v4l2-device.h>
66 #include <media/v4l2-mc.h>
67
68 #include "isp.h"
69 #include "ispreg.h"
70 #include "ispccdc.h"
71 #include "isppreview.h"
72 #include "ispresizer.h"
73 #include "ispcsi2.h"
74 #include "ispccp2.h"
75 #include "isph3a.h"
76 #include "isphist.h"
77
78 static unsigned int autoidle;
79 module_param(autoidle, int, 0444);
80 MODULE_PARM_DESC(autoidle, "Enable OMAP3ISP AUTOIDLE support");
81
82 static void isp_save_ctx(struct isp_device *isp);
83
84 static void isp_restore_ctx(struct isp_device *isp);
85
86 static const struct isp_res_mapping isp_res_maps[] = {
87 {
88 .isp_rev = ISP_REVISION_2_0,
89 .offset = {
90 /* first MMIO area */
91 0x0000, /* base, len 0x0070 */
92 0x0400, /* ccp2, len 0x01f0 */
93 0x0600, /* ccdc, len 0x00a8 */
94 0x0a00, /* hist, len 0x0048 */
95 0x0c00, /* h3a, len 0x0060 */
96 0x0e00, /* preview, len 0x00a0 */
97 0x1000, /* resizer, len 0x00ac */
98 0x1200, /* sbl, len 0x00fc */
99 /* second MMIO area */
100 0x0000, /* csi2a, len 0x0170 */
101 0x0170, /* csiphy2, len 0x000c */
102 },
103 .phy_type = ISP_PHY_TYPE_3430,
104 },
105 {
106 .isp_rev = ISP_REVISION_15_0,
107 .offset = {
108 /* first MMIO area */
109 0x0000, /* base, len 0x0070 */
110 0x0400, /* ccp2, len 0x01f0 */
111 0x0600, /* ccdc, len 0x00a8 */
112 0x0a00, /* hist, len 0x0048 */
113 0x0c00, /* h3a, len 0x0060 */
114 0x0e00, /* preview, len 0x00a0 */
115 0x1000, /* resizer, len 0x00ac */
116 0x1200, /* sbl, len 0x00fc */
117 /* second MMIO area */
118 0x0000, /* csi2a, len 0x0170 (1st area) */
119 0x0170, /* csiphy2, len 0x000c */
120 0x01c0, /* csi2a, len 0x0040 (2nd area) */
121 0x0400, /* csi2c, len 0x0170 (1st area) */
122 0x0570, /* csiphy1, len 0x000c */
123 0x05c0, /* csi2c, len 0x0040 (2nd area) */
124 },
125 .phy_type = ISP_PHY_TYPE_3630,
126 },
127 };
128
129 /* Structure for saving/restoring ISP module registers */
130 static struct isp_reg isp_reg_list[] = {
131 {OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG, 0},
132 {OMAP3_ISP_IOMEM_MAIN, ISP_CTRL, 0},
133 {OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_CTRL, 0},
134 {0, ISP_TOK_TERM, 0}
135 };
136
137 /*
138 * omap3isp_flush - Post pending L3 bus writes by doing a register readback
139 * @isp: OMAP3 ISP device
140 *
141 * In order to force posting of pending writes, we need to write and
142 * readback the same register, in this case the revision register.
143 *
144 * See this link for reference:
145 * https://www.mail-archive.com/linux-omap@vger.kernel.org/msg08149.html
146 */
omap3isp_flush(struct isp_device * isp)147 void omap3isp_flush(struct isp_device *isp)
148 {
149 isp_reg_writel(isp, 0, OMAP3_ISP_IOMEM_MAIN, ISP_REVISION);
150 isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_REVISION);
151 }
152
153 /* -----------------------------------------------------------------------------
154 * XCLK
155 */
156
157 #define to_isp_xclk(_hw) container_of(_hw, struct isp_xclk, hw)
158
isp_xclk_update(struct isp_xclk * xclk,u32 divider)159 static void isp_xclk_update(struct isp_xclk *xclk, u32 divider)
160 {
161 switch (xclk->id) {
162 case ISP_XCLK_A:
163 isp_reg_clr_set(xclk->isp, OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_CTRL,
164 ISPTCTRL_CTRL_DIVA_MASK,
165 divider << ISPTCTRL_CTRL_DIVA_SHIFT);
166 break;
167 case ISP_XCLK_B:
168 isp_reg_clr_set(xclk->isp, OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_CTRL,
169 ISPTCTRL_CTRL_DIVB_MASK,
170 divider << ISPTCTRL_CTRL_DIVB_SHIFT);
171 break;
172 }
173 }
174
isp_xclk_prepare(struct clk_hw * hw)175 static int isp_xclk_prepare(struct clk_hw *hw)
176 {
177 struct isp_xclk *xclk = to_isp_xclk(hw);
178
179 omap3isp_get(xclk->isp);
180
181 return 0;
182 }
183
isp_xclk_unprepare(struct clk_hw * hw)184 static void isp_xclk_unprepare(struct clk_hw *hw)
185 {
186 struct isp_xclk *xclk = to_isp_xclk(hw);
187
188 omap3isp_put(xclk->isp);
189 }
190
isp_xclk_enable(struct clk_hw * hw)191 static int isp_xclk_enable(struct clk_hw *hw)
192 {
193 struct isp_xclk *xclk = to_isp_xclk(hw);
194 unsigned long flags;
195
196 spin_lock_irqsave(&xclk->lock, flags);
197 isp_xclk_update(xclk, xclk->divider);
198 xclk->enabled = true;
199 spin_unlock_irqrestore(&xclk->lock, flags);
200
201 return 0;
202 }
203
isp_xclk_disable(struct clk_hw * hw)204 static void isp_xclk_disable(struct clk_hw *hw)
205 {
206 struct isp_xclk *xclk = to_isp_xclk(hw);
207 unsigned long flags;
208
209 spin_lock_irqsave(&xclk->lock, flags);
210 isp_xclk_update(xclk, 0);
211 xclk->enabled = false;
212 spin_unlock_irqrestore(&xclk->lock, flags);
213 }
214
isp_xclk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)215 static unsigned long isp_xclk_recalc_rate(struct clk_hw *hw,
216 unsigned long parent_rate)
217 {
218 struct isp_xclk *xclk = to_isp_xclk(hw);
219
220 return parent_rate / xclk->divider;
221 }
222
isp_xclk_calc_divider(unsigned long * rate,unsigned long parent_rate)223 static u32 isp_xclk_calc_divider(unsigned long *rate, unsigned long parent_rate)
224 {
225 u32 divider;
226
227 if (*rate >= parent_rate) {
228 *rate = parent_rate;
229 return ISPTCTRL_CTRL_DIV_BYPASS;
230 }
231
232 if (*rate == 0)
233 *rate = 1;
234
235 divider = DIV_ROUND_CLOSEST(parent_rate, *rate);
236 if (divider >= ISPTCTRL_CTRL_DIV_BYPASS)
237 divider = ISPTCTRL_CTRL_DIV_BYPASS - 1;
238
239 *rate = parent_rate / divider;
240 return divider;
241 }
242
isp_xclk_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)243 static long isp_xclk_round_rate(struct clk_hw *hw, unsigned long rate,
244 unsigned long *parent_rate)
245 {
246 isp_xclk_calc_divider(&rate, *parent_rate);
247 return rate;
248 }
249
isp_xclk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)250 static int isp_xclk_set_rate(struct clk_hw *hw, unsigned long rate,
251 unsigned long parent_rate)
252 {
253 struct isp_xclk *xclk = to_isp_xclk(hw);
254 unsigned long flags;
255 u32 divider;
256
257 divider = isp_xclk_calc_divider(&rate, parent_rate);
258
259 spin_lock_irqsave(&xclk->lock, flags);
260
261 xclk->divider = divider;
262 if (xclk->enabled)
263 isp_xclk_update(xclk, divider);
264
265 spin_unlock_irqrestore(&xclk->lock, flags);
266
267 dev_dbg(xclk->isp->dev, "%s: cam_xclk%c set to %lu Hz (div %u)\n",
268 __func__, xclk->id == ISP_XCLK_A ? 'a' : 'b', rate, divider);
269 return 0;
270 }
271
272 static const struct clk_ops isp_xclk_ops = {
273 .prepare = isp_xclk_prepare,
274 .unprepare = isp_xclk_unprepare,
275 .enable = isp_xclk_enable,
276 .disable = isp_xclk_disable,
277 .recalc_rate = isp_xclk_recalc_rate,
278 .round_rate = isp_xclk_round_rate,
279 .set_rate = isp_xclk_set_rate,
280 };
281
282 static const char *isp_xclk_parent_name = "cam_mclk";
283
isp_xclk_src_get(struct of_phandle_args * clkspec,void * data)284 static struct clk *isp_xclk_src_get(struct of_phandle_args *clkspec, void *data)
285 {
286 unsigned int idx = clkspec->args[0];
287 struct isp_device *isp = data;
288
289 if (idx >= ARRAY_SIZE(isp->xclks))
290 return ERR_PTR(-ENOENT);
291
292 return isp->xclks[idx].clk;
293 }
294
isp_xclk_init(struct isp_device * isp)295 static int isp_xclk_init(struct isp_device *isp)
296 {
297 struct device_node *np = isp->dev->of_node;
298 struct clk_init_data init = {};
299 unsigned int i;
300
301 for (i = 0; i < ARRAY_SIZE(isp->xclks); ++i)
302 isp->xclks[i].clk = ERR_PTR(-EINVAL);
303
304 for (i = 0; i < ARRAY_SIZE(isp->xclks); ++i) {
305 struct isp_xclk *xclk = &isp->xclks[i];
306
307 xclk->isp = isp;
308 xclk->id = i == 0 ? ISP_XCLK_A : ISP_XCLK_B;
309 xclk->divider = 1;
310 spin_lock_init(&xclk->lock);
311
312 init.name = i == 0 ? "cam_xclka" : "cam_xclkb";
313 init.ops = &isp_xclk_ops;
314 init.parent_names = &isp_xclk_parent_name;
315 init.num_parents = 1;
316
317 xclk->hw.init = &init;
318 /*
319 * The first argument is NULL in order to avoid circular
320 * reference, as this driver takes reference on the
321 * sensor subdevice modules and the sensors would take
322 * reference on this module through clk_get().
323 */
324 xclk->clk = clk_register(NULL, &xclk->hw);
325 if (IS_ERR(xclk->clk))
326 return PTR_ERR(xclk->clk);
327 }
328
329 if (np)
330 of_clk_add_provider(np, isp_xclk_src_get, isp);
331
332 return 0;
333 }
334
isp_xclk_cleanup(struct isp_device * isp)335 static void isp_xclk_cleanup(struct isp_device *isp)
336 {
337 struct device_node *np = isp->dev->of_node;
338 unsigned int i;
339
340 if (np)
341 of_clk_del_provider(np);
342
343 for (i = 0; i < ARRAY_SIZE(isp->xclks); ++i) {
344 struct isp_xclk *xclk = &isp->xclks[i];
345
346 if (!IS_ERR(xclk->clk))
347 clk_unregister(xclk->clk);
348 }
349 }
350
351 /* -----------------------------------------------------------------------------
352 * Interrupts
353 */
354
355 /*
356 * isp_enable_interrupts - Enable ISP interrupts.
357 * @isp: OMAP3 ISP device
358 */
isp_enable_interrupts(struct isp_device * isp)359 static void isp_enable_interrupts(struct isp_device *isp)
360 {
361 static const u32 irq = IRQ0ENABLE_CSIA_IRQ
362 | IRQ0ENABLE_CSIB_IRQ
363 | IRQ0ENABLE_CCDC_LSC_PREF_ERR_IRQ
364 | IRQ0ENABLE_CCDC_LSC_DONE_IRQ
365 | IRQ0ENABLE_CCDC_VD0_IRQ
366 | IRQ0ENABLE_CCDC_VD1_IRQ
367 | IRQ0ENABLE_HS_VS_IRQ
368 | IRQ0ENABLE_HIST_DONE_IRQ
369 | IRQ0ENABLE_H3A_AWB_DONE_IRQ
370 | IRQ0ENABLE_H3A_AF_DONE_IRQ
371 | IRQ0ENABLE_PRV_DONE_IRQ
372 | IRQ0ENABLE_RSZ_DONE_IRQ;
373
374 isp_reg_writel(isp, irq, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
375 isp_reg_writel(isp, irq, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE);
376 }
377
378 /*
379 * isp_disable_interrupts - Disable ISP interrupts.
380 * @isp: OMAP3 ISP device
381 */
isp_disable_interrupts(struct isp_device * isp)382 static void isp_disable_interrupts(struct isp_device *isp)
383 {
384 isp_reg_writel(isp, 0, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0ENABLE);
385 }
386
387 /*
388 * isp_core_init - ISP core settings
389 * @isp: OMAP3 ISP device
390 * @idle: Consider idle state.
391 *
392 * Set the power settings for the ISP and SBL bus and configure the HS/VS
393 * interrupt source.
394 *
395 * We need to configure the HS/VS interrupt source before interrupts get
396 * enabled, as the sensor might be free-running and the ISP default setting
397 * (HS edge) would put an unnecessary burden on the CPU.
398 */
isp_core_init(struct isp_device * isp,int idle)399 static void isp_core_init(struct isp_device *isp, int idle)
400 {
401 isp_reg_writel(isp,
402 ((idle ? ISP_SYSCONFIG_MIDLEMODE_SMARTSTANDBY :
403 ISP_SYSCONFIG_MIDLEMODE_FORCESTANDBY) <<
404 ISP_SYSCONFIG_MIDLEMODE_SHIFT) |
405 ((isp->revision == ISP_REVISION_15_0) ?
406 ISP_SYSCONFIG_AUTOIDLE : 0),
407 OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG);
408
409 isp_reg_writel(isp,
410 (isp->autoidle ? ISPCTRL_SBL_AUTOIDLE : 0) |
411 ISPCTRL_SYNC_DETECT_VSRISE,
412 OMAP3_ISP_IOMEM_MAIN, ISP_CTRL);
413 }
414
415 /*
416 * Configure the bridge and lane shifter. Valid inputs are
417 *
418 * CCDC_INPUT_PARALLEL: Parallel interface
419 * CCDC_INPUT_CSI2A: CSI2a receiver
420 * CCDC_INPUT_CCP2B: CCP2b receiver
421 * CCDC_INPUT_CSI2C: CSI2c receiver
422 *
423 * The bridge and lane shifter are configured according to the selected input
424 * and the ISP platform data.
425 */
omap3isp_configure_bridge(struct isp_device * isp,enum ccdc_input_entity input,const struct isp_parallel_cfg * parcfg,unsigned int shift,unsigned int bridge)426 void omap3isp_configure_bridge(struct isp_device *isp,
427 enum ccdc_input_entity input,
428 const struct isp_parallel_cfg *parcfg,
429 unsigned int shift, unsigned int bridge)
430 {
431 u32 ispctrl_val;
432
433 ispctrl_val = isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL);
434 ispctrl_val &= ~ISPCTRL_SHIFT_MASK;
435 ispctrl_val &= ~ISPCTRL_PAR_CLK_POL_INV;
436 ispctrl_val &= ~ISPCTRL_PAR_SER_CLK_SEL_MASK;
437 ispctrl_val &= ~ISPCTRL_PAR_BRIDGE_MASK;
438 ispctrl_val |= bridge;
439
440 switch (input) {
441 case CCDC_INPUT_PARALLEL:
442 ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_PARALLEL;
443 ispctrl_val |= parcfg->clk_pol << ISPCTRL_PAR_CLK_POL_SHIFT;
444 shift += parcfg->data_lane_shift;
445 break;
446
447 case CCDC_INPUT_CSI2A:
448 ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_CSIA;
449 break;
450
451 case CCDC_INPUT_CCP2B:
452 ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_CSIB;
453 break;
454
455 case CCDC_INPUT_CSI2C:
456 ispctrl_val |= ISPCTRL_PAR_SER_CLK_SEL_CSIC;
457 break;
458
459 default:
460 return;
461 }
462
463 ispctrl_val |= ((shift/2) << ISPCTRL_SHIFT_SHIFT) & ISPCTRL_SHIFT_MASK;
464
465 isp_reg_writel(isp, ispctrl_val, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL);
466 }
467
omap3isp_hist_dma_done(struct isp_device * isp)468 void omap3isp_hist_dma_done(struct isp_device *isp)
469 {
470 if (omap3isp_ccdc_busy(&isp->isp_ccdc) ||
471 omap3isp_stat_pcr_busy(&isp->isp_hist)) {
472 /* Histogram cannot be enabled in this frame anymore */
473 atomic_set(&isp->isp_hist.buf_err, 1);
474 dev_dbg(isp->dev,
475 "hist: Out of synchronization with CCDC. Ignoring next buffer.\n");
476 }
477 }
478
isp_isr_dbg(struct isp_device * isp,u32 irqstatus)479 static inline void isp_isr_dbg(struct isp_device *isp, u32 irqstatus)
480 {
481 static const char *name[] = {
482 "CSIA_IRQ",
483 "res1",
484 "res2",
485 "CSIB_LCM_IRQ",
486 "CSIB_IRQ",
487 "res5",
488 "res6",
489 "res7",
490 "CCDC_VD0_IRQ",
491 "CCDC_VD1_IRQ",
492 "CCDC_VD2_IRQ",
493 "CCDC_ERR_IRQ",
494 "H3A_AF_DONE_IRQ",
495 "H3A_AWB_DONE_IRQ",
496 "res14",
497 "res15",
498 "HIST_DONE_IRQ",
499 "CCDC_LSC_DONE",
500 "CCDC_LSC_PREFETCH_COMPLETED",
501 "CCDC_LSC_PREFETCH_ERROR",
502 "PRV_DONE_IRQ",
503 "CBUFF_IRQ",
504 "res22",
505 "res23",
506 "RSZ_DONE_IRQ",
507 "OVF_IRQ",
508 "res26",
509 "res27",
510 "MMU_ERR_IRQ",
511 "OCP_ERR_IRQ",
512 "SEC_ERR_IRQ",
513 "HS_VS_IRQ",
514 };
515 int i;
516
517 dev_dbg(isp->dev, "ISP IRQ: ");
518
519 for (i = 0; i < ARRAY_SIZE(name); i++) {
520 if ((1 << i) & irqstatus)
521 printk(KERN_CONT "%s ", name[i]);
522 }
523 printk(KERN_CONT "\n");
524 }
525
isp_isr_sbl(struct isp_device * isp)526 static void isp_isr_sbl(struct isp_device *isp)
527 {
528 struct device *dev = isp->dev;
529 struct isp_pipeline *pipe;
530 u32 sbl_pcr;
531
532 /*
533 * Handle shared buffer logic overflows for video buffers.
534 * ISPSBL_PCR_CCDCPRV_2_RSZ_OVF can be safely ignored.
535 */
536 sbl_pcr = isp_reg_readl(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_PCR);
537 isp_reg_writel(isp, sbl_pcr, OMAP3_ISP_IOMEM_SBL, ISPSBL_PCR);
538 sbl_pcr &= ~ISPSBL_PCR_CCDCPRV_2_RSZ_OVF;
539
540 if (sbl_pcr)
541 dev_dbg(dev, "SBL overflow (PCR = 0x%08x)\n", sbl_pcr);
542
543 if (sbl_pcr & ISPSBL_PCR_CSIB_WBL_OVF) {
544 pipe = to_isp_pipeline(&isp->isp_ccp2.subdev.entity);
545 if (pipe != NULL)
546 pipe->error = true;
547 }
548
549 if (sbl_pcr & ISPSBL_PCR_CSIA_WBL_OVF) {
550 pipe = to_isp_pipeline(&isp->isp_csi2a.subdev.entity);
551 if (pipe != NULL)
552 pipe->error = true;
553 }
554
555 if (sbl_pcr & ISPSBL_PCR_CCDC_WBL_OVF) {
556 pipe = to_isp_pipeline(&isp->isp_ccdc.subdev.entity);
557 if (pipe != NULL)
558 pipe->error = true;
559 }
560
561 if (sbl_pcr & ISPSBL_PCR_PRV_WBL_OVF) {
562 pipe = to_isp_pipeline(&isp->isp_prev.subdev.entity);
563 if (pipe != NULL)
564 pipe->error = true;
565 }
566
567 if (sbl_pcr & (ISPSBL_PCR_RSZ1_WBL_OVF
568 | ISPSBL_PCR_RSZ2_WBL_OVF
569 | ISPSBL_PCR_RSZ3_WBL_OVF
570 | ISPSBL_PCR_RSZ4_WBL_OVF)) {
571 pipe = to_isp_pipeline(&isp->isp_res.subdev.entity);
572 if (pipe != NULL)
573 pipe->error = true;
574 }
575
576 if (sbl_pcr & ISPSBL_PCR_H3A_AF_WBL_OVF)
577 omap3isp_stat_sbl_overflow(&isp->isp_af);
578
579 if (sbl_pcr & ISPSBL_PCR_H3A_AEAWB_WBL_OVF)
580 omap3isp_stat_sbl_overflow(&isp->isp_aewb);
581 }
582
583 /*
584 * isp_isr - Interrupt Service Routine for Camera ISP module.
585 * @irq: Not used currently.
586 * @_isp: Pointer to the OMAP3 ISP device
587 *
588 * Handles the corresponding callback if plugged in.
589 */
isp_isr(int irq,void * _isp)590 static irqreturn_t isp_isr(int irq, void *_isp)
591 {
592 static const u32 ccdc_events = IRQ0STATUS_CCDC_LSC_PREF_ERR_IRQ |
593 IRQ0STATUS_CCDC_LSC_DONE_IRQ |
594 IRQ0STATUS_CCDC_VD0_IRQ |
595 IRQ0STATUS_CCDC_VD1_IRQ |
596 IRQ0STATUS_HS_VS_IRQ;
597 struct isp_device *isp = _isp;
598 u32 irqstatus;
599
600 irqstatus = isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
601 isp_reg_writel(isp, irqstatus, OMAP3_ISP_IOMEM_MAIN, ISP_IRQ0STATUS);
602
603 isp_isr_sbl(isp);
604
605 if (irqstatus & IRQ0STATUS_CSIA_IRQ)
606 omap3isp_csi2_isr(&isp->isp_csi2a);
607
608 if (irqstatus & IRQ0STATUS_CSIB_IRQ)
609 omap3isp_ccp2_isr(&isp->isp_ccp2);
610
611 if (irqstatus & IRQ0STATUS_CCDC_VD0_IRQ) {
612 if (isp->isp_ccdc.output & CCDC_OUTPUT_PREVIEW)
613 omap3isp_preview_isr_frame_sync(&isp->isp_prev);
614 if (isp->isp_ccdc.output & CCDC_OUTPUT_RESIZER)
615 omap3isp_resizer_isr_frame_sync(&isp->isp_res);
616 omap3isp_stat_isr_frame_sync(&isp->isp_aewb);
617 omap3isp_stat_isr_frame_sync(&isp->isp_af);
618 omap3isp_stat_isr_frame_sync(&isp->isp_hist);
619 }
620
621 if (irqstatus & ccdc_events)
622 omap3isp_ccdc_isr(&isp->isp_ccdc, irqstatus & ccdc_events);
623
624 if (irqstatus & IRQ0STATUS_PRV_DONE_IRQ) {
625 if (isp->isp_prev.output & PREVIEW_OUTPUT_RESIZER)
626 omap3isp_resizer_isr_frame_sync(&isp->isp_res);
627 omap3isp_preview_isr(&isp->isp_prev);
628 }
629
630 if (irqstatus & IRQ0STATUS_RSZ_DONE_IRQ)
631 omap3isp_resizer_isr(&isp->isp_res);
632
633 if (irqstatus & IRQ0STATUS_H3A_AWB_DONE_IRQ)
634 omap3isp_stat_isr(&isp->isp_aewb);
635
636 if (irqstatus & IRQ0STATUS_H3A_AF_DONE_IRQ)
637 omap3isp_stat_isr(&isp->isp_af);
638
639 if (irqstatus & IRQ0STATUS_HIST_DONE_IRQ)
640 omap3isp_stat_isr(&isp->isp_hist);
641
642 omap3isp_flush(isp);
643
644 #if defined(DEBUG) && defined(ISP_ISR_DEBUG)
645 isp_isr_dbg(isp, irqstatus);
646 #endif
647
648 return IRQ_HANDLED;
649 }
650
651 static const struct media_device_ops isp_media_ops = {
652 .link_notify = v4l2_pipeline_link_notify,
653 };
654
655 /* -----------------------------------------------------------------------------
656 * Pipeline stream management
657 */
658
659 /*
660 * isp_pipeline_enable - Enable streaming on a pipeline
661 * @pipe: ISP pipeline
662 * @mode: Stream mode (single shot or continuous)
663 *
664 * Walk the entities chain starting at the pipeline output video node and start
665 * all modules in the chain in the given mode.
666 *
667 * Return 0 if successful, or the return value of the failed video::s_stream
668 * operation otherwise.
669 */
isp_pipeline_enable(struct isp_pipeline * pipe,enum isp_pipeline_stream_state mode)670 static int isp_pipeline_enable(struct isp_pipeline *pipe,
671 enum isp_pipeline_stream_state mode)
672 {
673 struct isp_device *isp = pipe->output->isp;
674 struct media_entity *entity;
675 struct media_pad *pad;
676 struct v4l2_subdev *subdev;
677 unsigned long flags;
678 int ret;
679
680 /* Refuse to start streaming if an entity included in the pipeline has
681 * crashed. This check must be performed before the loop below to avoid
682 * starting entities if the pipeline won't start anyway (those entities
683 * would then likely fail to stop, making the problem worse).
684 */
685 if (media_entity_enum_intersects(&pipe->ent_enum, &isp->crashed))
686 return -EIO;
687
688 spin_lock_irqsave(&pipe->lock, flags);
689 pipe->state &= ~(ISP_PIPELINE_IDLE_INPUT | ISP_PIPELINE_IDLE_OUTPUT);
690 spin_unlock_irqrestore(&pipe->lock, flags);
691
692 pipe->do_propagation = false;
693
694 mutex_lock(&isp->media_dev.graph_mutex);
695
696 entity = &pipe->output->video.entity;
697 while (1) {
698 pad = &entity->pads[0];
699 if (!(pad->flags & MEDIA_PAD_FL_SINK))
700 break;
701
702 pad = media_entity_remote_pad(pad);
703 if (!pad || !is_media_entity_v4l2_subdev(pad->entity))
704 break;
705
706 entity = pad->entity;
707 subdev = media_entity_to_v4l2_subdev(entity);
708
709 ret = v4l2_subdev_call(subdev, video, s_stream, mode);
710 if (ret < 0 && ret != -ENOIOCTLCMD) {
711 mutex_unlock(&isp->media_dev.graph_mutex);
712 return ret;
713 }
714
715 if (subdev == &isp->isp_ccdc.subdev) {
716 v4l2_subdev_call(&isp->isp_aewb.subdev, video,
717 s_stream, mode);
718 v4l2_subdev_call(&isp->isp_af.subdev, video,
719 s_stream, mode);
720 v4l2_subdev_call(&isp->isp_hist.subdev, video,
721 s_stream, mode);
722 pipe->do_propagation = true;
723 }
724
725 /* Stop at the first external sub-device. */
726 if (subdev->dev != isp->dev)
727 break;
728 }
729
730 mutex_unlock(&isp->media_dev.graph_mutex);
731
732 return 0;
733 }
734
isp_pipeline_wait_resizer(struct isp_device * isp)735 static int isp_pipeline_wait_resizer(struct isp_device *isp)
736 {
737 return omap3isp_resizer_busy(&isp->isp_res);
738 }
739
isp_pipeline_wait_preview(struct isp_device * isp)740 static int isp_pipeline_wait_preview(struct isp_device *isp)
741 {
742 return omap3isp_preview_busy(&isp->isp_prev);
743 }
744
isp_pipeline_wait_ccdc(struct isp_device * isp)745 static int isp_pipeline_wait_ccdc(struct isp_device *isp)
746 {
747 return omap3isp_stat_busy(&isp->isp_af)
748 || omap3isp_stat_busy(&isp->isp_aewb)
749 || omap3isp_stat_busy(&isp->isp_hist)
750 || omap3isp_ccdc_busy(&isp->isp_ccdc);
751 }
752
753 #define ISP_STOP_TIMEOUT msecs_to_jiffies(1000)
754
isp_pipeline_wait(struct isp_device * isp,int (* busy)(struct isp_device * isp))755 static int isp_pipeline_wait(struct isp_device *isp,
756 int(*busy)(struct isp_device *isp))
757 {
758 unsigned long timeout = jiffies + ISP_STOP_TIMEOUT;
759
760 while (!time_after(jiffies, timeout)) {
761 if (!busy(isp))
762 return 0;
763 }
764
765 return 1;
766 }
767
768 /*
769 * isp_pipeline_disable - Disable streaming on a pipeline
770 * @pipe: ISP pipeline
771 *
772 * Walk the entities chain starting at the pipeline output video node and stop
773 * all modules in the chain. Wait synchronously for the modules to be stopped if
774 * necessary.
775 *
776 * Return 0 if all modules have been properly stopped, or -ETIMEDOUT if a module
777 * can't be stopped (in which case a software reset of the ISP is probably
778 * necessary).
779 */
isp_pipeline_disable(struct isp_pipeline * pipe)780 static int isp_pipeline_disable(struct isp_pipeline *pipe)
781 {
782 struct isp_device *isp = pipe->output->isp;
783 struct media_entity *entity;
784 struct media_pad *pad;
785 struct v4l2_subdev *subdev;
786 int failure = 0;
787 int ret;
788
789 /*
790 * We need to stop all the modules after CCDC first or they'll
791 * never stop since they may not get a full frame from CCDC.
792 */
793 entity = &pipe->output->video.entity;
794 while (1) {
795 pad = &entity->pads[0];
796 if (!(pad->flags & MEDIA_PAD_FL_SINK))
797 break;
798
799 pad = media_entity_remote_pad(pad);
800 if (!pad || !is_media_entity_v4l2_subdev(pad->entity))
801 break;
802
803 entity = pad->entity;
804 subdev = media_entity_to_v4l2_subdev(entity);
805
806 if (subdev == &isp->isp_ccdc.subdev) {
807 v4l2_subdev_call(&isp->isp_aewb.subdev,
808 video, s_stream, 0);
809 v4l2_subdev_call(&isp->isp_af.subdev,
810 video, s_stream, 0);
811 v4l2_subdev_call(&isp->isp_hist.subdev,
812 video, s_stream, 0);
813 }
814
815 ret = v4l2_subdev_call(subdev, video, s_stream, 0);
816
817 /* Stop at the first external sub-device. */
818 if (subdev->dev != isp->dev)
819 break;
820
821 if (subdev == &isp->isp_res.subdev)
822 ret |= isp_pipeline_wait(isp, isp_pipeline_wait_resizer);
823 else if (subdev == &isp->isp_prev.subdev)
824 ret |= isp_pipeline_wait(isp, isp_pipeline_wait_preview);
825 else if (subdev == &isp->isp_ccdc.subdev)
826 ret |= isp_pipeline_wait(isp, isp_pipeline_wait_ccdc);
827
828 /* Handle stop failures. An entity that fails to stop can
829 * usually just be restarted. Flag the stop failure nonetheless
830 * to trigger an ISP reset the next time the device is released,
831 * just in case.
832 *
833 * The preview engine is a special case. A failure to stop can
834 * mean a hardware crash. When that happens the preview engine
835 * won't respond to read/write operations on the L4 bus anymore,
836 * resulting in a bus fault and a kernel oops next time it gets
837 * accessed. Mark it as crashed to prevent pipelines including
838 * it from being started.
839 */
840 if (ret) {
841 dev_info(isp->dev, "Unable to stop %s\n", subdev->name);
842 isp->stop_failure = true;
843 if (subdev == &isp->isp_prev.subdev)
844 media_entity_enum_set(&isp->crashed,
845 &subdev->entity);
846 failure = -ETIMEDOUT;
847 }
848 }
849
850 return failure;
851 }
852
853 /*
854 * omap3isp_pipeline_set_stream - Enable/disable streaming on a pipeline
855 * @pipe: ISP pipeline
856 * @state: Stream state (stopped, single shot or continuous)
857 *
858 * Set the pipeline to the given stream state. Pipelines can be started in
859 * single-shot or continuous mode.
860 *
861 * Return 0 if successful, or the return value of the failed video::s_stream
862 * operation otherwise. The pipeline state is not updated when the operation
863 * fails, except when stopping the pipeline.
864 */
omap3isp_pipeline_set_stream(struct isp_pipeline * pipe,enum isp_pipeline_stream_state state)865 int omap3isp_pipeline_set_stream(struct isp_pipeline *pipe,
866 enum isp_pipeline_stream_state state)
867 {
868 int ret;
869
870 if (state == ISP_PIPELINE_STREAM_STOPPED)
871 ret = isp_pipeline_disable(pipe);
872 else
873 ret = isp_pipeline_enable(pipe, state);
874
875 if (ret == 0 || state == ISP_PIPELINE_STREAM_STOPPED)
876 pipe->stream_state = state;
877
878 return ret;
879 }
880
881 /*
882 * omap3isp_pipeline_cancel_stream - Cancel stream on a pipeline
883 * @pipe: ISP pipeline
884 *
885 * Cancelling a stream mark all buffers on all video nodes in the pipeline as
886 * erroneous and makes sure no new buffer can be queued. This function is called
887 * when a fatal error that prevents any further operation on the pipeline
888 * occurs.
889 */
omap3isp_pipeline_cancel_stream(struct isp_pipeline * pipe)890 void omap3isp_pipeline_cancel_stream(struct isp_pipeline *pipe)
891 {
892 if (pipe->input)
893 omap3isp_video_cancel_stream(pipe->input);
894 if (pipe->output)
895 omap3isp_video_cancel_stream(pipe->output);
896 }
897
898 /*
899 * isp_pipeline_resume - Resume streaming on a pipeline
900 * @pipe: ISP pipeline
901 *
902 * Resume video output and input and re-enable pipeline.
903 */
isp_pipeline_resume(struct isp_pipeline * pipe)904 static void isp_pipeline_resume(struct isp_pipeline *pipe)
905 {
906 int singleshot = pipe->stream_state == ISP_PIPELINE_STREAM_SINGLESHOT;
907
908 omap3isp_video_resume(pipe->output, !singleshot);
909 if (singleshot)
910 omap3isp_video_resume(pipe->input, 0);
911 isp_pipeline_enable(pipe, pipe->stream_state);
912 }
913
914 /*
915 * isp_pipeline_suspend - Suspend streaming on a pipeline
916 * @pipe: ISP pipeline
917 *
918 * Suspend pipeline.
919 */
isp_pipeline_suspend(struct isp_pipeline * pipe)920 static void isp_pipeline_suspend(struct isp_pipeline *pipe)
921 {
922 isp_pipeline_disable(pipe);
923 }
924
925 /*
926 * isp_pipeline_is_last - Verify if entity has an enabled link to the output
927 * video node
928 * @me: ISP module's media entity
929 *
930 * Returns 1 if the entity has an enabled link to the output video node or 0
931 * otherwise. It's true only while pipeline can have no more than one output
932 * node.
933 */
isp_pipeline_is_last(struct media_entity * me)934 static int isp_pipeline_is_last(struct media_entity *me)
935 {
936 struct isp_pipeline *pipe;
937 struct media_pad *pad;
938
939 if (!me->pipe)
940 return 0;
941 pipe = to_isp_pipeline(me);
942 if (pipe->stream_state == ISP_PIPELINE_STREAM_STOPPED)
943 return 0;
944 pad = media_entity_remote_pad(&pipe->output->pad);
945 return pad->entity == me;
946 }
947
948 /*
949 * isp_suspend_module_pipeline - Suspend pipeline to which belongs the module
950 * @me: ISP module's media entity
951 *
952 * Suspend the whole pipeline if module's entity has an enabled link to the
953 * output video node. It works only while pipeline can have no more than one
954 * output node.
955 */
isp_suspend_module_pipeline(struct media_entity * me)956 static void isp_suspend_module_pipeline(struct media_entity *me)
957 {
958 if (isp_pipeline_is_last(me))
959 isp_pipeline_suspend(to_isp_pipeline(me));
960 }
961
962 /*
963 * isp_resume_module_pipeline - Resume pipeline to which belongs the module
964 * @me: ISP module's media entity
965 *
966 * Resume the whole pipeline if module's entity has an enabled link to the
967 * output video node. It works only while pipeline can have no more than one
968 * output node.
969 */
isp_resume_module_pipeline(struct media_entity * me)970 static void isp_resume_module_pipeline(struct media_entity *me)
971 {
972 if (isp_pipeline_is_last(me))
973 isp_pipeline_resume(to_isp_pipeline(me));
974 }
975
976 /*
977 * isp_suspend_modules - Suspend ISP submodules.
978 * @isp: OMAP3 ISP device
979 *
980 * Returns 0 if suspend left in idle state all the submodules properly,
981 * or returns 1 if a general Reset is required to suspend the submodules.
982 */
isp_suspend_modules(struct isp_device * isp)983 static int __maybe_unused isp_suspend_modules(struct isp_device *isp)
984 {
985 unsigned long timeout;
986
987 omap3isp_stat_suspend(&isp->isp_aewb);
988 omap3isp_stat_suspend(&isp->isp_af);
989 omap3isp_stat_suspend(&isp->isp_hist);
990 isp_suspend_module_pipeline(&isp->isp_res.subdev.entity);
991 isp_suspend_module_pipeline(&isp->isp_prev.subdev.entity);
992 isp_suspend_module_pipeline(&isp->isp_ccdc.subdev.entity);
993 isp_suspend_module_pipeline(&isp->isp_csi2a.subdev.entity);
994 isp_suspend_module_pipeline(&isp->isp_ccp2.subdev.entity);
995
996 timeout = jiffies + ISP_STOP_TIMEOUT;
997 while (omap3isp_stat_busy(&isp->isp_af)
998 || omap3isp_stat_busy(&isp->isp_aewb)
999 || omap3isp_stat_busy(&isp->isp_hist)
1000 || omap3isp_preview_busy(&isp->isp_prev)
1001 || omap3isp_resizer_busy(&isp->isp_res)
1002 || omap3isp_ccdc_busy(&isp->isp_ccdc)) {
1003 if (time_after(jiffies, timeout)) {
1004 dev_info(isp->dev, "can't stop modules.\n");
1005 return 1;
1006 }
1007 msleep(1);
1008 }
1009
1010 return 0;
1011 }
1012
1013 /*
1014 * isp_resume_modules - Resume ISP submodules.
1015 * @isp: OMAP3 ISP device
1016 */
isp_resume_modules(struct isp_device * isp)1017 static void __maybe_unused isp_resume_modules(struct isp_device *isp)
1018 {
1019 omap3isp_stat_resume(&isp->isp_aewb);
1020 omap3isp_stat_resume(&isp->isp_af);
1021 omap3isp_stat_resume(&isp->isp_hist);
1022 isp_resume_module_pipeline(&isp->isp_res.subdev.entity);
1023 isp_resume_module_pipeline(&isp->isp_prev.subdev.entity);
1024 isp_resume_module_pipeline(&isp->isp_ccdc.subdev.entity);
1025 isp_resume_module_pipeline(&isp->isp_csi2a.subdev.entity);
1026 isp_resume_module_pipeline(&isp->isp_ccp2.subdev.entity);
1027 }
1028
1029 /*
1030 * isp_reset - Reset ISP with a timeout wait for idle.
1031 * @isp: OMAP3 ISP device
1032 */
isp_reset(struct isp_device * isp)1033 static int isp_reset(struct isp_device *isp)
1034 {
1035 unsigned long timeout = 0;
1036
1037 isp_reg_writel(isp,
1038 isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG)
1039 | ISP_SYSCONFIG_SOFTRESET,
1040 OMAP3_ISP_IOMEM_MAIN, ISP_SYSCONFIG);
1041 while (!(isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN,
1042 ISP_SYSSTATUS) & 0x1)) {
1043 if (timeout++ > 10000) {
1044 dev_alert(isp->dev, "cannot reset ISP\n");
1045 return -ETIMEDOUT;
1046 }
1047 udelay(1);
1048 }
1049
1050 isp->stop_failure = false;
1051 media_entity_enum_zero(&isp->crashed);
1052 return 0;
1053 }
1054
1055 /*
1056 * isp_save_context - Saves the values of the ISP module registers.
1057 * @isp: OMAP3 ISP device
1058 * @reg_list: Structure containing pairs of register address and value to
1059 * modify on OMAP.
1060 */
1061 static void
isp_save_context(struct isp_device * isp,struct isp_reg * reg_list)1062 isp_save_context(struct isp_device *isp, struct isp_reg *reg_list)
1063 {
1064 struct isp_reg *next = reg_list;
1065
1066 for (; next->reg != ISP_TOK_TERM; next++)
1067 next->val = isp_reg_readl(isp, next->mmio_range, next->reg);
1068 }
1069
1070 /*
1071 * isp_restore_context - Restores the values of the ISP module registers.
1072 * @isp: OMAP3 ISP device
1073 * @reg_list: Structure containing pairs of register address and value to
1074 * modify on OMAP.
1075 */
1076 static void
isp_restore_context(struct isp_device * isp,struct isp_reg * reg_list)1077 isp_restore_context(struct isp_device *isp, struct isp_reg *reg_list)
1078 {
1079 struct isp_reg *next = reg_list;
1080
1081 for (; next->reg != ISP_TOK_TERM; next++)
1082 isp_reg_writel(isp, next->val, next->mmio_range, next->reg);
1083 }
1084
1085 /*
1086 * isp_save_ctx - Saves ISP, CCDC, HIST, H3A, PREV, RESZ & MMU context.
1087 * @isp: OMAP3 ISP device
1088 *
1089 * Routine for saving the context of each module in the ISP.
1090 * CCDC, HIST, H3A, PREV, RESZ and MMU.
1091 */
isp_save_ctx(struct isp_device * isp)1092 static void isp_save_ctx(struct isp_device *isp)
1093 {
1094 isp_save_context(isp, isp_reg_list);
1095 omap_iommu_save_ctx(isp->dev);
1096 }
1097
1098 /*
1099 * isp_restore_ctx - Restores ISP, CCDC, HIST, H3A, PREV, RESZ & MMU context.
1100 * @isp: OMAP3 ISP device
1101 *
1102 * Routine for restoring the context of each module in the ISP.
1103 * CCDC, HIST, H3A, PREV, RESZ and MMU.
1104 */
isp_restore_ctx(struct isp_device * isp)1105 static void isp_restore_ctx(struct isp_device *isp)
1106 {
1107 isp_restore_context(isp, isp_reg_list);
1108 omap_iommu_restore_ctx(isp->dev);
1109 omap3isp_ccdc_restore_context(isp);
1110 omap3isp_preview_restore_context(isp);
1111 }
1112
1113 /* -----------------------------------------------------------------------------
1114 * SBL resources management
1115 */
1116 #define OMAP3_ISP_SBL_READ (OMAP3_ISP_SBL_CSI1_READ | \
1117 OMAP3_ISP_SBL_CCDC_LSC_READ | \
1118 OMAP3_ISP_SBL_PREVIEW_READ | \
1119 OMAP3_ISP_SBL_RESIZER_READ)
1120 #define OMAP3_ISP_SBL_WRITE (OMAP3_ISP_SBL_CSI1_WRITE | \
1121 OMAP3_ISP_SBL_CSI2A_WRITE | \
1122 OMAP3_ISP_SBL_CSI2C_WRITE | \
1123 OMAP3_ISP_SBL_CCDC_WRITE | \
1124 OMAP3_ISP_SBL_PREVIEW_WRITE)
1125
omap3isp_sbl_enable(struct isp_device * isp,enum isp_sbl_resource res)1126 void omap3isp_sbl_enable(struct isp_device *isp, enum isp_sbl_resource res)
1127 {
1128 u32 sbl = 0;
1129
1130 isp->sbl_resources |= res;
1131
1132 if (isp->sbl_resources & OMAP3_ISP_SBL_CSI1_READ)
1133 sbl |= ISPCTRL_SBL_SHARED_RPORTA;
1134
1135 if (isp->sbl_resources & OMAP3_ISP_SBL_CCDC_LSC_READ)
1136 sbl |= ISPCTRL_SBL_SHARED_RPORTB;
1137
1138 if (isp->sbl_resources & OMAP3_ISP_SBL_CSI2C_WRITE)
1139 sbl |= ISPCTRL_SBL_SHARED_WPORTC;
1140
1141 if (isp->sbl_resources & OMAP3_ISP_SBL_RESIZER_WRITE)
1142 sbl |= ISPCTRL_SBL_WR0_RAM_EN;
1143
1144 if (isp->sbl_resources & OMAP3_ISP_SBL_WRITE)
1145 sbl |= ISPCTRL_SBL_WR1_RAM_EN;
1146
1147 if (isp->sbl_resources & OMAP3_ISP_SBL_READ)
1148 sbl |= ISPCTRL_SBL_RD_RAM_EN;
1149
1150 isp_reg_set(isp, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL, sbl);
1151 }
1152
omap3isp_sbl_disable(struct isp_device * isp,enum isp_sbl_resource res)1153 void omap3isp_sbl_disable(struct isp_device *isp, enum isp_sbl_resource res)
1154 {
1155 u32 sbl = 0;
1156
1157 isp->sbl_resources &= ~res;
1158
1159 if (!(isp->sbl_resources & OMAP3_ISP_SBL_CSI1_READ))
1160 sbl |= ISPCTRL_SBL_SHARED_RPORTA;
1161
1162 if (!(isp->sbl_resources & OMAP3_ISP_SBL_CCDC_LSC_READ))
1163 sbl |= ISPCTRL_SBL_SHARED_RPORTB;
1164
1165 if (!(isp->sbl_resources & OMAP3_ISP_SBL_CSI2C_WRITE))
1166 sbl |= ISPCTRL_SBL_SHARED_WPORTC;
1167
1168 if (!(isp->sbl_resources & OMAP3_ISP_SBL_RESIZER_WRITE))
1169 sbl |= ISPCTRL_SBL_WR0_RAM_EN;
1170
1171 if (!(isp->sbl_resources & OMAP3_ISP_SBL_WRITE))
1172 sbl |= ISPCTRL_SBL_WR1_RAM_EN;
1173
1174 if (!(isp->sbl_resources & OMAP3_ISP_SBL_READ))
1175 sbl |= ISPCTRL_SBL_RD_RAM_EN;
1176
1177 isp_reg_clr(isp, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL, sbl);
1178 }
1179
1180 /*
1181 * isp_module_sync_idle - Helper to sync module with its idle state
1182 * @me: ISP submodule's media entity
1183 * @wait: ISP submodule's wait queue for streamoff/interrupt synchronization
1184 * @stopping: flag which tells module wants to stop
1185 *
1186 * This function checks if ISP submodule needs to wait for next interrupt. If
1187 * yes, makes the caller to sleep while waiting for such event.
1188 */
omap3isp_module_sync_idle(struct media_entity * me,wait_queue_head_t * wait,atomic_t * stopping)1189 int omap3isp_module_sync_idle(struct media_entity *me, wait_queue_head_t *wait,
1190 atomic_t *stopping)
1191 {
1192 struct isp_pipeline *pipe = to_isp_pipeline(me);
1193
1194 if (pipe->stream_state == ISP_PIPELINE_STREAM_STOPPED ||
1195 (pipe->stream_state == ISP_PIPELINE_STREAM_SINGLESHOT &&
1196 !isp_pipeline_ready(pipe)))
1197 return 0;
1198
1199 /*
1200 * atomic_set() doesn't include memory barrier on ARM platform for SMP
1201 * scenario. We'll call it here to avoid race conditions.
1202 */
1203 atomic_set(stopping, 1);
1204 smp_mb();
1205
1206 /*
1207 * If module is the last one, it's writing to memory. In this case,
1208 * it's necessary to check if the module is already paused due to
1209 * DMA queue underrun or if it has to wait for next interrupt to be
1210 * idle.
1211 * If it isn't the last one, the function won't sleep but *stopping
1212 * will still be set to warn next submodule caller's interrupt the
1213 * module wants to be idle.
1214 */
1215 if (isp_pipeline_is_last(me)) {
1216 struct isp_video *video = pipe->output;
1217 unsigned long flags;
1218 spin_lock_irqsave(&video->irqlock, flags);
1219 if (video->dmaqueue_flags & ISP_VIDEO_DMAQUEUE_UNDERRUN) {
1220 spin_unlock_irqrestore(&video->irqlock, flags);
1221 atomic_set(stopping, 0);
1222 smp_mb();
1223 return 0;
1224 }
1225 spin_unlock_irqrestore(&video->irqlock, flags);
1226 if (!wait_event_timeout(*wait, !atomic_read(stopping),
1227 msecs_to_jiffies(1000))) {
1228 atomic_set(stopping, 0);
1229 smp_mb();
1230 return -ETIMEDOUT;
1231 }
1232 }
1233
1234 return 0;
1235 }
1236
1237 /*
1238 * omap3isp_module_sync_is_stopping - Helper to verify if module was stopping
1239 * @wait: ISP submodule's wait queue for streamoff/interrupt synchronization
1240 * @stopping: flag which tells module wants to stop
1241 *
1242 * This function checks if ISP submodule was stopping. In case of yes, it
1243 * notices the caller by setting stopping to 0 and waking up the wait queue.
1244 * Returns 1 if it was stopping or 0 otherwise.
1245 */
omap3isp_module_sync_is_stopping(wait_queue_head_t * wait,atomic_t * stopping)1246 int omap3isp_module_sync_is_stopping(wait_queue_head_t *wait,
1247 atomic_t *stopping)
1248 {
1249 if (atomic_cmpxchg(stopping, 1, 0)) {
1250 wake_up(wait);
1251 return 1;
1252 }
1253
1254 return 0;
1255 }
1256
1257 /* --------------------------------------------------------------------------
1258 * Clock management
1259 */
1260
1261 #define ISPCTRL_CLKS_MASK (ISPCTRL_H3A_CLK_EN | \
1262 ISPCTRL_HIST_CLK_EN | \
1263 ISPCTRL_RSZ_CLK_EN | \
1264 (ISPCTRL_CCDC_CLK_EN | ISPCTRL_CCDC_RAM_EN) | \
1265 (ISPCTRL_PREV_CLK_EN | ISPCTRL_PREV_RAM_EN))
1266
__isp_subclk_update(struct isp_device * isp)1267 static void __isp_subclk_update(struct isp_device *isp)
1268 {
1269 u32 clk = 0;
1270
1271 /* AEWB and AF share the same clock. */
1272 if (isp->subclk_resources &
1273 (OMAP3_ISP_SUBCLK_AEWB | OMAP3_ISP_SUBCLK_AF))
1274 clk |= ISPCTRL_H3A_CLK_EN;
1275
1276 if (isp->subclk_resources & OMAP3_ISP_SUBCLK_HIST)
1277 clk |= ISPCTRL_HIST_CLK_EN;
1278
1279 if (isp->subclk_resources & OMAP3_ISP_SUBCLK_RESIZER)
1280 clk |= ISPCTRL_RSZ_CLK_EN;
1281
1282 /* NOTE: For CCDC & Preview submodules, we need to affect internal
1283 * RAM as well.
1284 */
1285 if (isp->subclk_resources & OMAP3_ISP_SUBCLK_CCDC)
1286 clk |= ISPCTRL_CCDC_CLK_EN | ISPCTRL_CCDC_RAM_EN;
1287
1288 if (isp->subclk_resources & OMAP3_ISP_SUBCLK_PREVIEW)
1289 clk |= ISPCTRL_PREV_CLK_EN | ISPCTRL_PREV_RAM_EN;
1290
1291 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_MAIN, ISP_CTRL,
1292 ISPCTRL_CLKS_MASK, clk);
1293 }
1294
omap3isp_subclk_enable(struct isp_device * isp,enum isp_subclk_resource res)1295 void omap3isp_subclk_enable(struct isp_device *isp,
1296 enum isp_subclk_resource res)
1297 {
1298 isp->subclk_resources |= res;
1299
1300 __isp_subclk_update(isp);
1301 }
1302
omap3isp_subclk_disable(struct isp_device * isp,enum isp_subclk_resource res)1303 void omap3isp_subclk_disable(struct isp_device *isp,
1304 enum isp_subclk_resource res)
1305 {
1306 isp->subclk_resources &= ~res;
1307
1308 __isp_subclk_update(isp);
1309 }
1310
1311 /*
1312 * isp_enable_clocks - Enable ISP clocks
1313 * @isp: OMAP3 ISP device
1314 *
1315 * Return 0 if successful, or clk_prepare_enable return value if any of them
1316 * fails.
1317 */
isp_enable_clocks(struct isp_device * isp)1318 static int isp_enable_clocks(struct isp_device *isp)
1319 {
1320 int r;
1321 unsigned long rate;
1322
1323 r = clk_prepare_enable(isp->clock[ISP_CLK_CAM_ICK]);
1324 if (r) {
1325 dev_err(isp->dev, "failed to enable cam_ick clock\n");
1326 goto out_clk_enable_ick;
1327 }
1328 r = clk_set_rate(isp->clock[ISP_CLK_CAM_MCLK], CM_CAM_MCLK_HZ);
1329 if (r) {
1330 dev_err(isp->dev, "clk_set_rate for cam_mclk failed\n");
1331 goto out_clk_enable_mclk;
1332 }
1333 r = clk_prepare_enable(isp->clock[ISP_CLK_CAM_MCLK]);
1334 if (r) {
1335 dev_err(isp->dev, "failed to enable cam_mclk clock\n");
1336 goto out_clk_enable_mclk;
1337 }
1338 rate = clk_get_rate(isp->clock[ISP_CLK_CAM_MCLK]);
1339 if (rate != CM_CAM_MCLK_HZ)
1340 dev_warn(isp->dev, "unexpected cam_mclk rate:\n"
1341 " expected : %d\n"
1342 " actual : %ld\n", CM_CAM_MCLK_HZ, rate);
1343 r = clk_prepare_enable(isp->clock[ISP_CLK_CSI2_FCK]);
1344 if (r) {
1345 dev_err(isp->dev, "failed to enable csi2_fck clock\n");
1346 goto out_clk_enable_csi2_fclk;
1347 }
1348 return 0;
1349
1350 out_clk_enable_csi2_fclk:
1351 clk_disable_unprepare(isp->clock[ISP_CLK_CAM_MCLK]);
1352 out_clk_enable_mclk:
1353 clk_disable_unprepare(isp->clock[ISP_CLK_CAM_ICK]);
1354 out_clk_enable_ick:
1355 return r;
1356 }
1357
1358 /*
1359 * isp_disable_clocks - Disable ISP clocks
1360 * @isp: OMAP3 ISP device
1361 */
isp_disable_clocks(struct isp_device * isp)1362 static void isp_disable_clocks(struct isp_device *isp)
1363 {
1364 clk_disable_unprepare(isp->clock[ISP_CLK_CAM_ICK]);
1365 clk_disable_unprepare(isp->clock[ISP_CLK_CAM_MCLK]);
1366 clk_disable_unprepare(isp->clock[ISP_CLK_CSI2_FCK]);
1367 }
1368
1369 static const char *isp_clocks[] = {
1370 "cam_ick",
1371 "cam_mclk",
1372 "csi2_96m_fck",
1373 "l3_ick",
1374 };
1375
isp_get_clocks(struct isp_device * isp)1376 static int isp_get_clocks(struct isp_device *isp)
1377 {
1378 struct clk *clk;
1379 unsigned int i;
1380
1381 for (i = 0; i < ARRAY_SIZE(isp_clocks); ++i) {
1382 clk = devm_clk_get(isp->dev, isp_clocks[i]);
1383 if (IS_ERR(clk)) {
1384 dev_err(isp->dev, "clk_get %s failed\n", isp_clocks[i]);
1385 return PTR_ERR(clk);
1386 }
1387
1388 isp->clock[i] = clk;
1389 }
1390
1391 return 0;
1392 }
1393
1394 /*
1395 * omap3isp_get - Acquire the ISP resource.
1396 *
1397 * Initializes the clocks for the first acquire.
1398 *
1399 * Increment the reference count on the ISP. If the first reference is taken,
1400 * enable clocks and power-up all submodules.
1401 *
1402 * Return a pointer to the ISP device structure, or NULL if an error occurred.
1403 */
__omap3isp_get(struct isp_device * isp,bool irq)1404 static struct isp_device *__omap3isp_get(struct isp_device *isp, bool irq)
1405 {
1406 struct isp_device *__isp = isp;
1407
1408 if (isp == NULL)
1409 return NULL;
1410
1411 mutex_lock(&isp->isp_mutex);
1412 if (isp->ref_count > 0)
1413 goto out;
1414
1415 if (isp_enable_clocks(isp) < 0) {
1416 __isp = NULL;
1417 goto out;
1418 }
1419
1420 /* We don't want to restore context before saving it! */
1421 if (isp->has_context)
1422 isp_restore_ctx(isp);
1423
1424 if (irq)
1425 isp_enable_interrupts(isp);
1426
1427 out:
1428 if (__isp != NULL)
1429 isp->ref_count++;
1430 mutex_unlock(&isp->isp_mutex);
1431
1432 return __isp;
1433 }
1434
omap3isp_get(struct isp_device * isp)1435 struct isp_device *omap3isp_get(struct isp_device *isp)
1436 {
1437 return __omap3isp_get(isp, true);
1438 }
1439
1440 /*
1441 * omap3isp_put - Release the ISP
1442 *
1443 * Decrement the reference count on the ISP. If the last reference is released,
1444 * power-down all submodules, disable clocks and free temporary buffers.
1445 */
__omap3isp_put(struct isp_device * isp,bool save_ctx)1446 static void __omap3isp_put(struct isp_device *isp, bool save_ctx)
1447 {
1448 if (isp == NULL)
1449 return;
1450
1451 mutex_lock(&isp->isp_mutex);
1452 BUG_ON(isp->ref_count == 0);
1453 if (--isp->ref_count == 0) {
1454 isp_disable_interrupts(isp);
1455 if (save_ctx) {
1456 isp_save_ctx(isp);
1457 isp->has_context = 1;
1458 }
1459 /* Reset the ISP if an entity has failed to stop. This is the
1460 * only way to recover from such conditions.
1461 */
1462 if (!media_entity_enum_empty(&isp->crashed) ||
1463 isp->stop_failure)
1464 isp_reset(isp);
1465 isp_disable_clocks(isp);
1466 }
1467 mutex_unlock(&isp->isp_mutex);
1468 }
1469
omap3isp_put(struct isp_device * isp)1470 void omap3isp_put(struct isp_device *isp)
1471 {
1472 __omap3isp_put(isp, true);
1473 }
1474
1475 /* --------------------------------------------------------------------------
1476 * Platform device driver
1477 */
1478
1479 /*
1480 * omap3isp_print_status - Prints the values of the ISP Control Module registers
1481 * @isp: OMAP3 ISP device
1482 */
1483 #define ISP_PRINT_REGISTER(isp, name)\
1484 dev_dbg(isp->dev, "###ISP " #name "=0x%08x\n", \
1485 isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_##name))
1486 #define SBL_PRINT_REGISTER(isp, name)\
1487 dev_dbg(isp->dev, "###SBL " #name "=0x%08x\n", \
1488 isp_reg_readl(isp, OMAP3_ISP_IOMEM_SBL, ISPSBL_##name))
1489
omap3isp_print_status(struct isp_device * isp)1490 void omap3isp_print_status(struct isp_device *isp)
1491 {
1492 dev_dbg(isp->dev, "-------------ISP Register dump--------------\n");
1493
1494 ISP_PRINT_REGISTER(isp, SYSCONFIG);
1495 ISP_PRINT_REGISTER(isp, SYSSTATUS);
1496 ISP_PRINT_REGISTER(isp, IRQ0ENABLE);
1497 ISP_PRINT_REGISTER(isp, IRQ0STATUS);
1498 ISP_PRINT_REGISTER(isp, TCTRL_GRESET_LENGTH);
1499 ISP_PRINT_REGISTER(isp, TCTRL_PSTRB_REPLAY);
1500 ISP_PRINT_REGISTER(isp, CTRL);
1501 ISP_PRINT_REGISTER(isp, TCTRL_CTRL);
1502 ISP_PRINT_REGISTER(isp, TCTRL_FRAME);
1503 ISP_PRINT_REGISTER(isp, TCTRL_PSTRB_DELAY);
1504 ISP_PRINT_REGISTER(isp, TCTRL_STRB_DELAY);
1505 ISP_PRINT_REGISTER(isp, TCTRL_SHUT_DELAY);
1506 ISP_PRINT_REGISTER(isp, TCTRL_PSTRB_LENGTH);
1507 ISP_PRINT_REGISTER(isp, TCTRL_STRB_LENGTH);
1508 ISP_PRINT_REGISTER(isp, TCTRL_SHUT_LENGTH);
1509
1510 SBL_PRINT_REGISTER(isp, PCR);
1511 SBL_PRINT_REGISTER(isp, SDR_REQ_EXP);
1512
1513 dev_dbg(isp->dev, "--------------------------------------------\n");
1514 }
1515
1516 #ifdef CONFIG_PM
1517
1518 /*
1519 * Power management support.
1520 *
1521 * As the ISP can't properly handle an input video stream interruption on a non
1522 * frame boundary, the ISP pipelines need to be stopped before sensors get
1523 * suspended. However, as suspending the sensors can require a running clock,
1524 * which can be provided by the ISP, the ISP can't be completely suspended
1525 * before the sensor.
1526 *
1527 * To solve this problem power management support is split into prepare/complete
1528 * and suspend/resume operations. The pipelines are stopped in prepare() and the
1529 * ISP clocks get disabled in suspend(). Similarly, the clocks are re-enabled in
1530 * resume(), and the the pipelines are restarted in complete().
1531 *
1532 * TODO: PM dependencies between the ISP and sensors are not modelled explicitly
1533 * yet.
1534 */
isp_pm_prepare(struct device * dev)1535 static int isp_pm_prepare(struct device *dev)
1536 {
1537 struct isp_device *isp = dev_get_drvdata(dev);
1538 int reset;
1539
1540 WARN_ON(mutex_is_locked(&isp->isp_mutex));
1541
1542 if (isp->ref_count == 0)
1543 return 0;
1544
1545 reset = isp_suspend_modules(isp);
1546 isp_disable_interrupts(isp);
1547 isp_save_ctx(isp);
1548 if (reset)
1549 isp_reset(isp);
1550
1551 return 0;
1552 }
1553
isp_pm_suspend(struct device * dev)1554 static int isp_pm_suspend(struct device *dev)
1555 {
1556 struct isp_device *isp = dev_get_drvdata(dev);
1557
1558 WARN_ON(mutex_is_locked(&isp->isp_mutex));
1559
1560 if (isp->ref_count)
1561 isp_disable_clocks(isp);
1562
1563 return 0;
1564 }
1565
isp_pm_resume(struct device * dev)1566 static int isp_pm_resume(struct device *dev)
1567 {
1568 struct isp_device *isp = dev_get_drvdata(dev);
1569
1570 if (isp->ref_count == 0)
1571 return 0;
1572
1573 return isp_enable_clocks(isp);
1574 }
1575
isp_pm_complete(struct device * dev)1576 static void isp_pm_complete(struct device *dev)
1577 {
1578 struct isp_device *isp = dev_get_drvdata(dev);
1579
1580 if (isp->ref_count == 0)
1581 return;
1582
1583 isp_restore_ctx(isp);
1584 isp_enable_interrupts(isp);
1585 isp_resume_modules(isp);
1586 }
1587
1588 #else
1589
1590 #define isp_pm_prepare NULL
1591 #define isp_pm_suspend NULL
1592 #define isp_pm_resume NULL
1593 #define isp_pm_complete NULL
1594
1595 #endif /* CONFIG_PM */
1596
isp_unregister_entities(struct isp_device * isp)1597 static void isp_unregister_entities(struct isp_device *isp)
1598 {
1599 media_device_unregister(&isp->media_dev);
1600
1601 omap3isp_csi2_unregister_entities(&isp->isp_csi2a);
1602 omap3isp_ccp2_unregister_entities(&isp->isp_ccp2);
1603 omap3isp_ccdc_unregister_entities(&isp->isp_ccdc);
1604 omap3isp_preview_unregister_entities(&isp->isp_prev);
1605 omap3isp_resizer_unregister_entities(&isp->isp_res);
1606 omap3isp_stat_unregister_entities(&isp->isp_aewb);
1607 omap3isp_stat_unregister_entities(&isp->isp_af);
1608 omap3isp_stat_unregister_entities(&isp->isp_hist);
1609
1610 v4l2_device_unregister(&isp->v4l2_dev);
1611 media_device_cleanup(&isp->media_dev);
1612 }
1613
isp_link_entity(struct isp_device * isp,struct media_entity * entity,enum isp_interface_type interface)1614 static int isp_link_entity(
1615 struct isp_device *isp, struct media_entity *entity,
1616 enum isp_interface_type interface)
1617 {
1618 struct media_entity *input;
1619 unsigned int flags;
1620 unsigned int pad;
1621 unsigned int i;
1622
1623 /* Connect the sensor to the correct interface module.
1624 * Parallel sensors are connected directly to the CCDC, while
1625 * serial sensors are connected to the CSI2a, CCP2b or CSI2c
1626 * receiver through CSIPHY1 or CSIPHY2.
1627 */
1628 switch (interface) {
1629 case ISP_INTERFACE_PARALLEL:
1630 input = &isp->isp_ccdc.subdev.entity;
1631 pad = CCDC_PAD_SINK;
1632 flags = 0;
1633 break;
1634
1635 case ISP_INTERFACE_CSI2A_PHY2:
1636 input = &isp->isp_csi2a.subdev.entity;
1637 pad = CSI2_PAD_SINK;
1638 flags = MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED;
1639 break;
1640
1641 case ISP_INTERFACE_CCP2B_PHY1:
1642 case ISP_INTERFACE_CCP2B_PHY2:
1643 input = &isp->isp_ccp2.subdev.entity;
1644 pad = CCP2_PAD_SINK;
1645 flags = 0;
1646 break;
1647
1648 case ISP_INTERFACE_CSI2C_PHY1:
1649 input = &isp->isp_csi2c.subdev.entity;
1650 pad = CSI2_PAD_SINK;
1651 flags = MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED;
1652 break;
1653
1654 default:
1655 dev_err(isp->dev, "%s: invalid interface type %u\n", __func__,
1656 interface);
1657 return -EINVAL;
1658 }
1659
1660 /*
1661 * Not all interfaces are available on all revisions of the
1662 * ISP. The sub-devices of those interfaces aren't initialised
1663 * in such a case. Check this by ensuring the num_pads is
1664 * non-zero.
1665 */
1666 if (!input->num_pads) {
1667 dev_err(isp->dev, "%s: invalid input %u\n", entity->name,
1668 interface);
1669 return -EINVAL;
1670 }
1671
1672 for (i = 0; i < entity->num_pads; i++) {
1673 if (entity->pads[i].flags & MEDIA_PAD_FL_SOURCE)
1674 break;
1675 }
1676 if (i == entity->num_pads) {
1677 dev_err(isp->dev, "%s: no source pad in external entity %s\n",
1678 __func__, entity->name);
1679 return -EINVAL;
1680 }
1681
1682 return media_create_pad_link(entity, i, input, pad, flags);
1683 }
1684
isp_register_entities(struct isp_device * isp)1685 static int isp_register_entities(struct isp_device *isp)
1686 {
1687 int ret;
1688
1689 isp->media_dev.dev = isp->dev;
1690 strscpy(isp->media_dev.model, "TI OMAP3 ISP",
1691 sizeof(isp->media_dev.model));
1692 isp->media_dev.hw_revision = isp->revision;
1693 isp->media_dev.ops = &isp_media_ops;
1694 media_device_init(&isp->media_dev);
1695
1696 isp->v4l2_dev.mdev = &isp->media_dev;
1697 ret = v4l2_device_register(isp->dev, &isp->v4l2_dev);
1698 if (ret < 0) {
1699 dev_err(isp->dev, "%s: V4L2 device registration failed (%d)\n",
1700 __func__, ret);
1701 goto done;
1702 }
1703
1704 /* Register internal entities */
1705 ret = omap3isp_ccp2_register_entities(&isp->isp_ccp2, &isp->v4l2_dev);
1706 if (ret < 0)
1707 goto done;
1708
1709 ret = omap3isp_csi2_register_entities(&isp->isp_csi2a, &isp->v4l2_dev);
1710 if (ret < 0)
1711 goto done;
1712
1713 ret = omap3isp_ccdc_register_entities(&isp->isp_ccdc, &isp->v4l2_dev);
1714 if (ret < 0)
1715 goto done;
1716
1717 ret = omap3isp_preview_register_entities(&isp->isp_prev,
1718 &isp->v4l2_dev);
1719 if (ret < 0)
1720 goto done;
1721
1722 ret = omap3isp_resizer_register_entities(&isp->isp_res, &isp->v4l2_dev);
1723 if (ret < 0)
1724 goto done;
1725
1726 ret = omap3isp_stat_register_entities(&isp->isp_aewb, &isp->v4l2_dev);
1727 if (ret < 0)
1728 goto done;
1729
1730 ret = omap3isp_stat_register_entities(&isp->isp_af, &isp->v4l2_dev);
1731 if (ret < 0)
1732 goto done;
1733
1734 ret = omap3isp_stat_register_entities(&isp->isp_hist, &isp->v4l2_dev);
1735 if (ret < 0)
1736 goto done;
1737
1738 done:
1739 if (ret < 0)
1740 isp_unregister_entities(isp);
1741
1742 return ret;
1743 }
1744
1745 /*
1746 * isp_create_links() - Create links for internal and external ISP entities
1747 * @isp : Pointer to ISP device
1748 *
1749 * This function creates all links between ISP internal and external entities.
1750 *
1751 * Return: A negative error code on failure or zero on success. Possible error
1752 * codes are those returned by media_create_pad_link().
1753 */
isp_create_links(struct isp_device * isp)1754 static int isp_create_links(struct isp_device *isp)
1755 {
1756 int ret;
1757
1758 /* Create links between entities and video nodes. */
1759 ret = media_create_pad_link(
1760 &isp->isp_csi2a.subdev.entity, CSI2_PAD_SOURCE,
1761 &isp->isp_csi2a.video_out.video.entity, 0, 0);
1762 if (ret < 0)
1763 return ret;
1764
1765 ret = media_create_pad_link(
1766 &isp->isp_ccp2.video_in.video.entity, 0,
1767 &isp->isp_ccp2.subdev.entity, CCP2_PAD_SINK, 0);
1768 if (ret < 0)
1769 return ret;
1770
1771 ret = media_create_pad_link(
1772 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_OF,
1773 &isp->isp_ccdc.video_out.video.entity, 0, 0);
1774 if (ret < 0)
1775 return ret;
1776
1777 ret = media_create_pad_link(
1778 &isp->isp_prev.video_in.video.entity, 0,
1779 &isp->isp_prev.subdev.entity, PREV_PAD_SINK, 0);
1780 if (ret < 0)
1781 return ret;
1782
1783 ret = media_create_pad_link(
1784 &isp->isp_prev.subdev.entity, PREV_PAD_SOURCE,
1785 &isp->isp_prev.video_out.video.entity, 0, 0);
1786 if (ret < 0)
1787 return ret;
1788
1789 ret = media_create_pad_link(
1790 &isp->isp_res.video_in.video.entity, 0,
1791 &isp->isp_res.subdev.entity, RESZ_PAD_SINK, 0);
1792 if (ret < 0)
1793 return ret;
1794
1795 ret = media_create_pad_link(
1796 &isp->isp_res.subdev.entity, RESZ_PAD_SOURCE,
1797 &isp->isp_res.video_out.video.entity, 0, 0);
1798
1799 if (ret < 0)
1800 return ret;
1801
1802 /* Create links between entities. */
1803 ret = media_create_pad_link(
1804 &isp->isp_csi2a.subdev.entity, CSI2_PAD_SOURCE,
1805 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SINK, 0);
1806 if (ret < 0)
1807 return ret;
1808
1809 ret = media_create_pad_link(
1810 &isp->isp_ccp2.subdev.entity, CCP2_PAD_SOURCE,
1811 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SINK, 0);
1812 if (ret < 0)
1813 return ret;
1814
1815 ret = media_create_pad_link(
1816 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_VP,
1817 &isp->isp_prev.subdev.entity, PREV_PAD_SINK, 0);
1818 if (ret < 0)
1819 return ret;
1820
1821 ret = media_create_pad_link(
1822 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_OF,
1823 &isp->isp_res.subdev.entity, RESZ_PAD_SINK, 0);
1824 if (ret < 0)
1825 return ret;
1826
1827 ret = media_create_pad_link(
1828 &isp->isp_prev.subdev.entity, PREV_PAD_SOURCE,
1829 &isp->isp_res.subdev.entity, RESZ_PAD_SINK, 0);
1830 if (ret < 0)
1831 return ret;
1832
1833 ret = media_create_pad_link(
1834 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_VP,
1835 &isp->isp_aewb.subdev.entity, 0,
1836 MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE);
1837 if (ret < 0)
1838 return ret;
1839
1840 ret = media_create_pad_link(
1841 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_VP,
1842 &isp->isp_af.subdev.entity, 0,
1843 MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE);
1844 if (ret < 0)
1845 return ret;
1846
1847 ret = media_create_pad_link(
1848 &isp->isp_ccdc.subdev.entity, CCDC_PAD_SOURCE_VP,
1849 &isp->isp_hist.subdev.entity, 0,
1850 MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE);
1851 if (ret < 0)
1852 return ret;
1853
1854 return 0;
1855 }
1856
isp_cleanup_modules(struct isp_device * isp)1857 static void isp_cleanup_modules(struct isp_device *isp)
1858 {
1859 omap3isp_h3a_aewb_cleanup(isp);
1860 omap3isp_h3a_af_cleanup(isp);
1861 omap3isp_hist_cleanup(isp);
1862 omap3isp_resizer_cleanup(isp);
1863 omap3isp_preview_cleanup(isp);
1864 omap3isp_ccdc_cleanup(isp);
1865 omap3isp_ccp2_cleanup(isp);
1866 omap3isp_csi2_cleanup(isp);
1867 omap3isp_csiphy_cleanup(isp);
1868 }
1869
isp_initialize_modules(struct isp_device * isp)1870 static int isp_initialize_modules(struct isp_device *isp)
1871 {
1872 int ret;
1873
1874 ret = omap3isp_csiphy_init(isp);
1875 if (ret < 0) {
1876 dev_err(isp->dev, "CSI PHY initialization failed\n");
1877 return ret;
1878 }
1879
1880 ret = omap3isp_csi2_init(isp);
1881 if (ret < 0) {
1882 dev_err(isp->dev, "CSI2 initialization failed\n");
1883 goto error_csi2;
1884 }
1885
1886 ret = omap3isp_ccp2_init(isp);
1887 if (ret < 0) {
1888 if (ret != -EPROBE_DEFER)
1889 dev_err(isp->dev, "CCP2 initialization failed\n");
1890 goto error_ccp2;
1891 }
1892
1893 ret = omap3isp_ccdc_init(isp);
1894 if (ret < 0) {
1895 dev_err(isp->dev, "CCDC initialization failed\n");
1896 goto error_ccdc;
1897 }
1898
1899 ret = omap3isp_preview_init(isp);
1900 if (ret < 0) {
1901 dev_err(isp->dev, "Preview initialization failed\n");
1902 goto error_preview;
1903 }
1904
1905 ret = omap3isp_resizer_init(isp);
1906 if (ret < 0) {
1907 dev_err(isp->dev, "Resizer initialization failed\n");
1908 goto error_resizer;
1909 }
1910
1911 ret = omap3isp_hist_init(isp);
1912 if (ret < 0) {
1913 dev_err(isp->dev, "Histogram initialization failed\n");
1914 goto error_hist;
1915 }
1916
1917 ret = omap3isp_h3a_aewb_init(isp);
1918 if (ret < 0) {
1919 dev_err(isp->dev, "H3A AEWB initialization failed\n");
1920 goto error_h3a_aewb;
1921 }
1922
1923 ret = omap3isp_h3a_af_init(isp);
1924 if (ret < 0) {
1925 dev_err(isp->dev, "H3A AF initialization failed\n");
1926 goto error_h3a_af;
1927 }
1928
1929 return 0;
1930
1931 error_h3a_af:
1932 omap3isp_h3a_aewb_cleanup(isp);
1933 error_h3a_aewb:
1934 omap3isp_hist_cleanup(isp);
1935 error_hist:
1936 omap3isp_resizer_cleanup(isp);
1937 error_resizer:
1938 omap3isp_preview_cleanup(isp);
1939 error_preview:
1940 omap3isp_ccdc_cleanup(isp);
1941 error_ccdc:
1942 omap3isp_ccp2_cleanup(isp);
1943 error_ccp2:
1944 omap3isp_csi2_cleanup(isp);
1945 error_csi2:
1946 omap3isp_csiphy_cleanup(isp);
1947
1948 return ret;
1949 }
1950
isp_detach_iommu(struct isp_device * isp)1951 static void isp_detach_iommu(struct isp_device *isp)
1952 {
1953 #ifdef CONFIG_ARM_DMA_USE_IOMMU
1954 arm_iommu_detach_device(isp->dev);
1955 arm_iommu_release_mapping(isp->mapping);
1956 isp->mapping = NULL;
1957 #endif
1958 }
1959
isp_attach_iommu(struct isp_device * isp)1960 static int isp_attach_iommu(struct isp_device *isp)
1961 {
1962 #ifdef CONFIG_ARM_DMA_USE_IOMMU
1963 struct dma_iommu_mapping *mapping;
1964 int ret;
1965
1966 /*
1967 * Create the ARM mapping, used by the ARM DMA mapping core to allocate
1968 * VAs. This will allocate a corresponding IOMMU domain.
1969 */
1970 mapping = arm_iommu_create_mapping(&platform_bus_type, SZ_1G, SZ_2G);
1971 if (IS_ERR(mapping)) {
1972 dev_err(isp->dev, "failed to create ARM IOMMU mapping\n");
1973 return PTR_ERR(mapping);
1974 }
1975
1976 isp->mapping = mapping;
1977
1978 /* Attach the ARM VA mapping to the device. */
1979 ret = arm_iommu_attach_device(isp->dev, mapping);
1980 if (ret < 0) {
1981 dev_err(isp->dev, "failed to attach device to VA mapping\n");
1982 goto error;
1983 }
1984
1985 return 0;
1986
1987 error:
1988 arm_iommu_release_mapping(isp->mapping);
1989 isp->mapping = NULL;
1990 return ret;
1991 #else
1992 return -ENODEV;
1993 #endif
1994 }
1995
1996 /*
1997 * isp_remove - Remove ISP platform device
1998 * @pdev: Pointer to ISP platform device
1999 *
2000 * Always returns 0.
2001 */
isp_remove(struct platform_device * pdev)2002 static int isp_remove(struct platform_device *pdev)
2003 {
2004 struct isp_device *isp = platform_get_drvdata(pdev);
2005
2006 v4l2_async_notifier_unregister(&isp->notifier);
2007 isp_unregister_entities(isp);
2008 isp_cleanup_modules(isp);
2009 isp_xclk_cleanup(isp);
2010
2011 __omap3isp_get(isp, false);
2012 isp_detach_iommu(isp);
2013 __omap3isp_put(isp, false);
2014
2015 media_entity_enum_cleanup(&isp->crashed);
2016 v4l2_async_notifier_cleanup(&isp->notifier);
2017
2018 kfree(isp);
2019
2020 return 0;
2021 }
2022
2023 enum isp_of_phy {
2024 ISP_OF_PHY_PARALLEL = 0,
2025 ISP_OF_PHY_CSIPHY1,
2026 ISP_OF_PHY_CSIPHY2,
2027 };
2028
isp_subdev_notifier_complete(struct v4l2_async_notifier * async)2029 static int isp_subdev_notifier_complete(struct v4l2_async_notifier *async)
2030 {
2031 struct isp_device *isp = container_of(async, struct isp_device,
2032 notifier);
2033 struct v4l2_device *v4l2_dev = &isp->v4l2_dev;
2034 struct v4l2_subdev *sd;
2035 int ret;
2036
2037 mutex_lock(&isp->media_dev.graph_mutex);
2038
2039 ret = media_entity_enum_init(&isp->crashed, &isp->media_dev);
2040 if (ret)
2041 return ret;
2042
2043 list_for_each_entry(sd, &v4l2_dev->subdevs, list) {
2044 if (sd->notifier != &isp->notifier)
2045 continue;
2046
2047 ret = isp_link_entity(isp, &sd->entity,
2048 v4l2_subdev_to_bus_cfg(sd)->interface);
2049 if (ret < 0) {
2050 mutex_unlock(&isp->media_dev.graph_mutex);
2051 return ret;
2052 }
2053 }
2054
2055 mutex_unlock(&isp->media_dev.graph_mutex);
2056
2057 ret = v4l2_device_register_subdev_nodes(&isp->v4l2_dev);
2058 if (ret < 0)
2059 return ret;
2060
2061 return media_device_register(&isp->media_dev);
2062 }
2063
isp_parse_of_parallel_endpoint(struct device * dev,struct v4l2_fwnode_endpoint * vep,struct isp_bus_cfg * buscfg)2064 static void isp_parse_of_parallel_endpoint(struct device *dev,
2065 struct v4l2_fwnode_endpoint *vep,
2066 struct isp_bus_cfg *buscfg)
2067 {
2068 buscfg->interface = ISP_INTERFACE_PARALLEL;
2069 buscfg->bus.parallel.data_lane_shift = vep->bus.parallel.data_shift;
2070 buscfg->bus.parallel.clk_pol =
2071 !!(vep->bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_FALLING);
2072 buscfg->bus.parallel.hs_pol =
2073 !!(vep->bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_LOW);
2074 buscfg->bus.parallel.vs_pol =
2075 !!(vep->bus.parallel.flags & V4L2_MBUS_HSYNC_ACTIVE_LOW);
2076 buscfg->bus.parallel.fld_pol =
2077 !!(vep->bus.parallel.flags & V4L2_MBUS_FIELD_EVEN_LOW);
2078 buscfg->bus.parallel.data_pol =
2079 !!(vep->bus.parallel.flags & V4L2_MBUS_DATA_ACTIVE_LOW);
2080 buscfg->bus.parallel.bt656 = vep->bus_type == V4L2_MBUS_BT656;
2081 }
2082
isp_parse_of_csi2_endpoint(struct device * dev,struct v4l2_fwnode_endpoint * vep,struct isp_bus_cfg * buscfg)2083 static void isp_parse_of_csi2_endpoint(struct device *dev,
2084 struct v4l2_fwnode_endpoint *vep,
2085 struct isp_bus_cfg *buscfg)
2086 {
2087 unsigned int i;
2088
2089 buscfg->bus.csi2.lanecfg.clk.pos = vep->bus.mipi_csi2.clock_lane;
2090 buscfg->bus.csi2.lanecfg.clk.pol =
2091 vep->bus.mipi_csi2.lane_polarities[0];
2092 dev_dbg(dev, "clock lane polarity %u, pos %u\n",
2093 buscfg->bus.csi2.lanecfg.clk.pol,
2094 buscfg->bus.csi2.lanecfg.clk.pos);
2095
2096 buscfg->bus.csi2.num_data_lanes = vep->bus.mipi_csi2.num_data_lanes;
2097
2098 for (i = 0; i < buscfg->bus.csi2.num_data_lanes; i++) {
2099 buscfg->bus.csi2.lanecfg.data[i].pos =
2100 vep->bus.mipi_csi2.data_lanes[i];
2101 buscfg->bus.csi2.lanecfg.data[i].pol =
2102 vep->bus.mipi_csi2.lane_polarities[i + 1];
2103 dev_dbg(dev,
2104 "data lane %u polarity %u, pos %u\n", i,
2105 buscfg->bus.csi2.lanecfg.data[i].pol,
2106 buscfg->bus.csi2.lanecfg.data[i].pos);
2107 }
2108 /*
2109 * FIXME: now we assume the CRC is always there. Implement a way to
2110 * obtain this information from the sensor. Frame descriptors, perhaps?
2111 */
2112 buscfg->bus.csi2.crc = 1;
2113 }
2114
isp_parse_of_csi1_endpoint(struct device * dev,struct v4l2_fwnode_endpoint * vep,struct isp_bus_cfg * buscfg)2115 static void isp_parse_of_csi1_endpoint(struct device *dev,
2116 struct v4l2_fwnode_endpoint *vep,
2117 struct isp_bus_cfg *buscfg)
2118 {
2119 buscfg->bus.ccp2.lanecfg.clk.pos = vep->bus.mipi_csi1.clock_lane;
2120 buscfg->bus.ccp2.lanecfg.clk.pol = vep->bus.mipi_csi1.lane_polarity[0];
2121 dev_dbg(dev, "clock lane polarity %u, pos %u\n",
2122 buscfg->bus.ccp2.lanecfg.clk.pol,
2123 buscfg->bus.ccp2.lanecfg.clk.pos);
2124
2125 buscfg->bus.ccp2.lanecfg.data[0].pos = vep->bus.mipi_csi1.data_lane;
2126 buscfg->bus.ccp2.lanecfg.data[0].pol =
2127 vep->bus.mipi_csi1.lane_polarity[1];
2128
2129 dev_dbg(dev, "data lane polarity %u, pos %u\n",
2130 buscfg->bus.ccp2.lanecfg.data[0].pol,
2131 buscfg->bus.ccp2.lanecfg.data[0].pos);
2132
2133 buscfg->bus.ccp2.strobe_clk_pol = vep->bus.mipi_csi1.clock_inv;
2134 buscfg->bus.ccp2.phy_layer = vep->bus.mipi_csi1.strobe;
2135 buscfg->bus.ccp2.ccp2_mode = vep->bus_type == V4L2_MBUS_CCP2;
2136 buscfg->bus.ccp2.vp_clk_pol = 1;
2137
2138 buscfg->bus.ccp2.crc = 1;
2139 }
2140
2141 static struct {
2142 u32 phy;
2143 u32 csi2_if;
2144 u32 csi1_if;
2145 } isp_bus_interfaces[2] = {
2146 { ISP_OF_PHY_CSIPHY1,
2147 ISP_INTERFACE_CSI2C_PHY1, ISP_INTERFACE_CCP2B_PHY1 },
2148 { ISP_OF_PHY_CSIPHY2,
2149 ISP_INTERFACE_CSI2A_PHY2, ISP_INTERFACE_CCP2B_PHY2 },
2150 };
2151
isp_parse_of_endpoints(struct isp_device * isp)2152 static int isp_parse_of_endpoints(struct isp_device *isp)
2153 {
2154 struct fwnode_handle *ep;
2155 struct isp_async_subdev *isd = NULL;
2156 unsigned int i;
2157
2158 ep = fwnode_graph_get_endpoint_by_id(
2159 dev_fwnode(isp->dev), ISP_OF_PHY_PARALLEL, 0,
2160 FWNODE_GRAPH_ENDPOINT_NEXT);
2161
2162 if (ep) {
2163 struct v4l2_fwnode_endpoint vep = {
2164 .bus_type = V4L2_MBUS_PARALLEL
2165 };
2166 int ret;
2167
2168 dev_dbg(isp->dev, "parsing parallel interface\n");
2169
2170 ret = v4l2_fwnode_endpoint_parse(ep, &vep);
2171
2172 if (!ret) {
2173 isd = v4l2_async_notifier_add_fwnode_remote_subdev(
2174 &isp->notifier, ep, struct isp_async_subdev);
2175 if (!IS_ERR(isd))
2176 isp_parse_of_parallel_endpoint(isp->dev, &vep, &isd->bus);
2177 }
2178
2179 fwnode_handle_put(ep);
2180 }
2181
2182 for (i = 0; i < ARRAY_SIZE(isp_bus_interfaces); i++) {
2183 struct v4l2_fwnode_endpoint vep = {
2184 .bus_type = V4L2_MBUS_CSI2_DPHY
2185 };
2186 int ret;
2187
2188 ep = fwnode_graph_get_endpoint_by_id(
2189 dev_fwnode(isp->dev), isp_bus_interfaces[i].phy, 0,
2190 FWNODE_GRAPH_ENDPOINT_NEXT);
2191
2192 if (!ep)
2193 continue;
2194
2195 dev_dbg(isp->dev, "parsing serial interface %u, node %pOF\n", i,
2196 to_of_node(ep));
2197
2198 ret = v4l2_fwnode_endpoint_parse(ep, &vep);
2199 if (ret == -ENXIO) {
2200 vep = (struct v4l2_fwnode_endpoint)
2201 { .bus_type = V4L2_MBUS_CSI1 };
2202 ret = v4l2_fwnode_endpoint_parse(ep, &vep);
2203
2204 if (ret == -ENXIO) {
2205 vep = (struct v4l2_fwnode_endpoint)
2206 { .bus_type = V4L2_MBUS_CCP2 };
2207 ret = v4l2_fwnode_endpoint_parse(ep, &vep);
2208 }
2209 }
2210
2211 if (!ret) {
2212 isd = v4l2_async_notifier_add_fwnode_remote_subdev(
2213 &isp->notifier, ep, struct isp_async_subdev);
2214
2215 if (!IS_ERR(isd)) {
2216 switch (vep.bus_type) {
2217 case V4L2_MBUS_CSI2_DPHY:
2218 isd->bus.interface =
2219 isp_bus_interfaces[i].csi2_if;
2220 isp_parse_of_csi2_endpoint(isp->dev, &vep, &isd->bus);
2221 break;
2222 case V4L2_MBUS_CSI1:
2223 case V4L2_MBUS_CCP2:
2224 isd->bus.interface =
2225 isp_bus_interfaces[i].csi1_if;
2226 isp_parse_of_csi1_endpoint(isp->dev, &vep,
2227 &isd->bus);
2228 break;
2229 default:
2230 break;
2231 }
2232 }
2233 }
2234
2235 fwnode_handle_put(ep);
2236 }
2237
2238 return 0;
2239 }
2240
2241 static const struct v4l2_async_notifier_operations isp_subdev_notifier_ops = {
2242 .complete = isp_subdev_notifier_complete,
2243 };
2244
2245 /*
2246 * isp_probe - Probe ISP platform device
2247 * @pdev: Pointer to ISP platform device
2248 *
2249 * Returns 0 if successful,
2250 * -ENOMEM if no memory available,
2251 * -ENODEV if no platform device resources found
2252 * or no space for remapping registers,
2253 * -EINVAL if couldn't install ISR,
2254 * or clk_get return error value.
2255 */
isp_probe(struct platform_device * pdev)2256 static int isp_probe(struct platform_device *pdev)
2257 {
2258 struct isp_device *isp;
2259 struct resource *mem;
2260 int ret;
2261 int i, m;
2262
2263 isp = kzalloc(sizeof(*isp), GFP_KERNEL);
2264 if (!isp) {
2265 dev_err(&pdev->dev, "could not allocate memory\n");
2266 return -ENOMEM;
2267 }
2268
2269 ret = fwnode_property_read_u32(of_fwnode_handle(pdev->dev.of_node),
2270 "ti,phy-type", &isp->phy_type);
2271 if (ret)
2272 goto error_release_isp;
2273
2274 isp->syscon = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2275 "syscon");
2276 if (IS_ERR(isp->syscon)) {
2277 ret = PTR_ERR(isp->syscon);
2278 goto error_release_isp;
2279 }
2280
2281 ret = of_property_read_u32_index(pdev->dev.of_node,
2282 "syscon", 1, &isp->syscon_offset);
2283 if (ret)
2284 goto error_release_isp;
2285
2286 isp->autoidle = autoidle;
2287
2288 mutex_init(&isp->isp_mutex);
2289 spin_lock_init(&isp->stat_lock);
2290 v4l2_async_notifier_init(&isp->notifier);
2291 isp->dev = &pdev->dev;
2292
2293 ret = isp_parse_of_endpoints(isp);
2294 if (ret < 0)
2295 goto error;
2296
2297 isp->ref_count = 0;
2298
2299 ret = dma_coerce_mask_and_coherent(isp->dev, DMA_BIT_MASK(32));
2300 if (ret)
2301 goto error;
2302
2303 platform_set_drvdata(pdev, isp);
2304
2305 /* Regulators */
2306 isp->isp_csiphy1.vdd = devm_regulator_get(&pdev->dev, "vdd-csiphy1");
2307 isp->isp_csiphy2.vdd = devm_regulator_get(&pdev->dev, "vdd-csiphy2");
2308
2309 /* Clocks
2310 *
2311 * The ISP clock tree is revision-dependent. We thus need to enable ICLK
2312 * manually to read the revision before calling __omap3isp_get().
2313 *
2314 * Start by mapping the ISP MMIO area, which is in two pieces.
2315 * The ISP IOMMU is in between. Map both now, and fill in the
2316 * ISP revision specific portions a little later in the
2317 * function.
2318 */
2319 for (i = 0; i < 2; i++) {
2320 unsigned int map_idx = i ? OMAP3_ISP_IOMEM_CSI2A_REGS1 : 0;
2321
2322 mem = platform_get_resource(pdev, IORESOURCE_MEM, i);
2323 isp->mmio_base[map_idx] =
2324 devm_ioremap_resource(isp->dev, mem);
2325 if (IS_ERR(isp->mmio_base[map_idx])) {
2326 ret = PTR_ERR(isp->mmio_base[map_idx]);
2327 goto error;
2328 }
2329 }
2330
2331 ret = isp_get_clocks(isp);
2332 if (ret < 0)
2333 goto error;
2334
2335 ret = clk_enable(isp->clock[ISP_CLK_CAM_ICK]);
2336 if (ret < 0)
2337 goto error;
2338
2339 isp->revision = isp_reg_readl(isp, OMAP3_ISP_IOMEM_MAIN, ISP_REVISION);
2340 dev_info(isp->dev, "Revision %d.%d found\n",
2341 (isp->revision & 0xf0) >> 4, isp->revision & 0x0f);
2342
2343 clk_disable(isp->clock[ISP_CLK_CAM_ICK]);
2344
2345 if (__omap3isp_get(isp, false) == NULL) {
2346 ret = -ENODEV;
2347 goto error;
2348 }
2349
2350 ret = isp_reset(isp);
2351 if (ret < 0)
2352 goto error_isp;
2353
2354 ret = isp_xclk_init(isp);
2355 if (ret < 0)
2356 goto error_isp;
2357
2358 /* Memory resources */
2359 for (m = 0; m < ARRAY_SIZE(isp_res_maps); m++)
2360 if (isp->revision == isp_res_maps[m].isp_rev)
2361 break;
2362
2363 if (m == ARRAY_SIZE(isp_res_maps)) {
2364 dev_err(isp->dev, "No resource map found for ISP rev %d.%d\n",
2365 (isp->revision & 0xf0) >> 4, isp->revision & 0xf);
2366 ret = -ENODEV;
2367 goto error_isp;
2368 }
2369
2370 for (i = 1; i < OMAP3_ISP_IOMEM_CSI2A_REGS1; i++)
2371 isp->mmio_base[i] =
2372 isp->mmio_base[0] + isp_res_maps[m].offset[i];
2373
2374 for (i = OMAP3_ISP_IOMEM_CSIPHY2; i < OMAP3_ISP_IOMEM_LAST; i++)
2375 isp->mmio_base[i] =
2376 isp->mmio_base[OMAP3_ISP_IOMEM_CSI2A_REGS1]
2377 + isp_res_maps[m].offset[i];
2378
2379 isp->mmio_hist_base_phys =
2380 mem->start + isp_res_maps[m].offset[OMAP3_ISP_IOMEM_HIST];
2381
2382 /* IOMMU */
2383 ret = isp_attach_iommu(isp);
2384 if (ret < 0) {
2385 dev_err(&pdev->dev, "unable to attach to IOMMU\n");
2386 goto error_isp;
2387 }
2388
2389 /* Interrupt */
2390 ret = platform_get_irq(pdev, 0);
2391 if (ret <= 0) {
2392 ret = -ENODEV;
2393 goto error_iommu;
2394 }
2395 isp->irq_num = ret;
2396
2397 if (devm_request_irq(isp->dev, isp->irq_num, isp_isr, IRQF_SHARED,
2398 "OMAP3 ISP", isp)) {
2399 dev_err(isp->dev, "Unable to request IRQ\n");
2400 ret = -EINVAL;
2401 goto error_iommu;
2402 }
2403
2404 /* Entities */
2405 ret = isp_initialize_modules(isp);
2406 if (ret < 0)
2407 goto error_iommu;
2408
2409 ret = isp_register_entities(isp);
2410 if (ret < 0)
2411 goto error_modules;
2412
2413 ret = isp_create_links(isp);
2414 if (ret < 0)
2415 goto error_register_entities;
2416
2417 isp->notifier.ops = &isp_subdev_notifier_ops;
2418
2419 ret = v4l2_async_notifier_register(&isp->v4l2_dev, &isp->notifier);
2420 if (ret)
2421 goto error_register_entities;
2422
2423 isp_core_init(isp, 1);
2424 omap3isp_put(isp);
2425
2426 return 0;
2427
2428 error_register_entities:
2429 isp_unregister_entities(isp);
2430 error_modules:
2431 isp_cleanup_modules(isp);
2432 error_iommu:
2433 isp_detach_iommu(isp);
2434 error_isp:
2435 isp_xclk_cleanup(isp);
2436 __omap3isp_put(isp, false);
2437 error:
2438 v4l2_async_notifier_cleanup(&isp->notifier);
2439 mutex_destroy(&isp->isp_mutex);
2440 error_release_isp:
2441 kfree(isp);
2442
2443 return ret;
2444 }
2445
2446 static const struct dev_pm_ops omap3isp_pm_ops = {
2447 .prepare = isp_pm_prepare,
2448 .suspend = isp_pm_suspend,
2449 .resume = isp_pm_resume,
2450 .complete = isp_pm_complete,
2451 };
2452
2453 static const struct platform_device_id omap3isp_id_table[] = {
2454 { "omap3isp", 0 },
2455 { },
2456 };
2457 MODULE_DEVICE_TABLE(platform, omap3isp_id_table);
2458
2459 static const struct of_device_id omap3isp_of_table[] = {
2460 { .compatible = "ti,omap3-isp" },
2461 { },
2462 };
2463 MODULE_DEVICE_TABLE(of, omap3isp_of_table);
2464
2465 static struct platform_driver omap3isp_driver = {
2466 .probe = isp_probe,
2467 .remove = isp_remove,
2468 .id_table = omap3isp_id_table,
2469 .driver = {
2470 .name = "omap3isp",
2471 .pm = &omap3isp_pm_ops,
2472 .of_match_table = omap3isp_of_table,
2473 },
2474 };
2475
2476 module_platform_driver(omap3isp_driver);
2477
2478 MODULE_AUTHOR("Nokia Corporation");
2479 MODULE_DESCRIPTION("TI OMAP3 ISP driver");
2480 MODULE_LICENSE("GPL");
2481 MODULE_VERSION(ISP_VIDEO_DRIVER_VERSION);
2482