1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Marvell 88e6xxx Ethernet switch single-chip support
4 *
5 * Copyright (c) 2008 Marvell Semiconductor
6 *
7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
8 *
9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
11 */
12
13 #include <linux/bitfield.h>
14 #include <linux/delay.h>
15 #include <linux/etherdevice.h>
16 #include <linux/ethtool.h>
17 #include <linux/if_bridge.h>
18 #include <linux/interrupt.h>
19 #include <linux/irq.h>
20 #include <linux/irqdomain.h>
21 #include <linux/jiffies.h>
22 #include <linux/list.h>
23 #include <linux/mdio.h>
24 #include <linux/module.h>
25 #include <linux/of_device.h>
26 #include <linux/of_irq.h>
27 #include <linux/of_mdio.h>
28 #include <linux/platform_data/mv88e6xxx.h>
29 #include <linux/netdevice.h>
30 #include <linux/gpio/consumer.h>
31 #include <linux/phylink.h>
32 #include <net/dsa.h>
33
34 #include "chip.h"
35 #include "devlink.h"
36 #include "global1.h"
37 #include "global2.h"
38 #include "hwtstamp.h"
39 #include "phy.h"
40 #include "port.h"
41 #include "ptp.h"
42 #include "serdes.h"
43 #include "smi.h"
44
assert_reg_lock(struct mv88e6xxx_chip * chip)45 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
46 {
47 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
48 dev_err(chip->dev, "Switch registers lock not held!\n");
49 dump_stack();
50 }
51 }
52
mv88e6xxx_read(struct mv88e6xxx_chip * chip,int addr,int reg,u16 * val)53 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
54 {
55 int err;
56
57 assert_reg_lock(chip);
58
59 err = mv88e6xxx_smi_read(chip, addr, reg, val);
60 if (err)
61 return err;
62
63 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
64 addr, reg, *val);
65
66 return 0;
67 }
68
mv88e6xxx_write(struct mv88e6xxx_chip * chip,int addr,int reg,u16 val)69 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
70 {
71 int err;
72
73 assert_reg_lock(chip);
74
75 err = mv88e6xxx_smi_write(chip, addr, reg, val);
76 if (err)
77 return err;
78
79 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
80 addr, reg, val);
81
82 return 0;
83 }
84
mv88e6xxx_wait_mask(struct mv88e6xxx_chip * chip,int addr,int reg,u16 mask,u16 val)85 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
86 u16 mask, u16 val)
87 {
88 u16 data;
89 int err;
90 int i;
91
92 /* There's no bus specific operation to wait for a mask */
93 for (i = 0; i < 16; i++) {
94 err = mv88e6xxx_read(chip, addr, reg, &data);
95 if (err)
96 return err;
97
98 if ((data & mask) == val)
99 return 0;
100
101 usleep_range(1000, 2000);
102 }
103
104 dev_err(chip->dev, "Timeout while waiting for switch\n");
105 return -ETIMEDOUT;
106 }
107
mv88e6xxx_wait_bit(struct mv88e6xxx_chip * chip,int addr,int reg,int bit,int val)108 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
109 int bit, int val)
110 {
111 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit),
112 val ? BIT(bit) : 0x0000);
113 }
114
mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip * chip)115 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
116 {
117 struct mv88e6xxx_mdio_bus *mdio_bus;
118
119 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
120 list);
121 if (!mdio_bus)
122 return NULL;
123
124 return mdio_bus->bus;
125 }
126
mv88e6xxx_g1_irq_mask(struct irq_data * d)127 static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
128 {
129 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
130 unsigned int n = d->hwirq;
131
132 chip->g1_irq.masked |= (1 << n);
133 }
134
mv88e6xxx_g1_irq_unmask(struct irq_data * d)135 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
136 {
137 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
138 unsigned int n = d->hwirq;
139
140 chip->g1_irq.masked &= ~(1 << n);
141 }
142
mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip * chip)143 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
144 {
145 unsigned int nhandled = 0;
146 unsigned int sub_irq;
147 unsigned int n;
148 u16 reg;
149 u16 ctl1;
150 int err;
151
152 mv88e6xxx_reg_lock(chip);
153 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
154 mv88e6xxx_reg_unlock(chip);
155
156 if (err)
157 goto out;
158
159 do {
160 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
161 if (reg & (1 << n)) {
162 sub_irq = irq_find_mapping(chip->g1_irq.domain,
163 n);
164 handle_nested_irq(sub_irq);
165 ++nhandled;
166 }
167 }
168
169 mv88e6xxx_reg_lock(chip);
170 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1);
171 if (err)
172 goto unlock;
173 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
174 unlock:
175 mv88e6xxx_reg_unlock(chip);
176 if (err)
177 goto out;
178 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
179 } while (reg & ctl1);
180
181 out:
182 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
183 }
184
mv88e6xxx_g1_irq_thread_fn(int irq,void * dev_id)185 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
186 {
187 struct mv88e6xxx_chip *chip = dev_id;
188
189 return mv88e6xxx_g1_irq_thread_work(chip);
190 }
191
mv88e6xxx_g1_irq_bus_lock(struct irq_data * d)192 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
193 {
194 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
195
196 mv88e6xxx_reg_lock(chip);
197 }
198
mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data * d)199 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
200 {
201 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
202 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
203 u16 reg;
204 int err;
205
206 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®);
207 if (err)
208 goto out;
209
210 reg &= ~mask;
211 reg |= (~chip->g1_irq.masked & mask);
212
213 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
214 if (err)
215 goto out;
216
217 out:
218 mv88e6xxx_reg_unlock(chip);
219 }
220
221 static const struct irq_chip mv88e6xxx_g1_irq_chip = {
222 .name = "mv88e6xxx-g1",
223 .irq_mask = mv88e6xxx_g1_irq_mask,
224 .irq_unmask = mv88e6xxx_g1_irq_unmask,
225 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
226 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
227 };
228
mv88e6xxx_g1_irq_domain_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hwirq)229 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
230 unsigned int irq,
231 irq_hw_number_t hwirq)
232 {
233 struct mv88e6xxx_chip *chip = d->host_data;
234
235 irq_set_chip_data(irq, d->host_data);
236 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
237 irq_set_noprobe(irq);
238
239 return 0;
240 }
241
242 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
243 .map = mv88e6xxx_g1_irq_domain_map,
244 .xlate = irq_domain_xlate_twocell,
245 };
246
247 /* To be called with reg_lock held */
mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip * chip)248 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
249 {
250 int irq, virq;
251 u16 mask;
252
253 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
254 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
255 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
256
257 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
258 virq = irq_find_mapping(chip->g1_irq.domain, irq);
259 irq_dispose_mapping(virq);
260 }
261
262 irq_domain_remove(chip->g1_irq.domain);
263 }
264
mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip * chip)265 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
266 {
267 /*
268 * free_irq must be called without reg_lock taken because the irq
269 * handler takes this lock, too.
270 */
271 free_irq(chip->irq, chip);
272
273 mv88e6xxx_reg_lock(chip);
274 mv88e6xxx_g1_irq_free_common(chip);
275 mv88e6xxx_reg_unlock(chip);
276 }
277
mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip * chip)278 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
279 {
280 int err, irq, virq;
281 u16 reg, mask;
282
283 chip->g1_irq.nirqs = chip->info->g1_irqs;
284 chip->g1_irq.domain = irq_domain_add_simple(
285 NULL, chip->g1_irq.nirqs, 0,
286 &mv88e6xxx_g1_irq_domain_ops, chip);
287 if (!chip->g1_irq.domain)
288 return -ENOMEM;
289
290 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
291 irq_create_mapping(chip->g1_irq.domain, irq);
292
293 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
294 chip->g1_irq.masked = ~0;
295
296 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
297 if (err)
298 goto out_mapping;
299
300 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
301
302 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
303 if (err)
304 goto out_disable;
305
306 /* Reading the interrupt status clears (most of) them */
307 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
308 if (err)
309 goto out_disable;
310
311 return 0;
312
313 out_disable:
314 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
315 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
316
317 out_mapping:
318 for (irq = 0; irq < 16; irq++) {
319 virq = irq_find_mapping(chip->g1_irq.domain, irq);
320 irq_dispose_mapping(virq);
321 }
322
323 irq_domain_remove(chip->g1_irq.domain);
324
325 return err;
326 }
327
mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip * chip)328 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
329 {
330 static struct lock_class_key lock_key;
331 static struct lock_class_key request_key;
332 int err;
333
334 err = mv88e6xxx_g1_irq_setup_common(chip);
335 if (err)
336 return err;
337
338 /* These lock classes tells lockdep that global 1 irqs are in
339 * a different category than their parent GPIO, so it won't
340 * report false recursion.
341 */
342 irq_set_lockdep_class(chip->irq, &lock_key, &request_key);
343
344 snprintf(chip->irq_name, sizeof(chip->irq_name),
345 "mv88e6xxx-%s", dev_name(chip->dev));
346
347 mv88e6xxx_reg_unlock(chip);
348 err = request_threaded_irq(chip->irq, NULL,
349 mv88e6xxx_g1_irq_thread_fn,
350 IRQF_ONESHOT | IRQF_SHARED,
351 chip->irq_name, chip);
352 mv88e6xxx_reg_lock(chip);
353 if (err)
354 mv88e6xxx_g1_irq_free_common(chip);
355
356 return err;
357 }
358
mv88e6xxx_irq_poll(struct kthread_work * work)359 static void mv88e6xxx_irq_poll(struct kthread_work *work)
360 {
361 struct mv88e6xxx_chip *chip = container_of(work,
362 struct mv88e6xxx_chip,
363 irq_poll_work.work);
364 mv88e6xxx_g1_irq_thread_work(chip);
365
366 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
367 msecs_to_jiffies(100));
368 }
369
mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip * chip)370 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
371 {
372 int err;
373
374 err = mv88e6xxx_g1_irq_setup_common(chip);
375 if (err)
376 return err;
377
378 kthread_init_delayed_work(&chip->irq_poll_work,
379 mv88e6xxx_irq_poll);
380
381 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev));
382 if (IS_ERR(chip->kworker))
383 return PTR_ERR(chip->kworker);
384
385 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
386 msecs_to_jiffies(100));
387
388 return 0;
389 }
390
mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip * chip)391 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
392 {
393 kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
394 kthread_destroy_worker(chip->kworker);
395
396 mv88e6xxx_reg_lock(chip);
397 mv88e6xxx_g1_irq_free_common(chip);
398 mv88e6xxx_reg_unlock(chip);
399 }
400
mv88e6xxx_port_config_interface(struct mv88e6xxx_chip * chip,int port,phy_interface_t interface)401 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip,
402 int port, phy_interface_t interface)
403 {
404 int err;
405
406 if (chip->info->ops->port_set_rgmii_delay) {
407 err = chip->info->ops->port_set_rgmii_delay(chip, port,
408 interface);
409 if (err && err != -EOPNOTSUPP)
410 return err;
411 }
412
413 if (chip->info->ops->port_set_cmode) {
414 err = chip->info->ops->port_set_cmode(chip, port,
415 interface);
416 if (err && err != -EOPNOTSUPP)
417 return err;
418 }
419
420 return 0;
421 }
422
mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip * chip,int port,int link,int speed,int duplex,int pause,phy_interface_t mode)423 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
424 int link, int speed, int duplex, int pause,
425 phy_interface_t mode)
426 {
427 int err;
428
429 if (!chip->info->ops->port_set_link)
430 return 0;
431
432 /* Port's MAC control must not be changed unless the link is down */
433 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
434 if (err)
435 return err;
436
437 if (chip->info->ops->port_set_speed_duplex) {
438 err = chip->info->ops->port_set_speed_duplex(chip, port,
439 speed, duplex);
440 if (err && err != -EOPNOTSUPP)
441 goto restore_link;
442 }
443
444 if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode)
445 mode = chip->info->ops->port_max_speed_mode(port);
446
447 if (chip->info->ops->port_set_pause) {
448 err = chip->info->ops->port_set_pause(chip, port, pause);
449 if (err)
450 goto restore_link;
451 }
452
453 err = mv88e6xxx_port_config_interface(chip, port, mode);
454 restore_link:
455 if (chip->info->ops->port_set_link(chip, port, link))
456 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
457
458 return err;
459 }
460
mv88e6xxx_phy_is_internal(struct dsa_switch * ds,int port)461 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port)
462 {
463 struct mv88e6xxx_chip *chip = ds->priv;
464
465 return port < chip->info->num_internal_phys;
466 }
467
mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip * chip,int port)468 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)
469 {
470 u16 reg;
471 int err;
472
473 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
474 if (err) {
475 dev_err(chip->dev,
476 "p%d: %s: failed to read port status\n",
477 port, __func__);
478 return err;
479 }
480
481 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT);
482 }
483
mv88e6xxx_serdes_pcs_get_state(struct dsa_switch * ds,int port,struct phylink_link_state * state)484 static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port,
485 struct phylink_link_state *state)
486 {
487 struct mv88e6xxx_chip *chip = ds->priv;
488 int lane;
489 int err;
490
491 mv88e6xxx_reg_lock(chip);
492 lane = mv88e6xxx_serdes_get_lane(chip, port);
493 if (lane >= 0 && chip->info->ops->serdes_pcs_get_state)
494 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane,
495 state);
496 else
497 err = -EOPNOTSUPP;
498 mv88e6xxx_reg_unlock(chip);
499
500 return err;
501 }
502
mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip * chip,int port,unsigned int mode,phy_interface_t interface,const unsigned long * advertise)503 static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port,
504 unsigned int mode,
505 phy_interface_t interface,
506 const unsigned long *advertise)
507 {
508 const struct mv88e6xxx_ops *ops = chip->info->ops;
509 int lane;
510
511 if (ops->serdes_pcs_config) {
512 lane = mv88e6xxx_serdes_get_lane(chip, port);
513 if (lane >= 0)
514 return ops->serdes_pcs_config(chip, port, lane, mode,
515 interface, advertise);
516 }
517
518 return 0;
519 }
520
mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch * ds,int port)521 static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port)
522 {
523 struct mv88e6xxx_chip *chip = ds->priv;
524 const struct mv88e6xxx_ops *ops;
525 int err = 0;
526 int lane;
527
528 ops = chip->info->ops;
529
530 if (ops->serdes_pcs_an_restart) {
531 mv88e6xxx_reg_lock(chip);
532 lane = mv88e6xxx_serdes_get_lane(chip, port);
533 if (lane >= 0)
534 err = ops->serdes_pcs_an_restart(chip, port, lane);
535 mv88e6xxx_reg_unlock(chip);
536
537 if (err)
538 dev_err(ds->dev, "p%d: failed to restart AN\n", port);
539 }
540 }
541
mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip * chip,int port,unsigned int mode,int speed,int duplex)542 static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port,
543 unsigned int mode,
544 int speed, int duplex)
545 {
546 const struct mv88e6xxx_ops *ops = chip->info->ops;
547 int lane;
548
549 if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) {
550 lane = mv88e6xxx_serdes_get_lane(chip, port);
551 if (lane >= 0)
552 return ops->serdes_pcs_link_up(chip, port, lane,
553 speed, duplex);
554 }
555
556 return 0;
557 }
558
mv88e6065_phylink_validate(struct mv88e6xxx_chip * chip,int port,unsigned long * mask,struct phylink_link_state * state)559 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port,
560 unsigned long *mask,
561 struct phylink_link_state *state)
562 {
563 if (!phy_interface_mode_is_8023z(state->interface)) {
564 /* 10M and 100M are only supported in non-802.3z mode */
565 phylink_set(mask, 10baseT_Half);
566 phylink_set(mask, 10baseT_Full);
567 phylink_set(mask, 100baseT_Half);
568 phylink_set(mask, 100baseT_Full);
569 }
570 }
571
mv88e6185_phylink_validate(struct mv88e6xxx_chip * chip,int port,unsigned long * mask,struct phylink_link_state * state)572 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port,
573 unsigned long *mask,
574 struct phylink_link_state *state)
575 {
576 /* FIXME: if the port is in 1000Base-X mode, then it only supports
577 * 1000M FD speeds. In this case, CMODE will indicate 5.
578 */
579 phylink_set(mask, 1000baseT_Full);
580 phylink_set(mask, 1000baseX_Full);
581
582 mv88e6065_phylink_validate(chip, port, mask, state);
583 }
584
mv88e6341_phylink_validate(struct mv88e6xxx_chip * chip,int port,unsigned long * mask,struct phylink_link_state * state)585 static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port,
586 unsigned long *mask,
587 struct phylink_link_state *state)
588 {
589 if (port >= 5)
590 phylink_set(mask, 2500baseX_Full);
591
592 /* No ethtool bits for 200Mbps */
593 phylink_set(mask, 1000baseT_Full);
594 phylink_set(mask, 1000baseX_Full);
595
596 mv88e6065_phylink_validate(chip, port, mask, state);
597 }
598
mv88e6352_phylink_validate(struct mv88e6xxx_chip * chip,int port,unsigned long * mask,struct phylink_link_state * state)599 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port,
600 unsigned long *mask,
601 struct phylink_link_state *state)
602 {
603 /* No ethtool bits for 200Mbps */
604 phylink_set(mask, 1000baseT_Full);
605 phylink_set(mask, 1000baseX_Full);
606
607 mv88e6065_phylink_validate(chip, port, mask, state);
608 }
609
mv88e6390_phylink_validate(struct mv88e6xxx_chip * chip,int port,unsigned long * mask,struct phylink_link_state * state)610 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port,
611 unsigned long *mask,
612 struct phylink_link_state *state)
613 {
614 if (port >= 9) {
615 phylink_set(mask, 2500baseX_Full);
616 phylink_set(mask, 2500baseT_Full);
617 }
618
619 /* No ethtool bits for 200Mbps */
620 phylink_set(mask, 1000baseT_Full);
621 phylink_set(mask, 1000baseX_Full);
622
623 mv88e6065_phylink_validate(chip, port, mask, state);
624 }
625
mv88e6390x_phylink_validate(struct mv88e6xxx_chip * chip,int port,unsigned long * mask,struct phylink_link_state * state)626 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port,
627 unsigned long *mask,
628 struct phylink_link_state *state)
629 {
630 if (port >= 9) {
631 phylink_set(mask, 10000baseT_Full);
632 phylink_set(mask, 10000baseKR_Full);
633 }
634
635 mv88e6390_phylink_validate(chip, port, mask, state);
636 }
637
mv88e6393x_phylink_validate(struct mv88e6xxx_chip * chip,int port,unsigned long * mask,struct phylink_link_state * state)638 static void mv88e6393x_phylink_validate(struct mv88e6xxx_chip *chip, int port,
639 unsigned long *mask,
640 struct phylink_link_state *state)
641 {
642 if (port == 0 || port == 9 || port == 10) {
643 phylink_set(mask, 10000baseT_Full);
644 phylink_set(mask, 10000baseKR_Full);
645 phylink_set(mask, 10000baseCR_Full);
646 phylink_set(mask, 10000baseSR_Full);
647 phylink_set(mask, 10000baseLR_Full);
648 phylink_set(mask, 10000baseLRM_Full);
649 phylink_set(mask, 10000baseER_Full);
650 phylink_set(mask, 5000baseT_Full);
651 phylink_set(mask, 2500baseX_Full);
652 phylink_set(mask, 2500baseT_Full);
653 }
654
655 phylink_set(mask, 1000baseT_Full);
656 phylink_set(mask, 1000baseX_Full);
657
658 mv88e6065_phylink_validate(chip, port, mask, state);
659 }
660
mv88e6xxx_validate(struct dsa_switch * ds,int port,unsigned long * supported,struct phylink_link_state * state)661 static void mv88e6xxx_validate(struct dsa_switch *ds, int port,
662 unsigned long *supported,
663 struct phylink_link_state *state)
664 {
665 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
666 struct mv88e6xxx_chip *chip = ds->priv;
667
668 /* Allow all the expected bits */
669 phylink_set(mask, Autoneg);
670 phylink_set(mask, Pause);
671 phylink_set_port_modes(mask);
672
673 if (chip->info->ops->phylink_validate)
674 chip->info->ops->phylink_validate(chip, port, mask, state);
675
676 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
677 bitmap_and(state->advertising, state->advertising, mask,
678 __ETHTOOL_LINK_MODE_MASK_NBITS);
679
680 /* We can only operate at 2500BaseX or 1000BaseX. If requested
681 * to advertise both, only report advertising at 2500BaseX.
682 */
683 phylink_helper_basex_speed(state);
684 }
685
mv88e6xxx_mac_config(struct dsa_switch * ds,int port,unsigned int mode,const struct phylink_link_state * state)686 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port,
687 unsigned int mode,
688 const struct phylink_link_state *state)
689 {
690 struct mv88e6xxx_chip *chip = ds->priv;
691 struct mv88e6xxx_port *p;
692 int err;
693
694 p = &chip->ports[port];
695
696 /* FIXME: is this the correct test? If we're in fixed mode on an
697 * internal port, why should we process this any different from
698 * PHY mode? On the other hand, the port may be automedia between
699 * an internal PHY and the serdes...
700 */
701 if ((mode == MLO_AN_PHY) && mv88e6xxx_phy_is_internal(ds, port))
702 return;
703
704 mv88e6xxx_reg_lock(chip);
705 /* In inband mode, the link may come up at any time while the link
706 * is not forced down. Force the link down while we reconfigure the
707 * interface mode.
708 */
709 if (mode == MLO_AN_INBAND && p->interface != state->interface &&
710 chip->info->ops->port_set_link)
711 chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
712
713 err = mv88e6xxx_port_config_interface(chip, port, state->interface);
714 if (err && err != -EOPNOTSUPP)
715 goto err_unlock;
716
717 err = mv88e6xxx_serdes_pcs_config(chip, port, mode, state->interface,
718 state->advertising);
719 /* FIXME: we should restart negotiation if something changed - which
720 * is something we get if we convert to using phylinks PCS operations.
721 */
722 if (err > 0)
723 err = 0;
724
725 /* Undo the forced down state above after completing configuration
726 * irrespective of its state on entry, which allows the link to come up.
727 */
728 if (mode == MLO_AN_INBAND && p->interface != state->interface &&
729 chip->info->ops->port_set_link)
730 chip->info->ops->port_set_link(chip, port, LINK_UNFORCED);
731
732 p->interface = state->interface;
733
734 err_unlock:
735 mv88e6xxx_reg_unlock(chip);
736
737 if (err && err != -EOPNOTSUPP)
738 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port);
739 }
740
mv88e6xxx_mac_link_down(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface)741 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port,
742 unsigned int mode,
743 phy_interface_t interface)
744 {
745 struct mv88e6xxx_chip *chip = ds->priv;
746 const struct mv88e6xxx_ops *ops;
747 int err = 0;
748
749 ops = chip->info->ops;
750
751 mv88e6xxx_reg_lock(chip);
752 if ((!mv88e6xxx_port_ppu_updates(chip, port) ||
753 mode == MLO_AN_FIXED) && ops->port_sync_link)
754 err = ops->port_sync_link(chip, port, mode, false);
755 mv88e6xxx_reg_unlock(chip);
756
757 if (err)
758 dev_err(chip->dev,
759 "p%d: failed to force MAC link down\n", port);
760 }
761
mv88e6xxx_mac_link_up(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface,struct phy_device * phydev,int speed,int duplex,bool tx_pause,bool rx_pause)762 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port,
763 unsigned int mode, phy_interface_t interface,
764 struct phy_device *phydev,
765 int speed, int duplex,
766 bool tx_pause, bool rx_pause)
767 {
768 struct mv88e6xxx_chip *chip = ds->priv;
769 const struct mv88e6xxx_ops *ops;
770 int err = 0;
771
772 ops = chip->info->ops;
773
774 mv88e6xxx_reg_lock(chip);
775 if (!mv88e6xxx_port_ppu_updates(chip, port) || mode == MLO_AN_FIXED) {
776 /* FIXME: for an automedia port, should we force the link
777 * down here - what if the link comes up due to "other" media
778 * while we're bringing the port up, how is the exclusivity
779 * handled in the Marvell hardware? E.g. port 2 on 88E6390
780 * shared between internal PHY and Serdes.
781 */
782 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed,
783 duplex);
784 if (err)
785 goto error;
786
787 if (ops->port_set_speed_duplex) {
788 err = ops->port_set_speed_duplex(chip, port,
789 speed, duplex);
790 if (err && err != -EOPNOTSUPP)
791 goto error;
792 }
793
794 if (ops->port_sync_link)
795 err = ops->port_sync_link(chip, port, mode, true);
796 }
797 error:
798 mv88e6xxx_reg_unlock(chip);
799
800 if (err && err != -EOPNOTSUPP)
801 dev_err(ds->dev,
802 "p%d: failed to configure MAC link up\n", port);
803 }
804
mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip * chip,int port)805 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
806 {
807 if (!chip->info->ops->stats_snapshot)
808 return -EOPNOTSUPP;
809
810 return chip->info->ops->stats_snapshot(chip, port);
811 }
812
813 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
814 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
815 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
816 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
817 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
818 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
819 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
820 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
821 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
822 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
823 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
824 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
825 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
826 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
827 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
828 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
829 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
830 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
831 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
832 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
833 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
834 { "single", 4, 0x14, STATS_TYPE_BANK0, },
835 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
836 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
837 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
838 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
839 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
840 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
841 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
842 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
843 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
844 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
845 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
846 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
847 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
848 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
849 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
850 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
851 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
852 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
853 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
854 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
855 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
856 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
857 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
858 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
859 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
860 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
861 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
862 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
863 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
864 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
865 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
866 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
867 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
868 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
869 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
870 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
871 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
872 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
873 };
874
_mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip * chip,struct mv88e6xxx_hw_stat * s,int port,u16 bank1_select,u16 histogram)875 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
876 struct mv88e6xxx_hw_stat *s,
877 int port, u16 bank1_select,
878 u16 histogram)
879 {
880 u32 low;
881 u32 high = 0;
882 u16 reg = 0;
883 int err;
884 u64 value;
885
886 switch (s->type) {
887 case STATS_TYPE_PORT:
888 err = mv88e6xxx_port_read(chip, port, s->reg, ®);
889 if (err)
890 return U64_MAX;
891
892 low = reg;
893 if (s->size == 4) {
894 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®);
895 if (err)
896 return U64_MAX;
897 low |= ((u32)reg) << 16;
898 }
899 break;
900 case STATS_TYPE_BANK1:
901 reg = bank1_select;
902 fallthrough;
903 case STATS_TYPE_BANK0:
904 reg |= s->reg | histogram;
905 mv88e6xxx_g1_stats_read(chip, reg, &low);
906 if (s->size == 8)
907 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
908 break;
909 default:
910 return U64_MAX;
911 }
912 value = (((u64)high) << 32) | low;
913 return value;
914 }
915
mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip * chip,uint8_t * data,int types)916 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
917 uint8_t *data, int types)
918 {
919 struct mv88e6xxx_hw_stat *stat;
920 int i, j;
921
922 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
923 stat = &mv88e6xxx_hw_stats[i];
924 if (stat->type & types) {
925 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
926 ETH_GSTRING_LEN);
927 j++;
928 }
929 }
930
931 return j;
932 }
933
mv88e6095_stats_get_strings(struct mv88e6xxx_chip * chip,uint8_t * data)934 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
935 uint8_t *data)
936 {
937 return mv88e6xxx_stats_get_strings(chip, data,
938 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
939 }
940
mv88e6250_stats_get_strings(struct mv88e6xxx_chip * chip,uint8_t * data)941 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip,
942 uint8_t *data)
943 {
944 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0);
945 }
946
mv88e6320_stats_get_strings(struct mv88e6xxx_chip * chip,uint8_t * data)947 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
948 uint8_t *data)
949 {
950 return mv88e6xxx_stats_get_strings(chip, data,
951 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
952 }
953
954 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
955 "atu_member_violation",
956 "atu_miss_violation",
957 "atu_full_violation",
958 "vtu_member_violation",
959 "vtu_miss_violation",
960 };
961
mv88e6xxx_atu_vtu_get_strings(uint8_t * data)962 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data)
963 {
964 unsigned int i;
965
966 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
967 strlcpy(data + i * ETH_GSTRING_LEN,
968 mv88e6xxx_atu_vtu_stats_strings[i],
969 ETH_GSTRING_LEN);
970 }
971
mv88e6xxx_get_strings(struct dsa_switch * ds,int port,u32 stringset,uint8_t * data)972 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
973 u32 stringset, uint8_t *data)
974 {
975 struct mv88e6xxx_chip *chip = ds->priv;
976 int count = 0;
977
978 if (stringset != ETH_SS_STATS)
979 return;
980
981 mv88e6xxx_reg_lock(chip);
982
983 if (chip->info->ops->stats_get_strings)
984 count = chip->info->ops->stats_get_strings(chip, data);
985
986 if (chip->info->ops->serdes_get_strings) {
987 data += count * ETH_GSTRING_LEN;
988 count = chip->info->ops->serdes_get_strings(chip, port, data);
989 }
990
991 data += count * ETH_GSTRING_LEN;
992 mv88e6xxx_atu_vtu_get_strings(data);
993
994 mv88e6xxx_reg_unlock(chip);
995 }
996
mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip * chip,int types)997 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
998 int types)
999 {
1000 struct mv88e6xxx_hw_stat *stat;
1001 int i, j;
1002
1003 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1004 stat = &mv88e6xxx_hw_stats[i];
1005 if (stat->type & types)
1006 j++;
1007 }
1008 return j;
1009 }
1010
mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip * chip)1011 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1012 {
1013 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1014 STATS_TYPE_PORT);
1015 }
1016
mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip * chip)1017 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1018 {
1019 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0);
1020 }
1021
mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip * chip)1022 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1023 {
1024 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1025 STATS_TYPE_BANK1);
1026 }
1027
mv88e6xxx_get_sset_count(struct dsa_switch * ds,int port,int sset)1028 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset)
1029 {
1030 struct mv88e6xxx_chip *chip = ds->priv;
1031 int serdes_count = 0;
1032 int count = 0;
1033
1034 if (sset != ETH_SS_STATS)
1035 return 0;
1036
1037 mv88e6xxx_reg_lock(chip);
1038 if (chip->info->ops->stats_get_sset_count)
1039 count = chip->info->ops->stats_get_sset_count(chip);
1040 if (count < 0)
1041 goto out;
1042
1043 if (chip->info->ops->serdes_get_sset_count)
1044 serdes_count = chip->info->ops->serdes_get_sset_count(chip,
1045 port);
1046 if (serdes_count < 0) {
1047 count = serdes_count;
1048 goto out;
1049 }
1050 count += serdes_count;
1051 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);
1052
1053 out:
1054 mv88e6xxx_reg_unlock(chip);
1055
1056 return count;
1057 }
1058
mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data,int types,u16 bank1_select,u16 histogram)1059 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1060 uint64_t *data, int types,
1061 u16 bank1_select, u16 histogram)
1062 {
1063 struct mv88e6xxx_hw_stat *stat;
1064 int i, j;
1065
1066 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1067 stat = &mv88e6xxx_hw_stats[i];
1068 if (stat->type & types) {
1069 mv88e6xxx_reg_lock(chip);
1070 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1071 bank1_select,
1072 histogram);
1073 mv88e6xxx_reg_unlock(chip);
1074
1075 j++;
1076 }
1077 }
1078 return j;
1079 }
1080
mv88e6095_stats_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1081 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1082 uint64_t *data)
1083 {
1084 return mv88e6xxx_stats_get_stats(chip, port, data,
1085 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
1086 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1087 }
1088
mv88e6250_stats_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1089 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1090 uint64_t *data)
1091 {
1092 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0,
1093 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1094 }
1095
mv88e6320_stats_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1096 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1097 uint64_t *data)
1098 {
1099 return mv88e6xxx_stats_get_stats(chip, port, data,
1100 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1101 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
1102 MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1103 }
1104
mv88e6390_stats_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1105 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1106 uint64_t *data)
1107 {
1108 return mv88e6xxx_stats_get_stats(chip, port, data,
1109 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1110 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
1111 0);
1112 }
1113
mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1114 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
1115 uint64_t *data)
1116 {
1117 *data++ = chip->ports[port].atu_member_violation;
1118 *data++ = chip->ports[port].atu_miss_violation;
1119 *data++ = chip->ports[port].atu_full_violation;
1120 *data++ = chip->ports[port].vtu_member_violation;
1121 *data++ = chip->ports[port].vtu_miss_violation;
1122 }
1123
mv88e6xxx_get_stats(struct mv88e6xxx_chip * chip,int port,uint64_t * data)1124 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1125 uint64_t *data)
1126 {
1127 int count = 0;
1128
1129 if (chip->info->ops->stats_get_stats)
1130 count = chip->info->ops->stats_get_stats(chip, port, data);
1131
1132 mv88e6xxx_reg_lock(chip);
1133 if (chip->info->ops->serdes_get_stats) {
1134 data += count;
1135 count = chip->info->ops->serdes_get_stats(chip, port, data);
1136 }
1137 data += count;
1138 mv88e6xxx_atu_vtu_get_stats(chip, port, data);
1139 mv88e6xxx_reg_unlock(chip);
1140 }
1141
mv88e6xxx_get_ethtool_stats(struct dsa_switch * ds,int port,uint64_t * data)1142 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1143 uint64_t *data)
1144 {
1145 struct mv88e6xxx_chip *chip = ds->priv;
1146 int ret;
1147
1148 mv88e6xxx_reg_lock(chip);
1149
1150 ret = mv88e6xxx_stats_snapshot(chip, port);
1151 mv88e6xxx_reg_unlock(chip);
1152
1153 if (ret < 0)
1154 return;
1155
1156 mv88e6xxx_get_stats(chip, port, data);
1157
1158 }
1159
mv88e6xxx_get_regs_len(struct dsa_switch * ds,int port)1160 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1161 {
1162 struct mv88e6xxx_chip *chip = ds->priv;
1163 int len;
1164
1165 len = 32 * sizeof(u16);
1166 if (chip->info->ops->serdes_get_regs_len)
1167 len += chip->info->ops->serdes_get_regs_len(chip, port);
1168
1169 return len;
1170 }
1171
mv88e6xxx_get_regs(struct dsa_switch * ds,int port,struct ethtool_regs * regs,void * _p)1172 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1173 struct ethtool_regs *regs, void *_p)
1174 {
1175 struct mv88e6xxx_chip *chip = ds->priv;
1176 int err;
1177 u16 reg;
1178 u16 *p = _p;
1179 int i;
1180
1181 regs->version = chip->info->prod_num;
1182
1183 memset(p, 0xff, 32 * sizeof(u16));
1184
1185 mv88e6xxx_reg_lock(chip);
1186
1187 for (i = 0; i < 32; i++) {
1188
1189 err = mv88e6xxx_port_read(chip, port, i, ®);
1190 if (!err)
1191 p[i] = reg;
1192 }
1193
1194 if (chip->info->ops->serdes_get_regs)
1195 chip->info->ops->serdes_get_regs(chip, port, &p[i]);
1196
1197 mv88e6xxx_reg_unlock(chip);
1198 }
1199
mv88e6xxx_get_mac_eee(struct dsa_switch * ds,int port,struct ethtool_eee * e)1200 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
1201 struct ethtool_eee *e)
1202 {
1203 /* Nothing to do on the port's MAC */
1204 return 0;
1205 }
1206
mv88e6xxx_set_mac_eee(struct dsa_switch * ds,int port,struct ethtool_eee * e)1207 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
1208 struct ethtool_eee *e)
1209 {
1210 /* Nothing to do on the port's MAC */
1211 return 0;
1212 }
1213
1214 /* Mask of the local ports allowed to receive frames from a given fabric port */
mv88e6xxx_port_vlan(struct mv88e6xxx_chip * chip,int dev,int port)1215 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
1216 {
1217 struct dsa_switch *ds = chip->ds;
1218 struct dsa_switch_tree *dst = ds->dst;
1219 struct net_device *br;
1220 struct dsa_port *dp;
1221 bool found = false;
1222 u16 pvlan;
1223
1224 list_for_each_entry(dp, &dst->ports, list) {
1225 if (dp->ds->index == dev && dp->index == port) {
1226 found = true;
1227 break;
1228 }
1229 }
1230
1231 /* Prevent frames from unknown switch or port */
1232 if (!found)
1233 return 0;
1234
1235 /* Frames from DSA links and CPU ports can egress any local port */
1236 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA)
1237 return mv88e6xxx_port_mask(chip);
1238
1239 br = dp->bridge_dev;
1240 pvlan = 0;
1241
1242 /* Frames from user ports can egress any local DSA links and CPU ports,
1243 * as well as any local member of their bridge group.
1244 */
1245 list_for_each_entry(dp, &dst->ports, list)
1246 if (dp->ds == ds &&
1247 (dp->type == DSA_PORT_TYPE_CPU ||
1248 dp->type == DSA_PORT_TYPE_DSA ||
1249 (br && dp->bridge_dev == br)))
1250 pvlan |= BIT(dp->index);
1251
1252 return pvlan;
1253 }
1254
mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip * chip,int port)1255 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
1256 {
1257 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
1258
1259 /* prevent frames from going back out of the port they came in on */
1260 output_ports &= ~BIT(port);
1261
1262 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1263 }
1264
mv88e6xxx_port_stp_state_set(struct dsa_switch * ds,int port,u8 state)1265 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1266 u8 state)
1267 {
1268 struct mv88e6xxx_chip *chip = ds->priv;
1269 int err;
1270
1271 mv88e6xxx_reg_lock(chip);
1272 err = mv88e6xxx_port_set_state(chip, port, state);
1273 mv88e6xxx_reg_unlock(chip);
1274
1275 if (err)
1276 dev_err(ds->dev, "p%d: failed to update state\n", port);
1277 }
1278
mv88e6xxx_pri_setup(struct mv88e6xxx_chip * chip)1279 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
1280 {
1281 int err;
1282
1283 if (chip->info->ops->ieee_pri_map) {
1284 err = chip->info->ops->ieee_pri_map(chip);
1285 if (err)
1286 return err;
1287 }
1288
1289 if (chip->info->ops->ip_pri_map) {
1290 err = chip->info->ops->ip_pri_map(chip);
1291 if (err)
1292 return err;
1293 }
1294
1295 return 0;
1296 }
1297
mv88e6xxx_devmap_setup(struct mv88e6xxx_chip * chip)1298 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
1299 {
1300 struct dsa_switch *ds = chip->ds;
1301 int target, port;
1302 int err;
1303
1304 if (!chip->info->global2_addr)
1305 return 0;
1306
1307 /* Initialize the routing port to the 32 possible target devices */
1308 for (target = 0; target < 32; target++) {
1309 port = dsa_routing_port(ds, target);
1310 if (port == ds->num_ports)
1311 port = 0x1f;
1312
1313 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
1314 if (err)
1315 return err;
1316 }
1317
1318 if (chip->info->ops->set_cascade_port) {
1319 port = MV88E6XXX_CASCADE_PORT_MULTIPLE;
1320 err = chip->info->ops->set_cascade_port(chip, port);
1321 if (err)
1322 return err;
1323 }
1324
1325 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
1326 if (err)
1327 return err;
1328
1329 return 0;
1330 }
1331
mv88e6xxx_trunk_setup(struct mv88e6xxx_chip * chip)1332 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
1333 {
1334 /* Clear all trunk masks and mapping */
1335 if (chip->info->global2_addr)
1336 return mv88e6xxx_g2_trunk_clear(chip);
1337
1338 return 0;
1339 }
1340
mv88e6xxx_rmu_setup(struct mv88e6xxx_chip * chip)1341 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
1342 {
1343 if (chip->info->ops->rmu_disable)
1344 return chip->info->ops->rmu_disable(chip);
1345
1346 return 0;
1347 }
1348
mv88e6xxx_pot_setup(struct mv88e6xxx_chip * chip)1349 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
1350 {
1351 if (chip->info->ops->pot_clear)
1352 return chip->info->ops->pot_clear(chip);
1353
1354 return 0;
1355 }
1356
mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip * chip)1357 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
1358 {
1359 if (chip->info->ops->mgmt_rsvd2cpu)
1360 return chip->info->ops->mgmt_rsvd2cpu(chip);
1361
1362 return 0;
1363 }
1364
mv88e6xxx_atu_setup(struct mv88e6xxx_chip * chip)1365 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1366 {
1367 int err;
1368
1369 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1370 if (err)
1371 return err;
1372
1373 /* The chips that have a "learn2all" bit in Global1, ATU
1374 * Control are precisely those whose port registers have a
1375 * Message Port bit in Port Control 1 and hence implement
1376 * ->port_setup_message_port.
1377 */
1378 if (chip->info->ops->port_setup_message_port) {
1379 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1380 if (err)
1381 return err;
1382 }
1383
1384 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1385 }
1386
mv88e6xxx_irl_setup(struct mv88e6xxx_chip * chip)1387 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
1388 {
1389 int port;
1390 int err;
1391
1392 if (!chip->info->ops->irl_init_all)
1393 return 0;
1394
1395 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1396 /* Disable ingress rate limiting by resetting all per port
1397 * ingress rate limit resources to their initial state.
1398 */
1399 err = chip->info->ops->irl_init_all(chip, port);
1400 if (err)
1401 return err;
1402 }
1403
1404 return 0;
1405 }
1406
mv88e6xxx_mac_setup(struct mv88e6xxx_chip * chip)1407 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
1408 {
1409 if (chip->info->ops->set_switch_mac) {
1410 u8 addr[ETH_ALEN];
1411
1412 eth_random_addr(addr);
1413
1414 return chip->info->ops->set_switch_mac(chip, addr);
1415 }
1416
1417 return 0;
1418 }
1419
mv88e6xxx_pvt_map(struct mv88e6xxx_chip * chip,int dev,int port)1420 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1421 {
1422 struct dsa_switch_tree *dst = chip->ds->dst;
1423 struct dsa_switch *ds;
1424 struct dsa_port *dp;
1425 u16 pvlan = 0;
1426
1427 if (!mv88e6xxx_has_pvt(chip))
1428 return 0;
1429
1430 /* Skip the local source device, which uses in-chip port VLAN */
1431 if (dev != chip->ds->index) {
1432 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
1433
1434 ds = dsa_switch_find(dst->index, dev);
1435 dp = ds ? dsa_to_port(ds, port) : NULL;
1436 if (dp && dp->lag_dev) {
1437 /* As the PVT is used to limit flooding of
1438 * FORWARD frames, which use the LAG ID as the
1439 * source port, we must translate dev/port to
1440 * the special "LAG device" in the PVT, using
1441 * the LAG ID as the port number.
1442 */
1443 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK;
1444 port = dsa_lag_id(dst, dp->lag_dev);
1445 }
1446 }
1447
1448 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1449 }
1450
mv88e6xxx_pvt_setup(struct mv88e6xxx_chip * chip)1451 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1452 {
1453 int dev, port;
1454 int err;
1455
1456 if (!mv88e6xxx_has_pvt(chip))
1457 return 0;
1458
1459 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
1460 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1461 */
1462 err = mv88e6xxx_g2_misc_4_bit_port(chip);
1463 if (err)
1464 return err;
1465
1466 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1467 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1468 err = mv88e6xxx_pvt_map(chip, dev, port);
1469 if (err)
1470 return err;
1471 }
1472 }
1473
1474 return 0;
1475 }
1476
mv88e6xxx_port_fast_age(struct dsa_switch * ds,int port)1477 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1478 {
1479 struct mv88e6xxx_chip *chip = ds->priv;
1480 int err;
1481
1482 if (dsa_to_port(ds, port)->lag_dev)
1483 /* Hardware is incapable of fast-aging a LAG through a
1484 * regular ATU move operation. Until we have something
1485 * more fancy in place this is a no-op.
1486 */
1487 return;
1488
1489 mv88e6xxx_reg_lock(chip);
1490 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
1491 mv88e6xxx_reg_unlock(chip);
1492
1493 if (err)
1494 dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
1495 }
1496
mv88e6xxx_vtu_setup(struct mv88e6xxx_chip * chip)1497 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1498 {
1499 if (!mv88e6xxx_max_vid(chip))
1500 return 0;
1501
1502 return mv88e6xxx_g1_vtu_flush(chip);
1503 }
1504
mv88e6xxx_vtu_get(struct mv88e6xxx_chip * chip,u16 vid,struct mv88e6xxx_vtu_entry * entry)1505 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1506 struct mv88e6xxx_vtu_entry *entry)
1507 {
1508 int err;
1509
1510 if (!chip->info->ops->vtu_getnext)
1511 return -EOPNOTSUPP;
1512
1513 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip);
1514 entry->valid = false;
1515
1516 err = chip->info->ops->vtu_getnext(chip, entry);
1517
1518 if (entry->vid != vid)
1519 entry->valid = false;
1520
1521 return err;
1522 }
1523
mv88e6xxx_vtu_walk(struct mv88e6xxx_chip * chip,int (* cb)(struct mv88e6xxx_chip * chip,const struct mv88e6xxx_vtu_entry * entry,void * priv),void * priv)1524 static int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip,
1525 int (*cb)(struct mv88e6xxx_chip *chip,
1526 const struct mv88e6xxx_vtu_entry *entry,
1527 void *priv),
1528 void *priv)
1529 {
1530 struct mv88e6xxx_vtu_entry entry = {
1531 .vid = mv88e6xxx_max_vid(chip),
1532 .valid = false,
1533 };
1534 int err;
1535
1536 if (!chip->info->ops->vtu_getnext)
1537 return -EOPNOTSUPP;
1538
1539 do {
1540 err = chip->info->ops->vtu_getnext(chip, &entry);
1541 if (err)
1542 return err;
1543
1544 if (!entry.valid)
1545 break;
1546
1547 err = cb(chip, &entry, priv);
1548 if (err)
1549 return err;
1550 } while (entry.vid < mv88e6xxx_max_vid(chip));
1551
1552 return 0;
1553 }
1554
mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip * chip,struct mv88e6xxx_vtu_entry * entry)1555 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1556 struct mv88e6xxx_vtu_entry *entry)
1557 {
1558 if (!chip->info->ops->vtu_loadpurge)
1559 return -EOPNOTSUPP;
1560
1561 return chip->info->ops->vtu_loadpurge(chip, entry);
1562 }
1563
mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip * chip,const struct mv88e6xxx_vtu_entry * entry,void * _fid_bitmap)1564 static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip,
1565 const struct mv88e6xxx_vtu_entry *entry,
1566 void *_fid_bitmap)
1567 {
1568 unsigned long *fid_bitmap = _fid_bitmap;
1569
1570 set_bit(entry->fid, fid_bitmap);
1571 return 0;
1572 }
1573
mv88e6xxx_fid_map(struct mv88e6xxx_chip * chip,unsigned long * fid_bitmap)1574 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap)
1575 {
1576 int i, err;
1577 u16 fid;
1578
1579 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1580
1581 /* Set every FID bit used by the (un)bridged ports */
1582 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1583 err = mv88e6xxx_port_get_fid(chip, i, &fid);
1584 if (err)
1585 return err;
1586
1587 set_bit(fid, fid_bitmap);
1588 }
1589
1590 /* Set every FID bit used by the VLAN entries */
1591 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap);
1592 }
1593
mv88e6xxx_atu_new(struct mv88e6xxx_chip * chip,u16 * fid)1594 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1595 {
1596 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1597 int err;
1598
1599 err = mv88e6xxx_fid_map(chip, fid_bitmap);
1600 if (err)
1601 return err;
1602
1603 /* The reset value 0x000 is used to indicate that multiple address
1604 * databases are not needed. Return the next positive available.
1605 */
1606 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1607 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1608 return -ENOSPC;
1609
1610 /* Clear the database */
1611 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1612 }
1613
mv88e6xxx_port_check_hw_vlan(struct dsa_switch * ds,int port,u16 vid)1614 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1615 u16 vid)
1616 {
1617 struct mv88e6xxx_chip *chip = ds->priv;
1618 struct mv88e6xxx_vtu_entry vlan;
1619 int i, err;
1620
1621 if (!vid)
1622 return -EOPNOTSUPP;
1623
1624 /* DSA and CPU ports have to be members of multiple vlans */
1625 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1626 return 0;
1627
1628 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
1629 if (err)
1630 return err;
1631
1632 if (!vlan.valid)
1633 return 0;
1634
1635 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1636 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1637 continue;
1638
1639 if (!dsa_to_port(ds, i)->slave)
1640 continue;
1641
1642 if (vlan.member[i] ==
1643 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1644 continue;
1645
1646 if (dsa_to_port(ds, i)->bridge_dev ==
1647 dsa_to_port(ds, port)->bridge_dev)
1648 break; /* same bridge, check next VLAN */
1649
1650 if (!dsa_to_port(ds, i)->bridge_dev)
1651 continue;
1652
1653 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
1654 port, vlan.vid, i,
1655 netdev_name(dsa_to_port(ds, i)->bridge_dev));
1656 return -EOPNOTSUPP;
1657 }
1658
1659 return 0;
1660 }
1661
mv88e6xxx_port_vlan_filtering(struct dsa_switch * ds,int port,bool vlan_filtering,struct netlink_ext_ack * extack)1662 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1663 bool vlan_filtering,
1664 struct netlink_ext_ack *extack)
1665 {
1666 struct mv88e6xxx_chip *chip = ds->priv;
1667 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
1668 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
1669 int err;
1670
1671 if (!mv88e6xxx_max_vid(chip))
1672 return -EOPNOTSUPP;
1673
1674 mv88e6xxx_reg_lock(chip);
1675 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
1676 mv88e6xxx_reg_unlock(chip);
1677
1678 return err;
1679 }
1680
1681 static int
mv88e6xxx_port_vlan_prepare(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)1682 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1683 const struct switchdev_obj_port_vlan *vlan)
1684 {
1685 struct mv88e6xxx_chip *chip = ds->priv;
1686 int err;
1687
1688 if (!mv88e6xxx_max_vid(chip))
1689 return -EOPNOTSUPP;
1690
1691 /* If the requested port doesn't belong to the same bridge as the VLAN
1692 * members, do not support it (yet) and fallback to software VLAN.
1693 */
1694 mv88e6xxx_reg_lock(chip);
1695 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid);
1696 mv88e6xxx_reg_unlock(chip);
1697
1698 return err;
1699 }
1700
mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip * chip,int port,const unsigned char * addr,u16 vid,u8 state)1701 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1702 const unsigned char *addr, u16 vid,
1703 u8 state)
1704 {
1705 struct mv88e6xxx_atu_entry entry;
1706 struct mv88e6xxx_vtu_entry vlan;
1707 u16 fid;
1708 int err;
1709
1710 /* Null VLAN ID corresponds to the port private database */
1711 if (vid == 0) {
1712 err = mv88e6xxx_port_get_fid(chip, port, &fid);
1713 if (err)
1714 return err;
1715 } else {
1716 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
1717 if (err)
1718 return err;
1719
1720 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
1721 if (!vlan.valid)
1722 return -EOPNOTSUPP;
1723
1724 fid = vlan.fid;
1725 }
1726
1727 entry.state = 0;
1728 ether_addr_copy(entry.mac, addr);
1729 eth_addr_dec(entry.mac);
1730
1731 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry);
1732 if (err)
1733 return err;
1734
1735 /* Initialize a fresh ATU entry if it isn't found */
1736 if (!entry.state || !ether_addr_equal(entry.mac, addr)) {
1737 memset(&entry, 0, sizeof(entry));
1738 ether_addr_copy(entry.mac, addr);
1739 }
1740
1741 /* Purge the ATU entry only if no port is using it anymore */
1742 if (!state) {
1743 entry.portvec &= ~BIT(port);
1744 if (!entry.portvec)
1745 entry.state = 0;
1746 } else {
1747 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC)
1748 entry.portvec = BIT(port);
1749 else
1750 entry.portvec |= BIT(port);
1751
1752 entry.state = state;
1753 }
1754
1755 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry);
1756 }
1757
mv88e6xxx_policy_apply(struct mv88e6xxx_chip * chip,int port,const struct mv88e6xxx_policy * policy)1758 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port,
1759 const struct mv88e6xxx_policy *policy)
1760 {
1761 enum mv88e6xxx_policy_mapping mapping = policy->mapping;
1762 enum mv88e6xxx_policy_action action = policy->action;
1763 const u8 *addr = policy->addr;
1764 u16 vid = policy->vid;
1765 u8 state;
1766 int err;
1767 int id;
1768
1769 if (!chip->info->ops->port_set_policy)
1770 return -EOPNOTSUPP;
1771
1772 switch (mapping) {
1773 case MV88E6XXX_POLICY_MAPPING_DA:
1774 case MV88E6XXX_POLICY_MAPPING_SA:
1775 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
1776 state = 0; /* Dissociate the port and address */
1777 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
1778 is_multicast_ether_addr(addr))
1779 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY;
1780 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
1781 is_unicast_ether_addr(addr))
1782 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY;
1783 else
1784 return -EOPNOTSUPP;
1785
1786 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1787 state);
1788 if (err)
1789 return err;
1790 break;
1791 default:
1792 return -EOPNOTSUPP;
1793 }
1794
1795 /* Skip the port's policy clearing if the mapping is still in use */
1796 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
1797 idr_for_each_entry(&chip->policies, policy, id)
1798 if (policy->port == port &&
1799 policy->mapping == mapping &&
1800 policy->action != action)
1801 return 0;
1802
1803 return chip->info->ops->port_set_policy(chip, port, mapping, action);
1804 }
1805
mv88e6xxx_policy_insert(struct mv88e6xxx_chip * chip,int port,struct ethtool_rx_flow_spec * fs)1806 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port,
1807 struct ethtool_rx_flow_spec *fs)
1808 {
1809 struct ethhdr *mac_entry = &fs->h_u.ether_spec;
1810 struct ethhdr *mac_mask = &fs->m_u.ether_spec;
1811 enum mv88e6xxx_policy_mapping mapping;
1812 enum mv88e6xxx_policy_action action;
1813 struct mv88e6xxx_policy *policy;
1814 u16 vid = 0;
1815 u8 *addr;
1816 int err;
1817 int id;
1818
1819 if (fs->location != RX_CLS_LOC_ANY)
1820 return -EINVAL;
1821
1822 if (fs->ring_cookie == RX_CLS_FLOW_DISC)
1823 action = MV88E6XXX_POLICY_ACTION_DISCARD;
1824 else
1825 return -EOPNOTSUPP;
1826
1827 switch (fs->flow_type & ~FLOW_EXT) {
1828 case ETHER_FLOW:
1829 if (!is_zero_ether_addr(mac_mask->h_dest) &&
1830 is_zero_ether_addr(mac_mask->h_source)) {
1831 mapping = MV88E6XXX_POLICY_MAPPING_DA;
1832 addr = mac_entry->h_dest;
1833 } else if (is_zero_ether_addr(mac_mask->h_dest) &&
1834 !is_zero_ether_addr(mac_mask->h_source)) {
1835 mapping = MV88E6XXX_POLICY_MAPPING_SA;
1836 addr = mac_entry->h_source;
1837 } else {
1838 /* Cannot support DA and SA mapping in the same rule */
1839 return -EOPNOTSUPP;
1840 }
1841 break;
1842 default:
1843 return -EOPNOTSUPP;
1844 }
1845
1846 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) {
1847 if (fs->m_ext.vlan_tci != htons(0xffff))
1848 return -EOPNOTSUPP;
1849 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK;
1850 }
1851
1852 idr_for_each_entry(&chip->policies, policy, id) {
1853 if (policy->port == port && policy->mapping == mapping &&
1854 policy->action == action && policy->vid == vid &&
1855 ether_addr_equal(policy->addr, addr))
1856 return -EEXIST;
1857 }
1858
1859 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL);
1860 if (!policy)
1861 return -ENOMEM;
1862
1863 fs->location = 0;
1864 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff,
1865 GFP_KERNEL);
1866 if (err) {
1867 devm_kfree(chip->dev, policy);
1868 return err;
1869 }
1870
1871 memcpy(&policy->fs, fs, sizeof(*fs));
1872 ether_addr_copy(policy->addr, addr);
1873 policy->mapping = mapping;
1874 policy->action = action;
1875 policy->port = port;
1876 policy->vid = vid;
1877
1878 err = mv88e6xxx_policy_apply(chip, port, policy);
1879 if (err) {
1880 idr_remove(&chip->policies, fs->location);
1881 devm_kfree(chip->dev, policy);
1882 return err;
1883 }
1884
1885 return 0;
1886 }
1887
mv88e6xxx_get_rxnfc(struct dsa_switch * ds,int port,struct ethtool_rxnfc * rxnfc,u32 * rule_locs)1888 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port,
1889 struct ethtool_rxnfc *rxnfc, u32 *rule_locs)
1890 {
1891 struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
1892 struct mv88e6xxx_chip *chip = ds->priv;
1893 struct mv88e6xxx_policy *policy;
1894 int err;
1895 int id;
1896
1897 mv88e6xxx_reg_lock(chip);
1898
1899 switch (rxnfc->cmd) {
1900 case ETHTOOL_GRXCLSRLCNT:
1901 rxnfc->data = 0;
1902 rxnfc->data |= RX_CLS_LOC_SPECIAL;
1903 rxnfc->rule_cnt = 0;
1904 idr_for_each_entry(&chip->policies, policy, id)
1905 if (policy->port == port)
1906 rxnfc->rule_cnt++;
1907 err = 0;
1908 break;
1909 case ETHTOOL_GRXCLSRULE:
1910 err = -ENOENT;
1911 policy = idr_find(&chip->policies, fs->location);
1912 if (policy) {
1913 memcpy(fs, &policy->fs, sizeof(*fs));
1914 err = 0;
1915 }
1916 break;
1917 case ETHTOOL_GRXCLSRLALL:
1918 rxnfc->data = 0;
1919 rxnfc->rule_cnt = 0;
1920 idr_for_each_entry(&chip->policies, policy, id)
1921 if (policy->port == port)
1922 rule_locs[rxnfc->rule_cnt++] = id;
1923 err = 0;
1924 break;
1925 default:
1926 err = -EOPNOTSUPP;
1927 break;
1928 }
1929
1930 mv88e6xxx_reg_unlock(chip);
1931
1932 return err;
1933 }
1934
mv88e6xxx_set_rxnfc(struct dsa_switch * ds,int port,struct ethtool_rxnfc * rxnfc)1935 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port,
1936 struct ethtool_rxnfc *rxnfc)
1937 {
1938 struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
1939 struct mv88e6xxx_chip *chip = ds->priv;
1940 struct mv88e6xxx_policy *policy;
1941 int err;
1942
1943 mv88e6xxx_reg_lock(chip);
1944
1945 switch (rxnfc->cmd) {
1946 case ETHTOOL_SRXCLSRLINS:
1947 err = mv88e6xxx_policy_insert(chip, port, fs);
1948 break;
1949 case ETHTOOL_SRXCLSRLDEL:
1950 err = -ENOENT;
1951 policy = idr_remove(&chip->policies, fs->location);
1952 if (policy) {
1953 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL;
1954 err = mv88e6xxx_policy_apply(chip, port, policy);
1955 devm_kfree(chip->dev, policy);
1956 }
1957 break;
1958 default:
1959 err = -EOPNOTSUPP;
1960 break;
1961 }
1962
1963 mv88e6xxx_reg_unlock(chip);
1964
1965 return err;
1966 }
1967
mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip * chip,int port,u16 vid)1968 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
1969 u16 vid)
1970 {
1971 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
1972 u8 broadcast[ETH_ALEN];
1973
1974 eth_broadcast_addr(broadcast);
1975
1976 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
1977 }
1978
mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip * chip,u16 vid)1979 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
1980 {
1981 int port;
1982 int err;
1983
1984 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1985 struct dsa_port *dp = dsa_to_port(chip->ds, port);
1986 struct net_device *brport;
1987
1988 if (dsa_is_unused_port(chip->ds, port))
1989 continue;
1990
1991 brport = dsa_port_to_bridge_port(dp);
1992 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD))
1993 /* Skip bridged user ports where broadcast
1994 * flooding is disabled.
1995 */
1996 continue;
1997
1998 err = mv88e6xxx_port_add_broadcast(chip, port, vid);
1999 if (err)
2000 return err;
2001 }
2002
2003 return 0;
2004 }
2005
2006 struct mv88e6xxx_port_broadcast_sync_ctx {
2007 int port;
2008 bool flood;
2009 };
2010
2011 static int
mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip * chip,const struct mv88e6xxx_vtu_entry * vlan,void * _ctx)2012 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip,
2013 const struct mv88e6xxx_vtu_entry *vlan,
2014 void *_ctx)
2015 {
2016 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx;
2017 u8 broadcast[ETH_ALEN];
2018 u8 state;
2019
2020 if (ctx->flood)
2021 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
2022 else
2023 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED;
2024
2025 eth_broadcast_addr(broadcast);
2026
2027 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast,
2028 vlan->vid, state);
2029 }
2030
mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip * chip,int port,bool flood)2031 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port,
2032 bool flood)
2033 {
2034 struct mv88e6xxx_port_broadcast_sync_ctx ctx = {
2035 .port = port,
2036 .flood = flood,
2037 };
2038 struct mv88e6xxx_vtu_entry vid0 = {
2039 .vid = 0,
2040 };
2041 int err;
2042
2043 /* Update the port's private database... */
2044 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx);
2045 if (err)
2046 return err;
2047
2048 /* ...and the database for all VLANs. */
2049 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan,
2050 &ctx);
2051 }
2052
mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip * chip,int port,u16 vid,u8 member,bool warn)2053 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port,
2054 u16 vid, u8 member, bool warn)
2055 {
2056 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2057 struct mv88e6xxx_vtu_entry vlan;
2058 int i, err;
2059
2060 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2061 if (err)
2062 return err;
2063
2064 if (!vlan.valid) {
2065 memset(&vlan, 0, sizeof(vlan));
2066
2067 err = mv88e6xxx_atu_new(chip, &vlan.fid);
2068 if (err)
2069 return err;
2070
2071 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
2072 if (i == port)
2073 vlan.member[i] = member;
2074 else
2075 vlan.member[i] = non_member;
2076
2077 vlan.vid = vid;
2078 vlan.valid = true;
2079
2080 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2081 if (err)
2082 return err;
2083
2084 err = mv88e6xxx_broadcast_setup(chip, vlan.vid);
2085 if (err)
2086 return err;
2087 } else if (vlan.member[port] != member) {
2088 vlan.member[port] = member;
2089
2090 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2091 if (err)
2092 return err;
2093 } else if (warn) {
2094 dev_info(chip->dev, "p%d: already a member of VLAN %d\n",
2095 port, vid);
2096 }
2097
2098 return 0;
2099 }
2100
mv88e6xxx_port_vlan_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan,struct netlink_ext_ack * extack)2101 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
2102 const struct switchdev_obj_port_vlan *vlan,
2103 struct netlink_ext_ack *extack)
2104 {
2105 struct mv88e6xxx_chip *chip = ds->priv;
2106 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
2107 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
2108 bool warn;
2109 u8 member;
2110 int err;
2111
2112 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan);
2113 if (err)
2114 return err;
2115
2116 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
2117 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
2118 else if (untagged)
2119 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
2120 else
2121 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
2122
2123 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port
2124 * and then the CPU port. Do not warn for duplicates for the CPU port.
2125 */
2126 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port);
2127
2128 mv88e6xxx_reg_lock(chip);
2129
2130 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn);
2131 if (err) {
2132 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
2133 vlan->vid, untagged ? 'u' : 't');
2134 goto out;
2135 }
2136
2137 if (pvid) {
2138 err = mv88e6xxx_port_set_pvid(chip, port, vlan->vid);
2139 if (err) {
2140 dev_err(ds->dev, "p%d: failed to set PVID %d\n",
2141 port, vlan->vid);
2142 goto out;
2143 }
2144 }
2145 out:
2146 mv88e6xxx_reg_unlock(chip);
2147
2148 return err;
2149 }
2150
mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip * chip,int port,u16 vid)2151 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip,
2152 int port, u16 vid)
2153 {
2154 struct mv88e6xxx_vtu_entry vlan;
2155 int i, err;
2156
2157 if (!vid)
2158 return -EOPNOTSUPP;
2159
2160 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2161 if (err)
2162 return err;
2163
2164 /* If the VLAN doesn't exist in hardware or the port isn't a member,
2165 * tell switchdev that this VLAN is likely handled in software.
2166 */
2167 if (!vlan.valid ||
2168 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2169 return -EOPNOTSUPP;
2170
2171 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2172
2173 /* keep the VLAN unless all ports are excluded */
2174 vlan.valid = false;
2175 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
2176 if (vlan.member[i] !=
2177 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
2178 vlan.valid = true;
2179 break;
2180 }
2181 }
2182
2183 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2184 if (err)
2185 return err;
2186
2187 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
2188 }
2189
mv88e6xxx_port_vlan_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)2190 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2191 const struct switchdev_obj_port_vlan *vlan)
2192 {
2193 struct mv88e6xxx_chip *chip = ds->priv;
2194 int err = 0;
2195 u16 pvid;
2196
2197 if (!mv88e6xxx_max_vid(chip))
2198 return -EOPNOTSUPP;
2199
2200 mv88e6xxx_reg_lock(chip);
2201
2202 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
2203 if (err)
2204 goto unlock;
2205
2206 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid);
2207 if (err)
2208 goto unlock;
2209
2210 if (vlan->vid == pvid) {
2211 err = mv88e6xxx_port_set_pvid(chip, port, 0);
2212 if (err)
2213 goto unlock;
2214 }
2215
2216 unlock:
2217 mv88e6xxx_reg_unlock(chip);
2218
2219 return err;
2220 }
2221
mv88e6xxx_port_fdb_add(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid)2222 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2223 const unsigned char *addr, u16 vid)
2224 {
2225 struct mv88e6xxx_chip *chip = ds->priv;
2226 int err;
2227
2228 mv88e6xxx_reg_lock(chip);
2229 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2230 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2231 mv88e6xxx_reg_unlock(chip);
2232
2233 return err;
2234 }
2235
mv88e6xxx_port_fdb_del(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid)2236 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2237 const unsigned char *addr, u16 vid)
2238 {
2239 struct mv88e6xxx_chip *chip = ds->priv;
2240 int err;
2241
2242 mv88e6xxx_reg_lock(chip);
2243 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0);
2244 mv88e6xxx_reg_unlock(chip);
2245
2246 return err;
2247 }
2248
mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip * chip,u16 fid,u16 vid,int port,dsa_fdb_dump_cb_t * cb,void * data)2249 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2250 u16 fid, u16 vid, int port,
2251 dsa_fdb_dump_cb_t *cb, void *data)
2252 {
2253 struct mv88e6xxx_atu_entry addr;
2254 bool is_static;
2255 int err;
2256
2257 addr.state = 0;
2258 eth_broadcast_addr(addr.mac);
2259
2260 do {
2261 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
2262 if (err)
2263 return err;
2264
2265 if (!addr.state)
2266 break;
2267
2268 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
2269 continue;
2270
2271 if (!is_unicast_ether_addr(addr.mac))
2272 continue;
2273
2274 is_static = (addr.state ==
2275 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2276 err = cb(addr.mac, vid, is_static, data);
2277 if (err)
2278 return err;
2279 } while (!is_broadcast_ether_addr(addr.mac));
2280
2281 return err;
2282 }
2283
2284 struct mv88e6xxx_port_db_dump_vlan_ctx {
2285 int port;
2286 dsa_fdb_dump_cb_t *cb;
2287 void *data;
2288 };
2289
mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip * chip,const struct mv88e6xxx_vtu_entry * entry,void * _data)2290 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip,
2291 const struct mv88e6xxx_vtu_entry *entry,
2292 void *_data)
2293 {
2294 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data;
2295
2296 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid,
2297 ctx->port, ctx->cb, ctx->data);
2298 }
2299
mv88e6xxx_port_db_dump(struct mv88e6xxx_chip * chip,int port,dsa_fdb_dump_cb_t * cb,void * data)2300 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2301 dsa_fdb_dump_cb_t *cb, void *data)
2302 {
2303 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = {
2304 .port = port,
2305 .cb = cb,
2306 .data = data,
2307 };
2308 u16 fid;
2309 int err;
2310
2311 /* Dump port's default Filtering Information Database (VLAN ID 0) */
2312 err = mv88e6xxx_port_get_fid(chip, port, &fid);
2313 if (err)
2314 return err;
2315
2316 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
2317 if (err)
2318 return err;
2319
2320 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx);
2321 }
2322
mv88e6xxx_port_fdb_dump(struct dsa_switch * ds,int port,dsa_fdb_dump_cb_t * cb,void * data)2323 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2324 dsa_fdb_dump_cb_t *cb, void *data)
2325 {
2326 struct mv88e6xxx_chip *chip = ds->priv;
2327 int err;
2328
2329 mv88e6xxx_reg_lock(chip);
2330 err = mv88e6xxx_port_db_dump(chip, port, cb, data);
2331 mv88e6xxx_reg_unlock(chip);
2332
2333 return err;
2334 }
2335
mv88e6xxx_bridge_map(struct mv88e6xxx_chip * chip,struct net_device * br)2336 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
2337 struct net_device *br)
2338 {
2339 struct dsa_switch *ds = chip->ds;
2340 struct dsa_switch_tree *dst = ds->dst;
2341 struct dsa_port *dp;
2342 int err;
2343
2344 list_for_each_entry(dp, &dst->ports, list) {
2345 if (dp->bridge_dev == br) {
2346 if (dp->ds == ds) {
2347 /* This is a local bridge group member,
2348 * remap its Port VLAN Map.
2349 */
2350 err = mv88e6xxx_port_vlan_map(chip, dp->index);
2351 if (err)
2352 return err;
2353 } else {
2354 /* This is an external bridge group member,
2355 * remap its cross-chip Port VLAN Table entry.
2356 */
2357 err = mv88e6xxx_pvt_map(chip, dp->ds->index,
2358 dp->index);
2359 if (err)
2360 return err;
2361 }
2362 }
2363 }
2364
2365 return 0;
2366 }
2367
mv88e6xxx_port_bridge_join(struct dsa_switch * ds,int port,struct net_device * br)2368 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2369 struct net_device *br)
2370 {
2371 struct mv88e6xxx_chip *chip = ds->priv;
2372 int err;
2373
2374 mv88e6xxx_reg_lock(chip);
2375 err = mv88e6xxx_bridge_map(chip, br);
2376 mv88e6xxx_reg_unlock(chip);
2377
2378 return err;
2379 }
2380
mv88e6xxx_port_bridge_leave(struct dsa_switch * ds,int port,struct net_device * br)2381 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
2382 struct net_device *br)
2383 {
2384 struct mv88e6xxx_chip *chip = ds->priv;
2385
2386 mv88e6xxx_reg_lock(chip);
2387 if (mv88e6xxx_bridge_map(chip, br) ||
2388 mv88e6xxx_port_vlan_map(chip, port))
2389 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
2390 mv88e6xxx_reg_unlock(chip);
2391 }
2392
mv88e6xxx_crosschip_bridge_join(struct dsa_switch * ds,int tree_index,int sw_index,int port,struct net_device * br)2393 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds,
2394 int tree_index, int sw_index,
2395 int port, struct net_device *br)
2396 {
2397 struct mv88e6xxx_chip *chip = ds->priv;
2398 int err;
2399
2400 if (tree_index != ds->dst->index)
2401 return 0;
2402
2403 mv88e6xxx_reg_lock(chip);
2404 err = mv88e6xxx_pvt_map(chip, sw_index, port);
2405 mv88e6xxx_reg_unlock(chip);
2406
2407 return err;
2408 }
2409
mv88e6xxx_crosschip_bridge_leave(struct dsa_switch * ds,int tree_index,int sw_index,int port,struct net_device * br)2410 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds,
2411 int tree_index, int sw_index,
2412 int port, struct net_device *br)
2413 {
2414 struct mv88e6xxx_chip *chip = ds->priv;
2415
2416 if (tree_index != ds->dst->index)
2417 return;
2418
2419 mv88e6xxx_reg_lock(chip);
2420 if (mv88e6xxx_pvt_map(chip, sw_index, port))
2421 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
2422 mv88e6xxx_reg_unlock(chip);
2423 }
2424
mv88e6xxx_software_reset(struct mv88e6xxx_chip * chip)2425 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
2426 {
2427 if (chip->info->ops->reset)
2428 return chip->info->ops->reset(chip);
2429
2430 return 0;
2431 }
2432
mv88e6xxx_hardware_reset(struct mv88e6xxx_chip * chip)2433 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
2434 {
2435 struct gpio_desc *gpiod = chip->reset;
2436
2437 /* If there is a GPIO connected to the reset pin, toggle it */
2438 if (gpiod) {
2439 gpiod_set_value_cansleep(gpiod, 1);
2440 usleep_range(10000, 20000);
2441 gpiod_set_value_cansleep(gpiod, 0);
2442 usleep_range(10000, 20000);
2443
2444 mv88e6xxx_g1_wait_eeprom_done(chip);
2445 }
2446 }
2447
mv88e6xxx_disable_ports(struct mv88e6xxx_chip * chip)2448 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
2449 {
2450 int i, err;
2451
2452 /* Set all ports to the Disabled state */
2453 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2454 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
2455 if (err)
2456 return err;
2457 }
2458
2459 /* Wait for transmit queues to drain,
2460 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
2461 */
2462 usleep_range(2000, 4000);
2463
2464 return 0;
2465 }
2466
mv88e6xxx_switch_reset(struct mv88e6xxx_chip * chip)2467 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2468 {
2469 int err;
2470
2471 err = mv88e6xxx_disable_ports(chip);
2472 if (err)
2473 return err;
2474
2475 mv88e6xxx_hardware_reset(chip);
2476
2477 return mv88e6xxx_software_reset(chip);
2478 }
2479
mv88e6xxx_set_port_mode(struct mv88e6xxx_chip * chip,int port,enum mv88e6xxx_frame_mode frame,enum mv88e6xxx_egress_mode egress,u16 etype)2480 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
2481 enum mv88e6xxx_frame_mode frame,
2482 enum mv88e6xxx_egress_mode egress, u16 etype)
2483 {
2484 int err;
2485
2486 if (!chip->info->ops->port_set_frame_mode)
2487 return -EOPNOTSUPP;
2488
2489 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
2490 if (err)
2491 return err;
2492
2493 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
2494 if (err)
2495 return err;
2496
2497 if (chip->info->ops->port_set_ether_type)
2498 return chip->info->ops->port_set_ether_type(chip, port, etype);
2499
2500 return 0;
2501 }
2502
mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip * chip,int port)2503 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
2504 {
2505 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
2506 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
2507 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
2508 }
2509
mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip * chip,int port)2510 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
2511 {
2512 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
2513 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
2514 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
2515 }
2516
mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip * chip,int port)2517 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
2518 {
2519 return mv88e6xxx_set_port_mode(chip, port,
2520 MV88E6XXX_FRAME_MODE_ETHERTYPE,
2521 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
2522 ETH_P_EDSA);
2523 }
2524
mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip * chip,int port)2525 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
2526 {
2527 if (dsa_is_dsa_port(chip->ds, port))
2528 return mv88e6xxx_set_port_mode_dsa(chip, port);
2529
2530 if (dsa_is_user_port(chip->ds, port))
2531 return mv88e6xxx_set_port_mode_normal(chip, port);
2532
2533 /* Setup CPU port mode depending on its supported tag format */
2534 if (chip->tag_protocol == DSA_TAG_PROTO_DSA)
2535 return mv88e6xxx_set_port_mode_dsa(chip, port);
2536
2537 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA)
2538 return mv88e6xxx_set_port_mode_edsa(chip, port);
2539
2540 return -EINVAL;
2541 }
2542
mv88e6xxx_setup_message_port(struct mv88e6xxx_chip * chip,int port)2543 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
2544 {
2545 bool message = dsa_is_dsa_port(chip->ds, port);
2546
2547 return mv88e6xxx_port_set_message_port(chip, port, message);
2548 }
2549
mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip * chip,int port)2550 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
2551 {
2552 int err;
2553
2554 if (chip->info->ops->port_set_ucast_flood) {
2555 err = chip->info->ops->port_set_ucast_flood(chip, port, true);
2556 if (err)
2557 return err;
2558 }
2559 if (chip->info->ops->port_set_mcast_flood) {
2560 err = chip->info->ops->port_set_mcast_flood(chip, port, true);
2561 if (err)
2562 return err;
2563 }
2564
2565 return 0;
2566 }
2567
mv88e6xxx_serdes_irq_thread_fn(int irq,void * dev_id)2568 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id)
2569 {
2570 struct mv88e6xxx_port *mvp = dev_id;
2571 struct mv88e6xxx_chip *chip = mvp->chip;
2572 irqreturn_t ret = IRQ_NONE;
2573 int port = mvp->port;
2574 int lane;
2575
2576 mv88e6xxx_reg_lock(chip);
2577 lane = mv88e6xxx_serdes_get_lane(chip, port);
2578 if (lane >= 0)
2579 ret = mv88e6xxx_serdes_irq_status(chip, port, lane);
2580 mv88e6xxx_reg_unlock(chip);
2581
2582 return ret;
2583 }
2584
mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip * chip,int port,int lane)2585 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port,
2586 int lane)
2587 {
2588 struct mv88e6xxx_port *dev_id = &chip->ports[port];
2589 unsigned int irq;
2590 int err;
2591
2592 /* Nothing to request if this SERDES port has no IRQ */
2593 irq = mv88e6xxx_serdes_irq_mapping(chip, port);
2594 if (!irq)
2595 return 0;
2596
2597 snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name),
2598 "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port);
2599
2600 /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */
2601 mv88e6xxx_reg_unlock(chip);
2602 err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn,
2603 IRQF_ONESHOT, dev_id->serdes_irq_name,
2604 dev_id);
2605 mv88e6xxx_reg_lock(chip);
2606 if (err)
2607 return err;
2608
2609 dev_id->serdes_irq = irq;
2610
2611 return mv88e6xxx_serdes_irq_enable(chip, port, lane);
2612 }
2613
mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip * chip,int port,int lane)2614 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port,
2615 int lane)
2616 {
2617 struct mv88e6xxx_port *dev_id = &chip->ports[port];
2618 unsigned int irq = dev_id->serdes_irq;
2619 int err;
2620
2621 /* Nothing to free if no IRQ has been requested */
2622 if (!irq)
2623 return 0;
2624
2625 err = mv88e6xxx_serdes_irq_disable(chip, port, lane);
2626
2627 /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */
2628 mv88e6xxx_reg_unlock(chip);
2629 free_irq(irq, dev_id);
2630 mv88e6xxx_reg_lock(chip);
2631
2632 dev_id->serdes_irq = 0;
2633
2634 return err;
2635 }
2636
mv88e6xxx_serdes_power(struct mv88e6xxx_chip * chip,int port,bool on)2637 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
2638 bool on)
2639 {
2640 int lane;
2641 int err;
2642
2643 lane = mv88e6xxx_serdes_get_lane(chip, port);
2644 if (lane < 0)
2645 return 0;
2646
2647 if (on) {
2648 err = mv88e6xxx_serdes_power_up(chip, port, lane);
2649 if (err)
2650 return err;
2651
2652 err = mv88e6xxx_serdes_irq_request(chip, port, lane);
2653 } else {
2654 err = mv88e6xxx_serdes_irq_free(chip, port, lane);
2655 if (err)
2656 return err;
2657
2658 err = mv88e6xxx_serdes_power_down(chip, port, lane);
2659 }
2660
2661 return err;
2662 }
2663
mv88e6xxx_set_egress_port(struct mv88e6xxx_chip * chip,enum mv88e6xxx_egress_direction direction,int port)2664 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip,
2665 enum mv88e6xxx_egress_direction direction,
2666 int port)
2667 {
2668 int err;
2669
2670 if (!chip->info->ops->set_egress_port)
2671 return -EOPNOTSUPP;
2672
2673 err = chip->info->ops->set_egress_port(chip, direction, port);
2674 if (err)
2675 return err;
2676
2677 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS)
2678 chip->ingress_dest_port = port;
2679 else
2680 chip->egress_dest_port = port;
2681
2682 return 0;
2683 }
2684
mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip * chip,int port)2685 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
2686 {
2687 struct dsa_switch *ds = chip->ds;
2688 int upstream_port;
2689 int err;
2690
2691 upstream_port = dsa_upstream_port(ds, port);
2692 if (chip->info->ops->port_set_upstream_port) {
2693 err = chip->info->ops->port_set_upstream_port(chip, port,
2694 upstream_port);
2695 if (err)
2696 return err;
2697 }
2698
2699 if (port == upstream_port) {
2700 if (chip->info->ops->set_cpu_port) {
2701 err = chip->info->ops->set_cpu_port(chip,
2702 upstream_port);
2703 if (err)
2704 return err;
2705 }
2706
2707 err = mv88e6xxx_set_egress_port(chip,
2708 MV88E6XXX_EGRESS_DIR_INGRESS,
2709 upstream_port);
2710 if (err && err != -EOPNOTSUPP)
2711 return err;
2712
2713 err = mv88e6xxx_set_egress_port(chip,
2714 MV88E6XXX_EGRESS_DIR_EGRESS,
2715 upstream_port);
2716 if (err && err != -EOPNOTSUPP)
2717 return err;
2718 }
2719
2720 return 0;
2721 }
2722
mv88e6xxx_setup_port(struct mv88e6xxx_chip * chip,int port)2723 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2724 {
2725 struct dsa_switch *ds = chip->ds;
2726 int err;
2727 u16 reg;
2728
2729 chip->ports[port].chip = chip;
2730 chip->ports[port].port = port;
2731
2732 /* MAC Forcing register: don't force link, speed, duplex or flow control
2733 * state to any particular values on physical ports, but force the CPU
2734 * port and all DSA ports to their maximum bandwidth and full duplex.
2735 */
2736 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2737 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2738 SPEED_MAX, DUPLEX_FULL,
2739 PAUSE_OFF,
2740 PHY_INTERFACE_MODE_NA);
2741 else
2742 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2743 SPEED_UNFORCED, DUPLEX_UNFORCED,
2744 PAUSE_ON,
2745 PHY_INTERFACE_MODE_NA);
2746 if (err)
2747 return err;
2748
2749 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2750 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2751 * tunneling, determine priority by looking at 802.1p and IP
2752 * priority fields (IP prio has precedence), and set STP state
2753 * to Forwarding.
2754 *
2755 * If this is the CPU link, use DSA or EDSA tagging depending
2756 * on which tagging mode was configured.
2757 *
2758 * If this is a link to another switch, use DSA tagging mode.
2759 *
2760 * If this is the upstream port for this switch, enable
2761 * forwarding of unknown unicasts and multicasts.
2762 */
2763 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
2764 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
2765 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
2766 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
2767 if (err)
2768 return err;
2769
2770 err = mv88e6xxx_setup_port_mode(chip, port);
2771 if (err)
2772 return err;
2773
2774 err = mv88e6xxx_setup_egress_floods(chip, port);
2775 if (err)
2776 return err;
2777
2778 /* Port Control 2: don't force a good FCS, set the maximum frame size to
2779 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2780 * untagged frames on this port, do a destination address lookup on all
2781 * received packets as usual, disable ARP mirroring and don't send a
2782 * copy of all transmitted/received frames on this port to the CPU.
2783 */
2784 err = mv88e6xxx_port_set_map_da(chip, port);
2785 if (err)
2786 return err;
2787
2788 err = mv88e6xxx_setup_upstream_port(chip, port);
2789 if (err)
2790 return err;
2791
2792 err = mv88e6xxx_port_set_8021q_mode(chip, port,
2793 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);
2794 if (err)
2795 return err;
2796
2797 if (chip->info->ops->port_set_jumbo_size) {
2798 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240);
2799 if (err)
2800 return err;
2801 }
2802
2803 /* Port Association Vector: disable automatic address learning
2804 * on all user ports since they start out in standalone
2805 * mode. When joining a bridge, learning will be configured to
2806 * match the bridge port settings. Enable learning on all
2807 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the
2808 * learning process.
2809 *
2810 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData,
2811 * and RefreshLocked. I.e. setup standard automatic learning.
2812 */
2813 if (dsa_is_user_port(ds, port))
2814 reg = 0;
2815 else
2816 reg = 1 << port;
2817
2818 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
2819 reg);
2820 if (err)
2821 return err;
2822
2823 /* Egress rate control 2: disable egress rate control. */
2824 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
2825 0x0000);
2826 if (err)
2827 return err;
2828
2829 if (chip->info->ops->port_pause_limit) {
2830 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
2831 if (err)
2832 return err;
2833 }
2834
2835 if (chip->info->ops->port_disable_learn_limit) {
2836 err = chip->info->ops->port_disable_learn_limit(chip, port);
2837 if (err)
2838 return err;
2839 }
2840
2841 if (chip->info->ops->port_disable_pri_override) {
2842 err = chip->info->ops->port_disable_pri_override(chip, port);
2843 if (err)
2844 return err;
2845 }
2846
2847 if (chip->info->ops->port_tag_remap) {
2848 err = chip->info->ops->port_tag_remap(chip, port);
2849 if (err)
2850 return err;
2851 }
2852
2853 if (chip->info->ops->port_egress_rate_limiting) {
2854 err = chip->info->ops->port_egress_rate_limiting(chip, port);
2855 if (err)
2856 return err;
2857 }
2858
2859 if (chip->info->ops->port_setup_message_port) {
2860 err = chip->info->ops->port_setup_message_port(chip, port);
2861 if (err)
2862 return err;
2863 }
2864
2865 /* Port based VLAN map: give each port the same default address
2866 * database, and allow bidirectional communication between the
2867 * CPU and DSA port(s), and the other ports.
2868 */
2869 err = mv88e6xxx_port_set_fid(chip, port, 0);
2870 if (err)
2871 return err;
2872
2873 err = mv88e6xxx_port_vlan_map(chip, port);
2874 if (err)
2875 return err;
2876
2877 /* Default VLAN ID and priority: don't set a default VLAN
2878 * ID, and set the default packet priority to zero.
2879 */
2880 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
2881 }
2882
mv88e6xxx_get_max_mtu(struct dsa_switch * ds,int port)2883 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port)
2884 {
2885 struct mv88e6xxx_chip *chip = ds->priv;
2886
2887 if (chip->info->ops->port_set_jumbo_size)
2888 return 10240;
2889 else if (chip->info->ops->set_max_frame_size)
2890 return 1632;
2891 return 1522;
2892 }
2893
mv88e6xxx_change_mtu(struct dsa_switch * ds,int port,int new_mtu)2894 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
2895 {
2896 struct mv88e6xxx_chip *chip = ds->priv;
2897 int ret = 0;
2898
2899 mv88e6xxx_reg_lock(chip);
2900 if (chip->info->ops->port_set_jumbo_size)
2901 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu);
2902 else if (chip->info->ops->set_max_frame_size)
2903 ret = chip->info->ops->set_max_frame_size(chip, new_mtu);
2904 else
2905 if (new_mtu > 1522)
2906 ret = -EINVAL;
2907 mv88e6xxx_reg_unlock(chip);
2908
2909 return ret;
2910 }
2911
mv88e6xxx_port_enable(struct dsa_switch * ds,int port,struct phy_device * phydev)2912 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
2913 struct phy_device *phydev)
2914 {
2915 struct mv88e6xxx_chip *chip = ds->priv;
2916 int err;
2917
2918 mv88e6xxx_reg_lock(chip);
2919 err = mv88e6xxx_serdes_power(chip, port, true);
2920 mv88e6xxx_reg_unlock(chip);
2921
2922 return err;
2923 }
2924
mv88e6xxx_port_disable(struct dsa_switch * ds,int port)2925 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port)
2926 {
2927 struct mv88e6xxx_chip *chip = ds->priv;
2928
2929 mv88e6xxx_reg_lock(chip);
2930 if (mv88e6xxx_serdes_power(chip, port, false))
2931 dev_err(chip->dev, "failed to power off SERDES\n");
2932 mv88e6xxx_reg_unlock(chip);
2933 }
2934
mv88e6xxx_set_ageing_time(struct dsa_switch * ds,unsigned int ageing_time)2935 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2936 unsigned int ageing_time)
2937 {
2938 struct mv88e6xxx_chip *chip = ds->priv;
2939 int err;
2940
2941 mv88e6xxx_reg_lock(chip);
2942 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
2943 mv88e6xxx_reg_unlock(chip);
2944
2945 return err;
2946 }
2947
mv88e6xxx_stats_setup(struct mv88e6xxx_chip * chip)2948 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
2949 {
2950 int err;
2951
2952 /* Initialize the statistics unit */
2953 if (chip->info->ops->stats_set_histogram) {
2954 err = chip->info->ops->stats_set_histogram(chip);
2955 if (err)
2956 return err;
2957 }
2958
2959 return mv88e6xxx_g1_stats_clear(chip);
2960 }
2961
2962 /* Check if the errata has already been applied. */
mv88e6390_setup_errata_applied(struct mv88e6xxx_chip * chip)2963 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
2964 {
2965 int port;
2966 int err;
2967 u16 val;
2968
2969 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2970 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val);
2971 if (err) {
2972 dev_err(chip->dev,
2973 "Error reading hidden register: %d\n", err);
2974 return false;
2975 }
2976 if (val != 0x01c0)
2977 return false;
2978 }
2979
2980 return true;
2981 }
2982
2983 /* The 6390 copper ports have an errata which require poking magic
2984 * values into undocumented hidden registers and then performing a
2985 * software reset.
2986 */
mv88e6390_setup_errata(struct mv88e6xxx_chip * chip)2987 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip)
2988 {
2989 int port;
2990 int err;
2991
2992 if (mv88e6390_setup_errata_applied(chip))
2993 return 0;
2994
2995 /* Set the ports into blocking mode */
2996 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2997 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED);
2998 if (err)
2999 return err;
3000 }
3001
3002 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3003 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0);
3004 if (err)
3005 return err;
3006 }
3007
3008 return mv88e6xxx_software_reset(chip);
3009 }
3010
mv88e6xxx_teardown(struct dsa_switch * ds)3011 static void mv88e6xxx_teardown(struct dsa_switch *ds)
3012 {
3013 mv88e6xxx_teardown_devlink_params(ds);
3014 dsa_devlink_resources_unregister(ds);
3015 mv88e6xxx_teardown_devlink_regions(ds);
3016 }
3017
mv88e6xxx_setup(struct dsa_switch * ds)3018 static int mv88e6xxx_setup(struct dsa_switch *ds)
3019 {
3020 struct mv88e6xxx_chip *chip = ds->priv;
3021 u8 cmode;
3022 int err;
3023 int i;
3024
3025 chip->ds = ds;
3026 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
3027
3028 mv88e6xxx_reg_lock(chip);
3029
3030 if (chip->info->ops->setup_errata) {
3031 err = chip->info->ops->setup_errata(chip);
3032 if (err)
3033 goto unlock;
3034 }
3035
3036 /* Cache the cmode of each port. */
3037 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3038 if (chip->info->ops->port_get_cmode) {
3039 err = chip->info->ops->port_get_cmode(chip, i, &cmode);
3040 if (err)
3041 goto unlock;
3042
3043 chip->ports[i].cmode = cmode;
3044 }
3045 }
3046
3047 /* Setup Switch Port Registers */
3048 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3049 if (dsa_is_unused_port(ds, i))
3050 continue;
3051
3052 /* Prevent the use of an invalid port. */
3053 if (mv88e6xxx_is_invalid_port(chip, i)) {
3054 dev_err(chip->dev, "port %d is invalid\n", i);
3055 err = -EINVAL;
3056 goto unlock;
3057 }
3058
3059 err = mv88e6xxx_setup_port(chip, i);
3060 if (err)
3061 goto unlock;
3062 }
3063
3064 err = mv88e6xxx_irl_setup(chip);
3065 if (err)
3066 goto unlock;
3067
3068 err = mv88e6xxx_mac_setup(chip);
3069 if (err)
3070 goto unlock;
3071
3072 err = mv88e6xxx_phy_setup(chip);
3073 if (err)
3074 goto unlock;
3075
3076 err = mv88e6xxx_vtu_setup(chip);
3077 if (err)
3078 goto unlock;
3079
3080 err = mv88e6xxx_pvt_setup(chip);
3081 if (err)
3082 goto unlock;
3083
3084 err = mv88e6xxx_atu_setup(chip);
3085 if (err)
3086 goto unlock;
3087
3088 err = mv88e6xxx_broadcast_setup(chip, 0);
3089 if (err)
3090 goto unlock;
3091
3092 err = mv88e6xxx_pot_setup(chip);
3093 if (err)
3094 goto unlock;
3095
3096 err = mv88e6xxx_rmu_setup(chip);
3097 if (err)
3098 goto unlock;
3099
3100 err = mv88e6xxx_rsvd2cpu_setup(chip);
3101 if (err)
3102 goto unlock;
3103
3104 err = mv88e6xxx_trunk_setup(chip);
3105 if (err)
3106 goto unlock;
3107
3108 err = mv88e6xxx_devmap_setup(chip);
3109 if (err)
3110 goto unlock;
3111
3112 err = mv88e6xxx_pri_setup(chip);
3113 if (err)
3114 goto unlock;
3115
3116 /* Setup PTP Hardware Clock and timestamping */
3117 if (chip->info->ptp_support) {
3118 err = mv88e6xxx_ptp_setup(chip);
3119 if (err)
3120 goto unlock;
3121
3122 err = mv88e6xxx_hwtstamp_setup(chip);
3123 if (err)
3124 goto unlock;
3125 }
3126
3127 err = mv88e6xxx_stats_setup(chip);
3128 if (err)
3129 goto unlock;
3130
3131 unlock:
3132 mv88e6xxx_reg_unlock(chip);
3133
3134 if (err)
3135 return err;
3136
3137 /* Have to be called without holding the register lock, since
3138 * they take the devlink lock, and we later take the locks in
3139 * the reverse order when getting/setting parameters or
3140 * resource occupancy.
3141 */
3142 err = mv88e6xxx_setup_devlink_resources(ds);
3143 if (err)
3144 return err;
3145
3146 err = mv88e6xxx_setup_devlink_params(ds);
3147 if (err)
3148 goto out_resources;
3149
3150 err = mv88e6xxx_setup_devlink_regions(ds);
3151 if (err)
3152 goto out_params;
3153
3154 return 0;
3155
3156 out_params:
3157 mv88e6xxx_teardown_devlink_params(ds);
3158 out_resources:
3159 dsa_devlink_resources_unregister(ds);
3160
3161 return err;
3162 }
3163
3164 /* prod_id for switch families which do not have a PHY model number */
3165 static const u16 family_prod_id_table[] = {
3166 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
3167 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
3168 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
3169 };
3170
mv88e6xxx_mdio_read(struct mii_bus * bus,int phy,int reg)3171 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
3172 {
3173 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3174 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3175 u16 prod_id;
3176 u16 val;
3177 int err;
3178
3179 if (!chip->info->ops->phy_read)
3180 return -EOPNOTSUPP;
3181
3182 mv88e6xxx_reg_lock(chip);
3183 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
3184 mv88e6xxx_reg_unlock(chip);
3185
3186 /* Some internal PHYs don't have a model number. */
3187 if (reg == MII_PHYSID2 && !(val & 0x3f0) &&
3188 chip->info->family < ARRAY_SIZE(family_prod_id_table)) {
3189 prod_id = family_prod_id_table[chip->info->family];
3190 if (prod_id)
3191 val |= prod_id >> 4;
3192 }
3193
3194 return err ? err : val;
3195 }
3196
mv88e6xxx_mdio_write(struct mii_bus * bus,int phy,int reg,u16 val)3197 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
3198 {
3199 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3200 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3201 int err;
3202
3203 if (!chip->info->ops->phy_write)
3204 return -EOPNOTSUPP;
3205
3206 mv88e6xxx_reg_lock(chip);
3207 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
3208 mv88e6xxx_reg_unlock(chip);
3209
3210 return err;
3211 }
3212
mv88e6xxx_mdio_register(struct mv88e6xxx_chip * chip,struct device_node * np,bool external)3213 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
3214 struct device_node *np,
3215 bool external)
3216 {
3217 static int index;
3218 struct mv88e6xxx_mdio_bus *mdio_bus;
3219 struct mii_bus *bus;
3220 int err;
3221
3222 if (external) {
3223 mv88e6xxx_reg_lock(chip);
3224 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
3225 mv88e6xxx_reg_unlock(chip);
3226
3227 if (err)
3228 return err;
3229 }
3230
3231 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
3232 if (!bus)
3233 return -ENOMEM;
3234
3235 mdio_bus = bus->priv;
3236 mdio_bus->bus = bus;
3237 mdio_bus->chip = chip;
3238 INIT_LIST_HEAD(&mdio_bus->list);
3239 mdio_bus->external = external;
3240
3241 if (np) {
3242 bus->name = np->full_name;
3243 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
3244 } else {
3245 bus->name = "mv88e6xxx SMI";
3246 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3247 }
3248
3249 bus->read = mv88e6xxx_mdio_read;
3250 bus->write = mv88e6xxx_mdio_write;
3251 bus->parent = chip->dev;
3252
3253 if (!external) {
3254 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
3255 if (err)
3256 return err;
3257 }
3258
3259 err = of_mdiobus_register(bus, np);
3260 if (err) {
3261 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
3262 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3263 return err;
3264 }
3265
3266 if (external)
3267 list_add_tail(&mdio_bus->list, &chip->mdios);
3268 else
3269 list_add(&mdio_bus->list, &chip->mdios);
3270
3271 return 0;
3272 }
3273
mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip * chip)3274 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
3275
3276 {
3277 struct mv88e6xxx_mdio_bus *mdio_bus;
3278 struct mii_bus *bus;
3279
3280 list_for_each_entry(mdio_bus, &chip->mdios, list) {
3281 bus = mdio_bus->bus;
3282
3283 if (!mdio_bus->external)
3284 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3285
3286 mdiobus_unregister(bus);
3287 }
3288 }
3289
mv88e6xxx_mdios_register(struct mv88e6xxx_chip * chip,struct device_node * np)3290 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
3291 struct device_node *np)
3292 {
3293 struct device_node *child;
3294 int err;
3295
3296 /* Always register one mdio bus for the internal/default mdio
3297 * bus. This maybe represented in the device tree, but is
3298 * optional.
3299 */
3300 child = of_get_child_by_name(np, "mdio");
3301 err = mv88e6xxx_mdio_register(chip, child, false);
3302 if (err)
3303 return err;
3304
3305 /* Walk the device tree, and see if there are any other nodes
3306 * which say they are compatible with the external mdio
3307 * bus.
3308 */
3309 for_each_available_child_of_node(np, child) {
3310 if (of_device_is_compatible(
3311 child, "marvell,mv88e6xxx-mdio-external")) {
3312 err = mv88e6xxx_mdio_register(chip, child, true);
3313 if (err) {
3314 mv88e6xxx_mdios_unregister(chip);
3315 of_node_put(child);
3316 return err;
3317 }
3318 }
3319 }
3320
3321 return 0;
3322 }
3323
mv88e6xxx_get_eeprom_len(struct dsa_switch * ds)3324 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3325 {
3326 struct mv88e6xxx_chip *chip = ds->priv;
3327
3328 return chip->eeprom_len;
3329 }
3330
mv88e6xxx_get_eeprom(struct dsa_switch * ds,struct ethtool_eeprom * eeprom,u8 * data)3331 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3332 struct ethtool_eeprom *eeprom, u8 *data)
3333 {
3334 struct mv88e6xxx_chip *chip = ds->priv;
3335 int err;
3336
3337 if (!chip->info->ops->get_eeprom)
3338 return -EOPNOTSUPP;
3339
3340 mv88e6xxx_reg_lock(chip);
3341 err = chip->info->ops->get_eeprom(chip, eeprom, data);
3342 mv88e6xxx_reg_unlock(chip);
3343
3344 if (err)
3345 return err;
3346
3347 eeprom->magic = 0xc3ec4951;
3348
3349 return 0;
3350 }
3351
mv88e6xxx_set_eeprom(struct dsa_switch * ds,struct ethtool_eeprom * eeprom,u8 * data)3352 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3353 struct ethtool_eeprom *eeprom, u8 *data)
3354 {
3355 struct mv88e6xxx_chip *chip = ds->priv;
3356 int err;
3357
3358 if (!chip->info->ops->set_eeprom)
3359 return -EOPNOTSUPP;
3360
3361 if (eeprom->magic != 0xc3ec4951)
3362 return -EINVAL;
3363
3364 mv88e6xxx_reg_lock(chip);
3365 err = chip->info->ops->set_eeprom(chip, eeprom, data);
3366 mv88e6xxx_reg_unlock(chip);
3367
3368 return err;
3369 }
3370
3371 static const struct mv88e6xxx_ops mv88e6085_ops = {
3372 /* MV88E6XXX_FAMILY_6097 */
3373 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3374 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3375 .irl_init_all = mv88e6352_g2_irl_init_all,
3376 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3377 .phy_read = mv88e6185_phy_ppu_read,
3378 .phy_write = mv88e6185_phy_ppu_write,
3379 .port_set_link = mv88e6xxx_port_set_link,
3380 .port_sync_link = mv88e6xxx_port_sync_link,
3381 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3382 .port_tag_remap = mv88e6095_port_tag_remap,
3383 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3384 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3385 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
3386 .port_set_ether_type = mv88e6351_port_set_ether_type,
3387 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3388 .port_pause_limit = mv88e6097_port_pause_limit,
3389 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3390 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3391 .port_get_cmode = mv88e6185_port_get_cmode,
3392 .port_setup_message_port = mv88e6xxx_setup_message_port,
3393 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3394 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3395 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3396 .stats_get_strings = mv88e6095_stats_get_strings,
3397 .stats_get_stats = mv88e6095_stats_get_stats,
3398 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3399 .set_egress_port = mv88e6095_g1_set_egress_port,
3400 .watchdog_ops = &mv88e6097_watchdog_ops,
3401 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3402 .pot_clear = mv88e6xxx_g2_pot_clear,
3403 .ppu_enable = mv88e6185_g1_ppu_enable,
3404 .ppu_disable = mv88e6185_g1_ppu_disable,
3405 .reset = mv88e6185_g1_reset,
3406 .rmu_disable = mv88e6085_g1_rmu_disable,
3407 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3408 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3409 .phylink_validate = mv88e6185_phylink_validate,
3410 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3411 };
3412
3413 static const struct mv88e6xxx_ops mv88e6095_ops = {
3414 /* MV88E6XXX_FAMILY_6095 */
3415 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3416 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3417 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3418 .phy_read = mv88e6185_phy_ppu_read,
3419 .phy_write = mv88e6185_phy_ppu_write,
3420 .port_set_link = mv88e6xxx_port_set_link,
3421 .port_sync_link = mv88e6185_port_sync_link,
3422 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3423 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3424 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
3425 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
3426 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
3427 .port_get_cmode = mv88e6185_port_get_cmode,
3428 .port_setup_message_port = mv88e6xxx_setup_message_port,
3429 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3430 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3431 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3432 .stats_get_strings = mv88e6095_stats_get_strings,
3433 .stats_get_stats = mv88e6095_stats_get_stats,
3434 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3435 .serdes_power = mv88e6185_serdes_power,
3436 .serdes_get_lane = mv88e6185_serdes_get_lane,
3437 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state,
3438 .ppu_enable = mv88e6185_g1_ppu_enable,
3439 .ppu_disable = mv88e6185_g1_ppu_disable,
3440 .reset = mv88e6185_g1_reset,
3441 .vtu_getnext = mv88e6185_g1_vtu_getnext,
3442 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3443 .phylink_validate = mv88e6185_phylink_validate,
3444 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3445 };
3446
3447 static const struct mv88e6xxx_ops mv88e6097_ops = {
3448 /* MV88E6XXX_FAMILY_6097 */
3449 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3450 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3451 .irl_init_all = mv88e6352_g2_irl_init_all,
3452 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3453 .phy_read = mv88e6xxx_g2_smi_phy_read,
3454 .phy_write = mv88e6xxx_g2_smi_phy_write,
3455 .port_set_link = mv88e6xxx_port_set_link,
3456 .port_sync_link = mv88e6185_port_sync_link,
3457 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3458 .port_tag_remap = mv88e6095_port_tag_remap,
3459 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3460 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3461 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
3462 .port_set_ether_type = mv88e6351_port_set_ether_type,
3463 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
3464 .port_pause_limit = mv88e6097_port_pause_limit,
3465 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3466 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3467 .port_get_cmode = mv88e6185_port_get_cmode,
3468 .port_setup_message_port = mv88e6xxx_setup_message_port,
3469 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3470 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3471 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3472 .stats_get_strings = mv88e6095_stats_get_strings,
3473 .stats_get_stats = mv88e6095_stats_get_stats,
3474 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3475 .set_egress_port = mv88e6095_g1_set_egress_port,
3476 .watchdog_ops = &mv88e6097_watchdog_ops,
3477 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3478 .serdes_power = mv88e6185_serdes_power,
3479 .serdes_get_lane = mv88e6185_serdes_get_lane,
3480 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state,
3481 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3482 .serdes_irq_enable = mv88e6097_serdes_irq_enable,
3483 .serdes_irq_status = mv88e6097_serdes_irq_status,
3484 .pot_clear = mv88e6xxx_g2_pot_clear,
3485 .reset = mv88e6352_g1_reset,
3486 .rmu_disable = mv88e6085_g1_rmu_disable,
3487 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3488 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3489 .phylink_validate = mv88e6185_phylink_validate,
3490 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3491 };
3492
3493 static const struct mv88e6xxx_ops mv88e6123_ops = {
3494 /* MV88E6XXX_FAMILY_6165 */
3495 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3496 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3497 .irl_init_all = mv88e6352_g2_irl_init_all,
3498 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3499 .phy_read = mv88e6xxx_g2_smi_phy_read,
3500 .phy_write = mv88e6xxx_g2_smi_phy_write,
3501 .port_set_link = mv88e6xxx_port_set_link,
3502 .port_sync_link = mv88e6xxx_port_sync_link,
3503 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3504 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3505 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3506 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
3507 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3508 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3509 .port_get_cmode = mv88e6185_port_get_cmode,
3510 .port_setup_message_port = mv88e6xxx_setup_message_port,
3511 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3512 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3513 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3514 .stats_get_strings = mv88e6095_stats_get_strings,
3515 .stats_get_stats = mv88e6095_stats_get_stats,
3516 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3517 .set_egress_port = mv88e6095_g1_set_egress_port,
3518 .watchdog_ops = &mv88e6097_watchdog_ops,
3519 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3520 .pot_clear = mv88e6xxx_g2_pot_clear,
3521 .reset = mv88e6352_g1_reset,
3522 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3523 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3524 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3525 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3526 .phylink_validate = mv88e6185_phylink_validate,
3527 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3528 };
3529
3530 static const struct mv88e6xxx_ops mv88e6131_ops = {
3531 /* MV88E6XXX_FAMILY_6185 */
3532 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3533 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3534 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3535 .phy_read = mv88e6185_phy_ppu_read,
3536 .phy_write = mv88e6185_phy_ppu_write,
3537 .port_set_link = mv88e6xxx_port_set_link,
3538 .port_sync_link = mv88e6xxx_port_sync_link,
3539 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3540 .port_tag_remap = mv88e6095_port_tag_remap,
3541 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3542 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
3543 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
3544 .port_set_ether_type = mv88e6351_port_set_ether_type,
3545 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
3546 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3547 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3548 .port_pause_limit = mv88e6097_port_pause_limit,
3549 .port_set_pause = mv88e6185_port_set_pause,
3550 .port_get_cmode = mv88e6185_port_get_cmode,
3551 .port_setup_message_port = mv88e6xxx_setup_message_port,
3552 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3553 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3554 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3555 .stats_get_strings = mv88e6095_stats_get_strings,
3556 .stats_get_stats = mv88e6095_stats_get_stats,
3557 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3558 .set_egress_port = mv88e6095_g1_set_egress_port,
3559 .watchdog_ops = &mv88e6097_watchdog_ops,
3560 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3561 .ppu_enable = mv88e6185_g1_ppu_enable,
3562 .set_cascade_port = mv88e6185_g1_set_cascade_port,
3563 .ppu_disable = mv88e6185_g1_ppu_disable,
3564 .reset = mv88e6185_g1_reset,
3565 .vtu_getnext = mv88e6185_g1_vtu_getnext,
3566 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3567 .phylink_validate = mv88e6185_phylink_validate,
3568 };
3569
3570 static const struct mv88e6xxx_ops mv88e6141_ops = {
3571 /* MV88E6XXX_FAMILY_6341 */
3572 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3573 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3574 .irl_init_all = mv88e6352_g2_irl_init_all,
3575 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3576 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3577 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3578 .phy_read = mv88e6xxx_g2_smi_phy_read,
3579 .phy_write = mv88e6xxx_g2_smi_phy_write,
3580 .port_set_link = mv88e6xxx_port_set_link,
3581 .port_sync_link = mv88e6xxx_port_sync_link,
3582 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3583 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
3584 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
3585 .port_tag_remap = mv88e6095_port_tag_remap,
3586 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3587 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3588 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
3589 .port_set_ether_type = mv88e6351_port_set_ether_type,
3590 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3591 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3592 .port_pause_limit = mv88e6097_port_pause_limit,
3593 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3594 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3595 .port_get_cmode = mv88e6352_port_get_cmode,
3596 .port_set_cmode = mv88e6341_port_set_cmode,
3597 .port_setup_message_port = mv88e6xxx_setup_message_port,
3598 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3599 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3600 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3601 .stats_get_strings = mv88e6320_stats_get_strings,
3602 .stats_get_stats = mv88e6390_stats_get_stats,
3603 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3604 .set_egress_port = mv88e6390_g1_set_egress_port,
3605 .watchdog_ops = &mv88e6390_watchdog_ops,
3606 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3607 .pot_clear = mv88e6xxx_g2_pot_clear,
3608 .reset = mv88e6352_g1_reset,
3609 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3610 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3611 .serdes_power = mv88e6390_serdes_power,
3612 .serdes_get_lane = mv88e6341_serdes_get_lane,
3613 /* Check status register pause & lpa register */
3614 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
3615 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
3616 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
3617 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
3618 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3619 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
3620 .serdes_irq_status = mv88e6390_serdes_irq_status,
3621 .gpio_ops = &mv88e6352_gpio_ops,
3622 .phylink_validate = mv88e6341_phylink_validate,
3623 };
3624
3625 static const struct mv88e6xxx_ops mv88e6161_ops = {
3626 /* MV88E6XXX_FAMILY_6165 */
3627 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3628 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3629 .irl_init_all = mv88e6352_g2_irl_init_all,
3630 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3631 .phy_read = mv88e6xxx_g2_smi_phy_read,
3632 .phy_write = mv88e6xxx_g2_smi_phy_write,
3633 .port_set_link = mv88e6xxx_port_set_link,
3634 .port_sync_link = mv88e6xxx_port_sync_link,
3635 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3636 .port_tag_remap = mv88e6095_port_tag_remap,
3637 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3638 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3639 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
3640 .port_set_ether_type = mv88e6351_port_set_ether_type,
3641 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3642 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3643 .port_pause_limit = mv88e6097_port_pause_limit,
3644 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3645 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3646 .port_get_cmode = mv88e6185_port_get_cmode,
3647 .port_setup_message_port = mv88e6xxx_setup_message_port,
3648 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3649 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3650 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3651 .stats_get_strings = mv88e6095_stats_get_strings,
3652 .stats_get_stats = mv88e6095_stats_get_stats,
3653 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3654 .set_egress_port = mv88e6095_g1_set_egress_port,
3655 .watchdog_ops = &mv88e6097_watchdog_ops,
3656 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3657 .pot_clear = mv88e6xxx_g2_pot_clear,
3658 .reset = mv88e6352_g1_reset,
3659 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3660 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3661 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3662 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3663 .avb_ops = &mv88e6165_avb_ops,
3664 .ptp_ops = &mv88e6165_ptp_ops,
3665 .phylink_validate = mv88e6185_phylink_validate,
3666 };
3667
3668 static const struct mv88e6xxx_ops mv88e6165_ops = {
3669 /* MV88E6XXX_FAMILY_6165 */
3670 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3671 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3672 .irl_init_all = mv88e6352_g2_irl_init_all,
3673 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3674 .phy_read = mv88e6165_phy_read,
3675 .phy_write = mv88e6165_phy_write,
3676 .port_set_link = mv88e6xxx_port_set_link,
3677 .port_sync_link = mv88e6xxx_port_sync_link,
3678 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3679 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3680 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3681 .port_get_cmode = mv88e6185_port_get_cmode,
3682 .port_setup_message_port = mv88e6xxx_setup_message_port,
3683 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3684 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3685 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3686 .stats_get_strings = mv88e6095_stats_get_strings,
3687 .stats_get_stats = mv88e6095_stats_get_stats,
3688 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3689 .set_egress_port = mv88e6095_g1_set_egress_port,
3690 .watchdog_ops = &mv88e6097_watchdog_ops,
3691 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3692 .pot_clear = mv88e6xxx_g2_pot_clear,
3693 .reset = mv88e6352_g1_reset,
3694 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3695 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3696 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3697 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3698 .avb_ops = &mv88e6165_avb_ops,
3699 .ptp_ops = &mv88e6165_ptp_ops,
3700 .phylink_validate = mv88e6185_phylink_validate,
3701 };
3702
3703 static const struct mv88e6xxx_ops mv88e6171_ops = {
3704 /* MV88E6XXX_FAMILY_6351 */
3705 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3706 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3707 .irl_init_all = mv88e6352_g2_irl_init_all,
3708 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3709 .phy_read = mv88e6xxx_g2_smi_phy_read,
3710 .phy_write = mv88e6xxx_g2_smi_phy_write,
3711 .port_set_link = mv88e6xxx_port_set_link,
3712 .port_sync_link = mv88e6xxx_port_sync_link,
3713 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3714 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3715 .port_tag_remap = mv88e6095_port_tag_remap,
3716 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3717 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3718 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
3719 .port_set_ether_type = mv88e6351_port_set_ether_type,
3720 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3721 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3722 .port_pause_limit = mv88e6097_port_pause_limit,
3723 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3724 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3725 .port_get_cmode = mv88e6352_port_get_cmode,
3726 .port_setup_message_port = mv88e6xxx_setup_message_port,
3727 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3728 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3729 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3730 .stats_get_strings = mv88e6095_stats_get_strings,
3731 .stats_get_stats = mv88e6095_stats_get_stats,
3732 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3733 .set_egress_port = mv88e6095_g1_set_egress_port,
3734 .watchdog_ops = &mv88e6097_watchdog_ops,
3735 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3736 .pot_clear = mv88e6xxx_g2_pot_clear,
3737 .reset = mv88e6352_g1_reset,
3738 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3739 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3740 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3741 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3742 .phylink_validate = mv88e6185_phylink_validate,
3743 };
3744
3745 static const struct mv88e6xxx_ops mv88e6172_ops = {
3746 /* MV88E6XXX_FAMILY_6352 */
3747 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3748 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3749 .irl_init_all = mv88e6352_g2_irl_init_all,
3750 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3751 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3752 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3753 .phy_read = mv88e6xxx_g2_smi_phy_read,
3754 .phy_write = mv88e6xxx_g2_smi_phy_write,
3755 .port_set_link = mv88e6xxx_port_set_link,
3756 .port_sync_link = mv88e6xxx_port_sync_link,
3757 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3758 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
3759 .port_tag_remap = mv88e6095_port_tag_remap,
3760 .port_set_policy = mv88e6352_port_set_policy,
3761 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3762 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3763 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
3764 .port_set_ether_type = mv88e6351_port_set_ether_type,
3765 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3766 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3767 .port_pause_limit = mv88e6097_port_pause_limit,
3768 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3769 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3770 .port_get_cmode = mv88e6352_port_get_cmode,
3771 .port_setup_message_port = mv88e6xxx_setup_message_port,
3772 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3773 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3774 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3775 .stats_get_strings = mv88e6095_stats_get_strings,
3776 .stats_get_stats = mv88e6095_stats_get_stats,
3777 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3778 .set_egress_port = mv88e6095_g1_set_egress_port,
3779 .watchdog_ops = &mv88e6097_watchdog_ops,
3780 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3781 .pot_clear = mv88e6xxx_g2_pot_clear,
3782 .reset = mv88e6352_g1_reset,
3783 .rmu_disable = mv88e6352_g1_rmu_disable,
3784 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3785 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3786 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3787 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3788 .serdes_get_lane = mv88e6352_serdes_get_lane,
3789 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
3790 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
3791 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
3792 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
3793 .serdes_power = mv88e6352_serdes_power,
3794 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
3795 .serdes_get_regs = mv88e6352_serdes_get_regs,
3796 .gpio_ops = &mv88e6352_gpio_ops,
3797 .phylink_validate = mv88e6352_phylink_validate,
3798 };
3799
3800 static const struct mv88e6xxx_ops mv88e6175_ops = {
3801 /* MV88E6XXX_FAMILY_6351 */
3802 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3803 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3804 .irl_init_all = mv88e6352_g2_irl_init_all,
3805 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3806 .phy_read = mv88e6xxx_g2_smi_phy_read,
3807 .phy_write = mv88e6xxx_g2_smi_phy_write,
3808 .port_set_link = mv88e6xxx_port_set_link,
3809 .port_sync_link = mv88e6xxx_port_sync_link,
3810 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3811 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3812 .port_tag_remap = mv88e6095_port_tag_remap,
3813 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3814 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3815 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
3816 .port_set_ether_type = mv88e6351_port_set_ether_type,
3817 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3818 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3819 .port_pause_limit = mv88e6097_port_pause_limit,
3820 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3821 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3822 .port_get_cmode = mv88e6352_port_get_cmode,
3823 .port_setup_message_port = mv88e6xxx_setup_message_port,
3824 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3825 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3826 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3827 .stats_get_strings = mv88e6095_stats_get_strings,
3828 .stats_get_stats = mv88e6095_stats_get_stats,
3829 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3830 .set_egress_port = mv88e6095_g1_set_egress_port,
3831 .watchdog_ops = &mv88e6097_watchdog_ops,
3832 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3833 .pot_clear = mv88e6xxx_g2_pot_clear,
3834 .reset = mv88e6352_g1_reset,
3835 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3836 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3837 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3838 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3839 .phylink_validate = mv88e6185_phylink_validate,
3840 };
3841
3842 static const struct mv88e6xxx_ops mv88e6176_ops = {
3843 /* MV88E6XXX_FAMILY_6352 */
3844 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3845 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3846 .irl_init_all = mv88e6352_g2_irl_init_all,
3847 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3848 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3849 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3850 .phy_read = mv88e6xxx_g2_smi_phy_read,
3851 .phy_write = mv88e6xxx_g2_smi_phy_write,
3852 .port_set_link = mv88e6xxx_port_set_link,
3853 .port_sync_link = mv88e6xxx_port_sync_link,
3854 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3855 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
3856 .port_tag_remap = mv88e6095_port_tag_remap,
3857 .port_set_policy = mv88e6352_port_set_policy,
3858 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3859 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3860 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
3861 .port_set_ether_type = mv88e6351_port_set_ether_type,
3862 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3863 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3864 .port_pause_limit = mv88e6097_port_pause_limit,
3865 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3866 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3867 .port_get_cmode = mv88e6352_port_get_cmode,
3868 .port_setup_message_port = mv88e6xxx_setup_message_port,
3869 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3870 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3871 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3872 .stats_get_strings = mv88e6095_stats_get_strings,
3873 .stats_get_stats = mv88e6095_stats_get_stats,
3874 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3875 .set_egress_port = mv88e6095_g1_set_egress_port,
3876 .watchdog_ops = &mv88e6097_watchdog_ops,
3877 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3878 .pot_clear = mv88e6xxx_g2_pot_clear,
3879 .reset = mv88e6352_g1_reset,
3880 .rmu_disable = mv88e6352_g1_rmu_disable,
3881 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3882 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3883 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3884 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3885 .serdes_get_lane = mv88e6352_serdes_get_lane,
3886 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
3887 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
3888 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
3889 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
3890 .serdes_power = mv88e6352_serdes_power,
3891 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
3892 .serdes_irq_enable = mv88e6352_serdes_irq_enable,
3893 .serdes_irq_status = mv88e6352_serdes_irq_status,
3894 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
3895 .serdes_get_regs = mv88e6352_serdes_get_regs,
3896 .gpio_ops = &mv88e6352_gpio_ops,
3897 .phylink_validate = mv88e6352_phylink_validate,
3898 };
3899
3900 static const struct mv88e6xxx_ops mv88e6185_ops = {
3901 /* MV88E6XXX_FAMILY_6185 */
3902 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3903 .ip_pri_map = mv88e6085_g1_ip_pri_map,
3904 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3905 .phy_read = mv88e6185_phy_ppu_read,
3906 .phy_write = mv88e6185_phy_ppu_write,
3907 .port_set_link = mv88e6xxx_port_set_link,
3908 .port_sync_link = mv88e6185_port_sync_link,
3909 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3910 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3911 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
3912 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
3913 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
3914 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
3915 .port_set_pause = mv88e6185_port_set_pause,
3916 .port_get_cmode = mv88e6185_port_get_cmode,
3917 .port_setup_message_port = mv88e6xxx_setup_message_port,
3918 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3919 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3920 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3921 .stats_get_strings = mv88e6095_stats_get_strings,
3922 .stats_get_stats = mv88e6095_stats_get_stats,
3923 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3924 .set_egress_port = mv88e6095_g1_set_egress_port,
3925 .watchdog_ops = &mv88e6097_watchdog_ops,
3926 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3927 .serdes_power = mv88e6185_serdes_power,
3928 .serdes_get_lane = mv88e6185_serdes_get_lane,
3929 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state,
3930 .set_cascade_port = mv88e6185_g1_set_cascade_port,
3931 .ppu_enable = mv88e6185_g1_ppu_enable,
3932 .ppu_disable = mv88e6185_g1_ppu_disable,
3933 .reset = mv88e6185_g1_reset,
3934 .vtu_getnext = mv88e6185_g1_vtu_getnext,
3935 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3936 .phylink_validate = mv88e6185_phylink_validate,
3937 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3938 };
3939
3940 static const struct mv88e6xxx_ops mv88e6190_ops = {
3941 /* MV88E6XXX_FAMILY_6390 */
3942 .setup_errata = mv88e6390_setup_errata,
3943 .irl_init_all = mv88e6390_g2_irl_init_all,
3944 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3945 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3946 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3947 .phy_read = mv88e6xxx_g2_smi_phy_read,
3948 .phy_write = mv88e6xxx_g2_smi_phy_write,
3949 .port_set_link = mv88e6xxx_port_set_link,
3950 .port_sync_link = mv88e6xxx_port_sync_link,
3951 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3952 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
3953 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
3954 .port_tag_remap = mv88e6390_port_tag_remap,
3955 .port_set_policy = mv88e6352_port_set_policy,
3956 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3957 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
3958 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
3959 .port_set_ether_type = mv88e6351_port_set_ether_type,
3960 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3961 .port_pause_limit = mv88e6390_port_pause_limit,
3962 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3963 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3964 .port_get_cmode = mv88e6352_port_get_cmode,
3965 .port_set_cmode = mv88e6390_port_set_cmode,
3966 .port_setup_message_port = mv88e6xxx_setup_message_port,
3967 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3968 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3969 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3970 .stats_get_strings = mv88e6320_stats_get_strings,
3971 .stats_get_stats = mv88e6390_stats_get_stats,
3972 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3973 .set_egress_port = mv88e6390_g1_set_egress_port,
3974 .watchdog_ops = &mv88e6390_watchdog_ops,
3975 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3976 .pot_clear = mv88e6xxx_g2_pot_clear,
3977 .reset = mv88e6352_g1_reset,
3978 .rmu_disable = mv88e6390_g1_rmu_disable,
3979 .atu_get_hash = mv88e6165_g1_atu_get_hash,
3980 .atu_set_hash = mv88e6165_g1_atu_set_hash,
3981 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3982 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3983 .serdes_power = mv88e6390_serdes_power,
3984 .serdes_get_lane = mv88e6390_serdes_get_lane,
3985 /* Check status register pause & lpa register */
3986 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
3987 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
3988 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
3989 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
3990 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3991 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
3992 .serdes_irq_status = mv88e6390_serdes_irq_status,
3993 .serdes_get_strings = mv88e6390_serdes_get_strings,
3994 .serdes_get_stats = mv88e6390_serdes_get_stats,
3995 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
3996 .serdes_get_regs = mv88e6390_serdes_get_regs,
3997 .gpio_ops = &mv88e6352_gpio_ops,
3998 .phylink_validate = mv88e6390_phylink_validate,
3999 };
4000
4001 static const struct mv88e6xxx_ops mv88e6190x_ops = {
4002 /* MV88E6XXX_FAMILY_6390 */
4003 .setup_errata = mv88e6390_setup_errata,
4004 .irl_init_all = mv88e6390_g2_irl_init_all,
4005 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4006 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4007 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4008 .phy_read = mv88e6xxx_g2_smi_phy_read,
4009 .phy_write = mv88e6xxx_g2_smi_phy_write,
4010 .port_set_link = mv88e6xxx_port_set_link,
4011 .port_sync_link = mv88e6xxx_port_sync_link,
4012 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4013 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
4014 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
4015 .port_tag_remap = mv88e6390_port_tag_remap,
4016 .port_set_policy = mv88e6352_port_set_policy,
4017 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4018 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4019 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4020 .port_set_ether_type = mv88e6351_port_set_ether_type,
4021 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4022 .port_pause_limit = mv88e6390_port_pause_limit,
4023 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4024 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4025 .port_get_cmode = mv88e6352_port_get_cmode,
4026 .port_set_cmode = mv88e6390x_port_set_cmode,
4027 .port_setup_message_port = mv88e6xxx_setup_message_port,
4028 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4029 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4030 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4031 .stats_get_strings = mv88e6320_stats_get_strings,
4032 .stats_get_stats = mv88e6390_stats_get_stats,
4033 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4034 .set_egress_port = mv88e6390_g1_set_egress_port,
4035 .watchdog_ops = &mv88e6390_watchdog_ops,
4036 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4037 .pot_clear = mv88e6xxx_g2_pot_clear,
4038 .reset = mv88e6352_g1_reset,
4039 .rmu_disable = mv88e6390_g1_rmu_disable,
4040 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4041 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4042 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4043 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4044 .serdes_power = mv88e6390_serdes_power,
4045 .serdes_get_lane = mv88e6390x_serdes_get_lane,
4046 /* Check status register pause & lpa register */
4047 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4048 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4049 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4050 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4051 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4052 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4053 .serdes_irq_status = mv88e6390_serdes_irq_status,
4054 .serdes_get_strings = mv88e6390_serdes_get_strings,
4055 .serdes_get_stats = mv88e6390_serdes_get_stats,
4056 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4057 .serdes_get_regs = mv88e6390_serdes_get_regs,
4058 .gpio_ops = &mv88e6352_gpio_ops,
4059 .phylink_validate = mv88e6390x_phylink_validate,
4060 };
4061
4062 static const struct mv88e6xxx_ops mv88e6191_ops = {
4063 /* MV88E6XXX_FAMILY_6390 */
4064 .setup_errata = mv88e6390_setup_errata,
4065 .irl_init_all = mv88e6390_g2_irl_init_all,
4066 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4067 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4068 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4069 .phy_read = mv88e6xxx_g2_smi_phy_read,
4070 .phy_write = mv88e6xxx_g2_smi_phy_write,
4071 .port_set_link = mv88e6xxx_port_set_link,
4072 .port_sync_link = mv88e6xxx_port_sync_link,
4073 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4074 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4075 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4076 .port_tag_remap = mv88e6390_port_tag_remap,
4077 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4078 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4079 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4080 .port_set_ether_type = mv88e6351_port_set_ether_type,
4081 .port_pause_limit = mv88e6390_port_pause_limit,
4082 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4083 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4084 .port_get_cmode = mv88e6352_port_get_cmode,
4085 .port_set_cmode = mv88e6390_port_set_cmode,
4086 .port_setup_message_port = mv88e6xxx_setup_message_port,
4087 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4088 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4089 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4090 .stats_get_strings = mv88e6320_stats_get_strings,
4091 .stats_get_stats = mv88e6390_stats_get_stats,
4092 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4093 .set_egress_port = mv88e6390_g1_set_egress_port,
4094 .watchdog_ops = &mv88e6390_watchdog_ops,
4095 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4096 .pot_clear = mv88e6xxx_g2_pot_clear,
4097 .reset = mv88e6352_g1_reset,
4098 .rmu_disable = mv88e6390_g1_rmu_disable,
4099 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4100 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4101 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4102 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4103 .serdes_power = mv88e6390_serdes_power,
4104 .serdes_get_lane = mv88e6390_serdes_get_lane,
4105 /* Check status register pause & lpa register */
4106 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4107 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4108 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4109 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4110 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4111 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4112 .serdes_irq_status = mv88e6390_serdes_irq_status,
4113 .serdes_get_strings = mv88e6390_serdes_get_strings,
4114 .serdes_get_stats = mv88e6390_serdes_get_stats,
4115 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4116 .serdes_get_regs = mv88e6390_serdes_get_regs,
4117 .avb_ops = &mv88e6390_avb_ops,
4118 .ptp_ops = &mv88e6352_ptp_ops,
4119 .phylink_validate = mv88e6390_phylink_validate,
4120 };
4121
4122 static const struct mv88e6xxx_ops mv88e6240_ops = {
4123 /* MV88E6XXX_FAMILY_6352 */
4124 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4125 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4126 .irl_init_all = mv88e6352_g2_irl_init_all,
4127 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4128 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4129 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4130 .phy_read = mv88e6xxx_g2_smi_phy_read,
4131 .phy_write = mv88e6xxx_g2_smi_phy_write,
4132 .port_set_link = mv88e6xxx_port_set_link,
4133 .port_sync_link = mv88e6xxx_port_sync_link,
4134 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4135 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4136 .port_tag_remap = mv88e6095_port_tag_remap,
4137 .port_set_policy = mv88e6352_port_set_policy,
4138 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4139 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4140 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4141 .port_set_ether_type = mv88e6351_port_set_ether_type,
4142 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4143 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4144 .port_pause_limit = mv88e6097_port_pause_limit,
4145 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4146 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4147 .port_get_cmode = mv88e6352_port_get_cmode,
4148 .port_setup_message_port = mv88e6xxx_setup_message_port,
4149 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4150 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4151 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4152 .stats_get_strings = mv88e6095_stats_get_strings,
4153 .stats_get_stats = mv88e6095_stats_get_stats,
4154 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4155 .set_egress_port = mv88e6095_g1_set_egress_port,
4156 .watchdog_ops = &mv88e6097_watchdog_ops,
4157 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4158 .pot_clear = mv88e6xxx_g2_pot_clear,
4159 .reset = mv88e6352_g1_reset,
4160 .rmu_disable = mv88e6352_g1_rmu_disable,
4161 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4162 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4163 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4164 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4165 .serdes_get_lane = mv88e6352_serdes_get_lane,
4166 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
4167 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
4168 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
4169 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
4170 .serdes_power = mv88e6352_serdes_power,
4171 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4172 .serdes_irq_enable = mv88e6352_serdes_irq_enable,
4173 .serdes_irq_status = mv88e6352_serdes_irq_status,
4174 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4175 .serdes_get_regs = mv88e6352_serdes_get_regs,
4176 .gpio_ops = &mv88e6352_gpio_ops,
4177 .avb_ops = &mv88e6352_avb_ops,
4178 .ptp_ops = &mv88e6352_ptp_ops,
4179 .phylink_validate = mv88e6352_phylink_validate,
4180 };
4181
4182 static const struct mv88e6xxx_ops mv88e6250_ops = {
4183 /* MV88E6XXX_FAMILY_6250 */
4184 .ieee_pri_map = mv88e6250_g1_ieee_pri_map,
4185 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4186 .irl_init_all = mv88e6352_g2_irl_init_all,
4187 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4188 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4189 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4190 .phy_read = mv88e6xxx_g2_smi_phy_read,
4191 .phy_write = mv88e6xxx_g2_smi_phy_write,
4192 .port_set_link = mv88e6xxx_port_set_link,
4193 .port_sync_link = mv88e6xxx_port_sync_link,
4194 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4195 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex,
4196 .port_tag_remap = mv88e6095_port_tag_remap,
4197 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4198 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4199 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4200 .port_set_ether_type = mv88e6351_port_set_ether_type,
4201 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4202 .port_pause_limit = mv88e6097_port_pause_limit,
4203 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4204 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4205 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4206 .stats_get_sset_count = mv88e6250_stats_get_sset_count,
4207 .stats_get_strings = mv88e6250_stats_get_strings,
4208 .stats_get_stats = mv88e6250_stats_get_stats,
4209 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4210 .set_egress_port = mv88e6095_g1_set_egress_port,
4211 .watchdog_ops = &mv88e6250_watchdog_ops,
4212 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4213 .pot_clear = mv88e6xxx_g2_pot_clear,
4214 .reset = mv88e6250_g1_reset,
4215 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4216 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4217 .avb_ops = &mv88e6352_avb_ops,
4218 .ptp_ops = &mv88e6250_ptp_ops,
4219 .phylink_validate = mv88e6065_phylink_validate,
4220 };
4221
4222 static const struct mv88e6xxx_ops mv88e6290_ops = {
4223 /* MV88E6XXX_FAMILY_6390 */
4224 .setup_errata = mv88e6390_setup_errata,
4225 .irl_init_all = mv88e6390_g2_irl_init_all,
4226 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4227 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4228 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4229 .phy_read = mv88e6xxx_g2_smi_phy_read,
4230 .phy_write = mv88e6xxx_g2_smi_phy_write,
4231 .port_set_link = mv88e6xxx_port_set_link,
4232 .port_sync_link = mv88e6xxx_port_sync_link,
4233 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4234 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4235 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4236 .port_tag_remap = mv88e6390_port_tag_remap,
4237 .port_set_policy = mv88e6352_port_set_policy,
4238 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4239 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4240 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4241 .port_set_ether_type = mv88e6351_port_set_ether_type,
4242 .port_pause_limit = mv88e6390_port_pause_limit,
4243 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4244 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4245 .port_get_cmode = mv88e6352_port_get_cmode,
4246 .port_set_cmode = mv88e6390_port_set_cmode,
4247 .port_setup_message_port = mv88e6xxx_setup_message_port,
4248 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4249 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4250 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4251 .stats_get_strings = mv88e6320_stats_get_strings,
4252 .stats_get_stats = mv88e6390_stats_get_stats,
4253 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4254 .set_egress_port = mv88e6390_g1_set_egress_port,
4255 .watchdog_ops = &mv88e6390_watchdog_ops,
4256 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4257 .pot_clear = mv88e6xxx_g2_pot_clear,
4258 .reset = mv88e6352_g1_reset,
4259 .rmu_disable = mv88e6390_g1_rmu_disable,
4260 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4261 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4262 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4263 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4264 .serdes_power = mv88e6390_serdes_power,
4265 .serdes_get_lane = mv88e6390_serdes_get_lane,
4266 /* Check status register pause & lpa register */
4267 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4268 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4269 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4270 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4271 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4272 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4273 .serdes_irq_status = mv88e6390_serdes_irq_status,
4274 .serdes_get_strings = mv88e6390_serdes_get_strings,
4275 .serdes_get_stats = mv88e6390_serdes_get_stats,
4276 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4277 .serdes_get_regs = mv88e6390_serdes_get_regs,
4278 .gpio_ops = &mv88e6352_gpio_ops,
4279 .avb_ops = &mv88e6390_avb_ops,
4280 .ptp_ops = &mv88e6352_ptp_ops,
4281 .phylink_validate = mv88e6390_phylink_validate,
4282 };
4283
4284 static const struct mv88e6xxx_ops mv88e6320_ops = {
4285 /* MV88E6XXX_FAMILY_6320 */
4286 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4287 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4288 .irl_init_all = mv88e6352_g2_irl_init_all,
4289 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4290 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4291 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4292 .phy_read = mv88e6xxx_g2_smi_phy_read,
4293 .phy_write = mv88e6xxx_g2_smi_phy_write,
4294 .port_set_link = mv88e6xxx_port_set_link,
4295 .port_sync_link = mv88e6xxx_port_sync_link,
4296 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4297 .port_tag_remap = mv88e6095_port_tag_remap,
4298 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4299 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4300 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4301 .port_set_ether_type = mv88e6351_port_set_ether_type,
4302 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4303 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4304 .port_pause_limit = mv88e6097_port_pause_limit,
4305 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4306 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4307 .port_get_cmode = mv88e6352_port_get_cmode,
4308 .port_setup_message_port = mv88e6xxx_setup_message_port,
4309 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4310 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4311 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4312 .stats_get_strings = mv88e6320_stats_get_strings,
4313 .stats_get_stats = mv88e6320_stats_get_stats,
4314 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4315 .set_egress_port = mv88e6095_g1_set_egress_port,
4316 .watchdog_ops = &mv88e6390_watchdog_ops,
4317 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4318 .pot_clear = mv88e6xxx_g2_pot_clear,
4319 .reset = mv88e6352_g1_reset,
4320 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4321 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4322 .gpio_ops = &mv88e6352_gpio_ops,
4323 .avb_ops = &mv88e6352_avb_ops,
4324 .ptp_ops = &mv88e6352_ptp_ops,
4325 .phylink_validate = mv88e6185_phylink_validate,
4326 };
4327
4328 static const struct mv88e6xxx_ops mv88e6321_ops = {
4329 /* MV88E6XXX_FAMILY_6320 */
4330 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4331 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4332 .irl_init_all = mv88e6352_g2_irl_init_all,
4333 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4334 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4335 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4336 .phy_read = mv88e6xxx_g2_smi_phy_read,
4337 .phy_write = mv88e6xxx_g2_smi_phy_write,
4338 .port_set_link = mv88e6xxx_port_set_link,
4339 .port_sync_link = mv88e6xxx_port_sync_link,
4340 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4341 .port_tag_remap = mv88e6095_port_tag_remap,
4342 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4343 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4344 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4345 .port_set_ether_type = mv88e6351_port_set_ether_type,
4346 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4347 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4348 .port_pause_limit = mv88e6097_port_pause_limit,
4349 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4350 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4351 .port_get_cmode = mv88e6352_port_get_cmode,
4352 .port_setup_message_port = mv88e6xxx_setup_message_port,
4353 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4354 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4355 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4356 .stats_get_strings = mv88e6320_stats_get_strings,
4357 .stats_get_stats = mv88e6320_stats_get_stats,
4358 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4359 .set_egress_port = mv88e6095_g1_set_egress_port,
4360 .watchdog_ops = &mv88e6390_watchdog_ops,
4361 .reset = mv88e6352_g1_reset,
4362 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4363 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4364 .gpio_ops = &mv88e6352_gpio_ops,
4365 .avb_ops = &mv88e6352_avb_ops,
4366 .ptp_ops = &mv88e6352_ptp_ops,
4367 .phylink_validate = mv88e6185_phylink_validate,
4368 };
4369
4370 static const struct mv88e6xxx_ops mv88e6341_ops = {
4371 /* MV88E6XXX_FAMILY_6341 */
4372 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4373 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4374 .irl_init_all = mv88e6352_g2_irl_init_all,
4375 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4376 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4377 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4378 .phy_read = mv88e6xxx_g2_smi_phy_read,
4379 .phy_write = mv88e6xxx_g2_smi_phy_write,
4380 .port_set_link = mv88e6xxx_port_set_link,
4381 .port_sync_link = mv88e6xxx_port_sync_link,
4382 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4383 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
4384 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
4385 .port_tag_remap = mv88e6095_port_tag_remap,
4386 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4387 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4388 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4389 .port_set_ether_type = mv88e6351_port_set_ether_type,
4390 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4391 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4392 .port_pause_limit = mv88e6097_port_pause_limit,
4393 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4394 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4395 .port_get_cmode = mv88e6352_port_get_cmode,
4396 .port_set_cmode = mv88e6341_port_set_cmode,
4397 .port_setup_message_port = mv88e6xxx_setup_message_port,
4398 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4399 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4400 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4401 .stats_get_strings = mv88e6320_stats_get_strings,
4402 .stats_get_stats = mv88e6390_stats_get_stats,
4403 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4404 .set_egress_port = mv88e6390_g1_set_egress_port,
4405 .watchdog_ops = &mv88e6390_watchdog_ops,
4406 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4407 .pot_clear = mv88e6xxx_g2_pot_clear,
4408 .reset = mv88e6352_g1_reset,
4409 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4410 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4411 .serdes_power = mv88e6390_serdes_power,
4412 .serdes_get_lane = mv88e6341_serdes_get_lane,
4413 /* Check status register pause & lpa register */
4414 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4415 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4416 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4417 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4418 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4419 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4420 .serdes_irq_status = mv88e6390_serdes_irq_status,
4421 .gpio_ops = &mv88e6352_gpio_ops,
4422 .avb_ops = &mv88e6390_avb_ops,
4423 .ptp_ops = &mv88e6352_ptp_ops,
4424 .phylink_validate = mv88e6341_phylink_validate,
4425 };
4426
4427 static const struct mv88e6xxx_ops mv88e6350_ops = {
4428 /* MV88E6XXX_FAMILY_6351 */
4429 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4430 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4431 .irl_init_all = mv88e6352_g2_irl_init_all,
4432 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4433 .phy_read = mv88e6xxx_g2_smi_phy_read,
4434 .phy_write = mv88e6xxx_g2_smi_phy_write,
4435 .port_set_link = mv88e6xxx_port_set_link,
4436 .port_sync_link = mv88e6xxx_port_sync_link,
4437 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4438 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4439 .port_tag_remap = mv88e6095_port_tag_remap,
4440 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4441 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4442 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4443 .port_set_ether_type = mv88e6351_port_set_ether_type,
4444 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4445 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4446 .port_pause_limit = mv88e6097_port_pause_limit,
4447 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4448 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4449 .port_get_cmode = mv88e6352_port_get_cmode,
4450 .port_setup_message_port = mv88e6xxx_setup_message_port,
4451 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4452 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4453 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4454 .stats_get_strings = mv88e6095_stats_get_strings,
4455 .stats_get_stats = mv88e6095_stats_get_stats,
4456 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4457 .set_egress_port = mv88e6095_g1_set_egress_port,
4458 .watchdog_ops = &mv88e6097_watchdog_ops,
4459 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4460 .pot_clear = mv88e6xxx_g2_pot_clear,
4461 .reset = mv88e6352_g1_reset,
4462 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4463 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4464 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4465 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4466 .phylink_validate = mv88e6185_phylink_validate,
4467 };
4468
4469 static const struct mv88e6xxx_ops mv88e6351_ops = {
4470 /* MV88E6XXX_FAMILY_6351 */
4471 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4472 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4473 .irl_init_all = mv88e6352_g2_irl_init_all,
4474 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4475 .phy_read = mv88e6xxx_g2_smi_phy_read,
4476 .phy_write = mv88e6xxx_g2_smi_phy_write,
4477 .port_set_link = mv88e6xxx_port_set_link,
4478 .port_sync_link = mv88e6xxx_port_sync_link,
4479 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4480 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4481 .port_tag_remap = mv88e6095_port_tag_remap,
4482 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4483 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4484 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4485 .port_set_ether_type = mv88e6351_port_set_ether_type,
4486 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4487 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4488 .port_pause_limit = mv88e6097_port_pause_limit,
4489 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4490 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4491 .port_get_cmode = mv88e6352_port_get_cmode,
4492 .port_setup_message_port = mv88e6xxx_setup_message_port,
4493 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4494 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4495 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4496 .stats_get_strings = mv88e6095_stats_get_strings,
4497 .stats_get_stats = mv88e6095_stats_get_stats,
4498 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4499 .set_egress_port = mv88e6095_g1_set_egress_port,
4500 .watchdog_ops = &mv88e6097_watchdog_ops,
4501 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4502 .pot_clear = mv88e6xxx_g2_pot_clear,
4503 .reset = mv88e6352_g1_reset,
4504 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4505 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4506 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4507 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4508 .avb_ops = &mv88e6352_avb_ops,
4509 .ptp_ops = &mv88e6352_ptp_ops,
4510 .phylink_validate = mv88e6185_phylink_validate,
4511 };
4512
4513 static const struct mv88e6xxx_ops mv88e6352_ops = {
4514 /* MV88E6XXX_FAMILY_6352 */
4515 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4516 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4517 .irl_init_all = mv88e6352_g2_irl_init_all,
4518 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4519 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4520 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4521 .phy_read = mv88e6xxx_g2_smi_phy_read,
4522 .phy_write = mv88e6xxx_g2_smi_phy_write,
4523 .port_set_link = mv88e6xxx_port_set_link,
4524 .port_sync_link = mv88e6xxx_port_sync_link,
4525 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4526 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4527 .port_tag_remap = mv88e6095_port_tag_remap,
4528 .port_set_policy = mv88e6352_port_set_policy,
4529 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4530 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4531 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4532 .port_set_ether_type = mv88e6351_port_set_ether_type,
4533 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4534 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4535 .port_pause_limit = mv88e6097_port_pause_limit,
4536 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4537 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4538 .port_get_cmode = mv88e6352_port_get_cmode,
4539 .port_setup_message_port = mv88e6xxx_setup_message_port,
4540 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4541 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4542 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4543 .stats_get_strings = mv88e6095_stats_get_strings,
4544 .stats_get_stats = mv88e6095_stats_get_stats,
4545 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4546 .set_egress_port = mv88e6095_g1_set_egress_port,
4547 .watchdog_ops = &mv88e6097_watchdog_ops,
4548 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4549 .pot_clear = mv88e6xxx_g2_pot_clear,
4550 .reset = mv88e6352_g1_reset,
4551 .rmu_disable = mv88e6352_g1_rmu_disable,
4552 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4553 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4554 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4555 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4556 .serdes_get_lane = mv88e6352_serdes_get_lane,
4557 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
4558 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
4559 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
4560 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
4561 .serdes_power = mv88e6352_serdes_power,
4562 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4563 .serdes_irq_enable = mv88e6352_serdes_irq_enable,
4564 .serdes_irq_status = mv88e6352_serdes_irq_status,
4565 .gpio_ops = &mv88e6352_gpio_ops,
4566 .avb_ops = &mv88e6352_avb_ops,
4567 .ptp_ops = &mv88e6352_ptp_ops,
4568 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
4569 .serdes_get_strings = mv88e6352_serdes_get_strings,
4570 .serdes_get_stats = mv88e6352_serdes_get_stats,
4571 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4572 .serdes_get_regs = mv88e6352_serdes_get_regs,
4573 .phylink_validate = mv88e6352_phylink_validate,
4574 };
4575
4576 static const struct mv88e6xxx_ops mv88e6390_ops = {
4577 /* MV88E6XXX_FAMILY_6390 */
4578 .setup_errata = mv88e6390_setup_errata,
4579 .irl_init_all = mv88e6390_g2_irl_init_all,
4580 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4581 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4582 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4583 .phy_read = mv88e6xxx_g2_smi_phy_read,
4584 .phy_write = mv88e6xxx_g2_smi_phy_write,
4585 .port_set_link = mv88e6xxx_port_set_link,
4586 .port_sync_link = mv88e6xxx_port_sync_link,
4587 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4588 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4589 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4590 .port_tag_remap = mv88e6390_port_tag_remap,
4591 .port_set_policy = mv88e6352_port_set_policy,
4592 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4593 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4594 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4595 .port_set_ether_type = mv88e6351_port_set_ether_type,
4596 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4597 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4598 .port_pause_limit = mv88e6390_port_pause_limit,
4599 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4600 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4601 .port_get_cmode = mv88e6352_port_get_cmode,
4602 .port_set_cmode = mv88e6390_port_set_cmode,
4603 .port_setup_message_port = mv88e6xxx_setup_message_port,
4604 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4605 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4606 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4607 .stats_get_strings = mv88e6320_stats_get_strings,
4608 .stats_get_stats = mv88e6390_stats_get_stats,
4609 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4610 .set_egress_port = mv88e6390_g1_set_egress_port,
4611 .watchdog_ops = &mv88e6390_watchdog_ops,
4612 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4613 .pot_clear = mv88e6xxx_g2_pot_clear,
4614 .reset = mv88e6352_g1_reset,
4615 .rmu_disable = mv88e6390_g1_rmu_disable,
4616 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4617 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4618 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4619 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4620 .serdes_power = mv88e6390_serdes_power,
4621 .serdes_get_lane = mv88e6390_serdes_get_lane,
4622 /* Check status register pause & lpa register */
4623 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4624 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4625 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4626 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4627 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4628 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4629 .serdes_irq_status = mv88e6390_serdes_irq_status,
4630 .gpio_ops = &mv88e6352_gpio_ops,
4631 .avb_ops = &mv88e6390_avb_ops,
4632 .ptp_ops = &mv88e6352_ptp_ops,
4633 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4634 .serdes_get_strings = mv88e6390_serdes_get_strings,
4635 .serdes_get_stats = mv88e6390_serdes_get_stats,
4636 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4637 .serdes_get_regs = mv88e6390_serdes_get_regs,
4638 .phylink_validate = mv88e6390_phylink_validate,
4639 };
4640
4641 static const struct mv88e6xxx_ops mv88e6390x_ops = {
4642 /* MV88E6XXX_FAMILY_6390 */
4643 .setup_errata = mv88e6390_setup_errata,
4644 .irl_init_all = mv88e6390_g2_irl_init_all,
4645 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4646 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4647 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4648 .phy_read = mv88e6xxx_g2_smi_phy_read,
4649 .phy_write = mv88e6xxx_g2_smi_phy_write,
4650 .port_set_link = mv88e6xxx_port_set_link,
4651 .port_sync_link = mv88e6xxx_port_sync_link,
4652 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4653 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
4654 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
4655 .port_tag_remap = mv88e6390_port_tag_remap,
4656 .port_set_policy = mv88e6352_port_set_policy,
4657 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4658 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4659 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4660 .port_set_ether_type = mv88e6351_port_set_ether_type,
4661 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4662 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4663 .port_pause_limit = mv88e6390_port_pause_limit,
4664 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4665 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4666 .port_get_cmode = mv88e6352_port_get_cmode,
4667 .port_set_cmode = mv88e6390x_port_set_cmode,
4668 .port_setup_message_port = mv88e6xxx_setup_message_port,
4669 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4670 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4671 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4672 .stats_get_strings = mv88e6320_stats_get_strings,
4673 .stats_get_stats = mv88e6390_stats_get_stats,
4674 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4675 .set_egress_port = mv88e6390_g1_set_egress_port,
4676 .watchdog_ops = &mv88e6390_watchdog_ops,
4677 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4678 .pot_clear = mv88e6xxx_g2_pot_clear,
4679 .reset = mv88e6352_g1_reset,
4680 .rmu_disable = mv88e6390_g1_rmu_disable,
4681 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4682 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4683 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4684 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4685 .serdes_power = mv88e6390_serdes_power,
4686 .serdes_get_lane = mv88e6390x_serdes_get_lane,
4687 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4688 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4689 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4690 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4691 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4692 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4693 .serdes_irq_status = mv88e6390_serdes_irq_status,
4694 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4695 .serdes_get_strings = mv88e6390_serdes_get_strings,
4696 .serdes_get_stats = mv88e6390_serdes_get_stats,
4697 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4698 .serdes_get_regs = mv88e6390_serdes_get_regs,
4699 .gpio_ops = &mv88e6352_gpio_ops,
4700 .avb_ops = &mv88e6390_avb_ops,
4701 .ptp_ops = &mv88e6352_ptp_ops,
4702 .phylink_validate = mv88e6390x_phylink_validate,
4703 };
4704
4705 static const struct mv88e6xxx_ops mv88e6393x_ops = {
4706 /* MV88E6XXX_FAMILY_6393 */
4707 .setup_errata = mv88e6393x_serdes_setup_errata,
4708 .irl_init_all = mv88e6390_g2_irl_init_all,
4709 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4710 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4711 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4712 .phy_read = mv88e6xxx_g2_smi_phy_read,
4713 .phy_write = mv88e6xxx_g2_smi_phy_write,
4714 .port_set_link = mv88e6xxx_port_set_link,
4715 .port_sync_link = mv88e6xxx_port_sync_link,
4716 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4717 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex,
4718 .port_max_speed_mode = mv88e6393x_port_max_speed_mode,
4719 .port_tag_remap = mv88e6390_port_tag_remap,
4720 .port_set_policy = mv88e6393x_port_set_policy,
4721 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4722 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4723 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4724 .port_set_ether_type = mv88e6393x_port_set_ether_type,
4725 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4726 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4727 .port_pause_limit = mv88e6390_port_pause_limit,
4728 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4729 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4730 .port_get_cmode = mv88e6352_port_get_cmode,
4731 .port_set_cmode = mv88e6393x_port_set_cmode,
4732 .port_setup_message_port = mv88e6xxx_setup_message_port,
4733 .port_set_upstream_port = mv88e6393x_port_set_upstream_port,
4734 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4735 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4736 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4737 .stats_get_strings = mv88e6320_stats_get_strings,
4738 .stats_get_stats = mv88e6390_stats_get_stats,
4739 /* .set_cpu_port is missing because this family does not support a global
4740 * CPU port, only per port CPU port which is set via
4741 * .port_set_upstream_port method.
4742 */
4743 .set_egress_port = mv88e6393x_set_egress_port,
4744 .watchdog_ops = &mv88e6390_watchdog_ops,
4745 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu,
4746 .pot_clear = mv88e6xxx_g2_pot_clear,
4747 .reset = mv88e6352_g1_reset,
4748 .rmu_disable = mv88e6390_g1_rmu_disable,
4749 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4750 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4751 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4752 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4753 .serdes_power = mv88e6393x_serdes_power,
4754 .serdes_get_lane = mv88e6393x_serdes_get_lane,
4755 .serdes_pcs_get_state = mv88e6393x_serdes_pcs_get_state,
4756 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4757 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4758 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4759 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4760 .serdes_irq_enable = mv88e6393x_serdes_irq_enable,
4761 .serdes_irq_status = mv88e6393x_serdes_irq_status,
4762 /* TODO: serdes stats */
4763 .gpio_ops = &mv88e6352_gpio_ops,
4764 .avb_ops = &mv88e6390_avb_ops,
4765 .ptp_ops = &mv88e6352_ptp_ops,
4766 .phylink_validate = mv88e6393x_phylink_validate,
4767 };
4768
4769 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
4770 [MV88E6085] = {
4771 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
4772 .family = MV88E6XXX_FAMILY_6097,
4773 .name = "Marvell 88E6085",
4774 .num_databases = 4096,
4775 .num_macs = 8192,
4776 .num_ports = 10,
4777 .num_internal_phys = 5,
4778 .max_vid = 4095,
4779 .port_base_addr = 0x10,
4780 .phy_base_addr = 0x0,
4781 .global1_addr = 0x1b,
4782 .global2_addr = 0x1c,
4783 .age_time_coeff = 15000,
4784 .g1_irqs = 8,
4785 .g2_irqs = 10,
4786 .atu_move_port_mask = 0xf,
4787 .pvt = true,
4788 .multi_chip = true,
4789 .ops = &mv88e6085_ops,
4790 },
4791
4792 [MV88E6095] = {
4793 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
4794 .family = MV88E6XXX_FAMILY_6095,
4795 .name = "Marvell 88E6095/88E6095F",
4796 .num_databases = 256,
4797 .num_macs = 8192,
4798 .num_ports = 11,
4799 .num_internal_phys = 0,
4800 .max_vid = 4095,
4801 .port_base_addr = 0x10,
4802 .phy_base_addr = 0x0,
4803 .global1_addr = 0x1b,
4804 .global2_addr = 0x1c,
4805 .age_time_coeff = 15000,
4806 .g1_irqs = 8,
4807 .atu_move_port_mask = 0xf,
4808 .multi_chip = true,
4809 .ops = &mv88e6095_ops,
4810 },
4811
4812 [MV88E6097] = {
4813 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
4814 .family = MV88E6XXX_FAMILY_6097,
4815 .name = "Marvell 88E6097/88E6097F",
4816 .num_databases = 4096,
4817 .num_macs = 8192,
4818 .num_ports = 11,
4819 .num_internal_phys = 8,
4820 .max_vid = 4095,
4821 .port_base_addr = 0x10,
4822 .phy_base_addr = 0x0,
4823 .global1_addr = 0x1b,
4824 .global2_addr = 0x1c,
4825 .age_time_coeff = 15000,
4826 .g1_irqs = 8,
4827 .g2_irqs = 10,
4828 .atu_move_port_mask = 0xf,
4829 .pvt = true,
4830 .multi_chip = true,
4831 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
4832 .ops = &mv88e6097_ops,
4833 },
4834
4835 [MV88E6123] = {
4836 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
4837 .family = MV88E6XXX_FAMILY_6165,
4838 .name = "Marvell 88E6123",
4839 .num_databases = 4096,
4840 .num_macs = 1024,
4841 .num_ports = 3,
4842 .num_internal_phys = 5,
4843 .max_vid = 4095,
4844 .port_base_addr = 0x10,
4845 .phy_base_addr = 0x0,
4846 .global1_addr = 0x1b,
4847 .global2_addr = 0x1c,
4848 .age_time_coeff = 15000,
4849 .g1_irqs = 9,
4850 .g2_irqs = 10,
4851 .atu_move_port_mask = 0xf,
4852 .pvt = true,
4853 .multi_chip = true,
4854 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
4855 .ops = &mv88e6123_ops,
4856 },
4857
4858 [MV88E6131] = {
4859 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
4860 .family = MV88E6XXX_FAMILY_6185,
4861 .name = "Marvell 88E6131",
4862 .num_databases = 256,
4863 .num_macs = 8192,
4864 .num_ports = 8,
4865 .num_internal_phys = 0,
4866 .max_vid = 4095,
4867 .port_base_addr = 0x10,
4868 .phy_base_addr = 0x0,
4869 .global1_addr = 0x1b,
4870 .global2_addr = 0x1c,
4871 .age_time_coeff = 15000,
4872 .g1_irqs = 9,
4873 .atu_move_port_mask = 0xf,
4874 .multi_chip = true,
4875 .ops = &mv88e6131_ops,
4876 },
4877
4878 [MV88E6141] = {
4879 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
4880 .family = MV88E6XXX_FAMILY_6341,
4881 .name = "Marvell 88E6141",
4882 .num_databases = 4096,
4883 .num_macs = 2048,
4884 .num_ports = 6,
4885 .num_internal_phys = 5,
4886 .num_gpio = 11,
4887 .max_vid = 4095,
4888 .port_base_addr = 0x10,
4889 .phy_base_addr = 0x10,
4890 .global1_addr = 0x1b,
4891 .global2_addr = 0x1c,
4892 .age_time_coeff = 3750,
4893 .atu_move_port_mask = 0x1f,
4894 .g1_irqs = 9,
4895 .g2_irqs = 10,
4896 .pvt = true,
4897 .multi_chip = true,
4898 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
4899 .ops = &mv88e6141_ops,
4900 },
4901
4902 [MV88E6161] = {
4903 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
4904 .family = MV88E6XXX_FAMILY_6165,
4905 .name = "Marvell 88E6161",
4906 .num_databases = 4096,
4907 .num_macs = 1024,
4908 .num_ports = 6,
4909 .num_internal_phys = 5,
4910 .max_vid = 4095,
4911 .port_base_addr = 0x10,
4912 .phy_base_addr = 0x0,
4913 .global1_addr = 0x1b,
4914 .global2_addr = 0x1c,
4915 .age_time_coeff = 15000,
4916 .g1_irqs = 9,
4917 .g2_irqs = 10,
4918 .atu_move_port_mask = 0xf,
4919 .pvt = true,
4920 .multi_chip = true,
4921 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
4922 .ptp_support = true,
4923 .ops = &mv88e6161_ops,
4924 },
4925
4926 [MV88E6165] = {
4927 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
4928 .family = MV88E6XXX_FAMILY_6165,
4929 .name = "Marvell 88E6165",
4930 .num_databases = 4096,
4931 .num_macs = 8192,
4932 .num_ports = 6,
4933 .num_internal_phys = 0,
4934 .max_vid = 4095,
4935 .port_base_addr = 0x10,
4936 .phy_base_addr = 0x0,
4937 .global1_addr = 0x1b,
4938 .global2_addr = 0x1c,
4939 .age_time_coeff = 15000,
4940 .g1_irqs = 9,
4941 .g2_irqs = 10,
4942 .atu_move_port_mask = 0xf,
4943 .pvt = true,
4944 .multi_chip = true,
4945 .ptp_support = true,
4946 .ops = &mv88e6165_ops,
4947 },
4948
4949 [MV88E6171] = {
4950 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
4951 .family = MV88E6XXX_FAMILY_6351,
4952 .name = "Marvell 88E6171",
4953 .num_databases = 4096,
4954 .num_macs = 8192,
4955 .num_ports = 7,
4956 .num_internal_phys = 5,
4957 .max_vid = 4095,
4958 .port_base_addr = 0x10,
4959 .phy_base_addr = 0x0,
4960 .global1_addr = 0x1b,
4961 .global2_addr = 0x1c,
4962 .age_time_coeff = 15000,
4963 .g1_irqs = 9,
4964 .g2_irqs = 10,
4965 .atu_move_port_mask = 0xf,
4966 .pvt = true,
4967 .multi_chip = true,
4968 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
4969 .ops = &mv88e6171_ops,
4970 },
4971
4972 [MV88E6172] = {
4973 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
4974 .family = MV88E6XXX_FAMILY_6352,
4975 .name = "Marvell 88E6172",
4976 .num_databases = 4096,
4977 .num_macs = 8192,
4978 .num_ports = 7,
4979 .num_internal_phys = 5,
4980 .num_gpio = 15,
4981 .max_vid = 4095,
4982 .port_base_addr = 0x10,
4983 .phy_base_addr = 0x0,
4984 .global1_addr = 0x1b,
4985 .global2_addr = 0x1c,
4986 .age_time_coeff = 15000,
4987 .g1_irqs = 9,
4988 .g2_irqs = 10,
4989 .atu_move_port_mask = 0xf,
4990 .pvt = true,
4991 .multi_chip = true,
4992 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
4993 .ops = &mv88e6172_ops,
4994 },
4995
4996 [MV88E6175] = {
4997 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
4998 .family = MV88E6XXX_FAMILY_6351,
4999 .name = "Marvell 88E6175",
5000 .num_databases = 4096,
5001 .num_macs = 8192,
5002 .num_ports = 7,
5003 .num_internal_phys = 5,
5004 .max_vid = 4095,
5005 .port_base_addr = 0x10,
5006 .phy_base_addr = 0x0,
5007 .global1_addr = 0x1b,
5008 .global2_addr = 0x1c,
5009 .age_time_coeff = 15000,
5010 .g1_irqs = 9,
5011 .g2_irqs = 10,
5012 .atu_move_port_mask = 0xf,
5013 .pvt = true,
5014 .multi_chip = true,
5015 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5016 .ops = &mv88e6175_ops,
5017 },
5018
5019 [MV88E6176] = {
5020 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
5021 .family = MV88E6XXX_FAMILY_6352,
5022 .name = "Marvell 88E6176",
5023 .num_databases = 4096,
5024 .num_macs = 8192,
5025 .num_ports = 7,
5026 .num_internal_phys = 5,
5027 .num_gpio = 15,
5028 .max_vid = 4095,
5029 .port_base_addr = 0x10,
5030 .phy_base_addr = 0x0,
5031 .global1_addr = 0x1b,
5032 .global2_addr = 0x1c,
5033 .age_time_coeff = 15000,
5034 .g1_irqs = 9,
5035 .g2_irqs = 10,
5036 .atu_move_port_mask = 0xf,
5037 .pvt = true,
5038 .multi_chip = true,
5039 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5040 .ops = &mv88e6176_ops,
5041 },
5042
5043 [MV88E6185] = {
5044 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
5045 .family = MV88E6XXX_FAMILY_6185,
5046 .name = "Marvell 88E6185",
5047 .num_databases = 256,
5048 .num_macs = 8192,
5049 .num_ports = 10,
5050 .num_internal_phys = 0,
5051 .max_vid = 4095,
5052 .port_base_addr = 0x10,
5053 .phy_base_addr = 0x0,
5054 .global1_addr = 0x1b,
5055 .global2_addr = 0x1c,
5056 .age_time_coeff = 15000,
5057 .g1_irqs = 8,
5058 .atu_move_port_mask = 0xf,
5059 .multi_chip = true,
5060 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5061 .ops = &mv88e6185_ops,
5062 },
5063
5064 [MV88E6190] = {
5065 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
5066 .family = MV88E6XXX_FAMILY_6390,
5067 .name = "Marvell 88E6190",
5068 .num_databases = 4096,
5069 .num_macs = 16384,
5070 .num_ports = 11, /* 10 + Z80 */
5071 .num_internal_phys = 9,
5072 .num_gpio = 16,
5073 .max_vid = 8191,
5074 .port_base_addr = 0x0,
5075 .phy_base_addr = 0x0,
5076 .global1_addr = 0x1b,
5077 .global2_addr = 0x1c,
5078 .age_time_coeff = 3750,
5079 .g1_irqs = 9,
5080 .g2_irqs = 14,
5081 .pvt = true,
5082 .multi_chip = true,
5083 .atu_move_port_mask = 0x1f,
5084 .ops = &mv88e6190_ops,
5085 },
5086
5087 [MV88E6190X] = {
5088 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
5089 .family = MV88E6XXX_FAMILY_6390,
5090 .name = "Marvell 88E6190X",
5091 .num_databases = 4096,
5092 .num_macs = 16384,
5093 .num_ports = 11, /* 10 + Z80 */
5094 .num_internal_phys = 9,
5095 .num_gpio = 16,
5096 .max_vid = 8191,
5097 .port_base_addr = 0x0,
5098 .phy_base_addr = 0x0,
5099 .global1_addr = 0x1b,
5100 .global2_addr = 0x1c,
5101 .age_time_coeff = 3750,
5102 .g1_irqs = 9,
5103 .g2_irqs = 14,
5104 .atu_move_port_mask = 0x1f,
5105 .pvt = true,
5106 .multi_chip = true,
5107 .ops = &mv88e6190x_ops,
5108 },
5109
5110 [MV88E6191] = {
5111 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
5112 .family = MV88E6XXX_FAMILY_6390,
5113 .name = "Marvell 88E6191",
5114 .num_databases = 4096,
5115 .num_macs = 16384,
5116 .num_ports = 11, /* 10 + Z80 */
5117 .num_internal_phys = 9,
5118 .max_vid = 8191,
5119 .port_base_addr = 0x0,
5120 .phy_base_addr = 0x0,
5121 .global1_addr = 0x1b,
5122 .global2_addr = 0x1c,
5123 .age_time_coeff = 3750,
5124 .g1_irqs = 9,
5125 .g2_irqs = 14,
5126 .atu_move_port_mask = 0x1f,
5127 .pvt = true,
5128 .multi_chip = true,
5129 .ptp_support = true,
5130 .ops = &mv88e6191_ops,
5131 },
5132
5133 [MV88E6191X] = {
5134 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X,
5135 .family = MV88E6XXX_FAMILY_6393,
5136 .name = "Marvell 88E6191X",
5137 .num_databases = 4096,
5138 .num_ports = 11, /* 10 + Z80 */
5139 .num_internal_phys = 9,
5140 .max_vid = 8191,
5141 .port_base_addr = 0x0,
5142 .phy_base_addr = 0x0,
5143 .global1_addr = 0x1b,
5144 .global2_addr = 0x1c,
5145 .age_time_coeff = 3750,
5146 .g1_irqs = 10,
5147 .g2_irqs = 14,
5148 .atu_move_port_mask = 0x1f,
5149 .pvt = true,
5150 .multi_chip = true,
5151 .ptp_support = true,
5152 .ops = &mv88e6393x_ops,
5153 },
5154
5155 [MV88E6193X] = {
5156 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X,
5157 .family = MV88E6XXX_FAMILY_6393,
5158 .name = "Marvell 88E6193X",
5159 .num_databases = 4096,
5160 .num_ports = 11, /* 10 + Z80 */
5161 .num_internal_phys = 9,
5162 .max_vid = 8191,
5163 .port_base_addr = 0x0,
5164 .phy_base_addr = 0x0,
5165 .global1_addr = 0x1b,
5166 .global2_addr = 0x1c,
5167 .age_time_coeff = 3750,
5168 .g1_irqs = 10,
5169 .g2_irqs = 14,
5170 .atu_move_port_mask = 0x1f,
5171 .pvt = true,
5172 .multi_chip = true,
5173 .ptp_support = true,
5174 .ops = &mv88e6393x_ops,
5175 },
5176
5177 [MV88E6220] = {
5178 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220,
5179 .family = MV88E6XXX_FAMILY_6250,
5180 .name = "Marvell 88E6220",
5181 .num_databases = 64,
5182
5183 /* Ports 2-4 are not routed to pins
5184 * => usable ports 0, 1, 5, 6
5185 */
5186 .num_ports = 7,
5187 .num_internal_phys = 2,
5188 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4),
5189 .max_vid = 4095,
5190 .port_base_addr = 0x08,
5191 .phy_base_addr = 0x00,
5192 .global1_addr = 0x0f,
5193 .global2_addr = 0x07,
5194 .age_time_coeff = 15000,
5195 .g1_irqs = 9,
5196 .g2_irqs = 10,
5197 .atu_move_port_mask = 0xf,
5198 .dual_chip = true,
5199 .ptp_support = true,
5200 .ops = &mv88e6250_ops,
5201 },
5202
5203 [MV88E6240] = {
5204 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
5205 .family = MV88E6XXX_FAMILY_6352,
5206 .name = "Marvell 88E6240",
5207 .num_databases = 4096,
5208 .num_macs = 8192,
5209 .num_ports = 7,
5210 .num_internal_phys = 5,
5211 .num_gpio = 15,
5212 .max_vid = 4095,
5213 .port_base_addr = 0x10,
5214 .phy_base_addr = 0x0,
5215 .global1_addr = 0x1b,
5216 .global2_addr = 0x1c,
5217 .age_time_coeff = 15000,
5218 .g1_irqs = 9,
5219 .g2_irqs = 10,
5220 .atu_move_port_mask = 0xf,
5221 .pvt = true,
5222 .multi_chip = true,
5223 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5224 .ptp_support = true,
5225 .ops = &mv88e6240_ops,
5226 },
5227
5228 [MV88E6250] = {
5229 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250,
5230 .family = MV88E6XXX_FAMILY_6250,
5231 .name = "Marvell 88E6250",
5232 .num_databases = 64,
5233 .num_ports = 7,
5234 .num_internal_phys = 5,
5235 .max_vid = 4095,
5236 .port_base_addr = 0x08,
5237 .phy_base_addr = 0x00,
5238 .global1_addr = 0x0f,
5239 .global2_addr = 0x07,
5240 .age_time_coeff = 15000,
5241 .g1_irqs = 9,
5242 .g2_irqs = 10,
5243 .atu_move_port_mask = 0xf,
5244 .dual_chip = true,
5245 .ptp_support = true,
5246 .ops = &mv88e6250_ops,
5247 },
5248
5249 [MV88E6290] = {
5250 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
5251 .family = MV88E6XXX_FAMILY_6390,
5252 .name = "Marvell 88E6290",
5253 .num_databases = 4096,
5254 .num_ports = 11, /* 10 + Z80 */
5255 .num_internal_phys = 9,
5256 .num_gpio = 16,
5257 .max_vid = 8191,
5258 .port_base_addr = 0x0,
5259 .phy_base_addr = 0x0,
5260 .global1_addr = 0x1b,
5261 .global2_addr = 0x1c,
5262 .age_time_coeff = 3750,
5263 .g1_irqs = 9,
5264 .g2_irqs = 14,
5265 .atu_move_port_mask = 0x1f,
5266 .pvt = true,
5267 .multi_chip = true,
5268 .ptp_support = true,
5269 .ops = &mv88e6290_ops,
5270 },
5271
5272 [MV88E6320] = {
5273 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
5274 .family = MV88E6XXX_FAMILY_6320,
5275 .name = "Marvell 88E6320",
5276 .num_databases = 4096,
5277 .num_macs = 8192,
5278 .num_ports = 7,
5279 .num_internal_phys = 5,
5280 .num_gpio = 15,
5281 .max_vid = 4095,
5282 .port_base_addr = 0x10,
5283 .phy_base_addr = 0x0,
5284 .global1_addr = 0x1b,
5285 .global2_addr = 0x1c,
5286 .age_time_coeff = 15000,
5287 .g1_irqs = 8,
5288 .g2_irqs = 10,
5289 .atu_move_port_mask = 0xf,
5290 .pvt = true,
5291 .multi_chip = true,
5292 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5293 .ptp_support = true,
5294 .ops = &mv88e6320_ops,
5295 },
5296
5297 [MV88E6321] = {
5298 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
5299 .family = MV88E6XXX_FAMILY_6320,
5300 .name = "Marvell 88E6321",
5301 .num_databases = 4096,
5302 .num_macs = 8192,
5303 .num_ports = 7,
5304 .num_internal_phys = 5,
5305 .num_gpio = 15,
5306 .max_vid = 4095,
5307 .port_base_addr = 0x10,
5308 .phy_base_addr = 0x0,
5309 .global1_addr = 0x1b,
5310 .global2_addr = 0x1c,
5311 .age_time_coeff = 15000,
5312 .g1_irqs = 8,
5313 .g2_irqs = 10,
5314 .atu_move_port_mask = 0xf,
5315 .multi_chip = true,
5316 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5317 .ptp_support = true,
5318 .ops = &mv88e6321_ops,
5319 },
5320
5321 [MV88E6341] = {
5322 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
5323 .family = MV88E6XXX_FAMILY_6341,
5324 .name = "Marvell 88E6341",
5325 .num_databases = 4096,
5326 .num_macs = 2048,
5327 .num_internal_phys = 5,
5328 .num_ports = 6,
5329 .num_gpio = 11,
5330 .max_vid = 4095,
5331 .port_base_addr = 0x10,
5332 .phy_base_addr = 0x10,
5333 .global1_addr = 0x1b,
5334 .global2_addr = 0x1c,
5335 .age_time_coeff = 3750,
5336 .atu_move_port_mask = 0x1f,
5337 .g1_irqs = 9,
5338 .g2_irqs = 10,
5339 .pvt = true,
5340 .multi_chip = true,
5341 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5342 .ptp_support = true,
5343 .ops = &mv88e6341_ops,
5344 },
5345
5346 [MV88E6350] = {
5347 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
5348 .family = MV88E6XXX_FAMILY_6351,
5349 .name = "Marvell 88E6350",
5350 .num_databases = 4096,
5351 .num_macs = 8192,
5352 .num_ports = 7,
5353 .num_internal_phys = 5,
5354 .max_vid = 4095,
5355 .port_base_addr = 0x10,
5356 .phy_base_addr = 0x0,
5357 .global1_addr = 0x1b,
5358 .global2_addr = 0x1c,
5359 .age_time_coeff = 15000,
5360 .g1_irqs = 9,
5361 .g2_irqs = 10,
5362 .atu_move_port_mask = 0xf,
5363 .pvt = true,
5364 .multi_chip = true,
5365 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5366 .ops = &mv88e6350_ops,
5367 },
5368
5369 [MV88E6351] = {
5370 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
5371 .family = MV88E6XXX_FAMILY_6351,
5372 .name = "Marvell 88E6351",
5373 .num_databases = 4096,
5374 .num_macs = 8192,
5375 .num_ports = 7,
5376 .num_internal_phys = 5,
5377 .max_vid = 4095,
5378 .port_base_addr = 0x10,
5379 .phy_base_addr = 0x0,
5380 .global1_addr = 0x1b,
5381 .global2_addr = 0x1c,
5382 .age_time_coeff = 15000,
5383 .g1_irqs = 9,
5384 .g2_irqs = 10,
5385 .atu_move_port_mask = 0xf,
5386 .pvt = true,
5387 .multi_chip = true,
5388 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5389 .ops = &mv88e6351_ops,
5390 },
5391
5392 [MV88E6352] = {
5393 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
5394 .family = MV88E6XXX_FAMILY_6352,
5395 .name = "Marvell 88E6352",
5396 .num_databases = 4096,
5397 .num_macs = 8192,
5398 .num_ports = 7,
5399 .num_internal_phys = 5,
5400 .num_gpio = 15,
5401 .max_vid = 4095,
5402 .port_base_addr = 0x10,
5403 .phy_base_addr = 0x0,
5404 .global1_addr = 0x1b,
5405 .global2_addr = 0x1c,
5406 .age_time_coeff = 15000,
5407 .g1_irqs = 9,
5408 .g2_irqs = 10,
5409 .atu_move_port_mask = 0xf,
5410 .pvt = true,
5411 .multi_chip = true,
5412 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5413 .ptp_support = true,
5414 .ops = &mv88e6352_ops,
5415 },
5416 [MV88E6390] = {
5417 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
5418 .family = MV88E6XXX_FAMILY_6390,
5419 .name = "Marvell 88E6390",
5420 .num_databases = 4096,
5421 .num_macs = 16384,
5422 .num_ports = 11, /* 10 + Z80 */
5423 .num_internal_phys = 9,
5424 .num_gpio = 16,
5425 .max_vid = 8191,
5426 .port_base_addr = 0x0,
5427 .phy_base_addr = 0x0,
5428 .global1_addr = 0x1b,
5429 .global2_addr = 0x1c,
5430 .age_time_coeff = 3750,
5431 .g1_irqs = 9,
5432 .g2_irqs = 14,
5433 .atu_move_port_mask = 0x1f,
5434 .pvt = true,
5435 .multi_chip = true,
5436 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
5437 .ptp_support = true,
5438 .ops = &mv88e6390_ops,
5439 },
5440 [MV88E6390X] = {
5441 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
5442 .family = MV88E6XXX_FAMILY_6390,
5443 .name = "Marvell 88E6390X",
5444 .num_databases = 4096,
5445 .num_macs = 16384,
5446 .num_ports = 11, /* 10 + Z80 */
5447 .num_internal_phys = 9,
5448 .num_gpio = 16,
5449 .max_vid = 8191,
5450 .port_base_addr = 0x0,
5451 .phy_base_addr = 0x0,
5452 .global1_addr = 0x1b,
5453 .global2_addr = 0x1c,
5454 .age_time_coeff = 3750,
5455 .g1_irqs = 9,
5456 .g2_irqs = 14,
5457 .atu_move_port_mask = 0x1f,
5458 .pvt = true,
5459 .multi_chip = true,
5460 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
5461 .ptp_support = true,
5462 .ops = &mv88e6390x_ops,
5463 },
5464
5465 [MV88E6393X] = {
5466 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
5467 .family = MV88E6XXX_FAMILY_6393,
5468 .name = "Marvell 88E6393X",
5469 .num_databases = 4096,
5470 .num_ports = 11, /* 10 + Z80 */
5471 .num_internal_phys = 9,
5472 .max_vid = 8191,
5473 .port_base_addr = 0x0,
5474 .phy_base_addr = 0x0,
5475 .global1_addr = 0x1b,
5476 .global2_addr = 0x1c,
5477 .age_time_coeff = 3750,
5478 .g1_irqs = 10,
5479 .g2_irqs = 14,
5480 .atu_move_port_mask = 0x1f,
5481 .pvt = true,
5482 .multi_chip = true,
5483 .ptp_support = true,
5484 .ops = &mv88e6393x_ops,
5485 },
5486 };
5487
mv88e6xxx_lookup_info(unsigned int prod_num)5488 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
5489 {
5490 int i;
5491
5492 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
5493 if (mv88e6xxx_table[i].prod_num == prod_num)
5494 return &mv88e6xxx_table[i];
5495
5496 return NULL;
5497 }
5498
mv88e6xxx_detect(struct mv88e6xxx_chip * chip)5499 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
5500 {
5501 const struct mv88e6xxx_info *info;
5502 unsigned int prod_num, rev;
5503 u16 id;
5504 int err;
5505
5506 mv88e6xxx_reg_lock(chip);
5507 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
5508 mv88e6xxx_reg_unlock(chip);
5509 if (err)
5510 return err;
5511
5512 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
5513 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
5514
5515 info = mv88e6xxx_lookup_info(prod_num);
5516 if (!info)
5517 return -ENODEV;
5518
5519 /* Update the compatible info with the probed one */
5520 chip->info = info;
5521
5522 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
5523 chip->info->prod_num, chip->info->name, rev);
5524
5525 return 0;
5526 }
5527
mv88e6xxx_alloc_chip(struct device * dev)5528 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
5529 {
5530 struct mv88e6xxx_chip *chip;
5531
5532 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
5533 if (!chip)
5534 return NULL;
5535
5536 chip->dev = dev;
5537
5538 mutex_init(&chip->reg_lock);
5539 INIT_LIST_HEAD(&chip->mdios);
5540 idr_init(&chip->policies);
5541
5542 return chip;
5543 }
5544
mv88e6xxx_get_tag_protocol(struct dsa_switch * ds,int port,enum dsa_tag_protocol m)5545 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
5546 int port,
5547 enum dsa_tag_protocol m)
5548 {
5549 struct mv88e6xxx_chip *chip = ds->priv;
5550
5551 return chip->tag_protocol;
5552 }
5553
mv88e6xxx_change_tag_protocol(struct dsa_switch * ds,int port,enum dsa_tag_protocol proto)5554 static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds, int port,
5555 enum dsa_tag_protocol proto)
5556 {
5557 struct mv88e6xxx_chip *chip = ds->priv;
5558 enum dsa_tag_protocol old_protocol;
5559 int err;
5560
5561 switch (proto) {
5562 case DSA_TAG_PROTO_EDSA:
5563 switch (chip->info->edsa_support) {
5564 case MV88E6XXX_EDSA_UNSUPPORTED:
5565 return -EPROTONOSUPPORT;
5566 case MV88E6XXX_EDSA_UNDOCUMENTED:
5567 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n");
5568 fallthrough;
5569 case MV88E6XXX_EDSA_SUPPORTED:
5570 break;
5571 }
5572 break;
5573 case DSA_TAG_PROTO_DSA:
5574 break;
5575 default:
5576 return -EPROTONOSUPPORT;
5577 }
5578
5579 old_protocol = chip->tag_protocol;
5580 chip->tag_protocol = proto;
5581
5582 mv88e6xxx_reg_lock(chip);
5583 err = mv88e6xxx_setup_port_mode(chip, port);
5584 mv88e6xxx_reg_unlock(chip);
5585
5586 if (err)
5587 chip->tag_protocol = old_protocol;
5588
5589 return err;
5590 }
5591
mv88e6xxx_port_mdb_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb)5592 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
5593 const struct switchdev_obj_port_mdb *mdb)
5594 {
5595 struct mv88e6xxx_chip *chip = ds->priv;
5596 int err;
5597
5598 mv88e6xxx_reg_lock(chip);
5599 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
5600 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC);
5601 mv88e6xxx_reg_unlock(chip);
5602
5603 return err;
5604 }
5605
mv88e6xxx_port_mdb_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb)5606 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
5607 const struct switchdev_obj_port_mdb *mdb)
5608 {
5609 struct mv88e6xxx_chip *chip = ds->priv;
5610 int err;
5611
5612 mv88e6xxx_reg_lock(chip);
5613 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0);
5614 mv88e6xxx_reg_unlock(chip);
5615
5616 return err;
5617 }
5618
mv88e6xxx_port_mirror_add(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror,bool ingress)5619 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port,
5620 struct dsa_mall_mirror_tc_entry *mirror,
5621 bool ingress)
5622 {
5623 enum mv88e6xxx_egress_direction direction = ingress ?
5624 MV88E6XXX_EGRESS_DIR_INGRESS :
5625 MV88E6XXX_EGRESS_DIR_EGRESS;
5626 struct mv88e6xxx_chip *chip = ds->priv;
5627 bool other_mirrors = false;
5628 int i;
5629 int err;
5630
5631 mutex_lock(&chip->reg_lock);
5632 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) !=
5633 mirror->to_local_port) {
5634 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
5635 other_mirrors |= ingress ?
5636 chip->ports[i].mirror_ingress :
5637 chip->ports[i].mirror_egress;
5638
5639 /* Can't change egress port when other mirror is active */
5640 if (other_mirrors) {
5641 err = -EBUSY;
5642 goto out;
5643 }
5644
5645 err = mv88e6xxx_set_egress_port(chip, direction,
5646 mirror->to_local_port);
5647 if (err)
5648 goto out;
5649 }
5650
5651 err = mv88e6xxx_port_set_mirror(chip, port, direction, true);
5652 out:
5653 mutex_unlock(&chip->reg_lock);
5654
5655 return err;
5656 }
5657
mv88e6xxx_port_mirror_del(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror)5658 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port,
5659 struct dsa_mall_mirror_tc_entry *mirror)
5660 {
5661 enum mv88e6xxx_egress_direction direction = mirror->ingress ?
5662 MV88E6XXX_EGRESS_DIR_INGRESS :
5663 MV88E6XXX_EGRESS_DIR_EGRESS;
5664 struct mv88e6xxx_chip *chip = ds->priv;
5665 bool other_mirrors = false;
5666 int i;
5667
5668 mutex_lock(&chip->reg_lock);
5669 if (mv88e6xxx_port_set_mirror(chip, port, direction, false))
5670 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port);
5671
5672 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
5673 other_mirrors |= mirror->ingress ?
5674 chip->ports[i].mirror_ingress :
5675 chip->ports[i].mirror_egress;
5676
5677 /* Reset egress port when no other mirror is active */
5678 if (!other_mirrors) {
5679 if (mv88e6xxx_set_egress_port(chip, direction,
5680 dsa_upstream_port(ds, port)))
5681 dev_err(ds->dev, "failed to set egress port\n");
5682 }
5683
5684 mutex_unlock(&chip->reg_lock);
5685 }
5686
mv88e6xxx_port_pre_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)5687 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port,
5688 struct switchdev_brport_flags flags,
5689 struct netlink_ext_ack *extack)
5690 {
5691 struct mv88e6xxx_chip *chip = ds->priv;
5692 const struct mv88e6xxx_ops *ops;
5693
5694 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
5695 BR_BCAST_FLOOD))
5696 return -EINVAL;
5697
5698 ops = chip->info->ops;
5699
5700 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood)
5701 return -EINVAL;
5702
5703 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood)
5704 return -EINVAL;
5705
5706 return 0;
5707 }
5708
mv88e6xxx_port_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)5709 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port,
5710 struct switchdev_brport_flags flags,
5711 struct netlink_ext_ack *extack)
5712 {
5713 struct mv88e6xxx_chip *chip = ds->priv;
5714 bool do_fast_age = false;
5715 int err = -EOPNOTSUPP;
5716
5717 mv88e6xxx_reg_lock(chip);
5718
5719 if (flags.mask & BR_LEARNING) {
5720 bool learning = !!(flags.val & BR_LEARNING);
5721 u16 pav = learning ? (1 << port) : 0;
5722
5723 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav);
5724 if (err)
5725 goto out;
5726
5727 if (!learning)
5728 do_fast_age = true;
5729 }
5730
5731 if (flags.mask & BR_FLOOD) {
5732 bool unicast = !!(flags.val & BR_FLOOD);
5733
5734 err = chip->info->ops->port_set_ucast_flood(chip, port,
5735 unicast);
5736 if (err)
5737 goto out;
5738 }
5739
5740 if (flags.mask & BR_MCAST_FLOOD) {
5741 bool multicast = !!(flags.val & BR_MCAST_FLOOD);
5742
5743 err = chip->info->ops->port_set_mcast_flood(chip, port,
5744 multicast);
5745 if (err)
5746 goto out;
5747 }
5748
5749 if (flags.mask & BR_BCAST_FLOOD) {
5750 bool broadcast = !!(flags.val & BR_BCAST_FLOOD);
5751
5752 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast);
5753 if (err)
5754 goto out;
5755 }
5756
5757 out:
5758 mv88e6xxx_reg_unlock(chip);
5759
5760 if (do_fast_age)
5761 mv88e6xxx_port_fast_age(ds, port);
5762
5763 return err;
5764 }
5765
mv88e6xxx_port_set_mrouter(struct dsa_switch * ds,int port,bool mrouter,struct netlink_ext_ack * extack)5766 static int mv88e6xxx_port_set_mrouter(struct dsa_switch *ds, int port,
5767 bool mrouter,
5768 struct netlink_ext_ack *extack)
5769 {
5770 struct mv88e6xxx_chip *chip = ds->priv;
5771 int err;
5772
5773 if (!chip->info->ops->port_set_mcast_flood)
5774 return -EOPNOTSUPP;
5775
5776 mv88e6xxx_reg_lock(chip);
5777 err = chip->info->ops->port_set_mcast_flood(chip, port, mrouter);
5778 mv88e6xxx_reg_unlock(chip);
5779
5780 return err;
5781 }
5782
mv88e6xxx_lag_can_offload(struct dsa_switch * ds,struct net_device * lag,struct netdev_lag_upper_info * info)5783 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds,
5784 struct net_device *lag,
5785 struct netdev_lag_upper_info *info)
5786 {
5787 struct mv88e6xxx_chip *chip = ds->priv;
5788 struct dsa_port *dp;
5789 int id, members = 0;
5790
5791 if (!mv88e6xxx_has_lag(chip))
5792 return false;
5793
5794 id = dsa_lag_id(ds->dst, lag);
5795 if (id < 0 || id >= ds->num_lag_ids)
5796 return false;
5797
5798 dsa_lag_foreach_port(dp, ds->dst, lag)
5799 /* Includes the port joining the LAG */
5800 members++;
5801
5802 if (members > 8)
5803 return false;
5804
5805 /* We could potentially relax this to include active
5806 * backup in the future.
5807 */
5808 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
5809 return false;
5810
5811 /* Ideally we would also validate that the hash type matches
5812 * the hardware. Alas, this is always set to unknown on team
5813 * interfaces.
5814 */
5815 return true;
5816 }
5817
mv88e6xxx_lag_sync_map(struct dsa_switch * ds,struct net_device * lag)5818 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct net_device *lag)
5819 {
5820 struct mv88e6xxx_chip *chip = ds->priv;
5821 struct dsa_port *dp;
5822 u16 map = 0;
5823 int id;
5824
5825 id = dsa_lag_id(ds->dst, lag);
5826
5827 /* Build the map of all ports to distribute flows destined for
5828 * this LAG. This can be either a local user port, or a DSA
5829 * port if the LAG port is on a remote chip.
5830 */
5831 dsa_lag_foreach_port(dp, ds->dst, lag)
5832 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index));
5833
5834 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map);
5835 }
5836
5837 static const u8 mv88e6xxx_lag_mask_table[8][8] = {
5838 /* Row number corresponds to the number of active members in a
5839 * LAG. Each column states which of the eight hash buckets are
5840 * mapped to the column:th port in the LAG.
5841 *
5842 * Example: In a LAG with three active ports, the second port
5843 * ([2][1]) would be selected for traffic mapped to buckets
5844 * 3,4,5 (0x38).
5845 */
5846 { 0xff, 0, 0, 0, 0, 0, 0, 0 },
5847 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 },
5848 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 },
5849 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 },
5850 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 },
5851 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 },
5852 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 },
5853 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 },
5854 };
5855
mv88e6xxx_lag_set_port_mask(u16 * mask,int port,int num_tx,int nth)5856 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port,
5857 int num_tx, int nth)
5858 {
5859 u8 active = 0;
5860 int i;
5861
5862 num_tx = num_tx <= 8 ? num_tx : 8;
5863 if (nth < num_tx)
5864 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth];
5865
5866 for (i = 0; i < 8; i++) {
5867 if (BIT(i) & active)
5868 mask[i] |= BIT(port);
5869 }
5870 }
5871
mv88e6xxx_lag_sync_masks(struct dsa_switch * ds)5872 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds)
5873 {
5874 struct mv88e6xxx_chip *chip = ds->priv;
5875 unsigned int id, num_tx;
5876 struct net_device *lag;
5877 struct dsa_port *dp;
5878 int i, err, nth;
5879 u16 mask[8];
5880 u16 ivec;
5881
5882 /* Assume no port is a member of any LAG. */
5883 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1;
5884
5885 /* Disable all masks for ports that _are_ members of a LAG. */
5886 list_for_each_entry(dp, &ds->dst->ports, list) {
5887 if (!dp->lag_dev || dp->ds != ds)
5888 continue;
5889
5890 ivec &= ~BIT(dp->index);
5891 }
5892
5893 for (i = 0; i < 8; i++)
5894 mask[i] = ivec;
5895
5896 /* Enable the correct subset of masks for all LAG ports that
5897 * are in the Tx set.
5898 */
5899 dsa_lags_foreach_id(id, ds->dst) {
5900 lag = dsa_lag_dev(ds->dst, id);
5901 if (!lag)
5902 continue;
5903
5904 num_tx = 0;
5905 dsa_lag_foreach_port(dp, ds->dst, lag) {
5906 if (dp->lag_tx_enabled)
5907 num_tx++;
5908 }
5909
5910 if (!num_tx)
5911 continue;
5912
5913 nth = 0;
5914 dsa_lag_foreach_port(dp, ds->dst, lag) {
5915 if (!dp->lag_tx_enabled)
5916 continue;
5917
5918 if (dp->ds == ds)
5919 mv88e6xxx_lag_set_port_mask(mask, dp->index,
5920 num_tx, nth);
5921
5922 nth++;
5923 }
5924 }
5925
5926 for (i = 0; i < 8; i++) {
5927 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]);
5928 if (err)
5929 return err;
5930 }
5931
5932 return 0;
5933 }
5934
mv88e6xxx_lag_sync_masks_map(struct dsa_switch * ds,struct net_device * lag)5935 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds,
5936 struct net_device *lag)
5937 {
5938 int err;
5939
5940 err = mv88e6xxx_lag_sync_masks(ds);
5941
5942 if (!err)
5943 err = mv88e6xxx_lag_sync_map(ds, lag);
5944
5945 return err;
5946 }
5947
mv88e6xxx_port_lag_change(struct dsa_switch * ds,int port)5948 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port)
5949 {
5950 struct mv88e6xxx_chip *chip = ds->priv;
5951 int err;
5952
5953 mv88e6xxx_reg_lock(chip);
5954 err = mv88e6xxx_lag_sync_masks(ds);
5955 mv88e6xxx_reg_unlock(chip);
5956 return err;
5957 }
5958
mv88e6xxx_port_lag_join(struct dsa_switch * ds,int port,struct net_device * lag,struct netdev_lag_upper_info * info)5959 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port,
5960 struct net_device *lag,
5961 struct netdev_lag_upper_info *info)
5962 {
5963 struct mv88e6xxx_chip *chip = ds->priv;
5964 int err, id;
5965
5966 if (!mv88e6xxx_lag_can_offload(ds, lag, info))
5967 return -EOPNOTSUPP;
5968
5969 id = dsa_lag_id(ds->dst, lag);
5970
5971 mv88e6xxx_reg_lock(chip);
5972
5973 err = mv88e6xxx_port_set_trunk(chip, port, true, id);
5974 if (err)
5975 goto err_unlock;
5976
5977 err = mv88e6xxx_lag_sync_masks_map(ds, lag);
5978 if (err)
5979 goto err_clear_trunk;
5980
5981 mv88e6xxx_reg_unlock(chip);
5982 return 0;
5983
5984 err_clear_trunk:
5985 mv88e6xxx_port_set_trunk(chip, port, false, 0);
5986 err_unlock:
5987 mv88e6xxx_reg_unlock(chip);
5988 return err;
5989 }
5990
mv88e6xxx_port_lag_leave(struct dsa_switch * ds,int port,struct net_device * lag)5991 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port,
5992 struct net_device *lag)
5993 {
5994 struct mv88e6xxx_chip *chip = ds->priv;
5995 int err_sync, err_trunk;
5996
5997 mv88e6xxx_reg_lock(chip);
5998 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
5999 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0);
6000 mv88e6xxx_reg_unlock(chip);
6001 return err_sync ? : err_trunk;
6002 }
6003
mv88e6xxx_crosschip_lag_change(struct dsa_switch * ds,int sw_index,int port)6004 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index,
6005 int port)
6006 {
6007 struct mv88e6xxx_chip *chip = ds->priv;
6008 int err;
6009
6010 mv88e6xxx_reg_lock(chip);
6011 err = mv88e6xxx_lag_sync_masks(ds);
6012 mv88e6xxx_reg_unlock(chip);
6013 return err;
6014 }
6015
mv88e6xxx_crosschip_lag_join(struct dsa_switch * ds,int sw_index,int port,struct net_device * lag,struct netdev_lag_upper_info * info)6016 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index,
6017 int port, struct net_device *lag,
6018 struct netdev_lag_upper_info *info)
6019 {
6020 struct mv88e6xxx_chip *chip = ds->priv;
6021 int err;
6022
6023 if (!mv88e6xxx_lag_can_offload(ds, lag, info))
6024 return -EOPNOTSUPP;
6025
6026 mv88e6xxx_reg_lock(chip);
6027
6028 err = mv88e6xxx_lag_sync_masks_map(ds, lag);
6029 if (err)
6030 goto unlock;
6031
6032 err = mv88e6xxx_pvt_map(chip, sw_index, port);
6033
6034 unlock:
6035 mv88e6xxx_reg_unlock(chip);
6036 return err;
6037 }
6038
mv88e6xxx_crosschip_lag_leave(struct dsa_switch * ds,int sw_index,int port,struct net_device * lag)6039 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index,
6040 int port, struct net_device *lag)
6041 {
6042 struct mv88e6xxx_chip *chip = ds->priv;
6043 int err_sync, err_pvt;
6044
6045 mv88e6xxx_reg_lock(chip);
6046 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
6047 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port);
6048 mv88e6xxx_reg_unlock(chip);
6049 return err_sync ? : err_pvt;
6050 }
6051
6052 static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
6053 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
6054 .change_tag_protocol = mv88e6xxx_change_tag_protocol,
6055 .setup = mv88e6xxx_setup,
6056 .teardown = mv88e6xxx_teardown,
6057 .phylink_validate = mv88e6xxx_validate,
6058 .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state,
6059 .phylink_mac_config = mv88e6xxx_mac_config,
6060 .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart,
6061 .phylink_mac_link_down = mv88e6xxx_mac_link_down,
6062 .phylink_mac_link_up = mv88e6xxx_mac_link_up,
6063 .get_strings = mv88e6xxx_get_strings,
6064 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
6065 .get_sset_count = mv88e6xxx_get_sset_count,
6066 .port_enable = mv88e6xxx_port_enable,
6067 .port_disable = mv88e6xxx_port_disable,
6068 .port_max_mtu = mv88e6xxx_get_max_mtu,
6069 .port_change_mtu = mv88e6xxx_change_mtu,
6070 .get_mac_eee = mv88e6xxx_get_mac_eee,
6071 .set_mac_eee = mv88e6xxx_set_mac_eee,
6072 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
6073 .get_eeprom = mv88e6xxx_get_eeprom,
6074 .set_eeprom = mv88e6xxx_set_eeprom,
6075 .get_regs_len = mv88e6xxx_get_regs_len,
6076 .get_regs = mv88e6xxx_get_regs,
6077 .get_rxnfc = mv88e6xxx_get_rxnfc,
6078 .set_rxnfc = mv88e6xxx_set_rxnfc,
6079 .set_ageing_time = mv88e6xxx_set_ageing_time,
6080 .port_bridge_join = mv88e6xxx_port_bridge_join,
6081 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
6082 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags,
6083 .port_bridge_flags = mv88e6xxx_port_bridge_flags,
6084 .port_set_mrouter = mv88e6xxx_port_set_mrouter,
6085 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
6086 .port_fast_age = mv88e6xxx_port_fast_age,
6087 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
6088 .port_vlan_add = mv88e6xxx_port_vlan_add,
6089 .port_vlan_del = mv88e6xxx_port_vlan_del,
6090 .port_fdb_add = mv88e6xxx_port_fdb_add,
6091 .port_fdb_del = mv88e6xxx_port_fdb_del,
6092 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
6093 .port_mdb_add = mv88e6xxx_port_mdb_add,
6094 .port_mdb_del = mv88e6xxx_port_mdb_del,
6095 .port_mirror_add = mv88e6xxx_port_mirror_add,
6096 .port_mirror_del = mv88e6xxx_port_mirror_del,
6097 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join,
6098 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
6099 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set,
6100 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get,
6101 .port_txtstamp = mv88e6xxx_port_txtstamp,
6102 .port_rxtstamp = mv88e6xxx_port_rxtstamp,
6103 .get_ts_info = mv88e6xxx_get_ts_info,
6104 .devlink_param_get = mv88e6xxx_devlink_param_get,
6105 .devlink_param_set = mv88e6xxx_devlink_param_set,
6106 .devlink_info_get = mv88e6xxx_devlink_info_get,
6107 .port_lag_change = mv88e6xxx_port_lag_change,
6108 .port_lag_join = mv88e6xxx_port_lag_join,
6109 .port_lag_leave = mv88e6xxx_port_lag_leave,
6110 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change,
6111 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join,
6112 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave,
6113 };
6114
mv88e6xxx_register_switch(struct mv88e6xxx_chip * chip)6115 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
6116 {
6117 struct device *dev = chip->dev;
6118 struct dsa_switch *ds;
6119
6120 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
6121 if (!ds)
6122 return -ENOMEM;
6123
6124 ds->dev = dev;
6125 ds->num_ports = mv88e6xxx_num_ports(chip);
6126 ds->priv = chip;
6127 ds->dev = dev;
6128 ds->ops = &mv88e6xxx_switch_ops;
6129 ds->ageing_time_min = chip->info->age_time_coeff;
6130 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
6131
6132 /* Some chips support up to 32, but that requires enabling the
6133 * 5-bit port mode, which we do not support. 640k^W16 ought to
6134 * be enough for anyone.
6135 */
6136 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0;
6137
6138 dev_set_drvdata(dev, ds);
6139
6140 return dsa_register_switch(ds);
6141 }
6142
mv88e6xxx_unregister_switch(struct mv88e6xxx_chip * chip)6143 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
6144 {
6145 dsa_unregister_switch(chip->ds);
6146 }
6147
pdata_device_get_match_data(struct device * dev)6148 static const void *pdata_device_get_match_data(struct device *dev)
6149 {
6150 const struct of_device_id *matches = dev->driver->of_match_table;
6151 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data;
6152
6153 for (; matches->name[0] || matches->type[0] || matches->compatible[0];
6154 matches++) {
6155 if (!strcmp(pdata->compatible, matches->compatible))
6156 return matches->data;
6157 }
6158 return NULL;
6159 }
6160
6161 /* There is no suspend to RAM support at DSA level yet, the switch configuration
6162 * would be lost after a power cycle so prevent it to be suspended.
6163 */
mv88e6xxx_suspend(struct device * dev)6164 static int __maybe_unused mv88e6xxx_suspend(struct device *dev)
6165 {
6166 return -EOPNOTSUPP;
6167 }
6168
mv88e6xxx_resume(struct device * dev)6169 static int __maybe_unused mv88e6xxx_resume(struct device *dev)
6170 {
6171 return 0;
6172 }
6173
6174 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume);
6175
mv88e6xxx_probe(struct mdio_device * mdiodev)6176 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
6177 {
6178 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data;
6179 const struct mv88e6xxx_info *compat_info = NULL;
6180 struct device *dev = &mdiodev->dev;
6181 struct device_node *np = dev->of_node;
6182 struct mv88e6xxx_chip *chip;
6183 int port;
6184 int err;
6185
6186 if (!np && !pdata)
6187 return -EINVAL;
6188
6189 if (np)
6190 compat_info = of_device_get_match_data(dev);
6191
6192 if (pdata) {
6193 compat_info = pdata_device_get_match_data(dev);
6194
6195 if (!pdata->netdev)
6196 return -EINVAL;
6197
6198 for (port = 0; port < DSA_MAX_PORTS; port++) {
6199 if (!(pdata->enabled_ports & (1 << port)))
6200 continue;
6201 if (strcmp(pdata->cd.port_names[port], "cpu"))
6202 continue;
6203 pdata->cd.netdev[port] = &pdata->netdev->dev;
6204 break;
6205 }
6206 }
6207
6208 if (!compat_info)
6209 return -EINVAL;
6210
6211 chip = mv88e6xxx_alloc_chip(dev);
6212 if (!chip) {
6213 err = -ENOMEM;
6214 goto out;
6215 }
6216
6217 chip->info = compat_info;
6218
6219 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
6220 if (err)
6221 goto out;
6222
6223 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
6224 if (IS_ERR(chip->reset)) {
6225 err = PTR_ERR(chip->reset);
6226 goto out;
6227 }
6228 if (chip->reset)
6229 usleep_range(1000, 2000);
6230
6231 err = mv88e6xxx_detect(chip);
6232 if (err)
6233 goto out;
6234
6235 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED)
6236 chip->tag_protocol = DSA_TAG_PROTO_EDSA;
6237 else
6238 chip->tag_protocol = DSA_TAG_PROTO_DSA;
6239
6240 mv88e6xxx_phy_init(chip);
6241
6242 if (chip->info->ops->get_eeprom) {
6243 if (np)
6244 of_property_read_u32(np, "eeprom-length",
6245 &chip->eeprom_len);
6246 else
6247 chip->eeprom_len = pdata->eeprom_len;
6248 }
6249
6250 mv88e6xxx_reg_lock(chip);
6251 err = mv88e6xxx_switch_reset(chip);
6252 mv88e6xxx_reg_unlock(chip);
6253 if (err)
6254 goto out;
6255
6256 if (np) {
6257 chip->irq = of_irq_get(np, 0);
6258 if (chip->irq == -EPROBE_DEFER) {
6259 err = chip->irq;
6260 goto out;
6261 }
6262 }
6263
6264 if (pdata)
6265 chip->irq = pdata->irq;
6266
6267 /* Has to be performed before the MDIO bus is created, because
6268 * the PHYs will link their interrupts to these interrupt
6269 * controllers
6270 */
6271 mv88e6xxx_reg_lock(chip);
6272 if (chip->irq > 0)
6273 err = mv88e6xxx_g1_irq_setup(chip);
6274 else
6275 err = mv88e6xxx_irq_poll_setup(chip);
6276 mv88e6xxx_reg_unlock(chip);
6277
6278 if (err)
6279 goto out;
6280
6281 if (chip->info->g2_irqs > 0) {
6282 err = mv88e6xxx_g2_irq_setup(chip);
6283 if (err)
6284 goto out_g1_irq;
6285 }
6286
6287 err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
6288 if (err)
6289 goto out_g2_irq;
6290
6291 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
6292 if (err)
6293 goto out_g1_atu_prob_irq;
6294
6295 err = mv88e6xxx_mdios_register(chip, np);
6296 if (err)
6297 goto out_g1_vtu_prob_irq;
6298
6299 err = mv88e6xxx_register_switch(chip);
6300 if (err)
6301 goto out_mdio;
6302
6303 return 0;
6304
6305 out_mdio:
6306 mv88e6xxx_mdios_unregister(chip);
6307 out_g1_vtu_prob_irq:
6308 mv88e6xxx_g1_vtu_prob_irq_free(chip);
6309 out_g1_atu_prob_irq:
6310 mv88e6xxx_g1_atu_prob_irq_free(chip);
6311 out_g2_irq:
6312 if (chip->info->g2_irqs > 0)
6313 mv88e6xxx_g2_irq_free(chip);
6314 out_g1_irq:
6315 if (chip->irq > 0)
6316 mv88e6xxx_g1_irq_free(chip);
6317 else
6318 mv88e6xxx_irq_poll_free(chip);
6319 out:
6320 if (pdata)
6321 dev_put(pdata->netdev);
6322
6323 return err;
6324 }
6325
mv88e6xxx_remove(struct mdio_device * mdiodev)6326 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
6327 {
6328 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
6329 struct mv88e6xxx_chip *chip = ds->priv;
6330
6331 if (chip->info->ptp_support) {
6332 mv88e6xxx_hwtstamp_free(chip);
6333 mv88e6xxx_ptp_free(chip);
6334 }
6335
6336 mv88e6xxx_phy_destroy(chip);
6337 mv88e6xxx_unregister_switch(chip);
6338 mv88e6xxx_mdios_unregister(chip);
6339
6340 mv88e6xxx_g1_vtu_prob_irq_free(chip);
6341 mv88e6xxx_g1_atu_prob_irq_free(chip);
6342
6343 if (chip->info->g2_irqs > 0)
6344 mv88e6xxx_g2_irq_free(chip);
6345
6346 if (chip->irq > 0)
6347 mv88e6xxx_g1_irq_free(chip);
6348 else
6349 mv88e6xxx_irq_poll_free(chip);
6350 }
6351
6352 static const struct of_device_id mv88e6xxx_of_match[] = {
6353 {
6354 .compatible = "marvell,mv88e6085",
6355 .data = &mv88e6xxx_table[MV88E6085],
6356 },
6357 {
6358 .compatible = "marvell,mv88e6190",
6359 .data = &mv88e6xxx_table[MV88E6190],
6360 },
6361 {
6362 .compatible = "marvell,mv88e6250",
6363 .data = &mv88e6xxx_table[MV88E6250],
6364 },
6365 { /* sentinel */ },
6366 };
6367
6368 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
6369
6370 static struct mdio_driver mv88e6xxx_driver = {
6371 .probe = mv88e6xxx_probe,
6372 .remove = mv88e6xxx_remove,
6373 .mdiodrv.driver = {
6374 .name = "mv88e6085",
6375 .of_match_table = mv88e6xxx_of_match,
6376 .pm = &mv88e6xxx_pm_ops,
6377 },
6378 };
6379
6380 mdio_module_driver(mv88e6xxx_driver);
6381
6382 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
6383 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
6384 MODULE_LICENSE("GPL");
6385