1 /* SPDX-License-Identifier: GPL-2.0+ */
2 // Copyright (c) 2016-2017 Hisilicon Limited.
3
4 #ifndef __HNS3_ENET_H
5 #define __HNS3_ENET_H
6
7 #include <linux/if_vlan.h>
8
9 #include "hnae3.h"
10
11 enum hns3_nic_state {
12 HNS3_NIC_STATE_TESTING,
13 HNS3_NIC_STATE_RESETTING,
14 HNS3_NIC_STATE_INITED,
15 HNS3_NIC_STATE_DOWN,
16 HNS3_NIC_STATE_DISABLED,
17 HNS3_NIC_STATE_REMOVING,
18 HNS3_NIC_STATE_SERVICE_INITED,
19 HNS3_NIC_STATE_SERVICE_SCHED,
20 HNS3_NIC_STATE2_RESET_REQUESTED,
21 HNS3_NIC_STATE_HW_TX_CSUM_ENABLE,
22 HNS3_NIC_STATE_MAX
23 };
24
25 #define HNS3_RING_RX_RING_BASEADDR_L_REG 0x00000
26 #define HNS3_RING_RX_RING_BASEADDR_H_REG 0x00004
27 #define HNS3_RING_RX_RING_BD_NUM_REG 0x00008
28 #define HNS3_RING_RX_RING_BD_LEN_REG 0x0000C
29 #define HNS3_RING_RX_RING_TAIL_REG 0x00018
30 #define HNS3_RING_RX_RING_HEAD_REG 0x0001C
31 #define HNS3_RING_RX_RING_FBDNUM_REG 0x00020
32 #define HNS3_RING_RX_RING_PKTNUM_RECORD_REG 0x0002C
33
34 #define HNS3_RING_TX_RING_BASEADDR_L_REG 0x00040
35 #define HNS3_RING_TX_RING_BASEADDR_H_REG 0x00044
36 #define HNS3_RING_TX_RING_BD_NUM_REG 0x00048
37 #define HNS3_RING_TX_RING_TC_REG 0x00050
38 #define HNS3_RING_TX_RING_TAIL_REG 0x00058
39 #define HNS3_RING_TX_RING_HEAD_REG 0x0005C
40 #define HNS3_RING_TX_RING_FBDNUM_REG 0x00060
41 #define HNS3_RING_TX_RING_OFFSET_REG 0x00064
42 #define HNS3_RING_TX_RING_EBDNUM_REG 0x00068
43 #define HNS3_RING_TX_RING_PKTNUM_RECORD_REG 0x0006C
44 #define HNS3_RING_TX_RING_EBD_OFFSET_REG 0x00070
45 #define HNS3_RING_TX_RING_BD_ERR_REG 0x00074
46 #define HNS3_RING_EN_REG 0x00090
47 #define HNS3_RING_RX_EN_REG 0x00098
48 #define HNS3_RING_TX_EN_REG 0x000D4
49
50 #define HNS3_RX_HEAD_SIZE 256
51
52 #define HNS3_TX_TIMEOUT (5 * HZ)
53 #define HNS3_RING_NAME_LEN 16
54 #define HNS3_BUFFER_SIZE_2048 2048
55 #define HNS3_RING_MAX_PENDING 32760
56 #define HNS3_RING_MIN_PENDING 72
57 #define HNS3_RING_BD_MULTIPLE 8
58 /* max frame size of mac */
59 #define HNS3_MAX_MTU(max_frm_size) \
60 ((max_frm_size) - (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN))
61
62 #define HNS3_BD_SIZE_512_TYPE 0
63 #define HNS3_BD_SIZE_1024_TYPE 1
64 #define HNS3_BD_SIZE_2048_TYPE 2
65 #define HNS3_BD_SIZE_4096_TYPE 3
66
67 #define HNS3_RX_FLAG_VLAN_PRESENT 0x1
68 #define HNS3_RX_FLAG_L3ID_IPV4 0x0
69 #define HNS3_RX_FLAG_L3ID_IPV6 0x1
70 #define HNS3_RX_FLAG_L4ID_UDP 0x0
71 #define HNS3_RX_FLAG_L4ID_TCP 0x1
72
73 #define HNS3_RXD_DMAC_S 0
74 #define HNS3_RXD_DMAC_M (0x3 << HNS3_RXD_DMAC_S)
75 #define HNS3_RXD_VLAN_S 2
76 #define HNS3_RXD_VLAN_M (0x3 << HNS3_RXD_VLAN_S)
77 #define HNS3_RXD_L3ID_S 4
78 #define HNS3_RXD_L3ID_M (0xf << HNS3_RXD_L3ID_S)
79 #define HNS3_RXD_L4ID_S 8
80 #define HNS3_RXD_L4ID_M (0xf << HNS3_RXD_L4ID_S)
81 #define HNS3_RXD_FRAG_B 12
82 #define HNS3_RXD_STRP_TAGP_S 13
83 #define HNS3_RXD_STRP_TAGP_M (0x3 << HNS3_RXD_STRP_TAGP_S)
84
85 #define HNS3_RXD_L2_CSUM_B 15
86 #define HNS3_RXD_L2_CSUM_L_S 4
87 #define HNS3_RXD_L2_CSUM_L_M (0xff << HNS3_RXD_L2_CSUM_L_S)
88 #define HNS3_RXD_L2_CSUM_H_S 24
89 #define HNS3_RXD_L2_CSUM_H_M (0xff << HNS3_RXD_L2_CSUM_H_S)
90
91 #define HNS3_RXD_L2E_B 16
92 #define HNS3_RXD_L3E_B 17
93 #define HNS3_RXD_L4E_B 18
94 #define HNS3_RXD_TRUNCAT_B 19
95 #define HNS3_RXD_HOI_B 20
96 #define HNS3_RXD_DOI_B 21
97 #define HNS3_RXD_OL3E_B 22
98 #define HNS3_RXD_OL4E_B 23
99 #define HNS3_RXD_GRO_COUNT_S 24
100 #define HNS3_RXD_GRO_COUNT_M (0x3f << HNS3_RXD_GRO_COUNT_S)
101 #define HNS3_RXD_GRO_FIXID_B 30
102 #define HNS3_RXD_GRO_ECN_B 31
103
104 #define HNS3_RXD_ODMAC_S 0
105 #define HNS3_RXD_ODMAC_M (0x3 << HNS3_RXD_ODMAC_S)
106 #define HNS3_RXD_OVLAN_S 2
107 #define HNS3_RXD_OVLAN_M (0x3 << HNS3_RXD_OVLAN_S)
108 #define HNS3_RXD_OL3ID_S 4
109 #define HNS3_RXD_OL3ID_M (0xf << HNS3_RXD_OL3ID_S)
110 #define HNS3_RXD_OL4ID_S 8
111 #define HNS3_RXD_OL4ID_M (0xf << HNS3_RXD_OL4ID_S)
112 #define HNS3_RXD_FBHI_S 12
113 #define HNS3_RXD_FBHI_M (0x3 << HNS3_RXD_FBHI_S)
114 #define HNS3_RXD_FBLI_S 14
115 #define HNS3_RXD_FBLI_M (0x3 << HNS3_RXD_FBLI_S)
116
117 #define HNS3_RXD_BDTYPE_S 0
118 #define HNS3_RXD_BDTYPE_M (0xf << HNS3_RXD_BDTYPE_S)
119 #define HNS3_RXD_VLD_B 4
120 #define HNS3_RXD_UDP0_B 5
121 #define HNS3_RXD_EXTEND_B 7
122 #define HNS3_RXD_FE_B 8
123 #define HNS3_RXD_LUM_B 9
124 #define HNS3_RXD_CRCP_B 10
125 #define HNS3_RXD_L3L4P_B 11
126 #define HNS3_RXD_TSIND_S 12
127 #define HNS3_RXD_TSIND_M (0x7 << HNS3_RXD_TSIND_S)
128 #define HNS3_RXD_LKBK_B 15
129 #define HNS3_RXD_GRO_SIZE_S 16
130 #define HNS3_RXD_GRO_SIZE_M (0x3fff << HNS3_RXD_GRO_SIZE_S)
131
132 #define HNS3_TXD_L3T_S 0
133 #define HNS3_TXD_L3T_M (0x3 << HNS3_TXD_L3T_S)
134 #define HNS3_TXD_L4T_S 2
135 #define HNS3_TXD_L4T_M (0x3 << HNS3_TXD_L4T_S)
136 #define HNS3_TXD_L3CS_B 4
137 #define HNS3_TXD_L4CS_B 5
138 #define HNS3_TXD_VLAN_B 6
139 #define HNS3_TXD_TSO_B 7
140
141 #define HNS3_TXD_L2LEN_S 8
142 #define HNS3_TXD_L2LEN_M (0xff << HNS3_TXD_L2LEN_S)
143 #define HNS3_TXD_L3LEN_S 16
144 #define HNS3_TXD_L3LEN_M (0xff << HNS3_TXD_L3LEN_S)
145 #define HNS3_TXD_L4LEN_S 24
146 #define HNS3_TXD_L4LEN_M (0xff << HNS3_TXD_L4LEN_S)
147
148 #define HNS3_TXD_CSUM_START_S 8
149 #define HNS3_TXD_CSUM_START_M (0xffff << HNS3_TXD_CSUM_START_S)
150
151 #define HNS3_TXD_OL3T_S 0
152 #define HNS3_TXD_OL3T_M (0x3 << HNS3_TXD_OL3T_S)
153 #define HNS3_TXD_OVLAN_B 2
154 #define HNS3_TXD_MACSEC_B 3
155 #define HNS3_TXD_TUNTYPE_S 4
156 #define HNS3_TXD_TUNTYPE_M (0xf << HNS3_TXD_TUNTYPE_S)
157
158 #define HNS3_TXD_CSUM_OFFSET_S 8
159 #define HNS3_TXD_CSUM_OFFSET_M (0xffff << HNS3_TXD_CSUM_OFFSET_S)
160
161 #define HNS3_TXD_BDTYPE_S 0
162 #define HNS3_TXD_BDTYPE_M (0xf << HNS3_TXD_BDTYPE_S)
163 #define HNS3_TXD_FE_B 4
164 #define HNS3_TXD_SC_S 5
165 #define HNS3_TXD_SC_M (0x3 << HNS3_TXD_SC_S)
166 #define HNS3_TXD_EXTEND_B 7
167 #define HNS3_TXD_VLD_B 8
168 #define HNS3_TXD_RI_B 9
169 #define HNS3_TXD_RA_B 10
170 #define HNS3_TXD_TSYN_B 11
171 #define HNS3_TXD_DECTTL_S 12
172 #define HNS3_TXD_DECTTL_M (0xf << HNS3_TXD_DECTTL_S)
173
174 #define HNS3_TXD_OL4CS_B 22
175
176 #define HNS3_TXD_MSS_S 0
177 #define HNS3_TXD_MSS_M (0x3fff << HNS3_TXD_MSS_S)
178 #define HNS3_TXD_HW_CS_B 14
179
180 #define HNS3_VECTOR_TX_IRQ BIT_ULL(0)
181 #define HNS3_VECTOR_RX_IRQ BIT_ULL(1)
182
183 #define HNS3_VECTOR_NOT_INITED 0
184 #define HNS3_VECTOR_INITED 1
185
186 #define HNS3_MAX_BD_SIZE 65535
187 #define HNS3_MAX_TSO_BD_NUM 63U
188 #define HNS3_MAX_TSO_SIZE \
189 (HNS3_MAX_BD_SIZE * HNS3_MAX_TSO_BD_NUM)
190
191 #define HNS3_MAX_NON_TSO_SIZE(max_non_tso_bd_num) \
192 (HNS3_MAX_BD_SIZE * (max_non_tso_bd_num))
193
194 #define HNS3_VECTOR_GL0_OFFSET 0x100
195 #define HNS3_VECTOR_GL1_OFFSET 0x200
196 #define HNS3_VECTOR_GL2_OFFSET 0x300
197 #define HNS3_VECTOR_RL_OFFSET 0x900
198 #define HNS3_VECTOR_RL_EN_B 6
199 #define HNS3_VECTOR_TX_QL_OFFSET 0xe00
200 #define HNS3_VECTOR_RX_QL_OFFSET 0xf00
201
202 #define HNS3_RING_EN_B 0
203
204 enum hns3_pkt_l2t_type {
205 HNS3_L2_TYPE_UNICAST,
206 HNS3_L2_TYPE_MULTICAST,
207 HNS3_L2_TYPE_BROADCAST,
208 HNS3_L2_TYPE_INVALID,
209 };
210
211 enum hns3_pkt_l3t_type {
212 HNS3_L3T_NONE,
213 HNS3_L3T_IPV6,
214 HNS3_L3T_IPV4,
215 HNS3_L3T_RESERVED
216 };
217
218 enum hns3_pkt_l4t_type {
219 HNS3_L4T_UNKNOWN,
220 HNS3_L4T_TCP,
221 HNS3_L4T_UDP,
222 HNS3_L4T_SCTP
223 };
224
225 enum hns3_pkt_ol3t_type {
226 HNS3_OL3T_NONE,
227 HNS3_OL3T_IPV6,
228 HNS3_OL3T_IPV4_NO_CSUM,
229 HNS3_OL3T_IPV4_CSUM
230 };
231
232 enum hns3_pkt_tun_type {
233 HNS3_TUN_NONE,
234 HNS3_TUN_MAC_IN_UDP,
235 HNS3_TUN_NVGRE,
236 HNS3_TUN_OTHER
237 };
238
239 /* hardware spec ring buffer format */
240 struct __packed hns3_desc {
241 __le64 addr;
242 union {
243 struct {
244 __le16 vlan_tag;
245 __le16 send_size;
246 union {
247 __le32 type_cs_vlan_tso_len;
248 struct {
249 __u8 type_cs_vlan_tso;
250 __u8 l2_len;
251 __u8 l3_len;
252 __u8 l4_len;
253 };
254 };
255 __le16 outer_vlan_tag;
256 __le16 tv;
257
258 union {
259 __le32 ol_type_vlan_len_msec;
260 struct {
261 __u8 ol_type_vlan_msec;
262 __u8 ol2_len;
263 __u8 ol3_len;
264 __u8 ol4_len;
265 };
266 };
267
268 __le32 paylen_ol4cs;
269 __le16 bdtp_fe_sc_vld_ra_ri;
270 __le16 mss_hw_csum;
271 } tx;
272
273 struct {
274 __le32 l234_info;
275 __le16 pkt_len;
276 __le16 size;
277
278 __le32 rss_hash;
279 __le16 fd_id;
280 __le16 vlan_tag;
281
282 union {
283 __le32 ol_info;
284 struct {
285 __le16 o_dm_vlan_id_fb;
286 __le16 ot_vlan_tag;
287 };
288 };
289
290 __le32 bd_base_info;
291 } rx;
292 };
293 };
294
295 struct hns3_desc_cb {
296 dma_addr_t dma; /* dma address of this desc */
297 void *buf; /* cpu addr for a desc */
298
299 /* priv data for the desc, e.g. skb when use with ip stack */
300 void *priv;
301
302 union {
303 u32 page_offset; /* for rx */
304 u32 send_bytes; /* for tx */
305 };
306
307 u32 length; /* length of the buffer */
308
309 u16 reuse_flag;
310
311 /* desc type, used by the ring user to mark the type of the priv data */
312 u16 type;
313 u16 pagecnt_bias;
314 };
315
316 enum hns3_pkt_l3type {
317 HNS3_L3_TYPE_IPV4,
318 HNS3_L3_TYPE_IPV6,
319 HNS3_L3_TYPE_ARP,
320 HNS3_L3_TYPE_RARP,
321 HNS3_L3_TYPE_IPV4_OPT,
322 HNS3_L3_TYPE_IPV6_EXT,
323 HNS3_L3_TYPE_LLDP,
324 HNS3_L3_TYPE_BPDU,
325 HNS3_L3_TYPE_MAC_PAUSE,
326 HNS3_L3_TYPE_PFC_PAUSE,/* 0x9*/
327
328 /* reserved for 0xA~0xB */
329
330 HNS3_L3_TYPE_CNM = 0xc,
331
332 /* reserved for 0xD~0xE */
333
334 HNS3_L3_TYPE_PARSE_FAIL = 0xf /* must be last */
335 };
336
337 enum hns3_pkt_l4type {
338 HNS3_L4_TYPE_UDP,
339 HNS3_L4_TYPE_TCP,
340 HNS3_L4_TYPE_GRE,
341 HNS3_L4_TYPE_SCTP,
342 HNS3_L4_TYPE_IGMP,
343 HNS3_L4_TYPE_ICMP,
344
345 /* reserved for 0x6~0xE */
346
347 HNS3_L4_TYPE_PARSE_FAIL = 0xf /* must be last */
348 };
349
350 enum hns3_pkt_ol3type {
351 HNS3_OL3_TYPE_IPV4 = 0,
352 HNS3_OL3_TYPE_IPV6,
353 /* reserved for 0x2~0x3 */
354 HNS3_OL3_TYPE_IPV4_OPT = 4,
355 HNS3_OL3_TYPE_IPV6_EXT,
356
357 /* reserved for 0x6~0xE */
358
359 HNS3_OL3_TYPE_PARSE_FAIL = 0xf /* must be last */
360 };
361
362 enum hns3_pkt_ol4type {
363 HNS3_OL4_TYPE_NO_TUN,
364 HNS3_OL4_TYPE_MAC_IN_UDP,
365 HNS3_OL4_TYPE_NVGRE,
366 HNS3_OL4_TYPE_UNKNOWN
367 };
368
369 struct ring_stats {
370 u64 sw_err_cnt;
371 u64 seg_pkt_cnt;
372 union {
373 struct {
374 u64 tx_pkts;
375 u64 tx_bytes;
376 u64 tx_more;
377 u64 restart_queue;
378 u64 tx_busy;
379 u64 tx_copy;
380 u64 tx_vlan_err;
381 u64 tx_l4_proto_err;
382 u64 tx_l2l3l4_err;
383 u64 tx_tso_err;
384 u64 over_max_recursion;
385 u64 hw_limitation;
386 };
387 struct {
388 u64 rx_pkts;
389 u64 rx_bytes;
390 u64 rx_err_cnt;
391 u64 reuse_pg_cnt;
392 u64 err_pkt_len;
393 u64 err_bd_num;
394 u64 l2_err;
395 u64 l3l4_csum_err;
396 u64 csum_complete;
397 u64 rx_multicast;
398 u64 non_reuse_pg;
399 };
400 };
401 };
402
403 struct hns3_enet_ring {
404 struct hns3_desc *desc; /* dma map address space */
405 struct hns3_desc_cb *desc_cb;
406 struct hns3_enet_ring *next;
407 struct hns3_enet_tqp_vector *tqp_vector;
408 struct hnae3_queue *tqp;
409 int queue_index;
410 struct device *dev; /* will be used for DMA mapping of descriptors */
411
412 /* statistic */
413 struct ring_stats stats;
414 struct u64_stats_sync syncp;
415
416 dma_addr_t desc_dma_addr;
417 u32 buf_size; /* size for hnae_desc->addr, preset by AE */
418 u16 desc_num; /* total number of desc */
419 int next_to_use; /* idx of next spare desc */
420
421 /* idx of lastest sent desc, the ring is empty when equal to
422 * next_to_use
423 */
424 int next_to_clean;
425 union {
426 int last_to_use; /* last idx used by xmit */
427 u32 pull_len; /* memcpy len for current rx packet */
428 };
429 u32 frag_num;
430 void *va; /* first buffer address for current packet */
431
432 u32 flag; /* ring attribute */
433
434 int pending_buf;
435 struct sk_buff *skb;
436 struct sk_buff *tail_skb;
437 } ____cacheline_internodealigned_in_smp;
438
439 enum hns3_flow_level_range {
440 HNS3_FLOW_LOW = 0,
441 HNS3_FLOW_MID = 1,
442 HNS3_FLOW_HIGH = 2,
443 HNS3_FLOW_ULTRA = 3,
444 };
445
446 #define HNS3_INT_GL_50K 0x0014
447 #define HNS3_INT_GL_20K 0x0032
448 #define HNS3_INT_GL_18K 0x0036
449 #define HNS3_INT_GL_8K 0x007C
450
451 #define HNS3_INT_GL_1US BIT(31)
452
453 #define HNS3_INT_RL_MAX 0x00EC
454 #define HNS3_INT_RL_ENABLE_MASK 0x40
455
456 #define HNS3_INT_QL_DEFAULT_CFG 0x20
457
458 struct hns3_enet_coalesce {
459 u16 int_gl;
460 u16 int_ql;
461 u16 int_ql_max;
462 u8 adapt_enable:1;
463 u8 ql_enable:1;
464 u8 unit_1us:1;
465 enum hns3_flow_level_range flow_level;
466 };
467
468 struct hns3_enet_ring_group {
469 /* array of pointers to rings */
470 struct hns3_enet_ring *ring;
471 u64 total_bytes; /* total bytes processed this group */
472 u64 total_packets; /* total packets processed this group */
473 u16 count;
474 struct hns3_enet_coalesce coal;
475 };
476
477 struct hns3_enet_tqp_vector {
478 struct hnae3_handle *handle;
479 u8 __iomem *mask_addr;
480 int vector_irq;
481 int irq_init_flag;
482
483 u16 idx; /* index in the TQP vector array per handle. */
484
485 struct napi_struct napi;
486
487 struct hns3_enet_ring_group rx_group;
488 struct hns3_enet_ring_group tx_group;
489
490 cpumask_t affinity_mask;
491 u16 num_tqps; /* total number of tqps in TQP vector */
492 struct irq_affinity_notify affinity_notify;
493
494 char name[HNAE3_INT_NAME_LEN];
495
496 unsigned long last_jiffies;
497 } ____cacheline_internodealigned_in_smp;
498
499 struct hns3_nic_priv {
500 struct hnae3_handle *ae_handle;
501 struct net_device *netdev;
502 struct device *dev;
503
504 /**
505 * the cb for nic to manage the ring buffer, the first half of the
506 * array is for tx_ring and vice versa for the second half
507 */
508 struct hns3_enet_ring *ring;
509 struct hns3_enet_tqp_vector *tqp_vector;
510 u16 vector_num;
511 u8 max_non_tso_bd_num;
512
513 u64 tx_timeout_count;
514
515 unsigned long state;
516
517 struct hns3_enet_coalesce tx_coal;
518 struct hns3_enet_coalesce rx_coal;
519 };
520
521 union l3_hdr_info {
522 struct iphdr *v4;
523 struct ipv6hdr *v6;
524 unsigned char *hdr;
525 };
526
527 union l4_hdr_info {
528 struct tcphdr *tcp;
529 struct udphdr *udp;
530 struct gre_base_hdr *gre;
531 unsigned char *hdr;
532 };
533
534 struct hns3_hw_error_info {
535 enum hnae3_hw_error_type type;
536 const char *msg;
537 };
538
ring_space(struct hns3_enet_ring * ring)539 static inline int ring_space(struct hns3_enet_ring *ring)
540 {
541 /* This smp_load_acquire() pairs with smp_store_release() in
542 * hns3_nic_reclaim_one_desc called by hns3_clean_tx_ring.
543 */
544 int begin = smp_load_acquire(&ring->next_to_clean);
545 int end = READ_ONCE(ring->next_to_use);
546
547 return ((end >= begin) ? (ring->desc_num - end + begin) :
548 (begin - end)) - 1;
549 }
550
hns3_read_reg(void __iomem * base,u32 reg)551 static inline u32 hns3_read_reg(void __iomem *base, u32 reg)
552 {
553 return readl(base + reg);
554 }
555
hns3_write_reg(void __iomem * base,u32 reg,u32 value)556 static inline void hns3_write_reg(void __iomem *base, u32 reg, u32 value)
557 {
558 u8 __iomem *reg_addr = READ_ONCE(base);
559
560 writel(value, reg_addr + reg);
561 }
562
563 #define hns3_read_dev(a, reg) \
564 hns3_read_reg((a)->io_base, reg)
565
hns3_nic_resetting(struct net_device * netdev)566 static inline bool hns3_nic_resetting(struct net_device *netdev)
567 {
568 struct hns3_nic_priv *priv = netdev_priv(netdev);
569
570 return test_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
571 }
572
573 #define hns3_write_dev(a, reg, value) \
574 hns3_write_reg((a)->io_base, reg, value)
575
576 #define ring_to_dev(ring) ((ring)->dev)
577
578 #define ring_to_netdev(ring) ((ring)->tqp_vector->napi.dev)
579
580 #define ring_to_dma_dir(ring) (HNAE3_IS_TX_RING(ring) ? \
581 DMA_TO_DEVICE : DMA_FROM_DEVICE)
582
583 #define hns3_buf_size(_ring) ((_ring)->buf_size)
584
hns3_page_order(struct hns3_enet_ring * ring)585 static inline unsigned int hns3_page_order(struct hns3_enet_ring *ring)
586 {
587 #if (PAGE_SIZE < 8192)
588 if (ring->buf_size > (PAGE_SIZE / 2))
589 return 1;
590 #endif
591 return 0;
592 }
593
594 #define hns3_page_size(_ring) (PAGE_SIZE << hns3_page_order(_ring))
595
596 /* iterator for handling rings in ring group */
597 #define hns3_for_each_ring(pos, head) \
598 for (pos = (head).ring; (pos); pos = (pos)->next)
599
600 #define hns3_get_handle(ndev) \
601 (((struct hns3_nic_priv *)netdev_priv(ndev))->ae_handle)
602
603 #define hns3_gl_usec_to_reg(int_gl) ((int_gl) >> 1)
604 #define hns3_gl_round_down(int_gl) round_down(int_gl, 2)
605
606 #define hns3_rl_usec_to_reg(int_rl) ((int_rl) >> 2)
607 #define hns3_rl_round_down(int_rl) round_down(int_rl, 4)
608
609 void hns3_ethtool_set_ops(struct net_device *netdev);
610 int hns3_set_channels(struct net_device *netdev,
611 struct ethtool_channels *ch);
612
613 void hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget);
614 int hns3_init_all_ring(struct hns3_nic_priv *priv);
615 int hns3_nic_reset_all_ring(struct hnae3_handle *h);
616 void hns3_fini_ring(struct hns3_enet_ring *ring);
617 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev);
618 bool hns3_is_phys_func(struct pci_dev *pdev);
619 int hns3_clean_rx_ring(
620 struct hns3_enet_ring *ring, int budget,
621 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *));
622
623 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
624 u32 gl_value);
625 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
626 u32 gl_value);
627 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
628 u32 rl_value);
629 void hns3_set_vector_coalesce_rx_ql(struct hns3_enet_tqp_vector *tqp_vector,
630 u32 ql_value);
631 void hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector *tqp_vector,
632 u32 ql_value);
633
634 void hns3_enable_vlan_filter(struct net_device *netdev, bool enable);
635 void hns3_request_update_promisc_mode(struct hnae3_handle *handle);
636
637 #ifdef CONFIG_HNS3_DCB
638 void hns3_dcbnl_setup(struct hnae3_handle *handle);
639 #else
hns3_dcbnl_setup(struct hnae3_handle * handle)640 static inline void hns3_dcbnl_setup(struct hnae3_handle *handle) {}
641 #endif
642
643 void hns3_dbg_init(struct hnae3_handle *handle);
644 void hns3_dbg_uninit(struct hnae3_handle *handle);
645 void hns3_dbg_register_debugfs(const char *debugfs_dir_name);
646 void hns3_dbg_unregister_debugfs(void);
647 void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size);
648 #endif
649