1 // SPDX-License-Identifier: GPL-2.0-only
2 /* MCP23S08 SPI/I2C GPIO driver */
3
4 #include <linux/bitops.h>
5 #include <linux/kernel.h>
6 #include <linux/device.h>
7 #include <linux/mutex.h>
8 #include <linux/mod_devicetable.h>
9 #include <linux/module.h>
10 #include <linux/export.h>
11 #include <linux/gpio/driver.h>
12 #include <linux/slab.h>
13 #include <asm/byteorder.h>
14 #include <linux/interrupt.h>
15 #include <linux/regmap.h>
16 #include <linux/pinctrl/pinctrl.h>
17 #include <linux/pinctrl/pinconf.h>
18 #include <linux/pinctrl/pinconf-generic.h>
19
20 #include "pinctrl-mcp23s08.h"
21
22 /* Registers are all 8 bits wide.
23 *
24 * The mcp23s17 has twice as many bits, and can be configured to work
25 * with either 16 bit registers or with two adjacent 8 bit banks.
26 */
27 #define MCP_IODIR 0x00 /* init/reset: all ones */
28 #define MCP_IPOL 0x01
29 #define MCP_GPINTEN 0x02
30 #define MCP_DEFVAL 0x03
31 #define MCP_INTCON 0x04
32 #define MCP_IOCON 0x05
33 # define IOCON_MIRROR (1 << 6)
34 # define IOCON_SEQOP (1 << 5)
35 # define IOCON_HAEN (1 << 3)
36 # define IOCON_ODR (1 << 2)
37 # define IOCON_INTPOL (1 << 1)
38 # define IOCON_INTCC (1)
39 #define MCP_GPPU 0x06
40 #define MCP_INTF 0x07
41 #define MCP_INTCAP 0x08
42 #define MCP_GPIO 0x09
43 #define MCP_OLAT 0x0a
44
45 static const struct reg_default mcp23x08_defaults[] = {
46 {.reg = MCP_IODIR, .def = 0xff},
47 {.reg = MCP_IPOL, .def = 0x00},
48 {.reg = MCP_GPINTEN, .def = 0x00},
49 {.reg = MCP_DEFVAL, .def = 0x00},
50 {.reg = MCP_INTCON, .def = 0x00},
51 {.reg = MCP_IOCON, .def = 0x00},
52 {.reg = MCP_GPPU, .def = 0x00},
53 {.reg = MCP_OLAT, .def = 0x00},
54 };
55
56 static const struct regmap_range mcp23x08_volatile_range = {
57 .range_min = MCP_INTF,
58 .range_max = MCP_GPIO,
59 };
60
61 static const struct regmap_access_table mcp23x08_volatile_table = {
62 .yes_ranges = &mcp23x08_volatile_range,
63 .n_yes_ranges = 1,
64 };
65
66 static const struct regmap_range mcp23x08_precious_range = {
67 .range_min = MCP_GPIO,
68 .range_max = MCP_GPIO,
69 };
70
71 static const struct regmap_access_table mcp23x08_precious_table = {
72 .yes_ranges = &mcp23x08_precious_range,
73 .n_yes_ranges = 1,
74 };
75
76 const struct regmap_config mcp23x08_regmap = {
77 .reg_bits = 8,
78 .val_bits = 8,
79
80 .reg_stride = 1,
81 .volatile_table = &mcp23x08_volatile_table,
82 .precious_table = &mcp23x08_precious_table,
83 .reg_defaults = mcp23x08_defaults,
84 .num_reg_defaults = ARRAY_SIZE(mcp23x08_defaults),
85 .cache_type = REGCACHE_FLAT,
86 .max_register = MCP_OLAT,
87 };
88 EXPORT_SYMBOL_GPL(mcp23x08_regmap);
89
90 static const struct reg_default mcp23x17_defaults[] = {
91 {.reg = MCP_IODIR << 1, .def = 0xffff},
92 {.reg = MCP_IPOL << 1, .def = 0x0000},
93 {.reg = MCP_GPINTEN << 1, .def = 0x0000},
94 {.reg = MCP_DEFVAL << 1, .def = 0x0000},
95 {.reg = MCP_INTCON << 1, .def = 0x0000},
96 {.reg = MCP_IOCON << 1, .def = 0x0000},
97 {.reg = MCP_GPPU << 1, .def = 0x0000},
98 {.reg = MCP_OLAT << 1, .def = 0x0000},
99 };
100
101 static const struct regmap_range mcp23x17_volatile_range = {
102 .range_min = MCP_INTF << 1,
103 .range_max = MCP_GPIO << 1,
104 };
105
106 static const struct regmap_access_table mcp23x17_volatile_table = {
107 .yes_ranges = &mcp23x17_volatile_range,
108 .n_yes_ranges = 1,
109 };
110
111 static const struct regmap_range mcp23x17_precious_range = {
112 .range_min = MCP_INTCAP << 1,
113 .range_max = MCP_GPIO << 1,
114 };
115
116 static const struct regmap_access_table mcp23x17_precious_table = {
117 .yes_ranges = &mcp23x17_precious_range,
118 .n_yes_ranges = 1,
119 };
120
121 const struct regmap_config mcp23x17_regmap = {
122 .reg_bits = 8,
123 .val_bits = 16,
124
125 .reg_stride = 2,
126 .max_register = MCP_OLAT << 1,
127 .volatile_table = &mcp23x17_volatile_table,
128 .precious_table = &mcp23x17_precious_table,
129 .reg_defaults = mcp23x17_defaults,
130 .num_reg_defaults = ARRAY_SIZE(mcp23x17_defaults),
131 .cache_type = REGCACHE_FLAT,
132 .val_format_endian = REGMAP_ENDIAN_LITTLE,
133 };
134 EXPORT_SYMBOL_GPL(mcp23x17_regmap);
135
mcp_read(struct mcp23s08 * mcp,unsigned int reg,unsigned int * val)136 static int mcp_read(struct mcp23s08 *mcp, unsigned int reg, unsigned int *val)
137 {
138 return regmap_read(mcp->regmap, reg << mcp->reg_shift, val);
139 }
140
mcp_write(struct mcp23s08 * mcp,unsigned int reg,unsigned int val)141 static int mcp_write(struct mcp23s08 *mcp, unsigned int reg, unsigned int val)
142 {
143 return regmap_write(mcp->regmap, reg << mcp->reg_shift, val);
144 }
145
mcp_set_mask(struct mcp23s08 * mcp,unsigned int reg,unsigned int mask,bool enabled)146 static int mcp_set_mask(struct mcp23s08 *mcp, unsigned int reg,
147 unsigned int mask, bool enabled)
148 {
149 u16 val = enabled ? 0xffff : 0x0000;
150 return regmap_update_bits(mcp->regmap, reg << mcp->reg_shift,
151 mask, val);
152 }
153
mcp_set_bit(struct mcp23s08 * mcp,unsigned int reg,unsigned int pin,bool enabled)154 static int mcp_set_bit(struct mcp23s08 *mcp, unsigned int reg,
155 unsigned int pin, bool enabled)
156 {
157 u16 mask = BIT(pin);
158 return mcp_set_mask(mcp, reg, mask, enabled);
159 }
160
161 static const struct pinctrl_pin_desc mcp23x08_pins[] = {
162 PINCTRL_PIN(0, "gpio0"),
163 PINCTRL_PIN(1, "gpio1"),
164 PINCTRL_PIN(2, "gpio2"),
165 PINCTRL_PIN(3, "gpio3"),
166 PINCTRL_PIN(4, "gpio4"),
167 PINCTRL_PIN(5, "gpio5"),
168 PINCTRL_PIN(6, "gpio6"),
169 PINCTRL_PIN(7, "gpio7"),
170 };
171
172 static const struct pinctrl_pin_desc mcp23x17_pins[] = {
173 PINCTRL_PIN(0, "gpio0"),
174 PINCTRL_PIN(1, "gpio1"),
175 PINCTRL_PIN(2, "gpio2"),
176 PINCTRL_PIN(3, "gpio3"),
177 PINCTRL_PIN(4, "gpio4"),
178 PINCTRL_PIN(5, "gpio5"),
179 PINCTRL_PIN(6, "gpio6"),
180 PINCTRL_PIN(7, "gpio7"),
181 PINCTRL_PIN(8, "gpio8"),
182 PINCTRL_PIN(9, "gpio9"),
183 PINCTRL_PIN(10, "gpio10"),
184 PINCTRL_PIN(11, "gpio11"),
185 PINCTRL_PIN(12, "gpio12"),
186 PINCTRL_PIN(13, "gpio13"),
187 PINCTRL_PIN(14, "gpio14"),
188 PINCTRL_PIN(15, "gpio15"),
189 };
190
mcp_pinctrl_get_groups_count(struct pinctrl_dev * pctldev)191 static int mcp_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
192 {
193 return 0;
194 }
195
mcp_pinctrl_get_group_name(struct pinctrl_dev * pctldev,unsigned int group)196 static const char *mcp_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
197 unsigned int group)
198 {
199 return NULL;
200 }
201
mcp_pinctrl_get_group_pins(struct pinctrl_dev * pctldev,unsigned int group,const unsigned int ** pins,unsigned int * num_pins)202 static int mcp_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
203 unsigned int group,
204 const unsigned int **pins,
205 unsigned int *num_pins)
206 {
207 return -ENOTSUPP;
208 }
209
210 static const struct pinctrl_ops mcp_pinctrl_ops = {
211 .get_groups_count = mcp_pinctrl_get_groups_count,
212 .get_group_name = mcp_pinctrl_get_group_name,
213 .get_group_pins = mcp_pinctrl_get_group_pins,
214 #ifdef CONFIG_OF
215 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
216 .dt_free_map = pinconf_generic_dt_free_map,
217 #endif
218 };
219
mcp_pinconf_get(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * config)220 static int mcp_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
221 unsigned long *config)
222 {
223 struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev);
224 enum pin_config_param param = pinconf_to_config_param(*config);
225 unsigned int data, status;
226 int ret;
227
228 switch (param) {
229 case PIN_CONFIG_BIAS_PULL_UP:
230 ret = mcp_read(mcp, MCP_GPPU, &data);
231 if (ret < 0)
232 return ret;
233 status = (data & BIT(pin)) ? 1 : 0;
234 break;
235 default:
236 return -ENOTSUPP;
237 }
238
239 *config = 0;
240
241 return status ? 0 : -EINVAL;
242 }
243
mcp_pinconf_set(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned int num_configs)244 static int mcp_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
245 unsigned long *configs, unsigned int num_configs)
246 {
247 struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev);
248 enum pin_config_param param;
249 u32 arg;
250 int ret = 0;
251 int i;
252
253 for (i = 0; i < num_configs; i++) {
254 param = pinconf_to_config_param(configs[i]);
255 arg = pinconf_to_config_argument(configs[i]);
256
257 switch (param) {
258 case PIN_CONFIG_BIAS_PULL_UP:
259 ret = mcp_set_bit(mcp, MCP_GPPU, pin, arg);
260 break;
261 default:
262 dev_dbg(mcp->dev, "Invalid config param %04x\n", param);
263 return -ENOTSUPP;
264 }
265 }
266
267 return ret;
268 }
269
270 static const struct pinconf_ops mcp_pinconf_ops = {
271 .pin_config_get = mcp_pinconf_get,
272 .pin_config_set = mcp_pinconf_set,
273 .is_generic = true,
274 };
275
276 /*----------------------------------------------------------------------*/
277
mcp23s08_direction_input(struct gpio_chip * chip,unsigned offset)278 static int mcp23s08_direction_input(struct gpio_chip *chip, unsigned offset)
279 {
280 struct mcp23s08 *mcp = gpiochip_get_data(chip);
281 int status;
282
283 mutex_lock(&mcp->lock);
284 status = mcp_set_bit(mcp, MCP_IODIR, offset, true);
285 mutex_unlock(&mcp->lock);
286
287 return status;
288 }
289
mcp23s08_get(struct gpio_chip * chip,unsigned offset)290 static int mcp23s08_get(struct gpio_chip *chip, unsigned offset)
291 {
292 struct mcp23s08 *mcp = gpiochip_get_data(chip);
293 int status, ret;
294
295 mutex_lock(&mcp->lock);
296
297 /* REVISIT reading this clears any IRQ ... */
298 ret = mcp_read(mcp, MCP_GPIO, &status);
299 if (ret < 0)
300 status = 0;
301 else {
302 mcp->cached_gpio = status;
303 status = !!(status & (1 << offset));
304 }
305
306 mutex_unlock(&mcp->lock);
307 return status;
308 }
309
__mcp23s08_set(struct mcp23s08 * mcp,unsigned mask,bool value)310 static int __mcp23s08_set(struct mcp23s08 *mcp, unsigned mask, bool value)
311 {
312 return mcp_set_mask(mcp, MCP_OLAT, mask, value);
313 }
314
mcp23s08_set(struct gpio_chip * chip,unsigned offset,int value)315 static void mcp23s08_set(struct gpio_chip *chip, unsigned offset, int value)
316 {
317 struct mcp23s08 *mcp = gpiochip_get_data(chip);
318 unsigned mask = BIT(offset);
319
320 mutex_lock(&mcp->lock);
321 __mcp23s08_set(mcp, mask, !!value);
322 mutex_unlock(&mcp->lock);
323 }
324
325 static int
mcp23s08_direction_output(struct gpio_chip * chip,unsigned offset,int value)326 mcp23s08_direction_output(struct gpio_chip *chip, unsigned offset, int value)
327 {
328 struct mcp23s08 *mcp = gpiochip_get_data(chip);
329 unsigned mask = BIT(offset);
330 int status;
331
332 mutex_lock(&mcp->lock);
333 status = __mcp23s08_set(mcp, mask, value);
334 if (status == 0) {
335 status = mcp_set_mask(mcp, MCP_IODIR, mask, false);
336 }
337 mutex_unlock(&mcp->lock);
338 return status;
339 }
340
341 /*----------------------------------------------------------------------*/
mcp23s08_irq(int irq,void * data)342 static irqreturn_t mcp23s08_irq(int irq, void *data)
343 {
344 struct mcp23s08 *mcp = data;
345 int intcap, intcon, intf, i, gpio, gpio_orig, intcap_mask, defval;
346 unsigned int child_irq;
347 bool intf_set, intcap_changed, gpio_bit_changed,
348 defval_changed, gpio_set;
349
350 mutex_lock(&mcp->lock);
351 if (mcp_read(mcp, MCP_INTF, &intf))
352 goto unlock;
353
354 if (mcp_read(mcp, MCP_INTCAP, &intcap))
355 goto unlock;
356
357 if (mcp_read(mcp, MCP_INTCON, &intcon))
358 goto unlock;
359
360 if (mcp_read(mcp, MCP_DEFVAL, &defval))
361 goto unlock;
362
363 /* This clears the interrupt(configurable on S18) */
364 if (mcp_read(mcp, MCP_GPIO, &gpio))
365 goto unlock;
366
367 gpio_orig = mcp->cached_gpio;
368 mcp->cached_gpio = gpio;
369 mutex_unlock(&mcp->lock);
370
371 if (intf == 0) {
372 /* There is no interrupt pending */
373 return IRQ_HANDLED;
374 }
375
376 dev_dbg(mcp->chip.parent,
377 "intcap 0x%04X intf 0x%04X gpio_orig 0x%04X gpio 0x%04X\n",
378 intcap, intf, gpio_orig, gpio);
379
380 for (i = 0; i < mcp->chip.ngpio; i++) {
381 /* We must check all of the inputs on the chip,
382 * otherwise we may not notice a change on >=2 pins.
383 *
384 * On at least the mcp23s17, INTCAP is only updated
385 * one byte at a time(INTCAPA and INTCAPB are
386 * not written to at the same time - only on a per-bank
387 * basis).
388 *
389 * INTF only contains the single bit that caused the
390 * interrupt per-bank. On the mcp23s17, there is
391 * INTFA and INTFB. If two pins are changed on the A
392 * side at the same time, INTF will only have one bit
393 * set. If one pin on the A side and one pin on the B
394 * side are changed at the same time, INTF will have
395 * two bits set. Thus, INTF can't be the only check
396 * to see if the input has changed.
397 */
398
399 intf_set = intf & BIT(i);
400 if (i < 8 && intf_set)
401 intcap_mask = 0x00FF;
402 else if (i >= 8 && intf_set)
403 intcap_mask = 0xFF00;
404 else
405 intcap_mask = 0x00;
406
407 intcap_changed = (intcap_mask &
408 (intcap & BIT(i))) !=
409 (intcap_mask & (BIT(i) & gpio_orig));
410 gpio_set = BIT(i) & gpio;
411 gpio_bit_changed = (BIT(i) & gpio_orig) !=
412 (BIT(i) & gpio);
413 defval_changed = (BIT(i) & intcon) &&
414 ((BIT(i) & gpio) !=
415 (BIT(i) & defval));
416
417 if (((gpio_bit_changed || intcap_changed) &&
418 (BIT(i) & mcp->irq_rise) && gpio_set) ||
419 ((gpio_bit_changed || intcap_changed) &&
420 (BIT(i) & mcp->irq_fall) && !gpio_set) ||
421 defval_changed) {
422 child_irq = irq_find_mapping(mcp->chip.irq.domain, i);
423 handle_nested_irq(child_irq);
424 }
425 }
426
427 return IRQ_HANDLED;
428
429 unlock:
430 mutex_unlock(&mcp->lock);
431 return IRQ_HANDLED;
432 }
433
mcp23s08_irq_mask(struct irq_data * data)434 static void mcp23s08_irq_mask(struct irq_data *data)
435 {
436 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
437 struct mcp23s08 *mcp = gpiochip_get_data(gc);
438 unsigned int pos = data->hwirq;
439
440 mcp_set_bit(mcp, MCP_GPINTEN, pos, false);
441 }
442
mcp23s08_irq_unmask(struct irq_data * data)443 static void mcp23s08_irq_unmask(struct irq_data *data)
444 {
445 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
446 struct mcp23s08 *mcp = gpiochip_get_data(gc);
447 unsigned int pos = data->hwirq;
448
449 mcp_set_bit(mcp, MCP_GPINTEN, pos, true);
450 }
451
mcp23s08_irq_set_type(struct irq_data * data,unsigned int type)452 static int mcp23s08_irq_set_type(struct irq_data *data, unsigned int type)
453 {
454 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
455 struct mcp23s08 *mcp = gpiochip_get_data(gc);
456 unsigned int pos = data->hwirq;
457
458 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
459 mcp_set_bit(mcp, MCP_INTCON, pos, false);
460 mcp->irq_rise |= BIT(pos);
461 mcp->irq_fall |= BIT(pos);
462 } else if (type & IRQ_TYPE_EDGE_RISING) {
463 mcp_set_bit(mcp, MCP_INTCON, pos, false);
464 mcp->irq_rise |= BIT(pos);
465 mcp->irq_fall &= ~BIT(pos);
466 } else if (type & IRQ_TYPE_EDGE_FALLING) {
467 mcp_set_bit(mcp, MCP_INTCON, pos, false);
468 mcp->irq_rise &= ~BIT(pos);
469 mcp->irq_fall |= BIT(pos);
470 } else if (type & IRQ_TYPE_LEVEL_HIGH) {
471 mcp_set_bit(mcp, MCP_INTCON, pos, true);
472 mcp_set_bit(mcp, MCP_DEFVAL, pos, false);
473 } else if (type & IRQ_TYPE_LEVEL_LOW) {
474 mcp_set_bit(mcp, MCP_INTCON, pos, true);
475 mcp_set_bit(mcp, MCP_DEFVAL, pos, true);
476 } else
477 return -EINVAL;
478
479 return 0;
480 }
481
mcp23s08_irq_bus_lock(struct irq_data * data)482 static void mcp23s08_irq_bus_lock(struct irq_data *data)
483 {
484 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
485 struct mcp23s08 *mcp = gpiochip_get_data(gc);
486
487 mutex_lock(&mcp->lock);
488 regcache_cache_only(mcp->regmap, true);
489 }
490
mcp23s08_irq_bus_unlock(struct irq_data * data)491 static void mcp23s08_irq_bus_unlock(struct irq_data *data)
492 {
493 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
494 struct mcp23s08 *mcp = gpiochip_get_data(gc);
495
496 regcache_cache_only(mcp->regmap, false);
497 regcache_sync(mcp->regmap);
498
499 mutex_unlock(&mcp->lock);
500 }
501
mcp23s08_irq_setup(struct mcp23s08 * mcp)502 static int mcp23s08_irq_setup(struct mcp23s08 *mcp)
503 {
504 struct gpio_chip *chip = &mcp->chip;
505 int err;
506 unsigned long irqflags = IRQF_ONESHOT | IRQF_SHARED;
507
508 if (mcp->irq_active_high)
509 irqflags |= IRQF_TRIGGER_HIGH;
510 else
511 irqflags |= IRQF_TRIGGER_LOW;
512
513 err = devm_request_threaded_irq(chip->parent, mcp->irq, NULL,
514 mcp23s08_irq,
515 irqflags, dev_name(chip->parent), mcp);
516 if (err != 0) {
517 dev_err(chip->parent, "unable to request IRQ#%d: %d\n",
518 mcp->irq, err);
519 return err;
520 }
521
522 return 0;
523 }
524
525 /*----------------------------------------------------------------------*/
526
mcp23s08_probe_one(struct mcp23s08 * mcp,struct device * dev,unsigned int addr,unsigned int type,unsigned int base)527 int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
528 unsigned int addr, unsigned int type, unsigned int base)
529 {
530 int status, ret;
531 bool mirror = false;
532 bool open_drain = false;
533
534 mutex_init(&mcp->lock);
535
536 mcp->dev = dev;
537 mcp->addr = addr;
538
539 mcp->irq_active_high = false;
540 mcp->irq_chip.name = dev_name(dev);
541 mcp->irq_chip.irq_mask = mcp23s08_irq_mask;
542 mcp->irq_chip.irq_unmask = mcp23s08_irq_unmask;
543 mcp->irq_chip.irq_set_type = mcp23s08_irq_set_type;
544 mcp->irq_chip.irq_bus_lock = mcp23s08_irq_bus_lock;
545 mcp->irq_chip.irq_bus_sync_unlock = mcp23s08_irq_bus_unlock;
546
547 mcp->chip.direction_input = mcp23s08_direction_input;
548 mcp->chip.get = mcp23s08_get;
549 mcp->chip.direction_output = mcp23s08_direction_output;
550 mcp->chip.set = mcp23s08_set;
551 #ifdef CONFIG_OF_GPIO
552 mcp->chip.of_gpio_n_cells = 2;
553 mcp->chip.of_node = dev->of_node;
554 #endif
555
556 mcp->chip.base = base;
557 mcp->chip.can_sleep = true;
558 mcp->chip.parent = dev;
559 mcp->chip.owner = THIS_MODULE;
560
561 /* verify MCP_IOCON.SEQOP = 0, so sequential reads work,
562 * and MCP_IOCON.HAEN = 1, so we work with all chips.
563 */
564
565 ret = mcp_read(mcp, MCP_IOCON, &status);
566 if (ret < 0)
567 return dev_err_probe(dev, ret, "can't identify chip %d\n", addr);
568
569 mcp->irq_controller =
570 device_property_read_bool(dev, "interrupt-controller");
571 if (mcp->irq && mcp->irq_controller) {
572 mcp->irq_active_high =
573 device_property_read_bool(dev,
574 "microchip,irq-active-high");
575
576 mirror = device_property_read_bool(dev, "microchip,irq-mirror");
577 open_drain = device_property_read_bool(dev, "drive-open-drain");
578 }
579
580 if ((status & IOCON_SEQOP) || !(status & IOCON_HAEN) || mirror ||
581 mcp->irq_active_high || open_drain) {
582 /* mcp23s17 has IOCON twice, make sure they are in sync */
583 status &= ~(IOCON_SEQOP | (IOCON_SEQOP << 8));
584 status |= IOCON_HAEN | (IOCON_HAEN << 8);
585 if (mcp->irq_active_high)
586 status |= IOCON_INTPOL | (IOCON_INTPOL << 8);
587 else
588 status &= ~(IOCON_INTPOL | (IOCON_INTPOL << 8));
589
590 if (mirror)
591 status |= IOCON_MIRROR | (IOCON_MIRROR << 8);
592
593 if (open_drain)
594 status |= IOCON_ODR | (IOCON_ODR << 8);
595
596 if (type == MCP_TYPE_S18 || type == MCP_TYPE_018)
597 status |= IOCON_INTCC | (IOCON_INTCC << 8);
598
599 ret = mcp_write(mcp, MCP_IOCON, status);
600 if (ret < 0)
601 return dev_err_probe(dev, ret, "can't write IOCON %d\n", addr);
602 }
603
604 if (mcp->irq && mcp->irq_controller) {
605 struct gpio_irq_chip *girq = &mcp->chip.irq;
606
607 girq->chip = &mcp->irq_chip;
608 /* This will let us handle the parent IRQ in the driver */
609 girq->parent_handler = NULL;
610 girq->num_parents = 0;
611 girq->parents = NULL;
612 girq->default_type = IRQ_TYPE_NONE;
613 girq->handler = handle_simple_irq;
614 girq->threaded = true;
615 }
616
617 ret = devm_gpiochip_add_data(dev, &mcp->chip, mcp);
618 if (ret < 0)
619 return dev_err_probe(dev, ret, "can't add GPIO chip\n");
620
621 mcp->pinctrl_desc.pctlops = &mcp_pinctrl_ops;
622 mcp->pinctrl_desc.confops = &mcp_pinconf_ops;
623 mcp->pinctrl_desc.npins = mcp->chip.ngpio;
624 if (mcp->pinctrl_desc.npins == 8)
625 mcp->pinctrl_desc.pins = mcp23x08_pins;
626 else if (mcp->pinctrl_desc.npins == 16)
627 mcp->pinctrl_desc.pins = mcp23x17_pins;
628 mcp->pinctrl_desc.owner = THIS_MODULE;
629
630 mcp->pctldev = devm_pinctrl_register(dev, &mcp->pinctrl_desc, mcp);
631 if (IS_ERR(mcp->pctldev))
632 return dev_err_probe(dev, PTR_ERR(mcp->pctldev), "can't register controller\n");
633
634 if (mcp->irq) {
635 ret = mcp23s08_irq_setup(mcp);
636 if (ret)
637 return dev_err_probe(dev, ret, "can't setup IRQ\n");
638 }
639
640 return 0;
641 }
642 EXPORT_SYMBOL_GPL(mcp23s08_probe_one);
643
644 MODULE_LICENSE("GPL");
645