1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for Atmel QSPI Controller
4 *
5 * Copyright (C) 2015 Atmel Corporation
6 * Copyright (C) 2018 Cryptera A/S
7 *
8 * Author: Cyrille Pitchen <cyrille.pitchen@atmel.com>
9 * Author: Piotr Bugalski <bugalski.piotr@gmail.com>
10 *
11 * This driver is based on drivers/mtd/spi-nor/fsl-quadspi.c from Freescale.
12 */
13
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/err.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/of.h>
22 #include <linux/of_platform.h>
23 #include <linux/platform_device.h>
24 #include <linux/spi/spi-mem.h>
25
26 /* QSPI register offsets */
27 #define QSPI_CR 0x0000 /* Control Register */
28 #define QSPI_MR 0x0004 /* Mode Register */
29 #define QSPI_RD 0x0008 /* Receive Data Register */
30 #define QSPI_TD 0x000c /* Transmit Data Register */
31 #define QSPI_SR 0x0010 /* Status Register */
32 #define QSPI_IER 0x0014 /* Interrupt Enable Register */
33 #define QSPI_IDR 0x0018 /* Interrupt Disable Register */
34 #define QSPI_IMR 0x001c /* Interrupt Mask Register */
35 #define QSPI_SCR 0x0020 /* Serial Clock Register */
36
37 #define QSPI_IAR 0x0030 /* Instruction Address Register */
38 #define QSPI_ICR 0x0034 /* Instruction Code Register */
39 #define QSPI_WICR 0x0034 /* Write Instruction Code Register */
40 #define QSPI_IFR 0x0038 /* Instruction Frame Register */
41 #define QSPI_RICR 0x003C /* Read Instruction Code Register */
42
43 #define QSPI_SMR 0x0040 /* Scrambling Mode Register */
44 #define QSPI_SKR 0x0044 /* Scrambling Key Register */
45
46 #define QSPI_WPMR 0x00E4 /* Write Protection Mode Register */
47 #define QSPI_WPSR 0x00E8 /* Write Protection Status Register */
48
49 #define QSPI_VERSION 0x00FC /* Version Register */
50
51
52 /* Bitfields in QSPI_CR (Control Register) */
53 #define QSPI_CR_QSPIEN BIT(0)
54 #define QSPI_CR_QSPIDIS BIT(1)
55 #define QSPI_CR_SWRST BIT(7)
56 #define QSPI_CR_LASTXFER BIT(24)
57
58 /* Bitfields in QSPI_MR (Mode Register) */
59 #define QSPI_MR_SMM BIT(0)
60 #define QSPI_MR_LLB BIT(1)
61 #define QSPI_MR_WDRBT BIT(2)
62 #define QSPI_MR_SMRM BIT(3)
63 #define QSPI_MR_CSMODE_MASK GENMASK(5, 4)
64 #define QSPI_MR_CSMODE_NOT_RELOADED (0 << 4)
65 #define QSPI_MR_CSMODE_LASTXFER (1 << 4)
66 #define QSPI_MR_CSMODE_SYSTEMATICALLY (2 << 4)
67 #define QSPI_MR_NBBITS_MASK GENMASK(11, 8)
68 #define QSPI_MR_NBBITS(n) ((((n) - 8) << 8) & QSPI_MR_NBBITS_MASK)
69 #define QSPI_MR_DLYBCT_MASK GENMASK(23, 16)
70 #define QSPI_MR_DLYBCT(n) (((n) << 16) & QSPI_MR_DLYBCT_MASK)
71 #define QSPI_MR_DLYCS_MASK GENMASK(31, 24)
72 #define QSPI_MR_DLYCS(n) (((n) << 24) & QSPI_MR_DLYCS_MASK)
73
74 /* Bitfields in QSPI_SR/QSPI_IER/QSPI_IDR/QSPI_IMR */
75 #define QSPI_SR_RDRF BIT(0)
76 #define QSPI_SR_TDRE BIT(1)
77 #define QSPI_SR_TXEMPTY BIT(2)
78 #define QSPI_SR_OVRES BIT(3)
79 #define QSPI_SR_CSR BIT(8)
80 #define QSPI_SR_CSS BIT(9)
81 #define QSPI_SR_INSTRE BIT(10)
82 #define QSPI_SR_QSPIENS BIT(24)
83
84 #define QSPI_SR_CMD_COMPLETED (QSPI_SR_INSTRE | QSPI_SR_CSR)
85
86 /* Bitfields in QSPI_SCR (Serial Clock Register) */
87 #define QSPI_SCR_CPOL BIT(0)
88 #define QSPI_SCR_CPHA BIT(1)
89 #define QSPI_SCR_SCBR_MASK GENMASK(15, 8)
90 #define QSPI_SCR_SCBR(n) (((n) << 8) & QSPI_SCR_SCBR_MASK)
91 #define QSPI_SCR_DLYBS_MASK GENMASK(23, 16)
92 #define QSPI_SCR_DLYBS(n) (((n) << 16) & QSPI_SCR_DLYBS_MASK)
93
94 /* Bitfields in QSPI_ICR (Read/Write Instruction Code Register) */
95 #define QSPI_ICR_INST_MASK GENMASK(7, 0)
96 #define QSPI_ICR_INST(inst) (((inst) << 0) & QSPI_ICR_INST_MASK)
97 #define QSPI_ICR_OPT_MASK GENMASK(23, 16)
98 #define QSPI_ICR_OPT(opt) (((opt) << 16) & QSPI_ICR_OPT_MASK)
99
100 /* Bitfields in QSPI_IFR (Instruction Frame Register) */
101 #define QSPI_IFR_WIDTH_MASK GENMASK(2, 0)
102 #define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0 << 0)
103 #define QSPI_IFR_WIDTH_DUAL_OUTPUT (1 << 0)
104 #define QSPI_IFR_WIDTH_QUAD_OUTPUT (2 << 0)
105 #define QSPI_IFR_WIDTH_DUAL_IO (3 << 0)
106 #define QSPI_IFR_WIDTH_QUAD_IO (4 << 0)
107 #define QSPI_IFR_WIDTH_DUAL_CMD (5 << 0)
108 #define QSPI_IFR_WIDTH_QUAD_CMD (6 << 0)
109 #define QSPI_IFR_INSTEN BIT(4)
110 #define QSPI_IFR_ADDREN BIT(5)
111 #define QSPI_IFR_OPTEN BIT(6)
112 #define QSPI_IFR_DATAEN BIT(7)
113 #define QSPI_IFR_OPTL_MASK GENMASK(9, 8)
114 #define QSPI_IFR_OPTL_1BIT (0 << 8)
115 #define QSPI_IFR_OPTL_2BIT (1 << 8)
116 #define QSPI_IFR_OPTL_4BIT (2 << 8)
117 #define QSPI_IFR_OPTL_8BIT (3 << 8)
118 #define QSPI_IFR_ADDRL BIT(10)
119 #define QSPI_IFR_TFRTYP_MEM BIT(12)
120 #define QSPI_IFR_SAMA5D2_WRITE_TRSFR BIT(13)
121 #define QSPI_IFR_CRM BIT(14)
122 #define QSPI_IFR_NBDUM_MASK GENMASK(20, 16)
123 #define QSPI_IFR_NBDUM(n) (((n) << 16) & QSPI_IFR_NBDUM_MASK)
124 #define QSPI_IFR_APBTFRTYP_READ BIT(24) /* Defined in SAM9X60 */
125
126 /* Bitfields in QSPI_SMR (Scrambling Mode Register) */
127 #define QSPI_SMR_SCREN BIT(0)
128 #define QSPI_SMR_RVDIS BIT(1)
129
130 /* Bitfields in QSPI_WPMR (Write Protection Mode Register) */
131 #define QSPI_WPMR_WPEN BIT(0)
132 #define QSPI_WPMR_WPKEY_MASK GENMASK(31, 8)
133 #define QSPI_WPMR_WPKEY(wpkey) (((wpkey) << 8) & QSPI_WPMR_WPKEY_MASK)
134
135 /* Bitfields in QSPI_WPSR (Write Protection Status Register) */
136 #define QSPI_WPSR_WPVS BIT(0)
137 #define QSPI_WPSR_WPVSRC_MASK GENMASK(15, 8)
138 #define QSPI_WPSR_WPVSRC(src) (((src) << 8) & QSPI_WPSR_WPVSRC)
139
140 struct atmel_qspi_caps {
141 bool has_qspick;
142 bool has_ricr;
143 };
144
145 struct atmel_qspi {
146 void __iomem *regs;
147 void __iomem *mem;
148 struct clk *pclk;
149 struct clk *qspick;
150 struct platform_device *pdev;
151 const struct atmel_qspi_caps *caps;
152 resource_size_t mmap_size;
153 u32 pending;
154 u32 mr;
155 u32 scr;
156 struct completion cmd_completion;
157 };
158
159 struct atmel_qspi_mode {
160 u8 cmd_buswidth;
161 u8 addr_buswidth;
162 u8 data_buswidth;
163 u32 config;
164 };
165
166 static const struct atmel_qspi_mode atmel_qspi_modes[] = {
167 { 1, 1, 1, QSPI_IFR_WIDTH_SINGLE_BIT_SPI },
168 { 1, 1, 2, QSPI_IFR_WIDTH_DUAL_OUTPUT },
169 { 1, 1, 4, QSPI_IFR_WIDTH_QUAD_OUTPUT },
170 { 1, 2, 2, QSPI_IFR_WIDTH_DUAL_IO },
171 { 1, 4, 4, QSPI_IFR_WIDTH_QUAD_IO },
172 { 2, 2, 2, QSPI_IFR_WIDTH_DUAL_CMD },
173 { 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD },
174 };
175
176 #ifdef VERBOSE_DEBUG
atmel_qspi_reg_name(u32 offset,char * tmp,size_t sz)177 static const char *atmel_qspi_reg_name(u32 offset, char *tmp, size_t sz)
178 {
179 switch (offset) {
180 case QSPI_CR:
181 return "CR";
182 case QSPI_MR:
183 return "MR";
184 case QSPI_RD:
185 return "MR";
186 case QSPI_TD:
187 return "TD";
188 case QSPI_SR:
189 return "SR";
190 case QSPI_IER:
191 return "IER";
192 case QSPI_IDR:
193 return "IDR";
194 case QSPI_IMR:
195 return "IMR";
196 case QSPI_SCR:
197 return "SCR";
198 case QSPI_IAR:
199 return "IAR";
200 case QSPI_ICR:
201 return "ICR/WICR";
202 case QSPI_IFR:
203 return "IFR";
204 case QSPI_RICR:
205 return "RICR";
206 case QSPI_SMR:
207 return "SMR";
208 case QSPI_SKR:
209 return "SKR";
210 case QSPI_WPMR:
211 return "WPMR";
212 case QSPI_WPSR:
213 return "WPSR";
214 case QSPI_VERSION:
215 return "VERSION";
216 default:
217 snprintf(tmp, sz, "0x%02x", offset);
218 break;
219 }
220
221 return tmp;
222 }
223 #endif /* VERBOSE_DEBUG */
224
atmel_qspi_read(struct atmel_qspi * aq,u32 offset)225 static u32 atmel_qspi_read(struct atmel_qspi *aq, u32 offset)
226 {
227 u32 value = readl_relaxed(aq->regs + offset);
228
229 #ifdef VERBOSE_DEBUG
230 char tmp[8];
231
232 dev_vdbg(&aq->pdev->dev, "read 0x%08x from %s\n", value,
233 atmel_qspi_reg_name(offset, tmp, sizeof(tmp)));
234 #endif /* VERBOSE_DEBUG */
235
236 return value;
237 }
238
atmel_qspi_write(u32 value,struct atmel_qspi * aq,u32 offset)239 static void atmel_qspi_write(u32 value, struct atmel_qspi *aq, u32 offset)
240 {
241 #ifdef VERBOSE_DEBUG
242 char tmp[8];
243
244 dev_vdbg(&aq->pdev->dev, "write 0x%08x into %s\n", value,
245 atmel_qspi_reg_name(offset, tmp, sizeof(tmp)));
246 #endif /* VERBOSE_DEBUG */
247
248 writel_relaxed(value, aq->regs + offset);
249 }
250
atmel_qspi_is_compatible(const struct spi_mem_op * op,const struct atmel_qspi_mode * mode)251 static inline bool atmel_qspi_is_compatible(const struct spi_mem_op *op,
252 const struct atmel_qspi_mode *mode)
253 {
254 if (op->cmd.buswidth != mode->cmd_buswidth)
255 return false;
256
257 if (op->addr.nbytes && op->addr.buswidth != mode->addr_buswidth)
258 return false;
259
260 if (op->data.nbytes && op->data.buswidth != mode->data_buswidth)
261 return false;
262
263 return true;
264 }
265
atmel_qspi_find_mode(const struct spi_mem_op * op)266 static int atmel_qspi_find_mode(const struct spi_mem_op *op)
267 {
268 u32 i;
269
270 for (i = 0; i < ARRAY_SIZE(atmel_qspi_modes); i++)
271 if (atmel_qspi_is_compatible(op, &atmel_qspi_modes[i]))
272 return i;
273
274 return -ENOTSUPP;
275 }
276
atmel_qspi_supports_op(struct spi_mem * mem,const struct spi_mem_op * op)277 static bool atmel_qspi_supports_op(struct spi_mem *mem,
278 const struct spi_mem_op *op)
279 {
280 if (atmel_qspi_find_mode(op) < 0)
281 return false;
282
283 /* special case not supported by hardware */
284 if (op->addr.nbytes == 2 && op->cmd.buswidth != op->addr.buswidth &&
285 op->dummy.nbytes == 0)
286 return false;
287
288 /* DTR ops not supported. */
289 if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr)
290 return false;
291 if (op->cmd.nbytes != 1)
292 return false;
293
294 return true;
295 }
296
atmel_qspi_set_cfg(struct atmel_qspi * aq,const struct spi_mem_op * op,u32 * offset)297 static int atmel_qspi_set_cfg(struct atmel_qspi *aq,
298 const struct spi_mem_op *op, u32 *offset)
299 {
300 u32 iar, icr, ifr;
301 u32 dummy_cycles = 0;
302 int mode;
303
304 iar = 0;
305 icr = QSPI_ICR_INST(op->cmd.opcode);
306 ifr = QSPI_IFR_INSTEN;
307
308 mode = atmel_qspi_find_mode(op);
309 if (mode < 0)
310 return mode;
311 ifr |= atmel_qspi_modes[mode].config;
312
313 if (op->dummy.buswidth && op->dummy.nbytes)
314 dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth;
315
316 /*
317 * The controller allows 24 and 32-bit addressing while NAND-flash
318 * requires 16-bit long. Handling 8-bit long addresses is done using
319 * the option field. For the 16-bit addresses, the workaround depends
320 * of the number of requested dummy bits. If there are 8 or more dummy
321 * cycles, the address is shifted and sent with the first dummy byte.
322 * Otherwise opcode is disabled and the first byte of the address
323 * contains the command opcode (works only if the opcode and address
324 * use the same buswidth). The limitation is when the 16-bit address is
325 * used without enough dummy cycles and the opcode is using a different
326 * buswidth than the address.
327 */
328 if (op->addr.buswidth) {
329 switch (op->addr.nbytes) {
330 case 0:
331 break;
332 case 1:
333 ifr |= QSPI_IFR_OPTEN | QSPI_IFR_OPTL_8BIT;
334 icr |= QSPI_ICR_OPT(op->addr.val & 0xff);
335 break;
336 case 2:
337 if (dummy_cycles < 8 / op->addr.buswidth) {
338 ifr &= ~QSPI_IFR_INSTEN;
339 ifr |= QSPI_IFR_ADDREN;
340 iar = (op->cmd.opcode << 16) |
341 (op->addr.val & 0xffff);
342 } else {
343 ifr |= QSPI_IFR_ADDREN;
344 iar = (op->addr.val << 8) & 0xffffff;
345 dummy_cycles -= 8 / op->addr.buswidth;
346 }
347 break;
348 case 3:
349 ifr |= QSPI_IFR_ADDREN;
350 iar = op->addr.val & 0xffffff;
351 break;
352 case 4:
353 ifr |= QSPI_IFR_ADDREN | QSPI_IFR_ADDRL;
354 iar = op->addr.val & 0x7ffffff;
355 break;
356 default:
357 return -ENOTSUPP;
358 }
359 }
360
361 /* offset of the data access in the QSPI memory space */
362 *offset = iar;
363
364 /* Set number of dummy cycles */
365 if (dummy_cycles)
366 ifr |= QSPI_IFR_NBDUM(dummy_cycles);
367
368 /* Set data enable and data transfer type. */
369 if (op->data.nbytes) {
370 ifr |= QSPI_IFR_DATAEN;
371
372 if (op->addr.nbytes)
373 ifr |= QSPI_IFR_TFRTYP_MEM;
374 }
375
376 /*
377 * If the QSPI controller is set in regular SPI mode, set it in
378 * Serial Memory Mode (SMM).
379 */
380 if (aq->mr != QSPI_MR_SMM) {
381 atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR);
382 aq->mr = QSPI_MR_SMM;
383 }
384
385 /* Clear pending interrupts */
386 (void)atmel_qspi_read(aq, QSPI_SR);
387
388 /* Set QSPI Instruction Frame registers. */
389 if (op->addr.nbytes && !op->data.nbytes)
390 atmel_qspi_write(iar, aq, QSPI_IAR);
391
392 if (aq->caps->has_ricr) {
393 if (op->data.dir == SPI_MEM_DATA_IN)
394 atmel_qspi_write(icr, aq, QSPI_RICR);
395 else
396 atmel_qspi_write(icr, aq, QSPI_WICR);
397 } else {
398 if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
399 ifr |= QSPI_IFR_SAMA5D2_WRITE_TRSFR;
400
401 atmel_qspi_write(icr, aq, QSPI_ICR);
402 }
403
404 atmel_qspi_write(ifr, aq, QSPI_IFR);
405
406 return 0;
407 }
408
atmel_qspi_exec_op(struct spi_mem * mem,const struct spi_mem_op * op)409 static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
410 {
411 struct atmel_qspi *aq = spi_controller_get_devdata(mem->spi->master);
412 u32 sr, offset;
413 int err;
414
415 /*
416 * Check if the address exceeds the MMIO window size. An improvement
417 * would be to add support for regular SPI mode and fall back to it
418 * when the flash memories overrun the controller's memory space.
419 */
420 if (op->addr.val + op->data.nbytes > aq->mmap_size)
421 return -ENOTSUPP;
422
423 err = atmel_qspi_set_cfg(aq, op, &offset);
424 if (err)
425 return err;
426
427 /* Skip to the final steps if there is no data */
428 if (op->data.nbytes) {
429 /* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */
430 (void)atmel_qspi_read(aq, QSPI_IFR);
431
432 /* Send/Receive data */
433 if (op->data.dir == SPI_MEM_DATA_IN)
434 memcpy_fromio(op->data.buf.in, aq->mem + offset,
435 op->data.nbytes);
436 else
437 memcpy_toio(aq->mem + offset, op->data.buf.out,
438 op->data.nbytes);
439
440 /* Release the chip-select */
441 atmel_qspi_write(QSPI_CR_LASTXFER, aq, QSPI_CR);
442 }
443
444 /* Poll INSTRuction End status */
445 sr = atmel_qspi_read(aq, QSPI_SR);
446 if ((sr & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED)
447 return err;
448
449 /* Wait for INSTRuction End interrupt */
450 reinit_completion(&aq->cmd_completion);
451 aq->pending = sr & QSPI_SR_CMD_COMPLETED;
452 atmel_qspi_write(QSPI_SR_CMD_COMPLETED, aq, QSPI_IER);
453 if (!wait_for_completion_timeout(&aq->cmd_completion,
454 msecs_to_jiffies(1000)))
455 err = -ETIMEDOUT;
456 atmel_qspi_write(QSPI_SR_CMD_COMPLETED, aq, QSPI_IDR);
457
458 return err;
459 }
460
atmel_qspi_get_name(struct spi_mem * spimem)461 static const char *atmel_qspi_get_name(struct spi_mem *spimem)
462 {
463 return dev_name(spimem->spi->dev.parent);
464 }
465
466 static const struct spi_controller_mem_ops atmel_qspi_mem_ops = {
467 .supports_op = atmel_qspi_supports_op,
468 .exec_op = atmel_qspi_exec_op,
469 .get_name = atmel_qspi_get_name
470 };
471
atmel_qspi_setup(struct spi_device * spi)472 static int atmel_qspi_setup(struct spi_device *spi)
473 {
474 struct spi_controller *ctrl = spi->master;
475 struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
476 unsigned long src_rate;
477 u32 scbr;
478
479 if (ctrl->busy)
480 return -EBUSY;
481
482 if (!spi->max_speed_hz)
483 return -EINVAL;
484
485 src_rate = clk_get_rate(aq->pclk);
486 if (!src_rate)
487 return -EINVAL;
488
489 /* Compute the QSPI baudrate */
490 scbr = DIV_ROUND_UP(src_rate, spi->max_speed_hz);
491 if (scbr > 0)
492 scbr--;
493
494 aq->scr = QSPI_SCR_SCBR(scbr);
495 atmel_qspi_write(aq->scr, aq, QSPI_SCR);
496
497 return 0;
498 }
499
atmel_qspi_init(struct atmel_qspi * aq)500 static void atmel_qspi_init(struct atmel_qspi *aq)
501 {
502 /* Reset the QSPI controller */
503 atmel_qspi_write(QSPI_CR_SWRST, aq, QSPI_CR);
504
505 /* Set the QSPI controller by default in Serial Memory Mode */
506 atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR);
507 aq->mr = QSPI_MR_SMM;
508
509 /* Enable the QSPI controller */
510 atmel_qspi_write(QSPI_CR_QSPIEN, aq, QSPI_CR);
511 }
512
atmel_qspi_interrupt(int irq,void * dev_id)513 static irqreturn_t atmel_qspi_interrupt(int irq, void *dev_id)
514 {
515 struct atmel_qspi *aq = dev_id;
516 u32 status, mask, pending;
517
518 status = atmel_qspi_read(aq, QSPI_SR);
519 mask = atmel_qspi_read(aq, QSPI_IMR);
520 pending = status & mask;
521
522 if (!pending)
523 return IRQ_NONE;
524
525 aq->pending |= pending;
526 if ((aq->pending & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED)
527 complete(&aq->cmd_completion);
528
529 return IRQ_HANDLED;
530 }
531
atmel_qspi_probe(struct platform_device * pdev)532 static int atmel_qspi_probe(struct platform_device *pdev)
533 {
534 struct spi_controller *ctrl;
535 struct atmel_qspi *aq;
536 struct resource *res;
537 int irq, err = 0;
538
539 ctrl = devm_spi_alloc_master(&pdev->dev, sizeof(*aq));
540 if (!ctrl)
541 return -ENOMEM;
542
543 ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD;
544 ctrl->setup = atmel_qspi_setup;
545 ctrl->bus_num = -1;
546 ctrl->mem_ops = &atmel_qspi_mem_ops;
547 ctrl->num_chipselect = 1;
548 ctrl->dev.of_node = pdev->dev.of_node;
549 platform_set_drvdata(pdev, ctrl);
550
551 aq = spi_controller_get_devdata(ctrl);
552
553 init_completion(&aq->cmd_completion);
554 aq->pdev = pdev;
555
556 /* Map the registers */
557 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
558 aq->regs = devm_ioremap_resource(&pdev->dev, res);
559 if (IS_ERR(aq->regs)) {
560 dev_err(&pdev->dev, "missing registers\n");
561 return PTR_ERR(aq->regs);
562 }
563
564 /* Map the AHB memory */
565 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mmap");
566 aq->mem = devm_ioremap_resource(&pdev->dev, res);
567 if (IS_ERR(aq->mem)) {
568 dev_err(&pdev->dev, "missing AHB memory\n");
569 return PTR_ERR(aq->mem);
570 }
571
572 aq->mmap_size = resource_size(res);
573
574 /* Get the peripheral clock */
575 aq->pclk = devm_clk_get(&pdev->dev, "pclk");
576 if (IS_ERR(aq->pclk))
577 aq->pclk = devm_clk_get(&pdev->dev, NULL);
578
579 if (IS_ERR(aq->pclk)) {
580 dev_err(&pdev->dev, "missing peripheral clock\n");
581 return PTR_ERR(aq->pclk);
582 }
583
584 /* Enable the peripheral clock */
585 err = clk_prepare_enable(aq->pclk);
586 if (err) {
587 dev_err(&pdev->dev, "failed to enable the peripheral clock\n");
588 return err;
589 }
590
591 aq->caps = of_device_get_match_data(&pdev->dev);
592 if (!aq->caps) {
593 dev_err(&pdev->dev, "Could not retrieve QSPI caps\n");
594 err = -EINVAL;
595 goto disable_pclk;
596 }
597
598 if (aq->caps->has_qspick) {
599 /* Get the QSPI system clock */
600 aq->qspick = devm_clk_get(&pdev->dev, "qspick");
601 if (IS_ERR(aq->qspick)) {
602 dev_err(&pdev->dev, "missing system clock\n");
603 err = PTR_ERR(aq->qspick);
604 goto disable_pclk;
605 }
606
607 /* Enable the QSPI system clock */
608 err = clk_prepare_enable(aq->qspick);
609 if (err) {
610 dev_err(&pdev->dev,
611 "failed to enable the QSPI system clock\n");
612 goto disable_pclk;
613 }
614 }
615
616 /* Request the IRQ */
617 irq = platform_get_irq(pdev, 0);
618 if (irq < 0) {
619 err = irq;
620 goto disable_qspick;
621 }
622 err = devm_request_irq(&pdev->dev, irq, atmel_qspi_interrupt,
623 0, dev_name(&pdev->dev), aq);
624 if (err)
625 goto disable_qspick;
626
627 atmel_qspi_init(aq);
628
629 err = spi_register_controller(ctrl);
630 if (err)
631 goto disable_qspick;
632
633 return 0;
634
635 disable_qspick:
636 clk_disable_unprepare(aq->qspick);
637 disable_pclk:
638 clk_disable_unprepare(aq->pclk);
639
640 return err;
641 }
642
atmel_qspi_remove(struct platform_device * pdev)643 static int atmel_qspi_remove(struct platform_device *pdev)
644 {
645 struct spi_controller *ctrl = platform_get_drvdata(pdev);
646 struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
647
648 spi_unregister_controller(ctrl);
649 atmel_qspi_write(QSPI_CR_QSPIDIS, aq, QSPI_CR);
650 clk_disable_unprepare(aq->qspick);
651 clk_disable_unprepare(aq->pclk);
652 return 0;
653 }
654
atmel_qspi_suspend(struct device * dev)655 static int __maybe_unused atmel_qspi_suspend(struct device *dev)
656 {
657 struct spi_controller *ctrl = dev_get_drvdata(dev);
658 struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
659
660 atmel_qspi_write(QSPI_CR_QSPIDIS, aq, QSPI_CR);
661 clk_disable_unprepare(aq->qspick);
662 clk_disable_unprepare(aq->pclk);
663
664 return 0;
665 }
666
atmel_qspi_resume(struct device * dev)667 static int __maybe_unused atmel_qspi_resume(struct device *dev)
668 {
669 struct spi_controller *ctrl = dev_get_drvdata(dev);
670 struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
671
672 clk_prepare_enable(aq->pclk);
673 clk_prepare_enable(aq->qspick);
674
675 atmel_qspi_init(aq);
676
677 atmel_qspi_write(aq->scr, aq, QSPI_SCR);
678
679 return 0;
680 }
681
682 static SIMPLE_DEV_PM_OPS(atmel_qspi_pm_ops, atmel_qspi_suspend,
683 atmel_qspi_resume);
684
685 static const struct atmel_qspi_caps atmel_sama5d2_qspi_caps = {};
686
687 static const struct atmel_qspi_caps atmel_sam9x60_qspi_caps = {
688 .has_qspick = true,
689 .has_ricr = true,
690 };
691
692 static const struct of_device_id atmel_qspi_dt_ids[] = {
693 {
694 .compatible = "atmel,sama5d2-qspi",
695 .data = &atmel_sama5d2_qspi_caps,
696 },
697 {
698 .compatible = "microchip,sam9x60-qspi",
699 .data = &atmel_sam9x60_qspi_caps,
700 },
701 { /* sentinel */ }
702 };
703
704 MODULE_DEVICE_TABLE(of, atmel_qspi_dt_ids);
705
706 static struct platform_driver atmel_qspi_driver = {
707 .driver = {
708 .name = "atmel_qspi",
709 .of_match_table = atmel_qspi_dt_ids,
710 .pm = &atmel_qspi_pm_ops,
711 },
712 .probe = atmel_qspi_probe,
713 .remove = atmel_qspi_remove,
714 };
715 module_platform_driver(atmel_qspi_driver);
716
717 MODULE_AUTHOR("Cyrille Pitchen <cyrille.pitchen@atmel.com>");
718 MODULE_AUTHOR("Piotr Bugalski <bugalski.piotr@gmail.com");
719 MODULE_DESCRIPTION("Atmel QSPI Controller driver");
720 MODULE_LICENSE("GPL v2");
721