1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Driver for Broadcom BCM2835 SPI Controllers
4 *
5 * Copyright (C) 2012 Chris Boot
6 * Copyright (C) 2013 Stephen Warren
7 * Copyright (C) 2015 Martin Sperl
8 *
9 * This driver is inspired by:
10 * spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
11 * spi-atmel.c, Copyright (C) 2006 Atmel Corporation
12 */
13
14 #include <linux/clk.h>
15 #include <linux/completion.h>
16 #include <linux/debugfs.h>
17 #include <linux/delay.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/dmaengine.h>
20 #include <linux/err.h>
21 #include <linux/interrupt.h>
22 #include <linux/io.h>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/of.h>
26 #include <linux/of_address.h>
27 #include <linux/of_device.h>
28 #include <linux/gpio/consumer.h>
29 #include <linux/gpio/machine.h> /* FIXME: using chip internals */
30 #include <linux/gpio/driver.h> /* FIXME: using chip internals */
31 #include <linux/of_irq.h>
32 #include <linux/spi/spi.h>
33
34 /* SPI register offsets */
35 #define BCM2835_SPI_CS 0x00
36 #define BCM2835_SPI_FIFO 0x04
37 #define BCM2835_SPI_CLK 0x08
38 #define BCM2835_SPI_DLEN 0x0c
39 #define BCM2835_SPI_LTOH 0x10
40 #define BCM2835_SPI_DC 0x14
41
42 /* Bitfields in CS */
43 #define BCM2835_SPI_CS_LEN_LONG 0x02000000
44 #define BCM2835_SPI_CS_DMA_LEN 0x01000000
45 #define BCM2835_SPI_CS_CSPOL2 0x00800000
46 #define BCM2835_SPI_CS_CSPOL1 0x00400000
47 #define BCM2835_SPI_CS_CSPOL0 0x00200000
48 #define BCM2835_SPI_CS_RXF 0x00100000
49 #define BCM2835_SPI_CS_RXR 0x00080000
50 #define BCM2835_SPI_CS_TXD 0x00040000
51 #define BCM2835_SPI_CS_RXD 0x00020000
52 #define BCM2835_SPI_CS_DONE 0x00010000
53 #define BCM2835_SPI_CS_LEN 0x00002000
54 #define BCM2835_SPI_CS_REN 0x00001000
55 #define BCM2835_SPI_CS_ADCS 0x00000800
56 #define BCM2835_SPI_CS_INTR 0x00000400
57 #define BCM2835_SPI_CS_INTD 0x00000200
58 #define BCM2835_SPI_CS_DMAEN 0x00000100
59 #define BCM2835_SPI_CS_TA 0x00000080
60 #define BCM2835_SPI_CS_CSPOL 0x00000040
61 #define BCM2835_SPI_CS_CLEAR_RX 0x00000020
62 #define BCM2835_SPI_CS_CLEAR_TX 0x00000010
63 #define BCM2835_SPI_CS_CPOL 0x00000008
64 #define BCM2835_SPI_CS_CPHA 0x00000004
65 #define BCM2835_SPI_CS_CS_10 0x00000002
66 #define BCM2835_SPI_CS_CS_01 0x00000001
67
68 #define BCM2835_SPI_FIFO_SIZE 64
69 #define BCM2835_SPI_FIFO_SIZE_3_4 48
70 #define BCM2835_SPI_DMA_MIN_LENGTH 96
71 #define BCM2835_SPI_NUM_CS 4 /* raise as necessary */
72 #define BCM2835_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
73 | SPI_NO_CS | SPI_3WIRE)
74
75 #define DRV_NAME "spi-bcm2835"
76
77 /* define polling limits */
78 static unsigned int polling_limit_us = 30;
79 module_param(polling_limit_us, uint, 0664);
80 MODULE_PARM_DESC(polling_limit_us,
81 "time in us to run a transfer in polling mode\n");
82
83 /**
84 * struct bcm2835_spi - BCM2835 SPI controller
85 * @regs: base address of register map
86 * @clk: core clock, divided to calculate serial clock
87 * @irq: interrupt, signals TX FIFO empty or RX FIFO ¾ full
88 * @tfr: SPI transfer currently processed
89 * @ctlr: SPI controller reverse lookup
90 * @tx_buf: pointer whence next transmitted byte is read
91 * @rx_buf: pointer where next received byte is written
92 * @tx_len: remaining bytes to transmit
93 * @rx_len: remaining bytes to receive
94 * @tx_prologue: bytes transmitted without DMA if first TX sglist entry's
95 * length is not a multiple of 4 (to overcome hardware limitation)
96 * @rx_prologue: bytes received without DMA if first RX sglist entry's
97 * length is not a multiple of 4 (to overcome hardware limitation)
98 * @tx_spillover: whether @tx_prologue spills over to second TX sglist entry
99 * @prepare_cs: precalculated CS register value for ->prepare_message()
100 * (uses slave-specific clock polarity and phase settings)
101 * @debugfs_dir: the debugfs directory - neede to remove debugfs when
102 * unloading the module
103 * @count_transfer_polling: count of how often polling mode is used
104 * @count_transfer_irq: count of how often interrupt mode is used
105 * @count_transfer_irq_after_polling: count of how often we fall back to
106 * interrupt mode after starting in polling mode.
107 * These are counted as well in @count_transfer_polling and
108 * @count_transfer_irq
109 * @count_transfer_dma: count how often dma mode is used
110 * @chip_select: SPI slave currently selected
111 * (used by bcm2835_spi_dma_tx_done() to write @clear_rx_cs)
112 * @tx_dma_active: whether a TX DMA descriptor is in progress
113 * @rx_dma_active: whether a RX DMA descriptor is in progress
114 * (used by bcm2835_spi_dma_tx_done() to handle a race)
115 * @fill_tx_desc: preallocated TX DMA descriptor used for RX-only transfers
116 * (cyclically copies from zero page to TX FIFO)
117 * @fill_tx_addr: bus address of zero page
118 * @clear_rx_desc: preallocated RX DMA descriptor used for TX-only transfers
119 * (cyclically clears RX FIFO by writing @clear_rx_cs to CS register)
120 * @clear_rx_addr: bus address of @clear_rx_cs
121 * @clear_rx_cs: precalculated CS register value to clear RX FIFO
122 * (uses slave-specific clock polarity and phase settings)
123 */
124 struct bcm2835_spi {
125 void __iomem *regs;
126 struct clk *clk;
127 int irq;
128 struct spi_transfer *tfr;
129 struct spi_controller *ctlr;
130 const u8 *tx_buf;
131 u8 *rx_buf;
132 int tx_len;
133 int rx_len;
134 int tx_prologue;
135 int rx_prologue;
136 unsigned int tx_spillover;
137 u32 prepare_cs[BCM2835_SPI_NUM_CS];
138
139 struct dentry *debugfs_dir;
140 u64 count_transfer_polling;
141 u64 count_transfer_irq;
142 u64 count_transfer_irq_after_polling;
143 u64 count_transfer_dma;
144
145 u8 chip_select;
146 unsigned int tx_dma_active;
147 unsigned int rx_dma_active;
148 struct dma_async_tx_descriptor *fill_tx_desc;
149 dma_addr_t fill_tx_addr;
150 struct dma_async_tx_descriptor *clear_rx_desc[BCM2835_SPI_NUM_CS];
151 dma_addr_t clear_rx_addr;
152 u32 clear_rx_cs[BCM2835_SPI_NUM_CS] ____cacheline_aligned;
153 };
154
155 #if defined(CONFIG_DEBUG_FS)
bcm2835_debugfs_create(struct bcm2835_spi * bs,const char * dname)156 static void bcm2835_debugfs_create(struct bcm2835_spi *bs,
157 const char *dname)
158 {
159 char name[64];
160 struct dentry *dir;
161
162 /* get full name */
163 snprintf(name, sizeof(name), "spi-bcm2835-%s", dname);
164
165 /* the base directory */
166 dir = debugfs_create_dir(name, NULL);
167 bs->debugfs_dir = dir;
168
169 /* the counters */
170 debugfs_create_u64("count_transfer_polling", 0444, dir,
171 &bs->count_transfer_polling);
172 debugfs_create_u64("count_transfer_irq", 0444, dir,
173 &bs->count_transfer_irq);
174 debugfs_create_u64("count_transfer_irq_after_polling", 0444, dir,
175 &bs->count_transfer_irq_after_polling);
176 debugfs_create_u64("count_transfer_dma", 0444, dir,
177 &bs->count_transfer_dma);
178 }
179
bcm2835_debugfs_remove(struct bcm2835_spi * bs)180 static void bcm2835_debugfs_remove(struct bcm2835_spi *bs)
181 {
182 debugfs_remove_recursive(bs->debugfs_dir);
183 bs->debugfs_dir = NULL;
184 }
185 #else
bcm2835_debugfs_create(struct bcm2835_spi * bs,const char * dname)186 static void bcm2835_debugfs_create(struct bcm2835_spi *bs,
187 const char *dname)
188 {
189 }
190
bcm2835_debugfs_remove(struct bcm2835_spi * bs)191 static void bcm2835_debugfs_remove(struct bcm2835_spi *bs)
192 {
193 }
194 #endif /* CONFIG_DEBUG_FS */
195
bcm2835_rd(struct bcm2835_spi * bs,unsigned int reg)196 static inline u32 bcm2835_rd(struct bcm2835_spi *bs, unsigned int reg)
197 {
198 return readl(bs->regs + reg);
199 }
200
bcm2835_wr(struct bcm2835_spi * bs,unsigned int reg,u32 val)201 static inline void bcm2835_wr(struct bcm2835_spi *bs, unsigned int reg, u32 val)
202 {
203 writel(val, bs->regs + reg);
204 }
205
bcm2835_rd_fifo(struct bcm2835_spi * bs)206 static inline void bcm2835_rd_fifo(struct bcm2835_spi *bs)
207 {
208 u8 byte;
209
210 while ((bs->rx_len) &&
211 (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_RXD)) {
212 byte = bcm2835_rd(bs, BCM2835_SPI_FIFO);
213 if (bs->rx_buf)
214 *bs->rx_buf++ = byte;
215 bs->rx_len--;
216 }
217 }
218
bcm2835_wr_fifo(struct bcm2835_spi * bs)219 static inline void bcm2835_wr_fifo(struct bcm2835_spi *bs)
220 {
221 u8 byte;
222
223 while ((bs->tx_len) &&
224 (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_TXD)) {
225 byte = bs->tx_buf ? *bs->tx_buf++ : 0;
226 bcm2835_wr(bs, BCM2835_SPI_FIFO, byte);
227 bs->tx_len--;
228 }
229 }
230
231 /**
232 * bcm2835_rd_fifo_count() - blindly read exactly @count bytes from RX FIFO
233 * @bs: BCM2835 SPI controller
234 * @count: bytes to read from RX FIFO
235 *
236 * The caller must ensure that @bs->rx_len is greater than or equal to @count,
237 * that the RX FIFO contains at least @count bytes and that the DMA Enable flag
238 * in the CS register is set (such that a read from the FIFO register receives
239 * 32-bit instead of just 8-bit). Moreover @bs->rx_buf must not be %NULL.
240 */
bcm2835_rd_fifo_count(struct bcm2835_spi * bs,int count)241 static inline void bcm2835_rd_fifo_count(struct bcm2835_spi *bs, int count)
242 {
243 u32 val;
244 int len;
245
246 bs->rx_len -= count;
247
248 do {
249 val = bcm2835_rd(bs, BCM2835_SPI_FIFO);
250 len = min(count, 4);
251 memcpy(bs->rx_buf, &val, len);
252 bs->rx_buf += len;
253 count -= 4;
254 } while (count > 0);
255 }
256
257 /**
258 * bcm2835_wr_fifo_count() - blindly write exactly @count bytes to TX FIFO
259 * @bs: BCM2835 SPI controller
260 * @count: bytes to write to TX FIFO
261 *
262 * The caller must ensure that @bs->tx_len is greater than or equal to @count,
263 * that the TX FIFO can accommodate @count bytes and that the DMA Enable flag
264 * in the CS register is set (such that a write to the FIFO register transmits
265 * 32-bit instead of just 8-bit).
266 */
bcm2835_wr_fifo_count(struct bcm2835_spi * bs,int count)267 static inline void bcm2835_wr_fifo_count(struct bcm2835_spi *bs, int count)
268 {
269 u32 val;
270 int len;
271
272 bs->tx_len -= count;
273
274 do {
275 if (bs->tx_buf) {
276 len = min(count, 4);
277 memcpy(&val, bs->tx_buf, len);
278 bs->tx_buf += len;
279 } else {
280 val = 0;
281 }
282 bcm2835_wr(bs, BCM2835_SPI_FIFO, val);
283 count -= 4;
284 } while (count > 0);
285 }
286
287 /**
288 * bcm2835_wait_tx_fifo_empty() - busy-wait for TX FIFO to empty
289 * @bs: BCM2835 SPI controller
290 *
291 * The caller must ensure that the RX FIFO can accommodate as many bytes
292 * as have been written to the TX FIFO: Transmission is halted once the
293 * RX FIFO is full, causing this function to spin forever.
294 */
bcm2835_wait_tx_fifo_empty(struct bcm2835_spi * bs)295 static inline void bcm2835_wait_tx_fifo_empty(struct bcm2835_spi *bs)
296 {
297 while (!(bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_DONE))
298 cpu_relax();
299 }
300
301 /**
302 * bcm2835_rd_fifo_blind() - blindly read up to @count bytes from RX FIFO
303 * @bs: BCM2835 SPI controller
304 * @count: bytes available for reading in RX FIFO
305 */
bcm2835_rd_fifo_blind(struct bcm2835_spi * bs,int count)306 static inline void bcm2835_rd_fifo_blind(struct bcm2835_spi *bs, int count)
307 {
308 u8 val;
309
310 count = min(count, bs->rx_len);
311 bs->rx_len -= count;
312
313 do {
314 val = bcm2835_rd(bs, BCM2835_SPI_FIFO);
315 if (bs->rx_buf)
316 *bs->rx_buf++ = val;
317 } while (--count);
318 }
319
320 /**
321 * bcm2835_wr_fifo_blind() - blindly write up to @count bytes to TX FIFO
322 * @bs: BCM2835 SPI controller
323 * @count: bytes available for writing in TX FIFO
324 */
bcm2835_wr_fifo_blind(struct bcm2835_spi * bs,int count)325 static inline void bcm2835_wr_fifo_blind(struct bcm2835_spi *bs, int count)
326 {
327 u8 val;
328
329 count = min(count, bs->tx_len);
330 bs->tx_len -= count;
331
332 do {
333 val = bs->tx_buf ? *bs->tx_buf++ : 0;
334 bcm2835_wr(bs, BCM2835_SPI_FIFO, val);
335 } while (--count);
336 }
337
bcm2835_spi_reset_hw(struct bcm2835_spi * bs)338 static void bcm2835_spi_reset_hw(struct bcm2835_spi *bs)
339 {
340 u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
341
342 /* Disable SPI interrupts and transfer */
343 cs &= ~(BCM2835_SPI_CS_INTR |
344 BCM2835_SPI_CS_INTD |
345 BCM2835_SPI_CS_DMAEN |
346 BCM2835_SPI_CS_TA);
347 /*
348 * Transmission sometimes breaks unless the DONE bit is written at the
349 * end of every transfer. The spec says it's a RO bit. Either the
350 * spec is wrong and the bit is actually of type RW1C, or it's a
351 * hardware erratum.
352 */
353 cs |= BCM2835_SPI_CS_DONE;
354 /* and reset RX/TX FIFOS */
355 cs |= BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX;
356
357 /* and reset the SPI_HW */
358 bcm2835_wr(bs, BCM2835_SPI_CS, cs);
359 /* as well as DLEN */
360 bcm2835_wr(bs, BCM2835_SPI_DLEN, 0);
361 }
362
bcm2835_spi_interrupt(int irq,void * dev_id)363 static irqreturn_t bcm2835_spi_interrupt(int irq, void *dev_id)
364 {
365 struct bcm2835_spi *bs = dev_id;
366 u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
367
368 /*
369 * An interrupt is signaled either if DONE is set (TX FIFO empty)
370 * or if RXR is set (RX FIFO >= ¾ full).
371 */
372 if (cs & BCM2835_SPI_CS_RXF)
373 bcm2835_rd_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE);
374 else if (cs & BCM2835_SPI_CS_RXR)
375 bcm2835_rd_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE_3_4);
376
377 if (bs->tx_len && cs & BCM2835_SPI_CS_DONE)
378 bcm2835_wr_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE);
379
380 /* Read as many bytes as possible from FIFO */
381 bcm2835_rd_fifo(bs);
382 /* Write as many bytes as possible to FIFO */
383 bcm2835_wr_fifo(bs);
384
385 if (!bs->rx_len) {
386 /* Transfer complete - reset SPI HW */
387 bcm2835_spi_reset_hw(bs);
388 /* wake up the framework */
389 spi_finalize_current_transfer(bs->ctlr);
390 }
391
392 return IRQ_HANDLED;
393 }
394
bcm2835_spi_transfer_one_irq(struct spi_controller * ctlr,struct spi_device * spi,struct spi_transfer * tfr,u32 cs,bool fifo_empty)395 static int bcm2835_spi_transfer_one_irq(struct spi_controller *ctlr,
396 struct spi_device *spi,
397 struct spi_transfer *tfr,
398 u32 cs, bool fifo_empty)
399 {
400 struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
401
402 /* update usage statistics */
403 bs->count_transfer_irq++;
404
405 /*
406 * Enable HW block, but with interrupts still disabled.
407 * Otherwise the empty TX FIFO would immediately trigger an interrupt.
408 */
409 bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA);
410
411 /* fill TX FIFO as much as possible */
412 if (fifo_empty)
413 bcm2835_wr_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE);
414 bcm2835_wr_fifo(bs);
415
416 /* enable interrupts */
417 cs |= BCM2835_SPI_CS_INTR | BCM2835_SPI_CS_INTD | BCM2835_SPI_CS_TA;
418 bcm2835_wr(bs, BCM2835_SPI_CS, cs);
419
420 /* signal that we need to wait for completion */
421 return 1;
422 }
423
424 /**
425 * bcm2835_spi_transfer_prologue() - transfer first few bytes without DMA
426 * @ctlr: SPI master controller
427 * @tfr: SPI transfer
428 * @bs: BCM2835 SPI controller
429 * @cs: CS register
430 *
431 * A limitation in DMA mode is that the FIFO must be accessed in 4 byte chunks.
432 * Only the final write access is permitted to transmit less than 4 bytes, the
433 * SPI controller deduces its intended size from the DLEN register.
434 *
435 * If a TX or RX sglist contains multiple entries, one per page, and the first
436 * entry starts in the middle of a page, that first entry's length may not be
437 * a multiple of 4. Subsequent entries are fine because they span an entire
438 * page, hence do have a length that's a multiple of 4.
439 *
440 * This cannot happen with kmalloc'ed buffers (which is what most clients use)
441 * because they are contiguous in physical memory and therefore not split on
442 * page boundaries by spi_map_buf(). But it *can* happen with vmalloc'ed
443 * buffers.
444 *
445 * The DMA engine is incapable of combining sglist entries into a continuous
446 * stream of 4 byte chunks, it treats every entry separately: A TX entry is
447 * rounded up a to a multiple of 4 bytes by transmitting surplus bytes, an RX
448 * entry is rounded up by throwing away received bytes.
449 *
450 * Overcome this limitation by transferring the first few bytes without DMA:
451 * E.g. if the first TX sglist entry's length is 23 and the first RX's is 42,
452 * write 3 bytes to the TX FIFO but read only 2 bytes from the RX FIFO.
453 * The residue of 1 byte in the RX FIFO is picked up by DMA. Together with
454 * the rest of the first RX sglist entry it makes up a multiple of 4 bytes.
455 *
456 * Should the RX prologue be larger, say, 3 vis-à-vis a TX prologue of 1,
457 * write 1 + 4 = 5 bytes to the TX FIFO and read 3 bytes from the RX FIFO.
458 * Caution, the additional 4 bytes spill over to the second TX sglist entry
459 * if the length of the first is *exactly* 1.
460 *
461 * At most 6 bytes are written and at most 3 bytes read. Do we know the
462 * transfer has this many bytes? Yes, see BCM2835_SPI_DMA_MIN_LENGTH.
463 *
464 * The FIFO is normally accessed with 8-bit width by the CPU and 32-bit width
465 * by the DMA engine. Toggling the DMA Enable flag in the CS register switches
466 * the width but also garbles the FIFO's contents. The prologue must therefore
467 * be transmitted in 32-bit width to ensure that the following DMA transfer can
468 * pick up the residue in the RX FIFO in ungarbled form.
469 */
bcm2835_spi_transfer_prologue(struct spi_controller * ctlr,struct spi_transfer * tfr,struct bcm2835_spi * bs,u32 cs)470 static void bcm2835_spi_transfer_prologue(struct spi_controller *ctlr,
471 struct spi_transfer *tfr,
472 struct bcm2835_spi *bs,
473 u32 cs)
474 {
475 int tx_remaining;
476
477 bs->tfr = tfr;
478 bs->tx_prologue = 0;
479 bs->rx_prologue = 0;
480 bs->tx_spillover = false;
481
482 if (bs->tx_buf && !sg_is_last(&tfr->tx_sg.sgl[0]))
483 bs->tx_prologue = sg_dma_len(&tfr->tx_sg.sgl[0]) & 3;
484
485 if (bs->rx_buf && !sg_is_last(&tfr->rx_sg.sgl[0])) {
486 bs->rx_prologue = sg_dma_len(&tfr->rx_sg.sgl[0]) & 3;
487
488 if (bs->rx_prologue > bs->tx_prologue) {
489 if (!bs->tx_buf || sg_is_last(&tfr->tx_sg.sgl[0])) {
490 bs->tx_prologue = bs->rx_prologue;
491 } else {
492 bs->tx_prologue += 4;
493 bs->tx_spillover =
494 !(sg_dma_len(&tfr->tx_sg.sgl[0]) & ~3);
495 }
496 }
497 }
498
499 /* rx_prologue > 0 implies tx_prologue > 0, so check only the latter */
500 if (!bs->tx_prologue)
501 return;
502
503 /* Write and read RX prologue. Adjust first entry in RX sglist. */
504 if (bs->rx_prologue) {
505 bcm2835_wr(bs, BCM2835_SPI_DLEN, bs->rx_prologue);
506 bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA
507 | BCM2835_SPI_CS_DMAEN);
508 bcm2835_wr_fifo_count(bs, bs->rx_prologue);
509 bcm2835_wait_tx_fifo_empty(bs);
510 bcm2835_rd_fifo_count(bs, bs->rx_prologue);
511 bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_CLEAR_RX
512 | BCM2835_SPI_CS_CLEAR_TX
513 | BCM2835_SPI_CS_DONE);
514
515 dma_sync_single_for_device(ctlr->dma_rx->device->dev,
516 sg_dma_address(&tfr->rx_sg.sgl[0]),
517 bs->rx_prologue, DMA_FROM_DEVICE);
518
519 sg_dma_address(&tfr->rx_sg.sgl[0]) += bs->rx_prologue;
520 sg_dma_len(&tfr->rx_sg.sgl[0]) -= bs->rx_prologue;
521 }
522
523 if (!bs->tx_buf)
524 return;
525
526 /*
527 * Write remaining TX prologue. Adjust first entry in TX sglist.
528 * Also adjust second entry if prologue spills over to it.
529 */
530 tx_remaining = bs->tx_prologue - bs->rx_prologue;
531 if (tx_remaining) {
532 bcm2835_wr(bs, BCM2835_SPI_DLEN, tx_remaining);
533 bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA
534 | BCM2835_SPI_CS_DMAEN);
535 bcm2835_wr_fifo_count(bs, tx_remaining);
536 bcm2835_wait_tx_fifo_empty(bs);
537 bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_CLEAR_TX
538 | BCM2835_SPI_CS_DONE);
539 }
540
541 if (likely(!bs->tx_spillover)) {
542 sg_dma_address(&tfr->tx_sg.sgl[0]) += bs->tx_prologue;
543 sg_dma_len(&tfr->tx_sg.sgl[0]) -= bs->tx_prologue;
544 } else {
545 sg_dma_len(&tfr->tx_sg.sgl[0]) = 0;
546 sg_dma_address(&tfr->tx_sg.sgl[1]) += 4;
547 sg_dma_len(&tfr->tx_sg.sgl[1]) -= 4;
548 }
549 }
550
551 /**
552 * bcm2835_spi_undo_prologue() - reconstruct original sglist state
553 * @bs: BCM2835 SPI controller
554 *
555 * Undo changes which were made to an SPI transfer's sglist when transmitting
556 * the prologue. This is necessary to ensure the same memory ranges are
557 * unmapped that were originally mapped.
558 */
bcm2835_spi_undo_prologue(struct bcm2835_spi * bs)559 static void bcm2835_spi_undo_prologue(struct bcm2835_spi *bs)
560 {
561 struct spi_transfer *tfr = bs->tfr;
562
563 if (!bs->tx_prologue)
564 return;
565
566 if (bs->rx_prologue) {
567 sg_dma_address(&tfr->rx_sg.sgl[0]) -= bs->rx_prologue;
568 sg_dma_len(&tfr->rx_sg.sgl[0]) += bs->rx_prologue;
569 }
570
571 if (!bs->tx_buf)
572 goto out;
573
574 if (likely(!bs->tx_spillover)) {
575 sg_dma_address(&tfr->tx_sg.sgl[0]) -= bs->tx_prologue;
576 sg_dma_len(&tfr->tx_sg.sgl[0]) += bs->tx_prologue;
577 } else {
578 sg_dma_len(&tfr->tx_sg.sgl[0]) = bs->tx_prologue - 4;
579 sg_dma_address(&tfr->tx_sg.sgl[1]) -= 4;
580 sg_dma_len(&tfr->tx_sg.sgl[1]) += 4;
581 }
582 out:
583 bs->tx_prologue = 0;
584 }
585
586 /**
587 * bcm2835_spi_dma_rx_done() - callback for DMA RX channel
588 * @data: SPI master controller
589 *
590 * Used for bidirectional and RX-only transfers.
591 */
bcm2835_spi_dma_rx_done(void * data)592 static void bcm2835_spi_dma_rx_done(void *data)
593 {
594 struct spi_controller *ctlr = data;
595 struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
596
597 /* terminate tx-dma as we do not have an irq for it
598 * because when the rx dma will terminate and this callback
599 * is called the tx-dma must have finished - can't get to this
600 * situation otherwise...
601 */
602 dmaengine_terminate_async(ctlr->dma_tx);
603 bs->tx_dma_active = false;
604 bs->rx_dma_active = false;
605 bcm2835_spi_undo_prologue(bs);
606
607 /* reset fifo and HW */
608 bcm2835_spi_reset_hw(bs);
609
610 /* and mark as completed */;
611 spi_finalize_current_transfer(ctlr);
612 }
613
614 /**
615 * bcm2835_spi_dma_tx_done() - callback for DMA TX channel
616 * @data: SPI master controller
617 *
618 * Used for TX-only transfers.
619 */
bcm2835_spi_dma_tx_done(void * data)620 static void bcm2835_spi_dma_tx_done(void *data)
621 {
622 struct spi_controller *ctlr = data;
623 struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
624
625 /* busy-wait for TX FIFO to empty */
626 while (!(bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_DONE))
627 bcm2835_wr(bs, BCM2835_SPI_CS,
628 bs->clear_rx_cs[bs->chip_select]);
629
630 bs->tx_dma_active = false;
631 smp_wmb();
632
633 /*
634 * In case of a very short transfer, RX DMA may not have been
635 * issued yet. The onus is then on bcm2835_spi_transfer_one_dma()
636 * to terminate it immediately after issuing.
637 */
638 if (cmpxchg(&bs->rx_dma_active, true, false))
639 dmaengine_terminate_async(ctlr->dma_rx);
640
641 bcm2835_spi_undo_prologue(bs);
642 bcm2835_spi_reset_hw(bs);
643 spi_finalize_current_transfer(ctlr);
644 }
645
646 /**
647 * bcm2835_spi_prepare_sg() - prepare and submit DMA descriptor for sglist
648 * @ctlr: SPI master controller
649 * @spi: SPI slave
650 * @tfr: SPI transfer
651 * @bs: BCM2835 SPI controller
652 * @is_tx: whether to submit DMA descriptor for TX or RX sglist
653 *
654 * Prepare and submit a DMA descriptor for the TX or RX sglist of @tfr.
655 * Return 0 on success or a negative error number.
656 */
bcm2835_spi_prepare_sg(struct spi_controller * ctlr,struct spi_device * spi,struct spi_transfer * tfr,struct bcm2835_spi * bs,bool is_tx)657 static int bcm2835_spi_prepare_sg(struct spi_controller *ctlr,
658 struct spi_device *spi,
659 struct spi_transfer *tfr,
660 struct bcm2835_spi *bs,
661 bool is_tx)
662 {
663 struct dma_chan *chan;
664 struct scatterlist *sgl;
665 unsigned int nents;
666 enum dma_transfer_direction dir;
667 unsigned long flags;
668
669 struct dma_async_tx_descriptor *desc;
670 dma_cookie_t cookie;
671
672 if (is_tx) {
673 dir = DMA_MEM_TO_DEV;
674 chan = ctlr->dma_tx;
675 nents = tfr->tx_sg.nents;
676 sgl = tfr->tx_sg.sgl;
677 flags = tfr->rx_buf ? 0 : DMA_PREP_INTERRUPT;
678 } else {
679 dir = DMA_DEV_TO_MEM;
680 chan = ctlr->dma_rx;
681 nents = tfr->rx_sg.nents;
682 sgl = tfr->rx_sg.sgl;
683 flags = DMA_PREP_INTERRUPT;
684 }
685 /* prepare the channel */
686 desc = dmaengine_prep_slave_sg(chan, sgl, nents, dir, flags);
687 if (!desc)
688 return -EINVAL;
689
690 /*
691 * Completion is signaled by the RX channel for bidirectional and
692 * RX-only transfers; else by the TX channel for TX-only transfers.
693 */
694 if (!is_tx) {
695 desc->callback = bcm2835_spi_dma_rx_done;
696 desc->callback_param = ctlr;
697 } else if (!tfr->rx_buf) {
698 desc->callback = bcm2835_spi_dma_tx_done;
699 desc->callback_param = ctlr;
700 bs->chip_select = spi->chip_select;
701 }
702
703 /* submit it to DMA-engine */
704 cookie = dmaengine_submit(desc);
705
706 return dma_submit_error(cookie);
707 }
708
709 /**
710 * bcm2835_spi_transfer_one_dma() - perform SPI transfer using DMA engine
711 * @ctlr: SPI master controller
712 * @spi: SPI slave
713 * @tfr: SPI transfer
714 * @cs: CS register
715 *
716 * For *bidirectional* transfers (both tx_buf and rx_buf are non-%NULL), set up
717 * the TX and RX DMA channel to copy between memory and FIFO register.
718 *
719 * For *TX-only* transfers (rx_buf is %NULL), copying the RX FIFO's contents to
720 * memory is pointless. However not reading the RX FIFO isn't an option either
721 * because transmission is halted once it's full. As a workaround, cyclically
722 * clear the RX FIFO by setting the CLEAR_RX bit in the CS register.
723 *
724 * The CS register value is precalculated in bcm2835_spi_setup(). Normally
725 * this is called only once, on slave registration. A DMA descriptor to write
726 * this value is preallocated in bcm2835_dma_init(). All that's left to do
727 * when performing a TX-only transfer is to submit this descriptor to the RX
728 * DMA channel. Latency is thereby minimized. The descriptor does not
729 * generate any interrupts while running. It must be terminated once the
730 * TX DMA channel is done.
731 *
732 * Clearing the RX FIFO is paced by the DREQ signal. The signal is asserted
733 * when the RX FIFO becomes half full, i.e. 32 bytes. (Tuneable with the DC
734 * register.) Reading 32 bytes from the RX FIFO would normally require 8 bus
735 * accesses, whereas clearing it requires only 1 bus access. So an 8-fold
736 * reduction in bus traffic and thus energy consumption is achieved.
737 *
738 * For *RX-only* transfers (tx_buf is %NULL), fill the TX FIFO by cyclically
739 * copying from the zero page. The DMA descriptor to do this is preallocated
740 * in bcm2835_dma_init(). It must be terminated once the RX DMA channel is
741 * done and can then be reused.
742 *
743 * The BCM2835 DMA driver autodetects when a transaction copies from the zero
744 * page and utilizes the DMA controller's ability to synthesize zeroes instead
745 * of copying them from memory. This reduces traffic on the memory bus. The
746 * feature is not available on so-called "lite" channels, but normally TX DMA
747 * is backed by a full-featured channel.
748 *
749 * Zero-filling the TX FIFO is paced by the DREQ signal. Unfortunately the
750 * BCM2835 SPI controller continues to assert DREQ even after the DLEN register
751 * has been counted down to zero (hardware erratum). Thus, when the transfer
752 * has finished, the DMA engine zero-fills the TX FIFO until it is half full.
753 * (Tuneable with the DC register.) So up to 9 gratuitous bus accesses are
754 * performed at the end of an RX-only transfer.
755 */
bcm2835_spi_transfer_one_dma(struct spi_controller * ctlr,struct spi_device * spi,struct spi_transfer * tfr,u32 cs)756 static int bcm2835_spi_transfer_one_dma(struct spi_controller *ctlr,
757 struct spi_device *spi,
758 struct spi_transfer *tfr,
759 u32 cs)
760 {
761 struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
762 dma_cookie_t cookie;
763 int ret;
764
765 /* update usage statistics */
766 bs->count_transfer_dma++;
767
768 /*
769 * Transfer first few bytes without DMA if length of first TX or RX
770 * sglist entry is not a multiple of 4 bytes (hardware limitation).
771 */
772 bcm2835_spi_transfer_prologue(ctlr, tfr, bs, cs);
773
774 /* setup tx-DMA */
775 if (bs->tx_buf) {
776 ret = bcm2835_spi_prepare_sg(ctlr, spi, tfr, bs, true);
777 } else {
778 cookie = dmaengine_submit(bs->fill_tx_desc);
779 ret = dma_submit_error(cookie);
780 }
781 if (ret)
782 goto err_reset_hw;
783
784 /* set the DMA length */
785 bcm2835_wr(bs, BCM2835_SPI_DLEN, bs->tx_len);
786
787 /* start the HW */
788 bcm2835_wr(bs, BCM2835_SPI_CS,
789 cs | BCM2835_SPI_CS_TA | BCM2835_SPI_CS_DMAEN);
790
791 bs->tx_dma_active = true;
792 smp_wmb();
793
794 /* start TX early */
795 dma_async_issue_pending(ctlr->dma_tx);
796
797 /* setup rx-DMA late - to run transfers while
798 * mapping of the rx buffers still takes place
799 * this saves 10us or more.
800 */
801 if (bs->rx_buf) {
802 ret = bcm2835_spi_prepare_sg(ctlr, spi, tfr, bs, false);
803 } else {
804 cookie = dmaengine_submit(bs->clear_rx_desc[spi->chip_select]);
805 ret = dma_submit_error(cookie);
806 }
807 if (ret) {
808 /* need to reset on errors */
809 dmaengine_terminate_sync(ctlr->dma_tx);
810 bs->tx_dma_active = false;
811 goto err_reset_hw;
812 }
813
814 /* start rx dma late */
815 dma_async_issue_pending(ctlr->dma_rx);
816 bs->rx_dma_active = true;
817 smp_mb();
818
819 /*
820 * In case of a very short TX-only transfer, bcm2835_spi_dma_tx_done()
821 * may run before RX DMA is issued. Terminate RX DMA if so.
822 */
823 if (!bs->rx_buf && !bs->tx_dma_active &&
824 cmpxchg(&bs->rx_dma_active, true, false)) {
825 dmaengine_terminate_async(ctlr->dma_rx);
826 bcm2835_spi_reset_hw(bs);
827 }
828
829 /* wait for wakeup in framework */
830 return 1;
831
832 err_reset_hw:
833 bcm2835_spi_reset_hw(bs);
834 bcm2835_spi_undo_prologue(bs);
835 return ret;
836 }
837
bcm2835_spi_can_dma(struct spi_controller * ctlr,struct spi_device * spi,struct spi_transfer * tfr)838 static bool bcm2835_spi_can_dma(struct spi_controller *ctlr,
839 struct spi_device *spi,
840 struct spi_transfer *tfr)
841 {
842 /* we start DMA efforts only on bigger transfers */
843 if (tfr->len < BCM2835_SPI_DMA_MIN_LENGTH)
844 return false;
845
846 /* return OK */
847 return true;
848 }
849
bcm2835_dma_release(struct spi_controller * ctlr,struct bcm2835_spi * bs)850 static void bcm2835_dma_release(struct spi_controller *ctlr,
851 struct bcm2835_spi *bs)
852 {
853 int i;
854
855 if (ctlr->dma_tx) {
856 dmaengine_terminate_sync(ctlr->dma_tx);
857
858 if (bs->fill_tx_desc)
859 dmaengine_desc_free(bs->fill_tx_desc);
860
861 if (bs->fill_tx_addr)
862 dma_unmap_page_attrs(ctlr->dma_tx->device->dev,
863 bs->fill_tx_addr, sizeof(u32),
864 DMA_TO_DEVICE,
865 DMA_ATTR_SKIP_CPU_SYNC);
866
867 dma_release_channel(ctlr->dma_tx);
868 ctlr->dma_tx = NULL;
869 }
870
871 if (ctlr->dma_rx) {
872 dmaengine_terminate_sync(ctlr->dma_rx);
873
874 for (i = 0; i < BCM2835_SPI_NUM_CS; i++)
875 if (bs->clear_rx_desc[i])
876 dmaengine_desc_free(bs->clear_rx_desc[i]);
877
878 if (bs->clear_rx_addr)
879 dma_unmap_single(ctlr->dma_rx->device->dev,
880 bs->clear_rx_addr,
881 sizeof(bs->clear_rx_cs),
882 DMA_TO_DEVICE);
883
884 dma_release_channel(ctlr->dma_rx);
885 ctlr->dma_rx = NULL;
886 }
887 }
888
bcm2835_dma_init(struct spi_controller * ctlr,struct device * dev,struct bcm2835_spi * bs)889 static int bcm2835_dma_init(struct spi_controller *ctlr, struct device *dev,
890 struct bcm2835_spi *bs)
891 {
892 struct dma_slave_config slave_config;
893 const __be32 *addr;
894 dma_addr_t dma_reg_base;
895 int ret, i;
896
897 /* base address in dma-space */
898 addr = of_get_address(ctlr->dev.of_node, 0, NULL, NULL);
899 if (!addr) {
900 dev_err(dev, "could not get DMA-register address - not using dma mode\n");
901 /* Fall back to interrupt mode */
902 return 0;
903 }
904 dma_reg_base = be32_to_cpup(addr);
905
906 /* get tx/rx dma */
907 ctlr->dma_tx = dma_request_chan(dev, "tx");
908 if (IS_ERR(ctlr->dma_tx)) {
909 dev_err(dev, "no tx-dma configuration found - not using dma mode\n");
910 ret = PTR_ERR(ctlr->dma_tx);
911 ctlr->dma_tx = NULL;
912 goto err;
913 }
914 ctlr->dma_rx = dma_request_chan(dev, "rx");
915 if (IS_ERR(ctlr->dma_rx)) {
916 dev_err(dev, "no rx-dma configuration found - not using dma mode\n");
917 ret = PTR_ERR(ctlr->dma_rx);
918 ctlr->dma_rx = NULL;
919 goto err_release;
920 }
921
922 /*
923 * The TX DMA channel either copies a transfer's TX buffer to the FIFO
924 * or, in case of an RX-only transfer, cyclically copies from the zero
925 * page to the FIFO using a preallocated, reusable descriptor.
926 */
927 slave_config.dst_addr = (u32)(dma_reg_base + BCM2835_SPI_FIFO);
928 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
929
930 ret = dmaengine_slave_config(ctlr->dma_tx, &slave_config);
931 if (ret)
932 goto err_config;
933
934 bs->fill_tx_addr = dma_map_page_attrs(ctlr->dma_tx->device->dev,
935 ZERO_PAGE(0), 0, sizeof(u32),
936 DMA_TO_DEVICE,
937 DMA_ATTR_SKIP_CPU_SYNC);
938 if (dma_mapping_error(ctlr->dma_tx->device->dev, bs->fill_tx_addr)) {
939 dev_err(dev, "cannot map zero page - not using DMA mode\n");
940 bs->fill_tx_addr = 0;
941 ret = -ENOMEM;
942 goto err_release;
943 }
944
945 bs->fill_tx_desc = dmaengine_prep_dma_cyclic(ctlr->dma_tx,
946 bs->fill_tx_addr,
947 sizeof(u32), 0,
948 DMA_MEM_TO_DEV, 0);
949 if (!bs->fill_tx_desc) {
950 dev_err(dev, "cannot prepare fill_tx_desc - not using DMA mode\n");
951 ret = -ENOMEM;
952 goto err_release;
953 }
954
955 ret = dmaengine_desc_set_reuse(bs->fill_tx_desc);
956 if (ret) {
957 dev_err(dev, "cannot reuse fill_tx_desc - not using DMA mode\n");
958 goto err_release;
959 }
960
961 /*
962 * The RX DMA channel is used bidirectionally: It either reads the
963 * RX FIFO or, in case of a TX-only transfer, cyclically writes a
964 * precalculated value to the CS register to clear the RX FIFO.
965 */
966 slave_config.src_addr = (u32)(dma_reg_base + BCM2835_SPI_FIFO);
967 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
968 slave_config.dst_addr = (u32)(dma_reg_base + BCM2835_SPI_CS);
969 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
970
971 ret = dmaengine_slave_config(ctlr->dma_rx, &slave_config);
972 if (ret)
973 goto err_config;
974
975 bs->clear_rx_addr = dma_map_single(ctlr->dma_rx->device->dev,
976 bs->clear_rx_cs,
977 sizeof(bs->clear_rx_cs),
978 DMA_TO_DEVICE);
979 if (dma_mapping_error(ctlr->dma_rx->device->dev, bs->clear_rx_addr)) {
980 dev_err(dev, "cannot map clear_rx_cs - not using DMA mode\n");
981 bs->clear_rx_addr = 0;
982 ret = -ENOMEM;
983 goto err_release;
984 }
985
986 for (i = 0; i < BCM2835_SPI_NUM_CS; i++) {
987 bs->clear_rx_desc[i] = dmaengine_prep_dma_cyclic(ctlr->dma_rx,
988 bs->clear_rx_addr + i * sizeof(u32),
989 sizeof(u32), 0,
990 DMA_MEM_TO_DEV, 0);
991 if (!bs->clear_rx_desc[i]) {
992 dev_err(dev, "cannot prepare clear_rx_desc - not using DMA mode\n");
993 ret = -ENOMEM;
994 goto err_release;
995 }
996
997 ret = dmaengine_desc_set_reuse(bs->clear_rx_desc[i]);
998 if (ret) {
999 dev_err(dev, "cannot reuse clear_rx_desc - not using DMA mode\n");
1000 goto err_release;
1001 }
1002 }
1003
1004 /* all went well, so set can_dma */
1005 ctlr->can_dma = bcm2835_spi_can_dma;
1006
1007 return 0;
1008
1009 err_config:
1010 dev_err(dev, "issue configuring dma: %d - not using DMA mode\n",
1011 ret);
1012 err_release:
1013 bcm2835_dma_release(ctlr, bs);
1014 err:
1015 /*
1016 * Only report error for deferred probing, otherwise fall back to
1017 * interrupt mode
1018 */
1019 if (ret != -EPROBE_DEFER)
1020 ret = 0;
1021
1022 return ret;
1023 }
1024
bcm2835_spi_transfer_one_poll(struct spi_controller * ctlr,struct spi_device * spi,struct spi_transfer * tfr,u32 cs)1025 static int bcm2835_spi_transfer_one_poll(struct spi_controller *ctlr,
1026 struct spi_device *spi,
1027 struct spi_transfer *tfr,
1028 u32 cs)
1029 {
1030 struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
1031 unsigned long timeout;
1032
1033 /* update usage statistics */
1034 bs->count_transfer_polling++;
1035
1036 /* enable HW block without interrupts */
1037 bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA);
1038
1039 /* fill in the fifo before timeout calculations
1040 * if we are interrupted here, then the data is
1041 * getting transferred by the HW while we are interrupted
1042 */
1043 bcm2835_wr_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE);
1044
1045 /* set the timeout to at least 2 jiffies */
1046 timeout = jiffies + 2 + HZ * polling_limit_us / 1000000;
1047
1048 /* loop until finished the transfer */
1049 while (bs->rx_len) {
1050 /* fill in tx fifo with remaining data */
1051 bcm2835_wr_fifo(bs);
1052
1053 /* read from fifo as much as possible */
1054 bcm2835_rd_fifo(bs);
1055
1056 /* if there is still data pending to read
1057 * then check the timeout
1058 */
1059 if (bs->rx_len && time_after(jiffies, timeout)) {
1060 dev_dbg_ratelimited(&spi->dev,
1061 "timeout period reached: jiffies: %lu remaining tx/rx: %d/%d - falling back to interrupt mode\n",
1062 jiffies - timeout,
1063 bs->tx_len, bs->rx_len);
1064 /* fall back to interrupt mode */
1065
1066 /* update usage statistics */
1067 bs->count_transfer_irq_after_polling++;
1068
1069 return bcm2835_spi_transfer_one_irq(ctlr, spi,
1070 tfr, cs, false);
1071 }
1072 }
1073
1074 /* Transfer complete - reset SPI HW */
1075 bcm2835_spi_reset_hw(bs);
1076 /* and return without waiting for completion */
1077 return 0;
1078 }
1079
bcm2835_spi_transfer_one(struct spi_controller * ctlr,struct spi_device * spi,struct spi_transfer * tfr)1080 static int bcm2835_spi_transfer_one(struct spi_controller *ctlr,
1081 struct spi_device *spi,
1082 struct spi_transfer *tfr)
1083 {
1084 struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
1085 unsigned long spi_hz, clk_hz, cdiv;
1086 unsigned long hz_per_byte, byte_limit;
1087 u32 cs = bs->prepare_cs[spi->chip_select];
1088
1089 /* set clock */
1090 spi_hz = tfr->speed_hz;
1091 clk_hz = clk_get_rate(bs->clk);
1092
1093 if (spi_hz >= clk_hz / 2) {
1094 cdiv = 2; /* clk_hz/2 is the fastest we can go */
1095 } else if (spi_hz) {
1096 /* CDIV must be a multiple of two */
1097 cdiv = DIV_ROUND_UP(clk_hz, spi_hz);
1098 cdiv += (cdiv % 2);
1099
1100 if (cdiv >= 65536)
1101 cdiv = 0; /* 0 is the slowest we can go */
1102 } else {
1103 cdiv = 0; /* 0 is the slowest we can go */
1104 }
1105 tfr->effective_speed_hz = cdiv ? (clk_hz / cdiv) : (clk_hz / 65536);
1106 bcm2835_wr(bs, BCM2835_SPI_CLK, cdiv);
1107
1108 /* handle all the 3-wire mode */
1109 if (spi->mode & SPI_3WIRE && tfr->rx_buf)
1110 cs |= BCM2835_SPI_CS_REN;
1111
1112 /* set transmit buffers and length */
1113 bs->tx_buf = tfr->tx_buf;
1114 bs->rx_buf = tfr->rx_buf;
1115 bs->tx_len = tfr->len;
1116 bs->rx_len = tfr->len;
1117
1118 /* Calculate the estimated time in us the transfer runs. Note that
1119 * there is 1 idle clocks cycles after each byte getting transferred
1120 * so we have 9 cycles/byte. This is used to find the number of Hz
1121 * per byte per polling limit. E.g., we can transfer 1 byte in 30 us
1122 * per 300,000 Hz of bus clock.
1123 */
1124 hz_per_byte = polling_limit_us ? (9 * 1000000) / polling_limit_us : 0;
1125 byte_limit = hz_per_byte ? tfr->effective_speed_hz / hz_per_byte : 1;
1126
1127 /* run in polling mode for short transfers */
1128 if (tfr->len < byte_limit)
1129 return bcm2835_spi_transfer_one_poll(ctlr, spi, tfr, cs);
1130
1131 /* run in dma mode if conditions are right
1132 * Note that unlike poll or interrupt mode DMA mode does not have
1133 * this 1 idle clock cycle pattern but runs the spi clock without gaps
1134 */
1135 if (ctlr->can_dma && bcm2835_spi_can_dma(ctlr, spi, tfr))
1136 return bcm2835_spi_transfer_one_dma(ctlr, spi, tfr, cs);
1137
1138 /* run in interrupt-mode */
1139 return bcm2835_spi_transfer_one_irq(ctlr, spi, tfr, cs, true);
1140 }
1141
bcm2835_spi_prepare_message(struct spi_controller * ctlr,struct spi_message * msg)1142 static int bcm2835_spi_prepare_message(struct spi_controller *ctlr,
1143 struct spi_message *msg)
1144 {
1145 struct spi_device *spi = msg->spi;
1146 struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
1147 int ret;
1148
1149 if (ctlr->can_dma) {
1150 /*
1151 * DMA transfers are limited to 16 bit (0 to 65535 bytes) by
1152 * the SPI HW due to DLEN. Split up transfers (32-bit FIFO
1153 * aligned) if the limit is exceeded.
1154 */
1155 ret = spi_split_transfers_maxsize(ctlr, msg, 65532,
1156 GFP_KERNEL | GFP_DMA);
1157 if (ret)
1158 return ret;
1159 }
1160
1161 /*
1162 * Set up clock polarity before spi_transfer_one_message() asserts
1163 * chip select to avoid a gratuitous clock signal edge.
1164 */
1165 bcm2835_wr(bs, BCM2835_SPI_CS, bs->prepare_cs[spi->chip_select]);
1166
1167 return 0;
1168 }
1169
bcm2835_spi_handle_err(struct spi_controller * ctlr,struct spi_message * msg)1170 static void bcm2835_spi_handle_err(struct spi_controller *ctlr,
1171 struct spi_message *msg)
1172 {
1173 struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
1174
1175 /* if an error occurred and we have an active dma, then terminate */
1176 dmaengine_terminate_sync(ctlr->dma_tx);
1177 bs->tx_dma_active = false;
1178 dmaengine_terminate_sync(ctlr->dma_rx);
1179 bs->rx_dma_active = false;
1180 bcm2835_spi_undo_prologue(bs);
1181
1182 /* and reset */
1183 bcm2835_spi_reset_hw(bs);
1184 }
1185
chip_match_name(struct gpio_chip * chip,void * data)1186 static int chip_match_name(struct gpio_chip *chip, void *data)
1187 {
1188 return !strcmp(chip->label, data);
1189 }
1190
bcm2835_spi_setup(struct spi_device * spi)1191 static int bcm2835_spi_setup(struct spi_device *spi)
1192 {
1193 struct spi_controller *ctlr = spi->controller;
1194 struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
1195 struct gpio_chip *chip;
1196 u32 cs;
1197
1198 /*
1199 * Precalculate SPI slave's CS register value for ->prepare_message():
1200 * The driver always uses software-controlled GPIO chip select, hence
1201 * set the hardware-controlled native chip select to an invalid value
1202 * to prevent it from interfering.
1203 */
1204 cs = BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01;
1205 if (spi->mode & SPI_CPOL)
1206 cs |= BCM2835_SPI_CS_CPOL;
1207 if (spi->mode & SPI_CPHA)
1208 cs |= BCM2835_SPI_CS_CPHA;
1209 bs->prepare_cs[spi->chip_select] = cs;
1210
1211 /*
1212 * Precalculate SPI slave's CS register value to clear RX FIFO
1213 * in case of a TX-only DMA transfer.
1214 */
1215 if (ctlr->dma_rx) {
1216 bs->clear_rx_cs[spi->chip_select] = cs |
1217 BCM2835_SPI_CS_TA |
1218 BCM2835_SPI_CS_DMAEN |
1219 BCM2835_SPI_CS_CLEAR_RX;
1220 dma_sync_single_for_device(ctlr->dma_rx->device->dev,
1221 bs->clear_rx_addr,
1222 sizeof(bs->clear_rx_cs),
1223 DMA_TO_DEVICE);
1224 }
1225
1226 /*
1227 * sanity checking the native-chipselects
1228 */
1229 if (spi->mode & SPI_NO_CS)
1230 return 0;
1231 /*
1232 * The SPI core has successfully requested the CS GPIO line from the
1233 * device tree, so we are done.
1234 */
1235 if (spi->cs_gpiod)
1236 return 0;
1237 if (spi->chip_select > 1) {
1238 /* error in the case of native CS requested with CS > 1
1239 * officially there is a CS2, but it is not documented
1240 * which GPIO is connected with that...
1241 */
1242 dev_err(&spi->dev,
1243 "setup: only two native chip-selects are supported\n");
1244 return -EINVAL;
1245 }
1246
1247 /*
1248 * Translate native CS to GPIO
1249 *
1250 * FIXME: poking around in the gpiolib internals like this is
1251 * not very good practice. Find a way to locate the real problem
1252 * and fix it. Why is the GPIO descriptor in spi->cs_gpiod
1253 * sometimes not assigned correctly? Erroneous device trees?
1254 */
1255
1256 /* get the gpio chip for the base */
1257 chip = gpiochip_find("pinctrl-bcm2835", chip_match_name);
1258 if (!chip)
1259 return 0;
1260
1261 spi->cs_gpiod = gpiochip_request_own_desc(chip, 8 - spi->chip_select,
1262 DRV_NAME,
1263 GPIO_LOOKUP_FLAGS_DEFAULT,
1264 GPIOD_OUT_LOW);
1265 if (IS_ERR(spi->cs_gpiod))
1266 return PTR_ERR(spi->cs_gpiod);
1267
1268 /* and set up the "mode" and level */
1269 dev_info(&spi->dev, "setting up native-CS%i to use GPIO\n",
1270 spi->chip_select);
1271
1272 return 0;
1273 }
1274
bcm2835_spi_probe(struct platform_device * pdev)1275 static int bcm2835_spi_probe(struct platform_device *pdev)
1276 {
1277 struct spi_controller *ctlr;
1278 struct bcm2835_spi *bs;
1279 int err;
1280
1281 ctlr = devm_spi_alloc_master(&pdev->dev, ALIGN(sizeof(*bs),
1282 dma_get_cache_alignment()));
1283 if (!ctlr)
1284 return -ENOMEM;
1285
1286 platform_set_drvdata(pdev, ctlr);
1287
1288 ctlr->use_gpio_descriptors = true;
1289 ctlr->mode_bits = BCM2835_SPI_MODE_BITS;
1290 ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
1291 ctlr->num_chipselect = BCM2835_SPI_NUM_CS;
1292 ctlr->setup = bcm2835_spi_setup;
1293 ctlr->transfer_one = bcm2835_spi_transfer_one;
1294 ctlr->handle_err = bcm2835_spi_handle_err;
1295 ctlr->prepare_message = bcm2835_spi_prepare_message;
1296 ctlr->dev.of_node = pdev->dev.of_node;
1297
1298 bs = spi_controller_get_devdata(ctlr);
1299 bs->ctlr = ctlr;
1300
1301 bs->regs = devm_platform_ioremap_resource(pdev, 0);
1302 if (IS_ERR(bs->regs))
1303 return PTR_ERR(bs->regs);
1304
1305 bs->clk = devm_clk_get(&pdev->dev, NULL);
1306 if (IS_ERR(bs->clk))
1307 return dev_err_probe(&pdev->dev, PTR_ERR(bs->clk),
1308 "could not get clk\n");
1309
1310 ctlr->max_speed_hz = clk_get_rate(bs->clk) / 2;
1311
1312 bs->irq = platform_get_irq(pdev, 0);
1313 if (bs->irq <= 0)
1314 return bs->irq ? bs->irq : -ENODEV;
1315
1316 clk_prepare_enable(bs->clk);
1317
1318 err = bcm2835_dma_init(ctlr, &pdev->dev, bs);
1319 if (err)
1320 goto out_clk_disable;
1321
1322 /* initialise the hardware with the default polarities */
1323 bcm2835_wr(bs, BCM2835_SPI_CS,
1324 BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);
1325
1326 err = devm_request_irq(&pdev->dev, bs->irq, bcm2835_spi_interrupt, 0,
1327 dev_name(&pdev->dev), bs);
1328 if (err) {
1329 dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
1330 goto out_dma_release;
1331 }
1332
1333 err = spi_register_controller(ctlr);
1334 if (err) {
1335 dev_err(&pdev->dev, "could not register SPI controller: %d\n",
1336 err);
1337 goto out_dma_release;
1338 }
1339
1340 bcm2835_debugfs_create(bs, dev_name(&pdev->dev));
1341
1342 return 0;
1343
1344 out_dma_release:
1345 bcm2835_dma_release(ctlr, bs);
1346 out_clk_disable:
1347 clk_disable_unprepare(bs->clk);
1348 return err;
1349 }
1350
bcm2835_spi_remove(struct platform_device * pdev)1351 static int bcm2835_spi_remove(struct platform_device *pdev)
1352 {
1353 struct spi_controller *ctlr = platform_get_drvdata(pdev);
1354 struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
1355
1356 bcm2835_debugfs_remove(bs);
1357
1358 spi_unregister_controller(ctlr);
1359
1360 bcm2835_dma_release(ctlr, bs);
1361
1362 /* Clear FIFOs, and disable the HW block */
1363 bcm2835_wr(bs, BCM2835_SPI_CS,
1364 BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);
1365
1366 clk_disable_unprepare(bs->clk);
1367
1368 return 0;
1369 }
1370
bcm2835_spi_shutdown(struct platform_device * pdev)1371 static void bcm2835_spi_shutdown(struct platform_device *pdev)
1372 {
1373 int ret;
1374
1375 ret = bcm2835_spi_remove(pdev);
1376 if (ret)
1377 dev_err(&pdev->dev, "failed to shutdown\n");
1378 }
1379
1380 static const struct of_device_id bcm2835_spi_match[] = {
1381 { .compatible = "brcm,bcm2835-spi", },
1382 {}
1383 };
1384 MODULE_DEVICE_TABLE(of, bcm2835_spi_match);
1385
1386 static struct platform_driver bcm2835_spi_driver = {
1387 .driver = {
1388 .name = DRV_NAME,
1389 .of_match_table = bcm2835_spi_match,
1390 },
1391 .probe = bcm2835_spi_probe,
1392 .remove = bcm2835_spi_remove,
1393 .shutdown = bcm2835_spi_shutdown,
1394 };
1395 module_platform_driver(bcm2835_spi_driver);
1396
1397 MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835");
1398 MODULE_AUTHOR("Chris Boot <bootc@bootc.net>");
1399 MODULE_LICENSE("GPL");
1400