1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5 */
6 #include <linux/bitfield.h>
7 #include <linux/clk.h>
8 #include <linux/dmaengine.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/errno.h>
11 #include <linux/io.h>
12 #include <linux/iopoll.h>
13 #include <linux/interrupt.h>
14 #include <linux/module.h>
15 #include <linux/mutex.h>
16 #include <linux/of.h>
17 #include <linux/of_device.h>
18 #include <linux/pinctrl/consumer.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/platform_device.h>
21 #include <linux/reset.h>
22 #include <linux/sizes.h>
23 #include <linux/spi/spi-mem.h>
24
25 #define QSPI_CR 0x00
26 #define CR_EN BIT(0)
27 #define CR_ABORT BIT(1)
28 #define CR_DMAEN BIT(2)
29 #define CR_TCEN BIT(3)
30 #define CR_SSHIFT BIT(4)
31 #define CR_DFM BIT(6)
32 #define CR_FSEL BIT(7)
33 #define CR_FTHRES_SHIFT 8
34 #define CR_TEIE BIT(16)
35 #define CR_TCIE BIT(17)
36 #define CR_FTIE BIT(18)
37 #define CR_SMIE BIT(19)
38 #define CR_TOIE BIT(20)
39 #define CR_PRESC_MASK GENMASK(31, 24)
40
41 #define QSPI_DCR 0x04
42 #define DCR_FSIZE_MASK GENMASK(20, 16)
43
44 #define QSPI_SR 0x08
45 #define SR_TEF BIT(0)
46 #define SR_TCF BIT(1)
47 #define SR_FTF BIT(2)
48 #define SR_SMF BIT(3)
49 #define SR_TOF BIT(4)
50 #define SR_BUSY BIT(5)
51 #define SR_FLEVEL_MASK GENMASK(13, 8)
52
53 #define QSPI_FCR 0x0c
54 #define FCR_CTEF BIT(0)
55 #define FCR_CTCF BIT(1)
56
57 #define QSPI_DLR 0x10
58
59 #define QSPI_CCR 0x14
60 #define CCR_INST_MASK GENMASK(7, 0)
61 #define CCR_IMODE_MASK GENMASK(9, 8)
62 #define CCR_ADMODE_MASK GENMASK(11, 10)
63 #define CCR_ADSIZE_MASK GENMASK(13, 12)
64 #define CCR_DCYC_MASK GENMASK(22, 18)
65 #define CCR_DMODE_MASK GENMASK(25, 24)
66 #define CCR_FMODE_MASK GENMASK(27, 26)
67 #define CCR_FMODE_INDW (0U << 26)
68 #define CCR_FMODE_INDR (1U << 26)
69 #define CCR_FMODE_APM (2U << 26)
70 #define CCR_FMODE_MM (3U << 26)
71 #define CCR_BUSWIDTH_0 0x0
72 #define CCR_BUSWIDTH_1 0x1
73 #define CCR_BUSWIDTH_2 0x2
74 #define CCR_BUSWIDTH_4 0x3
75
76 #define QSPI_AR 0x18
77 #define QSPI_ABR 0x1c
78 #define QSPI_DR 0x20
79 #define QSPI_PSMKR 0x24
80 #define QSPI_PSMAR 0x28
81 #define QSPI_PIR 0x2c
82 #define QSPI_LPTR 0x30
83
84 #define STM32_QSPI_MAX_MMAP_SZ SZ_256M
85 #define STM32_QSPI_MAX_NORCHIP 2
86
87 #define STM32_FIFO_TIMEOUT_US 30000
88 #define STM32_BUSY_TIMEOUT_US 100000
89 #define STM32_ABT_TIMEOUT_US 100000
90 #define STM32_COMP_TIMEOUT_MS 1000
91 #define STM32_AUTOSUSPEND_DELAY -1
92
93 struct stm32_qspi_flash {
94 struct stm32_qspi *qspi;
95 u32 cs;
96 u32 presc;
97 };
98
99 struct stm32_qspi {
100 struct device *dev;
101 struct spi_controller *ctrl;
102 phys_addr_t phys_base;
103 void __iomem *io_base;
104 void __iomem *mm_base;
105 resource_size_t mm_size;
106 struct clk *clk;
107 u32 clk_rate;
108 struct stm32_qspi_flash flash[STM32_QSPI_MAX_NORCHIP];
109 struct completion data_completion;
110 u32 fmode;
111
112 struct dma_chan *dma_chtx;
113 struct dma_chan *dma_chrx;
114 struct completion dma_completion;
115
116 u32 cr_reg;
117 u32 dcr_reg;
118
119 /*
120 * to protect device configuration, could be different between
121 * 2 flash access (bk1, bk2)
122 */
123 struct mutex lock;
124 };
125
stm32_qspi_irq(int irq,void * dev_id)126 static irqreturn_t stm32_qspi_irq(int irq, void *dev_id)
127 {
128 struct stm32_qspi *qspi = (struct stm32_qspi *)dev_id;
129 u32 cr, sr;
130
131 sr = readl_relaxed(qspi->io_base + QSPI_SR);
132
133 if (sr & (SR_TEF | SR_TCF)) {
134 /* disable irq */
135 cr = readl_relaxed(qspi->io_base + QSPI_CR);
136 cr &= ~CR_TCIE & ~CR_TEIE;
137 writel_relaxed(cr, qspi->io_base + QSPI_CR);
138 complete(&qspi->data_completion);
139 }
140
141 return IRQ_HANDLED;
142 }
143
stm32_qspi_read_fifo(u8 * val,void __iomem * addr)144 static void stm32_qspi_read_fifo(u8 *val, void __iomem *addr)
145 {
146 *val = readb_relaxed(addr);
147 }
148
stm32_qspi_write_fifo(u8 * val,void __iomem * addr)149 static void stm32_qspi_write_fifo(u8 *val, void __iomem *addr)
150 {
151 writeb_relaxed(*val, addr);
152 }
153
stm32_qspi_tx_poll(struct stm32_qspi * qspi,const struct spi_mem_op * op)154 static int stm32_qspi_tx_poll(struct stm32_qspi *qspi,
155 const struct spi_mem_op *op)
156 {
157 void (*tx_fifo)(u8 *val, void __iomem *addr);
158 u32 len = op->data.nbytes, sr;
159 u8 *buf;
160 int ret;
161
162 if (op->data.dir == SPI_MEM_DATA_IN) {
163 tx_fifo = stm32_qspi_read_fifo;
164 buf = op->data.buf.in;
165
166 } else {
167 tx_fifo = stm32_qspi_write_fifo;
168 buf = (u8 *)op->data.buf.out;
169 }
170
171 while (len--) {
172 ret = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR,
173 sr, (sr & SR_FTF), 1,
174 STM32_FIFO_TIMEOUT_US);
175 if (ret) {
176 dev_err(qspi->dev, "fifo timeout (len:%d stat:%#x)\n",
177 len, sr);
178 return ret;
179 }
180 tx_fifo(buf++, qspi->io_base + QSPI_DR);
181 }
182
183 return 0;
184 }
185
stm32_qspi_tx_mm(struct stm32_qspi * qspi,const struct spi_mem_op * op)186 static int stm32_qspi_tx_mm(struct stm32_qspi *qspi,
187 const struct spi_mem_op *op)
188 {
189 memcpy_fromio(op->data.buf.in, qspi->mm_base + op->addr.val,
190 op->data.nbytes);
191 return 0;
192 }
193
stm32_qspi_dma_callback(void * arg)194 static void stm32_qspi_dma_callback(void *arg)
195 {
196 struct completion *dma_completion = arg;
197
198 complete(dma_completion);
199 }
200
stm32_qspi_tx_dma(struct stm32_qspi * qspi,const struct spi_mem_op * op)201 static int stm32_qspi_tx_dma(struct stm32_qspi *qspi,
202 const struct spi_mem_op *op)
203 {
204 struct dma_async_tx_descriptor *desc;
205 enum dma_transfer_direction dma_dir;
206 struct dma_chan *dma_ch;
207 struct sg_table sgt;
208 dma_cookie_t cookie;
209 u32 cr, t_out;
210 int err;
211
212 if (op->data.dir == SPI_MEM_DATA_IN) {
213 dma_dir = DMA_DEV_TO_MEM;
214 dma_ch = qspi->dma_chrx;
215 } else {
216 dma_dir = DMA_MEM_TO_DEV;
217 dma_ch = qspi->dma_chtx;
218 }
219
220 /*
221 * spi_map_buf return -EINVAL if the buffer is not DMA-able
222 * (DMA-able: in vmalloc | kmap | virt_addr_valid)
223 */
224 err = spi_controller_dma_map_mem_op_data(qspi->ctrl, op, &sgt);
225 if (err)
226 return err;
227
228 desc = dmaengine_prep_slave_sg(dma_ch, sgt.sgl, sgt.nents,
229 dma_dir, DMA_PREP_INTERRUPT);
230 if (!desc) {
231 err = -ENOMEM;
232 goto out_unmap;
233 }
234
235 cr = readl_relaxed(qspi->io_base + QSPI_CR);
236
237 reinit_completion(&qspi->dma_completion);
238 desc->callback = stm32_qspi_dma_callback;
239 desc->callback_param = &qspi->dma_completion;
240 cookie = dmaengine_submit(desc);
241 err = dma_submit_error(cookie);
242 if (err)
243 goto out;
244
245 dma_async_issue_pending(dma_ch);
246
247 writel_relaxed(cr | CR_DMAEN, qspi->io_base + QSPI_CR);
248
249 t_out = sgt.nents * STM32_COMP_TIMEOUT_MS;
250 if (!wait_for_completion_timeout(&qspi->dma_completion,
251 msecs_to_jiffies(t_out)))
252 err = -ETIMEDOUT;
253
254 if (err)
255 dmaengine_terminate_all(dma_ch);
256
257 out:
258 writel_relaxed(cr & ~CR_DMAEN, qspi->io_base + QSPI_CR);
259 out_unmap:
260 spi_controller_dma_unmap_mem_op_data(qspi->ctrl, op, &sgt);
261
262 return err;
263 }
264
stm32_qspi_tx(struct stm32_qspi * qspi,const struct spi_mem_op * op)265 static int stm32_qspi_tx(struct stm32_qspi *qspi, const struct spi_mem_op *op)
266 {
267 if (!op->data.nbytes)
268 return 0;
269
270 if (qspi->fmode == CCR_FMODE_MM)
271 return stm32_qspi_tx_mm(qspi, op);
272 else if (((op->data.dir == SPI_MEM_DATA_IN && qspi->dma_chrx) ||
273 (op->data.dir == SPI_MEM_DATA_OUT && qspi->dma_chtx)) &&
274 op->data.nbytes > 4)
275 if (!stm32_qspi_tx_dma(qspi, op))
276 return 0;
277
278 return stm32_qspi_tx_poll(qspi, op);
279 }
280
stm32_qspi_wait_nobusy(struct stm32_qspi * qspi)281 static int stm32_qspi_wait_nobusy(struct stm32_qspi *qspi)
282 {
283 u32 sr;
284
285 return readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR, sr,
286 !(sr & SR_BUSY), 1,
287 STM32_BUSY_TIMEOUT_US);
288 }
289
stm32_qspi_wait_cmd(struct stm32_qspi * qspi,const struct spi_mem_op * op)290 static int stm32_qspi_wait_cmd(struct stm32_qspi *qspi,
291 const struct spi_mem_op *op)
292 {
293 u32 cr, sr;
294 int err = 0;
295
296 if (!op->data.nbytes)
297 return stm32_qspi_wait_nobusy(qspi);
298
299 if (readl_relaxed(qspi->io_base + QSPI_SR) & SR_TCF)
300 goto out;
301
302 reinit_completion(&qspi->data_completion);
303 cr = readl_relaxed(qspi->io_base + QSPI_CR);
304 writel_relaxed(cr | CR_TCIE | CR_TEIE, qspi->io_base + QSPI_CR);
305
306 if (!wait_for_completion_timeout(&qspi->data_completion,
307 msecs_to_jiffies(STM32_COMP_TIMEOUT_MS))) {
308 err = -ETIMEDOUT;
309 } else {
310 sr = readl_relaxed(qspi->io_base + QSPI_SR);
311 if (sr & SR_TEF)
312 err = -EIO;
313 }
314
315 out:
316 /* clear flags */
317 writel_relaxed(FCR_CTCF | FCR_CTEF, qspi->io_base + QSPI_FCR);
318
319 return err;
320 }
321
stm32_qspi_get_mode(struct stm32_qspi * qspi,u8 buswidth)322 static int stm32_qspi_get_mode(struct stm32_qspi *qspi, u8 buswidth)
323 {
324 if (buswidth == 4)
325 return CCR_BUSWIDTH_4;
326
327 return buswidth;
328 }
329
stm32_qspi_send(struct spi_mem * mem,const struct spi_mem_op * op)330 static int stm32_qspi_send(struct spi_mem *mem, const struct spi_mem_op *op)
331 {
332 struct stm32_qspi *qspi = spi_controller_get_devdata(mem->spi->master);
333 struct stm32_qspi_flash *flash = &qspi->flash[mem->spi->chip_select];
334 u32 ccr, cr;
335 int timeout, err = 0;
336
337 dev_dbg(qspi->dev, "cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n",
338 op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
339 op->dummy.buswidth, op->data.buswidth,
340 op->addr.val, op->data.nbytes);
341
342 err = stm32_qspi_wait_nobusy(qspi);
343 if (err)
344 goto abort;
345
346 cr = readl_relaxed(qspi->io_base + QSPI_CR);
347 cr &= ~CR_PRESC_MASK & ~CR_FSEL;
348 cr |= FIELD_PREP(CR_PRESC_MASK, flash->presc);
349 cr |= FIELD_PREP(CR_FSEL, flash->cs);
350 writel_relaxed(cr, qspi->io_base + QSPI_CR);
351
352 if (op->data.nbytes)
353 writel_relaxed(op->data.nbytes - 1,
354 qspi->io_base + QSPI_DLR);
355
356 ccr = qspi->fmode;
357 ccr |= FIELD_PREP(CCR_INST_MASK, op->cmd.opcode);
358 ccr |= FIELD_PREP(CCR_IMODE_MASK,
359 stm32_qspi_get_mode(qspi, op->cmd.buswidth));
360
361 if (op->addr.nbytes) {
362 ccr |= FIELD_PREP(CCR_ADMODE_MASK,
363 stm32_qspi_get_mode(qspi, op->addr.buswidth));
364 ccr |= FIELD_PREP(CCR_ADSIZE_MASK, op->addr.nbytes - 1);
365 }
366
367 if (op->dummy.buswidth && op->dummy.nbytes)
368 ccr |= FIELD_PREP(CCR_DCYC_MASK,
369 op->dummy.nbytes * 8 / op->dummy.buswidth);
370
371 if (op->data.nbytes) {
372 ccr |= FIELD_PREP(CCR_DMODE_MASK,
373 stm32_qspi_get_mode(qspi, op->data.buswidth));
374 }
375
376 writel_relaxed(ccr, qspi->io_base + QSPI_CCR);
377
378 if (op->addr.nbytes && qspi->fmode != CCR_FMODE_MM)
379 writel_relaxed(op->addr.val, qspi->io_base + QSPI_AR);
380
381 err = stm32_qspi_tx(qspi, op);
382
383 /*
384 * Abort in:
385 * -error case
386 * -read memory map: prefetching must be stopped if we read the last
387 * byte of device (device size - fifo size). like device size is not
388 * knows, the prefetching is always stop.
389 */
390 if (err || qspi->fmode == CCR_FMODE_MM)
391 goto abort;
392
393 /* wait end of tx in indirect mode */
394 err = stm32_qspi_wait_cmd(qspi, op);
395 if (err)
396 goto abort;
397
398 return 0;
399
400 abort:
401 cr = readl_relaxed(qspi->io_base + QSPI_CR) | CR_ABORT;
402 writel_relaxed(cr, qspi->io_base + QSPI_CR);
403
404 /* wait clear of abort bit by hw */
405 timeout = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_CR,
406 cr, !(cr & CR_ABORT), 1,
407 STM32_ABT_TIMEOUT_US);
408
409 writel_relaxed(FCR_CTCF, qspi->io_base + QSPI_FCR);
410
411 if (err || timeout)
412 dev_err(qspi->dev, "%s err:%d abort timeout:%d\n",
413 __func__, err, timeout);
414
415 return err;
416 }
417
stm32_qspi_exec_op(struct spi_mem * mem,const struct spi_mem_op * op)418 static int stm32_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
419 {
420 struct stm32_qspi *qspi = spi_controller_get_devdata(mem->spi->master);
421 int ret;
422
423 ret = pm_runtime_get_sync(qspi->dev);
424 if (ret < 0) {
425 pm_runtime_put_noidle(qspi->dev);
426 return ret;
427 }
428
429 mutex_lock(&qspi->lock);
430 if (op->data.dir == SPI_MEM_DATA_IN && op->data.nbytes)
431 qspi->fmode = CCR_FMODE_INDR;
432 else
433 qspi->fmode = CCR_FMODE_INDW;
434
435 ret = stm32_qspi_send(mem, op);
436 mutex_unlock(&qspi->lock);
437
438 pm_runtime_mark_last_busy(qspi->dev);
439 pm_runtime_put_autosuspend(qspi->dev);
440
441 return ret;
442 }
443
stm32_qspi_dirmap_create(struct spi_mem_dirmap_desc * desc)444 static int stm32_qspi_dirmap_create(struct spi_mem_dirmap_desc *desc)
445 {
446 struct stm32_qspi *qspi = spi_controller_get_devdata(desc->mem->spi->master);
447
448 if (desc->info.op_tmpl.data.dir == SPI_MEM_DATA_OUT)
449 return -EOPNOTSUPP;
450
451 /* should never happen, as mm_base == null is an error probe exit condition */
452 if (!qspi->mm_base && desc->info.op_tmpl.data.dir == SPI_MEM_DATA_IN)
453 return -EOPNOTSUPP;
454
455 if (!qspi->mm_size)
456 return -EOPNOTSUPP;
457
458 return 0;
459 }
460
stm32_qspi_dirmap_read(struct spi_mem_dirmap_desc * desc,u64 offs,size_t len,void * buf)461 static ssize_t stm32_qspi_dirmap_read(struct spi_mem_dirmap_desc *desc,
462 u64 offs, size_t len, void *buf)
463 {
464 struct stm32_qspi *qspi = spi_controller_get_devdata(desc->mem->spi->master);
465 struct spi_mem_op op;
466 u32 addr_max;
467 int ret;
468
469 ret = pm_runtime_get_sync(qspi->dev);
470 if (ret < 0) {
471 pm_runtime_put_noidle(qspi->dev);
472 return ret;
473 }
474
475 mutex_lock(&qspi->lock);
476 /* make a local copy of desc op_tmpl and complete dirmap rdesc
477 * spi_mem_op template with offs, len and *buf in order to get
478 * all needed transfer information into struct spi_mem_op
479 */
480 memcpy(&op, &desc->info.op_tmpl, sizeof(struct spi_mem_op));
481 dev_dbg(qspi->dev, "%s len = 0x%zx offs = 0x%llx buf = 0x%p\n", __func__, len, offs, buf);
482
483 op.data.nbytes = len;
484 op.addr.val = desc->info.offset + offs;
485 op.data.buf.in = buf;
486
487 addr_max = op.addr.val + op.data.nbytes + 1;
488 if (addr_max < qspi->mm_size && op.addr.buswidth)
489 qspi->fmode = CCR_FMODE_MM;
490 else
491 qspi->fmode = CCR_FMODE_INDR;
492
493 ret = stm32_qspi_send(desc->mem, &op);
494 mutex_unlock(&qspi->lock);
495
496 pm_runtime_mark_last_busy(qspi->dev);
497 pm_runtime_put_autosuspend(qspi->dev);
498
499 return ret ?: len;
500 }
501
stm32_qspi_setup(struct spi_device * spi)502 static int stm32_qspi_setup(struct spi_device *spi)
503 {
504 struct spi_controller *ctrl = spi->master;
505 struct stm32_qspi *qspi = spi_controller_get_devdata(ctrl);
506 struct stm32_qspi_flash *flash;
507 u32 presc;
508 int ret;
509
510 if (ctrl->busy)
511 return -EBUSY;
512
513 if (!spi->max_speed_hz)
514 return -EINVAL;
515
516 ret = pm_runtime_get_sync(qspi->dev);
517 if (ret < 0) {
518 pm_runtime_put_noidle(qspi->dev);
519 return ret;
520 }
521
522 presc = DIV_ROUND_UP(qspi->clk_rate, spi->max_speed_hz) - 1;
523
524 flash = &qspi->flash[spi->chip_select];
525 flash->qspi = qspi;
526 flash->cs = spi->chip_select;
527 flash->presc = presc;
528
529 mutex_lock(&qspi->lock);
530 qspi->cr_reg = 3 << CR_FTHRES_SHIFT | CR_SSHIFT | CR_EN;
531 writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR);
532
533 /* set dcr fsize to max address */
534 qspi->dcr_reg = DCR_FSIZE_MASK;
535 writel_relaxed(qspi->dcr_reg, qspi->io_base + QSPI_DCR);
536 mutex_unlock(&qspi->lock);
537
538 pm_runtime_mark_last_busy(qspi->dev);
539 pm_runtime_put_autosuspend(qspi->dev);
540
541 return 0;
542 }
543
stm32_qspi_dma_setup(struct stm32_qspi * qspi)544 static int stm32_qspi_dma_setup(struct stm32_qspi *qspi)
545 {
546 struct dma_slave_config dma_cfg;
547 struct device *dev = qspi->dev;
548 int ret = 0;
549
550 memset(&dma_cfg, 0, sizeof(dma_cfg));
551
552 dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
553 dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
554 dma_cfg.src_addr = qspi->phys_base + QSPI_DR;
555 dma_cfg.dst_addr = qspi->phys_base + QSPI_DR;
556 dma_cfg.src_maxburst = 4;
557 dma_cfg.dst_maxburst = 4;
558
559 qspi->dma_chrx = dma_request_chan(dev, "rx");
560 if (IS_ERR(qspi->dma_chrx)) {
561 ret = PTR_ERR(qspi->dma_chrx);
562 qspi->dma_chrx = NULL;
563 if (ret == -EPROBE_DEFER)
564 goto out;
565 } else {
566 if (dmaengine_slave_config(qspi->dma_chrx, &dma_cfg)) {
567 dev_err(dev, "dma rx config failed\n");
568 dma_release_channel(qspi->dma_chrx);
569 qspi->dma_chrx = NULL;
570 }
571 }
572
573 qspi->dma_chtx = dma_request_chan(dev, "tx");
574 if (IS_ERR(qspi->dma_chtx)) {
575 ret = PTR_ERR(qspi->dma_chtx);
576 qspi->dma_chtx = NULL;
577 } else {
578 if (dmaengine_slave_config(qspi->dma_chtx, &dma_cfg)) {
579 dev_err(dev, "dma tx config failed\n");
580 dma_release_channel(qspi->dma_chtx);
581 qspi->dma_chtx = NULL;
582 }
583 }
584
585 out:
586 init_completion(&qspi->dma_completion);
587
588 if (ret != -EPROBE_DEFER)
589 ret = 0;
590
591 return ret;
592 }
593
stm32_qspi_dma_free(struct stm32_qspi * qspi)594 static void stm32_qspi_dma_free(struct stm32_qspi *qspi)
595 {
596 if (qspi->dma_chtx)
597 dma_release_channel(qspi->dma_chtx);
598 if (qspi->dma_chrx)
599 dma_release_channel(qspi->dma_chrx);
600 }
601
602 /*
603 * no special host constraint, so use default spi_mem_default_supports_op
604 * to check supported mode.
605 */
606 static const struct spi_controller_mem_ops stm32_qspi_mem_ops = {
607 .exec_op = stm32_qspi_exec_op,
608 .dirmap_create = stm32_qspi_dirmap_create,
609 .dirmap_read = stm32_qspi_dirmap_read,
610 };
611
stm32_qspi_probe(struct platform_device * pdev)612 static int stm32_qspi_probe(struct platform_device *pdev)
613 {
614 struct device *dev = &pdev->dev;
615 struct spi_controller *ctrl;
616 struct reset_control *rstc;
617 struct stm32_qspi *qspi;
618 struct resource *res;
619 int ret, irq;
620
621 ctrl = spi_alloc_master(dev, sizeof(*qspi));
622 if (!ctrl)
623 return -ENOMEM;
624
625 qspi = spi_controller_get_devdata(ctrl);
626 qspi->ctrl = ctrl;
627
628 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi");
629 qspi->io_base = devm_ioremap_resource(dev, res);
630 if (IS_ERR(qspi->io_base)) {
631 ret = PTR_ERR(qspi->io_base);
632 goto err_master_put;
633 }
634
635 qspi->phys_base = res->start;
636
637 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mm");
638 qspi->mm_base = devm_ioremap_resource(dev, res);
639 if (IS_ERR(qspi->mm_base)) {
640 ret = PTR_ERR(qspi->mm_base);
641 goto err_master_put;
642 }
643
644 qspi->mm_size = resource_size(res);
645 if (qspi->mm_size > STM32_QSPI_MAX_MMAP_SZ) {
646 ret = -EINVAL;
647 goto err_master_put;
648 }
649
650 irq = platform_get_irq(pdev, 0);
651 if (irq < 0) {
652 ret = irq;
653 goto err_master_put;
654 }
655
656 ret = devm_request_irq(dev, irq, stm32_qspi_irq, 0,
657 dev_name(dev), qspi);
658 if (ret) {
659 dev_err(dev, "failed to request irq\n");
660 goto err_master_put;
661 }
662
663 init_completion(&qspi->data_completion);
664
665 qspi->clk = devm_clk_get(dev, NULL);
666 if (IS_ERR(qspi->clk)) {
667 ret = PTR_ERR(qspi->clk);
668 goto err_master_put;
669 }
670
671 qspi->clk_rate = clk_get_rate(qspi->clk);
672 if (!qspi->clk_rate) {
673 ret = -EINVAL;
674 goto err_master_put;
675 }
676
677 ret = clk_prepare_enable(qspi->clk);
678 if (ret) {
679 dev_err(dev, "can not enable the clock\n");
680 goto err_master_put;
681 }
682
683 rstc = devm_reset_control_get_exclusive(dev, NULL);
684 if (IS_ERR(rstc)) {
685 ret = PTR_ERR(rstc);
686 if (ret == -EPROBE_DEFER)
687 goto err_clk_disable;
688 } else {
689 reset_control_assert(rstc);
690 udelay(2);
691 reset_control_deassert(rstc);
692 }
693
694 qspi->dev = dev;
695 platform_set_drvdata(pdev, qspi);
696 ret = stm32_qspi_dma_setup(qspi);
697 if (ret)
698 goto err_dma_free;
699
700 mutex_init(&qspi->lock);
701
702 ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD
703 | SPI_TX_DUAL | SPI_TX_QUAD;
704 ctrl->setup = stm32_qspi_setup;
705 ctrl->bus_num = -1;
706 ctrl->mem_ops = &stm32_qspi_mem_ops;
707 ctrl->num_chipselect = STM32_QSPI_MAX_NORCHIP;
708 ctrl->dev.of_node = dev->of_node;
709
710 pm_runtime_set_autosuspend_delay(dev, STM32_AUTOSUSPEND_DELAY);
711 pm_runtime_use_autosuspend(dev);
712 pm_runtime_set_active(dev);
713 pm_runtime_enable(dev);
714 pm_runtime_get_noresume(dev);
715
716 ret = devm_spi_register_master(dev, ctrl);
717 if (ret)
718 goto err_pm_runtime_free;
719
720 pm_runtime_mark_last_busy(dev);
721 pm_runtime_put_autosuspend(dev);
722
723 return 0;
724
725 err_pm_runtime_free:
726 pm_runtime_get_sync(qspi->dev);
727 /* disable qspi */
728 writel_relaxed(0, qspi->io_base + QSPI_CR);
729 mutex_destroy(&qspi->lock);
730 pm_runtime_put_noidle(qspi->dev);
731 pm_runtime_disable(qspi->dev);
732 pm_runtime_set_suspended(qspi->dev);
733 pm_runtime_dont_use_autosuspend(qspi->dev);
734 err_dma_free:
735 stm32_qspi_dma_free(qspi);
736 err_clk_disable:
737 clk_disable_unprepare(qspi->clk);
738 err_master_put:
739 spi_master_put(qspi->ctrl);
740
741 return ret;
742 }
743
stm32_qspi_remove(struct platform_device * pdev)744 static int stm32_qspi_remove(struct platform_device *pdev)
745 {
746 struct stm32_qspi *qspi = platform_get_drvdata(pdev);
747
748 pm_runtime_get_sync(qspi->dev);
749 /* disable qspi */
750 writel_relaxed(0, qspi->io_base + QSPI_CR);
751 stm32_qspi_dma_free(qspi);
752 mutex_destroy(&qspi->lock);
753 pm_runtime_put_noidle(qspi->dev);
754 pm_runtime_disable(qspi->dev);
755 pm_runtime_set_suspended(qspi->dev);
756 pm_runtime_dont_use_autosuspend(qspi->dev);
757 clk_disable_unprepare(qspi->clk);
758
759 return 0;
760 }
761
stm32_qspi_runtime_suspend(struct device * dev)762 static int __maybe_unused stm32_qspi_runtime_suspend(struct device *dev)
763 {
764 struct stm32_qspi *qspi = dev_get_drvdata(dev);
765
766 clk_disable_unprepare(qspi->clk);
767
768 return 0;
769 }
770
stm32_qspi_runtime_resume(struct device * dev)771 static int __maybe_unused stm32_qspi_runtime_resume(struct device *dev)
772 {
773 struct stm32_qspi *qspi = dev_get_drvdata(dev);
774
775 return clk_prepare_enable(qspi->clk);
776 }
777
stm32_qspi_suspend(struct device * dev)778 static int __maybe_unused stm32_qspi_suspend(struct device *dev)
779 {
780 pinctrl_pm_select_sleep_state(dev);
781
782 return pm_runtime_force_suspend(dev);
783 }
784
stm32_qspi_resume(struct device * dev)785 static int __maybe_unused stm32_qspi_resume(struct device *dev)
786 {
787 struct stm32_qspi *qspi = dev_get_drvdata(dev);
788 int ret;
789
790 ret = pm_runtime_force_resume(dev);
791 if (ret < 0)
792 return ret;
793
794 pinctrl_pm_select_default_state(dev);
795
796 ret = pm_runtime_get_sync(dev);
797 if (ret < 0) {
798 pm_runtime_put_noidle(dev);
799 return ret;
800 }
801
802 writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR);
803 writel_relaxed(qspi->dcr_reg, qspi->io_base + QSPI_DCR);
804
805 pm_runtime_mark_last_busy(dev);
806 pm_runtime_put_autosuspend(dev);
807
808 return 0;
809 }
810
811 static const struct dev_pm_ops stm32_qspi_pm_ops = {
812 SET_RUNTIME_PM_OPS(stm32_qspi_runtime_suspend,
813 stm32_qspi_runtime_resume, NULL)
814 SET_SYSTEM_SLEEP_PM_OPS(stm32_qspi_suspend, stm32_qspi_resume)
815 };
816
817 static const struct of_device_id stm32_qspi_match[] = {
818 {.compatible = "st,stm32f469-qspi"},
819 {}
820 };
821 MODULE_DEVICE_TABLE(of, stm32_qspi_match);
822
823 static struct platform_driver stm32_qspi_driver = {
824 .probe = stm32_qspi_probe,
825 .remove = stm32_qspi_remove,
826 .driver = {
827 .name = "stm32-qspi",
828 .of_match_table = stm32_qspi_match,
829 .pm = &stm32_qspi_pm_ops,
830 },
831 };
832 module_platform_driver(stm32_qspi_driver);
833
834 MODULE_AUTHOR("Ludovic Barre <ludovic.barre@st.com>");
835 MODULE_DESCRIPTION("STMicroelectronics STM32 quad spi driver");
836 MODULE_LICENSE("GPL v2");
837