1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Xilinx SPI controller driver (master mode only)
4  *
5  * Author: MontaVista Software, Inc.
6  *	source@mvista.com
7  *
8  * Copyright (c) 2010 Secret Lab Technologies, Ltd.
9  * Copyright (c) 2009 Intel Corporation
10  * 2002-2007 (c) MontaVista Software, Inc.
11 
12  */
13 
14 #include <linux/module.h>
15 #include <linux/interrupt.h>
16 #include <linux/of.h>
17 #include <linux/platform_device.h>
18 #include <linux/spi/spi.h>
19 #include <linux/spi/spi_bitbang.h>
20 #include <linux/spi/xilinx_spi.h>
21 #include <linux/io.h>
22 
23 #define XILINX_SPI_MAX_CS	32
24 
25 #define XILINX_SPI_NAME "xilinx_spi"
26 
27 /* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e)
28  * Product Specification", DS464
29  */
30 #define XSPI_CR_OFFSET		0x60	/* Control Register */
31 
32 #define XSPI_CR_LOOP		0x01
33 #define XSPI_CR_ENABLE		0x02
34 #define XSPI_CR_MASTER_MODE	0x04
35 #define XSPI_CR_CPOL		0x08
36 #define XSPI_CR_CPHA		0x10
37 #define XSPI_CR_MODE_MASK	(XSPI_CR_CPHA | XSPI_CR_CPOL | \
38 				 XSPI_CR_LSB_FIRST | XSPI_CR_LOOP)
39 #define XSPI_CR_TXFIFO_RESET	0x20
40 #define XSPI_CR_RXFIFO_RESET	0x40
41 #define XSPI_CR_MANUAL_SSELECT	0x80
42 #define XSPI_CR_TRANS_INHIBIT	0x100
43 #define XSPI_CR_LSB_FIRST	0x200
44 
45 #define XSPI_SR_OFFSET		0x64	/* Status Register */
46 
47 #define XSPI_SR_RX_EMPTY_MASK	0x01	/* Receive FIFO is empty */
48 #define XSPI_SR_RX_FULL_MASK	0x02	/* Receive FIFO is full */
49 #define XSPI_SR_TX_EMPTY_MASK	0x04	/* Transmit FIFO is empty */
50 #define XSPI_SR_TX_FULL_MASK	0x08	/* Transmit FIFO is full */
51 #define XSPI_SR_MODE_FAULT_MASK	0x10	/* Mode fault error */
52 
53 #define XSPI_TXD_OFFSET		0x68	/* Data Transmit Register */
54 #define XSPI_RXD_OFFSET		0x6c	/* Data Receive Register */
55 
56 #define XSPI_SSR_OFFSET		0x70	/* 32-bit Slave Select Register */
57 
58 /* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414
59  * IPIF registers are 32 bit
60  */
61 #define XIPIF_V123B_DGIER_OFFSET	0x1c	/* IPIF global int enable reg */
62 #define XIPIF_V123B_GINTR_ENABLE	0x80000000
63 
64 #define XIPIF_V123B_IISR_OFFSET		0x20	/* IPIF interrupt status reg */
65 #define XIPIF_V123B_IIER_OFFSET		0x28	/* IPIF interrupt enable reg */
66 
67 #define XSPI_INTR_MODE_FAULT		0x01	/* Mode fault error */
68 #define XSPI_INTR_SLAVE_MODE_FAULT	0x02	/* Selected as slave while
69 						 * disabled */
70 #define XSPI_INTR_TX_EMPTY		0x04	/* TxFIFO is empty */
71 #define XSPI_INTR_TX_UNDERRUN		0x08	/* TxFIFO was underrun */
72 #define XSPI_INTR_RX_FULL		0x10	/* RxFIFO is full */
73 #define XSPI_INTR_RX_OVERRUN		0x20	/* RxFIFO was overrun */
74 #define XSPI_INTR_TX_HALF_EMPTY		0x40	/* TxFIFO is half empty */
75 
76 #define XIPIF_V123B_RESETR_OFFSET	0x40	/* IPIF reset register */
77 #define XIPIF_V123B_RESET_MASK		0x0a	/* the value to write */
78 
79 struct xilinx_spi {
80 	/* bitbang has to be first */
81 	struct spi_bitbang bitbang;
82 	struct completion done;
83 	void __iomem	*regs;	/* virt. address of the control registers */
84 
85 	int		irq;
86 
87 	u8 *rx_ptr;		/* pointer in the Tx buffer */
88 	const u8 *tx_ptr;	/* pointer in the Rx buffer */
89 	u8 bytes_per_word;
90 	int buffer_size;	/* buffer size in words */
91 	u32 cs_inactive;	/* Level of the CS pins when inactive*/
92 	unsigned int (*read_fn)(void __iomem *);
93 	void (*write_fn)(u32, void __iomem *);
94 };
95 
xspi_write32(u32 val,void __iomem * addr)96 static void xspi_write32(u32 val, void __iomem *addr)
97 {
98 	iowrite32(val, addr);
99 }
100 
xspi_read32(void __iomem * addr)101 static unsigned int xspi_read32(void __iomem *addr)
102 {
103 	return ioread32(addr);
104 }
105 
xspi_write32_be(u32 val,void __iomem * addr)106 static void xspi_write32_be(u32 val, void __iomem *addr)
107 {
108 	iowrite32be(val, addr);
109 }
110 
xspi_read32_be(void __iomem * addr)111 static unsigned int xspi_read32_be(void __iomem *addr)
112 {
113 	return ioread32be(addr);
114 }
115 
xilinx_spi_tx(struct xilinx_spi * xspi)116 static void xilinx_spi_tx(struct xilinx_spi *xspi)
117 {
118 	u32 data = 0;
119 
120 	if (!xspi->tx_ptr) {
121 		xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET);
122 		return;
123 	}
124 
125 	switch (xspi->bytes_per_word) {
126 	case 1:
127 		data = *(u8 *)(xspi->tx_ptr);
128 		break;
129 	case 2:
130 		data = *(u16 *)(xspi->tx_ptr);
131 		break;
132 	case 4:
133 		data = *(u32 *)(xspi->tx_ptr);
134 		break;
135 	}
136 
137 	xspi->write_fn(data, xspi->regs + XSPI_TXD_OFFSET);
138 	xspi->tx_ptr += xspi->bytes_per_word;
139 }
140 
xilinx_spi_rx(struct xilinx_spi * xspi)141 static void xilinx_spi_rx(struct xilinx_spi *xspi)
142 {
143 	u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
144 
145 	if (!xspi->rx_ptr)
146 		return;
147 
148 	switch (xspi->bytes_per_word) {
149 	case 1:
150 		*(u8 *)(xspi->rx_ptr) = data;
151 		break;
152 	case 2:
153 		*(u16 *)(xspi->rx_ptr) = data;
154 		break;
155 	case 4:
156 		*(u32 *)(xspi->rx_ptr) = data;
157 		break;
158 	}
159 
160 	xspi->rx_ptr += xspi->bytes_per_word;
161 }
162 
xspi_init_hw(struct xilinx_spi * xspi)163 static void xspi_init_hw(struct xilinx_spi *xspi)
164 {
165 	void __iomem *regs_base = xspi->regs;
166 
167 	/* Reset the SPI device */
168 	xspi->write_fn(XIPIF_V123B_RESET_MASK,
169 		regs_base + XIPIF_V123B_RESETR_OFFSET);
170 	/* Enable the transmit empty interrupt, which we use to determine
171 	 * progress on the transmission.
172 	 */
173 	xspi->write_fn(XSPI_INTR_TX_EMPTY,
174 			regs_base + XIPIF_V123B_IIER_OFFSET);
175 	/* Disable the global IPIF interrupt */
176 	xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET);
177 	/* Deselect the slave on the SPI bus */
178 	xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET);
179 	/* Disable the transmitter, enable Manual Slave Select Assertion,
180 	 * put SPI controller into master mode, and enable it */
181 	xspi->write_fn(XSPI_CR_MANUAL_SSELECT |	XSPI_CR_MASTER_MODE |
182 		XSPI_CR_ENABLE | XSPI_CR_TXFIFO_RESET |	XSPI_CR_RXFIFO_RESET,
183 		regs_base + XSPI_CR_OFFSET);
184 }
185 
xilinx_spi_chipselect(struct spi_device * spi,int is_on)186 static void xilinx_spi_chipselect(struct spi_device *spi, int is_on)
187 {
188 	struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
189 	u16 cr;
190 	u32 cs;
191 
192 	if (is_on == BITBANG_CS_INACTIVE) {
193 		/* Deselect the slave on the SPI bus */
194 		xspi->write_fn(xspi->cs_inactive, xspi->regs + XSPI_SSR_OFFSET);
195 		return;
196 	}
197 
198 	/* Set the SPI clock phase and polarity */
199 	cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET)	& ~XSPI_CR_MODE_MASK;
200 	if (spi->mode & SPI_CPHA)
201 		cr |= XSPI_CR_CPHA;
202 	if (spi->mode & SPI_CPOL)
203 		cr |= XSPI_CR_CPOL;
204 	if (spi->mode & SPI_LSB_FIRST)
205 		cr |= XSPI_CR_LSB_FIRST;
206 	if (spi->mode & SPI_LOOP)
207 		cr |= XSPI_CR_LOOP;
208 	xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
209 
210 	/* We do not check spi->max_speed_hz here as the SPI clock
211 	 * frequency is not software programmable (the IP block design
212 	 * parameter)
213 	 */
214 
215 	cs = xspi->cs_inactive;
216 	cs ^= BIT(spi->chip_select);
217 
218 	/* Activate the chip select */
219 	xspi->write_fn(cs, xspi->regs + XSPI_SSR_OFFSET);
220 }
221 
222 /* spi_bitbang requires custom setup_transfer() to be defined if there is a
223  * custom txrx_bufs().
224  */
xilinx_spi_setup_transfer(struct spi_device * spi,struct spi_transfer * t)225 static int xilinx_spi_setup_transfer(struct spi_device *spi,
226 		struct spi_transfer *t)
227 {
228 	struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
229 
230 	if (spi->mode & SPI_CS_HIGH)
231 		xspi->cs_inactive &= ~BIT(spi->chip_select);
232 	else
233 		xspi->cs_inactive |= BIT(spi->chip_select);
234 
235 	return 0;
236 }
237 
xilinx_spi_txrx_bufs(struct spi_device * spi,struct spi_transfer * t)238 static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
239 {
240 	struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
241 	int remaining_words;	/* the number of words left to transfer */
242 	bool use_irq = false;
243 	u16 cr = 0;
244 
245 	/* We get here with transmitter inhibited */
246 
247 	xspi->tx_ptr = t->tx_buf;
248 	xspi->rx_ptr = t->rx_buf;
249 	remaining_words = t->len / xspi->bytes_per_word;
250 
251 	if (xspi->irq >= 0 &&  remaining_words > xspi->buffer_size) {
252 		u32 isr;
253 		use_irq = true;
254 		/* Inhibit irq to avoid spurious irqs on tx_empty*/
255 		cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
256 		xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
257 			       xspi->regs + XSPI_CR_OFFSET);
258 		/* ACK old irqs (if any) */
259 		isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET);
260 		if (isr)
261 			xspi->write_fn(isr,
262 				       xspi->regs + XIPIF_V123B_IISR_OFFSET);
263 		/* Enable the global IPIF interrupt */
264 		xspi->write_fn(XIPIF_V123B_GINTR_ENABLE,
265 				xspi->regs + XIPIF_V123B_DGIER_OFFSET);
266 		reinit_completion(&xspi->done);
267 	}
268 
269 	while (remaining_words) {
270 		int n_words, tx_words, rx_words;
271 		u32 sr;
272 		int stalled;
273 
274 		n_words = min(remaining_words, xspi->buffer_size);
275 
276 		tx_words = n_words;
277 		while (tx_words--)
278 			xilinx_spi_tx(xspi);
279 
280 		/* Start the transfer by not inhibiting the transmitter any
281 		 * longer
282 		 */
283 
284 		if (use_irq) {
285 			xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
286 			wait_for_completion(&xspi->done);
287 			/* A transmit has just completed. Process received data
288 			 * and check for more data to transmit. Always inhibit
289 			 * the transmitter while the Isr refills the transmit
290 			 * register/FIFO, or make sure it is stopped if we're
291 			 * done.
292 			 */
293 			xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
294 				       xspi->regs + XSPI_CR_OFFSET);
295 			sr = XSPI_SR_TX_EMPTY_MASK;
296 		} else
297 			sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
298 
299 		/* Read out all the data from the Rx FIFO */
300 		rx_words = n_words;
301 		stalled = 10;
302 		while (rx_words) {
303 			if (rx_words == n_words && !(stalled--) &&
304 			    !(sr & XSPI_SR_TX_EMPTY_MASK) &&
305 			    (sr & XSPI_SR_RX_EMPTY_MASK)) {
306 				dev_err(&spi->dev,
307 					"Detected stall. Check C_SPI_MODE and C_SPI_MEMORY\n");
308 				xspi_init_hw(xspi);
309 				return -EIO;
310 			}
311 
312 			if ((sr & XSPI_SR_TX_EMPTY_MASK) && (rx_words > 1)) {
313 				xilinx_spi_rx(xspi);
314 				rx_words--;
315 				continue;
316 			}
317 
318 			sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
319 			if (!(sr & XSPI_SR_RX_EMPTY_MASK)) {
320 				xilinx_spi_rx(xspi);
321 				rx_words--;
322 			}
323 		}
324 
325 		remaining_words -= n_words;
326 	}
327 
328 	if (use_irq) {
329 		xspi->write_fn(0, xspi->regs + XIPIF_V123B_DGIER_OFFSET);
330 		xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
331 	}
332 
333 	return t->len;
334 }
335 
336 
337 /* This driver supports single master mode only. Hence Tx FIFO Empty
338  * is the only interrupt we care about.
339  * Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Slave Mode
340  * Fault are not to happen.
341  */
xilinx_spi_irq(int irq,void * dev_id)342 static irqreturn_t xilinx_spi_irq(int irq, void *dev_id)
343 {
344 	struct xilinx_spi *xspi = dev_id;
345 	u32 ipif_isr;
346 
347 	/* Get the IPIF interrupts, and clear them immediately */
348 	ipif_isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET);
349 	xspi->write_fn(ipif_isr, xspi->regs + XIPIF_V123B_IISR_OFFSET);
350 
351 	if (ipif_isr & XSPI_INTR_TX_EMPTY) {	/* Transmission completed */
352 		complete(&xspi->done);
353 		return IRQ_HANDLED;
354 	}
355 
356 	return IRQ_NONE;
357 }
358 
xilinx_spi_find_buffer_size(struct xilinx_spi * xspi)359 static int xilinx_spi_find_buffer_size(struct xilinx_spi *xspi)
360 {
361 	u8 sr;
362 	int n_words = 0;
363 
364 	/*
365 	 * Before the buffer_size detection we reset the core
366 	 * to make sure we start with a clean state.
367 	 */
368 	xspi->write_fn(XIPIF_V123B_RESET_MASK,
369 		xspi->regs + XIPIF_V123B_RESETR_OFFSET);
370 
371 	/* Fill the Tx FIFO with as many words as possible */
372 	do {
373 		xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET);
374 		sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
375 		n_words++;
376 	} while (!(sr & XSPI_SR_TX_FULL_MASK));
377 
378 	return n_words;
379 }
380 
381 static const struct of_device_id xilinx_spi_of_match[] = {
382 	{ .compatible = "xlnx,axi-quad-spi-1.00.a", },
383 	{ .compatible = "xlnx,xps-spi-2.00.a", },
384 	{ .compatible = "xlnx,xps-spi-2.00.b", },
385 	{}
386 };
387 MODULE_DEVICE_TABLE(of, xilinx_spi_of_match);
388 
xilinx_spi_probe(struct platform_device * pdev)389 static int xilinx_spi_probe(struct platform_device *pdev)
390 {
391 	struct xilinx_spi *xspi;
392 	struct xspi_platform_data *pdata;
393 	struct resource *res;
394 	int ret, num_cs = 0, bits_per_word;
395 	struct spi_master *master;
396 	u32 tmp;
397 	u8 i;
398 
399 	pdata = dev_get_platdata(&pdev->dev);
400 	if (pdata) {
401 		num_cs = pdata->num_chipselect;
402 		bits_per_word = pdata->bits_per_word;
403 	} else {
404 		of_property_read_u32(pdev->dev.of_node, "xlnx,num-ss-bits",
405 					  &num_cs);
406 		ret = of_property_read_u32(pdev->dev.of_node,
407 					   "xlnx,num-transfer-bits",
408 					   &bits_per_word);
409 		if (ret)
410 			bits_per_word = 8;
411 	}
412 
413 	if (!num_cs) {
414 		dev_err(&pdev->dev,
415 			"Missing slave select configuration data\n");
416 		return -EINVAL;
417 	}
418 
419 	if (num_cs > XILINX_SPI_MAX_CS) {
420 		dev_err(&pdev->dev, "Invalid number of spi slaves\n");
421 		return -EINVAL;
422 	}
423 
424 	master = spi_alloc_master(&pdev->dev, sizeof(struct xilinx_spi));
425 	if (!master)
426 		return -ENODEV;
427 
428 	/* the spi->mode bits understood by this driver: */
429 	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_LOOP |
430 			    SPI_CS_HIGH;
431 
432 	xspi = spi_master_get_devdata(master);
433 	xspi->cs_inactive = 0xffffffff;
434 	xspi->bitbang.master = master;
435 	xspi->bitbang.chipselect = xilinx_spi_chipselect;
436 	xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer;
437 	xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs;
438 	init_completion(&xspi->done);
439 
440 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
441 	xspi->regs = devm_ioremap_resource(&pdev->dev, res);
442 	if (IS_ERR(xspi->regs)) {
443 		ret = PTR_ERR(xspi->regs);
444 		goto put_master;
445 	}
446 
447 	master->bus_num = pdev->id;
448 	master->num_chipselect = num_cs;
449 	master->dev.of_node = pdev->dev.of_node;
450 
451 	/*
452 	 * Detect endianess on the IP via loop bit in CR. Detection
453 	 * must be done before reset is sent because incorrect reset
454 	 * value generates error interrupt.
455 	 * Setup little endian helper functions first and try to use them
456 	 * and check if bit was correctly setup or not.
457 	 */
458 	xspi->read_fn = xspi_read32;
459 	xspi->write_fn = xspi_write32;
460 
461 	xspi->write_fn(XSPI_CR_LOOP, xspi->regs + XSPI_CR_OFFSET);
462 	tmp = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
463 	tmp &= XSPI_CR_LOOP;
464 	if (tmp != XSPI_CR_LOOP) {
465 		xspi->read_fn = xspi_read32_be;
466 		xspi->write_fn = xspi_write32_be;
467 	}
468 
469 	master->bits_per_word_mask = SPI_BPW_MASK(bits_per_word);
470 	xspi->bytes_per_word = bits_per_word / 8;
471 	xspi->buffer_size = xilinx_spi_find_buffer_size(xspi);
472 
473 	xspi->irq = platform_get_irq(pdev, 0);
474 	if (xspi->irq < 0 && xspi->irq != -ENXIO) {
475 		ret = xspi->irq;
476 		goto put_master;
477 	} else if (xspi->irq >= 0) {
478 		/* Register for SPI Interrupt */
479 		ret = devm_request_irq(&pdev->dev, xspi->irq, xilinx_spi_irq, 0,
480 				dev_name(&pdev->dev), xspi);
481 		if (ret)
482 			goto put_master;
483 	}
484 
485 	/* SPI controller initializations */
486 	xspi_init_hw(xspi);
487 
488 	ret = spi_bitbang_start(&xspi->bitbang);
489 	if (ret) {
490 		dev_err(&pdev->dev, "spi_bitbang_start FAILED\n");
491 		goto put_master;
492 	}
493 
494 	dev_info(&pdev->dev, "at %pR, irq=%d\n", res, xspi->irq);
495 
496 	if (pdata) {
497 		for (i = 0; i < pdata->num_devices; i++)
498 			spi_new_device(master, pdata->devices + i);
499 	}
500 
501 	platform_set_drvdata(pdev, master);
502 	return 0;
503 
504 put_master:
505 	spi_master_put(master);
506 
507 	return ret;
508 }
509 
xilinx_spi_remove(struct platform_device * pdev)510 static int xilinx_spi_remove(struct platform_device *pdev)
511 {
512 	struct spi_master *master = platform_get_drvdata(pdev);
513 	struct xilinx_spi *xspi = spi_master_get_devdata(master);
514 	void __iomem *regs_base = xspi->regs;
515 
516 	spi_bitbang_stop(&xspi->bitbang);
517 
518 	/* Disable all the interrupts just in case */
519 	xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET);
520 	/* Disable the global IPIF interrupt */
521 	xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET);
522 
523 	spi_master_put(xspi->bitbang.master);
524 
525 	return 0;
526 }
527 
528 /* work with hotplug and coldplug */
529 MODULE_ALIAS("platform:" XILINX_SPI_NAME);
530 
531 static struct platform_driver xilinx_spi_driver = {
532 	.probe = xilinx_spi_probe,
533 	.remove = xilinx_spi_remove,
534 	.driver = {
535 		.name = XILINX_SPI_NAME,
536 		.of_match_table = xilinx_spi_of_match,
537 	},
538 };
539 module_platform_driver(xilinx_spi_driver);
540 
541 MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
542 MODULE_DESCRIPTION("Xilinx SPI driver");
543 MODULE_LICENSE("GPL");
544