1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2014 NVIDIA Corporation
4 */
5
6 #ifndef __SOC_TEGRA_MC_H__
7 #define __SOC_TEGRA_MC_H__
8
9 #include <linux/bits.h>
10 #include <linux/debugfs.h>
11 #include <linux/err.h>
12 #include <linux/interconnect-provider.h>
13 #include <linux/reset-controller.h>
14 #include <linux/types.h>
15
16 struct clk;
17 struct device;
18 struct page;
19
20 struct tegra_smmu_enable {
21 unsigned int reg;
22 unsigned int bit;
23 };
24
25 struct tegra_mc_timing {
26 unsigned long rate;
27
28 u32 *emem_data;
29 };
30
31 /* latency allowance */
32 struct tegra_mc_la {
33 unsigned int reg;
34 unsigned int shift;
35 unsigned int mask;
36 unsigned int def;
37 };
38
39 struct tegra_mc_client {
40 unsigned int id;
41 const char *name;
42 unsigned int swgroup;
43
44 unsigned int fifo_size;
45
46 struct tegra_smmu_enable smmu;
47 struct tegra_mc_la la;
48 };
49
50 struct tegra_smmu_swgroup {
51 const char *name;
52 unsigned int swgroup;
53 unsigned int reg;
54 };
55
56 struct tegra_smmu_group_soc {
57 const char *name;
58 const unsigned int *swgroups;
59 unsigned int num_swgroups;
60 };
61
62 struct tegra_smmu_soc {
63 const struct tegra_mc_client *clients;
64 unsigned int num_clients;
65
66 const struct tegra_smmu_swgroup *swgroups;
67 unsigned int num_swgroups;
68
69 const struct tegra_smmu_group_soc *groups;
70 unsigned int num_groups;
71
72 bool supports_round_robin_arbitration;
73 bool supports_request_limit;
74
75 unsigned int num_tlb_lines;
76 unsigned int num_asids;
77 };
78
79 struct tegra_mc;
80 struct tegra_smmu;
81 struct gart_device;
82
83 #ifdef CONFIG_TEGRA_IOMMU_SMMU
84 struct tegra_smmu *tegra_smmu_probe(struct device *dev,
85 const struct tegra_smmu_soc *soc,
86 struct tegra_mc *mc);
87 void tegra_smmu_remove(struct tegra_smmu *smmu);
88 #else
89 static inline struct tegra_smmu *
tegra_smmu_probe(struct device * dev,const struct tegra_smmu_soc * soc,struct tegra_mc * mc)90 tegra_smmu_probe(struct device *dev, const struct tegra_smmu_soc *soc,
91 struct tegra_mc *mc)
92 {
93 return NULL;
94 }
95
tegra_smmu_remove(struct tegra_smmu * smmu)96 static inline void tegra_smmu_remove(struct tegra_smmu *smmu)
97 {
98 }
99 #endif
100
101 #ifdef CONFIG_TEGRA_IOMMU_GART
102 struct gart_device *tegra_gart_probe(struct device *dev, struct tegra_mc *mc);
103 int tegra_gart_suspend(struct gart_device *gart);
104 int tegra_gart_resume(struct gart_device *gart);
105 #else
106 static inline struct gart_device *
tegra_gart_probe(struct device * dev,struct tegra_mc * mc)107 tegra_gart_probe(struct device *dev, struct tegra_mc *mc)
108 {
109 return ERR_PTR(-ENODEV);
110 }
111
tegra_gart_suspend(struct gart_device * gart)112 static inline int tegra_gart_suspend(struct gart_device *gart)
113 {
114 return -ENODEV;
115 }
116
tegra_gart_resume(struct gart_device * gart)117 static inline int tegra_gart_resume(struct gart_device *gart)
118 {
119 return -ENODEV;
120 }
121 #endif
122
123 struct tegra_mc_reset {
124 const char *name;
125 unsigned long id;
126 unsigned int control;
127 unsigned int status;
128 unsigned int reset;
129 unsigned int bit;
130 };
131
132 struct tegra_mc_reset_ops {
133 int (*hotreset_assert)(struct tegra_mc *mc,
134 const struct tegra_mc_reset *rst);
135 int (*hotreset_deassert)(struct tegra_mc *mc,
136 const struct tegra_mc_reset *rst);
137 int (*block_dma)(struct tegra_mc *mc,
138 const struct tegra_mc_reset *rst);
139 bool (*dma_idling)(struct tegra_mc *mc,
140 const struct tegra_mc_reset *rst);
141 int (*unblock_dma)(struct tegra_mc *mc,
142 const struct tegra_mc_reset *rst);
143 int (*reset_status)(struct tegra_mc *mc,
144 const struct tegra_mc_reset *rst);
145 };
146
147 #define TEGRA_MC_ICC_TAG_DEFAULT 0
148 #define TEGRA_MC_ICC_TAG_ISO BIT(0)
149
150 struct tegra_mc_icc_ops {
151 int (*set)(struct icc_node *src, struct icc_node *dst);
152 int (*aggregate)(struct icc_node *node, u32 tag, u32 avg_bw,
153 u32 peak_bw, u32 *agg_avg, u32 *agg_peak);
154 struct icc_node_data *(*xlate_extended)(struct of_phandle_args *spec,
155 void *data);
156 };
157
158 struct tegra_mc_soc {
159 const struct tegra_mc_client *clients;
160 unsigned int num_clients;
161
162 const unsigned long *emem_regs;
163 unsigned int num_emem_regs;
164
165 unsigned int num_address_bits;
166 unsigned int atom_size;
167
168 u8 client_id_mask;
169
170 const struct tegra_smmu_soc *smmu;
171
172 u32 intmask;
173
174 const struct tegra_mc_reset_ops *reset_ops;
175 const struct tegra_mc_reset *resets;
176 unsigned int num_resets;
177
178 const struct tegra_mc_icc_ops *icc_ops;
179
180 int (*init)(struct tegra_mc *mc);
181 };
182
183 struct tegra_mc {
184 struct device *dev;
185 struct tegra_smmu *smmu;
186 struct gart_device *gart;
187 void __iomem *regs;
188 struct clk *clk;
189 int irq;
190
191 const struct tegra_mc_soc *soc;
192 unsigned long tick;
193
194 struct tegra_mc_timing *timings;
195 unsigned int num_timings;
196
197 struct reset_controller_dev reset;
198
199 struct icc_provider provider;
200
201 spinlock_t lock;
202
203 struct {
204 struct dentry *root;
205 } debugfs;
206 };
207
208 int tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate);
209 unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc);
210
211 #ifdef CONFIG_TEGRA_MC
212 struct tegra_mc *devm_tegra_memory_controller_get(struct device *dev);
213 #else
214 static inline struct tegra_mc *
devm_tegra_memory_controller_get(struct device * dev)215 devm_tegra_memory_controller_get(struct device *dev)
216 {
217 return ERR_PTR(-ENODEV);
218 }
219 #endif
220
221 #endif /* __SOC_TEGRA_MC_H__ */
222