1 /* 2 * Copyright (c) 2015-2021, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_mi.h 24 //! \brief MHW interface for MI and generic flush commands across all engines 25 //! \details Impelements the functionalities common across all platforms for MHW_MI 26 //! 27 28 #ifndef __MHW_MI_H__ 29 #define __MHW_MI_H__ 30 31 class MhwCpInterface; 32 33 #include "mos_os.h" 34 #include "mhw_utilities.h" 35 #include "mhw_cp_interface.h" 36 #include "mhw_mmio.h" 37 #include "mhw_mi_itf.h" 38 39 #define MHW_MI_WATCHDOG_ENABLE_COUNTER 0x0 40 #define MHW_MI_WATCHDOG_DISABLE_COUNTER 0x1 41 #define MHW_MI_DEFAULT_WATCHDOG_THRESHOLD_IN_MS 60 42 #define MHW_MI_ENCODER_16K_WATCHDOG_THRESHOLD_IN_MS 2000 43 #define MHW_MI_ENCODER_8K_WATCHDOG_THRESHOLD_IN_MS 500 44 #define MHW_MI_ENCODER_4K_WATCHDOG_THRESHOLD_IN_MS 100 45 #define MHW_MI_ENCODER_FHD_WATCHDOG_THRESHOLD_IN_MS 50 46 #define MHW_MI_DECODER_720P_WATCHDOG_THRESHOLD_IN_MS 10 47 #define MHW_MI_DECODER_16K_WATCHDOG_THRESHOLD_IN_MS 180 48 #define MHW_MI_DECODER_16Kx16K_WATCHDOG_THRESHOLD_IN_MS 256 49 #define MHW_MI_WATCHDOG_COUNTS_PER_MILLISECOND (19200123 / 1000) // Time stamp counts per millisecond 50 51 typedef enum _MHW_COMMON_MI_ADDRESS_SHIFT 52 { 53 MHW_COMMON_MI_GENERAL_SHIFT = 2, 54 MHW_COMMON_MI_PIPE_CONTROL_SHIFT = 3, 55 MHW_COMMON_MI_FLUSH_DW_SHIFT = 3, 56 MHW_COMMON_MI_STORE_DATA_DW_SHIFT = 2, //when write DW to memory, algin with 4 bytes. 57 MHW_COMMON_MI_STORE_DATA_QW_SHIFT = 3, //when write QW to memory, algin with 8 bytes 58 MHW_COMMON_MI_CONDITIONAL_BATCH_BUFFER_END_SHIFT = 3, 59 } MHW_COMMON_MI_ADDRESS_SHIFT; 60 61 typedef enum _MHW_MI_SET_PREDICATE_ENABLE 62 { 63 MHW_MI_SET_PREDICATE_DISABLE = 0x0, 64 MHW_MI_SET_PREDICATE_ENABLE_ON_CLEAR, 65 MHW_MI_SET_PREDICATE_ENABLE_ON_SET, 66 MHW_MI_SET_PREDICATE_ENABLE_ALWAYS = 0xF, 67 } MHW_MI_SET_PREDICATE_ENABLE; 68 69 typedef enum _MHW_MI_POST_SYNC_OPERATION 70 { 71 MHW_FLUSH_NOWRITE = 0, 72 MHW_FLUSH_WRITE_IMMEDIATE_DATA = 1, 73 MHW_FLUSH_WRITE_TIMESTAMP_REG = 3 74 } MHW_MI_POST_SYNC_OPERATION; 75 76 typedef enum _MHW_COMMON_MI_ATOMIC_OPCODE 77 { 78 MHW_MI_ATOMIC_NONE = 0, 79 MHW_MI_ATOMIC_AND = 1, 80 MHW_MI_ATOMIC_OR = 2, 81 MHW_MI_ATOMIC_XOR = 3, 82 MHW_MI_ATOMIC_MOVE = 4, 83 MHW_MI_ATOMIC_INC = 5, 84 MHW_MI_ATOMIC_DEC = 6, 85 MHW_MI_ATOMIC_ADD = 7, 86 MHW_MI_ATOMIC_SUB = 8, 87 MHW_MI_ATOMIC_RSUB = 9, 88 MHW_MI_ATOMIC_IMAX = 10, 89 MHW_MI_ATOMIC_IMIN = 11, 90 MHW_MI_ATOMIC_UMAX = 12, 91 MHW_MI_ATOMIC_UMIN = 13, 92 MHW_MI_ATOMIC_CMP = 14, 93 MHW_MI_ATOMIC_MAX = 15 94 } MHW_COMMON_MI_ATOMIC_OPCODE; 95 96 typedef enum _MHW_COMMON_MI_SEMAPHORE_COMPARE_OPERATION 97 { 98 MHW_MI_SAD_GREATER_THAN_SDD = 0, 99 MHW_MI_SAD_GREATER_THAN_OR_EQUAL_SDD = 1, 100 MHW_MI_SAD_LESS_THAN_SDD = 2, 101 MHW_MI_SAD_LESS_THAN_OR_EQUAL_SDD = 3, 102 MHW_MI_SAD_EQUAL_SDD = 4, 103 MHW_MI_SAD_NOT_EQUAL_SDD = 5, 104 } MHW_COMMON_MI_SEMAPHORE_COMPARE_OPERATION; 105 106 typedef enum _MHW_MI_ALU_OPCODE 107 { 108 MHW_MI_ALU_NOOP = 0x0, 109 MHW_MI_ALU_LOAD = 0x80, 110 MHW_MI_ALU_LOADINV = 0x480, 111 MHW_MI_ALU_LOAD0 = 0x81, 112 MHW_MI_ALU_LOAD1 = 0x481, 113 MHW_MI_ALU_ADD = 0x100, 114 MHW_MI_ALU_SUB = 0x101, 115 MHW_MI_ALU_AND = 0x102, 116 MHW_MI_ALU_OR = 0x103, 117 MHW_MI_ALU_XOR = 0x104, 118 MHW_MI_ALU_STORE = 0x180, 119 MHW_MI_ALU_STOREINV = 0x580 120 } MHW_MI_ALU_OPCODE; 121 122 typedef enum _MHW_MI_ALU_REG 123 { 124 MHW_MI_ALU_GPREG0 = 0, 125 MHW_MI_ALU_GPREG1, 126 MHW_MI_ALU_GPREG2, 127 MHW_MI_ALU_GPREG3, 128 MHW_MI_ALU_GPREG4, 129 MHW_MI_ALU_GPREG5, 130 MHW_MI_ALU_GPREG6, 131 MHW_MI_ALU_GPREG7, 132 MHW_MI_ALU_GPREG8, 133 MHW_MI_ALU_GPREG9, 134 MHW_MI_ALU_GPREG10, 135 MHW_MI_ALU_GPREG11, 136 MHW_MI_ALU_GPREG12, 137 MHW_MI_ALU_GPREG13, 138 MHW_MI_ALU_GPREG14, 139 MHW_MI_ALU_GPREG15, 140 MHW_MI_ALU_SRCA = 0x20, 141 MHW_MI_ALU_SRCB = 0x21, 142 MHW_MI_ALU_ACCU = 0x31, 143 MHW_MI_ALU_ZF = 0x32, 144 MHW_MI_ALU_CF = 0x33 145 } MHW_MI_ALU_REG; 146 147 typedef enum _MHW_FLUSH_OPERATION 148 { 149 MHW_FLUSH_NONE = 0, // No flush 150 MHW_FLUSH_WRITE_CACHE, // Flush write cache 151 MHW_FLUSH_READ_CACHE, // Flush read cache 152 MHW_FLUSH_CUSTOM // Flush with custom parameters 153 } MHW_FLUSH_OPERATION; 154 155 typedef enum _MMIO_REMAP_OPERATION 156 { 157 MMIO_REMAP_OPERATION_NONE = 0, // default operation 158 CCS_HW_FRONT_END_MMIO_REMAP // Remap CCS mmio base offset 159 }MMIO_REMAP_OPERATION; 160 161 typedef struct _MHW_PIPE_CONTROL_PARAMS 162 { 163 PMOS_RESOURCE presDest; 164 uint32_t dwResourceOffset; 165 uint32_t dwDataDW1; 166 uint32_t dwDataDW2; 167 uint32_t dwFlushMode; 168 uint32_t dwPostSyncOp; 169 uint32_t bDisableCSStall : 1; 170 uint32_t bInvalidateStateCache : 1; 171 uint32_t bInvalidateConstantCache : 1; 172 uint32_t bInvalidateVFECache : 1; 173 uint32_t bInvalidateInstructionCache : 1; 174 uint32_t bFlushRenderTargetCache : 1; 175 uint32_t bTlbInvalidate : 1; 176 uint32_t bInvalidateTextureCache : 1; 177 uint32_t bGenericMediaStateClear : 1; 178 uint32_t bIndirectStatePointersDisable : 1; 179 uint32_t bHdcPipelineFlush : 1; 180 uint32_t bKernelFenceEnabled : 1; 181 } MHW_PIPE_CONTROL_PARAMS, *PMHW_PIPE_CONTROL_PARAMS; 182 183 typedef struct _MHW_MI_COPY_MEM_MEM_PARAMS 184 { 185 PMOS_RESOURCE presSrc; 186 uint32_t dwSrcOffset; 187 PMOS_RESOURCE presDst; 188 uint32_t dwDstOffset; 189 } MHW_MI_COPY_MEM_MEM_PARAMS, *PMHW_MI_COPY_MEM_MEM_PARAMS; 190 191 typedef struct _MHW_MI_STORE_REGISTER_MEM_PARAMS 192 { 193 PMOS_RESOURCE presStoreBuffer; 194 uint32_t dwOffset; 195 uint32_t dwRegister; 196 uint32_t dwOption; 197 } MHW_MI_STORE_REGISTER_MEM_PARAMS, *PMHW_MI_STORE_REGISTER_MEM_PARAMS; 198 199 typedef MHW_MI_STORE_REGISTER_MEM_PARAMS MHW_MI_LOAD_REGISTER_MEM_PARAMS, *PMHW_MI_LOAD_REGISTER_MEM_PARAMS; 200 201 typedef struct _MHW_MI_LOAD_REGISTER_REG_PARAMS 202 { 203 uint32_t dwSrcRegister; 204 uint32_t dwDstRegister; 205 } MHW_MI_LOAD_REGISTER_REG_PARAMS, *PMHW_MI_LOAD_REGISTER_REG_PARAMS; 206 207 typedef struct _MHW_MI_ALU_PARAMS 208 { 209 // DW 0 210 union 211 { 212 struct 213 { 214 uint32_t Operand2 : MOS_BITFIELD_RANGE(0, 9); // Operand-2 215 uint32_t Operand1 : MOS_BITFIELD_RANGE(10, 19); // Operand-1 216 uint32_t AluOpcode : MOS_BITFIELD_RANGE(20, 31); // ALU OPCODE 217 }; 218 uint32_t Value; 219 }; 220 } MHW_MI_ALU_PARAMS, *PMHW_MI_ALU_PARAMS; 221 222 typedef struct _MHW_MI_MATH_PARAMS 223 { 224 PMHW_MI_ALU_PARAMS pAluPayload; 225 uint32_t dwNumAluParams; 226 } MHW_MI_MATH_PARAMS, *PMHW_MI_MATH_PARAMS; 227 228 typedef struct _MHW_MI_LOAD_REGISTER_IMM_PARAMS 229 { 230 uint32_t dwRegister; 231 uint32_t dwData; 232 } MHW_MI_LOAD_REGISTER_IMM_PARAMS, *PMHW_MI_LOAD_REGISTER_IMM_PARAMS; 233 234 typedef struct _MHW_MI_CONDITIONAL_BATCH_BUFFER_END_PARAMS 235 { 236 PMOS_RESOURCE presSemaphoreBuffer; 237 uint32_t dwOffset; 238 uint32_t dwValue; 239 bool bDisableCompareMask; 240 uint32_t dwParamsType; //reserved 241 } MHW_MI_CONDITIONAL_BATCH_BUFFER_END_PARAMS, *PMHW_MI_CONDITIONAL_BATCH_BUFFER_END_PARAMS; 242 243 typedef struct _MHW_MI_STORE_DATA_PARAMS 244 { 245 PMOS_RESOURCE pOsResource; // Target OS Resource 246 uint32_t dwResourceOffset; 247 uint32_t dwValue; // Value to Write 248 } MHW_MI_STORE_DATA_PARAMS, *PMHW_MI_STORE_DATA_PARAMS; 249 250 typedef struct _MHW_MI_FLUSH_DW_PARAMS 251 { 252 PMOS_RESOURCE pOsResource; // Target OS Resource 253 uint32_t dwResourceOffset; 254 uint32_t dwDataDW1; // Value to Write 255 uint32_t dwDataDW2; 256 bool bVideoPipelineCacheInvalidate; 257 uint32_t postSyncOperation; 258 uint32_t bQWordEnable; 259 bool bEnablePPCFlush; 260 } MHW_MI_FLUSH_DW_PARAMS, *PMHW_MI_FLUSH_DW_PARAMS; 261 262 typedef struct _MHW_MI_ATOMIC_PARAMS 263 { 264 PMOS_RESOURCE pOsResource; // Target OS Resource 265 uint32_t dwResourceOffset; 266 bool bReturnData; 267 bool bInlineData; 268 uint32_t dwOperand1Data[4]; // Values to Write 269 uint32_t dwOperand2Data[4]; // Values to Write 270 uint32_t dwDataSize; 271 MHW_COMMON_MI_ATOMIC_OPCODE Operation; 272 } MHW_MI_ATOMIC_PARAMS, *PMHW_MI_ATOMIC_PARAMS; 273 274 typedef struct _MHW_MI_SEMAPHORE_WAIT_PARAMS 275 { 276 PMOS_RESOURCE presSemaphoreMem; // Semaphore memory Resource 277 uint32_t dwResourceOffset; 278 bool bRegisterPollMode; 279 bool bPollingWaitMode; 280 uint32_t dwCompareOperation; 281 uint32_t dwSemaphoreData; 282 MHW_COMMON_MI_SEMAPHORE_COMPARE_OPERATION CompareOperation; 283 }MHW_MI_SEMAPHORE_WAIT_PARAMS, *PMHW_MI_SEMAPHORE_WAIT_PARAMS; 284 285 typedef struct _MHW_MEDIA_STATE_FLUSH_PARAM 286 { 287 bool bFlushToGo; 288 uint8_t ui8InterfaceDescriptorOffset; 289 } MHW_MEDIA_STATE_FLUSH_PARAM, *PMHW_MEDIA_STATE_FLUSH_PARAM; 290 291 typedef struct _MHW_MI_FORCE_WAKEUP_PARAMS 292 { 293 uint32_t bForceMediaSlice0Awake : 1; //!< Force Media-Slice0 Awake 294 uint32_t bForceRenderAwake : 1; //!< Force Render Awake 295 uint32_t bForceMediaSlice1Awake : 1; //!< Force Media-Slice1 Awake 296 uint32_t bForceMediaSlice2Awake : 1; //!< Force Media-Slice2 Awake 297 uint32_t bForceMediaSlice3Awake : 1; //!< Force Media-Slice3 Awake 298 uint32_t Reserved5 : 3; //!< Reserved 299 uint32_t bHEVCPowerWellControl : 1; //!< HEVC Power Well Control 300 uint32_t bMFXPowerWellControl : 1; //!< MFX Power Well Control 301 uint32_t Reserved10 : 6; //!< Reserved 302 uint32_t bForceMediaSlice0AwakeMask : 1; //!< Force Media-Slice0 Awake Mask 303 uint32_t bForceRenderAwakeMask : 1; //!< Force Render Awake Mask 304 uint32_t bForceMediaSlice1AwakeMask : 1; //!< Force Media-Slice1 Awake Mask 305 uint32_t bForceMediaSlice2AwakeMask : 1; //!< Force Media-Slice2 Awake Mask 306 uint32_t bForceMediaSlice3AwakeMask : 1; //!< Force Media-Slice3 Awake Mask 307 uint32_t ReservedMask23_21 : 3; //!< Reserved Mask 308 uint32_t bHEVCPowerWellControlMask : 1; //!< HEVC Power Well Control Mask 309 uint32_t bMFXPowerWellControlMask : 1; //!< MFX Power Well Control Mask 310 uint32_t Reserved31_26 : 6; //!< Reserved Mask 311 } MHW_MI_FORCE_WAKEUP_PARAMS, *PMHW_MI_FORCE_WAKEUP_PARAMS; 312 313 typedef struct _MHW_MI_VD_CONTROL_STATE_PARAMS 314 { 315 bool vdencEnabled; 316 bool avpEnabled; 317 bool initialization; 318 bool vdencInitialization; 319 bool scalableModePipeLock; 320 bool scalableModePipeUnlock; 321 bool memoryImplicitFlush; 322 } MHW_MI_VD_CONTROL_STATE_PARAMS, *PMHW_MI_VD_CONTROL_STATE_PARAMS; 323 324 class MhwMiInterface 325 { 326 public: ~MhwMiInterface()327 virtual ~MhwMiInterface() { MHW_FUNCTION_ENTER; } 328 329 //! 330 //! \brief Adds MI_NOOP_CMD to the buffer provided 331 //! \details Either the command or batch buffer must be valid 332 //! \param [in] cmdBuffer 333 //! If valid, command buffer to which HW command is added 334 //! \param [in] batchBuffer 335 //! If valid, batch buffer to which HW command is added 336 //! \return MOS_STATUS 337 //! MOS_STATUS_SUCCESS if success, else fail reason 338 //! 339 virtual MOS_STATUS AddMiNoop( 340 PMOS_COMMAND_BUFFER cmdBuffer, 341 PMHW_BATCH_BUFFER batchBuffer) = 0; 342 343 //! 344 //! \brief Adds MI_BATCH_BUFFER_END to the buffer provided 345 //! \details Either the command or batch buffer must be valid 346 //! \param [in] cmdBuffer 347 //! If valid, command buffer to which HW command is added 348 //! \param [in] batchBuffer 349 //! If valid, batch buffer to which HW command is added 350 //! \return MOS_STATUS 351 //! MOS_STATUS_SUCCESS if success, else fail reason 352 //! 353 virtual MOS_STATUS AddMiBatchBufferEnd( 354 PMOS_COMMAND_BUFFER cmdBuffer, 355 PMHW_BATCH_BUFFER batchBuffer) = 0; 356 357 //! 358 //! \brief Add batch buffer end insertion flag 359 //! 360 //! \param [in/out] constructedCmdBuf 361 //! Constructed cmd buffer 362 //! 363 //! \return MOS_STATUS 364 //! MOS_STATUS_SUCCESS if success, else fail reason 365 //! 366 virtual MOS_STATUS AddBatchBufferEndInsertionFlag( 367 MOS_COMMAND_BUFFER &constructedCmdBuf) = 0; 368 369 //! 370 //! \brief Adds MI_BATCH_BUFFER_END to the buffer provided without any WA 371 //! \details Either the command or batch buffer must be valid 372 //! \param [in] cmdBuffer 373 //! If valid, command buffer to which HW command is added 374 //! \param [in] batchBuffer 375 //! If valid, batch buffer to which HW command is added 376 //! \return MOS_STATUS 377 //! MOS_STATUS_SUCCESS if success, else fail reason 378 //! 379 virtual MOS_STATUS AddMiBatchBufferEndOnly( 380 PMOS_COMMAND_BUFFER cmdBuffer, 381 PMHW_BATCH_BUFFER batchBuffer) = 0; 382 383 //! 384 //! \brief Adds MI_CONDITIONAL_BATCH_BUFFER_END to the command buffer 385 //! \param [in] cmdBuffer 386 //! Command buffer to which requested command is added 387 //! \param [in] params 388 //! Parameters used to populate the requested command 389 //! \return MOS_STATUS 390 //! MOS_STATUS_SUCCESS if success, else fail reason 391 //! 392 virtual MOS_STATUS AddMiConditionalBatchBufferEndCmd( 393 PMOS_COMMAND_BUFFER cmdBuffer, 394 PMHW_MI_CONDITIONAL_BATCH_BUFFER_END_PARAMS params) = 0; 395 396 //! 397 //! \brief Adds MI_BATCH_BUFFER_START to the command buffer 398 //! \param [in] cmdBuffer 399 //! Command buffer to which requested command is added 400 //! \param [in] batchBuffer 401 //! Batch buffer to refer to in MI_BATCH_BUFFER_START 402 //! \return MOS_STATUS 403 //! MOS_STATUS_SUCCESS if success, else fail reason 404 //! 405 virtual MOS_STATUS AddMiBatchBufferStartCmd( 406 PMOS_COMMAND_BUFFER cmdBuffer, 407 PMHW_BATCH_BUFFER batchBuffer) = 0; 408 409 //! 410 //! \brief Adds MI_STORE_DATA_IMM to the command buffer 411 //! \param [in] cmdBuffer 412 //! Command buffer to which requested command is added 413 //! \param [in] params 414 //! Parameters used to populate the requested command 415 //! \return MOS_STATUS 416 //! MOS_STATUS_SUCCESS if success, else fail reason 417 //! 418 virtual MOS_STATUS AddMiStoreDataImmCmd( 419 PMOS_COMMAND_BUFFER cmdBuffer, 420 PMHW_MI_STORE_DATA_PARAMS params) = 0; 421 422 //! 423 //! \brief Adds MI_FLUSH_DW to the command buffer 424 //! \param [in] cmdBuffer 425 //! Command buffer to which requested command is added 426 //! \param [in] params 427 //! Parameters used to populate the requested command 428 //! \return MOS_STATUS 429 //! MOS_STATUS_SUCCESS if success, else fail reason 430 //! 431 virtual MOS_STATUS AddMiFlushDwCmd( 432 PMOS_COMMAND_BUFFER cmdBuffer, 433 PMHW_MI_FLUSH_DW_PARAMS params) = 0; 434 435 //! 436 //! \brief Adds MI_FORCE_WAKEUP to the command buffer 437 //! \param [in] cmdBuffer 438 //! Command buffer to which requested command is added 439 //! \param [in] params 440 //! Parameters used to populate the requested command 441 //! \return MOS_STATUS 442 //! MOS_STATUS_SUCCESS if success, else fail reason 443 //! AddMiForceWakeupCmd(PMOS_COMMAND_BUFFER cmdBuffer,PMHW_MI_FORCE_WAKEUP_PARAMS params)444 virtual MOS_STATUS AddMiForceWakeupCmd( 445 PMOS_COMMAND_BUFFER cmdBuffer, 446 PMHW_MI_FORCE_WAKEUP_PARAMS params) 447 { 448 return MOS_STATUS_SUCCESS; 449 }; 450 451 //! 452 //! \brief Adds MI_COPY_MEM_MEM to the command buffer 453 //! \param [in] cmdBuffer 454 //! Command buffer to which requested command is added 455 //! \param [in] params 456 //! Parameters used to populate the requested command 457 //! \return MOS_STATUS 458 //! MOS_STATUS_SUCCESS if success, else fail reason 459 //! 460 virtual MOS_STATUS AddMiCopyMemMemCmd( 461 PMOS_COMMAND_BUFFER cmdBuffer, 462 PMHW_MI_COPY_MEM_MEM_PARAMS params) = 0; 463 464 //! 465 //! \brief Adds MI_STORE_REGISTER_MEM to the command buffer 466 //! \param [in] cmdBuffer 467 //! Command buffer to which requested command is added 468 //! \param [in] params 469 //! Parameters used to populate the requested command 470 //! \return MOS_STATUS 471 //! MOS_STATUS_SUCCESS if success, else fail reason 472 //! 473 virtual MOS_STATUS AddMiStoreRegisterMemCmd( 474 PMOS_COMMAND_BUFFER cmdBuffer, 475 PMHW_MI_STORE_REGISTER_MEM_PARAMS params) = 0; 476 477 //! 478 //! \brief Adds MI_LOAD_REGISTER_MEM to the command buffer 479 //! \param [in] cmdBuffer 480 //! Command buffer to which requested command is added 481 //! \param [in] params 482 //! Parameters used to populate the requested command 483 //! \return MOS_STATUS 484 //! MOS_STATUS_SUCCESS if success, else fail reason 485 //! 486 virtual MOS_STATUS AddMiLoadRegisterMemCmd( 487 PMOS_COMMAND_BUFFER cmdBuffer, 488 PMHW_MI_STORE_REGISTER_MEM_PARAMS params) = 0; 489 490 //! 491 //! \brief Adds MI_LOAD_REGISTER_IMM to the command buffer 492 //! \param [in] cmdBuffer 493 //! Command buffer to which requested command is added 494 //! \param [in] params 495 //! Parameters used to populate the requested command 496 //! \return MOS_STATUS 497 //! MOS_STATUS_SUCCESS if success, else fail reason 498 //! 499 virtual MOS_STATUS AddMiLoadRegisterImmCmd( 500 PMOS_COMMAND_BUFFER cmdBuffer, 501 PMHW_MI_LOAD_REGISTER_IMM_PARAMS params) = 0; 502 503 //! 504 //! \brief Adds MI_LOAD_REGISTER_REG to the command buffer 505 //! \param [in] cmdBuffer 506 //! Command buffer to which requested command is added 507 //! \param [in] params 508 //! Parameters used to populate the requested command 509 //! \return MOS_STATUS 510 //! MOS_STATUS_SUCCESS if success, else fail reason 511 //! 512 virtual MOS_STATUS AddMiLoadRegisterRegCmd( 513 PMOS_COMMAND_BUFFER cmdBuffer, 514 PMHW_MI_LOAD_REGISTER_REG_PARAMS params) = 0; 515 516 //! 517 //! \brief Adds MI_MATH to the command buffer 518 //! \details MI_MATH is a variable length command requiring the ALU payload 519 //! for completion. 520 //! \param [in] cmdBuffer 521 //! Command buffer to which requested command is added 522 //! \param [in] params 523 //! Parameters used to populate the requested command 524 //! \return MOS_STATUS 525 //! MOS_STATUS_SUCCESS if success, else fail reason 526 //! 527 virtual MOS_STATUS AddMiMathCmd( 528 PMOS_COMMAND_BUFFER cmdBuffer, 529 PMHW_MI_MATH_PARAMS params) = 0; 530 531 //! 532 //! \brief Adds MI_SET_PREDICATE to the command buffer 533 //! for completion. 534 //! \param [in] cmdBuffer 535 //! Command buffer to which requested command is added 536 //! \param [in] params 537 //! Parameters used to populate the requested command 538 //! \return MOS_STATUS 539 //! MOS_STATUS_SUCCESS if success, else fail reason 540 //! 541 virtual MOS_STATUS AddMiSetPredicateCmd( 542 PMOS_COMMAND_BUFFER cmdBuffer, 543 MHW_MI_SET_PREDICATE_ENABLE enableFlag) = 0; 544 545 //! 546 //! \brief Adds MI_ATOMIC to the command buffer 547 //! \param [in] cmdBuffer 548 //! Command buffer to which requested command is added 549 //! \param [in] params 550 //! Parameters used to populate the requested command 551 //! \return MOS_STATUS 552 //! MOS_STATUS_SUCCESS if success, else fail reason 553 //! 554 virtual MOS_STATUS AddMiAtomicCmd( 555 PMOS_COMMAND_BUFFER cmdBuffer, 556 PMHW_MI_ATOMIC_PARAMS params) = 0; 557 558 //! 559 //! \brief Adds MI_SEMAPHORE_WAIT to the command buffer 560 //! \param [in] cmdBuffer 561 //! Command buffer to which requested command is added 562 //! \param [in] params 563 //! Parameters used to populate the requested command 564 //! \return MOS_STATUS 565 //! MOS_STATUS_SUCCESS if success, else fail reason 566 //! 567 virtual MOS_STATUS AddMiSemaphoreWaitCmd( 568 PMOS_COMMAND_BUFFER cmdBuffer, 569 PMHW_MI_SEMAPHORE_WAIT_PARAMS params) = 0; 570 571 //! 572 //! \brief Adds MI_ARB_CHECK to the command buffer 573 //! \param [in] cmdBuffer 574 //! Command buffer to which requested command is added 575 //! \return MOS_STATUS 576 //! MOS_STATUS_SUCCESS if success, else fail reason 577 //! 578 virtual MOS_STATUS AddMiArbCheckCmd( 579 PMOS_COMMAND_BUFFER cmdBuffer) = 0; 580 581 //! 582 //! \brief Adds PIPE_CONTROL to the command buffer 583 //! \details Although this function is not an MI function, all flushses are part of 584 //! the common MI interface, either the command or batch buffer must be valid 585 //! \param [in] cmdBuffer 586 //! Command buffer to which HW command is added, if valid batchBuffer should be null 587 //! \param [in] batchBuffer 588 //! Batch buffer to which HW command is added, if valid cmdBuffer should be null 589 //! \param [in] params 590 //! Parameters used to populate the requested command 591 //! \return MOS_STATUS 592 //! MOS_STATUS_SUCCESS if success, else fail reason 593 //! 594 virtual MOS_STATUS AddPipeControl( 595 PMOS_COMMAND_BUFFER cmdBuffer, 596 PMHW_BATCH_BUFFER batchBuffer, 597 PMHW_PIPE_CONTROL_PARAMS params) = 0; 598 599 //! 600 //! \brief Adds MFX_WAIT_CMD to the buffer provided 601 //! \details Either the command or batch buffer must be valid 602 //! \param [in] cmdBuffer 603 //! If valid, command buffer to which command are added 604 //! \param [in] batchBuffer 605 //! If valid, batch buffer to which the command is added 606 //! \param [in] stallVdboxPipeline 607 //! Indicates whether or not the MFX_WAIT will wait on VDBOX pipelines (HuC/HCP/MFX) 608 //! \return MOS_STATUS 609 //! MOS_STATUS_SUCCESS if success, else fail reason 610 //! 611 virtual MOS_STATUS AddMfxWaitCmd( 612 PMOS_COMMAND_BUFFER cmdBuffer, 613 PMHW_BATCH_BUFFER batchBuffer, 614 bool stallVdboxPipeline) = 0; 615 616 //! 617 //! \brief Adds MEDIA_STATE_FLUSH to valid buffer provided 618 //! \details Client facing function to add MEDIA_STATE_FLUSH to either the 619 //! command buffer or batch buffer (whichever is valid) 620 //! \param [in] cmdBuffer 621 //! If valid, command buffer to which HW command is added 622 //! \param [in] batchBuffer 623 //! If valid, Batch buffer to which HW command is added 624 //! \param [in] params 625 //! Parameters used to populate the requested command, may be nullptr if not needed 626 //! \return MOS_STATUS 627 //! MOS_STATUS_SUCCESS if success, else fail reason 628 //! 629 virtual MOS_STATUS AddMediaStateFlush( 630 PMOS_COMMAND_BUFFER cmdBuffer, 631 PMHW_BATCH_BUFFER batchBuffer, 632 PMHW_MEDIA_STATE_FLUSH_PARAM params = nullptr) = 0; 633 634 //! 635 //! \brief Skips batch buffer end command in a batch buffer 636 //! \details Inserts the space equivalent to what would have been inserted during 637 //! AddBatchBufferEnd to the batch buffer provided. 638 //! \param [in] batchBuffer 639 //! Batch buffer which HW command is skipped 640 //! \return MOS_STATUS 641 //! MOS_STATUS_SUCCESS if success, else fail reason 642 //! 643 virtual MOS_STATUS SkipMiBatchBufferEndBb( 644 PMHW_BATCH_BUFFER batchBuffer) = 0; 645 646 //! 647 //! \brief Adds prolog for protected content 648 //! \param [in] cmdBuffer 649 //! Command buffer into which prolog is inserted 650 //! \return MOS_STATUS 651 //! MOS_STATUS_SUCCESS if success, else fail reason 652 //! 653 MOS_STATUS AddProtectedProlog(MOS_COMMAND_BUFFER *cmdBuffer); 654 655 //! 656 //! \brief Get mmio registers address 657 //! \details Get mmio registers address 658 //! \return [out] PMHW_MI_MMIOREGISTERS* 659 //! mmio registers got. 660 //! GetMmioRegisters()661 inline PMHW_MI_MMIOREGISTERS GetMmioRegisters() 662 { 663 return &m_mmioRegisters; 664 } 665 666 //! 667 //! \brief get the size of hw command 668 //! \details Internal function to get the size of MI_FLUSH_DW_CMD 669 //! \return commandSize 670 //! The command size 671 //! 672 virtual uint32_t GetMiFlushDwCmdSize() = 0; 673 674 //! 675 //! \brief get the size of hw command 676 //! \details Internal function to get the size of MI_BATCH_BUFFER_START_CMD 677 //! \return commandSize 678 //! The command size 679 //! 680 virtual uint32_t GetMiBatchBufferStartCmdSize() = 0; 681 682 //! 683 //! \brief get the size of hw command 684 //! \details Internal function to get the size of MI_BATCH_BUFFER_END_CMD 685 //! \return commandSize 686 //! The command size 687 //! 688 virtual uint32_t GetMiBatchBufferEndCmdSize() = 0; 689 690 //! 691 //! \brief Set Watchdog Timer Threshold 692 //! \details Set Watchdog Timer Threshold 693 //! \return MOS_STATUS 694 //! MOS_STATUS_SUCCESS if success, else fail reason 695 //! 696 virtual MOS_STATUS SetWatchdogTimerThreshold(uint32_t frameWidth, uint32_t frameHeight, bool isEncoder = true) = 0; 697 698 //! 699 //! \brief Set Watchdog Timer Register Offset 700 //! \details Set Watchdog Timer Register Offset 701 //! \return MOS_STATUS 702 //! MOS_STATUS_SUCCESS if success, else fail reason 703 //! 704 virtual MOS_STATUS SetWatchdogTimerRegisterOffset(MOS_GPU_CONTEXT gpuContext) = 0; 705 706 //! 707 //! \brief Add Watchdog Timer Start Cmd 708 //! \details Add Watchdog Timer Start Cmd 709 //! \return MOS_STATUS 710 //! MOS_STATUS_SUCCESS if success, else fail reason 711 //! 712 virtual MOS_STATUS AddWatchdogTimerStartCmd(PMOS_COMMAND_BUFFER cmdBuffer) = 0; 713 714 //! 715 //! \brief Add Watchdog Timer Stop Cmd 716 //! \details Add Watchdog Timer Stop Cmd 717 //! \return MOS_STATUS 718 //! MOS_STATUS_SUCCESS if success, else fail reason 719 //! 720 virtual MOS_STATUS AddWatchdogTimerStopCmd(PMOS_COMMAND_BUFFER cmdBuffer) = 0; 721 722 //! 723 //! \brief Adds Mi Vd control state cmd in command buffer 724 //! 725 //! \param [in] cmdBuffer 726 //! Command buffer to which HW command is added 727 //! \param [in] params 728 //! Params structure used to populate the HW command 729 //! 730 //! \return MOS_STATUS 731 //! MOS_STATUS_SUCCESS if success, else fail reason 732 //! AddMiVdControlStateCmd(PMOS_COMMAND_BUFFER cmdBuffer,PMHW_MI_VD_CONTROL_STATE_PARAMS params)733 virtual MOS_STATUS AddMiVdControlStateCmd( 734 PMOS_COMMAND_BUFFER cmdBuffer, 735 PMHW_MI_VD_CONTROL_STATE_PARAMS params) 736 { 737 return MOS_STATUS_SUCCESS; 738 }; 739 740 //! 741 //! \brief Get new render interface, temporal solution before switching from 742 //! old interface to new one 743 //! 744 //! \return pointer to new render interface 745 //! GetNewMiInterface()746 virtual std::shared_ptr<void> GetNewMiInterface() { return nullptr; } 747 748 protected: 749 //! 750 //! \brief Initializes the MI interface 751 //! \details Internal MHW function to initialize all function pointers and some parameters 752 //! Assumes that the caller has checked pointer validity and whether or not an 753 //! addressing method has been selected in the OS interface (bUsesGfxAddress or 754 //! bUsesPatchList). 755 //! \param [in] pCpInterface 756 //! CP interface, must be valid 757 //! \param [in] pOsInterface 758 //! OS interface, must be valid 759 //! 760 MhwMiInterface( 761 MhwCpInterface *cpInterface, 762 PMOS_INTERFACE osInterface); 763 764 //! 765 //! \brief Adds a resource to the command buffer or indirect state (SSH) 766 //! \details Internal MHW function to add either a graphics address of a resource or 767 //! add the resource to the patch list for the requested buffer or state 768 //! \param [in] pOsInterface 769 //! OS interface 770 //! \param [in] cmdBuffer 771 //! If adding a resource to the command buffer, the buffer to which the resource 772 //! is added 773 //! \param [in] params 774 //! Parameters necessary to add the graphics address 775 //! \return MOS_STATUS 776 //! MOS_STATUS_SUCCESS if success, else fail reason 777 //! 778 MOS_STATUS (*AddResourceToCmd) ( 779 PMOS_INTERFACE pOsInterface, 780 PMOS_COMMAND_BUFFER cmdBuffer, 781 PMHW_RESOURCE_PARAMS params) = nullptr; 782 783 //! 784 //! \brief Helper function to get GTT type (PGTT or GGTT) 785 //! \return bool 786 //! true for GGTT, false for PPGTT 787 //! 788 bool IsGlobalGttInUse(); 789 790 void GetWatchdogThreshold(PMOS_INTERFACE osInterface); 791 792 MhwCpInterface *m_cpInterface = nullptr; //!< Responsible for CP functionality 793 PMOS_INTERFACE m_osInterface = nullptr; //!< Responsible for interaction with OS 794 795 //! \brief Indicates the global GTT setting on each engine. 796 struct 797 { 798 uint8_t m_cs : 1; //!< GGTT in use for the render engine. 799 uint8_t m_vcs : 1; //!< GGTT in use for VDBOX. 800 uint8_t m_vecs : 1; //!< GGTT in use for VEBOX. 801 } UseGlobalGtt; 802 803 //! \brief Indicates the MediaReset Parameter. 804 struct 805 { 806 uint32_t watchdogCountThreshold; 807 uint32_t watchdogCountCtrlOffset; 808 uint32_t watchdogCountThresholdOffset; 809 } MediaResetParam; 810 811 //! \brief Mmio registers address 812 MHW_MI_MMIOREGISTERS m_mmioRegisters = {}; //!< mfx mmio registers 813 814 std::shared_ptr<void> m_miItfNew = nullptr; 815 }; 816 817 #endif // __MHW_MI_H__ 818