1 /*===================== begin_copyright_notice ================================== 2 3 # Copyright (c) 2020-2021, Intel Corporation 4 5 # Permission is hereby granted, free of charge, to any person obtaining a 6 # copy of this software and associated documentation files (the "Software"), 7 # to deal in the Software without restriction, including without limitation 8 # the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 # and/or sell copies of the Software, and to permit persons to whom the 10 # Software is furnished to do so, subject to the following conditions: 11 12 # The above copyright notice and this permission notice shall be included 13 # in all copies or substantial portions of the Software. 14 15 # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 16 # OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 # OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 # ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 # OTHER DEALINGS IN THE SOFTWARE. 22 23 ======================= end_copyright_notice ==================================*/ 24 //! 25 //! \file mhw_sfc_hwcmd_xe_xpm.h 26 //! \brief Auto-generated constructors for MHW and states. 27 //! \details This file may not be included outside of g12_X as other components 28 //! should use MHW interface to interact with MHW commands and states. 29 //! 30 31 // DO NOT EDIT 32 33 #ifndef __MHW_SFC_HWCMD_XE_XPM_H__ 34 #define __MHW_SFC_HWCMD_XE_XPM_H__ 35 36 #pragma once 37 #pragma pack(1) 38 39 #include <cstdint> 40 #include <cstddef> 41 42 class mhw_sfc_xe_xpm 43 { 44 public: 45 // Internal Macros 46 #define __CODEGEN_MAX(_a, _b) (((_a) > (_b)) ? (_a) : (_b)) 47 #define __CODEGEN_BITFIELD(l, h) (h) - (l) + 1 48 #define __CODEGEN_OP_LENGTH_BIAS 2 49 #define __CODEGEN_OP_LENGTH(x) (uint32_t)((__CODEGEN_MAX(x, __CODEGEN_OP_LENGTH_BIAS)) - __CODEGEN_OP_LENGTH_BIAS) 50 GetOpLength(uint32_t uiLength)51 static uint32_t GetOpLength(uint32_t uiLength) { return __CODEGEN_OP_LENGTH(uiLength); } 52 53 //! 54 //! \brief SFC_AVS_STATE 55 //! \details 56 //! This command is sent from VDBOX/VEBOX to SFC pipeline at the start of 57 //! each frame once the lock request is granted. 58 //! 59 struct SFC_AVS_STATE_CMD 60 { 61 union 62 { 63 struct 64 { 65 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 66 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 67 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODEB 68 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPCODEA 69 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_COMMAND_OPCODE 70 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 71 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 72 }; 73 uint32_t Value; 74 } DW0; 75 union 76 { 77 struct 78 { 79 uint32_t TransitionAreaWith8Pixels : __CODEGEN_BITFIELD( 0, 2) ; //!< Transition Area with 8 Pixels 80 uint32_t Reserved35 : __CODEGEN_BITFIELD( 3, 3) ; //!< Reserved 81 uint32_t TransitionAreaWith4Pixels : __CODEGEN_BITFIELD( 4, 6) ; //!< Transition Area with 4 Pixels 82 uint32_t Reserved39 : __CODEGEN_BITFIELD( 7, 23) ; //!< Reserved 83 uint32_t SharpnessLevel : __CODEGEN_BITFIELD(24, 31) ; //!< SHARPNESS_LEVEL 84 }; 85 uint32_t Value; 86 } DW1; 87 union 88 { 89 struct 90 { 91 uint32_t MaxDerivativePoint8 : __CODEGEN_BITFIELD( 0, 7) ; //!< MAX Derivative Point 8 92 uint32_t Reserved72 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 93 uint32_t MaxDerivative4Pixels : __CODEGEN_BITFIELD(16, 23) ; //!< Max Derivative 4 Pixels 94 uint32_t Reserved88 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 95 }; 96 uint32_t Value; 97 } DW2; 98 union 99 { 100 struct 101 { 102 uint32_t InputVerticalSitingSpecifiesTheVerticalSitingOfTheInput : __CODEGEN_BITFIELD( 0, 3) ; //!< INPUT_VERTICAL_SITING_SPECIFIES_THE_VERTICAL_SITING_OF_THE_INPUT 103 uint32_t Reserved100 : __CODEGEN_BITFIELD( 4, 7) ; //!< Reserved 104 uint32_t InputHorizontalSitingValueSpecifiesTheHorizontalSitingOfTheInput : __CODEGEN_BITFIELD( 8, 12) ; //!< Input Horizontal Siting Value - Specifies the horizontal siting of the input 105 uint32_t Reserved109 : __CODEGEN_BITFIELD(13, 31) ; //!< Reserved 106 }; 107 uint32_t Value; 108 } DW3; 109 110 //! \name Local enumerations 111 112 enum SUBOPCODEB 113 { 114 SUBOPCODEB_SFCAVSSTATE = 2, //!< No additional details 115 }; 116 117 enum SUBOPCODEA 118 { 119 SUBOPCODEA_COMMON = 0, //!< No additional details 120 }; 121 122 enum MEDIA_COMMAND_OPCODE 123 { 124 MEDIA_COMMAND_OPCODE_MEDIAMISC = 10, //!< Media MFX/VEBOX+SFC Modegen 125 }; 126 127 enum PIPELINE 128 { 129 PIPELINE_MEDIA = 2, //!< No additional details 130 }; 131 132 enum COMMAND_TYPE 133 { 134 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 135 }; 136 137 //! \brief SHARPNESS_LEVEL 138 //! \details 139 //! When adaptive scaling is off, determines the balance between sharp and 140 //! smooth scalers. 141 enum SHARPNESS_LEVEL 142 { 143 SHARPNESS_LEVEL_UNNAMED0 = 0, //!< Contribute 1 from the smooth scalar 144 SHARPNESS_LEVEL_UNNAMED255 = 255, //!< Contribute 1 from the sharp scalar 145 }; 146 147 //! \brief INPUT_VERTICAL_SITING_SPECIFIES_THE_VERTICAL_SITING_OF_THE_INPUT 148 //! \details 149 //! For 444 and 422 format, vertical chroma siting should be programmed to 150 //! zero. 151 enum INPUT_VERTICAL_SITING_SPECIFIES_THE_VERTICAL_SITING_OF_THE_INPUT 152 { 153 INPUT_VERTICAL_SITING_SPECIFIES_THE_VERTICAL_SITING_OF_THE_INPUT_0 = 0, //!< No additional details 154 INPUT_VERTICAL_SITING_SPECIFIES_THE_VERTICAL_SITING_OF_THE_INPUT_18 = 1, //!< No additional details 155 INPUT_VERTICAL_SITING_SPECIFIES_THE_VERTICAL_SITING_OF_THE_INPUT_28 = 2, //!< No additional details 156 INPUT_VERTICAL_SITING_SPECIFIES_THE_VERTICAL_SITING_OF_THE_INPUT_38 = 3, //!< No additional details 157 INPUT_VERTICAL_SITING_SPECIFIES_THE_VERTICAL_SITING_OF_THE_INPUT_48 = 4, //!< No additional details 158 INPUT_VERTICAL_SITING_SPECIFIES_THE_VERTICAL_SITING_OF_THE_INPUT_58 = 5, //!< No additional details 159 INPUT_VERTICAL_SITING_SPECIFIES_THE_VERTICAL_SITING_OF_THE_INPUT_68 = 6, //!< No additional details 160 INPUT_VERTICAL_SITING_SPECIFIES_THE_VERTICAL_SITING_OF_THE_INPUT_78 = 7, //!< No additional details 161 INPUT_VERTICAL_SITING_SPECIFIES_THE_VERTICAL_SITING_OF_THE_INPUT_88 = 8, //!< No additional details 162 }; 163 164 //! \name Initializations 165 166 //! \brief Explicit member initialization function 167 SFC_AVS_STATE_CMD(); 168 169 static const size_t dwSize = 4; 170 static const size_t byteSize = 16; 171 }; 172 173 //! 174 //! \brief SFC_IEF_STATE 175 //! \details 176 //! This command is sent from VDBOX/VEBOX to SFC pipeline at the start of 177 //! each frame once the lock request is granted. 178 //! 179 struct SFC_IEF_STATE_CMD 180 { 181 union 182 { 183 struct 184 { 185 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 186 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 187 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODEB 188 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPCODEA 189 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_COMMAND_OPCODE 190 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 191 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 192 }; 193 uint32_t Value; 194 } DW0; 195 union 196 { 197 struct 198 { 199 uint32_t GainFactor : __CODEGEN_BITFIELD( 0, 5) ; //!< GAIN_FACTOR 200 uint32_t WeakEdgeThreshold : __CODEGEN_BITFIELD( 6, 11) ; //!< WEAK_EDGE_THRESHOLD 201 uint32_t StrongEdgeThreshold : __CODEGEN_BITFIELD(12, 17) ; //!< STRONG_EDGE_THRESHOLD 202 uint32_t R3XCoefficient : __CODEGEN_BITFIELD(18, 22) ; //!< R3X_COEFFICIENT 203 uint32_t R3CCoefficient : __CODEGEN_BITFIELD(23, 27) ; //!< R3C_COEFFICIENT 204 uint32_t Reserved60 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 205 }; 206 uint32_t Value; 207 } DW1; 208 union 209 { 210 struct 211 { 212 uint32_t GlobalNoiseEstimation : __CODEGEN_BITFIELD( 0, 7) ; //!< GLOBAL_NOISE_ESTIMATION 213 uint32_t NonEdgeWeight : __CODEGEN_BITFIELD( 8, 10) ; //!< NON_EDGE_WEIGHT 214 uint32_t RegularWeight : __CODEGEN_BITFIELD(11, 13) ; //!< REGULAR_WEIGHT 215 uint32_t StrongEdgeWeight : __CODEGEN_BITFIELD(14, 16) ; //!< STRONG_EDGE_WEIGHT 216 uint32_t R5XCoefficient : __CODEGEN_BITFIELD(17, 21) ; //!< R5X_COEFFICIENT 217 uint32_t R5CxCoefficient : __CODEGEN_BITFIELD(22, 26) ; //!< R5CX_COEFFICIENT 218 uint32_t R5CCoefficient : __CODEGEN_BITFIELD(27, 31) ; //!< R5C_COEFFICIENT 219 }; 220 uint32_t Value; 221 } DW2; 222 union 223 { 224 struct 225 { 226 uint32_t StdSinAlpha : __CODEGEN_BITFIELD( 0, 7) ; //!< STD Sin(alpha) 227 uint32_t StdCosAlpha : __CODEGEN_BITFIELD( 8, 15) ; //!< STD Cos(alpha) 228 uint32_t SatMax : __CODEGEN_BITFIELD(16, 21) ; //!< SAT_MAX 229 uint32_t HueMax : __CODEGEN_BITFIELD(22, 27) ; //!< HUE_MAX 230 uint32_t Reserved124 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 231 }; 232 uint32_t Value; 233 } DW3; 234 union 235 { 236 struct 237 { 238 uint32_t S3U : __CODEGEN_BITFIELD( 0, 10) ; //!< S3U 239 uint32_t Reserved139 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 240 uint32_t DiamondMargin : __CODEGEN_BITFIELD(12, 14) ; //!< DIAMOND_MARGIN 241 uint32_t VyStdEnable : __CODEGEN_BITFIELD(15, 15) ; //!< VY_STD_Enable 242 uint32_t UMid : __CODEGEN_BITFIELD(16, 23) ; //!< U_MID 243 uint32_t VMid : __CODEGEN_BITFIELD(24, 31) ; //!< V_MID 244 }; 245 uint32_t Value; 246 } DW4; 247 union 248 { 249 struct 250 { 251 uint32_t DiamondDv : __CODEGEN_BITFIELD( 0, 6) ; //!< DIAMOND_DV 252 uint32_t DiamondTh : __CODEGEN_BITFIELD( 7, 12) ; //!< DIAMOND_TH 253 uint32_t DiamondAlpha : __CODEGEN_BITFIELD(13, 20) ; //!< Diamond_alpha 254 uint32_t HsMargin : __CODEGEN_BITFIELD(21, 23) ; //!< HS_MARGIN 255 uint32_t DiamondDu : __CODEGEN_BITFIELD(24, 30) ; //!< DIAMOND_DU 256 uint32_t SkinDetailFactor : __CODEGEN_BITFIELD(31, 31) ; //!< SKIN_DETAIL_FACTOR 257 }; 258 uint32_t Value; 259 } DW5; 260 union 261 { 262 struct 263 { 264 uint32_t YPoint1 : __CODEGEN_BITFIELD( 0, 7) ; //!< Y_POINT_1 265 uint32_t YPoint2 : __CODEGEN_BITFIELD( 8, 15) ; //!< Y_POINT_2 266 uint32_t YPoint3 : __CODEGEN_BITFIELD(16, 23) ; //!< Y_POINT_3 267 uint32_t YPoint4 : __CODEGEN_BITFIELD(24, 31) ; //!< Y_POINT_4 268 }; 269 uint32_t Value; 270 } DW6; 271 union 272 { 273 struct 274 { 275 uint32_t InvMarginVyl : __CODEGEN_BITFIELD( 0, 15) ; //!< INV_Margin_VYL 276 uint32_t Reserved240 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 277 }; 278 uint32_t Value; 279 } DW7; 280 union 281 { 282 struct 283 { 284 uint32_t InvMarginVyu : __CODEGEN_BITFIELD( 0, 15) ; //!< INV_Margin_VYU 285 uint32_t P0L : __CODEGEN_BITFIELD(16, 23) ; //!< P0L 286 uint32_t P1L : __CODEGEN_BITFIELD(24, 31) ; //!< P1L 287 }; 288 uint32_t Value; 289 } DW8; 290 union 291 { 292 struct 293 { 294 uint32_t P2L : __CODEGEN_BITFIELD( 0, 7) ; //!< P2L 295 uint32_t P3L : __CODEGEN_BITFIELD( 8, 15) ; //!< P3L 296 uint32_t B0L : __CODEGEN_BITFIELD(16, 23) ; //!< B0L 297 uint32_t B1L : __CODEGEN_BITFIELD(24, 31) ; //!< B1L 298 }; 299 uint32_t Value; 300 } DW9; 301 union 302 { 303 struct 304 { 305 uint32_t B2L : __CODEGEN_BITFIELD( 0, 7) ; //!< B2L 306 uint32_t B3L : __CODEGEN_BITFIELD( 8, 15) ; //!< B3L 307 uint32_t S0L : __CODEGEN_BITFIELD(16, 26) ; //!< S0L 308 uint32_t YSlope2 : __CODEGEN_BITFIELD(27, 31) ; //!< Y_Slope_2 309 }; 310 uint32_t Value; 311 } DW10; 312 union 313 { 314 struct 315 { 316 uint32_t S1L : __CODEGEN_BITFIELD( 0, 10) ; //!< S1L 317 uint32_t S2L : __CODEGEN_BITFIELD(11, 21) ; //!< S2L 318 uint32_t Reserved374 : __CODEGEN_BITFIELD(22, 31) ; //!< Reserved 319 }; 320 uint32_t Value; 321 } DW11; 322 union 323 { 324 struct 325 { 326 uint32_t S3L : __CODEGEN_BITFIELD( 0, 10) ; //!< S3L 327 uint32_t P0U : __CODEGEN_BITFIELD(11, 18) ; //!< P0U 328 uint32_t P1U : __CODEGEN_BITFIELD(19, 26) ; //!< P1U 329 uint32_t YSlope1 : __CODEGEN_BITFIELD(27, 31) ; //!< Y_Slope1 330 }; 331 uint32_t Value; 332 } DW12; 333 union 334 { 335 struct 336 { 337 uint32_t P2U : __CODEGEN_BITFIELD( 0, 7) ; //!< P2U 338 uint32_t P3U : __CODEGEN_BITFIELD( 8, 15) ; //!< P3U 339 uint32_t B0U : __CODEGEN_BITFIELD(16, 23) ; //!< B0U 340 uint32_t B1U : __CODEGEN_BITFIELD(24, 31) ; //!< B1U 341 }; 342 uint32_t Value; 343 } DW13; 344 union 345 { 346 struct 347 { 348 uint32_t B2U : __CODEGEN_BITFIELD( 0, 7) ; //!< B2U 349 uint32_t B3U : __CODEGEN_BITFIELD( 8, 15) ; //!< B3U 350 uint32_t S0U : __CODEGEN_BITFIELD(16, 26) ; //!< S0U 351 uint32_t Reserved475 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 352 }; 353 uint32_t Value; 354 } DW14; 355 union 356 { 357 struct 358 { 359 uint32_t S1U : __CODEGEN_BITFIELD( 0, 10) ; //!< S1U 360 uint32_t S2U : __CODEGEN_BITFIELD(11, 21) ; //!< S2U 361 uint32_t Reserved502 : __CODEGEN_BITFIELD(22, 31) ; //!< Reserved 362 }; 363 uint32_t Value; 364 } DW15; 365 union 366 { 367 struct 368 { 369 uint32_t TransformEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< Transform Enable 370 uint32_t YuvChannelSwap : __CODEGEN_BITFIELD( 1, 1) ; //!< YUV Channel Swap 371 uint32_t Reserved514 : __CODEGEN_BITFIELD( 2, 2) ; //!< Reserved 372 uint32_t C0 : __CODEGEN_BITFIELD( 3, 15) ; //!< C0 373 uint32_t C1 : __CODEGEN_BITFIELD(16, 28) ; //!< C1 374 uint32_t Reserved541 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 375 }; 376 uint32_t Value; 377 } DW16; 378 union 379 { 380 struct 381 { 382 uint32_t C2 : __CODEGEN_BITFIELD( 0, 12) ; //!< C2 383 uint32_t C3 : __CODEGEN_BITFIELD(13, 25) ; //!< C3 384 uint32_t Reserved570 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 385 }; 386 uint32_t Value; 387 } DW17; 388 union 389 { 390 struct 391 { 392 uint32_t C4 : __CODEGEN_BITFIELD( 0, 12) ; //!< C4 393 uint32_t C5 : __CODEGEN_BITFIELD(13, 25) ; //!< C5 394 uint32_t Reserved602 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 395 }; 396 uint32_t Value; 397 } DW18; 398 union 399 { 400 struct 401 { 402 uint32_t C6 : __CODEGEN_BITFIELD( 0, 12) ; //!< C6 403 uint32_t C7 : __CODEGEN_BITFIELD(13, 25) ; //!< C7 404 uint32_t Reserved634 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 405 }; 406 uint32_t Value; 407 } DW19; 408 union 409 { 410 struct 411 { 412 uint32_t C8 : __CODEGEN_BITFIELD( 0, 12) ; //!< C8 413 uint32_t Reserved653 : __CODEGEN_BITFIELD(13, 31) ; //!< Reserved 414 }; 415 uint32_t Value; 416 } DW20; 417 union 418 { 419 struct 420 { 421 uint32_t OffsetIn1 : __CODEGEN_BITFIELD( 0, 10) ; //!< OFFSET_IN_1 422 uint32_t OffsetOut1 : __CODEGEN_BITFIELD(11, 21) ; //!< OFFSET_OUT_1 423 uint32_t Reserved694 : __CODEGEN_BITFIELD(22, 31) ; //!< Reserved 424 }; 425 uint32_t Value; 426 } DW21; 427 union 428 { 429 struct 430 { 431 uint32_t OffsetIn2 : __CODEGEN_BITFIELD( 0, 10) ; //!< OFFSET_IN_2 432 uint32_t OffsetOut2 : __CODEGEN_BITFIELD(11, 21) ; //!< OFFSET_OUT_2 433 uint32_t Reserved726 : __CODEGEN_BITFIELD(22, 31) ; //!< Reserved 434 }; 435 uint32_t Value; 436 } DW22; 437 union 438 { 439 struct 440 { 441 uint32_t OffsetIn3 : __CODEGEN_BITFIELD( 0, 10) ; //!< OFFSET_IN_3 442 uint32_t OffsetOut3 : __CODEGEN_BITFIELD(11, 21) ; //!< OFFSET_OUT_3 443 uint32_t Reserved758 : __CODEGEN_BITFIELD(22, 31) ; //!< Reserved 444 }; 445 uint32_t Value; 446 } DW23; 447 448 //! \name Local enumerations 449 450 enum SUBOPCODEB 451 { 452 SUBOPCODEB_SFCIEFSTATE = 3, //!< No additional details 453 }; 454 455 enum SUBOPCODEA 456 { 457 SUBOPCODEA_COMMON = 0, //!< No additional details 458 }; 459 460 enum MEDIA_COMMAND_OPCODE 461 { 462 MEDIA_COMMAND_OPCODE_MEDIAMISC = 10, //!< Media MFX/VEBOX+SFC Mode 463 }; 464 465 enum PIPELINE 466 { 467 PIPELINE_MEDIA = 2, //!< No additional details 468 }; 469 470 enum COMMAND_TYPE 471 { 472 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 473 }; 474 475 //! \brief GAIN_FACTOR 476 //! \details 477 //! User control sharpening strength. 478 enum GAIN_FACTOR 479 { 480 GAIN_FACTOR_UNNAMED44 = 44, //!< No additional details 481 }; 482 483 //! \brief WEAK_EDGE_THRESHOLD 484 //! \details 485 //! If Strong Edge Threshold > EM > Weak Edge Threshold → the basic 486 //! VSA detects a weak edge. 487 enum WEAK_EDGE_THRESHOLD 488 { 489 WEAK_EDGE_THRESHOLD_UNNAMED1 = 1, //!< No additional details 490 }; 491 492 //! \brief STRONG_EDGE_THRESHOLD 493 //! \details 494 //! If EM > Strong Edge Threshold → the basic VSA detects a strong edge. 495 enum STRONG_EDGE_THRESHOLD 496 { 497 STRONG_EDGE_THRESHOLD_UNNAMED8 = 8, //!< No additional details 498 }; 499 500 //! \brief R3X_COEFFICIENT 501 //! \details 502 //! IEF smoothing coefficient, see IEF map. 503 enum R3X_COEFFICIENT 504 { 505 R3X_COEFFICIENT_UNNAMED5 = 5, //!< No additional details 506 }; 507 508 //! \brief R3C_COEFFICIENT 509 //! \details 510 //! IEF smoothing coefficient, see IEF map. 511 enum R3C_COEFFICIENT 512 { 513 R3C_COEFFICIENT_UNNAMED5 = 5, //!< No additional details 514 }; 515 516 //! \brief GLOBAL_NOISE_ESTIMATION 517 //! \details 518 //! Global noise estimation of previous frame. 519 enum GLOBAL_NOISE_ESTIMATION 520 { 521 GLOBAL_NOISE_ESTIMATION_UNNAMED255 = 255, //!< No additional details 522 }; 523 524 //! \brief NON_EDGE_WEIGHT 525 //! \details 526 //! . Sharpening strength when NO EDGE is found in basic VSA. 527 enum NON_EDGE_WEIGHT 528 { 529 NON_EDGE_WEIGHT_UNNAMED1 = 1, //!< No additional details 530 }; 531 532 //! \brief REGULAR_WEIGHT 533 //! \details 534 //! Sharpening strength when a WEAK edge is found in basic VSA. 535 enum REGULAR_WEIGHT 536 { 537 REGULAR_WEIGHT_UNNAMED2 = 2, //!< No additional details 538 }; 539 540 //! \brief STRONG_EDGE_WEIGHT 541 //! \details 542 //! Sharpening strength when a STRONG edge is found in basic VSA. 543 enum STRONG_EDGE_WEIGHT 544 { 545 STRONG_EDGE_WEIGHT_UNNAMED7 = 7, //!< No additional details 546 }; 547 548 //! \brief R5X_COEFFICIENT 549 //! \details 550 //! IEF smoothing coefficient, see IEF map. 551 enum R5X_COEFFICIENT 552 { 553 R5X_COEFFICIENT_UNNAMED7 = 7, //!< No additional details 554 }; 555 556 //! \brief R5CX_COEFFICIENT 557 //! \details 558 //! IEF smoothing coefficient, see IEF map. 559 enum R5CX_COEFFICIENT 560 { 561 R5CX_COEFFICIENT_UNNAMED7 = 7, //!< No additional details 562 }; 563 564 //! \brief R5C_COEFFICIENT 565 //! \details 566 //! IEF smoothing coefficient, see IEF map. 567 enum R5C_COEFFICIENT 568 { 569 R5C_COEFFICIENT_UNNAMED7 = 7, //!< No additional details 570 }; 571 572 //! \brief SAT_MAX 573 //! \details 574 //! Rectangle half length. 575 enum SAT_MAX 576 { 577 SAT_MAX_UNNAMED31 = 31, //!< No additional details 578 }; 579 580 //! \brief HUE_MAX 581 //! \details 582 //! Rectangle half width. 583 enum HUE_MAX 584 { 585 HUE_MAX_UNNAMED14 = 14, //!< No additional details 586 }; 587 588 enum DIAMOND_MARGIN 589 { 590 DIAMOND_MARGIN_UNNAMED4 = 4, //!< No additional details 591 }; 592 593 //! \brief U_MID 594 //! \details 595 //! Rectangle middle-point U coordinate. 596 enum U_MID 597 { 598 U_MID_UNNAMED110 = 110, //!< No additional details 599 }; 600 601 //! \brief V_MID 602 //! \details 603 //! Rectangle middle-point V coordinate. 604 enum V_MID 605 { 606 V_MID_UNNAMED154 = 154, //!< No additional details 607 }; 608 609 //! \brief DIAMOND_DV 610 //! \details 611 //! Rhombus center shift in the hue-direction, relative to the rectangle 612 //! center. 613 enum DIAMOND_DV 614 { 615 DIAMOND_DV_UNNAMED0 = 0, //!< No additional details 616 }; 617 618 //! \brief DIAMOND_TH 619 //! \details 620 //! Half length of the rhombus axis in the sat-direction. 621 enum DIAMOND_TH 622 { 623 DIAMOND_TH_UNNAMED35 = 35, //!< No additional details 624 }; 625 626 //! \brief HS_MARGIN 627 //! \details 628 //! Defines rectangle margin. 629 enum HS_MARGIN 630 { 631 HS_MARGIN_UNNAMED3 = 3, //!< No additional details 632 }; 633 634 //! \brief DIAMOND_DU 635 //! \details 636 //! Rhombus center shift in the sat-direction, relative to the rectangle 637 //! center. 638 enum DIAMOND_DU 639 { 640 DIAMOND_DU_UNNAMED0 = 0, //!< No additional details 641 }; 642 643 //! \brief SKIN_DETAIL_FACTOR 644 //! \details 645 //! This flag bit is in operation only when one of the following conditions 646 //! exists: 647 //! 648 //! when the control bit SkinToneTunedIEF_Enable is on. 649 //! 650 651 //! <Li>When SkinDetailFactor is equal to 0, 652 //! sign(SkinDetailFactor) is equal to +1, and the content of the 653 //! detected skin tone area is detail revealed.</Li> 654 //! When SkinDetailFactor is equal to 1, 655 //! sign(SkinDetailFactor) is equal to -1, and the content of the 656 //! detected skin tone area is not detail revealed. 657 658 //! 659 enum SKIN_DETAIL_FACTOR 660 { 661 SKIN_DETAIL_FACTOR_DETAILREVEALED = 0, //!< No additional details 662 SKIN_DETAIL_FACTOR_NOTDETAILREVEALED = 1, //!< No additional details 663 }; 664 665 //! \brief Y_POINT_1 666 //! \details 667 //! First point of the Y piecewise linear membership function. 668 enum Y_POINT_1 669 { 670 Y_POINT_1_UNNAMED46 = 46, //!< No additional details 671 }; 672 673 //! \brief Y_POINT_2 674 //! \details 675 //! Second point of the Y piecewise linear membership function. 676 enum Y_POINT_2 677 { 678 Y_POINT_2_UNNAMED47 = 47, //!< No additional details 679 }; 680 681 //! \brief Y_POINT_3 682 //! \details 683 //! Third point of the Y piecewise linear membership function. 684 enum Y_POINT_3 685 { 686 Y_POINT_3_UNNAMED254 = 254, //!< No additional details 687 }; 688 689 //! \brief Y_POINT_4 690 //! \details 691 //! Fourth point of the Y piecewise linear membership function. 692 enum Y_POINT_4 693 { 694 Y_POINT_4_UNNAMED255 = 255, //!< No additional details 695 }; 696 697 //! \brief P0L 698 //! \details 699 //! Y Point 0 of the lower part of the detection PWLF. 700 enum P0L 701 { 702 P0L_UNNAMED46 = 46, //!< No additional details 703 }; 704 705 //! \brief P1L 706 //! \details 707 //! Y Point 1 of the lower part of the detection PWLF. 708 enum P1L 709 { 710 P1L_UNNAMED216 = 216, //!< No additional details 711 }; 712 713 //! \brief P2L 714 //! \details 715 //! Y Point 2 of the lower part of the detection PWLF. 716 enum P2L 717 { 718 P2L_UNNAMED236 = 236, //!< No additional details 719 }; 720 721 //! \brief P3L 722 //! \details 723 //! Y Point 3 of the lower part of the detection PWLF. 724 enum P3L 725 { 726 P3L_UNNAMED236 = 236, //!< No additional details 727 }; 728 729 //! \brief B0L 730 //! \details 731 //! V Bias 0 of the lower part of the detection PWLF. 732 enum B0L 733 { 734 B0L_UNNAMED133 = 133, //!< No additional details 735 }; 736 737 //! \brief B1L 738 //! \details 739 //! V Bias 1 of the lower part of the detection PWLF. 740 enum B1L 741 { 742 B1L_UNNAMED130 = 130, //!< No additional details 743 }; 744 745 //! \brief B2L 746 //! \details 747 //! V Bias 2 of the lower part of the detection PWLF. 748 enum B2L 749 { 750 B2L_UNNAMED130 = 130, //!< No additional details 751 }; 752 753 //! \brief B3L 754 //! \details 755 //! V Bias 3 of the lower part of the detection PWLF. 756 enum B3L 757 { 758 B3L_UNNAMED130 = 130, //!< No additional details 759 }; 760 761 //! \brief P0U 762 //! \details 763 //! Y Point 0 of the upper part of the detection PWLF. 764 enum P0U 765 { 766 P0U_UNNAMED46 = 46, //!< No additional details 767 }; 768 769 //! \brief P1U 770 //! \details 771 //! Y Point 1 of the upper part of the detection PWLF. 772 enum P1U 773 { 774 P1U_UNNAMED66 = 66, //!< No additional details 775 }; 776 777 //! \brief P2U 778 //! \details 779 //! Y Point 2 of the upper part of the detection PWLF. 780 enum P2U 781 { 782 P2U_UNNAMED150 = 150, //!< No additional details 783 }; 784 785 //! \brief P3U 786 //! \details 787 //! Y Point 3 of the upper part of the detection PWLF. 788 enum P3U 789 { 790 P3U_UNNAMED236 = 236, //!< No additional details 791 }; 792 793 //! \brief B0U 794 //! \details 795 //! V Bias 0 of the upper part of the detection PWLF. 796 enum B0U 797 { 798 B0U_UNNAMED143 = 143, //!< No additional details 799 }; 800 801 //! \brief B1U 802 //! \details 803 //! V Bias 1 of the upper part of the detection PWLF. 804 enum B1U 805 { 806 B1U_UNNAMED163 = 163, //!< No additional details 807 }; 808 809 //! \brief B2U 810 //! \details 811 //! V Bias 2 of the upper part of the detection PWLF. 812 enum B2U 813 { 814 B2U_UNNAMED200 = 200, //!< No additional details 815 }; 816 817 //! \brief B3U 818 //! \details 819 //! V Bias 3 of the upper part of the detection PWLF. 820 enum B3U 821 { 822 B3U_UNNAMED140 = 140, //!< No additional details 823 }; 824 825 //! \brief C0 826 //! \details 827 //! Transform coefficient 828 enum C0 829 { 830 C0_UNNAMED1024 = 1024, //!< No additional details 831 }; 832 833 //! \brief C1 834 //! \details 835 //! Transform coefficient 836 enum C1 837 { 838 C1_UNNAMED0 = 0, //!< No additional details 839 }; 840 841 //! \brief C2 842 //! \details 843 //! Transform coefficient 844 enum C2 845 { 846 C2_UNNAMED0 = 0, //!< No additional details 847 }; 848 849 //! \brief C3 850 //! \details 851 //! Transform coefficient 852 enum C3 853 { 854 C3_UNNAMED0 = 0, //!< No additional details 855 }; 856 857 //! \brief C4 858 //! \details 859 //! Transform coefficient 860 enum C4 861 { 862 C4_UNNAMED1024 = 1024, //!< No additional details 863 }; 864 865 //! \brief C5 866 //! \details 867 //! Transform coefficient 868 enum C5 869 { 870 C5_UNNAMED0 = 0, //!< No additional details 871 }; 872 873 //! \brief C6 874 //! \details 875 //! Transform coefficient 876 enum C6 877 { 878 C6_UNNAMED0 = 0, //!< No additional details 879 }; 880 881 //! \brief C7 882 //! \details 883 //! Transform coefficient 884 enum C7 885 { 886 C7_UNNAMED0 = 0, //!< No additional details 887 }; 888 889 //! \brief C8 890 //! \details 891 //! Transform coefficient 892 enum C8 893 { 894 C8_UNNAMED1024 = 1024, //!< No additional details 895 }; 896 897 //! \brief OFFSET_IN_1 898 //! \details 899 //! Offset in for Y/R. 900 enum OFFSET_IN_1 901 { 902 OFFSET_IN_1_UNNAMED0 = 0, //!< No additional details 903 }; 904 905 //! \brief OFFSET_OUT_1 906 //! \details 907 //! Offset out for Y/R. 908 enum OFFSET_OUT_1 909 { 910 OFFSET_OUT_1_UNNAMED0 = 0, //!< No additional details 911 }; 912 913 //! \brief OFFSET_IN_2 914 //! \details 915 //! Offset in for U/G. 916 enum OFFSET_IN_2 917 { 918 OFFSET_IN_2_UNNAMED0 = 0, //!< No additional details 919 }; 920 921 //! \brief OFFSET_OUT_2 922 //! \details 923 //! Offset out for U/G. 924 enum OFFSET_OUT_2 925 { 926 OFFSET_OUT_2_UNNAMED0 = 0, //!< No additional details 927 }; 928 929 //! \brief OFFSET_IN_3 930 //! \details 931 //! Offset in for V/B. 932 enum OFFSET_IN_3 933 { 934 OFFSET_IN_3_UNNAMED0 = 0, //!< No additional details 935 }; 936 937 //! \brief OFFSET_OUT_3 938 //! \details 939 //! Offset out for V/B. 940 enum OFFSET_OUT_3 941 { 942 OFFSET_OUT_3_UNNAMED0 = 0, //!< No additional details 943 }; 944 945 //! \name Initializations 946 947 //! \brief Explicit member initialization function 948 SFC_IEF_STATE_CMD(); 949 950 static const size_t dwSize = 24; 951 static const size_t byteSize = 96; 952 }; 953 954 //! 955 //! \brief SFC_FRAME_START 956 //! \details 957 //! This command is sent from VDBOX/VEBOX to SFC pipeline at the start of 958 //! each frame once the lock request is granted. 959 //! 960 struct SFC_FRAME_START_CMD 961 { 962 union 963 { 964 struct 965 { 966 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 967 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 968 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODEB 969 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPCODEA 970 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_COMMAND_OPCODE 971 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 972 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 973 }; 974 uint32_t Value; 975 } DW0; 976 union 977 { 978 struct 979 { 980 uint32_t Reserved32 ; //!< Reserved 981 }; 982 uint32_t Value; 983 } DW1; 984 985 //! \name Local enumerations 986 987 enum SUBOPCODEB 988 { 989 SUBOPCODEB_SFCFRAMESTART = 4, //!< No additional details 990 }; 991 992 enum SUBOPCODEA 993 { 994 SUBOPCODEA_COMMON = 0, //!< No additional details 995 }; 996 997 enum MEDIA_COMMAND_OPCODE 998 { 999 MEDIA_COMMAND_OPCODE_MEDIAMISC = 10, //!< Media MFX/VEBOX+SFC Mode 1000 }; 1001 1002 enum PIPELINE 1003 { 1004 PIPELINE_MEDIA = 2, //!< No additional details 1005 }; 1006 1007 enum COMMAND_TYPE 1008 { 1009 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1010 }; 1011 1012 //! \name Initializations 1013 1014 //! \brief Explicit member initialization function 1015 SFC_FRAME_START_CMD(); 1016 1017 static const size_t dwSize = 2; 1018 static const size_t byteSize = 8; 1019 }; 1020 1021 //! 1022 //! \brief SFC_LOCK 1023 //! \details 1024 //! This command is used for VD/VE box to communicate with SFC before the 1025 //! start of any SFC workload. VD/VE uses this command to make sure that it 1026 //! has the ownership of SFC pipe before running workload with SFC since SFC 1027 //! is shared between VD/VE on a frame level. 1028 //! For VD(MFX)-SFC workload, only decoder mode is allowed. Encoder mode 1029 //! cannot use SFC. 1030 //! 1031 //! For VD(HCP)-SFC workload, only decoder mode is allowed. Encoder mode 1032 //! cannot use SFC 1033 //! 1034 struct SFC_LOCK_CMD 1035 { 1036 union 1037 { 1038 struct 1039 { 1040 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 1041 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1042 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODEB 1043 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPCODEA 1044 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_COMMAND_OPCODE 1045 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1046 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1047 }; 1048 uint32_t Value; 1049 } DW0; 1050 union 1051 { 1052 struct 1053 { 1054 uint32_t VeSfcPipeSelect : __CODEGEN_BITFIELD( 0, 0) ; //!< VE-SFC Pipe Select 1055 uint32_t PreScaledOutputSurfaceOutputEnable : __CODEGEN_BITFIELD( 1, 1) ; //!< Pre-Scaled Output Surface Output Enable 1056 uint32_t Reserved34 : __CODEGEN_BITFIELD( 2, 31) ; //!< Reserved 1057 }; 1058 uint32_t Value; 1059 } DW1; 1060 1061 //! \name Local enumerations 1062 1063 enum SUBOPCODEB 1064 { 1065 SUBOPCODEB_SFCLOCK = 0, //!< No additional details 1066 }; 1067 1068 enum SUBOPCODEA 1069 { 1070 SUBOPCODEA_COMMON = 0, //!< No additional details 1071 }; 1072 1073 enum MEDIA_COMMAND_OPCODE 1074 { 1075 MEDIA_COMMAND_OPCODE_MEDIAMISC = 10, //!< Media MFX/VEBOX+SFC ModeFor VD(MFX)+SFC mode, only decoder mode is allowed. Encoder mode cannot use SFC 1076 }; 1077 1078 enum PIPELINE 1079 { 1080 PIPELINE_MEDIA = 2, //!< No additional details 1081 }; 1082 1083 enum COMMAND_TYPE 1084 { 1085 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1086 }; 1087 1088 //! \name Initializations 1089 1090 //! \brief Explicit member initialization function 1091 SFC_LOCK_CMD(); 1092 1093 static const size_t dwSize = 2; 1094 static const size_t byteSize = 8; 1095 }; 1096 1097 //! 1098 //! \brief SFC_STATE 1099 //! \details 1100 //! This command is sent from VDBOX/HCP/VEBOX to SFC pipeline at the start 1101 //! of each frame once the lock request is granted. 1102 //! 1103 struct SFC_STATE_CMD 1104 { 1105 union 1106 { 1107 struct 1108 { 1109 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 1110 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1111 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODEB 1112 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPCODEA 1113 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_COMMAND_OPCODE 1114 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1115 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1116 }; 1117 uint32_t Value; 1118 } DW0; 1119 union 1120 { 1121 struct 1122 { 1123 uint32_t SfcPipeMode : __CODEGEN_BITFIELD( 0, 3) ; //!< SFC_PIPE_MODE 1124 uint32_t SfcInputChromaSubSampling : __CODEGEN_BITFIELD( 4, 7) ; //!< SFC_INPUT_CHROMA_SUB_SAMPLING 1125 uint32_t VdVeInputOrderingMode : __CODEGEN_BITFIELD( 8, 10) ; //!< VDVE_INPUT_ORDERING_MODE 1126 uint32_t Reserved43 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 1127 uint32_t SfcEngineMode : __CODEGEN_BITFIELD(12, 13) ; //!< SFC Engine Mode 1128 uint32_t Reserved46 : __CODEGEN_BITFIELD(14, 17) ; //!< Reserved 1129 uint32_t InputFrameDataFormat : __CODEGEN_BITFIELD(18, 19) ; //!< Input frame data format 1130 uint32_t OutputFrameDataFormat : __CODEGEN_BITFIELD(20, 21) ; //!< Output frame data format 1131 uint32_t TopBottomField : __CODEGEN_BITFIELD(22, 22) ; //!< Top/Bottom field 1132 uint32_t TopBottomFieldFirst : __CODEGEN_BITFIELD(23, 23) ; //!< Top/Bottom field first 1133 uint32_t Reserved56 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 1134 }; 1135 uint32_t Value; 1136 } DW1; 1137 union 1138 { 1139 struct 1140 { 1141 uint32_t InputFrameResolutionWidth : __CODEGEN_BITFIELD( 0, 13) ; //!< Input Frame Resolution Width 1142 uint32_t Reserved78 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1143 uint32_t InputFrameResolutionHeight : __CODEGEN_BITFIELD(16, 29) ; //!< Input Frame Resolution Height 1144 uint32_t Reserved94 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1145 }; 1146 uint32_t Value; 1147 } DW2; 1148 union 1149 { 1150 struct 1151 { 1152 uint32_t OutputSurfaceFormatType : __CODEGEN_BITFIELD( 0, 3) ; //!< OUTPUT_SURFACE_FORMAT_TYPE 1153 uint32_t Reserved100 : __CODEGEN_BITFIELD( 4, 4) ; //!< Reserved 1154 uint32_t ChannelSwapEnable : __CODEGEN_BITFIELD( 5, 5) ; //!< Channel_Swap Enable 1155 uint32_t Reserved102 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 1156 uint32_t OutputChromaDownsamplingCoSitingPositionVerticalDirection : __CODEGEN_BITFIELD( 8, 11) ; //!< OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_VERTICAL_DIRECTION 1157 uint32_t OutputChromaDownsamplingCoSitingPositionHorizontalDirection : __CODEGEN_BITFIELD(12, 15) ; //!< OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_HORIZONTAL_DIRECTION 1158 uint32_t InputColorSpace0Yuv1Rgb : __CODEGEN_BITFIELD(16, 16) ; //!< INPUT_COLOR_SPACE_0_YUV1_RGB 1159 uint32_t DitherEnable : __CODEGEN_BITFIELD(17, 17) ; //!< Dither Enable 1160 uint32_t OutputCompressionFormat : __CODEGEN_BITFIELD(18, 22) ; //!< OUTPUT_COMPRESSION_FORMAT 1161 uint32_t Reserved119 : __CODEGEN_BITFIELD(23, 31) ; //!< Reserved 1162 }; 1163 uint32_t Value; 1164 } DW3; 1165 union 1166 { 1167 struct 1168 { 1169 uint32_t IefEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< IEF_ENABLE 1170 uint32_t SkinToneTunedIefEnable : __CODEGEN_BITFIELD( 1, 1) ; //!< Skin Tone Tuned IEF_Enable 1171 uint32_t Ief4SmoothEnable : __CODEGEN_BITFIELD( 2, 2) ; //!< IEF4SMOOTH_ENABLE_ 1172 uint32_t Enable8TapForChromaChannelsFiltering : __CODEGEN_BITFIELD( 3, 3) ; //!< Enable 8 tap for Chroma channels filtering 1173 uint32_t AvsFilterMode : __CODEGEN_BITFIELD( 4, 5) ; //!< AVS_FILTER_MODE 1174 uint32_t AdaptiveFilterForAllChannels : __CODEGEN_BITFIELD( 6, 6) ; //!< ADAPTIVE_FILTER_FOR_ALL_CHANNELS 1175 uint32_t AvsScalingEnable : __CODEGEN_BITFIELD( 7, 7) ; //!< AVS_SCALING_ENABLE 1176 uint32_t BypassYAdaptiveFiltering : __CODEGEN_BITFIELD( 8, 8) ; //!< BYPASS_Y_ADAPTIVE_FILTERING 1177 uint32_t BypassXAdaptiveFiltering : __CODEGEN_BITFIELD( 9, 9) ; //!< BYPASS_X_ADAPTIVE_FILTERING 1178 uint32_t RgbAdaptive : __CODEGEN_BITFIELD(10, 10) ; //!< RGB Adaptive 1179 uint32_t Reserved139 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 1180 uint32_t ChromaUpsamplingEnable : __CODEGEN_BITFIELD(12, 12) ; //!< Chroma Upsampling Enable 1181 uint32_t Reserved141 : __CODEGEN_BITFIELD(13, 15) ; //!< Reserved 1182 uint32_t RotationMode : __CODEGEN_BITFIELD(16, 17) ; //!< ROTATION_MODE 1183 uint32_t ColorFillEnable : __CODEGEN_BITFIELD(18, 18) ; //!< Color Fill Enable 1184 uint32_t CscEnable : __CODEGEN_BITFIELD(19, 19) ; //!< CSC Enable 1185 uint32_t Bitdepth : __CODEGEN_BITFIELD(20, 21) ; //!< BITDEPTH 1186 uint32_t TileType : __CODEGEN_BITFIELD(22, 22) ; //!< Tile Type 1187 uint32_t HistogramStreamout : __CODEGEN_BITFIELD(23, 23) ; //!< Histogram Streamout 1188 uint32_t Reserved151 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 1189 }; 1190 uint32_t Value; 1191 } DW4; 1192 union 1193 { 1194 struct 1195 { 1196 uint32_t SourceRegionWidth : __CODEGEN_BITFIELD( 0, 13) ; //!< Source Region Width 1197 uint32_t Reserved174 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1198 uint32_t SourceRegionHeight : __CODEGEN_BITFIELD(16, 29) ; //!< Source Region Height 1199 uint32_t Reserved190 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1200 }; 1201 uint32_t Value; 1202 } DW5; 1203 union 1204 { 1205 struct 1206 { 1207 uint32_t SourceRegionHorizontalOffset : __CODEGEN_BITFIELD( 0, 13) ; //!< Source Region Horizontal Offset 1208 uint32_t Reserved206 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1209 uint32_t SourceRegionVerticalOffset : __CODEGEN_BITFIELD(16, 29) ; //!< Source Region Vertical Offset 1210 uint32_t Reserved222 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1211 }; 1212 uint32_t Value; 1213 } DW6; 1214 union 1215 { 1216 struct 1217 { 1218 uint32_t OutputFrameWidth : __CODEGEN_BITFIELD( 0, 13) ; //!< Output Frame Width 1219 uint32_t Reserved238 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1220 uint32_t OutputFrameHeight : __CODEGEN_BITFIELD(16, 29) ; //!< Output Frame Height 1221 uint32_t Reserved254 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1222 }; 1223 uint32_t Value; 1224 } DW7; 1225 union 1226 { 1227 struct 1228 { 1229 uint32_t ScaledRegionSizeWidth : __CODEGEN_BITFIELD( 0, 13) ; //!< Scaled Region Size Width 1230 uint32_t Reserved270 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1231 uint32_t ScaledRegionSizeHeight : __CODEGEN_BITFIELD(16, 29) ; //!< Scaled Region Size Height 1232 uint32_t Reserved286 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1233 }; 1234 uint32_t Value; 1235 } DW8; 1236 union 1237 { 1238 struct 1239 { 1240 uint32_t ScaledRegionHorizontalOffset : __CODEGEN_BITFIELD( 0, 14) ; //!< Scaled Region Horizontal Offset 1241 uint32_t Reserved303 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 1242 uint32_t ScaledRegionVerticalOffset : __CODEGEN_BITFIELD(16, 30) ; //!< Scaled Region Vertical Offset 1243 uint32_t Reserved319 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 1244 }; 1245 uint32_t Value; 1246 } DW9; 1247 union 1248 { 1249 struct 1250 { 1251 uint32_t GrayBarPixelUG : __CODEGEN_BITFIELD( 0, 9) ; //!< Gray Bar Pixel - U/G 1252 uint32_t Reserved330 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved 1253 uint32_t GrayBarPixelYR : __CODEGEN_BITFIELD(16, 25) ; //!< Gray Bar Pixel - Y/R 1254 uint32_t Reserved346 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 1255 }; 1256 uint32_t Value; 1257 } DW10; 1258 union 1259 { 1260 struct 1261 { 1262 uint32_t GrayBarPixelA : __CODEGEN_BITFIELD( 0, 9) ; //!< Gray Bar Pixel - A 1263 uint32_t Reserved362 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved 1264 uint32_t GrayBarPixelVB : __CODEGEN_BITFIELD(16, 25) ; //!< Gray Bar Pixel - V/B 1265 uint32_t Reserved378 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 1266 }; 1267 uint32_t Value; 1268 } DW11; 1269 union 1270 { 1271 struct 1272 { 1273 uint32_t UvDefaultValueForUChannelForMonoInputSupport : __CODEGEN_BITFIELD( 0, 9) ; //!< UV Default value for U channel (For Mono Input Support) 1274 uint32_t Reserved394 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved 1275 uint32_t UvDefaultValueForVChannelForMonoInputSupport : __CODEGEN_BITFIELD(16, 25) ; //!< UV Default value for V channel (For Mono Input Support) 1276 uint32_t Reserved410 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 1277 }; 1278 uint32_t Value; 1279 } DW12; 1280 union 1281 { 1282 struct 1283 { 1284 uint32_t AlphaDefaultValue : __CODEGEN_BITFIELD( 0, 9) ; //!< Alpha Default Value 1285 uint32_t Reserved426 : __CODEGEN_BITFIELD(10, 31) ; //!< Reserved 1286 }; 1287 uint32_t Value; 1288 } DW13; 1289 union 1290 { 1291 struct 1292 { 1293 uint32_t Reserved448 : __CODEGEN_BITFIELD( 0, 4) ; //!< Reserved 1294 uint32_t ScalingFactorHeight : __CODEGEN_BITFIELD( 5, 27) ; //!< Scaling Factor Height 1295 uint32_t Reserved476 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 1296 }; 1297 uint32_t Value; 1298 } DW14; 1299 union 1300 { 1301 struct 1302 { 1303 uint32_t Reserved480 : __CODEGEN_BITFIELD( 0, 4) ; //!< Reserved 1304 uint32_t ScaleFactorWidth : __CODEGEN_BITFIELD( 5, 27) ; //!< Scale Factor Width 1305 uint32_t Reserved508 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 1306 }; 1307 uint32_t Value; 1308 } DW15; 1309 union 1310 { 1311 struct 1312 { 1313 uint32_t Reserved512 ; //!< Reserved 1314 }; 1315 uint32_t Value; 1316 } DW16; 1317 union 1318 { 1319 struct 1320 { 1321 uint32_t Reserved544 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1322 uint32_t OutputFrameSurfaceBaseAddress : __CODEGEN_BITFIELD(12, 31) ; //!< Output Frame Surface Base Address 1323 }; 1324 uint32_t Value; 1325 } DW17; 1326 union 1327 { 1328 struct 1329 { 1330 uint32_t OutputFrameSurfaceBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Output Frame Surface Base Address High 1331 uint32_t Reserved592 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1332 }; 1333 uint32_t Value; 1334 } DW18; 1335 union 1336 { 1337 struct 1338 { 1339 uint32_t Reserved608 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 1340 uint32_t OutputFrameSurfaceBaseAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< Output Frame Surface Base Address - Index to Memory Object Control State (MOCS) Tables 1341 uint32_t OutputFrameSurfaceBaseAddressArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< Output Frame Surface Base Address - Arbitration Priority Control 1342 uint32_t OutputFrameSurfaceBaseAddressMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< Output Frame Surface Base Address - Memory Compression Enable 1343 uint32_t CompressionType : __CODEGEN_BITFIELD(10, 10) ; //!< COMPRESSION_TYPE 1344 uint32_t Reserved619 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 1345 uint32_t OutputFrameSurfaceBaseAddressRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< OUTPUT_FRAME_SURFACE_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1346 uint32_t Reserved623 : __CODEGEN_BITFIELD(13, 31) ; //!< Reserved 1347 }; 1348 uint32_t Value; 1349 } DW19; 1350 union 1351 { 1352 struct 1353 { 1354 uint32_t Reserved640 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1355 uint32_t AvsLineBufferSurfaceBaseAddress : __CODEGEN_BITFIELD(12, 31) ; //!< AVS Line Buffer Surface Base Address 1356 }; 1357 uint32_t Value; 1358 } DW20; 1359 union 1360 { 1361 struct 1362 { 1363 uint32_t AvsLineBufferSurfaceBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< AVS Line Buffer Surface Base Address High 1364 uint32_t Reserved688 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1365 }; 1366 uint32_t Value; 1367 } DW21; 1368 union 1369 { 1370 struct 1371 { 1372 uint32_t Reserved704 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 1373 uint32_t AvsLineBufferBaseAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< AVS Line Buffer Base Address - Index to Memory Object Control State (MOCS) Tables 1374 uint32_t AvsLineBufferBaseAddressArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< AVS Line Buffer Base Address - Arbitration Priority Control 1375 uint32_t AvsLineBufferBaseAddressMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< AVS_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_ENABLE 1376 uint32_t AvsLineBufferBaseAddressMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< AVS_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 1377 uint32_t Reserved715 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 1378 uint32_t AvsLineBufferBaseAddressRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< AVS_LINE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1379 uint32_t AvsLineBufferTiledMode : __CODEGEN_BITFIELD(13, 14) ; //!< AVS_LINE_BUFFER_TILED_MODE 1380 uint32_t Reserved719 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 1381 }; 1382 uint32_t Value; 1383 } DW22; 1384 union 1385 { 1386 struct 1387 { 1388 uint32_t Reserved736 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1389 uint32_t IefLineBufferSurfaceBaseAddress : __CODEGEN_BITFIELD(12, 31) ; //!< IEF Line Buffer Surface Base Address 1390 }; 1391 uint32_t Value; 1392 } DW23; 1393 union 1394 { 1395 struct 1396 { 1397 uint32_t IefLineBufferSurfaceBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< IEF Line Buffer Surface Base Address High 1398 uint32_t Reserved784 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1399 }; 1400 uint32_t Value; 1401 } DW24; 1402 union 1403 { 1404 struct 1405 { 1406 uint32_t Reserved800 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 1407 uint32_t IefLineBufferBaseAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< IEF Line Buffer Base Address - Index to Memory Object Control State (MOCS) Tables 1408 uint32_t IefLineBufferBaseAddressArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< IEF Line Buffer Base Address - Arbitration Priority Control 1409 uint32_t IefLineBufferBaseAddressMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< IEF_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_ENABLE 1410 uint32_t IefLineBufferBaseAddressMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< IEF_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 1411 uint32_t Reserved811 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 1412 uint32_t IefLineBufferBaseAddressRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< IEF_LINE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1413 uint32_t IefLineBufferTiledMode : __CODEGEN_BITFIELD(13, 14) ; //!< IEF_LINE_BUFFER_TILED_MODE 1414 uint32_t Reserved815 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 1415 }; 1416 uint32_t Value; 1417 } DW25; 1418 union 1419 { 1420 struct 1421 { 1422 uint32_t Reserved832 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1423 uint32_t SfdLineBufferSurfaceBaseAddress : __CODEGEN_BITFIELD(12, 31) ; //!< SFD Line Buffer Surface Base Address 1424 }; 1425 uint32_t Value; 1426 } DW26; 1427 union 1428 { 1429 struct 1430 { 1431 uint32_t SfdLineBufferSurfaceBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< SFD Line Buffer Surface Base Address High 1432 uint32_t Reserved880 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1433 }; 1434 uint32_t Value; 1435 } DW27; 1436 union 1437 { 1438 struct 1439 { 1440 uint32_t Reserved896 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 1441 uint32_t SfdLineBufferBaseAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< SFD Line Buffer Base Address - Index to Memory Object Control State (MOCS) Tables 1442 uint32_t SfdLineBufferBaseAddressArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< SFD Line Buffer Base Address - Arbitration Priority Control 1443 uint32_t SfdLineBufferBaseAddressMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< SFD_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_ENABLE 1444 uint32_t SfdLineBufferBaseAddressMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< SFD_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 1445 uint32_t Reserved907 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 1446 uint32_t SfdLineBufferBaseAddressRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< SFD_LINE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1447 uint32_t SfdLineBufferTiledMode : __CODEGEN_BITFIELD(13, 14) ; //!< SFD_LINE_BUFFER_TILED_MODE 1448 uint32_t Reserved911 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 1449 }; 1450 uint32_t Value; 1451 } DW28; 1452 union 1453 { 1454 struct 1455 { 1456 uint32_t OutputSurfaceTiledMode : __CODEGEN_BITFIELD( 0, 1) ; //!< OUTPUT_SURFACE_TILED_MODE 1457 uint32_t OutputSurfaceHalfPitchForChroma : __CODEGEN_BITFIELD( 2, 2) ; //!< Output Surface Half Pitch For Chroma 1458 uint32_t OutputSurfacePitch : __CODEGEN_BITFIELD( 3, 19) ; //!< Output Surface Pitch 1459 uint32_t Reserved948 : __CODEGEN_BITFIELD(20, 26) ; //!< Reserved 1460 uint32_t OutputSurfaceInterleaveChromaEnable : __CODEGEN_BITFIELD(27, 27) ; //!< Output Surface Interleave Chroma Enable 1461 uint32_t OutputSurfaceFormat : __CODEGEN_BITFIELD(28, 31) ; //!< Output Surface Format 1462 }; 1463 uint32_t Value; 1464 } DW29; 1465 union 1466 { 1467 struct 1468 { 1469 uint32_t OutputSurfaceYOffsetForU : __CODEGEN_BITFIELD( 0, 15) ; //!< Output Surface Y Offset For U 1470 uint32_t OutputSurfaceXOffsetForU : __CODEGEN_BITFIELD(16, 31) ; //!< Output Surface X Offset For U 1471 }; 1472 uint32_t Value; 1473 } DW30; 1474 union 1475 { 1476 struct 1477 { 1478 uint32_t OutputSurfaceYOffsetForV : __CODEGEN_BITFIELD( 0, 15) ; //!< Output Surface Y Offset For V 1479 uint32_t OutputSurfaceXOffsetForV : __CODEGEN_BITFIELD(16, 31) ; //!< Output Surface X Offset For V 1480 }; 1481 uint32_t Value; 1482 } DW31; 1483 union 1484 { 1485 struct 1486 { 1487 uint32_t Reserved1024 ; //!< Reserved 1488 }; 1489 uint32_t Value; 1490 } DW32; 1491 union 1492 { 1493 struct 1494 { 1495 uint32_t Reserved1056 ; //!< Reserved 1496 }; 1497 uint32_t Value; 1498 } DW33; 1499 union 1500 { 1501 struct 1502 { 1503 uint32_t Sourcestartx : __CODEGEN_BITFIELD( 0, 13) ; //!< SourceStartX 1504 uint32_t Reserved1102 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1505 uint32_t Sourceendx : __CODEGEN_BITFIELD(16, 29) ; //!< SourceEndX 1506 uint32_t Reserved1118 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1507 }; 1508 uint32_t Value; 1509 } DW34; 1510 union 1511 { 1512 struct 1513 { 1514 uint32_t Destinationstartx : __CODEGEN_BITFIELD( 0, 13) ; //!< DestinationStartX 1515 uint32_t Reserved1134 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1516 uint32_t Destinationendx : __CODEGEN_BITFIELD(16, 29) ; //!< DestinationEndX 1517 uint32_t Reserved1150 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1518 }; 1519 uint32_t Value; 1520 } DW35; 1521 union 1522 { 1523 struct 1524 { 1525 uint32_t Reserved1152 : __CODEGEN_BITFIELD( 0, 4) ; //!< Reserved 1526 uint32_t Xphaseshift : __CODEGEN_BITFIELD( 5, 28) ; //!< Xphaseshift 1527 uint32_t Reserved1181 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 1528 }; 1529 uint32_t Value; 1530 } DW36; 1531 union 1532 { 1533 struct 1534 { 1535 uint32_t Reserved1184 : __CODEGEN_BITFIELD( 0, 4) ; //!< Reserved 1536 uint32_t Yphaseshift : __CODEGEN_BITFIELD( 5, 28) ; //!< Yphaseshift 1537 uint32_t Reserved1213 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 1538 }; 1539 uint32_t Value; 1540 } DW37; 1541 union 1542 { 1543 struct 1544 { 1545 uint32_t Reserved1216 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1546 uint32_t AvsLineTileBufferSurfaceBaseAddress : __CODEGEN_BITFIELD(12, 31) ; //!< AVS Line Tile Buffer Surface Base Address 1547 }; 1548 uint32_t Value; 1549 } DW38; 1550 union 1551 { 1552 struct 1553 { 1554 uint32_t AvsLineTileBufferSurfaceBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< AVS Line Tile Buffer Surface Base Address High 1555 uint32_t Reserved1264 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1556 }; 1557 uint32_t Value; 1558 } DW39; 1559 union 1560 { 1561 struct 1562 { 1563 uint32_t Reserved1280 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 1564 uint32_t AvsLineTileBufferBaseAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< AVS Line Tile Buffer Base Address - Index to Memory Object Control State (MOCS) Tables 1565 uint32_t AvsLineTileBufferBaseAddressArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< AVS Line Tile Buffer Base Address - Arbitration Priority Control 1566 uint32_t AvsLineTileBufferBaseAddressMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< AVS_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_ENABLE 1567 uint32_t AvsLineTileBufferBaseAddressMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< AVS_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 1568 uint32_t Reserved1291 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 1569 uint32_t AvsLineTileBufferBaseAddressRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< AVS_LINE_TILE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1570 uint32_t AvsLineTileBufferTiledMode : __CODEGEN_BITFIELD(13, 14) ; //!< AVS_LINE_TILE_BUFFER_TILED_MODE 1571 uint32_t Reserved1295 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 1572 }; 1573 uint32_t Value; 1574 } DW40; 1575 union 1576 { 1577 struct 1578 { 1579 uint32_t Reserved1312 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1580 uint32_t IefLineTileBufferSurfaceBaseAddress : __CODEGEN_BITFIELD(12, 31) ; //!< IEF Line Tile Buffer Surface Base Address 1581 }; 1582 uint32_t Value; 1583 } DW41; 1584 union 1585 { 1586 struct 1587 { 1588 uint32_t IefLineTileBufferSurfaceBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< IEF Line Tile Buffer Surface Base Address High 1589 uint32_t Reserved1360 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1590 }; 1591 uint32_t Value; 1592 } DW42; 1593 union 1594 { 1595 struct 1596 { 1597 uint32_t Reserved1376 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 1598 uint32_t IefLineTileBufferBaseAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< IEF Line Tile Buffer Base Address - Index to Memory Object Control State (MOCS) Tables 1599 uint32_t IefLineTileBufferBaseAddressArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< IEF Line Tile Buffer Base Address - Arbitration Priority Control 1600 uint32_t IefLineTileBufferBaseAddressMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< IEF_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_ENABLE 1601 uint32_t IefLineTileBufferBaseAddressMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< IEF_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 1602 uint32_t Reserved1387 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 1603 uint32_t IefLineTileBufferBaseAddressRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< IEF_LINE_TILE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1604 uint32_t IefLineTileBufferTiledMode : __CODEGEN_BITFIELD(13, 14) ; //!< IEF_LINE_TILE_BUFFER_TILED_MODE 1605 uint32_t Reserved1391 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 1606 }; 1607 uint32_t Value; 1608 } DW43; 1609 union 1610 { 1611 struct 1612 { 1613 uint32_t Reserved1408 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1614 uint32_t SfdLineTileBufferSurfaceBaseAddress : __CODEGEN_BITFIELD(12, 31) ; //!< SFD Line Tile Buffer Surface Base Address 1615 }; 1616 uint32_t Value; 1617 } DW44; 1618 union 1619 { 1620 struct 1621 { 1622 uint32_t SfdLineTileBufferSurfaceBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< SFD Line Tile Buffer Surface Base Address High 1623 uint32_t Reserved1456 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1624 }; 1625 uint32_t Value; 1626 } DW45; 1627 union 1628 { 1629 struct 1630 { 1631 uint32_t Reserved1472 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 1632 uint32_t SfdLineTileBufferBaseAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< SFD Line Tile Buffer Base Address - Index to Memory Object Control State (MOCS) Tables 1633 uint32_t SfdLineTileBufferBaseAddressArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< SFD Line Tile Buffer Base Address - Arbitration Priority Control 1634 uint32_t SfdLineTileBufferBaseAddressMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< SFD_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_ENABLE 1635 uint32_t SfdLineTileBufferBaseAddressMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< SFD_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 1636 uint32_t Reserved1483 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 1637 uint32_t SfdLineTileBufferBaseAddressRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< SFD_LINE_TILE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1638 uint32_t SfdLineTileBufferTiledMode : __CODEGEN_BITFIELD(13, 14) ; //!< SFD_LINE_TILE_BUFFER_TILED_MODE 1639 uint32_t Reserved1487 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 1640 }; 1641 uint32_t Value; 1642 } DW46; 1643 union 1644 { 1645 struct 1646 { 1647 uint32_t Reserved1504 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1648 uint32_t HistogramSurfaceBaseAddress : __CODEGEN_BITFIELD(12, 31) ; //!< Histogram Surface Base Address 1649 }; 1650 uint32_t Value; 1651 } DW47; 1652 union 1653 { 1654 struct 1655 { 1656 uint32_t HistogramSurfaceBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Histogram Surface Base Address High 1657 uint32_t Reserved1552 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1658 }; 1659 uint32_t Value; 1660 } DW48; 1661 union 1662 { 1663 struct 1664 { 1665 uint32_t Reserved1568 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 1666 uint32_t HisgotramBaseAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< Hisgotram Base Address - Index to Memory Object Control State (MOCS) Tables 1667 uint32_t HistogramBaseAddressArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< Histogram Base Address - Arbitration Priority Control 1668 uint32_t HistogramBaseAddressMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< HISTOGRAM_BASE_ADDRESS_MEMORY_COMPRESSION_ENABLE 1669 uint32_t HistogramBaseAddressMemoryCompressionType : __CODEGEN_BITFIELD(10, 10) ; //!< HISTOGRAM_BASE_ADDRESS_MEMORY_COMPRESSION_TYPE 1670 uint32_t Reserved1579 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 1671 uint32_t HistogramBaseAddressCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< HISTOGRAM_BASE_ADDRESS_CACHE_SELECT 1672 uint32_t HistogramTiledMode : __CODEGEN_BITFIELD(13, 14) ; //!< HISTOGRAM_TILED_MODE 1673 uint32_t Reserved1583 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 1674 }; 1675 uint32_t Value; 1676 } DW49; 1677 union 1678 { 1679 struct 1680 { 1681 uint32_t DitheringLutDelta12 : __CODEGEN_BITFIELD( 0, 2) ; //!< Dithering LUT delta 12 1682 uint32_t Reserved1603 : __CODEGEN_BITFIELD( 3, 7) ; //!< Reserved 1683 uint32_t DitheringLutDelta13 : __CODEGEN_BITFIELD( 8, 10) ; //!< Dithering LUT delta 13 1684 uint32_t Reserved1611 : __CODEGEN_BITFIELD(11, 15) ; //!< Reserved 1685 uint32_t DitheringLutDelta14 : __CODEGEN_BITFIELD(16, 18) ; //!< Dithering LUT delta 14 1686 uint32_t Reserved1619 : __CODEGEN_BITFIELD(19, 23) ; //!< Reserved 1687 uint32_t DitheringLutDelta15 : __CODEGEN_BITFIELD(24, 26) ; //!< Dithering LUT delta 15 1688 uint32_t Reserved1627 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 1689 }; 1690 uint32_t Value; 1691 } DW50; 1692 union 1693 { 1694 struct 1695 { 1696 uint32_t DitheringLutDelta8 : __CODEGEN_BITFIELD( 0, 2) ; //!< Dithering LUT delta 8 1697 uint32_t Reserved1635 : __CODEGEN_BITFIELD( 3, 7) ; //!< Reserved 1698 uint32_t DitheringLutDelta9 : __CODEGEN_BITFIELD( 8, 10) ; //!< Dithering LUT delta 9 1699 uint32_t Reserved1643 : __CODEGEN_BITFIELD(11, 15) ; //!< Reserved 1700 uint32_t DitheringLutDelta10 : __CODEGEN_BITFIELD(16, 18) ; //!< Dithering LUT delta 10 1701 uint32_t Reserved1651 : __CODEGEN_BITFIELD(19, 23) ; //!< Reserved 1702 uint32_t DitheringLutDelta11 : __CODEGEN_BITFIELD(24, 26) ; //!< Dithering LUT delta 11 1703 uint32_t Reserved1659 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 1704 }; 1705 uint32_t Value; 1706 } DW51; 1707 union 1708 { 1709 struct 1710 { 1711 uint32_t DitheringLutDelta4 : __CODEGEN_BITFIELD( 0, 2) ; //!< Dithering LUT delta 4 1712 uint32_t Reserved1667 : __CODEGEN_BITFIELD( 3, 7) ; //!< Reserved 1713 uint32_t DitheringLutDelta5 : __CODEGEN_BITFIELD( 8, 10) ; //!< Dithering LUT delta 5 1714 uint32_t Reserved1675 : __CODEGEN_BITFIELD(11, 15) ; //!< Reserved 1715 uint32_t DitheringLutDelta6 : __CODEGEN_BITFIELD(16, 18) ; //!< Dithering LUT delta 6 1716 uint32_t Reserved1683 : __CODEGEN_BITFIELD(19, 23) ; //!< Reserved 1717 uint32_t DitheringLutDelta7 : __CODEGEN_BITFIELD(24, 26) ; //!< Dithering LUT delta 7 1718 uint32_t Reserved1691 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 1719 }; 1720 uint32_t Value; 1721 } DW52; 1722 union 1723 { 1724 struct 1725 { 1726 uint32_t DitheringLutDelta0 : __CODEGEN_BITFIELD( 0, 2) ; //!< Dithering LUT delta 0 1727 uint32_t Reserved1699 : __CODEGEN_BITFIELD( 3, 7) ; //!< Reserved 1728 uint32_t DitheringLutDelta1 : __CODEGEN_BITFIELD( 8, 10) ; //!< Dithering LUT delta 1 1729 uint32_t Reserved1707 : __CODEGEN_BITFIELD(11, 15) ; //!< Reserved 1730 uint32_t DitheringLutDelta2 : __CODEGEN_BITFIELD(16, 18) ; //!< Dithering LUT delta 2 1731 uint32_t Reserved1715 : __CODEGEN_BITFIELD(19, 23) ; //!< Reserved 1732 uint32_t DitheringLutDelta3 : __CODEGEN_BITFIELD(24, 26) ; //!< Dithering LUT delta 3 1733 uint32_t Reserved1723 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 1734 }; 1735 uint32_t Value; 1736 } DW53; 1737 union 1738 { 1739 struct 1740 { 1741 uint32_t BottomFieldVerticalScalingOffset : __CODEGEN_BITFIELD( 0, 23) ; //!< Bottom field vertical scaling offset 1742 uint32_t Reserved1752 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 1743 }; 1744 uint32_t Value; 1745 } DW54; 1746 union 1747 { 1748 struct 1749 { 1750 uint32_t Reserved1760 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1751 uint32_t BottomFieldBaseAddress : __CODEGEN_BITFIELD(12, 31) ; //!< Bottom field base address 1752 }; 1753 uint32_t Value; 1754 } DW55; 1755 union 1756 { 1757 struct 1758 { 1759 uint32_t BottomFieldBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Bottom field base address high 1760 uint32_t Reserved1808 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1761 }; 1762 uint32_t Value; 1763 } DW56; 1764 union 1765 { 1766 struct 1767 { 1768 uint32_t Reserved1824 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 1769 uint32_t BottomFieldSurfaceBaseAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< Bottom field Surface Base Address - Index to Memory Object Control State (MOCS) Tables 1770 uint32_t BottomFieldSurfaceBaseAddressArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< Bottom field Surface Base Address - Arbitration Priority Control 1771 uint32_t BottomFiledSurfaceBaseAddressMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< Bottom filed Surface Base Address - Memory Compression Enable 1772 uint32_t BottomFiledSurfaceBaseAddressMemoryCompressionType : __CODEGEN_BITFIELD(10, 10) ; //!< BOTTOM_FILED_SURFACE_BASE_ADDRESS_MEMORY_COMPRESSION_TYPE 1773 uint32_t Reserved1835 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 1774 uint32_t BottomFieldSurfaceTiledMode : __CODEGEN_BITFIELD(13, 14) ; //!< BOTTOM_FIELD_SURFACE_TILED_MODE 1775 uint32_t Reserved1839 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 1776 }; 1777 uint32_t Value; 1778 } DW57; 1779 union 1780 { 1781 struct 1782 { 1783 uint32_t BottomFieldSurfaceTileWalk : __CODEGEN_BITFIELD( 0, 0) ; //!< BOTTOM_FIELD_SURFACE_TILE_WALK 1784 uint32_t BottomFieldSurfaceTiled : __CODEGEN_BITFIELD( 1, 1) ; //!< BOTTOM_FIELD_SURFACE_TILED 1785 uint32_t BottomFieldSurfaceHalfPitchForChroma : __CODEGEN_BITFIELD( 2, 2) ; //!< Bottom field Surface Half Pitch For Chroma 1786 uint32_t BottomFieldSurfacePitch : __CODEGEN_BITFIELD( 3, 19) ; //!< Bottom field Surface Pitch 1787 uint32_t Reserved1878 : __CODEGEN_BITFIELD(22, 26) ; //!< Reserved 1788 uint32_t BottomFieldSurfaceInterleaveChromaEnable : __CODEGEN_BITFIELD(27, 27) ; //!< Bottom field Surface Interleave Chroma Enable 1789 uint32_t Reserved1884 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 1790 }; 1791 uint32_t Value; 1792 } DW58; 1793 union 1794 { 1795 struct 1796 { 1797 uint32_t BottomFieldSurfaceYOffsetForU : __CODEGEN_BITFIELD( 0, 15) ; //!< Bottom field Surface Y Offset For U 1798 uint32_t BottomFieldSurfaceXOffsetForU : __CODEGEN_BITFIELD(16, 31) ; //!< Bottom field Surface X Offset For U 1799 }; 1800 uint32_t Value; 1801 } DW59; 1802 union 1803 { 1804 struct 1805 { 1806 uint32_t BottomFieldSurfaceYOffsetForV : __CODEGEN_BITFIELD( 0, 15) ; //!< Bottom field Surface Y Offset For V 1807 uint32_t BottomFieldSurfaceXOffsetForV : __CODEGEN_BITFIELD(16, 31) ; //!< Bottom field Surface X Offset For V 1808 }; 1809 uint32_t Value; 1810 } DW60; 1811 1812 //! \name Local enumerations 1813 1814 enum SUBOPCODEB 1815 { 1816 SUBOPCODEB_SFCSTATE = 1, //!< No additional details 1817 }; 1818 1819 enum SUBOPCODEA 1820 { 1821 SUBOPCODEA_COMMON = 0, //!< No additional details 1822 }; 1823 1824 enum MEDIA_COMMAND_OPCODE 1825 { 1826 MEDIA_COMMAND_OPCODE_MEDIAHCPSFCMODE = 9, //!< Media HCP+SFC mode 1827 MEDIA_COMMAND_OPCODE_MEDIAMFXVEBOXSFCMODE = 10, //!< Media VDBOX/VEBOX+SFC mode 1828 }; 1829 1830 enum PIPELINE 1831 { 1832 PIPELINE_MEDIA = 2, //!< No additional details 1833 }; 1834 1835 enum COMMAND_TYPE 1836 { 1837 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1838 }; 1839 1840 //! \brief SFC_PIPE_MODE 1841 //! \details 1842 //! Note: for SFC Pipe mode set to VE-to-SFC AVS mode. 1843 //! IECP pipeline mode MUST be enabled. 1844 //! However, each sub-IECP feature can be turned on/off independently. 1845 enum SFC_PIPE_MODE 1846 { 1847 SFC_PIPE_MODE_UNNAMED0 = 0, //!< VD-to-SFC AVS 1848 SFC_PIPE_MODE_UNNAMED1 = 1, //!< VE-to-SFC AVS + IEF + Rotation 1849 SFC_PIPE_MODE_UNNAMED2 = 2, //!< HCP-to-SFC AVS 1850 SFC_PIPE_MODE_UNNAMED3 = 3, //!< Reserved 1851 SFC_PIPE_MODE_UNNAMED4 = 4, //!< VE-to-SFC Integral Image 1852 SFC_PIPE_MODE_UNNAMED5 = 5, //!< No additional details 1853 }; 1854 1855 //! \brief SFC_INPUT_CHROMA_SUB_SAMPLING 1856 //! \details 1857 //! This field shall be programmed according to video modes used in VDBOX. 1858 //! NOTE: SFC supports progressive input and output only (Interlaced/MBAFF 1859 //! is not supported). 1860 //! <table border="1"> 1861 //! <tbody> 1862 //! <tr> 1863 //! <td>Video Mode</td> 1864 //! <td>Surface Format</td> 1865 //! <td>SFC Input Chroma Sub-Sampling</td> 1866 //! <td>VD/VE Input Ordering Mode</td> 1867 //! </tr> 1868 //! <tr> 1869 //! <td>VC1 w/o LF and w/o OS Note: VC1 LF applies for either 1870 //! ILDB</td> 1871 //! <td>420 (NV12)</td> 1872 //! <td>1</td> 1873 //! <td>0</td> 1874 //! </tr> 1875 //! <tr> 1876 //! <td>VC1 w/ LF or w/ OS or w/ both Note: VC1 LF applies for either 1877 //! ILDB</td> 1878 //! <td /> 1879 //! <td>INVALID with SFC</td> 1880 //! <td>INVALID with SFC</td> 1881 //! </tr> 1882 //! <tr> 1883 //! <td>AVC w/o LF</td> 1884 //! <td>Monochrome</td> 1885 //! <td>0</td> 1886 //! <td>0</td> 1887 //! </tr> 1888 //! <tr> 1889 //! <td>AVC w/o LF</td> 1890 //! <td>420 (NV12)</td> 1891 //! <td>1</td> 1892 //! <td>0</td> 1893 //! </tr> 1894 //! <tr> 1895 //! <td>AVC with LF</td> 1896 //! <td>Monochrome</td> 1897 //! <td>0</td> 1898 //! <td>1</td> 1899 //! </tr> 1900 //! <tr> 1901 //! <td>AVC/VP8 with LF</td> 1902 //! <td>420 (NV12)</td> 1903 //! <td>1</td> 1904 //! <td>1</td> 1905 //! </tr> 1906 //! <tr> 1907 //! <td>VP8 w/o LF</td> 1908 //! <td>420 (NV12)</td> 1909 //! <td>1</td> 1910 //! <td>4</td> 1911 //! </tr> 1912 //! <tr> 1913 //! <td>JPEG (YUV Interleaved)</td> 1914 //! <td>Monochrome</td> 1915 //! <td>0</td> 1916 //! <td>2</td> 1917 //! </tr> 1918 //! <tr> 1919 //! <td>JPEG (YUV Interleaved)</td> 1920 //! <td>420</td> 1921 //! <td>1</td> 1922 //! <td>3</td> 1923 //! </tr> 1924 //! <tr> 1925 //! <td>JPEG (YUV Interleaved)</td> 1926 //! <td>422H_2Y</td> 1927 //! <td>2</td> 1928 //! <td>2</td> 1929 //! </tr> 1930 //! <tr> 1931 //! <td>JPEG (YUV Interleaved)</td> 1932 //! <td>422H_4Y</td> 1933 //! <td>2</td> 1934 //! <td>3</td> 1935 //! </tr> 1936 //! <tr> 1937 //! <td>JPEG (YUV Interleaved)</td> 1938 //! <td>444</td> 1939 //! <td>4</td> 1940 //! <td>2</td> 1941 //! </tr> 1942 //! </tbody> 1943 //! </table> 1944 //! This field shall be programmed according to Image enhancement modes used 1945 //! in VEBOX. 1946 //! 1947 //! <table border="1"> 1948 //! <tbody> 1949 //! <tr> 1950 //! <td>VEBOX MODE</td> 1951 //! <td>Surface Format</td> 1952 //! <td>SFC Input Chroma Sub Sampling</td> 1953 //! <td>VD/VE Input Ordering Mode</td> 1954 //! </tr> 1955 //! <tr> 1956 //! <td>Legacy DN/DI/IECP features</td> 1957 //! <td>Monochrome</td> 1958 //! <td>0</td> 1959 //! <td>0</td> 1960 //! </tr> 1961 //! <tr> 1962 //! <td>Legacy DN/DI/IECP features</td> 1963 //! <td>420 (NV12)</td> 1964 //! <td>1</td> 1965 //! <td>0</td> 1966 //! </tr> 1967 //! <tr> 1968 //! <td>Legacy DN/DI/IECP features</td> 1969 //! <td>422H</td> 1970 //! <td>2</td> 1971 //! <td>0</td> 1972 //! </tr> 1973 //! <tr> 1974 //! <td>Legacy DN/DI/IECP features</td> 1975 //! <td>444</td> 1976 //! <td>4</td> 1977 //! <td>0</td> 1978 //! </tr> 1979 //! <tr> 1980 //! <td>Capture/Camera pipe enabled(Demosaic)</td> 1981 //! <td>Monochrome</td> 1982 //! <td>0</td> 1983 //! <td>1</td> 1984 //! </tr> 1985 //! <tr> 1986 //! <td>Capture/Camera pipe enabled(Demosaic)</td> 1987 //! <td>420 (NV12)</td> 1988 //! <td>1</td> 1989 //! <td>1</td> 1990 //! </tr> 1991 //! <tr> 1992 //! <td>Capture/Camera pipe enabled(Demosaic)</td> 1993 //! <td>422H</td> 1994 //! <td>2</td> 1995 //! <td>1</td> 1996 //! </tr> 1997 //! <tr> 1998 //! <td>Capture/Camera pipe enabled(Demosaic)</td> 1999 //! <td>444</td> 2000 //! <td>4</td> 2001 //! <td>1</td> 2002 //! </tr> 2003 //! </tbody> 2004 //! </table> 2005 enum SFC_INPUT_CHROMA_SUB_SAMPLING 2006 { 2007 SFC_INPUT_CHROMA_SUB_SAMPLING_400 = 0, //!< SFC to insert UV channels 2008 SFC_INPUT_CHROMA_SUB_SAMPLING_420 = 1, //!< No additional details 2009 SFC_INPUT_CHROMA_SUB_SAMPLING_422HORIZONATAL = 2, //!< VD: 2:1:1 2010 SFC_INPUT_CHROMA_SUB_SAMPLING_444PROGRESSIVEINTERLEAVED = 4, //!< No additional details 2011 SFC_INPUT_CHROMA_SUB_SAMPLING_411 = 5, //!< No additional details 2012 }; 2013 2014 //! \brief VDVE_INPUT_ORDERING_MODE 2015 //! \details 2016 //! 2017 //! VD mode: (SFC pipe mode set as "0") 2018 2019 //! VE mode: (pipe mode set as "1 and 4") 2020 2021 //! 2022 //! For values for each mode, please refer to the table below: 2023 enum VDVE_INPUT_ORDERING_MODE 2024 { 2025 VDVE_INPUT_ORDERING_MODE_UNNAMED0 = 0, //!< 8x4 block column order, 64 pixel column 2026 VDVE_INPUT_ORDERING_MODE_UNNAMED1 = 1, //!< 4x4 block column order, 64 pixel column 2027 VDVE_INPUT_ORDERING_MODE_UNNAMED2 = 2, //!< No additional details 2028 VDVE_INPUT_ORDERING_MODE_UNNAMED3 = 3, //!< No additional details 2029 VDVE_INPUT_ORDERING_MODE_UNNAMED4 = 4, //!< 16x16 block VP8 row-scan order - no shift 2030 }; 2031 2032 //! \brief OUTPUT_SURFACE_FORMAT_TYPE 2033 //! \details 2034 //! SFC output surface format type. 2035 enum OUTPUT_SURFACE_FORMAT_TYPE 2036 { 2037 OUTPUT_SURFACE_FORMAT_TYPE_AYUV = 0, //!< AYUV 4:4:4 (8:8:8:8 MSB-A:Y:U:V) 2038 OUTPUT_SURFACE_FORMAT_TYPE_A8B8G8R8 = 1, //!< RGBA8 4:4:4:4 (8:8:8:8 MSB-A:B:G:R) 2039 OUTPUT_SURFACE_FORMAT_TYPE_A2R10G10B10 = 2, //!< RGBA10 10:10:10:2 (2:10:10:10 MSB-A:R:G:B) 2040 OUTPUT_SURFACE_FORMAT_TYPE_R5G6B5 = 3, //!< RGB 5:6:5 (5:6:5 MSB-R:G:B) 2041 OUTPUT_SURFACE_FORMAT_TYPE_NV12 = 4, //!< Planar NV12 4:2:0 8-bit 2042 OUTPUT_SURFACE_FORMAT_TYPE_YUYV = 5, //!< Packed YUYV 4:2:2 8-bit 2043 OUTPUT_SURFACE_FORMAT_TYPE_UYVY = 6, //!< Packed UYVY 4:2:2 8-bit 2044 OUTPUT_SURFACE_FORMAT_TYPE_INTEGRAL_32 = 7, //!< Packed integral Image 32-bit 2045 OUTPUT_SURFACE_FORMAT_TYPE_INTEGRAL_64 = 8, //!< Packed integral Image 64-bit 2046 OUTPUT_SURFACE_FORMAT_TYPE_P016 = 9, //!< P016 format 2047 OUTPUT_SURFACE_FORMAT_TYPE_Y216 = 10, //!< Y210 / Y216 FormatBitDepth = 0 => Y210BitDepth = 1 => Y216 2048 OUTPUT_SURFACE_FORMAT_TYPE_Y416 = 11, //!< Y410 / Y416 FormatBitDepth = 0 => Y410BitDepth = 1 => Y416 2049 OUTPUT_SURFACE_FORMAT_TYPE_A8B8G8R82 = 13, //!< Y8_NORM 2050 OUTPUT_SURFACE_FORMAT_TYPE_A8B8G8R83 = 14, //!< Y16_NORM 2051 OUTPUT_SURFACE_FORMAT_TYPE_A8B8G8R84 = 15, //!< R16G16B16A16 2052 }; 2053 2054 //! \brief OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_VERTICAL_DIRECTION 2055 //! \details 2056 //! This field specifies the fractional position of the bilinear filter for 2057 //! chroma downsampling. In the Y-axis. 2058 enum OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_VERTICAL_DIRECTION 2059 { 2060 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_VERTICAL_DIRECTION_08_LEFTFULLPIXEL = 0, //!< 0 (fraction_in_integer) 2061 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_VERTICAL_DIRECTION_18 = 1, //!< 1 (fraction_in_integer) 2062 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_VERTICAL_DIRECTION_14_28 = 2, //!< 2 (fraction_in_integer) 2063 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_VERTICAL_DIRECTION_38 = 3, //!< 3 (fraction_in_integer) 2064 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_VERTICAL_DIRECTION_12_48 = 4, //!< 4 (fraction_in_integer) 2065 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_VERTICAL_DIRECTION_58 = 5, //!< 5 (fraction_in_integer) 2066 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_VERTICAL_DIRECTION_34_68 = 6, //!< 6 (fraction_in_integer) 2067 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_VERTICAL_DIRECTION_78 = 7, //!< 7 (fraction_in_integer) 2068 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_VERTICAL_DIRECTION_88 = 8, //!< No additional details 2069 }; 2070 2071 //! \brief OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_HORIZONTAL_DIRECTION 2072 //! \details 2073 //! This field specifies the fractional position of the bilinear filter for 2074 //! chroma downsampling. In the X-axis. 2075 enum OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_HORIZONTAL_DIRECTION 2076 { 2077 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_HORIZONTAL_DIRECTION_08_LEFTFULLPIXEL = 0, //!< 0 (fraction_in_integer) 2078 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_HORIZONTAL_DIRECTION_18 = 1, //!< 1 (fraction_in_integer) 2079 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_HORIZONTAL_DIRECTION_14_28 = 2, //!< 2 (fraction_in_integer) 2080 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_HORIZONTAL_DIRECTION_38 = 3, //!< 3 (fraction_in_integer) 2081 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_HORIZONTAL_DIRECTION_12_48 = 4, //!< 4 (fraction_in_integer) 2082 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_HORIZONTAL_DIRECTION_58 = 5, //!< 5 (fraction_in_integer) 2083 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_HORIZONTAL_DIRECTION_34_68 = 6, //!< 6 (fraction_in_integer) 2084 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_HORIZONTAL_DIRECTION_78 = 7, //!< 7 (fraction_in_integer) 2085 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_HORIZONTAL_DIRECTION_88 = 8, //!< No additional details 2086 }; 2087 2088 //! \brief INPUT_COLOR_SPACE_0_YUV1_RGB 2089 //! \details 2090 //! THis specifies the color space of the input format. RGB is valid only 2091 //! with the VE-SFC mode. 2092 enum INPUT_COLOR_SPACE_0_YUV1_RGB 2093 { 2094 INPUT_COLOR_SPACE_0_YUV1_RGB_YUVCOLORSPACE = 0, //!< No additional details 2095 INPUT_COLOR_SPACE_0_YUV1_RGB_RGBCOLORSPACE = 1, //!< No additional details 2096 }; 2097 2098 //! \brief OUTPUT_COMPRESSION_FORMAT 2099 //! \details 2100 //! Specifies the 5-bit compression format. 2101 enum OUTPUT_COMPRESSION_FORMAT 2102 { 2103 OUTPUT_COMPRESSION_FORMAT_RGBA16FLOAT = 1, //!< No additional details 2104 OUTPUT_COMPRESSION_FORMAT_Y210 = 2, //!< No additional details 2105 OUTPUT_COMPRESSION_FORMAT_YUY2 = 3, //!< No additional details 2106 OUTPUT_COMPRESSION_FORMAT_Y410_1010102 = 4, //!< No additional details 2107 OUTPUT_COMPRESSION_FORMAT_Y216 = 5, //!< No additional details 2108 OUTPUT_COMPRESSION_FORMAT_Y416 = 6, //!< No additional details 2109 OUTPUT_COMPRESSION_FORMAT_P010 = 7, //!< No additional details 2110 OUTPUT_COMPRESSION_FORMAT_P016 = 8, //!< No additional details 2111 OUTPUT_COMPRESSION_FORMAT_AYUV = 9, //!< No additional details 2112 OUTPUT_COMPRESSION_FORMAT_ARGB8B = 10, //!< No additional details 2113 OUTPUT_COMPRESSION_FORMAT_YCRCBSWAPY = 11, //!< No additional details 2114 OUTPUT_COMPRESSION_FORMAT_YCRCBSWAPUV = 12, //!< No additional details 2115 OUTPUT_COMPRESSION_FORMAT_YCRCBSWAPUVY = 13, //!< No additional details 2116 OUTPUT_COMPRESSION_FORMAT_RGB10B = 14, //!< No additional details 2117 OUTPUT_COMPRESSION_FORMAT_NV21NV12 = 15, //!< No additional details 2118 }; 2119 2120 //! \brief IEF_ENABLE 2121 //! \details 2122 //! Restriction : For Integral Image Mode and VD Mode, this field is 2123 //! Reserved and MBZ. 2124 enum IEF_ENABLE 2125 { 2126 IEF_ENABLE_DISABLE = 0, //!< IEF Filter is Disabled 2127 IEF_ENABLE_ENABLE = 1, //!< IEF Filter is Enabled 2128 }; 2129 2130 //! \brief IEF4SMOOTH_ENABLE_ 2131 //! \details 2132 //! Restriction : For Integral Image Mode, this field is Reserved and MBZ. 2133 enum IEF4SMOOTH_ENABLE_ 2134 { 2135 IEF4SMOOTH_ENABLE_UNNAMED0 = 0, //!< IEF is operating as a content adaptive detail filter based on 5x5 region. 2136 IEF4SMOOTH_ENABLE_UNNAMED1 = 1, //!< IEF is operating as a content adaptive smooth filter based on 3x3 region 2137 }; 2138 2139 //! \brief AVS_FILTER_MODE 2140 //! \details 2141 //! In VD-to-SFC mode, value of 1 is not allowed. 2142 enum AVS_FILTER_MODE 2143 { 2144 AVS_FILTER_MODE_5X5POLY_PHASEFILTERBILINEAR_ADAPTIVE = 0, //!< No additional details 2145 AVS_FILTER_MODE_8X8POLY_PHASEFILTERBILINEAR_ADAPTIVE = 1, //!< No additional details 2146 AVS_FILTER_MODE_BILINEARFILTERONLY = 2, //!< No additional details 2147 }; 2148 2149 //! \brief ADAPTIVE_FILTER_FOR_ALL_CHANNELS 2150 //! \details 2151 //! The field can be enabled if 8-tap Adaptive filter mode is on. Else it 2152 //! should be disabled. 2153 enum ADAPTIVE_FILTER_FOR_ALL_CHANNELS 2154 { 2155 ADAPTIVE_FILTER_FOR_ALL_CHANNELS_DISABLEADAPTIVEFILTERONUVRBCHANNELS = 0, //!< No additional details 2156 ADAPTIVE_FILTER_FOR_ALL_CHANNELS_ENABLEADAPTIVEFILTERONUVRBCHANNELS = 1, //!< 8-tap Adaptive Filter Mode is on 2157 }; 2158 2159 enum AVS_SCALING_ENABLE 2160 { 2161 AVS_SCALING_ENABLE_DISABLE = 0, //!< The scaling factor is ignored and a scaling ratio of 1:1 is assumed. 2162 AVS_SCALING_ENABLE_ENABLE = 1, //!< No additional details 2163 }; 2164 2165 enum BYPASS_Y_ADAPTIVE_FILTERING 2166 { 2167 BYPASS_Y_ADAPTIVE_FILTERING_ENABLEYADAPTIVEFILTERING = 0, //!< No additional details 2168 BYPASS_Y_ADAPTIVE_FILTERING_DISABLEYADAPTIVEFILTERING = 1, //!< The Y direction will use Default Sharpness Level to blend between the smooth and sharp filters rather than the calculated value. 2169 }; 2170 2171 enum BYPASS_X_ADAPTIVE_FILTERING 2172 { 2173 BYPASS_X_ADAPTIVE_FILTERING_ENABLEXADAPTIVEFILTERING = 0, //!< No additional details 2174 BYPASS_X_ADAPTIVE_FILTERING_DISABLEXADAPTIVEFILTERING = 1, //!< The X direction will use Default Sharpness Level to blend between the smooth and sharp filters rather than the calculated value. 2175 }; 2176 2177 //! \brief ROTATION_MODE 2178 //! \details 2179 //! SFC rotation (90, 180 and 270) should be set only on VEBox input mode 2180 //! and SFC output set to TileY. 2181 //! Restriction: 2182 //! 2183 //! For Integral Image Mode, this field is Reserved and MBZ. 2184 2185 //! For VDBox Mode, this field is Reserved and MBZ. 2186 2187 //! For linear or TileX SFC output, this field is Reserved and 2188 //! MBZ. 2189 2190 //! 2191 enum ROTATION_MODE 2192 { 2193 ROTATION_MODE_0_DEGREES = 0, //!< No additional details 2194 ROTATION_MODE_90CLOCKWISE = 1, //!< No additional details 2195 ROTATION_MODE_180CLOCKWISE = 2, //!< No additional details 2196 ROTATION_MODE_270CLOCKWISE = 3, //!< No additional details 2197 }; 2198 2199 //! \brief BITDEPTH 2200 //! \details 2201 //! This field is valid only for output formats P016/Y216/Y416. This field 2202 //! is used to specify how many of the LSB bits have valid data. 2203 enum BITDEPTH 2204 { 2205 BITDEPTH_10BITFORMAT = 0, //!< Higher 10 bits are valid and lower 6 bits are 0 2206 }; 2207 2208 //! \brief COMPRESSION_TYPE 2209 //! \details 2210 //! This field is applicable only when Memory compression is enabled. 2211 enum COMPRESSION_TYPE 2212 { 2213 COMPRESSION_TYPE_MEDIACOMPRESSIONENABLED = 0, //!< No additional details 2214 COMPRESSION_TYPE_RENDERCOMPRESSIONENABLED = 1, //!< No additional details 2215 }; 2216 2217 //! \brief OUTPUT_FRAME_SURFACE_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2218 //! \details 2219 //! This must be set to 0 2220 enum OUTPUT_FRAME_SURFACE_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2221 { 2222 OUTPUT_FRAME_SURFACE_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_DISABLE = 0, //!< This field must be programmed to 0 2223 }; 2224 2225 //! \brief AVS_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_ENABLE 2226 //! \details 2227 //! This bit control memory compression for this surface 2228 enum AVS_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_ENABLE 2229 { 2230 AVS_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_ENABLE_DISABLE = 0, //!< No additional details 2231 }; 2232 2233 //! \brief AVS_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 2234 //! \details 2235 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2236 //! font-size: 13.3333330154419px; line-height: normal;">Distinguishes 2237 //! vertical from horizontal compression. Please refer to vol1a? 2238 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2239 //! font-size: 13.3333330154419px; line-height: normal;">Memory Data Formats 2240 //! chapter - section 2241 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2242 //! font-size: 13.3333330154419px; line-height: normal;">?media Memory 2243 //! Compression for more details. 2244 enum AVS_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 2245 { 2246 AVS_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 2247 }; 2248 2249 //! \brief AVS_LINE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2250 //! \details 2251 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2252 //! font-size: 13.3333330154419px; line-height: normal;">This field controls 2253 //! if the Row Store is going to store inside Media Cache (rowstore cache) 2254 //! or to LLC. 2255 enum AVS_LINE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2256 { 2257 AVS_LINE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_LLC = 0, //!< Buffer going to LLC 2258 }; 2259 2260 //! \brief AVS_LINE_BUFFER_TILED_MODE 2261 //! \details 2262 //! For Media Surfaces: 2263 //! This field specifies the tiled resource mode. 2264 enum AVS_LINE_BUFFER_TILED_MODE 2265 { 2266 AVS_LINE_BUFFER_TILED_MODE_TRMODENONE = 0, //!< No tiled resource 2267 AVS_LINE_BUFFER_TILED_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 2268 AVS_LINE_BUFFER_TILED_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 2269 }; 2270 2271 //! \brief IEF_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_ENABLE 2272 //! \details 2273 //! 2274 //! style="color: rgb(35, 35, 35); font-family: Arial, 2275 //! sans-serif; font-size: 13.3333330154419px; line-height: normal;">Memory 2276 //! compression is not supported for this surface 2277 //! 2278 //! 2279 //! style="color: rgb(35, 35, 35); font-family: Arial, 2280 //! sans-serif; font-size: 13.3333330154419px; line-height: normal;">Must be 2281 //! 0. 2282 //! 2283 //! /> 2284 enum IEF_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_ENABLE 2285 { 2286 IEF_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_ENABLE_DISABLE = 0, //!< No additional details 2287 }; 2288 2289 //! \brief IEF_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 2290 //! \details 2291 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2292 //! font-size: 13.3333330154419px; line-height: normal;">Distinguishes 2293 //! vertical from horizontal compression. 2294 enum IEF_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 2295 { 2296 IEF_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE_UNNAMED0 = 0, //!< No additional details 2297 }; 2298 2299 //! \brief IEF_LINE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2300 //! \details 2301 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2302 //! font-size: 13.3333330154419px; line-height: normal;">This field controls 2303 //! if the Row Store is going to store inside Media Cache (rowstore cache) 2304 //! or to LLC. 2305 enum IEF_LINE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2306 { 2307 IEF_LINE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_LLC = 0, //!< Buffer going to LLC 2308 }; 2309 2310 //! \brief IEF_LINE_BUFFER_TILED_MODE 2311 //! \details 2312 //! For Media Surfaces: 2313 //! This field specifies the tiled resource mode. 2314 enum IEF_LINE_BUFFER_TILED_MODE 2315 { 2316 IEF_LINE_BUFFER_TILED_MODE_TRMODENONE = 0, //!< No tiled resource 2317 IEF_LINE_BUFFER_TILED_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 2318 IEF_LINE_BUFFER_TILED_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 2319 }; 2320 2321 //! \brief SFD_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_ENABLE 2322 //! \details 2323 //! 2324 //! style="color: rgb(35, 35, 35); font-family: Arial, 2325 //! sans-serif; font-size: 13.3333330154419px; line-height: normal;">Memory 2326 //! compression is not supported for this surface 2327 //! 2328 //! 2329 //! style="color: rgb(35, 35, 35); font-family: Arial, 2330 //! sans-serif; font-size: 13.3333330154419px; line-height: normal;">Must be 2331 //! 0. 2332 //! 2333 //! /> 2334 enum SFD_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_ENABLE 2335 { 2336 SFD_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_ENABLE_DISABLE = 0, //!< No additional details 2337 }; 2338 2339 //! \brief SFD_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 2340 //! \details 2341 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2342 //! font-size: 13.3333330154419px; line-height: normal;">Distinguishes 2343 //! vertical from horizontal compression. Please refer to vol1a 2344 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2345 //! font-size: 13.3333330154419px; line-height: normal;">Memory Data Formats 2346 //! chapter - section 2347 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2348 //! font-size: 13.3333330154419px; line-height: normal;"> media Memory 2349 //! Compression for more details. 2350 enum SFD_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 2351 { 2352 SFD_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE_UNNAMED0 = 0, //!< No additional details 2353 }; 2354 2355 //! \brief SFD_LINE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2356 //! \details 2357 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2358 //! font-size: 13.3333330154419px; line-height: normal;">This field controls 2359 //! if the Row Store is going to store inside Media Cache (rowstore cache) 2360 //! or to LLC. 2361 enum SFD_LINE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2362 { 2363 SFD_LINE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_LLC = 0, //!< Buffer going to LLC 2364 SFD_LINE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_MEDIASTORAGE = 1, //!< style="margin:0in 0in 8pt">Data will first cache in Media Storage 2365 }; 2366 2367 //! \brief SFD_LINE_BUFFER_TILED_MODE 2368 //! \details 2369 //! For Media Surfaces: 2370 //! This field specifies the tiled resource mode. 2371 enum SFD_LINE_BUFFER_TILED_MODE 2372 { 2373 SFD_LINE_BUFFER_TILED_MODE_TRMODENONE = 0, //!< No tiled resource 2374 SFD_LINE_BUFFER_TILED_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 2375 SFD_LINE_BUFFER_TILED_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 2376 }; 2377 2378 //! \brief OUTPUT_SURFACE_TILE_WALK 2379 //! \details 2380 //! This field specifies the type of memory tiling (XMajor or YMajor) 2381 //! employed to tile this surface. See Memory Interface Functions for 2382 //! details on memory tiling and restrictions. 2383 enum OUTPUT_SURFACE_TILE_WALK 2384 { 2385 OUTPUT_SURFACE_TILE_WALK_TILEWALKXMAJOR = 0, //!< No additional details 2386 OUTPUT_SURFACE_TILE_WALK_TILEWALKYMAJOR = 1, //!< No additional details 2387 }; 2388 2389 //! \brief OUTPUT_SURFACE_TILED_MODE 2390 //! \details 2391 //! This field specifies which tiled mode the surface is. 2392 enum OUTPUT_SURFACE_TILED_MODE 2393 { 2394 OUTPUT_SURFACE_TILED_LINEAR = 0, //!< Linear 2395 OUTPUT_SURFACE_TILED_S = 1, //!< TileS(64K) 2396 OUTPUT_SURFACE_TILED_X = 2, //!< X Major 2397 OUTPUT_SURFACE_TILED_F = 3, //!< Tile F 2398 }; 2399 2400 //! \brief AVS_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_ENABLE 2401 //! \details 2402 //! 2403 //! style="color: rgb(35, 35, 35); font-family: Arial, 2404 //! sans-serif; font-size: 13.3333330154419px; line-height: normal;">Memory 2405 //! compression is not supported for this surface 2406 //! 2407 //! 2408 //! style="color: rgb(35, 35, 35); font-family: Arial, 2409 //! sans-serif; font-size: 13.3333330154419px; line-height: normal;">Must be 2410 //! 0. 2411 //! 2412 //! /> 2413 enum AVS_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_ENABLE 2414 { 2415 AVS_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_ENABLE_DISABLE = 0, //!< No additional details 2416 }; 2417 2418 //! \brief AVS_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 2419 //! \details 2420 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2421 //! font-size: 13.3333330154419px; line-height: normal;">Distinguishes 2422 //! vertical from horizontal compression. Please refer to vol1a 2423 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2424 //! font-size: 13.3333330154419px; line-height: normal;">Memory Data Formats 2425 //! chapter - section 2426 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2427 //! font-size: 13.3333330154419px; line-height: normal;"> media Memory 2428 //! Compression for more details. 2429 enum AVS_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 2430 { 2431 AVS_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE_UNNAMED0 = 0, //!< No additional details 2432 }; 2433 2434 //! \brief AVS_LINE_TILE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2435 //! \details 2436 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2437 //! font-size: 13.3333330154419px; line-height: normal;">This field controls 2438 //! if the Row Store is going to store inside Media Cache (rowstore cache) 2439 //! or to LLC. 2440 enum AVS_LINE_TILE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2441 { 2442 AVS_LINE_TILE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_LLC = 0, //!< Buffer going to LLC 2443 }; 2444 2445 //! \brief AVS_LINE_TILE_BUFFER_TILED_MODE 2446 //! \details 2447 //! For Media Surfaces: 2448 //! This field specifies the tiled resource mode. 2449 enum AVS_LINE_TILE_BUFFER_TILED_MODE 2450 { 2451 AVS_LINE_TILE_BUFFER_TILED_MODE_TRMODENONE = 0, //!< No tiled resource 2452 AVS_LINE_TILE_BUFFER_TILED_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 2453 AVS_LINE_TILE_BUFFER_TILED_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 2454 }; 2455 2456 //! \brief IEF_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_ENABLE 2457 //! \details 2458 //! 2459 //! style="color: rgb(35, 35, 35); font-family: Arial, 2460 //! sans-serif; font-size: 13.3333330154419px; line-height: normal;">Memory 2461 //! compression is not supported for this surface 2462 //! 2463 //! 2464 //! style="color: rgb(35, 35, 35); font-family: Arial, 2465 //! sans-serif; font-size: 13.3333330154419px; line-height: normal;">Must be 2466 //! 0. 2467 //! 2468 //! /> 2469 enum IEF_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_ENABLE 2470 { 2471 IEF_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_ENABLE_DISABLE = 0, //!< No additional details 2472 }; 2473 2474 //! \brief IEF_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 2475 //! \details 2476 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2477 //! font-size: 13.3333330154419px; line-height: normal;">Distinguishes 2478 //! vertical from horizontal compression. Please refer to vol1a 2479 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2480 //! font-size: 13.3333330154419px; line-height: normal;">Memory Data Formats 2481 //! chapter - section 2482 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2483 //! font-size: 13.3333330154419px; line-height: normal;"> media Memory 2484 //! Compression for more details. 2485 enum IEF_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 2486 { 2487 IEF_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE_UNNAMED0 = 0, //!< No additional details 2488 }; 2489 2490 //! \brief IEF_LINE_TILE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2491 //! \details 2492 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2493 //! font-size: 13.3333330154419px; line-height: normal;">This field controls 2494 //! if the Row Store is going to store inside Media Cache (rowstore cache) 2495 //! or to LLC. 2496 enum IEF_LINE_TILE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2497 { 2498 IEF_LINE_TILE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_LLC = 0, //!< Buffer going to LLC 2499 }; 2500 2501 //! \brief IEF_LINE_TILE_BUFFER_TILED_MODE 2502 //! \details 2503 //! For Media Surfaces: 2504 //! This field specifies the tiled resource mode. 2505 enum IEF_LINE_TILE_BUFFER_TILED_MODE 2506 { 2507 IEF_LINE_TILE_BUFFER_TILED_MODE_TRMODENONE = 0, //!< No tiled resource 2508 IEF_LINE_TILE_BUFFER_TILED_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 2509 IEF_LINE_TILE_BUFFER_TILED_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 2510 }; 2511 2512 //! \brief SFD_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_ENABLE 2513 //! \details 2514 //! 2515 //! style="color: rgb(35, 35, 35); font-family: Arial, 2516 //! sans-serif; font-size: 13.3333330154419px; line-height: normal;">Memory 2517 //! compression is not supported for this surface 2518 //! 2519 //! 2520 //! style="color: rgb(35, 35, 35); font-family: Arial, 2521 //! sans-serif; font-size: 13.3333330154419px; line-height: normal;">Must be 2522 //! 0. 2523 //! 2524 //! /> 2525 enum SFD_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_ENABLE 2526 { 2527 SFD_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_ENABLE_DISABLE = 0, //!< No additional details 2528 }; 2529 2530 //! \brief SFD_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 2531 //! \details 2532 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2533 //! font-size: 13.3333330154419px; line-height: normal;">Distinguishes 2534 //! vertical from horizontal compression. Please refer to vol1a 2535 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2536 //! font-size: 13.3333330154419px; line-height: normal;">Memory Data Formats 2537 //! chapter - section 2538 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2539 //! font-size: 13.3333330154419px; line-height: normal;"> media Memory 2540 //! Compression for more details. 2541 enum SFD_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 2542 { 2543 SFD_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE_UNNAMED0 = 0, //!< No additional details 2544 }; 2545 2546 //! \brief SFD_LINE_TILE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2547 //! \details 2548 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2549 //! font-size: 13.3333330154419px; line-height: normal;">This field controls 2550 //! if the Row Store is going to store inside Media Cache (rowstore cache) 2551 //! or to LLC. 2552 enum SFD_LINE_TILE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2553 { 2554 SFD_LINE_TILE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_LLC = 0, //!< Buffer going to LLC 2555 }; 2556 2557 //! \brief SFD_LINE_TILE_BUFFER_TILED_MODE 2558 //! \details 2559 //! For Media Surfaces: 2560 //! This field specifies the tiled resource mode. 2561 enum SFD_LINE_TILE_BUFFER_TILED_MODE 2562 { 2563 SFD_LINE_TILE_BUFFER_TILED_MODE_TRMODENONE = 0, //!< No tiled resource 2564 SFD_LINE_TILE_BUFFER_TILED_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 2565 SFD_LINE_TILE_BUFFER_TILED_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 2566 }; 2567 2568 //! \brief HISTOGRAM_BASE_ADDRESS_MEMORY_COMPRESSION_ENABLE 2569 //! \details 2570 //! 2571 //! style="color: rgb(35, 35, 35); font-family: Arial, 2572 //! sans-serif; font-size: 13.3333330154419px; line-height: normal;">Memory 2573 //! compression is not supported for this surface 2574 //! 2575 //! 2576 //! style="color: rgb(35, 35, 35); font-family: Arial, 2577 //! sans-serif; font-size: 13.3333330154419px; line-height: normal;">Must be 2578 //! 0. 2579 //! 2580 //! /> 2581 enum HISTOGRAM_BASE_ADDRESS_MEMORY_COMPRESSION_ENABLE 2582 { 2583 HISTOGRAM_BASE_ADDRESS_MEMORY_COMPRESSION_ENABLE_DISABLE = 0, //!< No additional details 2584 }; 2585 2586 //! \brief HISTOGRAM_BASE_ADDRESS_MEMORY_COMPRESSION_TYPE 2587 //! \details 2588 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2589 //! font-size: 13.3333330154419px; line-height: normal;">Distinguishes Media 2590 //! or 3D compression. 2591 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2592 //! font-size: 13.3333330154419px; line-height: normal;">Memory Data Formats 2593 //! chapter - section 2594 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2595 //! font-size: 13.3333330154419px; line-height: normal;"> media Memory 2596 //! Compression for more details. 2597 enum HISTOGRAM_BASE_ADDRESS_MEMORY_COMPRESSION_TYPE 2598 { 2599 HISTOGRAM_BASE_ADDRESS_MEMORY_COMPRESSION_TYPE_UNNAMED0 = 0, //!< No additional details 2600 }; 2601 2602 //! \brief HISTOGRAM_BASE_ADDRESS_CACHE_SELECT 2603 //! \details 2604 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2605 //! font-size: 13.3333330154419px; line-height: normal;">This field controls 2606 //! if the Histogram need to be cached in LLC or not. 2607 enum HISTOGRAM_BASE_ADDRESS_CACHE_SELECT 2608 { 2609 HISTOGRAM_BASE_ADDRESS_CACHE_SELECT_LLC = 0, //!< Buffer going to LLC 2610 }; 2611 2612 //! \brief HISTOGRAM_TILED_MODE 2613 //! \details 2614 //! For Media Surfaces: 2615 //! This field specifies the tiled resource mode. 2616 enum HISTOGRAM_TILED_MODE 2617 { 2618 HISTOGRAM_TILED_MODE_TRMODENONE = 0, //!< No tiled resource 2619 HISTOGRAM_TILED_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 2620 HISTOGRAM_TILED_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 2621 }; 2622 2623 //! \brief BOTTOM_FILED_SURFACE_BASE_ADDRESS_MEMORY_COMPRESSION_TYPE 2624 //! \details 2625 //! This field is applicable only when memory compression is enabled 2626 enum BOTTOM_FILED_SURFACE_BASE_ADDRESS_MEMORY_COMPRESSION_TYPE 2627 { 2628 BOTTOM_FILED_SURFACE_BASE_ADDRESS_MEMORY_COMPRESSION_TYPE_MEDIACOMPRESSIONENABLED = 0, //!< No additional details 2629 BOTTOM_FILED_SURFACE_BASE_ADDRESS_MEMORY_COMPRESSION_TYPE_RENDERCOMPRESSIONENABLED = 1, //!< No additional details 2630 }; 2631 2632 enum BOTTOM_FIELD_SURFACE_TILED_MODE 2633 { 2634 BOTTOM_FIELD_SURFACE_TILED_MODE_TRMODENONE = 0, //!< No tiled resource 2635 BOTTOM_FIELD_SURFACE_TILED_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 2636 BOTTOM_FIELD_SURFACE_TILED_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 2637 }; 2638 2639 //! \brief BOTTOM_FIELD_SURFACE_TILE_WALK 2640 //! \details 2641 //! This field specifies the type of memory tiling (XMajor or YMajor) 2642 //! employed to tile this surface. See Memory Interface Functions for 2643 //! details on memory tiling and restrictions. 2644 enum BOTTOM_FIELD_SURFACE_TILE_WALK 2645 { 2646 BOTTOM_FIELD_SURFACE_TILE_WALK_TILEWALKXMAJOR = 0, //!< No additional details 2647 BOTTOM_FIELD_SURFACE_TILE_WALK_TILEWALKYMAJOR = 1, //!< No additional details 2648 }; 2649 2650 //! \brief BOTTOM_FIELD_SURFACE_TILED 2651 //! \details 2652 //! This field specifies whether the surface is tiled. 2653 enum BOTTOM_FIELD_SURFACE_TILED 2654 { 2655 BOTTOM_FIELD_SURFACE_TILED_FALSE = 0, //!< Linear 2656 BOTTOM_FIELD_SURFACE_TILED_TRUE = 1, //!< Tiled 2657 }; 2658 2659 //! \name Initializations 2660 2661 //! \brief Explicit member initialization function 2662 SFC_STATE_CMD(); 2663 2664 static const size_t dwSize = 61; 2665 static const size_t byteSize = 244; 2666 }; 2667 2668 //! 2669 //! \brief SFC_AVS_LUMA_Coeff_Table 2670 //! \details 2671 //! This command is sent from VDBOX/VEBOX to SFC pipeline at the start of 2672 //! each frame once the lock request is granted. 2673 //! 2674 struct SFC_AVS_LUMA_Coeff_Table_CMD 2675 { 2676 union 2677 { 2678 struct 2679 { 2680 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2681 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2682 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODEB 2683 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPCODEA 2684 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_COMMAND_OPCODE 2685 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 2686 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2687 }; 2688 uint32_t Value; 2689 } DW0; 2690 union 2691 { 2692 struct 2693 { 2694 uint32_t Table0XFilterCoefficientN0 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 0X Filter Coefficient[[n],0] 2695 uint32_t Table0YFilterCoefficientN0 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 0Y Filter Coefficient[[n],0] 2696 uint32_t Table0XFilterCoefficientN1 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 0X Filter Coefficient[[n],1] 2697 uint32_t Table0YFilterCoefficientN1 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 0Y Filter Coefficient[[n],1] 2698 }; 2699 uint32_t Value; 2700 } DW1; 2701 union 2702 { 2703 struct 2704 { 2705 uint32_t Table0XFilterCoefficientN2 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 0X Filter Coefficient[[n],2] 2706 uint32_t Table0YFilterCoefficientN2 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 0Y Filter Coefficient[[n],2] 2707 uint32_t Table0XFilterCoefficientN3 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 0X Filter Coefficient[[n],3] 2708 uint32_t Table0YFilterCoefficientN3 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 0Y Filter Coefficient[[n],3] 2709 }; 2710 uint32_t Value; 2711 } DW2; 2712 union 2713 { 2714 struct 2715 { 2716 uint32_t Table0XFilterCoefficientN4 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 0X Filter Coefficient[[n],4] 2717 uint32_t Table0YFilterCoefficientN4 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 0Y Filter Coefficient[[n],4] 2718 uint32_t Table0XFilterCoefficientN5 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 0X Filter Coefficient[[n],5] 2719 uint32_t Table0YFilterCoefficientN5 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 0Y Filter Coefficient[[n],5] 2720 }; 2721 uint32_t Value; 2722 } DW3; 2723 union 2724 { 2725 struct 2726 { 2727 uint32_t Table0XFilterCoefficientN6 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 0X Filter Coefficient[[n],6] 2728 uint32_t Table0YFilterCoefficientN6 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 0Y Filter Coefficient[[n],6] 2729 uint32_t Table0XFilterCoefficientN7 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 0X Filter Coefficient[[n],7] 2730 uint32_t Table0YFilterCoefficientN7 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 0Y Filter Coefficient[[n],7] 2731 }; 2732 uint32_t Value; 2733 } DW4; 2734 uint32_t FilterCoefficients[124]; //!< Filter Coefficients 2735 2736 //! \name Local enumerations 2737 2738 enum SUBOPCODEB 2739 { 2740 SUBOPCODEB_SFCAVSLUMACOEFFTABLE = 5, //!< No additional details 2741 }; 2742 2743 enum SUBOPCODEA 2744 { 2745 SUBOPCODEA_COMMON = 0, //!< No additional details 2746 }; 2747 2748 enum MEDIA_COMMAND_OPCODE 2749 { 2750 MEDIA_COMMAND_OPCODE_MEDIAMISC = 10, //!< Media MFX/VEBOX+SFC Mode 2751 }; 2752 2753 enum PIPELINE 2754 { 2755 PIPELINE_MEDIA = 2, //!< No additional details 2756 }; 2757 2758 enum COMMAND_TYPE 2759 { 2760 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2761 }; 2762 2763 //! \name Initializations 2764 2765 //! \brief Explicit member initialization function 2766 SFC_AVS_LUMA_Coeff_Table_CMD(); 2767 2768 static const size_t dwSize = 129; 2769 static const size_t byteSize = 516; 2770 }; 2771 2772 //! 2773 //! \brief SFC_AVS_CHROMA_Coeff_Table 2774 //! \details 2775 //! This command is sent from VDBOX/VEBOX to SFC pipeline at the start of 2776 //! each frame once the lock request is granted. 2777 //! 2778 struct SFC_AVS_CHROMA_Coeff_Table_CMD 2779 { 2780 union 2781 { 2782 struct 2783 { 2784 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2785 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2786 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODEB 2787 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPCODEA 2788 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_COMMAND_OPCODE 2789 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 2790 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2791 }; 2792 uint32_t Value; 2793 } DW0; 2794 union 2795 { 2796 struct 2797 { 2798 uint32_t Table1XFilterCoefficientN2 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 1X Filter Coefficient[[n],2] 2799 uint32_t Table1YFilterCoefficientN2 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 1Y Filter Coefficient[[n],2] 2800 uint32_t Table1XFilterCoefficientN3 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 1X Filter Coefficient[[n],3] 2801 uint32_t Table1YFilterCoefficientN3 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 1Y Filter Coefficient[[n],3] 2802 }; 2803 uint32_t Value; 2804 } DW1; 2805 union 2806 { 2807 struct 2808 { 2809 uint32_t Table1XFilterCoefficientN4 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 1X Filter Coefficient[[n],4] 2810 uint32_t Table1YFilterCoefficientN4 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 1Y Filter Coefficient[[n],4] 2811 uint32_t Table1XFilterCoefficientN5 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 1X Filter Coefficient[[n],5] 2812 uint32_t Table1YFilterCoefficientN5 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 1Y Filter Coefficient[[n],5] 2813 }; 2814 uint32_t Value; 2815 } DW2; 2816 uint32_t FilterCoefficients[62]; //!< Filter Coefficients 2817 2818 //! \name Local enumerations 2819 2820 enum SUBOPCODEB 2821 { 2822 SUBOPCODEB_SFCAVSCHROMACOEFFTABLE = 6, //!< No additional details 2823 }; 2824 2825 enum SUBOPCODEA 2826 { 2827 SUBOPCODEA_COMMON = 0, //!< No additional details 2828 }; 2829 2830 enum MEDIA_COMMAND_OPCODE 2831 { 2832 MEDIA_COMMAND_OPCODE_MEDIAMISC = 10, //!< Media MFX/VEBOX+SFC Mode 2833 }; 2834 2835 enum PIPELINE 2836 { 2837 PIPELINE_MEDIA = 2, //!< No additional details 2838 }; 2839 2840 enum COMMAND_TYPE 2841 { 2842 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2843 }; 2844 2845 //! \name Initializations 2846 2847 //! \brief Explicit member initialization function 2848 SFC_AVS_CHROMA_Coeff_Table_CMD(); 2849 2850 static const size_t dwSize = 65; 2851 static const size_t byteSize = 260; 2852 }; 2853 2854 }; 2855 2856 #pragma pack() 2857 2858 #endif // __MHW_SFC_HWCMD_XE_XPM_H__ 2859