1 /*===================== begin_copyright_notice ==================================
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3 # Copyright (c) 2020-2021, Intel Corporation
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23 ======================= end_copyright_notice ==================================*/
24 //!
25 //! \file codechal_hw_xe_xpm_plus.cpp
26 //! \brief Implements HW interface layer for PVC used on all OSs.
27 //! \details Implements HW interface layer for PVC to be used on on all operating systems/DDIs, across CODECHAL components.
28 //! This module must not contain any OS dependent code.
29 //!
30
31 #include "codechal_hw_xe_xpm_plus.h"
32 #include "media_interfaces_pvc.h"//temporary include for getting avp interface
33 #include "codechal_hw_g12_X.h"
34 #include "mhw_render_g12_X.h"
35 #include "mhw_vdbox_hcp_hwcmd_g12_X.h" // temporary include for calculating size of various hardware commands
36 #include "mhw_vdbox_mfx_hwcmd_g11_X.h"
37 #include "mhw_vdbox_vdenc_g12_X.h"
38 #include "mhw_vdbox_hcp_g12_X.h"
39
40 #if defined(ENABLE_KERNELS) && !defined(_FULL_OPEN_SOURCE)
41 #include "Xe_XPM_plus_Film_Grain.h"
42 #endif
43
PrepareCmdSize(CODECHAL_FUNCTION codecFunction)44 void CodechalHwInterfaceXe_Xpm_Plus::PrepareCmdSize(CODECHAL_FUNCTION codecFunction)
45 {
46 m_bltState = MOS_New(BltStateXe_Xpm, m_osInterface);
47 if(m_bltState != nullptr)
48 {
49 m_bltState->Initialize();
50 }
51 else
52 {
53 MHW_ASSERTMESSAGE("Invalid(nullptr) BltStateXe_Xpm!");
54 }
55
56 InitCacheabilityControlSettings(codecFunction);
57
58 m_isVdencSuperSliceEnabled = true;
59
60 m_ssEuTable = m_defaultSsEuLutG12;
61
62 // Set platform dependent parameters
63 m_sizeOfCmdBatchBufferEnd = mhw_mi_g12_X::MI_BATCH_BUFFER_END_CMD::byteSize;
64 m_sizeOfCmdMediaReset = mhw_mi_g12_X::MI_LOAD_REGISTER_IMM_CMD::byteSize * 8;
65 m_vdencBrcImgStateBufferSize = 80
66 + mhw_vdbox_mfx_g12_X::MFX_AVC_IMG_STATE_CMD::byteSize
67 + 92
68 + mhw_mi_g12_X::MI_BATCH_BUFFER_END_CMD::byteSize;
69
70 m_vdencBatchBuffer1stGroupSize = mhw_vdbox_hcp_g12_X::HCP_PIPE_MODE_SELECT_CMD::byteSize
71 + mhw_mi_g12_X::MFX_WAIT_CMD::byteSize * 2
72 + mhw_mi_g12_X::MI_BATCH_BUFFER_END_CMD::byteSize;
73
74 m_vdencBatchBuffer2ndGroupSize = 132
75 + mhw_vdbox_hcp_g12_X::HCP_PIC_STATE_CMD::byteSize
76 + 248
77 + mhw_mi_g12_X::MI_BATCH_BUFFER_END_CMD::byteSize;
78
79 m_vdencReadBatchBufferSize =
80 m_vdenc2ndLevelBatchBufferSize = m_vdencBatchBuffer1stGroupSize
81 + m_vdencBatchBuffer2ndGroupSize
82 + ENCODE_HEVC_VDENC_NUM_MAX_SLICES
83 * (2 * mhw_vdbox_hcp_g12_X::HCP_WEIGHTOFFSET_STATE_CMD::byteSize
84 + mhw_vdbox_hcp_g12_X::HCP_SLICE_STATE_CMD::byteSize
85 + 3 * mhw_vdbox_hcp_g12_X::HCP_PAK_INSERT_OBJECT_CMD::byteSize
86 + 28
87 + mhw_mi_g12_X::MI_BATCH_BUFFER_END_CMD::byteSize
88 + 4 * ENCODE_VDENC_HEVC_PADDING_DW_SIZE);
89
90 m_HucStitchCmdBatchBufferSize = 7 * 4
91 + 14 * 4
92 + mhw_mi_g12_X::MI_BATCH_BUFFER_END_CMD::byteSize;
93
94 // HCP_WEIGHTOFFSET_STATE_CMD cmds is planned to be added in near future
95 m_vdencBatchBufferPerSliceConstSize = mhw_vdbox_hcp_g12_X::HCP_SLICE_STATE_CMD::byteSize
96 + mhw_vdbox_hcp_g12_X::HCP_PAK_INSERT_OBJECT_CMD::byteSize // 1st PakInsertObject cmd is not always inserted for each slice, 2nd PakInsertObject cmd is always inserted for each slice
97 + 28
98 + mhw_mi_g12_X::MI_BATCH_BUFFER_END_CMD::byteSize;
99
100 // Set to size of the BRC update command buffer, since it is larger than BRC Init/ PAK integration commands
101 m_hucCommandBufferSize = mhw_vdbox_huc_g12_X::HUC_IMEM_STATE_CMD::byteSize
102 + mhw_vdbox_huc_g12_X::HUC_PIPE_MODE_SELECT_CMD::byteSize
103 + mhw_mi_g12_X::MFX_WAIT_CMD::byteSize * 3
104 + mhw_vdbox_huc_g12_X::HUC_DMEM_STATE_CMD::byteSize
105 + mhw_vdbox_huc_g12_X::HUC_VIRTUAL_ADDR_STATE_CMD::byteSize
106 + mhw_vdbox_huc_g12_X::HUC_STREAM_OBJECT_CMD::byteSize
107 + mhw_mi_g12_X::MI_STORE_DATA_IMM_CMD::byteSize
108 + mhw_mi_g12_X::MI_STORE_REGISTER_MEM_CMD::byteSize
109 + mhw_vdbox_huc_g12_X::HUC_START_CMD::byteSize
110 + mhw_vdbox_vdenc_g12_X::VD_PIPELINE_FLUSH_CMD::byteSize
111 + mhw_mi_g12_X::MI_FLUSH_DW_CMD::byteSize
112 + mhw_mi_g12_X::MI_STORE_DATA_IMM_CMD::byteSize * 2
113 + mhw_mi_g12_X::MI_STORE_REGISTER_MEM_CMD::byteSize * 2
114 + mhw_mi_g12_X::MI_BATCH_BUFFER_END_CMD::byteSize;
115
116 m_maxKernelLoadCmdSize =
117 mhw_mi_g12_X::PIPE_CONTROL_CMD::byteSize +
118 mhw_render_g12_X::PIPELINE_SELECT_CMD::byteSize +
119 mhw_render_g12_X::MEDIA_OBJECT_CMD::byteSize +
120 mhw_render_g12_X::STATE_BASE_ADDRESS_CMD::byteSize +
121 mhw_render_g12_X::MEDIA_VFE_STATE_CMD::byteSize +
122 mhw_render_g12_X::MEDIA_CURBE_LOAD_CMD::byteSize +
123 mhw_render_g12_X::MEDIA_INTERFACE_DESCRIPTOR_LOAD_CMD::byteSize +
124 mhw_mi_g12_X::MI_BATCH_BUFFER_START_CMD::byteSize +
125 mhw_render_g12_X::MEDIA_OBJECT_WALKER_CMD::byteSize +
126 mhw_mi_g12_X::MI_STORE_DATA_IMM_CMD::byteSize;
127
128 m_sizeOfCmdMediaObject = mhw_render_g12_X::MEDIA_OBJECT_CMD::byteSize;
129 m_sizeOfCmdMediaStateFlush = mhw_mi_g12_X::MEDIA_STATE_FLUSH_CMD::byteSize;
130 }
131
CodechalHwInterfaceXe_Xpm_Plus(PMOS_INTERFACE osInterface,CODECHAL_FUNCTION codecFunction,MhwInterfaces * mhwInterfaces,bool disableScalability)132 CodechalHwInterfaceXe_Xpm_Plus::CodechalHwInterfaceXe_Xpm_Plus(
133 PMOS_INTERFACE osInterface,
134 CODECHAL_FUNCTION codecFunction,
135 MhwInterfaces *mhwInterfaces,
136 bool disableScalability)
137 : CodechalHwInterfaceG12(osInterface, codecFunction, mhwInterfaces, disableScalability)
138 {
139 CODECHAL_HW_FUNCTION_ENTER;
140 PrepareCmdSize(codecFunction);
141 }
142
CodechalHwInterfaceXe_Xpm_Plus(PMOS_INTERFACE osInterface,CODECHAL_FUNCTION codecFunction,MhwInterfacesNext * mhwInterfacesNext,bool disableScalability)143 CodechalHwInterfaceXe_Xpm_Plus::CodechalHwInterfaceXe_Xpm_Plus(
144 PMOS_INTERFACE osInterface,
145 CODECHAL_FUNCTION codecFunction,
146 MhwInterfacesNext *mhwInterfacesNext,
147 bool disableScalability)
148 : CodechalHwInterfaceG12(osInterface, codecFunction, mhwInterfacesNext, disableScalability)
149 {
150 CODECHAL_HW_FUNCTION_ENTER;
151 m_hwInterfaceNext = MOS_New(CodechalHwInterfaceNext, osInterface, codecFunction, mhwInterfacesNext);
152 PrepareCmdSize(codecFunction);
153 }
154
GetVdencPictureSecondLevelCommandsSize(uint32_t mode,uint32_t * commandsSize)155 MOS_STATUS CodechalHwInterfaceXe_Xpm_Plus::GetVdencPictureSecondLevelCommandsSize(
156 uint32_t mode,
157 uint32_t *commandsSize)
158 {
159 CODECHAL_HW_FUNCTION_ENTER;
160
161 uint32_t commands = 0;
162
163 MHW_MI_CHK_NULL(m_hcpInterface);
164 MHW_MI_CHK_NULL(m_vdencInterface);
165
166 uint32_t standard = CodecHal_GetStandardFromMode(mode);
167
168 if (standard == CODECHAL_VP9)
169 {
170 commands += m_hcpInterface->GetHcpVp9PicStateCommandSize();
171 commands += m_hcpInterface->GetHcpVp9SegmentStateCommandSize() * 8;
172 commands += 132;
173 commands += 248;
174 commands += m_sizeOfCmdBatchBufferEnd;
175 }
176 else
177 {
178 MHW_ASSERTMESSAGE("Unsupported encode mode.");
179 return MOS_STATUS_UNKNOWN;
180 }
181
182 *commandsSize = commands;
183
184 return MOS_STATUS_SUCCESS;
185 }
186
GetFilmGrainKernelInfo(uint8_t * & kernelBase,uint32_t & kernelSize)187 MOS_STATUS CodechalHwInterfaceXe_Xpm_Plus::GetFilmGrainKernelInfo(
188 uint8_t*& kernelBase,
189 uint32_t& kernelSize)
190 {
191 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
192
193 #if defined(ENABLE_KERNELS) && !defined(_FULL_OPEN_SOURCE)
194 kernelBase = (uint8_t*)XE_XPM_PLUS_FILM_GRAIN;
195 kernelSize = XE_XPM_PLUS_FILM_GRAIN_SIZE;
196 #else
197 kernelBase = nullptr;
198 kernelSize = 0;
199 #endif
200
201 return eStatus;
202 }
203
SetCacheabilitySettings(MHW_MEMORY_OBJECT_CONTROL_PARAMS cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_END_CODEC])204 MOS_STATUS CodechalHwInterfaceXe_Xpm_Plus::SetCacheabilitySettings(
205 MHW_MEMORY_OBJECT_CONTROL_PARAMS cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_END_CODEC])
206 {
207 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
208
209 CODECHAL_HW_FUNCTION_ENTER;
210
211 if (m_mfxInterface)
212 {
213 CODECHAL_HW_CHK_STATUS_RETURN(m_mfxInterface->SetCacheabilitySettings(cacheabilitySettings));
214 }
215 if (GetHcpInterfaceNext())
216 {
217 CODECHAL_HW_CHK_STATUS_RETURN(GetHcpInterfaceNext()->SetCacheabilitySettings(cacheabilitySettings));
218 }
219 if (m_hcpInterface)
220 {
221 CODECHAL_HW_CHK_STATUS_RETURN(m_hcpInterface->SetCacheabilitySettings(cacheabilitySettings));
222 }
223 if (m_vdencInterface)
224 {
225 CODECHAL_HW_CHK_STATUS_RETURN(m_vdencInterface->SetCacheabilitySettings(cacheabilitySettings));
226 }
227 else if (m_avpInterface)
228 {
229 CODECHAL_HW_CHK_STATUS_RETURN(m_avpInterface->SetCacheabilitySettings(cacheabilitySettings));
230 }
231 if (m_hucInterface)
232 {
233 CODECHAL_HW_CHK_STATUS_RETURN(m_hucInterface->SetCacheabilitySettings(cacheabilitySettings));
234 }
235
236 return eStatus;
237 }
238