1 /* 2 * Copyright (c) 2015-2020, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_render_g12_X.h 24 //! \brief Defines functions for constructing render engine commands on Gen12-based platforms 25 //! 26 27 #ifndef __MHW_RENDER_G12_X_H__ 28 #define __MHW_RENDER_G12_X_H__ 29 30 #include "mhw_render_generic.h" 31 #include "mhw_render_hwcmd_g12_X.h" 32 #include "mhw_mmio_g12.h" 33 #include "mhw_state_heap_g12.h" 34 35 typedef struct MHW_RENDER_ENGINE_L3_CACHE_SETTINGS_G12 : MHW_RENDER_ENGINE_L3_CACHE_SETTINGS 36 { 37 uint32_t dwTcCntlReg = 0; 38 uint32_t dwAllocReg = 0; 39 bool bUpdateDefault = 0; 40 } *PMHW_RENDER_ENGINE_L3_CACHE_SETTINGS_G12; 41 42 typedef struct MHW_RENDER_ENGINE_L3_CACHE_CONFIG_G12 : MHW_RENDER_ENGINE_L3_CACHE_CONFIG 43 { 44 uint32_t dwRcsL3CacheTcCntlReg_Register = 0; 45 uint32_t dwL3CacheTcCntlReg_Setting = 0; 46 uint32_t dwRcsL3CacheAllocReg_Register = 0; 47 uint32_t dwL3CacheAllocReg_Setting = 0; 48 uint32_t dwCcs0L3CacheTcCntlReg_Register = 0; 49 uint32_t dwCcs0L3CacheAllocReg_Register = 0; 50 } *PMHW_RENDER_ENGINE_L3_CACHE_CONFIG_G12; 51 52 struct MHW_VFE_PARAMS_G12 : MHW_VFE_PARAMS 53 { 54 bool bFusedEuDispatch = 0; 55 uint32_t numOfWalkers = 0; 56 bool enableSingleSliceDispatchCcsMode = 0; 57 58 // Surface state offset of scratch space buffer. 59 uint32_t scratchStateOffset = 0; 60 }; 61 62 class MhwRenderInterfaceG12 : public MhwRenderInterfaceGeneric<mhw_render_g12_X> 63 { 64 public: MhwRenderInterfaceG12(MhwMiInterface * miInterface,PMOS_INTERFACE osInterface,MEDIA_SYSTEM_INFO * gtSystemInfo,uint8_t newStateHeapManagerRequested)65 MhwRenderInterfaceG12( 66 MhwMiInterface *miInterface, 67 PMOS_INTERFACE osInterface, 68 MEDIA_SYSTEM_INFO *gtSystemInfo, 69 uint8_t newStateHeapManagerRequested) : 70 MhwRenderInterfaceGeneric(miInterface, osInterface, gtSystemInfo, newStateHeapManagerRequested) 71 { 72 MHW_FUNCTION_ENTER; 73 74 m_l3CacheCntlRegisterValueDefault = 0x80000080; 75 76 InitMmioRegisters(); 77 } 78 ~MhwRenderInterfaceG12()79 virtual ~MhwRenderInterfaceG12() { MHW_FUNCTION_ENTER; } 80 81 MOS_STATUS AddMediaVfeCmd( 82 PMOS_COMMAND_BUFFER cmdBuffer, 83 PMHW_VFE_PARAMS params); 84 85 MOS_STATUS AddPipelineSelectCmd( 86 PMOS_COMMAND_BUFFER cmdBuffer, 87 bool gpGpuPipe); 88 89 MOS_STATUS AddMediaObject( 90 PMOS_COMMAND_BUFFER cmdBuffer, 91 PMHW_BATCH_BUFFER batchBuffer, 92 PMHW_MEDIA_OBJECT_PARAMS params); 93 AddPaletteLoadCmd(PMOS_COMMAND_BUFFER cmdBuffer,PMHW_PALETTE_PARAMS params)94 MOS_STATUS AddPaletteLoadCmd( 95 PMOS_COMMAND_BUFFER cmdBuffer, 96 PMHW_PALETTE_PARAMS params) 97 { 98 MHW_ASSERTMESSAGE("PALETTE_ENTRY is not supported!"); 99 return MOS_STATUS_PLATFORM_NOT_SUPPORTED; 100 } 101 102 MOS_STATUS AddGpgpuCsrBaseAddrCmd( 103 PMOS_COMMAND_BUFFER cmdBuffer, 104 PMOS_RESOURCE csrResource); 105 106 MOS_STATUS EnableL3Caching( 107 PMHW_RENDER_ENGINE_L3_CACHE_SETTINGS cacheSettings); 108 109 MOS_STATUS SetL3Cache( 110 PMOS_COMMAND_BUFFER cmdBuffer ); 111 GetL3CacheConfig()112 MHW_RENDER_ENGINE_L3_CACHE_CONFIG* GetL3CacheConfig() { return &m_l3CacheConfig; } 113 GetMmioRegisters()114 virtual PMHW_MI_MMIOREGISTERS GetMmioRegisters() 115 { 116 return &m_mmioRegisters; 117 } 118 119 //! 120 //! \brief Get AVS sampler state Inc unit 121 //! \details Get AVS sampler state Inc unit 122 //! \return [out] uint32_t 123 //! AVS sampler unit. GetSamplerStateAVSIncUnit()124 virtual uint32_t GetSamplerStateAVSIncUnit() { return MHW_SAMPLER_STATE_AVS_INC_G12; } 125 126 //! 127 //! \brief Get Conv sampler state Inc unit 128 //! \details Get Conv sampler state Inc unit 129 //! \return [out] uint32_t 130 //! Conv sampler unit. GetSamplerStateConvIncUnit()131 virtual uint32_t GetSamplerStateConvIncUnit() { return MHW_SAMPLER_STATE_CONV_INC_G12; } 132 133 //! 134 //! \brief Get the sampler height and width align unit 135 //! \details NV12 format needs the width and height to be a multiple of some unit 136 //! \param [in] bool 137 //! true if AVS sampler, false otherwise 138 //! \param [in, out] uint32_t 139 //! weight align unit 140 //! \param [in, out] uint32_t 141 //! height align unit GetSamplerResolutionAlignUnit(bool isAVSSampler,uint32_t & widthAlignUnit,uint32_t & heightAlignUnit)142 virtual void GetSamplerResolutionAlignUnit(bool isAVSSampler, uint32_t &widthAlignUnit, uint32_t &heightAlignUnit) 143 { 144 // enable 2 plane NV12 when width is not multiple of 2 or height is 145 // not multiple of 4. For AVS sampler, no limitation for 4 alignment. 146 widthAlignUnit = isAVSSampler ? MHW_AVS_SAMPLER_WIDTH_ALIGN_UNIT : MHW_SAMPLER_WIDTH_ALIGN_UNIT_G12; 147 heightAlignUnit = isAVSSampler ? MHW_AVS_SAMPLER_HEIGHT_ALIGN_UNIT : MHW_SAMPLER_HEIGHT_ALIGN_UNIT_G12; 148 } 149 150 protected: 151 MHW_RENDER_ENGINE_L3_CACHE_CONFIG_G12 m_l3CacheConfig; 152 153 uint32_t m_l3CacheTcCntlRegisterValueDefault = 0; 154 uint32_t m_l3CacheAllocRegisterValueDefault = 0xD0000020; 155 156 private: 157 //! \brief Mmio registers address 158 MHW_MI_MMIOREGISTERS m_mmioRegisters = {}; 159 void InitMmioRegisters(); 160 }; 161 #endif 162