1 /* 2 * Copyright (c) 2010-2019, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file vphal_render_hdr_g9_base.h 24 //! \brief Rendering definitions for Unified VP HAL HDR processing 25 //! 26 //! 27 //! \file vphal_render_hdr_g9_base.h 28 //! \brief Common interface and structure used in HDR for GEN9 29 //! \details Common interface and structure used in HDR which are for for GEN9 platform 30 //! 31 32 #ifndef __VPHAL_RENDER_HDR_G9_BASE_H__ 33 #define __VPHAL_RENDER_HDR_G9_BASE_H__ 34 35 #define KERNEL_HDR_MANDATORY_G9 0 36 #define KERNEL_HDR_PREPROCESS_G9 4 37 38 #define VPHAL_HDR_BTINDEX_EOTF1DLUT_OFFSET_G9 3 39 #define VPHAL_HDR_BTINDEX_OETF1DLUT_OFFSET_G9 4 40 #define VPHAL_HDR_BTINDEX_CRI3DLUT_OFFSET_G9 3 41 42 #define VPHAL_HDR_BTINDEX_LAYER0_G9 16 43 #define VPHAL_HDR_BTINDEX_PER_LAYER0_G9 5 44 #define VPHAL_HDR_BTINDEX_RENDERTARGET_G9 56 45 #define VPHAL_HDR_BTINDEX_PER_TARGET_G9 3 46 #define VPHAL_HDR_BTINDEX_COEFF_G9 59 47 48 #define VPHAL_HDR_AVS_SAMPLER_STATE_NEAREST 1 49 #define VPHAL_HDR_AVS_SAMPLER_STATE_ADAPTIVE 3 50 #define VPHAL_HDR_3D_SAMPLER_STATE_NEAREST 13 51 #define VPHAL_HDR_3D_SAMPLER_STATE_BILINEAR 14 52 53 #define VPHAL_HDR_COEF_SURFACE_WIDTH_G9 8 54 #define VPHAL_HDR_COEF_SURFACE_HEIGHT_BASIC_G9 66 55 #define VPHAL_HDR_COEF_SURFACE_HEIGHT_EXT_G9 32 56 #define VPHAL_HDR_COEF_SURFACE_HEIGHT_G9 (VPHAL_HDR_COEF_SURFACE_HEIGHT_BASIC_G9 + VPHAL_HDR_COEF_SURFACE_HEIGHT_EXT_G9) 57 #define VPHAL_HDR_COEF_SURFACE_PITCH_G9 64 58 #define VPHAL_HDR_COEF_LINES_PER_LAYER_BASIC_G9 8 59 #define VPHAL_HDR_COEF_LINES_PER_LAYER_EXT_G9 4 60 #define VPHAL_HDR_COEF_EOTF_OFFSET 6 61 #define VPHAL_HDR_COEF_PIVOT_POINT_LINE_OFFSET 6 62 #define VPHAL_HDR_COEF_SLOPE_INTERCEPT_LINE_OFFSET 7 63 #define VPHAL_HDR_COEF_CCMEXT_OFFSET 6 64 #define VPHAL_HDR_COEF_CLAMP_OFFSET 7 65 66 #define VPHAL_HDR_EOTF_COEFF1_TRADITIONNAL_GAMMA_G9 0.081f 67 #define VPHAL_HDR_EOTF_COEFF2_TRADITIONNAL_GAMMA_G9 (1.0f / 4.5f) 68 #define VPHAL_HDR_EOTF_COEFF3_TRADITIONNAL_GAMMA_G9 (1.0f / 1.099f) 69 #define VPHAL_HDR_EOTF_COEFF4_TRADITIONNAL_GAMMA_G9 (0.099f / 1.099f) 70 #define VPHAL_HDR_EOTF_COEFF5_TRADITIONNAL_GAMMA_G9 (1.0f / 0.45f) 71 72 #define VPHAL_HDR_OETF_COEFF1_TRADITIONNAL_GAMMA_G9 0.018f 73 #define VPHAL_HDR_OETF_COEFF2_TRADITIONNAL_GAMMA_G9 4.5f 74 #define VPHAL_HDR_OETF_COEFF3_TRADITIONNAL_GAMMA_G9 1.099f 75 #define VPHAL_HDR_OETF_COEFF4_TRADITIONNAL_GAMMA_G9 (-0.099f) 76 #define VPHAL_HDR_OETF_COEFF5_TRADITIONNAL_GAMMA_G9 0.45f 77 78 #define VPHAL_HDR_EOTF_COEFF1_TRADITIONNAL_GAMMA_BT1886_G9 (-0.0f) 79 #define VPHAL_HDR_EOTF_COEFF2_TRADITIONNAL_GAMMA_BT1886_G9 0.0f 80 #define VPHAL_HDR_EOTF_COEFF3_TRADITIONNAL_GAMMA_BT1886_G9 1.0f 81 #define VPHAL_HDR_EOTF_COEFF4_TRADITIONNAL_GAMMA_BT1886_G9 0.0f 82 #define VPHAL_HDR_EOTF_COEFF5_TRADITIONNAL_GAMMA_BT1886_G9 2.4f 83 84 #define VPHAL_HDR_EOTF_COEFF1_TRADITIONNAL_GAMMA_SRGB_G9 0.04045f 85 #define VPHAL_HDR_EOTF_COEFF2_TRADITIONNAL_GAMMA_SRGB_G9 (1.0f / 12.92f) 86 #define VPHAL_HDR_EOTF_COEFF3_TRADITIONNAL_GAMMA_SRGB_G9 (1.0f / 1.055f) 87 #define VPHAL_HDR_EOTF_COEFF4_TRADITIONNAL_GAMMA_SRGB_G9 (0.055f / 1.055f) 88 #define VPHAL_HDR_EOTF_COEFF5_TRADITIONNAL_GAMMA_SRGB_G9 2.4f 89 90 #define VPHAL_HDR_OETF_COEFF1_TRADITIONNAL_GAMMA_SRGB_G9 0.0031308f 91 #define VPHAL_HDR_OETF_COEFF2_TRADITIONNAL_GAMMA_SRGB_G9 12.92f 92 #define VPHAL_HDR_OETF_COEFF3_TRADITIONNAL_GAMMA_SRGB_G9 1.055f 93 #define VPHAL_HDR_OETF_COEFF4_TRADITIONNAL_GAMMA_SRGB_G9 (-0.055f) 94 #define VPHAL_HDR_OETF_COEFF5_TRADITIONNAL_GAMMA_SRGB_G9 (1.0f / 2.4f) 95 96 #define VPHAL_HDR_EOTF_COEFF1_SMPTE_ST2084_G9 -0.8359375f 97 #define VPHAL_HDR_EOTF_COEFF2_SMPTE_ST2084_G9 18.8515625f 98 #define VPHAL_HDR_EOTF_COEFF3_SMPTE_ST2084_G9 -18.6875f 99 #define VPHAL_HDR_EOTF_COEFF4_SMPTE_ST2084_G9 6.277394636015326f 100 #define VPHAL_HDR_EOTF_COEFF5_SMPTE_ST2084_G9 0.012683313515656f 101 102 #define VPHAL_HDR_OETF_COEFF1_SMPTE_ST2084_G9 0.8359375f 103 #define VPHAL_HDR_OETF_COEFF2_SMPTE_ST2084_G9 18.8515625f 104 #define VPHAL_HDR_OETF_COEFF3_SMPTE_ST2084_G9 18.6875f 105 #define VPHAL_HDR_OETF_COEFF4_SMPTE_ST2084_G9 0.1593017578125f 106 #define VPHAL_HDR_OETF_COEFF5_SMPTE_ST2084_G9 78.84375f 107 108 #define HDR_MANDATORY_KERNEL_BLOCK_WIDTH 16 109 #define HDR_MANDATORY_KERNEL_BLOCK_HEIGHT 8 110 111 #define MAX_CSC_COEFF_VAL_ICL 3.9921875 // (4.0 * 511.0 / 512.0) 112 #define ARRAY_SIZE(a) (sizeof(a) / sizeof(a[0])) 113 114 typedef struct 115 { 116 uint32_t reserved : 2; 117 uint32_t mantissa : 9; 118 uint32_t exponent : 3; 119 uint32_t sign : 1; 120 } CSC_COEFF_FORMAT; 121 122 extern CSC_COEFF_FORMAT Convert_CSC_Coeff_To_Register_Format(double coeff); 123 extern double Convert_CSC_Coeff_Register_Format_To_Double(CSC_COEFF_FORMAT regVal); 124 extern float LimitFP32PrecisionToF3_9(float fp); 125 extern void LimitFP32ArrayPrecisionToF3_9(float fps[], size_t size); 126 127 #if __cplusplus 128 extern "C" 129 { 130 #endif // __cplusplus 131 132 //! 133 //! \brief Gen9 Hdr kernel params 134 //! 135 const RENDERHAL_KERNEL_PARAM g_Hdr_KernelParam_g9[KERNEL_HDR_MAX] = 136 { 137 /* GRF_Count 138 | BT_Count 139 | | Sampler_Count 140 | | | Thread_Count 141 | | | | GRF_Start_Register 142 | | | | | CURBE_Length (in 256-bit blocks) 143 | | | | | | block_width 144 | | | | | | | block_height 145 | | | | | | | | blocks_x 146 | | | | | | | | | blocks_y 147 | | | | | | | | | |*/ 148 {8, 40, 4, VPHAL_USE_MEDIA_THREADS_MAX, 0, 8, 16, 8, 1, 1}, 149 {8, 40, 4, VPHAL_USE_MEDIA_THREADS_MAX, 0, 8, 16, 8, 1, 1}, 150 {8, 40, 4, VPHAL_USE_MEDIA_THREADS_MAX, 0, 4, 16, 8, 1, 1}, 151 {8, 40, 4, VPHAL_USE_MEDIA_THREADS_MAX, 0, 4, 16, 8, 1, 1}, 152 {8, 40, 0, VPHAL_USE_MEDIA_THREADS_MAX, 0, 4, 1, 1, 1, 1}, 153 }; 154 155 #define CONFIG_ENTRY_INITIALIZER(CCM, PWLF, CCMExt1, GamutClamp1, CCMExt2, GamutClamp2, Invalid) \ 156 ((CCM) | (PWLF) << 3 | (CCMExt1) << 6 | (GamutClamp1) << 9 | (CCMExt2) << 10 | (GamutClamp2) << 13 | (Invalid) << 15) 157 158 const uint16_t HDRStageConfigTable_g9[HDR_STAGES_CONFIG_TABLE_SIZE] = 159 { 160 // CCM & CCMExt1 & CCMExt2 mode(should keep consistent with enum definition VPHAL_HDR_CCM_TYPE): 161 // 0 - VPHAL_HDR_CCM_NONE 162 // 1 - VPHAL_HDR_CCM_BT2020_TO_BT601_BT709_MATRIX 163 // 2 - VPHAL_HDR_CCM_BT601_BT709_TO_BT2020_MATRIX 164 // 3 - VPHAL_HDR_CCM_BT2020_TO_MONITOR_MATRIX 165 // 4 - VPHAL_HDR_CCM_MONITOR_TO_BT2020_MATRIX 166 // 5 - VPHAL_HDR_CCM_MONITOR_TO_BT709_MATRIX 167 // 168 // PWLF mode(should keep consistent with enum definition VPHAL_HDR_MODE): 169 // 0 - VPHAL_HDR_MODE_NONE 170 // 1 - VPHAL_HDR_MODE_TONE_MAPPING 171 // 2 - VPHAL_HDR_MODE_INVERSE_TONE_MAPPING 172 // 3 - VPHAL_HDR_MODE_H2H 173 // 4 - VPHAL_HDR_MODE_S2S 174 // 175 // Result: CCM PWLF CCMExt1 GamutClamp1 CCMExt2 GamutClamp2 Invalid Case id: OutputLinear OutputGamut OutputXDR InputGamut InputXDR 176 CONFIG_ENTRY_INITIALIZER(0, 0, 0, 0, 0, 0, 0), // 0 0 0 0 0 177 CONFIG_ENTRY_INITIALIZER(2, 1, 1, 0, 0, 0, 0), // 0 0 0 0 1 178 CONFIG_ENTRY_INITIALIZER(1, 0, 0, 0, 0, 0, 0), // 0 0 0 1 0 179 CONFIG_ENTRY_INITIALIZER(0, 1, 1, 0, 0, 0, 0), // 0 0 0 1 1 180 CONFIG_ENTRY_INITIALIZER(0, 0, 0, 0, 0, 0, 1), // 0 0 1 0 0 181 CONFIG_ENTRY_INITIALIZER(0, 0, 0, 0, 0, 0, 1), // 0 0 1 0 1 182 CONFIG_ENTRY_INITIALIZER(0, 0, 0, 0, 0, 0, 1), // 0 0 1 1 0 183 CONFIG_ENTRY_INITIALIZER(0, 0, 0, 0, 0, 0, 1), // 0 0 1 1 1 184 CONFIG_ENTRY_INITIALIZER(2, 0, 0, 0, 0, 0, 0), // 0 1 0 0 0 185 CONFIG_ENTRY_INITIALIZER(2, 1, 0, 0, 0, 0, 0), // 0 1 0 0 1 186 CONFIG_ENTRY_INITIALIZER(0, 0, 0, 0, 0, 0, 0), // 0 1 0 1 0 187 CONFIG_ENTRY_INITIALIZER(0, 1, 0, 0, 0, 0, 0), // 0 1 0 1 1 188 CONFIG_ENTRY_INITIALIZER(0, 2, 2, 0, 0, 0, 0), // 0 1 1 0 0 189 CONFIG_ENTRY_INITIALIZER(2, 3, 3, 1, 4, 0, 0), // 0 1 1 0 1 190 CONFIG_ENTRY_INITIALIZER(0, 2, 3, 1, 4, 0, 0), // 0 1 1 1 0 191 CONFIG_ENTRY_INITIALIZER(0, 3, 0, 0, 0, 0, 0), // 0 1 1 1 1 192 CONFIG_ENTRY_INITIALIZER(0, 0, 0, 0, 0, 0, 0), // 1 0 0 0 0 193 CONFIG_ENTRY_INITIALIZER(2, 1, 1, 1, 0, 0, 0), // 1 0 0 0 1 194 CONFIG_ENTRY_INITIALIZER(1, 0, 0, 0, 0, 0, 0), // 1 0 0 1 0 195 CONFIG_ENTRY_INITIALIZER(0, 1, 1, 1, 0, 0, 0), // 1 0 0 1 1 196 CONFIG_ENTRY_INITIALIZER(0, 2, 0, 0, 0, 0, 0), // 1 0 1 0 0 197 CONFIG_ENTRY_INITIALIZER(2, 3, 3, 1, 5, 0, 0), // 1 0 1 0 1 198 CONFIG_ENTRY_INITIALIZER(0, 2, 3, 1, 5, 0, 0), // 1 0 1 1 0 199 CONFIG_ENTRY_INITIALIZER(0, 3, 5, 0, 0, 0, 0), // 1 0 1 1 1 200 CONFIG_ENTRY_INITIALIZER(0, 0, 0, 0, 0, 0, 1), // 1 1 0 0 0 201 CONFIG_ENTRY_INITIALIZER(0, 0, 0, 0, 0, 0, 1), // 1 1 0 0 1 202 CONFIG_ENTRY_INITIALIZER(0, 0, 0, 0, 0, 0, 1), // 1 1 0 1 0 203 CONFIG_ENTRY_INITIALIZER(0, 0, 0, 0, 0, 0, 1), // 1 1 0 1 1 204 CONFIG_ENTRY_INITIALIZER(0, 0, 0, 0, 0, 0, 1), // 1 1 1 0 0 205 CONFIG_ENTRY_INITIALIZER(0, 0, 0, 0, 0, 0, 1), // 1 1 1 0 1 206 CONFIG_ENTRY_INITIALIZER(0, 0, 0, 0, 0, 0, 1), // 1 1 1 1 0 207 CONFIG_ENTRY_INITIALIZER(0, 0, 0, 0, 0, 0, 1) // 1 1 1 1 1 208 }; 209 210 // Static Data for Gen9 HDR PreProcess kernel 211 typedef struct _MEDIA_WALKER_HDR_PREPROCESS_STATIC_DATA_G9 212 { 213 // uint32_t 0-7 - GRF R1.0-R1.7 214 uint32_t uiTMMode[VPHAL_MAX_HDR_INPUT_LAYER] = { 0 }; 215 // uint32_t 8-15 - GRF R2.0-R2.7 216 uint32_t uiMaxCLL[VPHAL_MAX_HDR_INPUT_LAYER] = { 0 }; 217 // uint32_t 16-23 - GRF R3.0-R3.7 218 uint32_t uiMaxDLL[VPHAL_MAX_HDR_INPUT_LAYER] = { 0 }; 219 // uint32_t 16 220 uint32_t OutputCoeffIndex = 0; 221 }MEDIA_WALKER_HDR_PREPROCESS_STATIC_DATA_G9, *PMEDIA_WALKER_HDR_PREPROCESS_STATIC_DATA_G9; 222 C_ASSERT(SIZE32(MEDIA_WALKER_HDR_PREPROCESS_STATIC_DATA_G9) == 25); 223 224 // Static Data for Gen9 HDR kernel 225 typedef struct _MEDIA_WALKER_HDR_STATIC_DATA_G9 226 { 227 // uint32_t 0 - GRF R1.0 228 union 229 { 230 struct { 231 float HorizontalFrameOriginLayer0; 232 }; 233 float Value; 234 } DW0; 235 236 // uint32_t 1 - GRF R1.1 237 union 238 { 239 struct { 240 float HorizontalFrameOriginLayer1; 241 }; 242 float Value; 243 } DW1; 244 245 // uint32_t 2 - GRF R1.2 246 union 247 { 248 struct { 249 float HorizontalFrameOriginLayer2; 250 }; 251 float Value; 252 } DW2; 253 254 // uint32_t 3 - GRF R1.3 255 union 256 { 257 struct { 258 float HorizontalFrameOriginLayer3; 259 }; 260 float Value; 261 } DW3; 262 263 // uint32_t 4 - GRF R1.4 264 union 265 { 266 struct { 267 float HorizontalFrameOriginLayer4; 268 }; 269 float Value; 270 } DW4; 271 272 // uint32_t 5 - GRF R1.5 273 union 274 { 275 struct { 276 float HorizontalFrameOriginLayer5; 277 }; 278 float Value; 279 } DW5; 280 281 // uint32_t 6 - GRF R1.6 282 union 283 { 284 struct { 285 float HorizontalFrameOriginLayer6; 286 }; 287 float Value; 288 } DW6; 289 290 // uint32_t 7 - GRF R1.7 291 union 292 { 293 struct { 294 float HorizontalFrameOriginLayer7; 295 }; 296 float Value; 297 } DW7; 298 299 // uint32_t 8 - GRF R2.0 300 union 301 { 302 struct { 303 float VerticalFrameOriginLayer0; 304 }; 305 float Value; 306 } DW8; 307 308 // uint32_t 9 - GRF R2.1 309 union 310 { 311 struct { 312 float VerticalFrameOriginLayer1; 313 }; 314 float Value; 315 } DW9; 316 317 // uint32_t 10 - GRF R2.2 318 union 319 { 320 struct { 321 float VerticalFrameOriginLayer2; 322 }; 323 float Value; 324 } DW10; 325 326 // uint32_t 11 - GRF R2.3 327 union 328 { 329 struct { 330 float VerticalFrameOriginLayer3; 331 }; 332 float Value; 333 } DW11; 334 335 // uint32_t 12 - GRF R2.4 336 union 337 { 338 struct { 339 float VerticalFrameOriginLayer4; 340 }; 341 float Value; 342 } DW12; 343 344 // uint32_t 13 - GRF R2.5 345 union 346 { 347 struct { 348 float VerticalFrameOriginLayer5; 349 }; 350 float Value; 351 } DW13; 352 353 // uint32_t 14 - GRF R2.6 354 union 355 { 356 struct { 357 float VerticalFrameOriginLayer6; 358 }; 359 float Value; 360 } DW14; 361 362 // uint32_t 15 - GRF R2.7 363 union 364 { 365 struct { 366 float VerticalFrameOriginLayer7; 367 }; 368 float Value; 369 } DW15; 370 371 // uint32_t 16 - GRF R3.0 372 union 373 { 374 struct { 375 float HorizontalScalingStepRatioLayer0; 376 }; 377 float Value; 378 } DW16; 379 380 // uint32_t 17 - GRF R3.1 381 union 382 { 383 struct { 384 float HorizontalScalingStepRatioLayer1; 385 }; 386 float Value; 387 } DW17; 388 389 // uint32_t 18 - GRF R3.2 390 union 391 { 392 struct { 393 float HorizontalScalingStepRatioLayer2; 394 }; 395 float Value; 396 } DW18; 397 398 // uint32_t 19 - GRF R3.3 399 union 400 { 401 struct { 402 float HorizontalScalingStepRatioLayer3; 403 }; 404 float Value; 405 } DW19; 406 407 // uint32_t 20 - GRF R3.4 408 union 409 { 410 struct { 411 float HorizontalScalingStepRatioLayer4; 412 }; 413 float Value; 414 } DW20; 415 416 // uint32_t 21 - GRF R3.5 417 union 418 { 419 struct { 420 float HorizontalScalingStepRatioLayer5; 421 }; 422 float Value; 423 } DW21; 424 425 // uint32_t 22 - GRF R3.6 426 union 427 { 428 struct { 429 float HorizontalScalingStepRatioLayer6; 430 }; 431 float Value; 432 } DW22; 433 434 // uint32_t 23 - GRF R3.7 435 union 436 { 437 struct { 438 float HorizontalScalingStepRatioLayer7; 439 }; 440 float Value; 441 } DW23; 442 443 // uint32_t 24 - GRF R4.0 444 union 445 { 446 struct { 447 float VerticalScalingStepRatioLayer0; 448 }; 449 float Value; 450 } DW24; 451 452 // uint32_t 25 - GRF R4.1 453 union 454 { 455 struct { 456 float VerticalScalingStepRatioLayer1; 457 }; 458 float Value; 459 } DW25; 460 461 // uint32_t 26 - GRF R4.2 462 union 463 { 464 struct { 465 float VerticalScalingStepRatioLayer2; 466 }; 467 float Value; 468 } DW26; 469 470 // uint32_t 27 - GRF R4.3 471 union 472 { 473 struct { 474 float VerticalScalingStepRatioLayer3; 475 }; 476 float Value; 477 } DW27; 478 479 // uint32_t 28 - GRF R4.4 480 union 481 { 482 struct { 483 float VerticalScalingStepRatioLayer4; 484 }; 485 float Value; 486 } DW28; 487 488 // uint32_t 29 - GRF R4.5 489 union 490 { 491 struct { 492 float VerticalScalingStepRatioLayer5; 493 }; 494 float Value; 495 } DW29; 496 497 // uint32_t 30 - GRF R4.6 498 union 499 { 500 struct { 501 float VerticalScalingStepRatioLayer6; 502 }; 503 float Value; 504 } DW30; 505 506 // uint32_t 31 - GRF R4.7 507 union 508 { 509 struct { 510 float VerticalScalingStepRatioLayer7; 511 }; 512 float Value; 513 } DW31; 514 515 // uint32_t 32 - GRF R5.0 516 union 517 { 518 struct { 519 uint32_t LeftCoordinateRectangleLayer0 : BITFIELD_RANGE( 0,15 ); 520 uint32_t TopCoordinateRectangleLayer0 : BITFIELD_RANGE( 16,31 ); 521 }; 522 uint32_t Value; 523 } DW32; 524 525 // uint32_t 33 - GRF R5.1 526 union 527 { 528 struct { 529 uint32_t LeftCoordinateRectangleLayer1 : BITFIELD_RANGE( 0,15 ); 530 uint32_t TopCoordinateRectangleLayer1 : BITFIELD_RANGE( 16,31 ); 531 }; 532 uint32_t Value; 533 } DW33; 534 535 // uint32_t 34 - GRF R5.2 536 union 537 { 538 struct { 539 uint32_t LeftCoordinateRectangleLayer2 : BITFIELD_RANGE( 0,15 ); 540 uint32_t TopCoordinateRectangleLayer2 : BITFIELD_RANGE( 16,31 ); 541 }; 542 uint32_t Value; 543 } DW34; 544 545 // uint32_t 35 - GRF R5.3 546 union 547 { 548 struct { 549 uint32_t LeftCoordinateRectangleLayer3 : BITFIELD_RANGE( 0,15 ); 550 uint32_t TopCoordinateRectangleLayer3 : BITFIELD_RANGE( 16,31 ); 551 }; 552 uint32_t Value; 553 } DW35; 554 555 // uint32_t 36 - GRF R5.4 556 union 557 { 558 struct { 559 uint32_t LeftCoordinateRectangleLayer4 : BITFIELD_RANGE( 0,15 ); 560 uint32_t TopCoordinateRectangleLayer4 : BITFIELD_RANGE( 16,31 ); 561 }; 562 uint32_t Value; 563 } DW36; 564 565 // uint32_t 37 - GRF R5.5 566 union 567 { 568 struct { 569 uint32_t LeftCoordinateRectangleLayer5 : BITFIELD_RANGE( 0,15 ); 570 uint32_t TopCoordinateRectangleLayer5 : BITFIELD_RANGE( 16,31 ); 571 }; 572 uint32_t Value; 573 } DW37; 574 575 // uint32_t 38 - GRF R5.6 576 union 577 { 578 struct { 579 uint32_t LeftCoordinateRectangleLayer6 : BITFIELD_RANGE( 0,15 ); 580 uint32_t TopCoordinateRectangleLayer6 : BITFIELD_RANGE( 16,31 ); 581 }; 582 uint32_t Value; 583 } DW38; 584 585 // uint32_t 39 - GRF R5.7 586 union 587 { 588 struct { 589 uint32_t LeftCoordinateRectangleLayer7 : BITFIELD_RANGE( 0,15 ); 590 uint32_t TopCoordinateRectangleLayer7 : BITFIELD_RANGE( 16,31 ); 591 }; 592 uint32_t Value; 593 } DW39; 594 595 // uint32_t 40 - GRF R6.0 596 union 597 { 598 struct { 599 uint32_t RightCoordinateRectangleLayer0 : BITFIELD_RANGE( 0,15 ); 600 uint32_t BottomCoordinateRectangleLayer0 : BITFIELD_RANGE( 16,31 ); 601 }; 602 uint32_t Value; 603 } DW40; 604 605 // uint32_t 41 - GRF R6.1 606 union 607 { 608 struct { 609 uint32_t RightCoordinateRectangleLayer1 : BITFIELD_RANGE( 0,15 ); 610 uint32_t BottomCoordinateRectangleLayer1 : BITFIELD_RANGE( 16,31 ); 611 }; 612 uint32_t Value; 613 } DW41; 614 615 // uint32_t 42 - GRF R6.2 616 union 617 { 618 struct { 619 uint32_t RightCoordinateRectangleLayer2 : BITFIELD_RANGE( 0,15 ); 620 uint32_t BottomCoordinateRectangleLayer2 : BITFIELD_RANGE( 16,31 ); 621 }; 622 uint32_t Value; 623 } DW42; 624 625 // uint32_t 43 - GRF R6.3 626 union 627 { 628 struct { 629 uint32_t RightCoordinateRectangleLayer3 : BITFIELD_RANGE( 0,15 ); 630 uint32_t BottomCoordinateRectangleLayer3 : BITFIELD_RANGE( 16,31 ); 631 }; 632 uint32_t Value; 633 } DW43; 634 635 // uint32_t 44 - GRF R6.4 636 union 637 { 638 struct { 639 uint32_t RightCoordinateRectangleLayer4 : BITFIELD_RANGE( 0,15 ); 640 uint32_t BottomCoordinateRectangleLayer4 : BITFIELD_RANGE( 16,31 ); 641 }; 642 uint32_t Value; 643 } DW44; 644 645 // uint32_t 45 - GRF R6.5 646 union 647 { 648 struct { 649 uint32_t RightCoordinateRectangleLayer5 : BITFIELD_RANGE( 0,15 ); 650 uint32_t BottomCoordinateRectangleLayer5 : BITFIELD_RANGE( 16,31 ); 651 }; 652 uint32_t Value; 653 } DW45; 654 655 // uint32_t 46 - GRF R6.6 656 union 657 { 658 struct { 659 uint32_t RightCoordinateRectangleLayer6 : BITFIELD_RANGE( 0,15 ); 660 uint32_t BottomCoordinateRectangleLayer6 : BITFIELD_RANGE( 16,31 ); 661 }; 662 uint32_t Value; 663 } DW46; 664 665 // uint32_t 47 - GRF R6.7 666 union 667 { 668 struct { 669 uint32_t RightCoordinateRectangleLayer7 : BITFIELD_RANGE( 0,15 ); 670 uint32_t BottomCoordinateRectangleLayer7 : BITFIELD_RANGE( 16,31 ); 671 }; 672 uint32_t Value; 673 } DW47; 674 675 // uint32_t 48 - GRF R7.0 676 union 677 { 678 struct { 679 uint32_t FormatDescriptorLayer0 : BITFIELD_RANGE( 0,7 ); 680 uint32_t ChromaSittingLocationLayer0 : BITFIELD_RANGE( 8,10 ); 681 uint32_t ChannelSwapEnablingFlagLayer0 : BITFIELD_RANGE( 11,11 ); 682 uint32_t IEFBypassEnablingFlagLayer0 : BITFIELD_RANGE( 12,12 ); 683 uint32_t RotationAngleMirrorDirectionLayer0 : BITFIELD_RANGE( 13,15 ); 684 uint32_t SamplerIndexFirstPlaneLayer0 : BITFIELD_RANGE( 16,19 ); 685 uint32_t SamplerIndexSecondThirdPlaneLayer0 : BITFIELD_RANGE( 20,23 ); 686 uint32_t CCMExtensionEnablingFlagLayer0 : BITFIELD_RANGE( 24,24 ); 687 uint32_t ToneMappingEnablingFlagLayer0 : BITFIELD_RANGE( 25,25 ); 688 uint32_t PriorCSCEnablingFlagLayer0 : BITFIELD_RANGE( 26,26 ); 689 uint32_t EOTF1DLUTEnablingFlagLayer0 : BITFIELD_RANGE( 27,27 ); 690 uint32_t CCMEnablingFlagLayer0 : BITFIELD_RANGE( 28,28 ); 691 uint32_t OETF1DLUTEnablingFlagLayer0 : BITFIELD_RANGE( 29,29 ); 692 uint32_t PostCSCEnablingFlagLayer0 : BITFIELD_RANGE( 30,30 ); 693 uint32_t Enabling3DLUTFlagLayer0 : BITFIELD_RANGE( 31,31 ); 694 }; 695 uint32_t Value; 696 } DW48; 697 698 // uint32_t 49 - GRF R7.1 699 union 700 { 701 struct { 702 uint32_t FormatDescriptorLayer1 : BITFIELD_RANGE( 0,7 ); 703 uint32_t ChromaSittingLocationLayer1 : BITFIELD_RANGE( 8,10 ); 704 uint32_t ChannelSwapEnablingFlagLayer1 : BITFIELD_RANGE( 11,11 ); 705 uint32_t IEFBypassEnablingFlagLayer1 : BITFIELD_RANGE( 12,12 ); 706 uint32_t RotationAngleMirrorDirectionLayer1 : BITFIELD_RANGE( 13,15 ); 707 uint32_t SamplerIndexFirstPlaneLayer1 : BITFIELD_RANGE( 16,19 ); 708 uint32_t SamplerIndexSecondThirdPlaneLayer1 : BITFIELD_RANGE( 20,23 ); 709 uint32_t CCMExtensionEnablingFlagLayer1 : BITFIELD_RANGE( 24,24 ); 710 uint32_t ToneMappingEnablingFlagLayer1 : BITFIELD_RANGE( 25,25 ); 711 uint32_t PriorCSCEnablingFlagLayer1 : BITFIELD_RANGE( 26,26 ); 712 uint32_t EOTF1DLUTEnablingFlagLayer1 : BITFIELD_RANGE( 27,27 ); 713 uint32_t CCMEnablingFlagLayer1 : BITFIELD_RANGE( 28,28 ); 714 uint32_t OETF1DLUTEnablingFlagLayer1 : BITFIELD_RANGE( 29,29 ); 715 uint32_t PostCSCEnablingFlagLayer1 : BITFIELD_RANGE( 30,30 ); 716 uint32_t Enabling3DLUTFlagLayer1 : BITFIELD_RANGE( 31,31 ); 717 }; 718 uint32_t Value; 719 } DW49; 720 721 // uint32_t 50 - GRF R7.2 722 union 723 { 724 struct { 725 uint32_t FormatDescriptorLayer2 : BITFIELD_RANGE( 0,7 ); 726 uint32_t ChromaSittingLocationLayer2 : BITFIELD_RANGE( 8,10 ); 727 uint32_t ChannelSwapEnablingFlagLayer2 : BITFIELD_RANGE( 11,11 ); 728 uint32_t IEFBypassEnablingFlagLayer2 : BITFIELD_RANGE( 12,12 ); 729 uint32_t RotationAngleMirrorDirectionLayer2 : BITFIELD_RANGE( 13,15 ); 730 uint32_t SamplerIndexFirstPlaneLayer2 : BITFIELD_RANGE( 16,19 ); 731 uint32_t SamplerIndexSecondThirdPlaneLayer2 : BITFIELD_RANGE( 20,23 ); 732 uint32_t CCMExtensionEnablingFlagLayer2 : BITFIELD_RANGE( 24,24 ); 733 uint32_t ToneMappingEnablingFlagLayer2 : BITFIELD_RANGE( 25,25 ); 734 uint32_t PriorCSCEnablingFlagLayer2 : BITFIELD_RANGE( 26,26 ); 735 uint32_t EOTF1DLUTEnablingFlagLayer2 : BITFIELD_RANGE( 27,27 ); 736 uint32_t CCMEnablingFlagLayer2 : BITFIELD_RANGE( 28,28 ); 737 uint32_t OETF1DLUTEnablingFlagLayer2 : BITFIELD_RANGE( 29,29 ); 738 uint32_t PostCSCEnablingFlagLayer2 : BITFIELD_RANGE( 30,30 ); 739 uint32_t Enabling3DLUTFlagLayer2 : BITFIELD_RANGE( 31,31 ); 740 }; 741 uint32_t Value; 742 } DW50; 743 744 // uint32_t 51 - GRF R7.3 745 union 746 { 747 struct { 748 uint32_t FormatDescriptorLayer3 : BITFIELD_RANGE( 0,7 ); 749 uint32_t ChromaSittingLocationLayer3 : BITFIELD_RANGE( 8,10 ); 750 uint32_t ChannelSwapEnablingFlagLayer3 : BITFIELD_RANGE( 11,11 ); 751 uint32_t IEFBypassEnablingFlagLayer3 : BITFIELD_RANGE( 12,12 ); 752 uint32_t RotationAngleMirrorDirectionLayer3 : BITFIELD_RANGE( 13,15 ); 753 uint32_t SamplerIndexFirstPlaneLayer3 : BITFIELD_RANGE( 16,19 ); 754 uint32_t SamplerIndexSecondThirdPlaneLayer3 : BITFIELD_RANGE( 20,23 ); 755 uint32_t CCMExtensionEnablingFlagLayer3 : BITFIELD_RANGE( 24,24 ); 756 uint32_t ToneMappingEnablingFlagLayer3 : BITFIELD_RANGE( 25,25 ); 757 uint32_t PriorCSCEnablingFlagLayer3 : BITFIELD_RANGE( 26,26 ); 758 uint32_t EOTF1DLUTEnablingFlagLayer3 : BITFIELD_RANGE( 27,27 ); 759 uint32_t CCMEnablingFlagLayer3 : BITFIELD_RANGE( 28,28 ); 760 uint32_t OETF1DLUTEnablingFlagLayer3 : BITFIELD_RANGE( 29,29 ); 761 uint32_t PostCSCEnablingFlagLayer3 : BITFIELD_RANGE( 30,30 ); 762 uint32_t Enabling3DLUTFlagLayer3 : BITFIELD_RANGE( 31,31 ); 763 }; 764 uint32_t Value; 765 } DW51; 766 767 // uint32_t 52 - GRF R7.4 768 union 769 { 770 struct { 771 uint32_t FormatDescriptorLayer4 : BITFIELD_RANGE( 0,7 ); 772 uint32_t ChromaSittingLocationLayer4 : BITFIELD_RANGE( 8,10 ); 773 uint32_t ChannelSwapEnablingFlagLayer4 : BITFIELD_RANGE( 11,11 ); 774 uint32_t IEFBypassEnablingFlagLayer4 : BITFIELD_RANGE( 12,12 ); 775 uint32_t RotationAngleMirrorDirectionLayer4 : BITFIELD_RANGE( 13,15 ); 776 uint32_t SamplerIndexFirstPlaneLayer4 : BITFIELD_RANGE( 16,19 ); 777 uint32_t SamplerIndexSecondThirdPlaneLayer4 : BITFIELD_RANGE( 20,23 ); 778 uint32_t CCMExtensionEnablingFlagLayer4 : BITFIELD_RANGE( 24,24 ); 779 uint32_t ToneMappingEnablingFlagLayer4 : BITFIELD_RANGE( 25,25 ); 780 uint32_t PriorCSCEnablingFlagLayer4 : BITFIELD_RANGE( 26,26 ); 781 uint32_t EOTF1DLUTEnablingFlagLayer4 : BITFIELD_RANGE( 27,27 ); 782 uint32_t CCMEnablingFlagLayer4 : BITFIELD_RANGE( 28,28 ); 783 uint32_t OETF1DLUTEnablingFlagLayer4 : BITFIELD_RANGE( 29,29 ); 784 uint32_t PostCSCEnablingFlagLayer4 : BITFIELD_RANGE( 30,30 ); 785 uint32_t Enabling3DLUTFlagLayer4 : BITFIELD_RANGE( 31,31 ); 786 }; 787 uint32_t Value; 788 } DW52; 789 790 // uint32_t 53 - GRF R7.5 791 union 792 { 793 struct { 794 uint32_t FormatDescriptorLayer5 : BITFIELD_RANGE( 0,7 ); 795 uint32_t ChromaSittingLocationLayer5 : BITFIELD_RANGE( 8,10 ); 796 uint32_t ChannelSwapEnablingFlagLayer5 : BITFIELD_RANGE( 11,11 ); 797 uint32_t IEFBypassEnablingFlagLayer5 : BITFIELD_RANGE( 12,12 ); 798 uint32_t RotationAngleMirrorDirectionLayer5 : BITFIELD_RANGE( 13,15 ); 799 uint32_t SamplerIndexFirstPlaneLayer5 : BITFIELD_RANGE( 16,19 ); 800 uint32_t SamplerIndexSecondThirdPlaneLayer5 : BITFIELD_RANGE( 20,23 ); 801 uint32_t CCMExtensionEnablingFlagLayer5 : BITFIELD_RANGE( 24,24 ); 802 uint32_t ToneMappingEnablingFlagLayer5 : BITFIELD_RANGE( 25,25 ); 803 uint32_t PriorCSCEnablingFlagLayer5 : BITFIELD_RANGE( 26,26 ); 804 uint32_t EOTF1DLUTEnablingFlagLayer5 : BITFIELD_RANGE( 27,27 ); 805 uint32_t CCMEnablingFlagLayer5 : BITFIELD_RANGE( 28,28 ); 806 uint32_t OETF1DLUTEnablingFlagLayer5 : BITFIELD_RANGE( 29,29 ); 807 uint32_t PostCSCEnablingFlagLayer5 : BITFIELD_RANGE( 30,30 ); 808 uint32_t Enabling3DLUTFlagLayer5 : BITFIELD_RANGE( 31,31 ); 809 }; 810 uint32_t Value; 811 } DW53; 812 813 // uint32_t 54 - GRF R7.6 814 union 815 { 816 struct { 817 uint32_t FormatDescriptorLayer6 : BITFIELD_RANGE( 0,7 ); 818 uint32_t ChromaSittingLocationLayer6 : BITFIELD_RANGE( 8,10 ); 819 uint32_t ChannelSwapEnablingFlagLayer6 : BITFIELD_RANGE( 11,11 ); 820 uint32_t IEFBypassEnablingFlagLayer6 : BITFIELD_RANGE( 12,12 ); 821 uint32_t RotationAngleMirrorDirectionLayer6 : BITFIELD_RANGE( 13,15 ); 822 uint32_t SamplerIndexFirstPlaneLayer6 : BITFIELD_RANGE( 16,19 ); 823 uint32_t SamplerIndexSecondThirdPlaneLayer6 : BITFIELD_RANGE( 20,23 ); 824 uint32_t CCMExtensionEnablingFlagLayer6 : BITFIELD_RANGE( 24,24 ); 825 uint32_t ToneMappingEnablingFlagLayer6 : BITFIELD_RANGE( 25,25 ); 826 uint32_t PriorCSCEnablingFlagLayer6 : BITFIELD_RANGE( 26,26 ); 827 uint32_t EOTF1DLUTEnablingFlagLayer6 : BITFIELD_RANGE( 27,27 ); 828 uint32_t CCMEnablingFlagLayer6 : BITFIELD_RANGE( 28,28 ); 829 uint32_t OETF1DLUTEnablingFlagLayer6 : BITFIELD_RANGE( 29,29 ); 830 uint32_t PostCSCEnablingFlagLayer6 : BITFIELD_RANGE( 30,30 ); 831 uint32_t Enabling3DLUTFlagLayer6 : BITFIELD_RANGE( 31,31 ); 832 }; 833 uint32_t Value; 834 } DW54; 835 836 // uint32_t 55 - GRF R7.7 837 union 838 { 839 struct { 840 uint32_t FormatDescriptorLayer7 : BITFIELD_RANGE( 0,7 ); 841 uint32_t ChromaSittingLocationLayer7 : BITFIELD_RANGE( 8,10 ); 842 uint32_t ChannelSwapEnablingFlagLayer7 : BITFIELD_RANGE( 11,11 ); 843 uint32_t IEFBypassEnablingFlagLayer7 : BITFIELD_RANGE( 12,12 ); 844 uint32_t RotationAngleMirrorDirectionLayer7 : BITFIELD_RANGE( 13,15 ); 845 uint32_t SamplerIndexFirstPlaneLayer7 : BITFIELD_RANGE( 16,19 ); 846 uint32_t SamplerIndexSecondThirdPlaneLayer7 : BITFIELD_RANGE( 20,23 ); 847 uint32_t CCMExtensionEnablingFlagLayer7 : BITFIELD_RANGE( 24,24 ); 848 uint32_t ToneMappingEnablingFlagLayer7 : BITFIELD_RANGE( 25,25 ); 849 uint32_t PriorCSCEnablingFlagLayer7 : BITFIELD_RANGE( 26,26 ); 850 uint32_t EOTF1DLUTEnablingFlagLayer7 : BITFIELD_RANGE( 27,27 ); 851 uint32_t CCMEnablingFlagLayer7 : BITFIELD_RANGE( 28,28 ); 852 uint32_t OETF1DLUTEnablingFlagLayer7 : BITFIELD_RANGE( 29,29 ); 853 uint32_t PostCSCEnablingFlagLayer7 : BITFIELD_RANGE( 30,30 ); 854 uint32_t Enabling3DLUTFlagLayer7 : BITFIELD_RANGE( 31,31 ); 855 }; 856 uint32_t Value; 857 } DW55; 858 859 // uint32_t 56 - GRF R8.0 860 union 861 { 862 struct { 863 uint32_t ConstantBlendingAlphaFillColorLayer0 : BITFIELD_RANGE( 0,7 ); 864 uint32_t ConstantBlendingAlphaFillColorLayer1 : BITFIELD_RANGE( 8,15 ); 865 uint32_t ConstantBlendingAlphaFillColorLayer2 : BITFIELD_RANGE( 16,23 ); 866 uint32_t ConstantBlendingAlphaFillColorLayer3 : BITFIELD_RANGE( 24,31 ); 867 }; 868 uint32_t Value; 869 } DW56; 870 871 // uint32_t 57 - GRF R8.1 872 union 873 { 874 struct { 875 uint32_t ConstantBlendingAlphaFillColorLayer4 : BITFIELD_RANGE( 0,7 ); 876 uint32_t ConstantBlendingAlphaFillColorLayer5 : BITFIELD_RANGE( 8,15 ); 877 uint32_t ConstantBlendingAlphaFillColorLayer6 : BITFIELD_RANGE( 16,23 ); 878 uint32_t ConstantBlendingAlphaFillColorLayer7 : BITFIELD_RANGE( 24,31 ); 879 }; 880 uint32_t Value; 881 } DW57; 882 883 // uint32_t 58 - GRF R8.2 884 union 885 { 886 struct { 887 uint32_t TwoLayerOperationLayer0 : BITFIELD_RANGE( 0,7 ); 888 uint32_t TwoLayerOperationLayer1 : BITFIELD_RANGE( 8,15 ); 889 uint32_t TwoLayerOperationLayer2 : BITFIELD_RANGE( 16,23 ); 890 uint32_t TwoLayerOperationLayer3 : BITFIELD_RANGE( 24,31 ); 891 }; 892 uint32_t Value; 893 } DW58; 894 895 // uint32_t 59 - GRF R8.3 896 union 897 { 898 struct { 899 uint32_t TwoLayerOperationLayer4 : BITFIELD_RANGE( 0,7 ); 900 uint32_t TwoLayerOperationLayer5 : BITFIELD_RANGE( 8,15 ); 901 uint32_t TwoLayerOperationLayer6 : BITFIELD_RANGE( 16,23 ); 902 uint32_t TwoLayerOperationLayer7 : BITFIELD_RANGE( 24,31 ); 903 }; 904 uint32_t Value; 905 } DW59; 906 907 // uint32_t 60 - GRF R8.4 908 union 909 { 910 struct { 911 uint32_t FixedPointFillColorRVChannel : BITFIELD_RANGE( 0,15 ); 912 uint32_t FixedPointFillColorGYChannel : BITFIELD_RANGE( 16,31 ); 913 }; 914 uint32_t Value; 915 } DW60; 916 917 // uint32_t 61 - GRF R8.5 918 union 919 { 920 struct { 921 uint32_t FixedPointFillColorBUChannel : BITFIELD_RANGE( 0,15 ); 922 uint32_t FixedPointFillColorAlphaChannel : BITFIELD_RANGE( 16,31 ); 923 }; 924 uint32_t Value; 925 } DW61; 926 927 // uint32_t 62 - GRF R8.6 928 union 929 { 930 struct { 931 uint32_t DestinationWidth : BITFIELD_RANGE( 0,15 ); 932 uint32_t DestinationHeight : BITFIELD_RANGE( 16,31 ); 933 }; 934 uint32_t Value; 935 } DW62; 936 937 // uint32_t 63 - GRF R8.7 938 union 939 { 940 struct { 941 uint32_t TotalNumberInputLayers : BITFIELD_RANGE( 0,15 ); 942 uint32_t FormatDescriptorDestination : BITFIELD_RANGE( 16,23 ); 943 uint32_t ChromaSittingLocationDestination : BITFIELD_RANGE( 24,26 ); 944 uint32_t ChannelSwapEnablingFlagDestination : BITFIELD_RANGE( 27,27 ); 945 uint32_t DstCSCEnablingFlagDestination : BITFIELD_RANGE( 28,28 ); 946 uint32_t Reserved : BITFIELD_RANGE( 29,29 ); 947 uint32_t DitherRoundEnablingFlagDestinationSurface : BITFIELD_RANGE( 30,31 ); 948 }; 949 uint32_t Value; 950 } DW63; 951 } MEDIA_WALKER_HDR_STATIC_DATA_G9, * PMEDIA_WALKER_HDR_STATIC_DATA_G9; 952 C_ASSERT(SIZE32(MEDIA_WALKER_HDR_STATIC_DATA_G9) == 64); 953 954 //! 955 //! \brief hdr kernel eotf/oetf type definition enum 956 //! 957 typedef enum _VPHAL_HDR_KERNEL_EOTF_TYPE_G9 958 { 959 VPHAL_HDR_KERNEL_EOTF_TRADITIONAL_GAMMA_G9 = 0, 960 VPHAL_HDR_KERNEL_SMPTE_ST2084_G9 = 1 961 } VPHAL_HDR_KERNEL_EOTF_TYPE_G9; 962 963 //! 964 //! \brief HDR Format Descriptor enum 965 //! 966 typedef enum _VPHAL_HDR_FORMAT_DESCRIPTOR_G9 967 { 968 VPHAL_HDR_FORMAT_DESCRIPTOR_UNKNOW_G9 = -1, 969 VPHAL_HDR_FORMAT_R16G16B16A16_FLOAT_G9 = 44, 970 VPHAL_HDR_FORMAT_DESCRIPTOR_R16G16_UNORM_G9 = 60, 971 VPHAL_HDR_FORMAT_DESCRIPTOR_R16_UNORM_G9 = 70, 972 VPHAL_HDR_FORMAT_DESCRIPTOR_R10G10B10A2_UNORM_G9 = 89, 973 VPHAL_HDR_FORMAT_DESCRIPTOR_R8G8B8A8_UNORM_G9 = 101, 974 VPHAL_HDR_FORMAT_DESCRIPTOR_YUY2_G9 = 201, 975 VPHAL_HDR_FORMAT_DESCRIPTOR_NV12_G9 = 220, 976 VPHAL_HDR_FORMAT_DESCRIPTOR_P010_G9 = 222, 977 VPHAL_HDR_FORMAT_DESCRIPTOR_P016_G9 = 223 978 } VPHAL_HDR_FORMAT_DESCRIPTOR_G9; 979 980 //! 981 //! \brief HDR Chroma Siting enum 982 //! 983 typedef enum _VPHAL_HDR_CHROMA_SITING_G9 984 { 985 VPHAL_HDR_CHROMA_SITTING_A_G9 = 0, // Sample even index at even line 986 VPHAL_HDR_CHROMA_SITTING_B_G9, // Sample even index at odd line 987 VPHAL_HDR_CHROMA_SITTING_AC_G9, // Average consistent even index and odd index at even line 988 VPHAL_HDR_CHROMA_SITTING_BD_G9, // Average consistent even index and odd index at odd line 989 VPHAL_HDR_CHROMA_SITTING_AB_G9, // Average even index of even line and even index of odd line 990 VPHAL_HDR_CHROMA_SITTING_ABCD_G9 // Average even and odd index at even line and odd line 991 } VPHAL_HDR_CHROMA_SITING_G9; 992 993 //! 994 //! \brief HDR Rotation enum 995 //! 996 typedef enum _VPHAL_HDR_ROTATION_G9 997 { 998 VPHAL_HDR_LAYER_ROTATION_0_G9 = 0, // 0 degree rotation 999 VPHAL_HDR_LAYER_ROTATION_90_G9, // 90 degree CW rotation 1000 VPHAL_HDR_LAYER_ROTATION_180_G9, // 180 degree rotation 1001 VPHAL_HDR_LAYER_ROTATION_270_G9, // 270 degree CW rotation 1002 VPHAL_HDR_LAYER_MIRROR_H_G9, // 0 degree rotation then mirror horizontally 1003 VPHAL_HDR_LAYER_ROT_90_MIR_H_G9, // 90 degree CW rotation then mirror horizontally 1004 VPHAL_HDR_LAYER_MIRROR_V_G9, // 180 degree rotation then mirror horizontally (vertical mirror) 1005 VPHAL_HDR_LAYER_ROT_90_MIR_V_G9 // 270 degree CW rotation then mirror horizontally (90 degree CW rotation then vertical mirror) 1006 } VPHAL_HDR_ROTATION_G9; 1007 1008 //! 1009 //! \brief Two Layer Option enum 1010 //! 1011 typedef enum _VPHAL_HDR_TWO_LAYER_OPTION_G9 1012 { 1013 VPHAL_HDR_TWO_LAYER_OPTION_SBLEND_G9 = 0, // Source Blending 1014 VPHAL_HDR_TWO_LAYER_OPTION_CBLEND_G9, // Constant Blending 1015 VPHAL_HDR_TWO_LAYER_OPTION_PBLEND_G9, // Partial Blending 1016 VPHAL_HDR_TWO_LAYER_OPTION_CSBLEND_G9, // Constant Source Blending 1017 VPHAL_HDR_TWO_LAYER_OPTION_CPBLEND_G9, // Constant Partial Blending 1018 VPHAL_HDR_TWO_LAYER_OPTION_COMP_G9 // Composition 1019 } VPHAL_HDR_TWO_LAYER_OPTION_G9; 1020 1021 //! 1022 //! \brief sampler state index enum 1023 //! 1024 typedef enum _VPHAL_HDR_SAMPLER_STATE_INDEX_G9 1025 { 1026 VPHAL_HDR_SAMPLER_STATE_AVS_NEAREST_INDEX_G9 = 1, 1027 VPHAL_HDR_SAMPLER_STATE_AVS_POLYPHASE_INDEX_G9 = 3, 1028 VPHAL_HDR_SAMPLER_STATE_3D_NEAREST_INDEX_G9 = 13, 1029 VPHAL_HDR_SAMPLER_STATE_3D_BILINEAR_INDEX_G9 = 14 1030 } VPHAL_HDR_SAMPLER_STATE_INDEX_G9; 1031 1032 //! 1033 //! \brief Destroy interface for HDR 1034 //! \details Destroy interface for HDR which is Gen9 platform specific 1035 //! \param PVPHAL_HDR_STATE pHdrState 1036 //! [in] Pointer to HDR state 1037 //! \return MOS_STATUS 1038 //! 1039 MOS_STATUS VpHal_HdrDestroyInterface_g9( 1040 PVPHAL_HDR_STATE pHdrState); 1041 1042 //! 1043 //! \brief Checks to see if HDR can be enabled for the formats 1044 //! \details Checks to see if HDR can be enabled for the formats 1045 //! \param PVPHAL_SURFACE pSrcSurface 1046 //! [in] Pointer to source surface 1047 //! \param bool* pbSupported 1048 //! [out] true supported false not supported 1049 //! \return MOS_STATUS 1050 //! MOS_STATUS_SUCCESS if successful, otherwise failed 1051 //! 1052 MOS_STATUS VpHal_HdrIsInputFormatSupported_g9( 1053 PVPHAL_SURFACE pSrcSurface, 1054 bool* pbSupported); 1055 1056 //! 1057 //! \brief Checks to see if HDR can be enabled for the formats 1058 //! \details Checks to see if HDR can be enabled for the formats 1059 //! \param PVPHAL_SURFACE pTargetSurface 1060 //! [in] Pointer to target surface 1061 //! \param bool* pbSupported 1062 //! [out] true supported false not supported 1063 //! \return MOS_STATUS 1064 //! MOS_STATUS_SUCCESS if successful, otherwise failed 1065 //! 1066 MOS_STATUS VpHal_HdrIsOutputFormatSupported_g9( 1067 PVPHAL_SURFACE pTargetSurface, 1068 bool* pbSupported); 1069 1070 //! 1071 //! \brief Allocate Resources for HDR 1072 //! \details Allocate Resources for HDR 1073 //! \param PVPHAL_HDR_STATE pHdrStatee 1074 //! [in] Pointer to HDR state 1075 //! \return void 1076 //! 1077 MOS_STATUS VpHal_HdrAllocateResources_g9( 1078 PVPHAL_HDR_STATE pHdrState); 1079 1080 //! 1081 //! \brief HDR Surface State Setup 1082 //! \details Set up surface state used in HDR process, and bind the surface to pointed binding table entry. 1083 //! \param PVPHAL_HDR_STATE pHdrState 1084 // [in/out] Pointer to HDR state 1085 //! \param PVPHAL_HDR_RENDER_DATA pRenderData 1086 //! [in] Pointer to hdr render data. 1087 //! \return MOS_STATUS 1088 //! MOS_STATUS_SUCCESS if successful, otherwise failed 1089 //! 1090 MOS_STATUS VpHal_HdrSetupSurfaceStates_g9( 1091 PVPHAL_HDR_STATE pHdrState, 1092 PVPHAL_HDR_RENDER_DATA pRenderData); 1093 1094 //! 1095 //! \brief Get the Kernel Params 1096 //! \details Get the Kernel Params, including kernel unique ID, KDT Index, and performance tag 1097 //! \param VPHAL_HDR_PHASE pHdrState 1098 //! [in] pointer to HDR State 1099 //! \param int32_t* pKUIDOut 1100 //! [out] Kernel unique ID 1101 //! \param int32_t* pKDTIndexOut 1102 //! [out] KDT index 1103 //! \param PVPHAL_PERFTAG pPerfTag 1104 //! [out] Performance tag 1105 //! \return MOS_STATUS 1106 //! MOS_STATUS_SUCCESS if successful, otherwise failed 1107 //! 1108 MOS_STATUS VpHal_HdrGetKernelParam_g9( 1109 uint32_t HdrKernelID, 1110 int32_t* pKUIDOut, 1111 int32_t* pKDTIndexOut); 1112 1113 //! 1114 //! \brief Load CURBE for HDR kernel 1115 //! \details Load CURBE for Gen9 HDR kernel, but also expose it to be used by subsequent generations. 1116 //! \param PVPHAL_HDR_STATE pHdrState 1117 //! [in] Pointer to HDR state 1118 //! \param PVPHAL_HDR_RENDER_DATA pRenderData 1119 //! [in] Poniter to HDR render data 1120 //! \param int32_t* piCurbeOffsetOut 1121 //! [Out] Curbe offset 1122 //! \return MOS_STATUS 1123 //! 1124 MOS_STATUS VpHal_HdrLoadStaticData_g9( 1125 PVPHAL_HDR_STATE pHdrState, 1126 PVPHAL_HDR_RENDER_DATA pRenderData, 1127 int32_t* piCurbeOffsetOut); 1128 1129 //! \brief Get the HDR format descriptor of a format 1130 //! \details Get the HDR format descriptor of a format and return. 1131 //! \param MOS_FORMAT Format 1132 //! [in] MOS_FORMAT of a surface 1133 //! \return VPHAL_HDR_FORMAT_DESCRIPTOR_G9 1134 //! HDR format descriptor 1135 //! 1136 VPHAL_HDR_FORMAT_DESCRIPTOR_G9 VpHal_HdrGetFormatDescriptor_g9( 1137 MOS_FORMAT Format); 1138 1139 //! \brief Get the HDR Chroma siting 1140 //! \details Get the HDR Chroma siting and return. 1141 //! \param uint32_t ChromaSiting 1142 //! [in] ChromaSiting of a surface 1143 //! \return VPHAL_HDR_CHROMA_SITING_G9 1144 //! HDR Chroma siting 1145 //! 1146 VPHAL_HDR_CHROMA_SITING_G9 VpHal_HdrGetHdrChromaSiting_g9( 1147 uint32_t ChromaSiting); 1148 1149 //! \brief Get the HDR rotation 1150 //! \details Get the HDR rotation and return. 1151 //! \param VPHAL_ROTATION Rotation 1152 //! [in] Rotation of a surface 1153 //! \return VPHAL_HDR_ROTATION_G9 1154 //! HDR Chroma siting 1155 //! 1156 VPHAL_HDR_ROTATION_G9 VpHal_HdrGetHdrRotation_g9( 1157 VPHAL_ROTATION Rotation); 1158 1159 //! 1160 //! \brief Initializes interface for HDR 1161 //! \details Initializes interface for HDR which is Gen9 platform specific 1162 //! \param PVPHAL_HDR_STATE pHdrState 1163 //! [in] Pointer to HDR state 1164 //! \return MOS_STATUS 1165 //! 1166 MOS_STATUS VpHal_HdrInitInterface_g9( 1167 PVPHAL_HDR_STATE pHdrState); 1168 1169 //! 1170 //! \brief Checks to see if HDR can be enabled for the formats 1171 //! \details Checks to see if HDR can be enabled for the formats 1172 //! \param PVPHAL_SURFACE pSrcSurface 1173 //! [in] Pointer to source surface 1174 //! \param bool* pbSupported 1175 //! [out] true supported false not supported 1176 //! \return MOS_STATUS 1177 //! MOS_STATUS_SUCCESS if successful, otherwise failed 1178 //! 1179 MOS_STATUS VpHal_HdrIsInputFormatSupported_g9( 1180 PVPHAL_SURFACE pSrcSurface, 1181 bool* pbSupported); 1182 1183 //! 1184 //! \brief Checks to see if HDR can be enabled for the formats 1185 //! \details Checks to see if HDR can be enabled for the formats 1186 //! \param PVPHAL_SURFACE pTargetSurface 1187 //! [in] Pointer to target surface 1188 //! \param bool* pbSupported 1189 //! [out] true supported false not supported 1190 //! \return MOS_STATUS 1191 //! MOS_STATUS_SUCCESS if successful, otherwise failed 1192 //! 1193 MOS_STATUS VpHal_HdrIsOutputFormatSupported_g9( 1194 PVPHAL_SURFACE pTargetSurface, 1195 bool* pbSupported); 1196 1197 //! 1198 //! \brief Initiate EOTF Surface for HDR 1199 //! \details Initiate EOTF Surface for HDR 1200 //! \param PVPHAL_HDR_STATE pHdrStatee 1201 //! [in] Pointer to HDR state 1202 //! \param int32_t iIndex 1203 //! [in] input surface index 1204 //! \param PVPHAL_SURFACE pOETF1DLUTSurface 1205 //! [in] Pointer to OETF 1D LUT Surface 1206 //! \return MOS_STATUS 1207 //! 1208 MOS_STATUS VpHal_HdrInitOETF1DLUT_g9( 1209 PVPHAL_HDR_STATE pHdrState, 1210 int32_t iIndex, 1211 PVPHAL_SURFACE pOETF1DLUTSurface); 1212 1213 //! 1214 //! \brief Set HDR Ief State 1215 //! \details Set HDR Ief State 1216 //! \param PVPHAL_HDR_STATE pHdrState 1217 //! [in] Pointer to HDR state 1218 //! \param PVPHAL_HDR_RENDER_DATA pRenderData 1219 //! [in] Pointer to render data 1220 //! \param PMHW_SAMPLER_STATE_PARAM pSamplerStateParams 1221 //! [in] Pointer to Sampler State Parameters 1222 //! \return MOS_STATUS 1223 //! 1224 MOS_STATUS VpHal_HdrSetIefStates_g9( 1225 PVPHAL_HDR_STATE pHdrState, 1226 PVPHAL_HDR_RENDER_DATA pRenderData, 1227 PMHW_SAMPLER_STATE_PARAM pSamplerStateParams); 1228 1229 //! 1230 //! \brief Set the Sampler States 1231 //! \details Set the Sampler States 1232 //! \param VPHAL_HDR_PHASE pHdrState 1233 //! [in] pointer to HDR State 1234 //! \param PVPHAL_HDR_RENDER_DATA 1235 //! [in] HDR render data 1236 //! \return MOS_STATUS 1237 //! MOS_STATUS_SUCCESS if successful, otherwise failed 1238 //! 1239 MOS_STATUS VpHal_HdrSetSamplerStates_g9 ( 1240 PVPHAL_HDR_STATE pHdrState, 1241 PVPHAL_HDR_RENDER_DATA pRenderData); 1242 1243 //! 1244 //! \brief Set Sampler8x8 Table for Gen9 Hdr AVS 1245 //! \details Set sampler8x8 table based on format, scale and chroma siting 1246 //! \param PRENDERHAL_INTERFACE pRenderHal 1247 //! [in] Pointer to RenderHal interface 1248 //! \param PMHW_SAMPLER_STATE_PARAM pSamplerStateParams, 1249 //! [in] Pointer to sampler state params 1250 //! \param PVPHAL_AVS_PARAMS pAvsParams 1251 //! [in] Pointer to avs parameters 1252 //! \param MOS_FORMAT SrcFormat 1253 //! [in] source format 1254 //! \param float fScaleX 1255 //! [in] Scale X 1256 //! \param float fScaleY 1257 //! [in] Scale Y 1258 //! \param uint32_t dwChromaSiting 1259 //! [in] Chroma siting 1260 //! \return void 1261 //! 1262 MOS_STATUS VpHal_HdrSetSamplerAvsTableParam_g9( 1263 PRENDERHAL_INTERFACE pRenderHal, 1264 PMHW_SAMPLER_STATE_PARAM pSamplerStateParams, 1265 PMHW_AVS_PARAMS pAvsParams, 1266 MOS_FORMAT SrcFormat, 1267 float fScaleX, 1268 float fScaleY, 1269 uint32_t dwChromaSiting); 1270 1271 //! 1272 //! \brief Get Hdr iTouch Split Frame Portion number 1273 //! \details Get Hdr iTouch Split Frame Portion number is Gen9 platform specific 1274 //! \param PVPHAL_HDR_STATE pHdrState 1275 //! [in/out] Pointer to HDR state 1276 //! \return MOS_STATUS 1277 //! 1278 MOS_STATUS VpHal_HdrGetSplitFramePortion_g9( 1279 PVPHAL_HDR_STATE pHdrState); 1280 1281 //! 1282 //! \brief HDR PreProcess Surface State Setup 1283 //! \details Set up surface state used in HDR PreProcess, and bind the surface to pointed binding table entry. 1284 //! \param PVPHAL_HDR_STATE pHdrState 1285 // [in/out] Pointer to HDR state 1286 //! \param PVPHAL_HDR_RENDER_DATA pRenderData 1287 //! [in] Pointer to hdr render data. 1288 //! \return MOS_STATUS 1289 //! MOS_STATUS_SUCCESS if successful, otherwise failed 1290 //! 1291 MOS_STATUS VpHal_HdrSetupPreProcessSurfaceStates_g9( 1292 PVPHAL_HDR_STATE pHdrState, 1293 PVPHAL_HDR_RENDER_DATA pRenderData); 1294 1295 //! 1296 //! \brief Setup HDR PreProcess CURBE data 1297 //! \details Setup HDR PreProcess CURBE data 1298 //! \param PVPHAL_HDR_STATE pHdrState 1299 //! [in] Poniter to HDR state 1300 //! \param PVPHAL_HDR_RENDER_DATA pRenderData 1301 //! [in] Poniter to HDR render data 1302 //! \param int32_t* piCurbeOffsetOut 1303 //! [Out] Curbe offset 1304 //! \return MOS_STATUS 1305 //! MOS_STATUS_SUCCESS if successful, otherwise 1306 //! 1307 MOS_STATUS VpHal_HdrPreprocessLoadStaticData_g9( 1308 PVPHAL_HDR_STATE pHdrState, 1309 PVPHAL_HDR_RENDER_DATA pRenderData, 1310 int32_t* piCurbeOffsetOut); 1311 #if __cplusplus 1312 } 1313 #endif // __cplusplus 1314 #endif // __VPHAL_RENDER_HDR_G9_BASE_H__ 1315