1 /*===================== begin_copyright_notice ================================== 2 3 * Copyright (c) 2015-2020, Intel Corporation 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included 13 * in all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 16 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 23 ======================= end_copyright_notice ==================================*/ 24 //! 25 //! \file mhw_render_hwcmd_xe_hpg.h 26 //! \brief Auto-generated constructors for MHW and states. 27 //! \details This file may not be included outside of Xe_HPG as other components 28 //! should use MHW interface to interact with MHW commands and states. 29 //! 30 #ifndef __MHW_RENDER_HWCMD_XE_HPG_H__ 31 #define __MHW_RENDER_HWCMD_XE_HPG_H__ 32 33 #include "mhw_hwcmd.h" 34 #pragma once 35 #pragma pack(1) 36 37 namespace mhw 38 { 39 namespace render 40 { 41 namespace xe_hpg 42 { 43 struct Cmd 44 { 45 public: 46 47 // Internal Macros 48 #define __CODEGEN_MAX(_a, _b) (((_a) > (_b)) ? (_a) : (_b)) 49 #define __CODEGEN_BITFIELD(l, h) (h) - (l) + 1 50 #define __CODEGEN_OP_LENGTH_BIAS 2 51 #define __CODEGEN_OP_LENGTH(x) (uint32_t)((__CODEGEN_MAX(x, __CODEGEN_OP_LENGTH_BIAS)) - __CODEGEN_OP_LENGTH_BIAS) 52 GetOpLengthCmd53 static uint32_t GetOpLength(uint32_t uiLength) { return __CODEGEN_OP_LENGTH(uiLength); } 54 55 struct PIPELINE_SELECT_CMD 56 { 57 union 58 { 59 struct 60 { 61 uint32_t PipelineSelection : __CODEGEN_BITFIELD(0, 1); //!< PIPELINE_SELECTION 62 uint32_t RenderSliceCommonPowerGateEnable : __CODEGEN_BITFIELD(2, 2); //!< RENDER_SLICE_COMMON_POWER_GATE_ENABLE 63 uint32_t RenderSamplerPowerGateEnable : __CODEGEN_BITFIELD(3, 3); //!< RENDER_SAMPLER_POWER_GATE_ENABLE 64 uint32_t MediaSamplerDopClockGateEnable : __CODEGEN_BITFIELD(4, 4); //!< MEDIA_SAMPLER_DOP_CLOCK_GATE_ENABLE 65 uint32_t Reserved5 : __CODEGEN_BITFIELD(5, 5); //!< Reserved 66 uint32_t MediaSamplerPowerClockGateDisable : __CODEGEN_BITFIELD(6, 6); //!< Media Sampler Power Clock Gate Disable 67 uint32_t SystolicModeEnable : __CODEGEN_BITFIELD(7, 7); //!< SYSTOLIC_MODE_ENABLE 68 uint32_t MaskBits : __CODEGEN_BITFIELD(8, 15); //!< Mask Bits 69 uint32_t _3DCommandSubOpcode : __CODEGEN_BITFIELD(16, 23); //!< _3D_COMMAND_SUB_OPCODE 70 uint32_t _3DCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< _3D_COMMAND_OPCODE 71 uint32_t CommandSubtype : __CODEGEN_BITFIELD(27, 28); //!< COMMAND_SUBTYPE 72 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 73 }; 74 uint32_t Value; 75 } DW0; 76 77 //! \name Local enumerations 78 79 //! \brief PIPELINE_SELECTION 80 //! \details 81 //! Mask bits [9:8] has to be set for HW to look at this field when 82 //! PIPELINE_SELECT command is parsed. Setting only one of the mask bit [9] 83 //! or [8] is illegal. 84 enum PIPELINE_SELECTION 85 { 86 PIPELINE_SELECTION_3D = 0, //!< 3D pipeline is selected 87 PIPELINE_SELECTION_MEDIA = 1, //!< Media pipeline is selected (Includes HD optical disc playback, HD video playback, and generic media workloads) 88 PIPELINE_SELECTION_GPGPU = 2, //!< GPGPU pipeline is selected 89 }; 90 91 //! \brief RENDER_SLICE_COMMON_POWER_GATE_ENABLE 92 //! \details 93 //! Mask bit [10] has to be set for HW to look at this field when 94 //! PIPELINE_SELECT command is parsed. 95 enum RENDER_SLICE_COMMON_POWER_GATE_ENABLE 96 { 97 RENDER_SLICE_COMMON_POWER_GATE_ENABLE_DISABLED = 0, //!< Command Streamer sends message to PM to disable render slice common Power Gating. 98 RENDER_SLICE_COMMON_POWER_GATE_ENABLE_ENABLED = 1, //!< Command Streamer sends message to PM to enable render slice common Power Gating. 99 }; 100 101 //! \brief RENDER_SAMPLER_POWER_GATE_ENABLE 102 //! \details 103 //! Mask bit [11] has to be set for HW to look at this field when 104 //! PIPELINE_SELECT command is parsed. 105 enum RENDER_SAMPLER_POWER_GATE_ENABLE 106 { 107 RENDER_SAMPLER_POWER_GATE_ENABLE_DISABLED = 0, //!< Command Streamer sends message to PM to disable render sampler Power Gating. 108 RENDER_SAMPLER_POWER_GATE_ENABLE_ENABLED = 1, //!< Command Streamer sends message to PM to enable render sampler Power Gating. 109 }; 110 111 //! \brief MEDIA_SAMPLER_DOP_CLOCK_GATE_ENABLE 112 //! \details 113 //! Mask bit [12] has to be set for HW to look at this field when 114 //! PIPELINE_SELECT command is parsed. 115 enum MEDIA_SAMPLER_DOP_CLOCK_GATE_ENABLE 116 { 117 MEDIA_SAMPLER_DOP_CLOCK_GATE_ENABLE_DISABLED = 0, //!< Command Streamer sends message to PM to disable sampler DOP Clock Gating. 118 MEDIA_SAMPLER_DOP_CLOCK_GATE_ENABLE_ENABLED = 1, //!< Command Streamer sends message to PM to enable media sampler DOP Clock Gating. 119 }; 120 121 //! \brief SYSTOLIC_MODE_ENABLE 122 //! \details 123 //! When set, this will enable systolic mode for the following 124 //! COMPUTE_WALKER commands. This will lower the Fmax to avoid ICC current 125 //! issues when executing systolic array commands in the execution units. If 126 //! this is not set prior to executing systolic array operations, the 127 //! context will be halted to avoid any ICC issues. 128 enum SYSTOLIC_MODE_ENABLE 129 { 130 SYSTOLIC_MODE_ENABLE_SYSTOLICMODEDISABLED = 0, //!< No additional details 131 SYSTOLIC_MODE_ENABLE_SYSTOLICMODEENABLED = 1, //!< No additional details 132 }; 133 134 enum _3D_COMMAND_SUB_OPCODE 135 { 136 _3D_COMMAND_SUB_OPCODE_PIPELINESELECT = 4, //!< No additional details 137 }; 138 139 enum _3D_COMMAND_OPCODE 140 { 141 _3D_COMMAND_OPCODE_GFXPIPENONPIPELINED = 1, //!< No additional details 142 }; 143 144 enum COMMAND_SUBTYPE 145 { 146 COMMAND_SUBTYPE_GFXPIPESINGLEDW = 1, //!< No additional details 147 }; 148 149 enum COMMAND_TYPE 150 { 151 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 152 }; 153 154 //! \name Initializations 155 156 //! \brief Explicit member initialization function PIPELINE_SELECT_CMDCmd::PIPELINE_SELECT_CMD157 PIPELINE_SELECT_CMD() 158 { 159 DW0.Value = 0x69040000; 160 //DW0.PipelineSelection = PIPELINE_SELECTION_3D; 161 //DW0.RenderSliceCommonPowerGateEnable = RENDER_SLICE_COMMON_POWER_GATE_ENABLE_DISABLED; 162 //DW0.RenderSamplerPowerGateEnable = RENDER_SAMPLER_POWER_GATE_ENABLE_DISABLED; 163 //DW0.MediaSamplerDopClockGateEnable = MEDIA_SAMPLER_DOP_CLOCK_GATE_ENABLE_DISABLED; 164 //DW0.SystolicModeEnable = SYSTOLIC_MODE_ENABLE_SYSTOLICMODEDISABLED; 165 //DW0._3DCommandSubOpcode = _3D_COMMAND_SUB_OPCODE_PIPELINESELECT; 166 //DW0._3DCommandOpcode = _3D_COMMAND_OPCODE_GFXPIPENONPIPELINED; 167 //DW0.CommandSubtype = COMMAND_SUBTYPE_GFXPIPESINGLEDW; 168 //DW0.CommandType = COMMAND_TYPE_GFXPIPE; 169 } 170 171 static const size_t dwSize = 1; 172 static const size_t byteSize = 4; 173 }; 174 175 //! 176 //! \brief STATE_BASE_ADDRESS 177 //! \details 178 //! The STATE_BASE_ADDRESS command sets the base pointers for subsequent 179 //! state, instruction, and media indirect object accesses by the GPE. 180 //! For more information see the Base Address Utilization table in the 181 //! Memory Access Indirection narrative topic. 182 //! 183 //! The following commands must be reissued following any change to the base 184 //! addresses: 185 //! 186 //! 3DSTATE_CC_POINTERS 187 //! 188 //! 3DSTATE_BINDING_TABLE_POINTERS 189 //! 190 //! 3DSTATE_SAMPLER_STATE_POINTERS 191 //! 192 //! 3DSTATE_VIEWPORT_STATE_POINTERS 193 //! 194 //! 195 //! 196 //! 197 //! 198 //! Execution of this command causes a full pipeline flush, thus its use 199 //! should be minimized for higher performance. 200 //! 201 //! If 3DSTATE_PS_EXTRA::Pixel Shader Is Per Coarse Pixel == 1, the 202 //! 3DSTATE_CPS_POINTERS command must be reissued following any change to 203 //! the dynamic state base address. 204 //! 205 //! SW must always program PIPE_CONTROL with "CS Stall" and "Render Target 206 //! Cache Flush Enable" set before programming STATE_BASE_ADDRESS command 207 //! for GPGPU workloads i.e when pipeline select is GPGPU via 208 //! PIPELINE_SELECT command. This is required to achieve better GPGPU 209 //! preemption latencies in certain workload programming sequences. If 210 //! programming PIPE_CONTROL has performance implications then preemption 211 //! latencies can be traded off against performance by not implementing this 212 //! programming note. 213 //! 214 //! SW must always program PIPE_CONTROL command with "HDC Pipleine FLush" 215 //! set prior to programming of STATE_BASE_ADDRESS command for GPGPU/Media 216 //! workloads i.e when pipeline select is GPGPU or Media via PIPELINE_SELECT 217 //! command. This is required to ensure thewrite data out of the prior 218 //! thread group are flushed out prior to the state changes due to the 219 //! programming of STATE_BASE_ADDRESS command take place. 220 //! 221 struct STATE_BASE_ADDRESS_CMD 222 { 223 union 224 { 225 struct 226 { 227 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 7); //!< DWORD_LENGTH 228 uint32_t Reserved8 : __CODEGEN_BITFIELD(8, 15); //!< Reserved 229 uint32_t Command3DSubOpcode : __CODEGEN_BITFIELD(16, 23); //!< _3D_COMMAND_SUB_OPCODE 230 uint32_t Command3DOpcode : __CODEGEN_BITFIELD(24, 26); //!< _3D_COMMAND_OPCODE 231 uint32_t CommandSubtype : __CODEGEN_BITFIELD(27, 28); //!< COMMAND_SUBTYPE 232 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 233 }; 234 uint32_t Value; 235 } DW0; 236 union 237 { 238 struct 239 { 240 uint64_t GeneralStateBaseAddressModifyEnable : __CODEGEN_BITFIELD(0, 0); //!< GENERAL_STATE_BASE_ADDRESS_MODIFY_ENABLE 241 uint64_t Reserved33 : __CODEGEN_BITFIELD(1, 3); //!< Reserved 242 uint64_t GeneralStateMemoryObjectControlState : __CODEGEN_BITFIELD(4, 10); //!< General State Memory Object Control State 243 uint64_t Reserved43 : __CODEGEN_BITFIELD(11, 11); //!< Reserved 244 uint64_t GeneralStateBaseAddress : __CODEGEN_BITFIELD(12, 63); //!< General State Base Address 245 }; 246 uint32_t Value[2]; 247 } DW1_2; 248 union 249 { 250 struct 251 { 252 uint32_t CoherencySettingModifyEnable : __CODEGEN_BITFIELD(0, 0); //!< COHERENCY_SETTING_MODIFY_ENABLE 253 uint32_t Reserved97 : __CODEGEN_BITFIELD(1, 12); //!< Reserved 254 uint32_t EnableMemoryCompressionForAllStatelessAccesses : __CODEGEN_BITFIELD(13, 13); //!< ENABLE_MEMORY_COMPRESSION_FOR_ALL_STATELESS_ACCESSES 255 uint32_t DisableSupportForMultiGpuAtomicsForStatelessAccesses : __CODEGEN_BITFIELD(14, 14); //!< DISABLE_SUPPORT_FOR_MULTI_GPU_ATOMICS_FOR_STATELESS_ACCESSES 256 uint32_t DisableSupportForMultiGpuPartialWritesForStatelessMessages : __CODEGEN_BITFIELD(15, 15); //!< DISABLE_SUPPORT_FOR_MULTI_GPU_PARTIAL_WRITES_FOR_STATELESS_MESSAGES 257 uint32_t StatelessDataPortAccessMemoryObjectControlState : __CODEGEN_BITFIELD(16, 22); //!< Stateless Data Port Access Memory Object Control State 258 uint32_t L1CachePolicy : __CODEGEN_BITFIELD(23, 25); //!< L1 Cache Policy for stateless accesses 259 uint32_t Reserved119 : __CODEGEN_BITFIELD(26, 31); //!< Reserved 260 }; 261 uint32_t Value; 262 } DW3; 263 union 264 { 265 struct 266 { 267 uint64_t SurfaceStateBaseAddressModifyEnable : __CODEGEN_BITFIELD(0, 0); //!< SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE 268 uint64_t Reserved129 : __CODEGEN_BITFIELD(1, 3); //!< Reserved 269 uint64_t SurfaceStateMemoryObjectControlState : __CODEGEN_BITFIELD(4, 10); //!< Surface State Memory Object Control State 270 uint64_t Reserved139 : __CODEGEN_BITFIELD(11, 11); //!< Reserved 271 uint64_t SurfaceStateBaseAddress : __CODEGEN_BITFIELD(12, 63); //!< Surface State Base Address 272 }; 273 uint32_t Value[2]; 274 } DW4_5; 275 union 276 { 277 struct 278 { 279 uint64_t DynamicStateBaseAddressModifyEnable : __CODEGEN_BITFIELD(0, 0); //!< DYNAMIC_STATE_BASE_ADDRESS_MODIFY_ENABLE 280 uint64_t Reserved193 : __CODEGEN_BITFIELD(1, 3); //!< Reserved 281 uint64_t DynamicStateMemoryObjectControlState : __CODEGEN_BITFIELD(4, 10); //!< Dynamic State Memory Object Control State 282 uint64_t Reserved203 : __CODEGEN_BITFIELD(11, 11); //!< Reserved 283 uint64_t DynamicStateBaseAddress : __CODEGEN_BITFIELD(12, 63); //!< Dynamic State Base Address 284 }; 285 uint32_t Value[2]; 286 } DW6_7; 287 union 288 { 289 struct 290 { 291 uint64_t IndirectObjectBaseAddressModifyEnable : __CODEGEN_BITFIELD(0, 0); //!< INDIRECT_OBJECT_BASE_ADDRESS_MODIFY_ENABLE 292 uint64_t Reserved257 : __CODEGEN_BITFIELD(1, 3); //!< Reserved 293 uint64_t IndirectObjectMemoryObjectControlState : __CODEGEN_BITFIELD(4, 10); //!< Indirect Object Memory Object Control State 294 uint64_t Reserved267 : __CODEGEN_BITFIELD(11, 11); //!< Reserved 295 uint64_t IndirectObjectBaseAddress : __CODEGEN_BITFIELD(12, 63); //!< Indirect Object Base Address 296 }; 297 uint32_t Value[2]; 298 } DW8_9; 299 union 300 { 301 struct 302 { 303 uint64_t InstructionBaseAddressModifyEnable : __CODEGEN_BITFIELD(0, 0); //!< INSTRUCTION_BASE_ADDRESS_MODIFY_ENABLE 304 uint64_t Reserved321 : __CODEGEN_BITFIELD(1, 3); //!< Reserved 305 uint64_t InstructionMemoryObjectControlState : __CODEGEN_BITFIELD(4, 10); //!< Instruction Memory Object Control State 306 uint64_t Reserved331 : __CODEGEN_BITFIELD(11, 11); //!< Reserved 307 uint64_t InstructionBaseAddress : __CODEGEN_BITFIELD(12, 63); //!< Instruction Base Address 308 }; 309 uint32_t Value[2]; 310 } DW10_11; 311 union 312 { 313 struct 314 { 315 uint32_t GeneralStateBufferSizeModifyEnable : __CODEGEN_BITFIELD(0, 0); //!< GENERAL_STATE_BUFFER_SIZE_MODIFY_ENABLE 316 uint32_t Reserved385 : __CODEGEN_BITFIELD(1, 11); //!< Reserved 317 uint32_t GeneralStateBufferSize : __CODEGEN_BITFIELD(12, 31); //!< General State Buffer Size 318 }; 319 uint32_t Value; 320 } DW12; 321 union 322 { 323 struct 324 { 325 uint32_t DynamicStateBufferSizeModifyEnable : __CODEGEN_BITFIELD(0, 0); //!< DYNAMIC_STATE_BUFFER_SIZE_MODIFY_ENABLE 326 uint32_t Reserved417 : __CODEGEN_BITFIELD(1, 11); //!< Reserved 327 uint32_t DynamicStateBufferSize : __CODEGEN_BITFIELD(12, 31); //!< Dynamic State Buffer Size 328 }; 329 uint32_t Value; 330 } DW13; 331 union 332 { 333 struct 334 { 335 uint32_t IndirectObjectBufferSizeModifyEnable : __CODEGEN_BITFIELD(0, 0); //!< INDIRECT_OBJECT_BUFFER_SIZE_MODIFY_ENABLE 336 uint32_t Reserved449 : __CODEGEN_BITFIELD(1, 11); //!< Reserved 337 uint32_t IndirectObjectBufferSize : __CODEGEN_BITFIELD(12, 31); //!< Indirect Object Buffer Size 338 }; 339 uint32_t Value; 340 } DW14; 341 union 342 { 343 struct 344 { 345 uint32_t InstructionBufferSizeModifyEnable : __CODEGEN_BITFIELD(0, 0); //!< INSTRUCTION_BUFFER_SIZE_MODIFY_ENABLE 346 uint32_t Reserved481 : __CODEGEN_BITFIELD(1, 11); //!< Reserved 347 uint32_t InstructionBufferSize : __CODEGEN_BITFIELD(12, 31); //!< Instruction Buffer Size 348 }; 349 uint32_t Value; 350 } DW15; 351 union 352 { 353 struct 354 { 355 uint64_t BindlessSurfaceStateBaseAddressModifyEnable : __CODEGEN_BITFIELD(0, 0); //!< BINDLESS_SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE 356 uint64_t Reserved513 : __CODEGEN_BITFIELD(1, 3); //!< Reserved 357 uint64_t BindlessSurfaceStateMemoryObjectControlState : __CODEGEN_BITFIELD(4, 10); //!< Bindless Surface State Memory Object Control State 358 uint64_t Reserved523 : __CODEGEN_BITFIELD(11, 11); //!< Reserved 359 uint64_t BindlessSurfaceStateBaseAddress : __CODEGEN_BITFIELD(12, 63); //!< Bindless Surface State Base Address 360 }; 361 uint32_t Value[2]; 362 } DW16_17; 363 union 364 { 365 struct 366 { 367 uint32_t BindlessSurfaceStateSize; //!< Bindless Surface State Size 368 }; 369 uint32_t Value; 370 } DW18; 371 union 372 { 373 struct 374 { 375 uint64_t BindlessSamplerStateBaseAddressModifyEnable : __CODEGEN_BITFIELD(0, 0); //!< BINDLESS_SAMPLER_STATE_BASE_ADDRESS_MODIFY_ENABLE 376 uint64_t Reserved609 : __CODEGEN_BITFIELD(1, 3); //!< Reserved 377 uint64_t BindlessSamplerStateMemoryObjectControlState : __CODEGEN_BITFIELD(4, 10); //!< Bindless Sampler State Memory Object Control State 378 uint64_t Reserved619 : __CODEGEN_BITFIELD(11, 11); //!< Reserved 379 uint64_t BindlessSamplerStateBaseAddress : __CODEGEN_BITFIELD(12, 63); //!< Bindless Sampler State Base Address 380 }; 381 uint32_t Value[2]; 382 } DW19_20; 383 union 384 { 385 struct 386 { 387 uint32_t Reserved672 : __CODEGEN_BITFIELD(0, 11); //!< Reserved 388 uint32_t BindlessSamplerStateBufferSize : __CODEGEN_BITFIELD(12, 31); //!< Bindless Sampler State Buffer Size 389 }; 390 uint32_t Value; 391 } DW21; 392 393 //! \name Local enumerations 394 395 enum _3D_COMMAND_SUB_OPCODE 396 { 397 _3D_COMMAND_SUB_OPCODE_STATEBASEADDRESS = 1, //!< No additional details 398 }; 399 400 enum _3D_COMMAND_OPCODE 401 { 402 _3D_COMMAND_OPCODE_GFXPIPENONPIPELINED = 1, //!< No additional details 403 }; 404 405 enum COMMAND_SUBTYPE 406 { 407 COMMAND_SUBTYPE_GFXPIPECOMMON = 0, //!< No additional details 408 }; 409 410 enum COMMAND_TYPE 411 { 412 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 413 }; 414 415 //! \brief GENERAL_STATE_BASE_ADDRESS_MODIFY_ENABLE 416 //! \details 417 //! The other fields in this DWord and the following DWord are updated 418 //! only when this bit is set. 419 enum GENERAL_STATE_BASE_ADDRESS_MODIFY_ENABLE 420 { 421 GENERAL_STATE_BASE_ADDRESS_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated address. 422 GENERAL_STATE_BASE_ADDRESS_MODIFY_ENABLE_ENABLE = 1, //!< Modify the address. 423 }; 424 425 //! \brief COHERENCY_SETTING_MODIFY_ENABLE 426 //! \details 427 //! All the fields in this DW is only updated when this bit is set. 428 enum COHERENCY_SETTING_MODIFY_ENABLE 429 { 430 COHERENCY_SETTING_MODIFY_ENABLE_DISABLEWRITETOTHISDW = 0, //!< No additional details 431 COHERENCY_SETTING_MODIFY_ENABLE_ENABLEWRITETOTHISDW = 1, //!< No additional details 432 }; 433 434 //! \brief ENABLE_MEMORY_COMPRESSION_FOR_ALL_STATELESS_ACCESSES 435 //! \details 436 //! Enable compression for stateless memory accesses. 437 enum ENABLE_MEMORY_COMPRESSION_FOR_ALL_STATELESS_ACCESSES 438 { 439 ENABLE_MEMORY_COMPRESSION_FOR_ALL_STATELESS_ACCESSES_DISABLED = 0, //!< No additional details 440 ENABLE_MEMORY_COMPRESSION_FOR_ALL_STATELESS_ACCESSES_ENABLED = 1, //!< No additional details 441 }; 442 443 //! \brief DISABLE_SUPPORT_FOR_MULTI_GPU_ATOMICS_FOR_STATELESS_ACCESSES 444 //! \details 445 //! Specifies whether sequential consistency of atomic memory operations are 446 //! supported across multiple GPUs. 447 enum DISABLE_SUPPORT_FOR_MULTI_GPU_ATOMICS_FOR_STATELESS_ACCESSES 448 { 449 DISABLE_SUPPORT_FOR_MULTI_GPU_ATOMICS_FOR_STATELESS_ACCESSES_ENABLE = 0, //!< Atomic memory operations from all GPUs to the same address is sequentially consistent. 450 DISABLE_SUPPORT_FOR_MULTI_GPU_ATOMICS_FOR_STATELESS_ACCESSES_DISABLE = 1, //!< Disable multi-GPU Atomic consistency. Atomic memory operations to the same address is sequentially consistent only if the operations are from the same GPU. 451 }; 452 453 //! \brief DISABLE_SUPPORT_FOR_MULTI_GPU_PARTIAL_WRITES_FOR_STATELESS_MESSAGES 454 //! \details 455 //! Specifies whether data-consistency on partial memory write operations 456 //! are supported across multiple GPUs. 457 enum DISABLE_SUPPORT_FOR_MULTI_GPU_PARTIAL_WRITES_FOR_STATELESS_MESSAGES 458 { 459 DISABLE_SUPPORT_FOR_MULTI_GPU_PARTIAL_WRITES_FOR_STATELESS_MESSAGES_ENABLED = 0, //!< Enable data consistency on multi-GPU partial memory writes. 460 DISABLE_SUPPORT_FOR_MULTI_GPU_PARTIAL_WRITES_FOR_STATELESS_MESSAGES_DISABLED = 1, //!< Disable data consistency on multi-GPU partial memory writes. If multiple GPUs write different bytes of the same cacheline, the data may be corrupted. 461 }; 462 463 //! \brief SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE 464 //! \details 465 //! The other fields in this DWord and the following DWord are updated only 466 //! when this bit is set. 467 enum SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE 468 { 469 SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated address. 470 SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE_ENABLE = 1, //!< Modify the address. 471 }; 472 473 //! \brief DYNAMIC_STATE_BASE_ADDRESS_MODIFY_ENABLE 474 //! \details 475 //! The other fields in this DWord and the following DWord are updated only 476 //! when this bit is set. 477 enum DYNAMIC_STATE_BASE_ADDRESS_MODIFY_ENABLE 478 { 479 DYNAMIC_STATE_BASE_ADDRESS_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated address. 480 DYNAMIC_STATE_BASE_ADDRESS_MODIFY_ENABLE_ENABLE = 1, //!< Modify the address. 481 }; 482 483 //! \brief INDIRECT_OBJECT_BASE_ADDRESS_MODIFY_ENABLE 484 //! \details 485 //! The other fields in this DWord and the following DWord are updated 486 //! only when this bit is set. 487 enum INDIRECT_OBJECT_BASE_ADDRESS_MODIFY_ENABLE 488 { 489 INDIRECT_OBJECT_BASE_ADDRESS_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated address. 490 INDIRECT_OBJECT_BASE_ADDRESS_MODIFY_ENABLE_ENABLE = 1, //!< Modify the address. 491 }; 492 493 //! \brief INSTRUCTION_BASE_ADDRESS_MODIFY_ENABLE 494 //! \details 495 //! The other fields in this DWord and the following DWord are updated 496 //! only when this bit is set. 497 enum INSTRUCTION_BASE_ADDRESS_MODIFY_ENABLE 498 { 499 INSTRUCTION_BASE_ADDRESS_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated address. 500 INSTRUCTION_BASE_ADDRESS_MODIFY_ENABLE_ENABLE = 1, //!< Modify the address. 501 }; 502 503 //! \brief GENERAL_STATE_BUFFER_SIZE_MODIFY_ENABLE 504 //! \details 505 //! The bound in this DWord is updated only when this bit is set. 506 enum GENERAL_STATE_BUFFER_SIZE_MODIFY_ENABLE 507 { 508 GENERAL_STATE_BUFFER_SIZE_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated bound. 509 GENERAL_STATE_BUFFER_SIZE_MODIFY_ENABLE_ENABLE = 1, //!< Modify the updated bound. 510 }; 511 512 //! \brief DYNAMIC_STATE_BUFFER_SIZE_MODIFY_ENABLE 513 //! \details 514 //! FormatDesc 515 enum DYNAMIC_STATE_BUFFER_SIZE_MODIFY_ENABLE 516 { 517 DYNAMIC_STATE_BUFFER_SIZE_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated bound. 518 DYNAMIC_STATE_BUFFER_SIZE_MODIFY_ENABLE_ENABLE = 1, //!< Modify the updated bound. 519 }; 520 521 //! \brief INDIRECT_OBJECT_BUFFER_SIZE_MODIFY_ENABLE 522 //! \details 523 //! FormatDesc 524 enum INDIRECT_OBJECT_BUFFER_SIZE_MODIFY_ENABLE 525 { 526 INDIRECT_OBJECT_BUFFER_SIZE_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated bound. 527 INDIRECT_OBJECT_BUFFER_SIZE_MODIFY_ENABLE_ENABLE = 1, //!< Modify the updated bound. 528 }; 529 530 //! \brief INSTRUCTION_BUFFER_SIZE_MODIFY_ENABLE 531 //! \details 532 //! FormatDesc 533 enum INSTRUCTION_BUFFER_SIZE_MODIFY_ENABLE 534 { 535 INSTRUCTION_BUFFER_SIZE_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated bound. 536 }; 537 538 //! \brief BINDLESS_SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE 539 //! \details 540 //! The other fields in this DWord and the following two DWords are 541 //! updated only when this bit is set. 542 enum BINDLESS_SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE 543 { 544 BINDLESS_SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated address 545 BINDLESS_SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE_ENABLE = 1, //!< Modify the address 546 }; 547 548 //! \brief BINDLESS_SAMPLER_STATE_BASE_ADDRESS_MODIFY_ENABLE 549 //! \details 550 //! The other fields in this DWord and the following two DWords are 551 //! updated only when this bit is set. 552 enum BINDLESS_SAMPLER_STATE_BASE_ADDRESS_MODIFY_ENABLE 553 { 554 BINDLESS_SAMPLER_STATE_BASE_ADDRESS_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated address 555 BINDLESS_SAMPLER_STATE_BASE_ADDRESS_MODIFY_ENABLE_ENABLE = 1, //!< Modify the address 556 }; 557 558 //! \name Initializations 559 560 //! \brief Explicit member initialization function STATE_BASE_ADDRESS_CMDCmd::STATE_BASE_ADDRESS_CMD561 STATE_BASE_ADDRESS_CMD() 562 { 563 DW0.Value = 0x61010014; 564 //DW0.DwordLength = GetOpLength(dwSize); 565 //DW0.Command3DSubOpcode = _3D_COMMAND_SUB_OPCODE_STATEBASEADDRESS; 566 //DW0.Command3DOpcode = _3D_COMMAND_OPCODE_GFXPIPENONPIPELINED; 567 //DW0.CommandSubtype = COMMAND_SUBTYPE_GFXPIPECOMMON; 568 //DW0.CommandType = COMMAND_TYPE_GFXPIPE; 569 570 DW1_2.Value[0] = DW1_2.Value[1] = 0x00000000; 571 //DW1_2.GeneralStateBaseAddressModifyEnable = GENERAL_STATE_BASE_ADDRESS_MODIFY_ENABLE_DISABLE; 572 573 DW3.Value = 0x00000000; 574 //DW3.CoherencySettingModifyEnable = COHERENCY_SETTING_MODIFY_ENABLE_DISABLEWRITETOTHISDW; 575 //DW3.EnableMemoryCompressionForAllStatelessAccesses = ENABLE_MEMORY_COMPRESSION_FOR_ALL_STATELESS_ACCESSES_DISABLED; 576 //DW3.DisableSupportForMultiGpuAtomicsForStatelessAccesses = DISABLE_SUPPORT_FOR_MULTI_GPU_ATOMICS_FOR_STATELESS_ACCESSES_ENABLE; 577 578 //To improve performance disable support for MultipleGpu sync features 579 //Current kernels don't support cross tiles writes 580 DW3.DisableSupportForMultiGpuAtomicsForStatelessAccesses = DISABLE_SUPPORT_FOR_MULTI_GPU_ATOMICS_FOR_STATELESS_ACCESSES_DISABLE; 581 DW3.DisableSupportForMultiGpuPartialWritesForStatelessMessages = DISABLE_SUPPORT_FOR_MULTI_GPU_PARTIAL_WRITES_FOR_STATELESS_MESSAGES_DISABLED; 582 583 DW4_5.Value[0] = DW4_5.Value[1] = 0x00000000; 584 //DW4_5.SurfaceStateBaseAddressModifyEnable = SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE_DISABLE; 585 586 DW6_7.Value[0] = DW6_7.Value[1] = 0x00000000; 587 //DW6_7.DynamicStateBaseAddressModifyEnable = DYNAMIC_STATE_BASE_ADDRESS_MODIFY_ENABLE_DISABLE; 588 589 DW8_9.Value[0] = DW8_9.Value[1] = 0x00000000; 590 //DW8_9.IndirectObjectBaseAddressModifyEnable = INDIRECT_OBJECT_BASE_ADDRESS_MODIFY_ENABLE_DISABLE; 591 592 DW10_11.Value[0] = DW10_11.Value[1] = 0x00000000; 593 //DW10_11.InstructionBaseAddressModifyEnable = INSTRUCTION_BASE_ADDRESS_MODIFY_ENABLE_DISABLE; 594 595 DW12.Value = 0x00000000; 596 //DW12.GeneralStateBufferSizeModifyEnable = GENERAL_STATE_BUFFER_SIZE_MODIFY_ENABLE_DISABLE; 597 598 DW13.Value = 0x00000000; 599 //DW13.DynamicStateBufferSizeModifyEnable = DYNAMIC_STATE_BUFFER_SIZE_MODIFY_ENABLE_DISABLE; 600 601 DW14.Value = 0x00000000; 602 //DW14.IndirectObjectBufferSizeModifyEnable = INDIRECT_OBJECT_BUFFER_SIZE_MODIFY_ENABLE_DISABLE; 603 604 DW15.Value = 0x00000000; 605 //DW15.InstructionBufferSizeModifyEnable = INSTRUCTION_BUFFER_SIZE_MODIFY_ENABLE_DISABLE; 606 607 DW16_17.Value[0] = DW16_17.Value[1] = 0x00000000; 608 //DW16_17.BindlessSurfaceStateBaseAddressModifyEnable = BINDLESS_SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE_DISABLE; 609 610 DW18.Value = 0x00000000; 611 612 DW19_20.Value[0] = DW19_20.Value[1] = 0x00000000; 613 //DW19_20.BindlessSamplerStateBaseAddressModifyEnable = BINDLESS_SAMPLER_STATE_BASE_ADDRESS_MODIFY_ENABLE_DISABLE; 614 615 DW21.Value = 0x00000000; 616 } 617 618 static const size_t dwSize = 22; 619 static const size_t byteSize = 88; 620 }; 621 622 //! 623 //! \brief _3DSTATE_CHROMA_KEY 624 //! \details 625 //! The 3DSTATE_CHROMA_KEY instruction is used to program texture 626 //! color/chroma-key key values. A table containing four set of values is 627 //! supported. The ChromaKey Index sampler state variable is used to select 628 //! which table entry is associated with the map. Texture chromakey 629 //! functions are enabled and controlled via use of the ChromaKey Enable 630 //! texture sampler state variable.Texture Color Key (keying on a paletted 631 //! texture index) is not supported. 632 //! 633 struct _3DSTATE_CHROMA_KEY_CMD 634 { 635 union 636 { 637 struct 638 { 639 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 7); //!< DWORD_LENGTH 640 uint32_t Reserved8 : __CODEGEN_BITFIELD(8, 15); //!< Reserved 641 uint32_t _3DCommandSubOpcode : __CODEGEN_BITFIELD(16, 23); //!< _3D_COMMAND_SUB_OPCODE 642 uint32_t _3DCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< _3D_COMMAND_OPCODE 643 uint32_t CommandSubtype : __CODEGEN_BITFIELD(27, 28); //!< COMMAND_SUBTYPE 644 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 645 }; 646 uint32_t Value; 647 } DW0; 648 union 649 { 650 struct 651 { 652 uint32_t Reserved32 : __CODEGEN_BITFIELD(0, 29); //!< Reserved 653 uint32_t ChromakeyTableIndex : __CODEGEN_BITFIELD(30, 31); //!< ChromaKey Table Index 654 }; 655 uint32_t Value; 656 } DW1; 657 union 658 { 659 struct 660 { 661 uint32_t ChromakeyLowValue; //!< ChromaKey Low Value 662 }; 663 uint32_t Value; 664 } DW2; 665 union 666 { 667 struct 668 { 669 uint32_t ChromakeyHighValue; //!< ChromaKey High Value 670 }; 671 uint32_t Value; 672 } DW3; 673 674 //! \name Local enumerations 675 676 enum _3D_COMMAND_SUB_OPCODE 677 { 678 _3D_COMMAND_SUB_OPCODE_3DSTATECHROMAKEY = 4, //!< No additional details 679 }; 680 681 enum _3D_COMMAND_OPCODE 682 { 683 _3D_COMMAND_OPCODE_3DSTATENONPIPELINED = 1, //!< No additional details 684 }; 685 686 enum COMMAND_SUBTYPE 687 { 688 COMMAND_SUBTYPE_GFXPIPE3D = 3, //!< No additional details 689 }; 690 691 enum COMMAND_TYPE 692 { 693 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 694 }; 695 696 //! \name Initializations 697 698 //! \brief Explicit member initialization function _3DSTATE_CHROMA_KEY_CMDCmd::_3DSTATE_CHROMA_KEY_CMD699 _3DSTATE_CHROMA_KEY_CMD() 700 { 701 DW0.Value = 0x79040002; 702 //DW0.DwordLength = GetOpLength(dwSize); 703 //DW0._3DCommandSubOpcode = _3D_COMMAND_SUB_OPCODE_3DSTATECHROMAKEY; 704 //DW0._3DCommandOpcode = _3D_COMMAND_OPCODE_3DSTATENONPIPELINED; 705 //DW0.CommandSubtype = COMMAND_SUBTYPE_GFXPIPE3D; 706 //DW0.CommandType = COMMAND_TYPE_GFXPIPE; 707 708 DW1.Value = 0x00000000; 709 710 DW2.Value = 0x00000000; 711 712 DW3.Value = 0x00000000; 713 } 714 715 static const size_t dwSize = 4; 716 static const size_t byteSize = 16; 717 }; 718 719 //! 720 //! \brief PALETTE_ENTRY 721 //! \details 722 //! 723 //! 724 struct PALETTE_ENTRY_CMD 725 { 726 union 727 { 728 struct 729 { 730 uint32_t Blue : __CODEGEN_BITFIELD(0, 7); //!< Blue 731 uint32_t Green : __CODEGEN_BITFIELD(8, 15); //!< Green 732 uint32_t Red : __CODEGEN_BITFIELD(16, 23); //!< Red 733 uint32_t Alpha : __CODEGEN_BITFIELD(24, 31); //!< Alpha 734 }; 735 uint32_t Value; 736 } DW0; 737 738 //! \name Local enumerations 739 740 //! \name Initializations 741 742 //! \brief Explicit member initialization function PALETTE_ENTRY_CMDCmd::PALETTE_ENTRY_CMD743 PALETTE_ENTRY_CMD() 744 { 745 DW0.Value = 0x00000000; 746 } 747 748 static const size_t dwSize = 1; 749 static const size_t byteSize = 4; 750 }; 751 752 //! 753 //! \brief STATE_SIP 754 //! \details 755 //! The STATE_SIP command specifies the starting instruction location of the 756 //! System Routine that is shared by all threads in execution. 757 //! 758 struct STATE_SIP_CMD 759 { 760 union 761 { 762 struct 763 { 764 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 7); //!< DWORD_LENGTH 765 uint32_t Reserved8 : __CODEGEN_BITFIELD(8, 15); //!< Reserved 766 uint32_t _3DCommandSubOpcode : __CODEGEN_BITFIELD(16, 23); //!< _3D_COMMAND_SUB_OPCODE 767 uint32_t _3DCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< _3D_COMMAND_OPCODE 768 uint32_t CommandSubtype : __CODEGEN_BITFIELD(27, 28); //!< COMMAND_SUBTYPE 769 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 770 }; 771 uint32_t Value; 772 } DW0; 773 union 774 { 775 struct 776 { 777 uint64_t Reserved32 : __CODEGEN_BITFIELD(0, 3); //!< Reserved 778 uint64_t SystemInstructionPointer : __CODEGEN_BITFIELD(4, 63); //!< System Instruction Pointer 779 }; 780 uint32_t Value[2]; 781 } DW1_2; 782 783 //! \name Local enumerations 784 785 enum _3D_COMMAND_SUB_OPCODE 786 { 787 _3D_COMMAND_SUB_OPCODE_STATESIP = 2, //!< No additional details 788 }; 789 790 enum _3D_COMMAND_OPCODE 791 { 792 _3D_COMMAND_OPCODE_GFXPIPENONPIPELINED = 1, //!< No additional details 793 }; 794 795 enum COMMAND_SUBTYPE 796 { 797 COMMAND_SUBTYPE_GFXPIPECOMMON = 0, //!< No additional details 798 }; 799 800 enum COMMAND_TYPE 801 { 802 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 803 }; 804 805 //! \name Initializations 806 807 //! \brief Explicit member initialization function STATE_SIP_CMDCmd::STATE_SIP_CMD808 STATE_SIP_CMD() 809 { 810 DW0.Value = 0x61020001; 811 //DW0.DwordLength = GetOpLength(dwSize); 812 //DW0._3DCommandSubOpcode = _3D_COMMAND_SUB_OPCODE_STATESIP; 813 //DW0._3DCommandOpcode = _3D_COMMAND_OPCODE_GFXPIPENONPIPELINED; 814 //DW0.CommandSubtype = COMMAND_SUBTYPE_GFXPIPECOMMON; 815 //DW0.CommandType = COMMAND_TYPE_GFXPIPE; 816 817 DW1_2.Value[0] = DW1_2.Value[1] = 0x00000000; 818 } 819 820 static const size_t dwSize = 3; 821 static const size_t byteSize = 12; 822 }; 823 824 //! 825 //! \brief GPGPU_CSR_BASE_ADDRESS 826 //! \details 827 //! The GPGPU_CSR_BASE_ADDRESS command sets the base pointers for EU and L3 828 //! to Context Save and Restore EU State and SLM for GPGPU mid-thread 829 //! preemption. 830 //! 831 //! Execution of this command causes a full pipeline flush, thus its use 832 //! should be minimized for higher performance. State and instruction caches 833 //! are flushed on completion of the flush. 834 //! 835 //! SW must always program PIPE_CONTROL with "CS Stall" and "Render Target 836 //! Cache Flush Enable" set prior to programming GPGPU_CSR_BASE_ADDRESS 837 //! command for GPGPU workloads i.e when pipeline select is GPGPU via 838 //! PIPELINE_SELECT command. This is required to achieve better GPGPU 839 //! preemption latencies for certain programming sequences. If programming 840 //! PIPE_CONTROL has performance implications then preemption latencies can 841 //! be trade off against performance by not implementing this programming 842 //! note. 843 //! 844 struct GPGPU_CSR_BASE_ADDRESS_CMD 845 { 846 union 847 { 848 struct 849 { 850 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 7); //!< DWORD_LENGTH 851 uint32_t Reserved8 : __CODEGEN_BITFIELD(8, 15); //!< Reserved 852 uint32_t _3DCommandSubOpcode : __CODEGEN_BITFIELD(16, 23); //!< _3D_COMMAND_SUB_OPCODE 853 uint32_t _3DCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< _3D_COMMAND_OPCODE 854 uint32_t CommandSubtype : __CODEGEN_BITFIELD(27, 28); //!< COMMAND_SUBTYPE 855 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 856 }; 857 uint32_t Value; 858 } DW0; 859 union 860 { 861 struct 862 { 863 uint64_t Reserved32 : __CODEGEN_BITFIELD(0, 11); //!< Reserved 864 uint64_t GpgpuCsrBaseAddress : __CODEGEN_BITFIELD(12, 63); //!< GPGPU CSR Base Address 865 }; 866 uint32_t Value[2]; 867 } DW1_2; 868 869 //! \name Local enumerations 870 871 enum _3D_COMMAND_SUB_OPCODE 872 { 873 _3D_COMMAND_SUB_OPCODE_GPGPUCSRBASEADDRESS = 4, //!< No additional details 874 }; 875 876 enum _3D_COMMAND_OPCODE 877 { 878 _3D_COMMAND_OPCODE_GFXPIPENONPIPELINED = 1, //!< No additional details 879 }; 880 881 enum COMMAND_SUBTYPE 882 { 883 COMMAND_SUBTYPE_GFXPIPECOMMON = 0, //!< No additional details 884 }; 885 886 enum COMMAND_TYPE 887 { 888 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 889 }; 890 891 //! \name Initializations 892 893 //! \brief Explicit member initialization function GPGPU_CSR_BASE_ADDRESS_CMDCmd::GPGPU_CSR_BASE_ADDRESS_CMD894 GPGPU_CSR_BASE_ADDRESS_CMD() 895 { 896 DW0.Value = 0x61040001; 897 //DW0.DwordLength = GetOpLength(dwSize); 898 //DW0._3DCommandSubOpcode = _3D_COMMAND_SUB_OPCODE_GPGPUCSRBASEADDRESS; 899 //DW0._3DCommandOpcode = _3D_COMMAND_OPCODE_GFXPIPENONPIPELINED; 900 //DW0.CommandSubtype = COMMAND_SUBTYPE_GFXPIPECOMMON; 901 //DW0.CommandType = COMMAND_TYPE_GFXPIPE; 902 903 DW1_2.Value[0] = DW1_2.Value[1] = 0x00000000; 904 } 905 static const size_t dwSize = 3; 906 static const size_t byteSize = 12; 907 }; 908 909 //! 910 //! \brief _3DSTATE_BINDING_TABLE_POOL_ALLOC 911 //! \details 912 //! This command is to program the base address and size of the binding 913 //! table pool. The address to fetch the binding table is based on the 914 //! Binding Table Pool Base Address and the binding table pointer if the 915 //! Binding Table Pool is enabled. Otherwise the binding table pointer is an 916 //! offset from the Surface Base Address. 917 //! 918 struct _3DSTATE_BINDING_TABLE_POOL_ALLOC_CMD 919 { 920 union 921 { 922 struct 923 { 924 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 7); //!< DWORD_LENGTH 925 uint32_t Reserved8 : __CODEGEN_BITFIELD(8, 15); //!< Reserved 926 uint32_t _3DCommandSubOpcode : __CODEGEN_BITFIELD(16, 23); //!< _3D_COMMAND_SUB_OPCODE 927 uint32_t _3DCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< _3D_COMMAND_OPCODE 928 uint32_t CommandSubtype : __CODEGEN_BITFIELD(27, 28); //!< COMMAND_SUBTYPE 929 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 930 }; 931 uint32_t Value; 932 } DW0; 933 union 934 { 935 struct 936 { 937 uint64_t SurfaceObjectControlState : __CODEGEN_BITFIELD(0, 6); //!< Surface Object Control State 938 uint64_t Reserved39 : __CODEGEN_BITFIELD(7, 11); //!< Reserved 939 uint64_t BindingTablePoolBaseAddress : __CODEGEN_BITFIELD(12, 63); //!< Binding Table Pool Base Address 940 }; 941 uint32_t Value[2]; 942 } DW1_2; 943 union 944 { 945 struct 946 { 947 uint32_t Reserved96 : __CODEGEN_BITFIELD(0, 11); //!< Reserved 948 uint32_t BindingTablePoolBufferSize : __CODEGEN_BITFIELD(12, 31); //!< BINDING_TABLE_POOL_BUFFER_SIZE 949 }; 950 uint32_t Value; 951 } DW3; 952 953 //! \name Local enumerations 954 955 enum _3D_COMMAND_SUB_OPCODE 956 { 957 _3D_COMMAND_SUB_OPCODE_3DSTATEBINDINGTABLEPOOLALLOC = 25, //!< No additional details 958 }; 959 960 enum _3D_COMMAND_OPCODE 961 { 962 _3D_COMMAND_OPCODE_3DSTATENONPIPELINED = 1, //!< No additional details 963 }; 964 965 enum COMMAND_SUBTYPE 966 { 967 COMMAND_SUBTYPE_GFXPIPE3D = 3, //!< No additional details 968 }; 969 970 enum COMMAND_TYPE 971 { 972 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 973 }; 974 975 //! \brief BINDING_TABLE_POOL_BUFFER_SIZE 976 //! \details 977 //! This field specifies the size of the buffer in 4K pages. Any access 978 //! which straddle or go past the end of the buffer will return 0. 979 enum BINDING_TABLE_POOL_BUFFER_SIZE 980 { 981 BINDING_TABLE_POOL_BUFFER_SIZE_NOVALIDDATA = 0, //!< There is no valid data in the buffer 982 }; 983 984 //! \name Initializations 985 986 //! \brief Explicit member initialization function _3DSTATE_BINDING_TABLE_POOL_ALLOC_CMDCmd::_3DSTATE_BINDING_TABLE_POOL_ALLOC_CMD987 _3DSTATE_BINDING_TABLE_POOL_ALLOC_CMD() 988 { 989 DW0.Value = 0x79190002; 990 //DW0.DwordLength = GetOpLength(dwSize); 991 //DW0._3DCommandSubOpcode = _3D_COMMAND_SUB_OPCODE_3DSTATEBINDINGTABLEPOOLALLOC; 992 //DW0._3DCommandOpcode = _3D_COMMAND_OPCODE_3DSTATENONPIPELINED; 993 //DW0.CommandSubtype = COMMAND_SUBTYPE_GFXPIPE3D; 994 //DW0.CommandType = COMMAND_TYPE_GFXPIPE; 995 996 DW1_2.Value[0] = DW1_2.Value[1] = 0x00000000; 997 998 DW3.Value = 0x00000000; 999 //DW3.BindingTablePoolBufferSize = BINDING_TABLE_POOL_BUFFER_SIZE_NOVALIDDATA; 1000 } 1001 1002 static const size_t dwSize = 4; 1003 static const size_t byteSize = 16; 1004 }; 1005 1006 //! 1007 //! \brief CFE_STATE 1008 //! \details 1009 //! 1010 //! 1011 struct CFE_STATE_CMD 1012 { 1013 union 1014 { 1015 //!< DWORD 0 1016 struct 1017 { 1018 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 7); //!< DWord Length 1019 uint32_t Reserved8 : __CODEGEN_BITFIELD(8, 15); //!< Reserved 1020 uint32_t CFESubOpcodeVariant : __CODEGEN_BITFIELD(16, 17); //!< CFE SubOpcode Variant 1021 uint32_t CFESubOpcode : __CODEGEN_BITFIELD(18, 23); //!< CFE SubOpcode 1022 uint32_t ComputeCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< Compute Command Opcode 1023 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< Pipeline 1024 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< Command Type 1025 }; 1026 uint32_t Value = 0; 1027 } DW0; 1028 union 1029 { 1030 //!< DWORD 1_2 1031 struct 1032 { 1033 uint64_t Reserved32 : __CODEGEN_BITFIELD(0, 9); //!< Reserved 1034 uint64_t ScratchSpaceBuffer : __CODEGEN_BITFIELD(10, 31); //!< Scratch Space Base Pointer 1035 uint64_t Reserved64 : __CODEGEN_BITFIELD(32, 63); //!< Reserved 1036 }; 1037 uint64_t Value = 0; 1038 } DW1_2; 1039 union 1040 { 1041 //!< DWORD 3 1042 struct 1043 { 1044 uint32_t Reserved96 : __CODEGEN_BITFIELD(0, 2); //!< Reserved 1045 uint32_t NumberOfWalkers : __CODEGEN_BITFIELD(3, 5); //!< Number Of Walkers 1046 uint32_t FusedEuDispatch : __CODEGEN_BITFIELD(6, 6); //!< Fused EU Dispatch 1047 uint32_t Reserved103 : __CODEGEN_BITFIELD(7, 12); //!< Reserved 1048 uint32_t SingleSliceDispatchCcsMode : __CODEGEN_BITFIELD(13, 13); //!< Single Slice Dispatch CCS Mode 1049 uint32_t OverDispatchControl : __CODEGEN_BITFIELD(14, 15); //!< Over Dispatch Control 1050 uint32_t MaximumNumberOfThreads : __CODEGEN_BITFIELD(16, 31); //!< Maximum Number of Threads 1051 }; 1052 uint32_t Value = 0; 1053 } DW3; 1054 union 1055 { 1056 //!< DWORD 4 1057 struct 1058 { 1059 uint32_t Reserved128 : __CODEGEN_BITFIELD(0, 23); //!< Reserved 1060 uint32_t StopAndDrainTimer : __CODEGEN_BITFIELD(24, 30); //!< Stop And Drain Timer 1061 uint32_t StopAndDrainTimerEnable : __CODEGEN_BITFIELD(31, 31); //!< Stop And Drain Timer Enable 1062 }; 1063 uint32_t Value = 0; 1064 } DW4; 1065 union 1066 { 1067 //!< DWORD 5 1068 struct 1069 { 1070 uint32_t DebugCounterControl : __CODEGEN_BITFIELD(0, 1); //!< Debug Counter Control 1071 uint32_t Reserved162 : __CODEGEN_BITFIELD(2, 7); //!< Reserved 1072 uint32_t DebugObjectID : __CODEGEN_BITFIELD(8, 31); //!< Debug Object ID 1073 }; 1074 uint32_t Value = 0; 1075 } DW5; 1076 1077 //! \name Local enumerations 1078 enum PIPELINE 1079 { 1080 PIPELINE_COMPUTE = 2, //!< No additional details 1081 }; 1082 1083 enum COMMAND_TYPE 1084 { 1085 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 1086 }; 1087 1088 enum COMPUTE_COMMAND_OPCODE 1089 { 1090 COMPUTE_COMMAND_OPCODE_CFE_COMMAND = 2, //!< No additional details 1091 }; 1092 1093 enum OVER_DISPATCH_CONTROL 1094 { 1095 VER_DISPATCH_CONTROL_NONE = 0, //!< 0% overdispatch 1096 VER_DISPATCH_CONTROL_LOW = 1, //!< 25% overdispatch 1097 VER_DISPATCH_CONTROL_NORMAL = 2, //!< 50% overdispatch 1098 VER_DISPATCH_CONTROL_HIGH = 3, //!< 75% overdispatch 1099 }; 1100 1101 enum SINGLE_SLICE_DISPATCH_CCS_MODE 1102 { 1103 SINGLE_SLICE_DISPATCH_CCS_MODE_DISABLE = 0, //!< No additional details 1104 SINGLE_SLICE_DISPATCH_CCS_MODE_ENABLE = 1, //!< No additional details 1105 }; 1106 1107 enum FUSED_EU_DISPATCH 1108 { 1109 FUSED_EU_DISPATCH_LEGACY_MODE = 1, //!< Legacy Mode, threads are not fused 1110 FUSED_EU_DISPATCH_FUSED_EU_MODE = 0, //!< Fused EU Mode 1111 }; 1112 1113 //! \name Initializations 1114 1115 //! \brief Explicit member initialization function CFE_STATE_CMDCmd::CFE_STATE_CMD1116 CFE_STATE_CMD() 1117 { 1118 DW0.DwordLength = __CODEGEN_OP_LENGTH(dwSize); 1119 DW0.CFESubOpcodeVariant = 0; 1120 DW0.CFESubOpcode = 0; 1121 DW0.ComputeCommandOpcode = COMPUTE_COMMAND_OPCODE_CFE_COMMAND; 1122 DW0.Pipeline = PIPELINE_COMPUTE; 1123 DW0.CommandType = COMMAND_TYPE_GFXPIPE; 1124 1125 DW3.OverDispatchControl = VER_DISPATCH_CONTROL_NORMAL; 1126 } 1127 1128 static const size_t dwSize = 6; 1129 static const size_t byteSize = 24; 1130 }; 1131 1132 //! 1133 //! \brief COMPUTE_WALKER for GEN12 HP 1134 //! \details COMPUTE_WALKER spawns threadgroups in 1, 2, or 3 dimensions (X, Y, Z). 1135 //! Each threadgroup is described by Interface Descriptor in this command. 1136 //! Each dispatched thread has a standard payload delivered in R0 and R1, 1137 //! including the Indirect Address to fetch the thread's parameters. 1138 //! After the Walker completes dispatching its threads and those threads have 1139 //! completed running, a PostSync operation can write a completion code or a 1140 //! timestamp. 1141 //! 1142 struct COMPUTE_WALKER_CMD 1143 { 1144 union 1145 { 1146 //!< DWORD 0 1147 struct 1148 { 1149 uint32_t DWordLength : __CODEGEN_BITFIELD(0, 7); //!< DWord Length 1150 uint32_t PredicateEnable : __CODEGEN_BITFIELD(8, 8); //!< Predicate Enable 1151 uint32_t WorkloadPartitionEnable : __CODEGEN_BITFIELD(9, 9); //!< Workload Partition Enable 1152 uint32_t IndirectParameterEnable : __CODEGEN_BITFIELD(10, 10); //!< Indirect Parameter Enable 1153 uint32_t UAVWaitToProduce : __CODEGEN_BITFIELD(11, 11); //!< UAV Wait to Produce 1154 uint32_t UAVProducer : __CODEGEN_BITFIELD(12, 12); //!< UAV Producer 1155 uint32_t UAVConsumer : __CODEGEN_BITFIELD(13, 13); //!< UAV Consumer 1156 uint32_t SystolicModeEnable : __CODEGEN_BITFIELD(14, 14); //!< Systolic Mode Enable 1157 uint32_t Reserved : __CODEGEN_BITFIELD(15, 15); //!< Reserved 1158 uint32_t CFESubOpcodeVariant : __CODEGEN_BITFIELD(16, 17); //!< CFE SubOpcode Variant 1159 uint32_t CFESubOpcode : __CODEGEN_BITFIELD(18, 23); //!< CFE SubOpcode 1160 uint32_t ComputeCommandOpcode : __CODEGEN_BITFIELD(24, 26); //!< Compute Command Opcode 1161 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28); //!< Pipeline 1162 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< Command Type 1163 }; 1164 uint32_t Value = 0; 1165 } DW0; 1166 union 1167 { 1168 //!< DWORD 1 1169 struct 1170 { 1171 uint32_t Reserved32 : __CODEGEN_BITFIELD(0, 7); //!< Reserved 1172 uint32_t DebugObjectID : __CODEGEN_BITFIELD(8, 31); //!< Debug Object ID 1173 }; 1174 uint32_t Value = 0; 1175 } DW1; 1176 union 1177 { 1178 //!< DWORD 2 1179 struct 1180 { 1181 uint32_t IndirectDataLength : __CODEGEN_BITFIELD(0, 16); //!< Indirect Data Length 1182 uint32_t L3PrefetchDisable : __CODEGEN_BITFIELD(17, 17); //!< L3 prefetch disable 1183 uint32_t PartitionDispatchParameter : __CODEGEN_BITFIELD(18, 29); //!< Partition Dispatch Parameter 1184 uint32_t PartitionType : __CODEGEN_BITFIELD(30, 31); //!< PartitionType 1185 }; 1186 uint32_t Value = 0; 1187 } DW2; 1188 union 1189 { 1190 //!< DWORD 3 1191 struct 1192 { 1193 uint32_t Reserved96 : __CODEGEN_BITFIELD(0, 5); //!< Reserved 1194 uint32_t IndirectDataStartAddress : __CODEGEN_BITFIELD(6, 31); //!< Indirect Data Start Address 1195 }; 1196 uint32_t Value = 0; 1197 } DW3; 1198 union 1199 { 1200 //!< DWORD 4 1201 struct 1202 { 1203 uint32_t Reserved128 : __CODEGEN_BITFIELD(0, 16); //!< Reserved 1204 uint32_t MessageSIMD : __CODEGEN_BITFIELD(17, 18); //!< Message SIMD 1205 uint32_t TileLayout : __CODEGEN_BITFIELD(19, 21); //!< Tile Layout 1206 uint32_t WalkOrder : __CODEGEN_BITFIELD(22, 24); //!< Walk Order 1207 uint32_t EmitInlineParameter : __CODEGEN_BITFIELD(25, 25); //!< Emit Inline Parameter 1208 uint32_t EmitLocal : __CODEGEN_BITFIELD(26, 28); //!< Emit Local 1209 uint32_t GenerateLocalID : __CODEGEN_BITFIELD(29, 29); //!< Generate Local ID 1210 uint32_t SIMDSize : __CODEGEN_BITFIELD(30, 31); //!< SIMD Size 1211 }; 1212 uint32_t Value = 0; 1213 } DW4; 1214 union 1215 { 1216 //!< DWORD 5 1217 struct 1218 { 1219 uint32_t ExecutionMask : __CODEGEN_BITFIELD(0, 31); //!< Execution Mask 1220 }; 1221 uint32_t Value = 0; 1222 } DW5; 1223 union 1224 { 1225 //!< DWORD 6 1226 struct 1227 { 1228 uint32_t LocalXMaximum : __CODEGEN_BITFIELD(0, 9); //!< Local X Maximum 1229 uint32_t LocalYMaximum : __CODEGEN_BITFIELD(10, 19); //!< Local Y Maximum 1230 uint32_t LocalZMaximum : __CODEGEN_BITFIELD(20, 29); //!< Local Z Maximum 1231 uint32_t Reserved222 : __CODEGEN_BITFIELD(30, 31); //!< Reserved 1232 }; 1233 uint32_t Value = 0; 1234 } DW6; 1235 union 1236 { 1237 //!< DWORD 7 1238 struct 1239 { 1240 uint32_t ThreadGroupIDXDimension : __CODEGEN_BITFIELD(0, 31); //!< Thread Group ID X Dimension 1241 }; 1242 uint32_t Value = 0; 1243 } DW7; 1244 union 1245 { 1246 //!< DWORD 8 1247 struct 1248 { 1249 uint32_t ThreadGroupIDYDimension : __CODEGEN_BITFIELD(0, 31); //!< Thread Group ID Y Dimension 1250 }; 1251 uint32_t Value = 0; 1252 } DW8; 1253 union 1254 { 1255 //!< DWORD 9 1256 struct 1257 { 1258 uint32_t ThreadGroupIDZDimension : __CODEGEN_BITFIELD(0, 31); //!< Thread Group ID Z Dimension 1259 }; 1260 uint32_t Value = 0; 1261 } DW9; 1262 union 1263 { 1264 //!< DWORD 10 1265 struct 1266 { 1267 uint32_t ThreadGroupIDStartingX : __CODEGEN_BITFIELD(0, 31); //!< Thread Group ID Starting X 1268 }; 1269 uint32_t Value = 0; 1270 } DW10; 1271 union 1272 { 1273 //!< DWORD 11 1274 struct 1275 { 1276 uint32_t ThreadGroupIDStartingY : __CODEGEN_BITFIELD(0, 31); //!< Thread Group ID Starting Y 1277 }; 1278 uint32_t Value = 0; 1279 } DW11; 1280 union 1281 { 1282 //!< DWORD 12 1283 struct 1284 { 1285 uint32_t ThreadGroupIDStartingZ : __CODEGEN_BITFIELD(0, 31); //!< Thread Group ID Starting Z 1286 }; 1287 uint32_t Value = 0; 1288 } DW12; 1289 union 1290 { 1291 //!< DWORD 13_14 1292 struct 1293 { 1294 uint64_t PartitionID : __CODEGEN_BITFIELD(0, 31); //!< Partition ID 1295 uint64_t PartitionSize : __CODEGEN_BITFIELD(32, 63); //!< Partition Size 1296 }; 1297 uint64_t Value = 0; 1298 } DW13_14; 1299 1300 union 1301 { 1302 struct 1303 { 1304 uint32_t PreemptX; 1305 }; 1306 uint32_t Value = 0; 1307 } DW15; 1308 1309 union 1310 { 1311 struct 1312 { 1313 uint32_t PreemptY; 1314 }; 1315 uint32_t Value = 0; 1316 } DW16; 1317 1318 union 1319 { 1320 struct 1321 { 1322 uint32_t PreemptZ; 1323 }; 1324 uint32_t Value = 0; 1325 } DW17; 1326 1327 //! 1328 //! \brief INTERFACE_DESCRIPTOR_DATA for Gen12 HP 1329 //! \details The Interface Descriptor describes the thread state common for all threads 1330 //! in the dispatch, including the Kernel base address, the binding tables, 1331 //! threadgroup size, and SLM size. 1332 //! 1333 struct INTERFACE_DESCRIPTOR_DATA_G12HP_CMD 1334 { 1335 union 1336 { 1337 //!< DWORD 0_1 1338 struct 1339 { 1340 uint64_t Reserved0 : __CODEGEN_BITFIELD(0, 5); //!< Reserved 1341 uint64_t KernelStartPointer : __CODEGEN_BITFIELD(6, 31); //!< Kernel Start Pointer 1342 uint64_t Reserved32 : __CODEGEN_BITFIELD(32, 63); //!< Reserved 1343 }; 1344 uint32_t Value[2] = {0}; 1345 } DW0_1; 1346 union 1347 { 1348 //!< DWORD 2 1349 struct 1350 { 1351 uint32_t Reserved64 : __CODEGEN_BITFIELD(0, 6); //!< Reserved 1352 uint32_t SoftwareExceptionEnable : __CODEGEN_BITFIELD(7, 7); //!< Software Exception Enable 1353 uint32_t Reserved72 : __CODEGEN_BITFIELD(8, 10); //!< Reserved 1354 uint32_t MaskStackExceptionEnable : __CODEGEN_BITFIELD(11, 11); //!< Mask Stack Exception Enable 1355 uint32_t Reserved76 : __CODEGEN_BITFIELD(12, 12); //!< Reserved 1356 uint32_t IllegalOpcodeExceptionEnable : __CODEGEN_BITFIELD(13, 13); //!< Illegal Opcode Exception Enable 1357 uint32_t Reserved78 : __CODEGEN_BITFIELD(14, 15); //!< Reserved 1358 uint32_t FloatingPointMode : __CODEGEN_BITFIELD(16, 16); //!< Floating Point Mode 1359 uint32_t Reserved81 : __CODEGEN_BITFIELD(17, 17); //!< Reserved 1360 uint32_t SingleProgramFlow : __CODEGEN_BITFIELD(18, 18); //!< Single Program Flow 1361 uint32_t DenormMode : __CODEGEN_BITFIELD(19, 19); //!< Denorm Mode 1362 uint32_t ThreadPreemptionDisable : __CODEGEN_BITFIELD(20, 20); //!< Thread Preemption Disable 1363 uint32_t Reserved85 : __CODEGEN_BITFIELD(21, 31); //!< Reserved 1364 }; 1365 uint32_t Value = 0; 1366 } DW2; 1367 union 1368 { 1369 //!< DWORD 3 1370 struct 1371 { 1372 uint32_t Reserved96 : __CODEGEN_BITFIELD(0, 1); //!< Reserved 1373 uint32_t SamplerCount : __CODEGEN_BITFIELD(2, 4); //!< Sampler Count 1374 uint32_t SamplerStatePointer : __CODEGEN_BITFIELD(5, 31); //!< Sampler State Pointer 1375 }; 1376 uint32_t Value = 0; 1377 } DW3; 1378 union 1379 { 1380 //!< DWORD 4 1381 struct 1382 { 1383 uint32_t BindingTableEntryCount : __CODEGEN_BITFIELD(0, 4); //!< Binding Table Entry Count 1384 uint32_t BindingTablePointer : __CODEGEN_BITFIELD(5, 20); //!< Binding Table Pointer 1385 uint32_t Reserved149 : __CODEGEN_BITFIELD(21, 31); //!< Reserved 1386 }; 1387 uint32_t Value = 0; 1388 } DW4; 1389 union 1390 { 1391 //!< DWORD 5 1392 struct 1393 { 1394 uint32_t NumberOfThreadsInGpgpuThreadGroup : __CODEGEN_BITFIELD(0, 9); //!< Number of Threads in GPGPU Thread Group 1395 uint32_t Reserved170 : __CODEGEN_BITFIELD(10, 15); //!< Reserved 1396 uint32_t SharedLocalMemorySize : __CODEGEN_BITFIELD(16, 20); //!< Shared Local Memory Size 1397 uint32_t BarrierEnable : __CODEGEN_BITFIELD(21, 21); //!< Barrier Enable 1398 uint32_t RoundingMode : __CODEGEN_BITFIELD(22, 23); //!< Rounding Mode 1399 uint32_t Reserved184 : __CODEGEN_BITFIELD(24, 25); //!< Reserved 1400 uint32_t ThreadGroupDispatchSize : __CODEGEN_BITFIELD(26, 27); //!< Thread group dispatch size 1401 uint32_t Reserved188 : __CODEGEN_BITFIELD(28, 30); //!< Reserved 1402 uint32_t BTDMode : __CODEGEN_BITFIELD(31, 31); //!< BTD mode 1403 }; 1404 uint32_t Value = 0; 1405 } DW5; 1406 union 1407 { 1408 //!< DWORD 6_7 1409 struct 1410 { 1411 uint64_t Reserved192 : __CODEGEN_BITFIELD(0, 63); //!< Reserved 1412 }; 1413 uint64_t Value = 0; 1414 } DW6_7; 1415 1416 //! \name Initializations 1417 1418 //! \brief Explicit member initialization function INTERFACE_DESCRIPTOR_DATA_G12HP_CMDCmd::COMPUTE_WALKER_CMD::INTERFACE_DESCRIPTOR_DATA_G12HP_CMD1419 INTERFACE_DESCRIPTOR_DATA_G12HP_CMD() 1420 { 1421 } 1422 1423 static const size_t dwSize = 8; 1424 static const size_t byteSize = 32; 1425 } interface_descriptor_data; 1426 1427 //! 1428 //! \brief POSTSYNC_DATA_CMD 1429 //! \detail Post Sync command payload includes the operation, the address, a MOCS field, and an Immediate Data Value. 1430 //! 1431 struct POSTSYNC_DATA_CMD 1432 { 1433 union 1434 { 1435 //!< DWORD 0 1436 struct 1437 { 1438 uint32_t Operation : __CODEGEN_BITFIELD(0, 1); //!< Operation 1439 uint32_t HDCPipelineFlush : __CODEGEN_BITFIELD(2, 2); //!< HDC Pipeline Flush 1440 uint32_t L3Flush : __CODEGEN_BITFIELD(3, 3); //!< Reserved 1441 uint32_t MOCS : __CODEGEN_BITFIELD(4, 10); //!< MOCS 1442 uint32_t Reserved11 : __CODEGEN_BITFIELD(11, 31); //!< Reserved 1443 }; 1444 uint32_t Value = 0; 1445 } DW0; 1446 union 1447 { 1448 //!< DWORD 1_2 1449 struct 1450 { 1451 uint64_t DestinationAddress : __CODEGEN_BITFIELD(0, 63); //!< Destination Address 1452 }; 1453 uint32_t Value[2] = {0}; 1454 } DW1_2; 1455 union 1456 { 1457 //!< DWORD 3_4 1458 struct 1459 { 1460 uint64_t ImmediateData : __CODEGEN_BITFIELD(0, 63); //!< Immediate Data 1461 }; 1462 uint64_t Value = 0; 1463 } DW3_4; 1464 1465 //! \name local enumerations. 1466 enum POSTSYNC_OPERATION 1467 { 1468 POSTSYNC_OPERATION_NO_WRITE = 0, //!< The destination address and immediate data fields are ignored. 1469 POSTSYNC_OPERATION_WRITE_IMMEDIATE_DATA = 1, //!< Writes 8 bytes (64 bits) of immediate data to the destination address. 1470 POSTSYNC_OPERATION_WRITE_TIMESTAMP = 3, //!< Writes 16 bytes (128 bits) of timestamp data to the destination address. 1471 }; 1472 1473 //! \brief Explicit member initialization function POSTSYNC_DATA_CMDCmd::COMPUTE_WALKER_CMD::POSTSYNC_DATA_CMD1474 POSTSYNC_DATA_CMD() 1475 { 1476 DW3_4.Value = 0; 1477 DW1_2.Value[1] = DW1_2.Value[0] = DW0.Value = 0; 1478 } 1479 1480 static const size_t dwSize = 5; 1481 static const size_t byteSize = 20; 1482 } postsync_data; 1483 1484 struct INLINE_DATA_CMD 1485 { 1486 uint32_t Value[8] = {0}; 1487 1488 //! \brief Explicit member initialization function INLINE_DATA_CMDCmd::COMPUTE_WALKER_CMD::INLINE_DATA_CMD1489 INLINE_DATA_CMD() {} 1490 static const size_t dwSize = 8; 1491 static const size_t byteSize = 32; 1492 } inline_data; 1493 1494 //! \name Local enumerations 1495 enum PIPELINE 1496 { 1497 PIPELINE_COMPUTE = 2, //!< No additional details 1498 }; 1499 1500 enum COMMAND_TYPE 1501 { 1502 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 1503 }; 1504 1505 enum CFE_SUBOPCODE 1506 { 1507 CFE_SUBOPCODE_COMPUTE_WALKER = 2, //!< No additional details 1508 }; 1509 1510 enum COMPUTE_COMMAND_OPCODE 1511 { 1512 COMPUTE_COMMAND_OPCODE_CFE_COMMAND = 2, //!< No additional details 1513 }; 1514 1515 enum CFE_SUBOPCODE_VARIANT 1516 { 1517 CFE_SUBOPCODE_VARIANT_STANDARD = 0, //!< No additional details 1518 CFE_SUBOPCODE_VARIANT_RESUME = 1, //!< Resumption of GPGPU_WALKER command, recorded in context image to continue execution after preemption. 1519 }; 1520 1521 //! \brief SIMD_SIZE 1522 //! \details This field determines the size of the payload and the number of bits of 1523 //! the execution mask that are expected. The kernel pointed to by the 1524 //! interface descriptor should match the SIMD declared here. 1525 enum SIMD_SIZE 1526 { 1527 SIMD_SIZE_SIMD8 = 0, //!< 8 LSBs of the execution mask are used 1528 SIMD_SIZE_SIMD16 = 1, //!< 16 LSBs used in execution mask 1529 SIMD_SIZE_SIMD32 = 2, //!< 32 bits of execution mask used 1530 }; 1531 1532 enum WALKER_ORDER 1533 { 1534 WALKER_ORDER_WALK012 = 0, //!< Normal Linear walk order 1535 WALKER_ORDER_WALK021 = 1, //!< No additional details 1536 WALKER_ORDER_WALK102 = 2, //!< Normal TileY walk order 1537 WALKER_ORDER_WALK120 = 3, //!< No additional details 1538 WALKER_ORDER_WALK201 = 4, //!< No additional details 1539 WALKER_ORDER_WALK210 = 5, //!< No additional details 1540 }; 1541 1542 //! \name Initializations 1543 1544 //! \brief Explicit member initialization function COMPUTE_WALKER_CMDCmd::COMPUTE_WALKER_CMD1545 COMPUTE_WALKER_CMD() 1546 { 1547 DW0.DWordLength = __CODEGEN_OP_LENGTH(dwSize); 1548 DW0.CFESubOpcodeVariant = CFE_SUBOPCODE_VARIANT_STANDARD; 1549 DW0.CFESubOpcode = CFE_SUBOPCODE_COMPUTE_WALKER; 1550 DW0.ComputeCommandOpcode = COMPUTE_COMMAND_OPCODE_CFE_COMMAND; 1551 DW0.Pipeline = PIPELINE_COMPUTE; 1552 DW0.CommandType = COMMAND_TYPE_GFXPIPE; 1553 } 1554 1555 static const size_t dwSize = 39; 1556 static const size_t byteSize = 156; 1557 }; 1558 1559 //! 1560 //! \brief STATE_COMPUTE_MODE command, a general compute programming state shared in the 1561 //! pipeline. 1562 //! 1563 struct STATE_COMPUTE_MODE_CMD 1564 { 1565 union 1566 { 1567 struct 1568 { 1569 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 7); 1570 uint32_t Reserved8 : __CODEGEN_BITFIELD(8, 15); 1571 uint32_t CommandSubOpcode : __CODEGEN_BITFIELD(16, 23); 1572 uint32_t CommandOpcode : __CODEGEN_BITFIELD(24, 26); 1573 uint32_t CommandSubType : __CODEGEN_BITFIELD(27, 28); 1574 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); 1575 }; 1576 uint32_t Value = 0; 1577 } DW0; 1578 1579 union 1580 { 1581 struct 1582 { 1583 uint32_t DisableSupportForMultiGpuFence : __CODEGEN_BITFIELD(0, 0); 1584 uint32_t DisableSupportForMultiGpuAtomics : __CODEGEN_BITFIELD(1, 1); 1585 1586 uint32_t DisableSupportMultiGpuPartialWrites : __CODEGEN_BITFIELD(2, 2); 1587 1588 uint32_t ForceNonCoherent : __CODEGEN_BITFIELD(3, 4); 1589 uint32_t FastClearDisabledOnCompressedSurface : __CODEGEN_BITFIELD(5, 5); 1590 1591 uint32_t DisableSlmReadMergeOptimization : __CODEGEN_BITFIELD(6, 6); 1592 1593 uint32_t AsyncComputeThreadLimit : __CODEGEN_BITFIELD(7, 9); 1594 uint32_t BindingTableAlignment : __CODEGEN_BITFIELD(10, 10); 1595 uint32_t DisableAtomicOnClearData : __CODEGEN_BITFIELD(11, 11); 1596 uint32_t CoherentAccessL1CacheDisable : __CODEGEN_BITFIELD(12, 12); 1597 1598 uint32_t DisableL1InvalidateForNonL1CacheableWrites : __CODEGEN_BITFIELD(13, 13); 1599 1600 uint32_t Reserved46 : __CODEGEN_BITFIELD(14, 14); 1601 uint32_t LargeGrfMode : __CODEGEN_BITFIELD(15, 15); 1602 uint32_t MaskBits : __CODEGEN_BITFIELD(16, 31); 1603 }; 1604 uint32_t Value = 0; 1605 } DW1; 1606 STATE_COMPUTE_MODE_CMDCmd::STATE_COMPUTE_MODE_CMD1607 STATE_COMPUTE_MODE_CMD() 1608 { 1609 DW0.DwordLength = __CODEGEN_OP_LENGTH(dwSize); 1610 DW0.CommandSubOpcode = STATE_COMPUTE_MODE; 1611 DW0.CommandOpcode = GFXPIPE_NONPIPELINED; 1612 DW0.CommandSubType = GFXPIPE_COMMON; 1613 DW0.CommandType = GFXPIPE; 1614 1615 //To improve performance disable support for DisableSupportForMultiGpuAtomics 1616 //and MultipleGpuParitalWrites, current kernels don't support cross tiles writes 1617 DW1.DisableSupportForMultiGpuAtomics = 1; 1618 DW1.DisableSupportMultiGpuPartialWrites = 1; 1619 } 1620 1621 static const size_t dwSize = 2; 1622 static const size_t byteSize = 8; 1623 static const uint32_t GFXPIPE = 3; 1624 static const uint32_t GFXPIPE_COMMON = 0; 1625 static const uint32_t GFXPIPE_NONPIPELINED = 1; 1626 static const uint32_t STATE_COMPUTE_MODE = 5; 1627 }; 1628 }; 1629 1630 } // namespace xe_hpg 1631 } // namespace render 1632 } // namespace mhw 1633 class mhw_render_xe_hpm 1634 {}; 1635 #pragma pack() 1636 1637 #endif // __MHW_RENDER_HWCMD_XE_HPG_H__ 1638