1 /* 2 * mach64.h 3 * This software has been released under the terms of the GNU Public 4 * license. See http://www.gnu.org/copyleft/gpl.html for details. 5 * 6 * It's based on radeonfb, X11, GATOS sources 7 */ 8 9 #ifndef __MACH64_INCLUDED 10 #define __MACH64_INCLUDED 1 11 12 /* Note: this model of accessing to IO space is based on MMIO technology. 13 This means that this sources don't support ISA and VLB cards */ 14 #define BlockIOTag(val) (val) 15 #define IOPortTag(sparce,val) (val) 16 17 /* MDA/[M]CGA/EGA/VGA I/O ports */ 18 #define GENVS 0x0102u /* Write (and Read on uC only) */ 19 20 #define R_GENLPS 0x03b9u /* Read */ 21 22 #define GENHP 0x03bfu 23 24 #define ATTRX 0x03c0u 25 #define ATTRD 0x03c1u 26 #define GENS0 0x03c2u /* Read */ 27 #define GENMO 0x03c2u /* Write */ 28 #define GENENB 0x03c3u /* Read */ 29 #define SEQX 0x03c4u 30 #define SEQD 0x03c5u 31 #define VGA_DAC_MASK 0x03c6u 32 #define VGA_DAC_READ 0x03c7u 33 #define VGA_DAC_WRITE 0x03c8u 34 #define VGA_DAC_DATA 0x03c9u 35 #define R_GENFC 0x03cau /* Read */ 36 /* ? 0x03cbu */ 37 #define R_GENMO 0x03ccu /* Read */ 38 /* ? 0x03cdu */ 39 #define GRAX 0x03ceu 40 #define GRAD 0x03cfu 41 42 #define GENB 0x03d9u 43 44 #define GENLPS 0x03dcu /* Write */ 45 #define KCX 0x03ddu 46 #define KCD 0x03deu 47 48 #define GENENA 0x46e8u /* Write */ 49 50 /* I/O port base numbers */ 51 #define MonochromeIOBase 0x03b0u 52 #define ColourIOBase 0x03d0u 53 54 /* Other MDA/[M]CGA/EGA/VGA I/O ports */ 55 /* ?(_IOBase) ((_IOBase) + 0x00u) */ /* CRTX synonym */ 56 /* ?(_IOBase) ((_IOBase) + 0x01u) */ /* CRTD synonym */ 57 /* ?(_IOBase) ((_IOBase) + 0x02u) */ /* CRTX synonym */ 58 /* ?(_IOBase) ((_IOBase) + 0x03u) */ /* CRTD synonym */ 59 #define CRTX(_IOBase) ((_IOBase) + 0x04u) 60 #define CRTD(_IOBase) ((_IOBase) + 0x05u) 61 /* ?(_IOBase) ((_IOBase) + 0x06u) */ 62 /* ?(_IOBase) ((_IOBase) + 0x07u) */ 63 #define GENMC(_IOBase) ((_IOBase) + 0x08u) 64 /* ?(_IOBase) ((_IOBase) + 0x09u) */ /* R_GENLPS/GENB */ 65 #define GENS1(_IOBase) ((_IOBase) + 0x0au) /* Read */ 66 #define GENFC(_IOBase) ((_IOBase) + 0x0au) /* Write */ 67 #define GENLPC(_IOBase) ((_IOBase) + 0x0bu) 68 /* ?(_IOBase) ((_IOBase) + 0x0cu) */ /* /GENLPS */ 69 /* ?(_IOBase) ((_IOBase) + 0x0du) */ /* /KCX */ 70 /* ?(_IOBase) ((_IOBase) + 0x0eu) */ /* /KCD */ 71 /* ?(_IOBase) ((_IOBase) + 0x0fu) */ /* GENHP/ */ 72 73 /* 8514/A VESA approved register definitions */ 74 #define DISP_STAT 0x02e8u /* Read */ 75 #define SENSE 0x0001u /* Presumably belong here */ 76 #define VBLANK 0x0002u 77 #define HORTOG 0x0004u 78 #define H_TOTAL 0x02e8u /* Write */ 79 #define IBM_DAC_MASK 0x02eau 80 #define IBM_DAC_READ 0x02ebu 81 #define IBM_DAC_WRITE 0x02ecu 82 #define IBM_DAC_DATA 0x02edu 83 #define H_DISP 0x06e8u /* Write */ 84 #define H_SYNC_STRT 0x0ae8u /* Write */ 85 #define H_SYNC_WID 0x0ee8u /* Write */ 86 #define HSYNCPOL_POS 0x0000u 87 #define HSYNCPOL_NEG 0x0020u 88 #define H_POLARITY_POS HSYNCPOL_POS /* Sigh */ 89 #define H_POLARITY_NEG HSYNCPOL_NEG /* Sigh */ 90 #define V_TOTAL 0x12e8u /* Write */ 91 #define V_DISP 0x16e8u /* Write */ 92 #define V_SYNC_STRT 0x1ae8u /* Write */ 93 #define V_SYNC_WID 0x1ee8u /* Write */ 94 #define VSYNCPOL_POS 0x0000u 95 #define VSYNCPOL_NEG 0x0020u 96 #define V_POLARITY_POS VSYNCPOL_POS /* Sigh */ 97 #define V_POLARITY_NEG VSYNCPOL_NEG /* Sigh */ 98 #define DISP_CNTL 0x22e8u /* Write */ 99 #define ODDBNKENAB 0x0001u 100 #define MEMCFG_2 0x0000u 101 #define MEMCFG_4 0x0002u 102 #define MEMCFG_6 0x0004u 103 #define MEMCFG_8 0x0006u 104 #define DBLSCAN 0x0008u 105 #define INTERLACE 0x0010u 106 #define DISPEN_NC 0x0000u 107 #define DISPEN_ENAB 0x0020u 108 #define DISPEN_DISAB 0x0040u 109 #define R_H_TOTAL 0x26e8u /* Read */ 110 /* ? 0x2ae8u */ 111 /* ? 0x2ee8u */ 112 /* ? 0x32e8u */ 113 /* ? 0x36e8u */ 114 /* ? 0x3ae8u */ 115 /* ? 0x3ee8u */ 116 #define SUBSYS_STAT 0x42e8u /* Read */ 117 #define VBLNKFLG 0x0001u 118 #define PICKFLAG 0x0002u 119 #define INVALIDIO 0x0004u 120 #define GPIDLE 0x0008u 121 #define MONITORID_MASK 0x0070u 122 /* MONITORID_? 0x0000u */ 123 #define MONITORID_8507 0x0010u 124 #define MONITORID_8514 0x0020u 125 /* MONITORID_? 0x0030u */ 126 /* MONITORID_? 0x0040u */ 127 #define MONITORID_8503 0x0050u 128 #define MONITORID_8512 0x0060u 129 #define MONITORID_8513 0x0060u 130 #define MONITORID_NONE 0x0070u 131 #define _8PLANE 0x0080u 132 #define SUBSYS_CNTL 0x42e8u /* Write */ 133 #define RVBLNKFLG 0x0001u 134 #define RPICKFLAG 0x0002u 135 #define RINVALIDIO 0x0004u 136 #define RGPIDLE 0x0008u 137 #define IVBLNKFLG 0x0100u 138 #define IPICKFLAG 0x0200u 139 #define IINVALIDIO 0x0400u 140 #define IGPIDLE 0x0800u 141 #define CHPTEST_NC 0x0000u 142 #define CHPTEST_NORMAL 0x1000u 143 #define CHPTEST_ENAB 0x2000u 144 #define GPCTRL_NC 0x0000u 145 #define GPCTRL_ENAB 0x4000u 146 #define GPCTRL_RESET 0x8000u 147 #define ROM_PAGE_SEL 0x46e8u /* Write */ 148 #define ADVFUNC_CNTL 0x4ae8u /* Write */ 149 #define DISABPASSTHRU 0x0001u 150 #define CLOKSEL 0x0004u 151 /* ? 0x4ee8u */ 152 #define EXT_CONFIG_0 0x52e8u /* C & T 82C480 */ 153 #define EXT_CONFIG_1 0x56e8u /* C & T 82C480 */ 154 #define EXT_CONFIG_2 0x5ae8u /* C & T 82C480 */ 155 #define EXT_CONFIG_3 0x5ee8u /* C & T 82C480 */ 156 /* ? 0x62e8u */ 157 /* ? 0x66e8u */ 158 /* ? 0x6ae8u */ 159 /* ? 0x6ee8u */ 160 /* ? 0x72e8u */ 161 /* ? 0x76e8u */ 162 /* ? 0x7ae8u */ 163 /* ? 0x7ee8u */ 164 #define CUR_Y 0x82e8u 165 #define CUR_X 0x86e8u 166 #define DESTY_AXSTP 0x8ae8u /* Write */ 167 #define DESTX_DIASTP 0x8ee8u /* Write */ 168 #define ERR_TERM 0x92e8u 169 #define MAJ_AXIS_PCNT 0x96e8u /* Write */ 170 #define GP_STAT 0x9ae8u /* Read */ 171 #define GE_STAT 0x9ae8u /* Alias */ 172 #define DATARDY 0x0100u 173 #define DATA_READY DATARDY /* Alias */ 174 #define GPBUSY 0x0200u 175 #define CMD 0x9ae8u /* Write */ 176 #define WRTDATA 0x0001u 177 #define PLANAR 0x0002u 178 #define LASTPIX 0x0004u 179 #define LINETYPE 0x0008u 180 #define DRAW 0x0010u 181 #define INC_X 0x0020u 182 #define YMAJAXIS 0x0040u 183 #define INC_Y 0x0080u 184 #define PCDATA 0x0100u 185 #define _16BIT 0x0200u 186 #define CMD_NOP 0x0000u 187 #define CMD_OP_MSK 0xf000u 188 #define BYTSEQ 0x1000u 189 #define CMD_LINE 0x2000u 190 #define CMD_RECT 0x4000u 191 #define CMD_RECTV1 0x6000u 192 #define CMD_RECTV2 0x8000u 193 #define CMD_LINEAF 0xa000u 194 #define CMD_BITBLT 0xc000u 195 #define SHORT_STROKE 0x9ee8u /* Write */ 196 #define SSVDRAW 0x0010u 197 #define VECDIR_000 0x0000u 198 #define VECDIR_045 0x0020u 199 #define VECDIR_090 0x0040u 200 #define VECDIR_135 0x0060u 201 #define VECDIR_180 0x0080u 202 #define VECDIR_225 0x00a0u 203 #define VECDIR_270 0x00c0u 204 #define VECDIR_315 0x00e0u 205 #define BKGD_COLOR 0xa2e8u /* Write */ 206 #define FRGD_COLOR 0xa6e8u /* Write */ 207 #define WRT_MASK 0xaae8u /* Write */ 208 #define RD_MASK 0xaee8u /* Write */ 209 #define COLOR_CMP 0xb2e8u /* Write */ 210 #define BKGD_MIX 0xb6e8u /* Write */ 211 /* 0x001fu See MIX_* definitions below */ 212 #define BSS_BKGDCOL 0x0000u 213 #define BSS_FRGDCOL 0x0020u 214 #define BSS_PCDATA 0x0040u 215 #define BSS_BITBLT 0x0060u 216 #define FRGD_MIX 0xbae8u /* Write */ 217 /* 0x001fu See MIX_* definitions below */ 218 #define FSS_BKGDCOL 0x0000u 219 #define FSS_FRGDCOL 0x0020u 220 #define FSS_PCDATA 0x0040u 221 #define FSS_BITBLT 0x0060u 222 #define MULTIFUNC_CNTL 0xbee8u /* Write */ 223 #define MIN_AXIS_PCNT 0x0000u 224 #define SCISSORS_T 0x1000u 225 #define SCISSORS_L 0x2000u 226 #define SCISSORS_B 0x3000u 227 #define SCISSORS_R 0x4000u 228 #define M32_MEM_CNTL 0x5000u 229 #define HORCFG_4 0x0000u 230 #define HORCFG_5 0x0001u 231 #define HORCFG_8 0x0002u 232 #define HORCFG_10 0x0003u 233 #define VRTCFG_2 0x0000u 234 #define VRTCFG_4 0x0004u 235 #define VRTCFG_6 0x0008u 236 #define VRTCFG_8 0x000cu 237 #define BUFSWP 0x0010u 238 #define PATTERN_L 0x8000u 239 #define PATTERN_H 0x9000u 240 #define PIX_CNTL 0xa000u 241 #define PLANEMODE 0x0004u 242 #define COLCMPOP_F 0x0000u 243 #define COLCMPOP_T 0x0008u 244 #define COLCMPOP_GE 0x0010u 245 #define COLCMPOP_LT 0x0018u 246 #define COLCMPOP_NE 0x0020u 247 #define COLCMPOP_EQ 0x0028u 248 #define COLCMPOP_LE 0x0030u 249 #define COLCMPOP_GT 0x0038u 250 #define MIXSEL_FRGDMIX 0x0000u 251 #define MIXSEL_PATT 0x0040u 252 #define MIXSEL_EXPPC 0x0080u 253 #define MIXSEL_EXPBLT 0x00c0u 254 /* ? 0xc2e8u */ 255 /* ? 0xc6e8u */ 256 /* ? 0xcae8u */ 257 /* ? 0xcee8u */ 258 /* ? 0xd2e8u */ 259 /* ? 0xd6e8u */ 260 /* ? 0xdae8u */ 261 /* ? 0xdee8u */ 262 #define PIX_TRANS 0xe2e8u 263 /* ? 0xe6e8u */ 264 /* ? 0xeae8u */ 265 /* ? 0xeee8u */ 266 /* ? 0xf2e8u */ 267 /* ? 0xf6e8u */ 268 /* ? 0xfae8u */ 269 /* ? 0xfee8u */ 270 271 /* ATI Mach8 & Mach32 register definitions */ 272 #define OVERSCAN_COLOR_8 0x02eeu /* Write */ /* Mach32 */ 273 #define OVERSCAN_BLUE_24 0x02efu /* Write */ /* Mach32 */ 274 #define OVERSCAN_GREEN_24 0x06eeu /* Write */ /* Mach32 */ 275 #define OVERSCAN_RED_24 0x06efu /* Write */ /* Mach32 */ 276 #define CURSOR_OFFSET_LO 0x0aeeu /* Write */ /* Mach32 */ 277 #define CURSOR_OFFSET_HI 0x0eeeu /* Write */ /* Mach32 */ 278 #define CONFIG_STATUS_1 0x12eeu /* Read */ 279 #define CLK_MODE 0x0001u /* Mach8 */ 280 #define BUS_16 0x0002u /* Mach8 */ 281 #define MC_BUS 0x0004u /* Mach8 */ 282 #define EEPROM_ENA 0x0008u /* Mach8 */ 283 #define DRAM_ENA 0x0010u /* Mach8 */ 284 #define MEM_INSTALLED 0x0060u /* Mach8 */ 285 #define ROM_ENA 0x0080u /* Mach8 */ 286 #define ROM_PAGE_ENA 0x0100u /* Mach8 */ 287 #define ROM_LOCATION 0xfe00u /* Mach8 */ 288 #define _8514_ONLY 0x0001u /* Mach32 */ 289 #define BUS_TYPE 0x000eu /* Mach32 */ 290 #define ISA_16_BIT 0x0000u /* Mach32 */ 291 #define EISA 0x0002u /* Mach32 */ 292 #define MICRO_C_16_BIT 0x0004u /* Mach32 */ 293 #define MICRO_C_8_BIT 0x0006u /* Mach32 */ 294 #define LOCAL_386SX 0x0008u /* Mach32 */ 295 #define LOCAL_386DX 0x000au /* Mach32 */ 296 #define LOCAL_486 0x000cu /* Mach32 */ 297 #define PCI 0x000eu /* Mach32 */ 298 #define MEM_TYPE 0x0070u /* Mach32 */ 299 #define CHIP_DIS 0x0080u /* Mach32 */ 300 #define TST_VCTR_ENA 0x0100u /* Mach32 */ 301 #define DACTYPE 0x0e00u /* Mach32 */ 302 #define MC_ADR_DECODE 0x1000u /* Mach32 */ 303 #define CARD_ID 0xe000u /* Mach32 */ 304 #define HORZ_CURSOR_POSN 0x12eeu /* Write */ /* Mach32 */ 305 #define CONFIG_STATUS_2 0x16eeu /* Read */ 306 #define SHARE_CLOCK 0x0001u /* Mach8 */ 307 #define HIRES_BOOT 0x0002u /* Mach8 */ 308 #define EPROM_16_ENA 0x0004u /* Mach8 */ 309 #define WRITE_PER_BIT 0x0008u /* Mach8 */ 310 #define FLASH_ENA 0x0010u /* Mach8 */ 311 #define SLOW_SEQ_EN 0x0001u /* Mach32 */ 312 #define MEM_ADDR_DIS 0x0002u /* Mach32 */ 313 #define ISA_16_ENA 0x0004u /* Mach32 */ 314 #define KOR_TXT_MODE_ENA 0x0008u /* Mach32 */ 315 #define LOCAL_BUS_SUPPORT 0x0030u /* Mach32 */ 316 #define LOCAL_BUS_CONFIG_2 0x0040u /* Mach32 */ 317 #define LOCAL_BUS_RD_DLY_ENA 0x0080u /* Mach32 */ 318 #define LOCAL_DAC_EN 0x0100u /* Mach32 */ 319 #define LOCAL_RDY_EN 0x0200u /* Mach32 */ 320 #define EEPROM_ADR_SEL 0x0400u /* Mach32 */ 321 #define GE_STRAP_SEL 0x0800u /* Mach32 */ 322 #define VESA_RDY 0x1000u /* Mach32 */ 323 #define Z4GB 0x2000u /* Mach32 */ 324 #define LOC2_MDRAM 0x4000u /* Mach32 */ 325 #define VERT_CURSOR_POSN 0x16eeu /* Write */ /* Mach32 */ 326 #define FIFO_TEST_DATA 0x1aeeu /* Read */ /* Mach32 */ 327 #define CURSOR_COLOR_0 0x1aeeu /* Write */ /* Mach32 */ 328 #define CURSOR_COLOR_1 0x1aefu /* Write */ /* Mach32 */ 329 #define HORZ_CURSOR_OFFSET 0x1eeeu /* Write */ /* Mach32 */ 330 #define VERT_CURSOR_OFFSET 0x1eefu /* Write */ /* Mach32 */ 331 #define PCI_CNTL 0x22eeu /* Mach32-PCI */ 332 #define CRT_PITCH 0x26eeu /* Write */ 333 #define CRT_OFFSET_LO 0x2aeeu /* Write */ 334 #define CRT_OFFSET_HI 0x2eeeu /* Write */ 335 #define LOCAL_CNTL 0x32eeu /* Mach32 */ 336 #define FIFO_OPT 0x36eeu /* Write */ /* Mach8 */ 337 #define MISC_OPTIONS 0x36eeu /* Mach32 */ 338 #define W_STATE_ENA 0x0000u /* Mach32 */ 339 #define HOST_8_ENA 0x0001u /* Mach32 */ 340 #define MEM_SIZE_ALIAS 0x000cu /* Mach32 */ 341 #define MEM_SIZE_512K 0x0000u /* Mach32 */ 342 #define MEM_SIZE_1M 0x0004u /* Mach32 */ 343 #define MEM_SIZE_2M 0x0008u /* Mach32 */ 344 #define MEM_SIZE_4M 0x000cu /* Mach32 */ 345 #define DISABLE_VGA 0x0010u /* Mach32 */ 346 #define _16_BIT_IO 0x0020u /* Mach32 */ 347 #define DISABLE_DAC 0x0040u /* Mach32 */ 348 #define DLY_LATCH_ENA 0x0080u /* Mach32 */ 349 #define TEST_MODE 0x0100u /* Mach32 */ 350 #define BLK_WR_ENA 0x0400u /* Mach32 */ 351 #define _64_DRAW_ENA 0x0800u /* Mach32 */ 352 #define FIFO_TEST_TAG 0x3aeeu /* Read */ /* Mach32 */ 353 #define EXT_CURSOR_COLOR_0 0x3aeeu /* Write */ /* Mach32 */ 354 #define EXT_CURSOR_COLOR_1 0x3eeeu /* Write */ /* Mach32 */ 355 #define MEM_BNDRY 0x42eeu /* Mach32 */ 356 #define MEM_PAGE_BNDRY 0x000fu /* Mach32 */ 357 #define MEM_BNDRY_ENA 0x0010u /* Mach32 */ 358 #define SHADOW_CTL 0x46eeu /* Write */ 359 #define CLOCK_SEL 0x4aeeu 360 /* DISABPASSTHRU 0x0001u See ADVFUNC_CNTL */ 361 #define VFIFO_DEPTH_1 0x0100u /* Mach32 */ 362 #define VFIFO_DEPTH_2 0x0200u /* Mach32 */ 363 #define VFIFO_DEPTH_3 0x0300u /* Mach32 */ 364 #define VFIFO_DEPTH_4 0x0400u /* Mach32 */ 365 #define VFIFO_DEPTH_5 0x0500u /* Mach32 */ 366 #define VFIFO_DEPTH_6 0x0600u /* Mach32 */ 367 #define VFIFO_DEPTH_7 0x0700u /* Mach32 */ 368 #define VFIFO_DEPTH_8 0x0800u /* Mach32 */ 369 #define VFIFO_DEPTH_9 0x0900u /* Mach32 */ 370 #define VFIFO_DEPTH_A 0x0a00u /* Mach32 */ 371 #define VFIFO_DEPTH_B 0x0b00u /* Mach32 */ 372 #define VFIFO_DEPTH_C 0x0c00u /* Mach32 */ 373 #define VFIFO_DEPTH_D 0x0d00u /* Mach32 */ 374 #define VFIFO_DEPTH_E 0x0e00u /* Mach32 */ 375 #define VFIFO_DEPTH_F 0x0f00u /* Mach32 */ 376 #define COMPOSITE_SYNC 0x1000u 377 /* ? 0x4eeeu */ 378 #define ROM_ADDR_1 0x52eeu 379 #define BIOS_BASE_SEGMENT 0x007fu /* Mach32 */ 380 /* ? 0xff80u */ /* Mach32 */ 381 #define ROM_ADDR_2 0x56eeu /* Sick ... */ 382 #define SHADOW_SET 0x5aeeu /* Write */ 383 #define MEM_CFG 0x5eeeu /* Mach32 */ 384 #define MEM_APERT_SEL 0x0003u /* Mach32 */ 385 #define MEM_APERT_PAGE 0x000cu /* Mach32 */ 386 #define MEM_APERT_LOC 0xfff0u /* Mach32 */ 387 #define EXT_GE_STATUS 0x62eeu /* Read */ /* Mach32 */ 388 #define HORZ_OVERSCAN 0x62eeu /* Write */ /* Mach32 */ 389 #define VERT_OVERSCAN 0x66eeu /* Write */ /* Mach32 */ 390 #define MAX_WAITSTATES 0x6aeeu 391 #define GE_OFFSET_LO 0x6eeeu /* Write */ 392 #define BOUNDS_LEFT 0x72eeu /* Read */ 393 #define GE_OFFSET_HI 0x72eeu /* Write */ 394 #define BOUNDS_TOP 0x76eeu /* Read */ 395 #define GE_PITCH 0x76eeu /* Write */ 396 #define BOUNDS_RIGHT 0x7aeeu /* Read */ 397 #define EXT_GE_CONFIG 0x7aeeu /* Write */ /* Mach32 */ 398 #define MONITOR_ALIAS 0x0007u /* Mach32 */ 399 /* MONITOR_? 0x0000u */ /* Mach32 */ 400 #define MONITOR_8507 0x0001u /* Mach32 */ 401 #define MONITOR_8514 0x0002u /* Mach32 */ 402 /* MONITOR_? 0x0003u */ /* Mach32 */ 403 /* MONITOR_? 0x0004u */ /* Mach32 */ 404 #define MONITOR_8503 0x0005u /* Mach32 */ 405 #define MONITOR_8512 0x0006u /* Mach32 */ 406 #define MONITOR_8513 0x0006u /* Mach32 */ 407 #define MONITOR_NONE 0x0007u /* Mach32 */ 408 #define ALIAS_ENA 0x0008u /* Mach32 */ 409 #define PIXEL_WIDTH_4 0x0000u /* Mach32 */ 410 #define PIXEL_WIDTH_8 0x0010u /* Mach32 */ 411 #define PIXEL_WIDTH_16 0x0020u /* Mach32 */ 412 #define PIXEL_WIDTH_24 0x0030u /* Mach32 */ 413 #define RGB16_555 0x0000u /* Mach32 */ 414 #define RGB16_565 0x0040u /* Mach32 */ 415 #define RGB16_655 0x0080u /* Mach32 */ 416 #define RGB16_664 0x00c0u /* Mach32 */ 417 #define MULTIPLEX_PIXELS 0x0100u /* Mach32 */ 418 #define RGB24 0x0000u /* Mach32 */ 419 #define RGBx24 0x0200u /* Mach32 */ 420 #define BGR24 0x0400u /* Mach32 */ 421 #define xBGR24 0x0600u /* Mach32 */ 422 #define DAC_8_BIT_EN 0x4000u /* Mach32 */ 423 #define ORDER_16BPP_565 RGB16_565 /* Mach32 */ 424 #define BOUNDS_BOTTOM 0x7eeeu /* Read */ 425 #define MISC_CNTL 0x7eeeu /* Write */ /* Mach32 */ 426 #define PATT_DATA_INDEX 0x82eeu 427 /* ? 0x86eeu */ 428 /* ? 0x8aeeu */ 429 #define R_EXT_GE_CONFIG 0x8eeeu /* Read */ /* Mach32 */ 430 #define PATT_DATA 0x8eeeu /* Write */ 431 #define R_MISC_CNTL 0x92eeu /* Read */ /* Mach32 */ 432 #define BRES_COUNT 0x96eeu 433 #define EXT_FIFO_STATUS 0x9aeeu /* Read */ 434 #define LINEDRAW_INDEX 0x9aeeu /* Write */ 435 /* ? 0x9eeeu */ 436 #define LINEDRAW_OPT 0xa2eeu 437 #define BOUNDS_RESET 0x0100u 438 #define CLIP_MODE_0 0x0000u /* Clip exception disabled */ 439 #define CLIP_MODE_1 0x0200u /* Line segments */ 440 #define CLIP_MODE_2 0x0400u /* Polygon boundary lines */ 441 #define CLIP_MODE_3 0x0600u /* Patterned lines */ 442 #define DEST_X_START 0xa6eeu /* Write */ 443 #define DEST_X_END 0xaaeeu /* Write */ 444 #define DEST_Y_END 0xaeeeu /* Write */ 445 #define R_H_TOTAL_DISP 0xb2eeu /* Read */ /* Mach32 */ 446 #define SRC_X_STRT 0xb2eeu /* Write */ 447 #define R_H_SYNC_STRT 0xb6eeu /* Read */ /* Mach32 */ 448 #define ALU_BG_FN 0xb6eeu /* Write */ 449 #define R_H_SYNC_WID 0xbaeeu /* Read */ /* Mach32 */ 450 #define ALU_FG_FN 0xbaeeu /* Write */ 451 #define SRC_X_END 0xbeeeu /* Write */ 452 #define R_V_TOTAL 0xc2eeu /* Read */ 453 #define SRC_Y_DIR 0xc2eeu /* Write */ 454 #define R_V_DISP 0xc6eeu /* Read */ /* Mach32 */ 455 #define EXT_SHORT_STROKE 0xc6eeu /* Write */ 456 #define R_V_SYNC_STRT 0xcaeeu /* Read */ /* Mach32 */ 457 #define SCAN_X 0xcaeeu /* Write */ 458 #define VERT_LINE_CNTR 0xceeeu /* Read */ /* Mach32 */ 459 #define DP_CONFIG 0xceeeu /* Write */ 460 #define READ_WRITE 0x0001u 461 #define DATA_WIDTH 0x0200u 462 #define DATA_ORDER 0x1000u 463 #define FG_COLOR_SRC_FG 0x2000u 464 #define FG_COLOR_SRC_BLIT 0x6000u 465 #define R_V_SYNC_WID 0xd2eeu /* Read */ 466 #define PATT_LENGTH 0xd2eeu /* Write */ 467 #define PATT_INDEX 0xd6eeu /* Write */ 468 #define READ_SRC_X 0xdaeeu /* Read */ /* Mach32 */ 469 #define EXT_SCISSOR_L 0xdaeeu /* Write */ 470 #define READ_SRC_Y 0xdeeeu /* Read */ /* Mach32 */ 471 #define EXT_SCISSOR_T 0xdeeeu /* Write */ 472 #define EXT_SCISSOR_R 0xe2eeu /* Write */ 473 #define EXT_SCISSOR_B 0xe6eeu /* Write */ 474 /* ? 0xeaeeu */ 475 #define DEST_COMP_FN 0xeeeeu /* Write */ 476 #define DEST_COLOR_CMP_MASK 0xf2eeu /* Write */ /* Mach32 */ 477 /* ? 0xf6eeu */ 478 #define CHIP_ID 0xfaeeu /* Read */ /* Mach32 */ 479 #define CHIP_CODE_0 0x001fu /* Mach32 */ 480 #define CHIP_CODE_1 0x03e0u /* Mach32 */ 481 #define CHIP_CLASS 0x0c00u /* Mach32 */ 482 #define CHIP_REV 0xf000u /* Mach32 */ 483 #define LINEDRAW 0xfeeeu /* Write */ 484 485 /* ATI Mach64 register definitions */ 486 #define CRTC_H_TOTAL_DISP IOPortTag(0x00u, 0x00u) 487 # define CRTC_H_TOTAL 0x000001fful 488 /* ? 0x0000fe00ul */ 489 # define CRTC_H_DISP 0x01ff0000ul 490 /* ? 0xfe000000ul */ 491 #define CRTC_H_SYNC_STRT_WID IOPortTag(0x01u, 0x01u) 492 # define CRTC_H_SYNC_STRT 0x000000fful 493 # define CRTC_H_SYNC_DLY 0x00000700ul 494 /* ? 0x00000800ul */ 495 # define CRTC_H_SYNC_STRT_HI 0x00001000ul 496 /* ? 0x0000e000ul */ 497 # define CRTC_H_SYNC_WID 0x001f0000ul 498 # define CRTC_H_SYNC_POL 0x00200000ul 499 /* ? 0xffc00000ul */ 500 #define CRTC_V_TOTAL_DISP IOPortTag(0x02u, 0x02u) 501 # define CRTC_V_TOTAL 0x000007fful 502 /* ? 0x0000f800ul */ 503 # define CRTC_V_DISP 0x07ff0000ul 504 /* ? 0xf8000000ul */ 505 #define CRTC_V_SYNC_STRT_WID IOPortTag(0x03u, 0x03u) 506 # define CRTC_V_SYNC_STRT 0x000007fful 507 /* ? 0x0000f800ul */ 508 # define CRTC_V_SYNC_WID 0x001f0000ul 509 # define CRTC_V_SYNC_POL 0x00200000ul 510 /* ? 0xffc00000ul */ 511 #define CRTC_VLINE_CRNT_VLINE IOPortTag(0x04u, 0x04u) 512 #define CRTC_VLINE 0x000007fful 513 /* ? 0x0000f800ul */ 514 #define CRTC_CRNT_VLINE 0x07ff0000ul 515 /* ? 0xf8000000ul */ 516 #define CRTC_OFF_PITCH IOPortTag(0x05u, 0x05u) 517 # define CRTC_OFFSET 0x000ffffful 518 # define CRTC_OFFSET_VGA 0x0003fffful 519 # define CRTC_OFFSET_LOCK 0x00100000ul /* XC/XL */ 520 /* ? 0x00200000ul */ 521 # define CRTC_PITCH 0xffc00000ul 522 #define CRTC_INT_CNTL IOPortTag(0x06u, 0x06u) 523 # define CRTC_VBLANK 0x00000001ul 524 # define CRTC_VBLANK_INT_EN 0x00000002ul 525 # define CRTC_VBLANK_INT 0x00000004ul 526 # define CRTC_VLINE_INT_EN 0x00000008ul 527 # define CRTC_VLINE_INT 0x00000010ul 528 # define CRTC_VLINE_SYNC 0x00000020ul 529 # define CRTC_FRAME 0x00000040ul 530 # define CRTC_SNAPSHOT_INT_EN 0x00000080ul /* GTPro */ 531 # define CRTC_SNAPSHOT_INT 0x00000100ul /* GTPro */ 532 # define CRTC_I2C_INT_EN 0x00000200ul /* GTPro */ 533 # define CRTC_I2C_INT 0x00000400ul /* GTPro */ 534 # define CRTC2_VBLANK 0x00000800ul /* LTPro */ 535 # define CRTC2_VBLANK_INT_EN 0x00001000ul /* LTPro */ 536 # define CRTC2_VBLANK_INT 0x00002000ul /* LTPro */ 537 # define CRTC2_VLINE_INT_EN 0x00004000ul /* LTPro */ 538 # define CRTC2_VLINE_INT 0x00008000ul /* LTPro */ 539 # define CRTC_CAPBUF0_INT_EN 0x00010000ul /* VT/GT */ 540 # define CRTC_CAPBUF0_INT 0x00020000ul /* VT/GT */ 541 # define CRTC_CAPBUF1_INT_EN 0x00040000ul /* VT/GT */ 542 # define CRTC_CAPBUF1_INT 0x00080000ul /* VT/GT */ 543 # define CRTC_OVERLAY_EOF_INT_EN 0x00100000ul /* VT/GT */ 544 # define CRTC_OVERLAY_EOF_INT 0x00200000ul /* VT/GT */ 545 # define CRTC_ONESHOT_CAP_INT_EN 0x00400000ul /* VT/GT */ 546 # define CRTC_ONESHOT_CAP_INT 0x00800000ul /* VT/GT */ 547 # define CRTC_BUSMASTER_EOL_INT_EN 0x01000000ul /* VTB/GTB/LT */ 548 # define CRTC_BUSMASTER_EOL_INT 0x02000000ul /* VTB/GTB/LT */ 549 # define CRTC_GP_INT_EN 0x04000000ul /* VTB/GTB/LT */ 550 # define CRTC_GP_INT 0x08000000ul /* VTB/GTB/LT */ 551 # define CRTC2_VLINE_SYNC 0x10000000ul /* LTPro */ 552 # define CRTC_SNAPSHOT2_INT_EN 0x20000000ul /* LTPro */ 553 # define CRTC_SNAPSHOT2_INT 0x40000000ul /* LTPro */ 554 # define CRTC_VBLANK_BIT2_INT 0x80000000ul /* GTPro */ 555 # define CRTC_INT_ENS /* *** UPDATE ME *** */ \ 556 ( \ 557 CRTC_VBLANK_INT_EN | \ 558 CRTC_VLINE_INT_EN | \ 559 CRTC_SNAPSHOT_INT_EN | \ 560 CRTC_I2C_INT_EN | \ 561 CRTC2_VBLANK_INT_EN | \ 562 CRTC2_VLINE_INT_EN | \ 563 CRTC_CAPBUF0_INT_EN | \ 564 CRTC_CAPBUF1_INT_EN | \ 565 CRTC_OVERLAY_EOF_INT_EN | \ 566 CRTC_ONESHOT_CAP_INT_EN | \ 567 CRTC_BUSMASTER_EOL_INT_EN | \ 568 CRTC_GP_INT_EN | \ 569 CRTC_SNAPSHOT2_INT_EN | \ 570 0 \ 571 ) 572 # define CRTC_INT_ACKS /* *** UPDATE ME *** */ \ 573 ( \ 574 CRTC_VBLANK_INT | \ 575 CRTC_VLINE_INT | \ 576 CRTC_SNAPSHOT_INT | \ 577 CRTC_I2C_INT | \ 578 CRTC2_VBLANK_INT | \ 579 CRTC2_VLINE_INT | \ 580 CRTC_CAPBUF0_INT | \ 581 CRTC_CAPBUF1_INT | \ 582 CRTC_OVERLAY_EOF_INT | \ 583 CRTC_ONESHOT_CAP_INT | \ 584 CRTC_BUSMASTER_EOL_INT | \ 585 CRTC_GP_INT | \ 586 CRTC_SNAPSHOT2_INT | \ 587 CRTC_VBLANK_BIT2_INT | \ 588 0 \ 589 ) 590 #define CRTC_GEN_CNTL IOPortTag(0x07u, 0x07u) 591 # define CRTC_DBL_SCAN_EN 0x00000001ul 592 # define CRTC_INTERLACE_EN 0x00000002ul 593 # define CRTC_HSYNC_DIS 0x00000004ul 594 # define CRTC_VSYNC_DIS 0x00000008ul 595 # define CRTC_CSYNC_EN 0x00000010ul 596 # define CRTC_PIX_BY_2_EN 0x00000020ul 597 # define CRTC2_DBL_SCAN_EN 0x00000020ul /* LTPro */ 598 # define CRTC_DISPLAY_DIS 0x00000040ul 599 # define CRTC_VGA_XOVERSCAN 0x00000080ul 600 # define CRTC_PIX_WIDTH 0x00000700ul 601 # define CRTC_BYTE_PIX_ORDER 0x00000800ul 602 # define CRTC_VSYNC_INT_EN 0x00001000ul /* XC/XL */ 603 # define CRTC_VSYNC_INT 0x00002000ul /* XC/XL */ 604 # define CRTC_FIFO_OVERFILL 0x0000c000ul /* VT/GT */ 605 # define CRTC2_VSYNC_INT_EN 0x00004000ul /* XC/XL */ 606 # define CRTC2_VSYNC_INT 0x00008000ul /* XC/XL */ 607 # define CRTC_FIFO_LWM 0x000f0000ul 608 # define CRTC_HVSYNC_IO_DRIVE 0x00010000ul /* XC/XL */ 609 # define CRTC2_PIX_WIDTH 0x000e0000ul /* LTPro */ 610 # define CRTC_VGA_128KAP_PAGING 0x00100000ul /* VT/GT */ 611 # define CRTC_DISPREQ_ONLY 0x00200000ul /* VT/GT */ 612 # define CRTC_VFC_SYNC_TRISTATE 0x00200000ul /* VTB/GTB/LT */ 613 # define CRTC2_EN 0x00200000ul /* LTPro */ 614 # define CRTC_LOCK_REGS 0x00400000ul /* VT/GT */ 615 # define CRTC_SYNC_TRISTATE 0x00800000ul /* VT/GT */ 616 # define CRTC_EXT_DISP_EN 0x01000000ul 617 # define CRTC_EN 0x02000000ul 618 # define CRTC_DISP_REQ_EN 0x04000000ul 619 # define CRTC_VGA_LINEAR 0x08000000ul 620 # define CRTC_VSYNC_FALL_EDGE 0x10000000ul 621 # define CRTC_VGA_TEXT_132 0x20000000ul 622 # define CRTC_CNT_EN 0x40000000ul 623 # define CRTC_CUR_B_TEST 0x80000000ul 624 # define CRTC_INT_ENS_X /* *** UPDATE ME *** */ \ 625 ( \ 626 CRTC_VSYNC_INT_EN | \ 627 CRTC2_VSYNC_INT_EN | \ 628 0 \ 629 ) 630 # define CRTC_INT_ACKS_X /* *** UPDATE ME *** */ \ 631 ( \ 632 CRTC_VSYNC_INT | \ 633 CRTC2_VSYNC_INT | \ 634 0 \ 635 ) 636 #define DSP_CONFIG BlockIOTag(0x08u) /* VTB/GTB/LT */ 637 # define DSP_XCLKS_PER_QW 0x00003ffful 638 /* ? 0x00004000ul */ 639 # define DSP_FLUSH_WB 0x00008000ul 640 # define DSP_LOOP_LATENCY 0x000f0000ul 641 # define DSP_PRECISION 0x00700000ul 642 /* ? 0xff800000ul */ 643 #define DSP_ON_OFF BlockIOTag(0x09u) /* VTB/GTB/LT */ 644 # define DSP_OFF 0x000007fful 645 /* ? 0x0000f800ul */ 646 # define DSP_ON 0x07ff0000ul 647 /* ? 0xf8000000ul */ 648 #define TIMER_CONFIG BlockIOTag(0x0au) /* VTB/GTB/LT */ 649 #define MEM_BUF_CNTL BlockIOTag(0x0bu) /* VTB/GTB/LT */ 650 #define SHARED_CNTL BlockIOTag(0x0cu) /* VTB/GTB/LT */ 651 #define SHARED_MEM_CONFIG BlockIOTag(0x0du) /* VTB/GTB/LT */ 652 #define MEM_ADDR_CONFIG BlockIOTag(0x0du) /* GTPro */ 653 #define SHARED_CNTL_CTD BlockIOTag(0x0eu) /* CTD */ 654 /* ? 0x00fffffful */ 655 #define CTD_FIFO5 0x01000000ul 656 /* ? 0xfe000000ul */ 657 #define CRT_TRAP BlockIOTag(0x0eu) /* VTB/GTB/LT */ 658 #define DSTN_CONTROL BlockIOTag(0x0fu) /* LT */ 659 #define I2C_CNTL_0 BlockIOTag(0x0fu) /* GTPro */ 660 #define OVR_CLR IOPortTag(0x08u, 0x10u) 661 # define OVR_CLR_8 0x000000fful 662 # define OVR_CLR_B 0x0000ff00ul 663 # define OVR_CLR_G 0x00ff0000ul 664 # define OVR_CLR_R 0xff000000ul 665 #define OVR_WID_LEFT_RIGHT IOPortTag(0x09u, 0x11u) 666 # define OVR_WID_LEFT 0x0000003ful /* 0x0f on <LT */ 667 /* ? 0x0000ffc0ul */ 668 # define OVR_WID_RIGHT 0x003f0000ul /* 0x0f0000 on <LT */ 669 /* ? 0xffc00000ul */ 670 #define OVR_WID_TOP_BOTTOM IOPortTag(0x0au, 0x12u) 671 # define OVR_WID_TOP 0x000001fful /* 0x00ff on <LT */ 672 /* ? 0x0000fe00ul */ 673 # define OVR_WID_BOTTOM 0x01ff0000ul /* 0x00ff0000 on <LT */ 674 /* ? 0xfe000000ul */ 675 #define VGA_DSP_CONFIG BlockIOTag(0x13u) /* VTB/GTB/LT */ 676 # define VGA_DSP_XCLKS_PER_QW DSP_XCLKS_PER_QW 677 /* ? 0x000fc000ul */ 678 # define VGA_DSP_PREC_PCLKBY2 0x00700000ul 679 /* ? 0x00800000ul */ 680 # define VGA_DSP_PREC_PCLK 0x07000000ul 681 /* ? 0xf8000000ul */ 682 #define VGA_DSP_ON_OFF BlockIOTag(0x14u) /* VTB/GTB/LT */ 683 # define VGA_DSP_OFF DSP_OFF 684 /* ? 0x0000f800ul */ 685 # define VGA_DSP_ON DSP_ON 686 /* ? 0xf8000000ul */ 687 #define DSP2_CONFIG BlockIOTag(0x15u) /* LTPro */ 688 #define DSP2_ON_OFF BlockIOTag(0x16u) /* LTPro */ 689 #define EXT_CRTC_GEN_CNTL BlockIOTag(0x17u) /* VT-A4 (W) */ 690 #define CRTC2_OFF_PITCH BlockIOTag(0x17u) /* LTPro */ 691 #define CUR_CLR0 IOPortTag(0x0bu, 0x18u) 692 #define CUR_CLR1 IOPortTag(0x0cu, 0x19u) 693 /* These are for both CUR_CLR0 and CUR_CLR1 */ 694 # define CUR_CLR_I 0x000000fful 695 # define CUR_CLR_B 0x0000ff00ul 696 # define CUR_CLR_G 0x00ff0000ul 697 # define CUR_CLR_R 0xff000000ul 698 # define CUR_CLR (CUR_CLR_R | CUR_CLR_G | CUR_CLR_B) 699 #define CUR_OFFSET IOPortTag(0x0du, 0x1au) 700 #define CUR_HORZ_VERT_POSN IOPortTag(0x0eu, 0x1bu) 701 # define CUR_HORZ_POSN 0x000007fful 702 /* ? 0x0000f800ul */ 703 # define CUR_VERT_POSN 0x07ff0000ul 704 /* ? 0xf8000000ul */ 705 #define CUR_HORZ_VERT_OFF IOPortTag(0x0fu, 0x1cu) 706 # define CUR_HORZ_OFF 0x0000007ful 707 /* ? 0x0000ff80ul */ 708 # define CUR_VERT_OFF 0x007f0000ul 709 /* ? 0xff800000ul */ 710 #define CONFIG_PANEL BlockIOTag(0x1du) /* LT */ 711 # define PANEL_FORMAT 0x00000007ul 712 /* ? 0x00000008ul */ 713 # define PANEL_TYPE 0x000000f0ul 714 # define NO_OF_GREY 0x00000700ul 715 # define MOD_GEN 0x00001800ul 716 # define EXT_LVDS_CLK 0x00001800ul /* LTPro */ 717 # define BLINK_RATE 0x00006000ul 718 # define BLINK_RATE_PRO 0x00002000ul /* LTPro */ 719 # define DONT_SHADOW_HEND 0x00004000ul /* LTPro */ 720 # define DONT_USE_F32KHZ 0x00008000ul 721 # define LCD_IO_DRIVE 0x00008000ul /* XC/XL */ 722 # define FP_POL 0x00010000ul 723 # define LP_POL 0x00020000ul 724 # define DTMG_POL 0x00040000ul 725 # define SCK_POL 0x00080000ul 726 # define DITHER_SEL 0x00300000ul 727 # define INVERSE_VIDEO_EN 0x00400000ul 728 # define BL_CLK_SEL 0x01800000ul 729 # define BL_LEVEL 0x0e000000ul 730 # define BL_CLK_SEL_PRO 0x00800000ul /* LTPro */ 731 # define BL_LEVEL_PRO 0x03000000ul /* LTPro */ 732 # define BIAS_LEVEL_PRO 0x0c000000ul /* LTPro */ 733 # define HSYNC_DELAY 0xf0000000ul 734 #define TV_OUT_INDEX BlockIOTag(0x1du) /* LTPro */ 735 # define TV_REG_INDEX 0x000000fful 736 # define TV_ON 0x00000100ul 737 /* ? 0xfffffe00ul */ 738 #define GP_IO IOPortTag(0x1eu, 0x1eu) /* VT/GT */ 739 #define GP_IO_CNTL BlockIOTag(0x1fu) /* VT/GT */ 740 #define HW_DEBUG BlockIOTag(0x1fu) /* VTB/GTB/LT */ 741 # define FAST_SRCCOPY_DIS 0x00000001ul 742 # define BYPASS_SUBPIC_DBF 0x00000001ul /* XL/XC */ 743 # define SRC_AUTONA_FIX_DIS 0x00000002ul 744 # define SYNC_PD_EN 0x00000002ul /* Mobility */ 745 # define DISP_QW_FIX_DIS 0x00000004ul 746 # define GUIDST_WB_EXP_DIS 0x00000008ul 747 # define CYC_ALL_FIX_DIS 0x00000008ul /* GTPro */ 748 # define AGPPLL_FIX_EN 0x00000008ul /* Mobility */ 749 # define SRC_AUTONA_ALWAYS_EN 0x00000010ul 750 # define GUI_BEATS_HOST_P 0x00000010ul /* GTPro */ 751 # define DRV_CNTL_DQMB_WEB 0x00000020ul 752 # define FAST_FILL_SCISSOR_DIS 0x00000020ul /* GT2c/VT4 */ 753 # define INTER_BLIT_FIX_DIS 0x00000020ul /* GTPro */ 754 # define DRV_CNTL_MA 0x00000040ul 755 # define AUTO_BLKWRT_COLOR_DIS 0x00000040ul /* GT2c/VT4 */ 756 # define INTER_PRIM_DIS 0x00000040ul /* GTPro */ 757 # define DRV_CNTL_MD 0x00000080ul 758 # define CHG_DEV_ID 0x00000100ul 759 # define SRC_TRACK_DST_FIX_DIS 0x00000200ul 760 # define HCLK_FB_SKEW 0x00000380ul /* GT2c/VT4 */ 761 # define SRC_TRACK_DST_FIX_DIS_P 0x00000080ul /* GTPro */ 762 # define AUTO_BLKWRT_COLOR_DIS_P 0x00000100ul /* GTPro */ 763 # define INTER_LINE_OVERLAP_DIS 0x00000200ul /* GTPro */ 764 # define MEM_OE_PULLBACK 0x00000400ul 765 # define DBL_BUFFER_EN 0x00000400ul /* GTPro */ 766 # define MEM_WE_FIX_DIS 0x00000800ul 767 # define MEM_OE_PULLBACK_B 0x00000800ul /* GT2c/VT4 */ 768 # define CMDFIFO_SIZE_DIS_P 0x00000800ul /* GTPro */ 769 # define RD_EN_FIX_DIS 0x00001000ul 770 # define MEM_WE_FIX_DIS_B 0x00001000ul 771 # define AUTO_FF_DIS 0x00001000ul /* GTPro */ 772 # define CMDFIFO_SIZE_DIS 0x00002000ul /* GT2c/VT4 */ 773 # define AUTO_BLKWRT_DIS 0x00002000ul /* GTPro */ 774 # define GUI_BEATS_HOST 0x00004000ul /* GT2c/VT4 */ 775 # define ORED_INVLD_RB_CACHE 0x00004000ul /* GTPro */ 776 # define BLOCK_DBL_BUF 0x00008000ul /* GTPro */ 777 # define R2W_TURNAROUND_DELAY 0x00020000ul /* GT2c/VT4 */ 778 # define ENA_32BIT_DATA_BUS 0x00040000ul /* GT2c/VT4 */ 779 # define HCLK_FB_SKEW_P 0x00070000ul /* GTPro */ 780 # define ENA_FLASH_ROM 0x00080000ul /* GT2c/VT4 */ 781 # define DISABLE_SWITCH_FIX 0x00080000ul /* GTPro */ 782 # define MCLK_START_EN 0x00080000ul /* LTPro */ 783 # define SEL_VBLANK_BDL_BUF 0x00100000ul /* GTPro */ 784 # define CMDFIFO_64EN 0x00200000ul /* GTPro must be set if IDCT_EN */ 785 # define BM_FIX_DIS 0x00400000ul /* GTPro */ 786 # define Z_SWITCH_EN 0x00800000ul /* LTPro */ 787 # define FLUSH_HOST_WB 0x01000000ul /* GTPro */ 788 # define HW_DEBUG_WRITE_MSK_FIX_DIS 0x02000000ul /* LTPro */ 789 # define Z_NO_WRITE_EN 0x04000000ul /* LTPro */ 790 # define DISABLE_PCLK_RESET_P 0x08000000ul /* LTPro */ 791 # define PM_D3_SUPPORT_ENABLE_P 0x10000000ul /* LTPro */ 792 # define STARTCYCLE_FIX_ENABLE 0x20000000ul /* LTPro */ 793 # define DONT_RST_CHAREN 0x20000000ul /* XL/XC */ 794 # define C3_FIX_ENABLE 0x40000000ul /* LTPro */ 795 # define BM_HOSTRA_EN 0x40000000ul /* XL/XC */ 796 # define PKGBGAb 0x80000000ul /* XL/XC */ 797 # define AUTOEXP_HORZ_FIX 0x80000000ul /* Mobility */ 798 #define SCRATCH_REG0 IOPortTag(0x10u, 0x20u) 799 #define SCRATCH_REG1 IOPortTag(0x11u, 0x21u) 800 /* BIOS_BASE_SEGMENT 0x0000007ful */ /* As above */ 801 /* ? 0x00000f80ul */ 802 #define BIOS_INIT_DAC_SUBTYPE 0x0000f000ul 803 /* ? 0xffff0000ul */ 804 #define SCRATCH_REG2 BlockIOTag(0x22u) /* LT */ 805 #define SCRATCH_REG3 BlockIOTag(0x23u) /* GTPro */ 806 #define CLOCK_CNTL IOPortTag(0x12u, 0x24u) 807 # define CLOCK_BIT 0x00000004ul /* For ICS2595 */ 808 # define CLOCK_PULSE 0x00000008ul /* For ICS2595 */ 809 # define CLOCK_SELECT 0x0000000ful 810 # define CLOCK_DIVIDER 0x00000030ul 811 # define CLOCK_STROBE 0x00000040ul 812 # define CLOCK_DATA 0x00000080ul 813 /* ? 0x00000100ul */ 814 # define PLL_WR_EN 0x00000200ul /* For internal PLL */ 815 # define PLL_ADDR 0x0000fc00ul /* For internal PLL */ 816 # define PLL_DATA 0x00ff0000ul /* For internal PLL */ 817 /* ? 0xff000000ul */ 818 #define CONFIG_STAT64_1 BlockIOTag(0x25u) /* GTPro */ 819 # define CFG_SUBSYS_DEV_ID 0x000000fful 820 # define CFG_SUBSYS_VEN_ID 0x00ffff00ul 821 /* ? 0x1f000000ul */ 822 # define CFG_DIMM_TYPE 0xe0000000ul 823 # define CFG_PCI_SUBSYS_DEV_ID 0x0000fffful /* XC/XL */ 824 # define CFG_PCI_SUBSYS_VEN_ID 0xffff0000ul /* XC/XL */ 825 #define CONFIG_STAT64_2 BlockIOTag(0x26u) /* GTPro */ 826 # define CFG_DIMM_TYPE_3 0x00000001ul 827 /* ? 0x0000001eul */ 828 # define CFG_ROMWRTEN 0x00000020ul 829 # define CFG_AGPVCOGAIN 0x000000c0ul 830 # define CFG_PCI_TYPE 0x00000100ul 831 # define CFG_AGPSKEW 0x00000e00ul 832 # define CFG_X1CLKSKEW 0x00007000ul 833 # define CFG_PANEL_ID_P 0x000f8000ul /* LTPro */ 834 /* ? 0x00100000ul */ 835 # define CFG_PREFETCH_EN 0x00200000ul 836 # define CFG_ID_DISABLE 0x00400000ul 837 # define CFG_PRE_TESTEN 0x00800000ul 838 /* ? 0x01000000ul */ 839 # define CFG_PCI5VEN 0x02000000ul /* LTPro */ 840 # define CFG_VGA_DISABLE 0x04000000ul 841 # define CFG_ENINTB 0x08000000ul 842 /* ? 0x10000000ul */ 843 # define CFG_ROM_REMAP_2 0x20000000ul 844 # define CFG_IDSEL 0x40000000ul 845 /* ? 0x80000000ul */ 846 #define TV_OUT_DATA BlockIOTag(0x27u) /* LTPro */ 847 #define BUS_CNTL IOPortTag(0x13u, 0x28u) 848 # define BUS_WS 0x0000000ful 849 # define BUS_DBL_RESYNC 0x00000001ul /* VTB/GTB/LT */ 850 # define BUS_MSTR_RESET 0x00000002ul /* VTB/GTB/LT */ 851 # define BUS_FLUSH_BUF 0x00000004ul /* VTB/GTB/LT */ 852 # define BUS_STOP_REQ_DIS 0x00000008ul /* VTB/GTB/LT */ 853 # define BUS_ROM_WS 0x000000f0ul 854 # define BUS_APER_REG_DIS 0x00000010ul /* VTB/GTB/LT */ 855 # define BUS_EXTRA_PIPE_DIS 0x00000020ul /* VTB/GTB/LT */ 856 # define BUS_MASTER_DIS 0x00000040ul /* VTB/GTB/LT */ 857 # define BUS_ROM_WRT_EN 0x00000080ul /* GTPro */ 858 # define BUS_ROM_PAGE 0x00000f00ul 859 # define BUS_MINOR_REV_ID 0x00000700ul /* LTPro */ 860 # define BUS_EXT_REG_EN 0x08000000ul 861 /* First silicom - Prototype (A11) 0x00000000ul */ 862 /* Metal mask spin (A12 & A13) 0x00000100ul */ 863 /* All layer spin (A21) 0x00000200ul */ 864 /* Fast metal spin (A22) - Prod. 0x00000300ul */ 865 /* All layer spin (A31) 0x00000700ul */ 866 /* ? 0x00000800ul */ /* LTPro */ 867 # define BUS_CHIP_HIDDEN_REV 0x00000300ul /* XC/XL */ 868 /* ? 0x00001c00ul */ /* XC/XL */ 869 # define BUS_ROM_DIS 0x00001000ul 870 # define BUS_IO_16_EN 0x00002000ul /* GX */ 871 # define BUS_PCI_READ_RETRY_EN 0x00002000ul /* VTB/GTB/LT */ 872 # define BUS_DAC_SNOOP_EN 0x00004000ul 873 # define BUS_PCI_RETRY_EN 0x00008000ul /* VT/GT */ 874 # define BUS_PCI_WRT_RETRY_EN 0x00008000ul /* VTB/GTB/LT */ 875 # define BUS_FIFO_WS 0x000f0000ul 876 # define BUS_RETRY_WS 0x000f0000ul /* VTB/GTB/LT */ 877 # define BUS_FIFO_ERR_INT_EN 0x00100000ul 878 # define BUS_MSTR_RD_MULT 0x00100000ul /* VTB/GTB/LT */ 879 # define BUS_FIFO_ERR_INT 0x00200000ul 880 # define BUS_MSTR_RD_LINE 0x00200000ul /* VTB/GTB/LT */ 881 # define BUS_HOST_ERR_INT_EN 0x00400000ul 882 # define BUS_SUSPEND 0x00400000ul /* GTPro */ 883 # define BUS_HOST_ERR_INT 0x00800000ul 884 # define BUS_LAT16X 0x00800000ul /* GTPro */ 885 # define BUS_PCI_DAC_WS 0x07000000ul 886 # define BUS_RD_DISCARD_EN 0x01000000ul /* VTB/GTB/LT */ 887 # define BUS_RD_ABORT_EN 0x02000000ul /* VTB/GTB/LT */ 888 # define BUS_MSTR_WS 0x04000000ul /* VTB/GTB/LT */ 889 # define BUS_PCI_DAC_DLY 0x08000000ul 890 # define BUS_EXT_REG_EN 0x08000000ul /* VT/GT */ 891 # define BUS_PCI_MEMW_WS 0x10000000ul 892 # define BUS_MSTR_DISCONNECT_EN 0x10000000ul /* VTB/GTB/LT */ 893 # define BUS_PCI_BURST_DEC 0x20000000ul /* GX/CX */ 894 # define BUS_BURST 0x20000000ul /* 264xT */ 895 # define BUS_WRT_BURST 0x20000000ul /* VTB/GTB/LT */ 896 # define BUS_RDY_READ_DLY 0xc0000000ul 897 # define BUS_READ_BURST 0x40000000ul /* VTB/GTB/LT */ 898 # define BUS_RDY_READ_DLY_B 0x80000000ul /* VTB/GTB/LT */ 899 #define LCD_INDEX BlockIOTag(0x29u) /* LTPro */ 900 # define LCD_REG_INDEX 0x0000003ful 901 # define LCD_DISPLAY_DIS 0x00000100ul 902 # define LCD_SRC_SEL 0x00000200ul 903 # define LCD_SRC_SEL_CRTC1 0x00000000ul 904 # define LCD_SRC_SEL_CRTC2 0x00000200ul 905 # define LCD_CRTC2_DISPLAY_DIS 0x00000400ul 906 # define LCD_GUI_ACTIVE 0x00000800ul /* XC/XL */ 907 # define LCD_MONDET_SENSE 0x01000000ul /* XC/XL */ 908 # define LCD_MONDET_INT_POL 0x02000000ul /* XC/XL */ 909 # define LCD_MONDET_INT_EN 0x04000000ul /* XC/XL */ 910 # define LCD_MONDET_INT 0x08000000ul /* XC/XL */ 911 # define LCD_MONDET_EN 0x10000000ul /* XC/XL */ 912 # define LCD_EN_PL 0x20000000ul /* XC/XL */ 913 #define HFB_PITCH_ADDR BlockIOTag(0x2au) /* LT */ 914 #define LCD_DATA BlockIOTag(0x2au) /* LTPro */ 915 #define EXT_MEM_CNTL BlockIOTag(0x2bu) /* VTB/GTB/LT */ 916 #define MEM_CNTL IOPortTag(0x14u, 0x2cu) 917 # define CTL_MEM_SIZE 0x00000007ul 918 /* ? 0x00000008ul */ 919 # define CTL_MEM_REFRESH 0x00000078ul /* VT/GT */ 920 # define CTL_MEM_SIZEB 0x0000000ful /* VTB/GTB/LT */ 921 # define CTL_MEM_RD_LATCH_EN 0x00000010ul 922 # define CTL_MEM_RD_LATCH_DLY 0x00000020ul 923 # define CTL_MEM_LATENCY 0x00000030ul /* VTB/GTB/LT */ 924 # define CTL_MEM_SD_LATCH_EN 0x00000040ul 925 # define CTL_MEM_SD_LATCH_DLY 0x00000080ul 926 # define CTL_MEM_LATCH 0x000000c0ul /* VTB/GTB/LT */ 927 # define CTL_MEM_WDOE_CNTL 0x000000c0ul /* XC/XL */ 928 # define CTL_MEM_FULL_PLS 0x00000100ul 929 # define CTL_MEM_CYC_LNTH_AUX 0x00000180ul /* VT/GT */ 930 # define CTL_MEM_TRP 0x00000300ul /* VTB/GTB/LT */ 931 # define CTL_MEM_CYC_LNTH 0x00000600ul 932 # define CTL_MEM_REFRESH_RATE 0x00001800ul /* 264xT */ 933 # define CTL_MEM_TRCD 0x00000c00ul /* VTB/GTB/LT */ 934 # define CTL_MEM_WR_RDY_SEL 0x00000800ul /* GX/CX */ 935 # define CTL_MEM_EXT_RMW_CYC_EN 0x00001000ul /* GX/CX */ 936 # define CTL_MEM_TCRD 0x00001000ul /* VTB/GTB/LT */ 937 # define CTL_MEM_DLL_RESET 0x00002000ul /* VT/GT */ 938 # define CTL_MEM_TR2W 0x00002000ul /* GTPro */ 939 # define CTL_MEM_ACTV_PRE 0x0000c000ul /* VT/GT */ 940 # define CTL_MEM_CAS_PHASE 0x00004000ul /* GTPro */ 941 # define CTL_MEM_OE_PULLBACK 0x00008000ul /* GTPro */ 942 # define CTL_MEM_TWR 0x0000c000ul /* XC/XL */ 943 # define CTL_MEM_BNDRY 0x00030000ul 944 # define CTL_MEM_BNDRY_0K 0x00000000ul 945 # define CTL_MEM_BNDRY_256K 0x00010000ul 946 # define CTL_MEM_BNDRY_512K 0x00020000ul 947 # define CTL_MEM_BNDRY_1024K 0x00030000ul 948 # define CTL_MEM_DLL_GAIN_CNTL 0x00030000ul /* VT/GT */ 949 # define CTL_MEM_BNDRY_EN 0x00040000ul 950 # define CTL_MEM_SDRAM_RESET 0x00040000ul /* VT/GT */ 951 # define CTL_MEM_TRAS 0x00070000ul /* VTB/GTB/LT */ 952 # define CTL_MEM_TILE_SELECT 0x00180000ul /* VT/GT */ 953 # define CTL_MEM_REFRESH_DIS 0x00080000ul /* VTB/GTB/LT */ 954 # define CTL_MEM_LOW_LATENCY_MODE 0x00200000ul /* VT/GT */ 955 # define CTL_MEM_CDE_PULLBACK 0x00400000ul /* VT/GT */ 956 # define CTL_MEM_REFRESH_RATE_B 0x00f00000ul /* VTB/GTB/LT */ 957 # define CTL_MEM_PIX_WIDTH 0x07000000ul 958 # define CTL_MEM_LOWER_APER_ENDIAN 0x03000000ul /* VTB/GTB/LT */ 959 # define CTL_MEM_OE_SELECT 0x18000000ul /* VT/GT */ 960 # define CTL_MEM_UPPER_APER_ENDIAN 0x0c000000ul /* VTB/GTB/LT */ 961 /* ? 0xe0000000ul */ 962 # define CTL_MEM_PAGE_SIZE 0x30000000ul /* VTB/GTB/LT */ 963 #define MEM_VGA_WP_SEL IOPortTag(0x15u, 0x2du) 964 # define MEM_VGA_WPS0 0x0000fffful 965 # define MEM_VGA_WPS1 0xffff0000ul 966 #define MEM_VGA_RP_SEL IOPortTag(0x16u, 0x2eu) 967 # define MEM_VGA_RPS0 0x0000fffful 968 # define MEM_VGA_RPS1 0xffff0000ul 969 #define LT_GIO BlockIOTag(0x2fu) /* LT */ 970 #define I2C_CNTL_1 BlockIOTag(0x2fu) /* GTPro */ 971 #define DAC_REGS IOPortTag(0x17u, 0x30u) /* 4 separate bytes */ 972 # define M64_DAC_WRITE (DAC_REGS + 0) 973 # define M64_DAC_DATA (DAC_REGS + 1) 974 # define M64_DAC_MASK (DAC_REGS + 2) 975 # define M64_DAC_READ (DAC_REGS + 3) 976 #define DAC_CNTL IOPortTag(0x18u, 0x31u) 977 # define DAC_EXT_SEL 0x00000003ul 978 # define DAC_EXT_SEL_RS2 0x00000001ul 979 # define DAC_EXT_SEL_RS3 0x00000002ul 980 # define DAC_RANGE_CTL 0x00000003ul /* VTB/GTB/LT */ 981 # define DAC_BLANKING 0x00000004ul /* 264xT */ 982 # define DAC_CMP_DIS 0x00000008ul /* 264xT */ 983 # define DAC1_CLK_SEL 0x00000010ul /* LTPro */ 984 # define DAC_PALETTE_ACCESS_CNTL 0x00000020ul /* LTPro */ 985 # define DAC_PALETTE2_SNOOP_EN 0x00000040ul /* LTPro */ 986 # define DAC_CMP_OUTPUT 0x00000080ul /* 264xT */ 987 # define DAC_8BIT_EN 0x00000100ul 988 # define DAC_PIX_DLY 0x00000600ul 989 # define DAC_DIRECT 0x00000400ul /* VTB/GTB/LT */ 990 # define DAC_BLANK_ADJ 0x00001800ul 991 # define DAC_PAL_CLK_SEL 0x00000800ul /* VTB/GTB/LT */ 992 # define DAC_CRT_SENSE 0x00000800ul /* XC/XL */ 993 # define DAC_CRT_DETECTION_ON 0x00001000ul /* XC/XL */ 994 # define DAC_VGA_ADR_EN 0x00002000ul 995 # define DAC_FEA_CON_EN 0x00004000ul /* 264xT */ 996 # define DAC_PDMN 0x00008000ul /* 264xT */ 997 # define DAC_TYPE 0x00070000ul 998 /* ? 0x00f80000ul */ 999 # define DAC_MON_ID_STATE0 0x01000000ul /* GX-E+/CX */ 1000 # define DAC_GIO_STATE_1 0x01000000ul /* 264xT */ 1001 # define DAC_MON_ID_STATE1 0x02000000ul /* GX-E+/CX */ 1002 # define DAC_GIO_STATE_0 0x02000000ul /* 264xT */ 1003 # define DAC_MON_ID_STATE2 0x04000000ul /* GX-E+/CX */ 1004 # define DAC_GIO_STATE_4 0x04000000ul /* 264xT */ 1005 # define DAC_MON_ID_DIR0 0x08000000ul /* GX-E+/CX */ 1006 # define DAC_GIO_DIR_1 0x08000000ul /* 264xT */ 1007 # define DAC_MON_ID_DIR1 0x10000000ul /* GX-E+/CX */ 1008 # define DAC_GIO_DIR_0 0x10000000ul /* 264xT */ 1009 # define DAC_MON_ID_DIR2 0x20000000ul /* GX-E+/CX */ 1010 # define DAC_GIO_DIR_4 0x20000000ul /* 264xT */ 1011 # define DAC_MAN_CMP_STATE 0x40000000ul /* GX-E+ */ 1012 # define DAC_RW_WS 0x80000000ul /* VT/GT */ 1013 #define HORZ_STRETCHING BlockIOTag(0x32u) /* LT */ 1014 # define HORZ_STRETCH_BLEND 0x00000ffful 1015 # define HORZ_STRETCH_RATIO 0x0000fffful 1016 # define HORZ_STRETCH_LOOP 0x00070000ul 1017 # define HORZ_STRETCH_LOOP09 0x00000000ul 1018 # define HORZ_STRETCH_LOOP11 0x00010000ul 1019 # define HORZ_STRETCH_LOOP12 0x00020000ul 1020 # define HORZ_STRETCH_LOOP14 0x00030000ul 1021 # define HORZ_STRETCH_LOOP15 0x00040000ul 1022 /* ? 0x00050000ul */ 1023 /* ? 0x00060000ul */ 1024 /* ? 0x00070000ul */ 1025 /* ? 0x00080000ul */ 1026 # define HORZ_PANEL_SIZE 0x0ff00000ul /* XC/XL */ 1027 /* ? 0x10000000ul */ 1028 # define AUTO_HORZ_RATIO 0x20000000ul /* XC/XL */ 1029 # define HORZ_STRETCH_MODE 0x40000000ul 1030 # define HORZ_STRETCH_EN 0x80000000ul 1031 #define EXT_DAC_REGS BlockIOTag(0x32u) /* GTPro */ 1032 #define VERT_STRETCHING BlockIOTag(0x33u) /* LT */ 1033 # define VERT_STRETCH_RATIO0 0x000003fful 1034 # define VERT_STRETCH_RATIO1 0x000ffc00ul 1035 # define VERT_STRETCH_RATIO2 0x3ff00000ul 1036 # define VERT_STRETCH_USE0 0x40000000ul 1037 # define VERT_STRETCH_EN 0x80000000ul 1038 #define GEN_TEST_CNTL IOPortTag(0x19u, 0x34u) 1039 # define GEN_EE_DATA_OUT 0x00000001ul /* GX/CX */ 1040 # define GEN_GIO2_DATA_OUT 0x00000001ul /* 264xT */ 1041 # define GEN_EE_CLOCK 0x00000002ul /* GX/CX */ 1042 /* ? 0x00000002ul */ /* 264xT */ 1043 # define GEN_EE_CHIP_SEL 0x00000004ul /* GX/CX */ 1044 # define GEN_GIO3_DATA_OUT 0x00000004ul /* 264xT */ 1045 # define GEN_EE_DATA_IN 0x00000008ul /* GX/CX */ 1046 # define GEN_GIO2_DATA_IN 0x00000008ul /* 264xT */ 1047 # define GEN_EE_EN 0x00000010ul /* GX/CX */ 1048 # define GEN_GIO2_ENABLE 0x00000010ul /* 264xT */ 1049 # define GEN_ICON2_ENABLE 0x00000010ul /* XC/XL */ 1050 # define GEN_OVR_OUTPUT_EN 0x00000020ul /* GX/CX */ 1051 # define GEN_GIO2_WRITE 0x00000020ul /* 264xT */ 1052 # define GEN_CUR2_ENABLE 0x00000020ul /* XC/XL */ 1053 # define GEN_OVR_POLARITY 0x00000040ul /* GX/CX */ 1054 # define GEN_ICON_ENABLE 0x00000040ul /* XC/XL */ 1055 # define GEN_CUR_EN 0x00000080ul 1056 # define GEN_GUI_EN 0x00000100ul /* GX/CX */ 1057 # define GEN_GUI_RESETB 0x00000100ul /* 264xT */ 1058 # define GEN_BLOCK_WR_EN 0x00000200ul /* GX */ 1059 /* ? 0x00000200ul */ /* CX/264xT */ 1060 # define GEN_SOFT_RESET 0x00000200ul /* VTB/GTB/LT */ 1061 # define GEN_MEM_TRISTATE 0x00000400ul /* GTPro */ 1062 /* ? 0x00000800ul */ 1063 # define GEN_TEST_VECT_MODE 0x00003000ul /* VT/GT */ 1064 /* ? 0x0000c000ul */ 1065 # define GEN_TEST_FIFO_EN 0x00010000ul /* GX/CX */ 1066 # define GEN_TEST_GUI_REGS_EN 0x00020000ul /* GX/CX */ 1067 # define GEN_TEST_VECT_EN 0x00040000ul /* GX/CX */ 1068 # define GEN_TEST_CRC_STR 0x00080000ul /* GX-C/-D */ 1069 /* ? 0x00080000ul */ /* GX-E+/CX */ 1070 # define GEN_TEST_MODE_T 0x000f0000ul /* 264xT */ 1071 # define GEN_TEST_MODE 0x00700000ul /* GX/CX */ 1072 # define GEN_TEST_CNT_EN 0x00100000ul /* 264xT */ 1073 # define GEN_TEST_CRC_EN 0x00200000ul /* 264xT */ 1074 /* ? 0x00400000ul */ /* 264xT */ 1075 /* ? 0x00800000ul */ 1076 # define GEN_TEST_MEM_WR 0x01000000ul /* GX-C/-D */ 1077 # define GEN_TEST_MEM_STROBE 0x02000000ul /* GX-C/-D */ 1078 # define GEN_TEST_DST_SS_EN 0x04000000ul /* GX/CX */ 1079 # define GEN_TEST_DST_SS_STROBE 0x08000000ul /* GX/CX */ 1080 # define GEN_TEST_SRC_SS_EN 0x10000000ul /* GX/CX */ 1081 # define GEN_TEST_SRC_SS_STROBE 0x20000000ul /* GX/CX */ 1082 # define GEN_TEST_CNT_VALUE 0x3f000000ul /* 264xT */ 1083 # define GEN_TEST_CC_EN 0x40000000ul /* GX/CX */ 1084 # define GEN_TEST_CC_STROBE 0x80000000ul /* GX/CX */ 1085 /* ? 0xc0000000ul */ /* 264xT */ 1086 # define GEN_DEBUG_MODE 0xff000000ul /* VTB/GTB/LT */ 1087 # define GEN_DEBUG_MC_PARSER 0x2A000000ul /* Mobility pro */ 1088 # define GEN_DEBUG_IDCT_PARSER 0x2B000000ul /* Mobility pro */ 1089 # define GEN_DEBUG_MC_BUFFER 0x2C000000ul /* Mobility pro */ 1090 # define GEN_DEBUG_IDCT_BUFFER 0x2E000000ul /* Mobility pro */ 1091 # define GEN_DEBUG_IDCT1 0x90000000ul /* Mobility pro */ 1092 # define GEN_DEBUG_IDCT2 0x91000000ul /* Mobility pro */ 1093 # define GEN_DEBUG_IDCT3 0x92000000ul /* Mobility pro */ 1094 #define LCD_GEN_CTRL BlockIOTag(0x35u) /* LT */ 1095 # define CRT_ON 0x00000001ul 1096 # define LCD_ON 0x00000002ul 1097 # define HORZ_DIVBY2_EN 0x00000004ul 1098 # define DONT_DS_ICON 0x00000008ul 1099 # define LOCK_8DOT 0x00000010ul 1100 # define ICON_ENABLE 0x00000020ul 1101 # define DONT_SHADOW_VPAR 0x00000040ul 1102 # define V2CLK_PM_EN 0x00000080ul 1103 # define RST_FM 0x00000100ul 1104 # define DISABLE_PCLK_RESET 0x00000200ul /* XC/XL */ 1105 # define DIS_HOR_CRT_DIVBY2 0x00000400ul 1106 # define SCLK_SEL 0x00000800ul 1107 # define SCLK_DELAY 0x0000f000ul 1108 # define TVCLK_PM_EN 0x00010000ul 1109 # define VCLK_DAC_PM_EN 0x00020000ul 1110 # define VCLK_LCD_OFF 0x00040000ul 1111 # define SELECT_WAIT_4MS 0x00080000ul 1112 # define XTALIN_PM_EN 0x00080000ul /* XC/XL */ 1113 # define V2CLK_DAC_PM_EN 0x00100000ul 1114 # define LVDS_EN 0x00200000ul 1115 # define LVDS_PLL_EN 0x00400000ul 1116 # define LVDS_PLL_RESET 0x00800000ul 1117 # define LVDS_RESERVED_BITS 0x07000000ul 1118 # define CRTC_RW_SELECT 0x08000000ul /* LTPro */ 1119 # define USE_SHADOWED_VEND 0x10000000ul 1120 # define USE_SHADOWED_ROWCUR 0x20000000ul 1121 # define SHADOW_EN 0x40000000ul 1122 # define SHADOW_RW_EN 0x80000000ul 1123 #define CUSTOM_MACRO_CNTL BlockIOTag(0x35u) /* GTPro */ 1124 # define IDCT_FIFO_EXTENSE 0x00000001ul 1125 #define POWER_MANAGEMENT BlockIOTag(0x36u) /* LT */ 1126 # define PWR_MGT_ON 0x00000001ul 1127 # define PWR_MGT_MODE 0x00000006ul 1128 # define AUTO_PWRUP_EN 0x00000008ul 1129 # define ACTIVITY_PIN_ON 0x00000010ul 1130 # define STANDBY_POL 0x00000020ul 1131 # define SUSPEND_POL 0x00000040ul 1132 # define SELF_REFRESH 0x00000080ul 1133 # define ACTIVITY_PIN_EN 0x00000100ul 1134 # define KEYBD_SNOOP 0x00000200ul 1135 # define USE_F32KHZ 0x00000400ul /* LTPro */ 1136 # define DONT_USE_XTALIN 0x00000400ul /* XC/XL */ 1137 # define TRISTATE_MEM_EN 0x00000800ul /* LTPro */ 1138 # define LCDENG_TEST_MODE 0x0000f000ul 1139 # define STANDBY_COUNT 0x000f0000ul 1140 # define SUSPEND_COUNT 0x00f00000ul 1141 # define BAISON 0x01000000ul 1142 # define BLON 0x02000000ul 1143 # define DIGON 0x04000000ul 1144 # define PM_D3_SUPPORT_ENABLE 0x08000000ul /* XC/XL */ 1145 # define STANDBY_NOW 0x10000000ul 1146 # define SUSPEND_NOW 0x20000000ul 1147 # define PWR_MGT_STATUS 0xc0000000ul 1148 #define CONFIG_CNTL IOPortTag(0x1au, 0x37u) 1149 # define CFG_MEM_AP_SIZE 0x00000003ul 1150 # define CFG_MEM_VGA_AP_EN 0x00000004ul 1151 /* ? 0x00000008ul */ 1152 # define CFG_MEM_AP_LOC 0x00003ff0ul 1153 /* ? 0x0000c000ul */ 1154 # define CFG_CARD_ID 0x00070000ul 1155 # define CFG_VGA_DIS 0x00080000ul 1156 /* ? 0x00f00000ul */ 1157 # define CFG_CDE_WINDOW 0x3f000000ul /* VT/GT */ 1158 /* ? 0xc0000000ul */ 1159 #define CONFIG_CHIP_ID IOPortTag(0x1bu, 0x38u) /* Read */ 1160 # define CFG_CHIP_TYPE0 0x000000fful 1161 # define CFG_CHIP_TYPE1 0x0000ff00ul 1162 # define CFG_CHIP_TYPE 0x0000fffful 1163 # define CFG_CHIP_CLASS 0x00ff0000ul 1164 # define CFG_CHIP_REV 0xff000000ul 1165 # define CFG_CHIP_VERSION 0x07000000ul /* 264xT */ 1166 # define CFG_CHIP_FOUNDRY 0x38000000ul /* 264xT */ 1167 # define CFG_CHIP_REVISION 0xc0000000ul /* 264xT */ 1168 #define CONFIG_STATUS64_0 IOPortTag(0x1cu, 0x39u) /* Read (R/W (264xT)) */ 1169 # define CFG_BUS_TYPE 0x00000007ul /* GX/CX */ 1170 # define CFG_MEM_TYPE_T 0x00000007ul /* 264xT */ 1171 # define CFG_MEM_TYPE 0x00000038ul /* GX/CX */ 1172 # define CFG_DUAL_CAS_EN_T 0x00000008ul /* 264xT */ 1173 # define CFG_ROM_128K_EN 0x00000008ul /* VTB/GTB/LT */ 1174 # define CFG_ROM_REMAP 0x00000008ul /* GTPro */ 1175 # define CFG_VGA_EN_T 0x00000010ul /* VT/GT */ 1176 # define CFG_CLOCK_EN 0x00000020ul /* 264xT */ 1177 # define CFG_DUAL_CAS_EN 0x00000040ul /* GX/CX */ 1178 # define CFG_VMC_SENSE 0x00000040ul /* VT/GT */ 1179 # define CFG_SHARED_MEM_EN 0x00000040ul /* VTB/GTB/LT */ 1180 # define CFG_LOCAL_BUS_OPTION 0x00000180ul /* GX/CX */ 1181 # define CFG_VFC_SENSE 0x00000080ul /* VT/GT */ 1182 # define CFG_INIT_DAC_TYPE 0x00000e00ul /* GX/CX */ 1183 # define CFG_INIT_CARD_ID 0x00007000ul /* GX-C/-D */ 1184 # define CFG_BLK_WR_SIZE 0x00001000ul /* GX-E+ */ 1185 # define CFG_INT_QSF_EN 0x00002000ul /* GX-E+ */ 1186 /* ? 0x00004000ul */ /* GX-E+ */ 1187 /* ? 0x00007000ul */ /* CX */ 1188 # define CFG_TRI_BUF_DIS 0x00008000ul /* GX/CX */ 1189 # define CFG_BOARD_ID 0x0000ff00ul /* VT/GT */ 1190 # define CFG_EXT_RAM_ADDR 0x003f0000ul /* GX/CX */ 1191 # define CFG_PANEL_ID 0x001f0000ul /* LT */ 1192 # define CFG_MACROVISION_EN 0x00200000ul /* GTPro */ 1193 # define CFG_ROM_DIS 0x00400000ul /* GX/CX */ 1194 # define CFG_PCI33EN 0x00400000ul /* GTPro */ 1195 # define CFG_VGA_EN 0x00800000ul /* GX/CX */ 1196 # define CFG_FULLAGP 0x00800000ul /* GTPro */ 1197 # define CFG_ARITHMOS_ENABLE 0x00800000ul /* XC/XL */ 1198 # define CFG_LOCAL_BUS_CFG 0x01000000ul /* GX/CX */ 1199 # define CFG_CHIP_EN 0x02000000ul /* GX/CX */ 1200 # define CFG_LOCAL_READ_DLY_DIS 0x04000000ul /* GX/CX */ 1201 # define CFG_ROM_OPTION 0x08000000ul /* GX/CX */ 1202 # define CFG_BUS_OPTION 0x10000000ul /* GX/CX */ 1203 # define CFG_LOCAL_DAC_WR_EN 0x20000000ul /* GX/CX */ 1204 # define CFG_VLB_RDY_DIS 0x40000000ul /* GX/CX */ 1205 # define CFG_AP_4GBYTE_DIS 0x80000000ul /* GX/CX */ 1206 #define CONFIG_STATUS64_1 IOPortTag(0x1du, 0x3au) /* Read */ 1207 # define CFG_PCI_DAC_CFG 0x00000001ul /* GX/CX */ 1208 /* ? 0x0000001eul */ /* GX/CX */ 1209 # define CFG_1C8_IO_SEL 0x00000020ul /* GX/CX */ 1210 /* ? 0xffffffc0ul */ /* GX/CX */ 1211 # define CRC_SIG 0xfffffffful /* 264xT */ 1212 #define MPP_CONFIG BlockIOTag(0x3bu) /* VTB/GTB/LT */ 1213 #define MPP_STROBE_CONFIG BlockIOTag(0x3cu) /* VTB/GTB/LT */ 1214 #define MPP_ADDR BlockIOTag(0x3du) /* VTB/GTB/LT */ 1215 #define MPP_DATA BlockIOTag(0x3eu) /* VTB/GTB/LT */ 1216 #define TVO_CNTL BlockIOTag(0x3fu) /* VTB/GTB/LT */ 1217 /* GP_IO IOPortTag(0x1eu, 0x1eu) */ /* See above */ 1218 /* CRTC_H_TOTAL_DISP IOPortTag(0x1fu, 0x00u) */ /* Duplicate */ 1219 #define DST_OFF_PITCH BlockIOTag(0x40u) 1220 # define DST_OFFSET 0x000ffffful 1221 /* ? 0x00300000ul */ 1222 # define DST_PITCH 0xffc00000ul 1223 #define DST_X BlockIOTag(0x41u) 1224 #define DST_Y BlockIOTag(0x42u) 1225 #define DST_Y_X BlockIOTag(0x43u) 1226 #define DST_WIDTH BlockIOTag(0x44u) 1227 #define DST_HEIGHT BlockIOTag(0x45u) 1228 #define DST_HEIGHT_WIDTH BlockIOTag(0x46u) 1229 #define DST_X_WIDTH BlockIOTag(0x47u) 1230 #define DST_BRES_LNTH BlockIOTag(0x48u) 1231 #define DST_BRES_ERR BlockIOTag(0x49u) 1232 #define DST_BRES_INC BlockIOTag(0x4au) 1233 #define DST_BRES_DEC BlockIOTag(0x4bu) 1234 #define DST_CNTL BlockIOTag(0x4cu) 1235 # define DST_X_DIR 0x00000001ul 1236 # define DST_Y_DIR 0x00000002ul 1237 # define DST_Y_MAJOR 0x00000004ul 1238 # define DST_X_TILE 0x00000008ul 1239 # define DST_Y_TILE 0x00000010ul 1240 # define DST_LAST_PEL 0x00000020ul 1241 # define DST_POLYGON_EN 0x00000040ul 1242 # define DST_24_ROT_EN 0x00000080ul 1243 # define DST_24_ROT 0x00000700ul 1244 # define DST_BRES_SIGN 0x00000800ul /* GX/CX */ 1245 # define DST_BRES_ZERO 0x00000800ul /* CT */ 1246 # define DST_POLYGON_RTEDGE_DIS 0x00001000ul /* CT */ 1247 # define TRAIL_X_DIR 0x00002000ul /* GT */ 1248 # define TRAP_FILL_DIR 0x00004000ul /* GT */ 1249 # define TRAIL_BRES_SIGN 0x00008000ul /* GT */ 1250 /* ? 0x00010000ul */ 1251 # define BRES_SIGN_AUTO 0x00020000ul /* GT */ 1252 /* ? 0x00040000ul */ 1253 # define ALPHA_OVERLAP_ENB 0x00080000ul /* GTPro */ 1254 # define SUB_PIX_ON 0x00100000ul /* GTPro */ 1255 /* ? 0xffe00000ul */ 1256 /* DST_Y_X BlockIOTag(0x4du) */ /* Duplicate */ 1257 #define TRAIL_BRES_ERR BlockIOTag(0x4eu) /* GT */ 1258 #define TRAIL_BRES_INC BlockIOTag(0x4fu) /* GT */ 1259 #define TRAIL_BRES_DEC BlockIOTag(0x50u) /* GT */ 1260 #define LEAD_BRES_LNTH BlockIOTag(0x51u) /* GT */ 1261 #define Z_OFF_PITCH BlockIOTag(0x52u) /* GT */ 1262 #define Z_CNTL BlockIOTag(0x53u) /* GT */ 1263 #define ALPHA_TST_CNTL BlockIOTag(0x54u) /* GTPro */ 1264 # define IDCT_EN 0x00008000UL 1265 /* ? BlockIOTag(0x55u) */ 1266 #define SECONDARY_STW_EXP BlockIOTag(0x56u) /* GTPro */ 1267 #define SECONDARY_S_X_INC BlockIOTag(0x57u) /* GTPro */ 1268 #define SECONDARY_S_Y_INC BlockIOTag(0x58u) /* GTPro */ 1269 #define SECONDARY_S_START BlockIOTag(0x59u) /* GTPro */ 1270 #define SECONDARY_W_X_INC BlockIOTag(0x5au) /* GTPro */ 1271 #define SECONDARY_W_Y_INC BlockIOTag(0x5bu) /* GTPro */ 1272 #define SECONDARY_W_START BlockIOTag(0x5cu) /* GTPro */ 1273 #define SECONDARY_T_X_INC BlockIOTag(0x5du) /* GTPro */ 1274 #define SECONDARY_T_Y_INC BlockIOTag(0x5eu) /* GTPro */ 1275 #define SECONDARY_T_START BlockIOTag(0x5fu) /* GTPro */ 1276 #define SRC_OFF_PITCH BlockIOTag(0x60u) 1277 # define SRC_OFFSET 0x000ffffful 1278 /* ? 0x00300000ul */ 1279 # define SRC_PITCH 0xffc00000ul 1280 #define SRC_X BlockIOTag(0x61u) 1281 #define SRC_Y BlockIOTag(0x62u) 1282 #define SRC_Y_X BlockIOTag(0x63u) 1283 #define SRC_WIDTH1 BlockIOTag(0x64u) 1284 #define SRC_HEIGHT1 BlockIOTag(0x65u) 1285 #define SRC_HEIGHT1_WIDTH1 BlockIOTag(0x66u) 1286 #define SRC_X_START BlockIOTag(0x67u) 1287 #define SRC_Y_START BlockIOTag(0x68u) 1288 #define SRC_Y_X_START BlockIOTag(0x69u) 1289 #define SRC_WIDTH2 BlockIOTag(0x6au) 1290 #define SRC_HEIGHT2 BlockIOTag(0x6bu) 1291 #define SRC_HEIGHT2_WIDTH2 BlockIOTag(0x6cu) 1292 #define SRC_CNTL BlockIOTag(0x6du) 1293 # define SRC_PATT_EN 0x00000001ul 1294 # define SRC_PATT_ROT_EN 0x00000002ul 1295 # define SRC_LINEAR_EN 0x00000004ul 1296 # define SRC_BYTE_ALIGN 0x00000008ul 1297 # define SRC_LINE_X_DIR 0x00000010ul 1298 # define SRC_8X8X8_BRUSH 0x00000020ul /* VTB/GTB */ 1299 # define FAST_FILL_EN 0x00000040ul /* VTB/GTB */ 1300 # define SRC_TRACK_DST 0x00000080ul /* VTB/GTB */ 1301 # define BUS_MASTER_EN 0x00000100ul /* VTB/GTB */ 1302 # define BUS_MASTER_SYNC 0x00000200ul /* VTB/GTB */ 1303 # define BUS_MASTER_OP 0x00000c00ul /* VTB/GTB */ 1304 # define BM_OP_FRAME_TO_SYSTEM (0 << 10) 1305 # define BM_OP_SYSTEM_TO_FRAME (1 << 10) 1306 # define BM_OP_REG_TO_SYSTEM (2 << 10) 1307 # define BM_OP_SYSTEM_TO_REG (3 << 10) 1308 # define SRC_8X8X8_BRUSH_LOADED 0x00001000ul /* VTB/GTB */ 1309 # define COLOR_REG_WRITE_EN 0x00002000ul /* VTB/GTB */ 1310 # define BLOCK_WRITE_EN 0x00004000ul /* VTB/GTB */ 1311 /* ? 0xffff8000ul */ 1312 /* ? BlockIOTag(0x6eu) */ 1313 /* ? BlockIOTag(0x6fu) */ 1314 #define SCALE_Y_OFF BlockIOTag(0x70u) /* GT */ 1315 #define SCALE_OFF BlockIOTag(0x70u) /* GTPro */ 1316 #define SECONDARY_SCALE_OFF BlockIOTag(0x70u) /* GTPro */ 1317 #define TEX_0_OFF BlockIOTag(0x70u) /* GT */ 1318 #define TEX_1_OFF BlockIOTag(0x71u) /* GT */ 1319 #define TEX_2_OFF BlockIOTag(0x72u) /* GT */ 1320 #define TEX_3_OFF BlockIOTag(0x73u) /* GT */ 1321 #define TEX_4_OFF BlockIOTag(0x74u) /* GT */ 1322 #define TEX_5_OFF BlockIOTag(0x75u) /* GT */ 1323 #define TEX_6_OFF BlockIOTag(0x76u) /* GT */ 1324 #define SCALE_WIDTH BlockIOTag(0x77u) /* GT */ 1325 #define TEX_7_OFF BlockIOTag(0x77u) /* GT */ 1326 #define SCALE_HEIGHT BlockIOTag(0x78u) /* GT */ 1327 #define TEX_8_OFF BlockIOTag(0x78u) /* GT */ 1328 #define TEX_9_OFF BlockIOTag(0x79u) /* GT */ 1329 #define TEX_10_OFF BlockIOTag(0x7au) /* GT */ 1330 #define S_Y_INC BlockIOTag(0x7bu) /* GT */ 1331 #define SCALE_Y_PITCH BlockIOTag(0x7bu) /* GT */ 1332 #define SCALE_X_INC BlockIOTag(0x7cu) /* GT */ 1333 #define RED_X_INC BlockIOTag(0x7cu) /* GT */ 1334 #define GREEN_X_INC BlockIOTag(0x7du) /* GT */ 1335 #define SCALE_Y_INC BlockIOTag(0x7du) /* GT */ 1336 #define SCALE_VACC BlockIOTag(0x7eu) /* GT */ 1337 #define SCALE_3D_CNTL BlockIOTag(0x7fu) /* GT */ 1338 # define SIGNED_DST_CLAMP 0x00008000UL /* MPEG's MC */ 1339 #define HOST_DATA_0 BlockIOTag(0x80u) 1340 #define HOST_DATA_1 BlockIOTag(0x81u) 1341 #define HOST_DATA_2 BlockIOTag(0x82u) 1342 #define HOST_DATA_3 BlockIOTag(0x83u) 1343 #define HOST_DATA_4 BlockIOTag(0x84u) 1344 #define HOST_DATA_5 BlockIOTag(0x85u) 1345 #define HOST_DATA_6 BlockIOTag(0x86u) 1346 #define HOST_DATA_7 BlockIOTag(0x87u) 1347 #define HOST_DATA_8 BlockIOTag(0x88u) 1348 #define HOST_DATA_9 BlockIOTag(0x89u) 1349 #define HOST_DATA_A BlockIOTag(0x8au) 1350 #define HOST_DATA_B BlockIOTag(0x8bu) 1351 #define HOST_DATA_C BlockIOTag(0x8cu) 1352 #define HOST_DATA_D BlockIOTag(0x8du) 1353 #define HOST_DATA_E BlockIOTag(0x8eu) 1354 #define HOST_DATA_F BlockIOTag(0x8fu) 1355 #define HOST_CNTL BlockIOTag(0x90u) 1356 #define HOST_BYTE_ALIGN 0x00000001ul 1357 #define HOST_BIG_ENDIAN_EN 0x00000002ul /* GX-E/CT */ 1358 /* ? 0xfffffffcul */ 1359 #define BM_HOSTDATA BlockIOTag(0x91u) /* VTB/GTB write-only */ 1360 #define BM_ADDR BlockIOTag(0x92u) /* VTB/GTB */ 1361 # define GUIREG_ADDR 0x000000FFUL 1362 # define GUIREG_COUNTER 0x003F0000UL 1363 # define IDCT_FLAGS 0x60000000UL 1364 # define IDCT_EOB 0x00000000UL 1365 # define IDCT_TRIPLETS 0x20000000UL /* run, level, level */ 1366 # define IDCT_AUTOINC 0x40000000UL 1367 # define IDCT_STREAM 0x80000000UL 1368 #define BM_DATA BlockIOTag(0x92u) /* VTB/GTB write-only */ 1369 #define BM_GUI_TABLE_CMD BlockIOTag(0x93u) /* GTPro */ 1370 # define CIRCULAR_BUF_SIZE_16KB (0 << 0) 1371 # define CIRCULAR_BUF_SIZE_32KB (1 << 0) 1372 # define CIRCULAR_BUF_SIZE_64KB (2 << 0) 1373 # define CIRCULAR_BUF_SIZE_128KB (3 << 0) 1374 # define LAST_DESCRIPTOR (1 << 31) 1375 /* ? BlockIOTag(0x94u) */ 1376 /* ? BlockIOTag(0x95u) */ 1377 /* ? BlockIOTag(0x96u) */ 1378 /* ? BlockIOTag(0x97u) */ 1379 /* ? BlockIOTag(0x98u) */ 1380 /* ? BlockIOTag(0x99u) */ 1381 /* ? BlockIOTag(0x9au) */ 1382 /* ? BlockIOTag(0x9bu) */ 1383 /* ? BlockIOTag(0x9cu) */ 1384 /* ? BlockIOTag(0x9du) */ 1385 /* ? BlockIOTag(0x9eu) */ 1386 /* ? BlockIOTag(0x9fu) */ 1387 #define PAT_REG0 BlockIOTag(0xa0u) 1388 #define PAT_REG1 BlockIOTag(0xa1u) 1389 #define PAT_CNTL BlockIOTag(0xa2u) 1390 # define PAT_MONO_EN 0x00000001ul 1391 # define PAT_CLR_4x2_EN 0x00000002ul 1392 # define PAT_CLR_8x1_EN 0x00000004ul 1393 /* ? 0xfffffff8ul */ 1394 /* ? BlockIOTag(0xa3u) */ 1395 /* ? BlockIOTag(0xa4u) */ 1396 /* ? BlockIOTag(0xa5u) */ 1397 /* ? BlockIOTag(0xa6u) */ 1398 /* ? BlockIOTag(0xa7u) */ 1399 #define SC_LEFT BlockIOTag(0xa8u) 1400 #define SC_RIGHT BlockIOTag(0xa9u) 1401 #define SC_LEFT_RIGHT BlockIOTag(0xaau) 1402 #define SC_TOP BlockIOTag(0xabu) 1403 #define SC_BOTTOM BlockIOTag(0xacu) 1404 #define SC_TOP_BOTTOM BlockIOTag(0xadu) 1405 #define USR1_DST_OFF_PITCH BlockIOTag(0xaeu) /* LTPro */ 1406 #define USR2_DST_OFF_PITCH BlockIOTag(0xafu) /* LTPro */ 1407 #define DP_BKGD_CLR BlockIOTag(0xb0u) 1408 #define DP_FRGD_CLR BlockIOTag(0xb1u) 1409 #define DP_WRITE_MASK BlockIOTag(0xb2u) 1410 #define DP_CHAIN_MASK BlockIOTag(0xb3u) 1411 # define DP_CHAIN_1BPP 0x00000000ul /* Irrelevant */ 1412 # define DP_CHAIN_4BPP 0x00008888ul 1413 # define DP_CHAIN_8BPP 0x00008080ul 1414 # define DP_CHAIN_8BPP_332 0x00009292ul 1415 # define DP_CHAIN_15BPP_1555 0x00004210ul 1416 # define DP_CHAIN_16BPP_565 0x00008410ul 1417 # define DP_CHAIN_24BPP_888 0x00008080ul 1418 # define DP_CHAIN_32BPP_8888 0x00008080ul 1419 /* ? 0xffff0000ul */ 1420 #define DP_PIX_WIDTH BlockIOTag(0xb4u) 1421 # define DP_DST_PIX_WIDTH 0x0000000ful 1422 # define COMPOSITE_PIX_WIDTH 0x000000f0ul /* GTPro */ 1423 # define DP_SRC_PIX_WIDTH 0x00000f00ul 1424 /* ? 0x00001000ul */ 1425 # define DP_HOST_TRIPLE_EN 0x00002000ul /* GT2c/VT4 */ 1426 # define DP_SRC_AUTONA_FIX_DIS 0x00004000ul /* GTB */ 1427 # define DP_FAST_SRCCOPY_DIS 0x00008000ul /* GTB */ 1428 # define DP_HOST_PIX_WIDTH 0x000f0000ul 1429 # define DP_CI4_RGB_INDEX 0x00f00000ul /* GTB */ 1430 # define DP_BYTE_PIX_ORDER 0x01000000ul 1431 # define DP_CONVERSION_TEMP 0x02000000ul /* GTB */ 1432 # define DP_CI4_RGB_LOW_NIBBLE 0x04000000ul /* GTB */ 1433 # define DP_C14_RGB_HIGH_NIBBLE 0x08000000ul /* GTB */ 1434 # define DP_SCALE_PIX_WIDTH 0xf0000000ul /* GTB */ 1435 #define DP_MIX BlockIOTag(0xb5u) 1436 # define BKGD_MIX_NOT_D (0 << 0) 1437 # define BKGD_MIX_ZERO (1 << 0) 1438 # define BKGD_MIX_ONE (2 << 0) 1439 # define BKGD_MIX_D (3 << 0) 1440 # define BKGD_MIX_NOT_S (4 << 0) 1441 # define BKGD_MIX_D_XOR_S (5 << 0) 1442 # define BKGD_MIX_NOT_D_XOR_S (6 << 0) 1443 # define BKGD_MIX_S (7 << 0) 1444 # define BKGD_MIX_NOT_D_OR_NOT_S (8 << 0) 1445 # define BKGD_MIX_D_OR_NOT_S (9 << 0) 1446 # define BKGD_MIX_NOT_D_OR_S (10 << 0) 1447 # define BKGD_MIX_D_OR_S (11 << 0) 1448 # define BKGD_MIX_D_AND_S (12 << 0) 1449 # define BKGD_MIX_NOT_D_AND_S (13 << 0) 1450 # define BKGD_MIX_D_AND_NOT_S (14 << 0) 1451 # define BKGD_MIX_NOT_D_AND_NOT_S (15 << 0) 1452 # define BKGD_MIX_D_PLUS_S_DIV2 (23 << 0) 1453 # define FRGD_MIX_NOT_D (0 << 16) 1454 # define FRGD_MIX_ZERO (1 << 16) 1455 # define FRGD_MIX_ONE (2 << 16) 1456 # define FRGD_MIX_D (3 << 16) 1457 # define FRGD_MIX_NOT_S (4 << 16) 1458 # define FRGD_MIX_D_XOR_S (5 << 16) 1459 # define FRGD_MIX_NOT_D_XOR_S (6 << 16) 1460 # define FRGD_MIX_S (7 << 16) 1461 # define FRGD_MIX_NOT_D_OR_NOT_S (8 << 16) 1462 # define FRGD_MIX_D_OR_NOT_S (9 << 16) 1463 # define FRGD_MIX_NOT_D_OR_S (10 << 16) 1464 # define FRGD_MIX_D_OR_S (11 << 16) 1465 # define FRGD_MIX_D_AND_S (12 << 16) 1466 # define FRGD_MIX_NOT_D_AND_S (13 << 16) 1467 # define FRGD_MIX_D_AND_NOT_S (14 << 16) 1468 # define FRGD_MIX_NOT_D_AND_NOT_S (15 << 16) 1469 # define FRGD_MIX_D_PLUS_S_DIV2 (23 << 16) 1470 #define DP_SRC BlockIOTag(0xb6u) 1471 # define BKGD_SRC_BKGD_CLR (0 << 0) 1472 # define BKGD_SRC_FRGD_CLR (1 << 0) 1473 # define BKGD_SRC_HOST (2 << 0) 1474 # define BKGD_SRC_BLIT (3 << 0) 1475 # define BKGD_SRC_PATTERN (4 << 0) 1476 # define BKGD_SRC_3D (5 << 0) 1477 # define FRGD_SRC_BKGD_CLR (0 << 8) 1478 # define FRGD_SRC_FRGD_CLR (1 << 8) 1479 # define FRGD_SRC_HOST (2 << 8) 1480 # define FRGD_SRC_BLIT (3 << 8) 1481 # define FRGD_SRC_PATTERN (4 << 8) 1482 # define FRGD_SRC_3D (5 << 8) 1483 # define MONO_SRC_ONE (0 << 16) 1484 # define MONO_SRC_PATTERN (1 << 16) 1485 # define MONO_SRC_HOST (2 << 16) 1486 # define MONO_SRC_BLIT (3 << 16) 1487 #define DP_FRGD_CLR_MIX BlockIOTag(0xb7u) /* VTB/GTB */ 1488 #define DP_FRGD_BKGD_CLR BlockIOTag(0xb8u) /* VTB/GTB */ 1489 /* ? BlockIOTag(0xb9u) */ 1490 #define DST_X_Y BlockIOTag(0xbau) /* VTB/GTB */ 1491 #define DST_WIDTH_HEIGHT BlockIOTag(0xbbu) /* VTB/GTB */ 1492 #define USR_DST_PITCH BlockIOTag(0xbcu) /* GTPro */ 1493 /* ? BlockIOTag(0xbdu) */ 1494 #define DP_SET_GUI_ENGINE2 BlockIOTag(0xbeu) /* GTPro */ 1495 #define DP_SET_GUI_ENGINE BlockIOTag(0xbfu) /* VTB/GTB */ 1496 #define CLR_CMP_CLR BlockIOTag(0xc0u) 1497 #define CLR_CMP_MSK BlockIOTag(0xc1u) 1498 #define CLR_CMP_CNTL BlockIOTag(0xc2u) 1499 # define CLR_CMP_FN 0x00000007ul 1500 # define CLR_CMP_FN_FALSE 0x00000000ul 1501 # define CLR_CMP_FN_TRUE 0x00000001ul 1502 /* ? 0x00000002ul */ 1503 /* ? 0x00000003ul */ 1504 # define CLR_CMP_FN_NOT_EQUAL 0x00000004ul 1505 # define CLR_CMP_FN_EQUAL 0x00000005ul 1506 /* ? 0x00000006ul */ 1507 /* ? 0x00000007ul */ 1508 /* ? 0x00fffff8ul */ 1509 # define CLR_CMP_SRC 0x03000000ul 1510 # define CLR_CMP_SRC_DST 0x00000000ul 1511 # define CLR_CMP_SRC_2D 0x01000000ul 1512 # define CLR_CMP_SRC_TEXEL 0x02000000ul 1513 /* ? 0x03000000ul */ 1514 /* ? 0xfc000000ul */ 1515 /* ? BlockIOTag(0xc3u) */ 1516 #define FIFO_STAT BlockIOTag(0xc4u) 1517 # define FIFO_STAT_BITS 0x0000fffful 1518 /* ? 0x7fff0000ul */ 1519 # define FIFO_ERR 0x80000000ul 1520 /* ? BlockIOTag(0xc5u) */ 1521 /* ? BlockIOTag(0xc6u) */ 1522 /* ? BlockIOTag(0xc7u) */ 1523 #define CONTEXT_MASK BlockIOTag(0xc8u) 1524 /* ? BlockIOTag(0xc9u) */ 1525 /* ? BlockIOTag(0xcau) */ 1526 #define CONTEXT_LOAD_CNTL BlockIOTag(0xcbu) 1527 # define CONTEXT_LOAD_PTR 0x00007ffful 1528 /* ? 0x00008000ul */ 1529 # define CONTEXT_LOAD_CMD 0x00030000ul 1530 # define CONTEXT_LOAD_NONE 0x00000000ul 1531 # define CONTEXT_LOAD_ONLY 0x00010000ul 1532 # define CONTEXT_LOAD_FILL 0x00020000ul 1533 # define CONTEXT_LOAD_LINE 0x00030000ul 1534 /* ? 0x7ffc0000ul */ 1535 #define CONTEXT_LOAD_DIS 0x80000000ul 1536 #define GUI_TRAJ_CNTL BlockIOTag(0xccu) 1537 /* ? BlockIOTag(0xcdu) */ 1538 #define GUI_STAT BlockIOTag(0xceu) 1539 #define GUI_ACTIVE 0x00000001ul 1540 /* ? 0x000000feul */ 1541 #define DSTX_LT_SCISSOR_LEFT 0x00000100ul 1542 #define DSTX_GT_SCISSOR_RIGHT 0x00000200ul 1543 #define DSTY_LT_SCISSOR_TOP 0x00000400ul 1544 #define DSTY_GT_SCISSOR_BOTTOM 0x00000800ul 1545 /* ? 0x0000f000ul */ 1546 #define GUI_FIFO 0x03ff0000ul /* VTB/GTB */ 1547 /* ? 0xfc000000ul */ 1548 /* ? BlockIOTag(0xcfu) */ 1549 #define S_X_INC2 BlockIOTag(0xd0u) /* GTB */ 1550 #define TEX_PALETTE_INDEX BlockIOTag(0xd0u) /* GTPro */ 1551 #define S_Y_INC2 BlockIOTag(0xd1u) /* GTB */ 1552 #define STW_EXP BlockIOTag(0xd1u) /* GTPro */ 1553 #define S_XY_INC2 BlockIOTag(0xd2u) /* GTB */ 1554 #define LOG_MAX_INC BlockIOTag(0xd2u) /* GTPro */ 1555 #define S_XINC_START BlockIOTag(0xd3u) /* GTB */ 1556 /* S_Y_INC BlockIOTag(0xd4u) */ /* Duplicate */ 1557 /* SCALE_Y_PITCH BlockIOTag(0xd4u) */ /* Duplicate */ 1558 #define S_START BlockIOTag(0xd5u) /* GTB */ 1559 #define T_X_INC2 BlockIOTag(0xd6u) /* GTB */ 1560 #define W_X_INC BlockIOTag(0xd6u) /* GTPro */ 1561 #define T_Y_INC2 BlockIOTag(0xd7u) /* GTB */ 1562 #define W_Y_INC BlockIOTag(0xd7u) /* GTPro */ 1563 #define T_XY_INC2 BlockIOTag(0xd8u) /* GTB */ 1564 #define W_START BlockIOTag(0xd8u) /* GTPro */ 1565 #define T_XINC_START BlockIOTag(0xd9u) /* GTB */ 1566 #define T_Y_INC BlockIOTag(0xdau) /* GTB */ 1567 #define SECONDARY_SCALE_PITCH BlockIOTag(0xdau) /* GTPro */ 1568 #define T_START BlockIOTag(0xdbu) /* GTB */ 1569 #define TEX_SIZE_PITCH BlockIOTag(0xdcu) /* GTB */ 1570 #define TEX_CNTL BlockIOTag(0xddu) /* GTPro */ 1571 #define SECONDARY_TEX_OFFSET BlockIOTag(0xdeu) /* GTPro */ 1572 #define TEX_PAL_WR BlockIOTag(0xdfu) /* GTB */ 1573 #define TEX_PALETTE BlockIOTag(0xdfu) /* GTPro */ 1574 #define SCALE_PITCH_BOTH BlockIOTag(0xe0u) /* GTPro */ 1575 #define SECONDARY_SCALE_OFF_ACC BlockIOTag(0xe1u) /* GTPro */ 1576 #define SCALE_OFF_ACC BlockIOTag(0xe2u) /* GTPro */ 1577 #define SCALE_DST_Y_X BlockIOTag(0xe3u) /* GTPro */ 1578 /* ? BlockIOTag(0xe4u) */ 1579 /* ? BlockIOTag(0xe5u) */ 1580 #define COMPOSITE_SHADOW_ID BlockIOTag(0xe6u) /* GTPro */ 1581 #define SECONDARY_SCALE_X_INC BlockIOTag(0xe7u) /* GTPro */ 1582 #define SPECULAR_RED_X_INC BlockIOTag(0xe7u) /* GTPro */ 1583 #define SPECULAR_RED_Y_INC BlockIOTag(0xe8u) /* GTPro */ 1584 #define SPECULAR_RED_START BlockIOTag(0xe9u) /* GTPro */ 1585 #define SECONDARY_SCALE_HACC BlockIOTag(0xe9u) /* GTPro */ 1586 #define SPECULAR_GREEN_X_INC BlockIOTag(0xeau) /* GTPro */ 1587 #define SPECULAR_GREEN_Y_INC BlockIOTag(0xebu) /* GTPro */ 1588 #define SPECULAR_GREEN_START BlockIOTag(0xecu) /* GTPro */ 1589 #define SPECULAR_BLUE_X_INC BlockIOTag(0xedu) /* GTPro */ 1590 #define SPECULAR_BLUE_Y_INC BlockIOTag(0xeeu) /* GTPro */ 1591 #define SPECULAR_BLUE_START BlockIOTag(0xefu) /* GTPro */ 1592 /* SCALE_X_INC BlockIOTag(0xf0u) */ /* Duplicate */ 1593 /* RED_X_INC BlockIOTag(0xf0u) */ /* Duplicate */ 1594 #define RED_Y_INC BlockIOTag(0xf1u) /* GTB */ 1595 #define SCALE_HACC BlockIOTag(0xf2u) /* GTB */ 1596 #define RED_START BlockIOTag(0xf2u) /* GTB */ 1597 /* GREEN_X_INC BlockIOTag(0xf3u) */ /* Duplicate */ 1598 /* SCALE_Y_INC BlockIOTag(0xf3u) */ /* Duplicate */ 1599 #define GREEN_Y_INC BlockIOTag(0xf4u) /* GTB */ 1600 #define SECONDARY_SCALE_Y_INC BlockIOTag(0xf4u) /* GTPro */ 1601 #define SECONDARY_SCALE_VACC BlockIOTag(0xf5u) /* GTPro */ 1602 #define GREEN_START BlockIOTag(0xf5u) /* GTB */ 1603 #define BLUE_X_INC BlockIOTag(0xf6u) /* GTB */ 1604 #define SCALE_XUV_INC BlockIOTag(0xf6u) /* GTB */ 1605 #define BLUE_Y_INC BlockIOTag(0xf7u) /* GTB */ 1606 #define BLUE_START BlockIOTag(0xf8u) /* GTB */ 1607 #define SCALE_UV_HACC BlockIOTag(0xf8u) /* GTB */ 1608 #define Z_X_INC BlockIOTag(0xf9u) /* GTB */ 1609 #define Z_Y_INC BlockIOTag(0xfau) /* GTB */ 1610 #define Z_START BlockIOTag(0xfbu) /* GTB */ 1611 #define ALPHA_FOG_X_INC BlockIOTag(0xfcu) /* GTB */ 1612 #define ALPHA_FOG_Y_INC BlockIOTag(0xfdu) /* GTB */ 1613 #define ALPHA_FOG_START BlockIOTag(0xfeu) /* GTB */ 1614 /* ? BlockIOTag(0xffu) */ 1615 #define OVERLAY_Y_X_START BlockIOTag(0x100u) 1616 # define OVERLAY_Y_START 0x000007FFUL 1617 # define OVERLAY_X_START 0x07FF0000UL 1618 # define OVERLAY_LOCK_START 0x80000000UL 1619 #define OVERLAY_Y_X_END BlockIOTag(0x101u) 1620 # define OVERLAY_Y_END 0x000007FFUL 1621 # define OVERLAY_X_END 0x07FF0000UL 1622 # define OVERLAY_LOCK_END 0x80000000UL 1623 #define OVERLAY_VIDEO_KEY_CLR BlockIOTag(0x102u) 1624 #define OVERLAY_VIDEO_KEY_MSK BlockIOTag(0x103u) 1625 #define OVERLAY_GRAPHICS_KEY_CLR BlockIOTag(0x104u) 1626 #define OVERLAY_GRAPHICS_KEY_MSK BlockIOTag(0x105u) 1627 #define OVERLAY_KEY_CNTL BlockIOTag(0x106u) 1628 # define VIDEO_KEY_FN_MASK 0x00000007L 1629 # define VIDEO_KEY_FN_FALSE 0x00000000L 1630 # define VIDEO_KEY_FN_TRUE 0x00000001L 1631 # define VIDEO_KEY_FN_NE 0x00000004L 1632 # define VIDEO_KEY_FN_EQ 0x00000005L // EQ and NE are exchanged relative to radeon 1633 # define GRAPHIC_KEY_FN_MASK 0x00000070L 1634 # define GRAPHIC_KEY_FN_FALSE 0x00000000L 1635 # define GRAPHIC_KEY_FN_TRUE 0x00000010L 1636 # define GRAPHIC_KEY_FN_NE 0x00000040L 1637 # define GRAPHIC_KEY_FN_EQ 0x00000050L // EQ and NE are exchanged relative to radeon 1638 # define CMP_MIX_MASK 0x00000100L 1639 # define CMP_MIX_OR 0x00000000L 1640 # define CMP_MIX_AND 0x00000100L 1641 /* ? BlockIOTag(0x107u) */ 1642 #define OVERLAY_SCALE_INC BlockIOTag(0x108u) 1643 #define OVERLAY_SCALE_CNTL BlockIOTag(0x109u) 1644 # define SCALE_PIX_EXPAND 0x00000001UL 1645 # define SCALE_Y2R_TEMP 0x00000002UL 1646 # define SCALE_HORZ_MODE 0x00000004UL 1647 # define SCALE_VERT_MODE 0x00000008UL 1648 # define SCALE_SIGNED_UV 0x00000010UL 1649 # define SCALE_GAMMA_SEL_MSK 0x00000060UL 1650 # define SCALE_GAMMA_SEL_BRIGHT 0x00000000UL 1651 # define SCALE_GAMMA_SEL_G22 0x00000020UL 1652 # define SCALE_GAMMA_SEL_G18 0x00000040UL 1653 # define SCALE_GAMMA_SEL_G14 0x00000060UL 1654 # define SCALE_SEL_DISP2 0x00000080UL /* pro only */ 1655 # define SCALE_BANDWIDTH 0x04000000UL 1656 # define SCALE_DIS_LIMIT 0x08000000UL 1657 # define SCALE_CLK_FORCE_ON 0x20000000UL 1658 # define OVERLAY_EN 0x40000000UL 1659 # define SCALE_EN 0x80000000UL 1660 #define SCALER_HEIGHT_WIDTH BlockIOTag(0x10au) 1661 #define OVERLAY_TEST BlockIOTag(0x10bu) 1662 # define SCALE_SUBPIC_ONLY 0x00000001UL 1663 # define SCALE_Y2R_DIS 0x00000002UL 1664 #define SCALER_THRESHOLD BlockIOTag(0x10cu) 1665 #define SCALER_BUF0_OFFSET BlockIOTag(0x10du) /* VTB/GTB */ 1666 #define SCALER_BUF1_OFFSET BlockIOTag(0x10eu) /* VTB/GTB */ 1667 #define SCALER_BUF_PITCH BlockIOTag(0x10fu) /* VTB/GTB */ 1668 #define CAPTURE_Y_X BlockIOTag(0x110u) 1669 #define CAPTURE_START_END BlockIOTag(0x110u) /* VTB/GTB */ 1670 #define CAPTURE_HEIGHT_WIDTH BlockIOTag(0x111u) 1671 #define CAPTURE_X_WIDTH BlockIOTag(0x111u) /* VTB/GTB */ 1672 #define VIDEO_FORMAT BlockIOTag(0x112u) 1673 # define VIDEO_IN_MSK 0x0000000FUL 1674 # define VIDEO_IN_VYUY422 0x0000000BUL 1675 # define VIDEO_IN_YVYU422 0x0000000CUL 1676 # define VIDEO_SIGNED_UV 0x00000010UL 1677 # define SCALER_IN_MSK 0x000F0000UL 1678 # define SCALER_IN_RGB15 0x00030000UL 1679 # define SCALER_IN_RGB16 0x00040000UL 1680 # define SCALER_IN_RGB32 0x00060000UL 1681 # define SCALER_IN_YUV9 0x00090000UL 1682 # define SCALER_IN_YUV12 0x000A0000UL 1683 # define SCALER_IN_VYUY422 0x000B0000UL 1684 # define SCALER_IN_YVYU422 0x000C0000UL 1685 # define HOST_BYTE_SHIFT_EN 0x10000000UL 1686 # define HOST_YUV_APER 0x20000000UL 1687 # define HOST_MEM_MODE_MSK 0xC0000000UL 1688 # define HOST_MEM_MODE_NORMAL 0x00000000UL 1689 # define HOST_MEM_MODE_Y 0x40000000UL 1690 # define HOST_MEM_MODE_U 0x80000000UL 1691 # define HOST_MEM_MODE_V 0xC0000000UL 1692 #define VIDEO_CONFIG BlockIOTag(0x113u) 1693 #define VBI_START_END BlockIOTag(0x113u) /* VTB/GTB */ 1694 #define CAPTURE_CONFIG BlockIOTag(0x114u) 1695 #define TRIG_CNTL BlockIOTag(0x115u) 1696 #define VIDEO_SYNC_TEST BlockIOTag(0x116u) 1697 #define OVERLAY_EXCLUSIVE_HORZ BlockIOTag(0x116u) /* VTB/GTB */ 1698 # define EXCLUSIVE_HORZ_START 0x000000FFUL 1699 # define EXCLUSIVE_HORZ_END 0x0000FF00UL 1700 # define EXCLUSIVE_BACK_PORSH 0x00FF0000UL 1701 # define EXCLUSIVE_EN 0x80000000UL 1702 #define EXT_CRTC_GEN_CNTL_R BlockIOTag(0x117u) /* VT-A4 (R) */ 1703 #define OVERLAY_EXCLUSIVE_VERT BlockIOTag(0x117u) /* VTB/GTB */ 1704 # define EXCLUSIVE_VERT_START 0x000007FFUL 1705 # define EXCLUSIVE_VERT_END 0x07FF0000UL 1706 #define VMC_CONFIG BlockIOTag(0x118u) 1707 #define VBI_WIDTH BlockIOTag(0x118u) /* VTB/GTB */ 1708 #define VMC_STATUS BlockIOTag(0x119u) 1709 #define CAPTURE_DEBUG BlockIOTag(0x119u) /* VTB/GTB */ 1710 #define VMC_CMD BlockIOTag(0x11au) 1711 #define VIDEO_SYNC_TEST_B BlockIOTag(0x11au) /* VTB/GTB */ 1712 # define TEST_CRTC_OVLSOF 0x00000001UL 1713 # define TEST_CRTC_VOVLEN 0x00000002UL 1714 # define TEST_VID_SOF 0x00000100UL 1715 # define TEST_VID_EOF 0x00000200UL 1716 # define TEST_VID_EOL 0x00000400UL 1717 # define TEST_VID_FIELD 0x00000800UL 1718 # define TEST_END_OF_VBI 0x00001000UL 1719 # define TEST_BUSMASTER_EOL 0x00002000UL 1720 # define TEST_SYNC_EN 0x80000000UL 1721 #define VMC_ARG0 BlockIOTag(0x11bu) 1722 #define VMC_ARG1 BlockIOTag(0x11cu) 1723 #define SNAPSHOT_VH_COUNTS BlockIOTag(0x11cu) /* GTPro */ 1724 #define VMC_SNOOP_ARG0 BlockIOTag(0x11du) 1725 #define SNAPSHOT_F_COUNT BlockIOTag(0x11du) /* GTPro */ 1726 #define VMC_SNOOP_ARG1 BlockIOTag(0x11eu) 1727 #define N_VIF_COUNT BlockIOTag(0x11eu) /* GTPro */ 1728 #define SNAPSHOT_VIF_COUNT BlockIOTag(0x11fu) /* GTPro */ 1729 #define BUF0_OFFSET BlockIOTag(0x120u) 1730 #define CAPTURE_BUF0_OFFSET BlockIOTag(0x120u) /* VTB/GTB */ 1731 #define CAPTURE_BUF1_OFFSET BlockIOTag(0x121u) /* VTB/GTB */ 1732 #define ONESHOT_BUF_OFFSET BlockIOTag(0x122u) /* VTB/GTB */ 1733 #define BUF0_PITCH BlockIOTag(0x123u) 1734 /* ? BlockIOTag(0x124u) */ 1735 /* ? BlockIOTag(0x125u) */ 1736 #define BUF1_OFFSET BlockIOTag(0x126u) 1737 /* ? BlockIOTag(0x127u) */ 1738 /* ? BlockIOTag(0x128u) */ 1739 #define BUF1_PITCH BlockIOTag(0x129u) 1740 /* ? BlockIOTag(0x12au) */ 1741 #define BUF0_CAP_ODD_OFFSET BlockIOTag(0x12bu) 1742 #define BUF1_CAP_ODD_OFFSET BlockIOTag(0x12cu) 1743 #define SNAPSHOT2_VH_COUNTS BlockIOTag(0x12cu) /* LTPro */ 1744 #define SNAPSHOT2_F_COUNT BlockIOTag(0x12du) /* LTPro */ 1745 #define N_VIF2_COUNT BlockIOTag(0x12eu) /* LTPro */ 1746 #define SNAPSHOT2_VIF_COUNT BlockIOTag(0x12fu) /* LTPro */ 1747 #define VMC_STRM_DATA_0 BlockIOTag(0x130u) 1748 /* MPP_CONFIG BlockIOTag(0x130u) */ /* See 0x3bu */ 1749 #define VMC_STRM_DATA_1 BlockIOTag(0x131u) 1750 /* MPP_STROBE_SEQ BlockIOTag(0x131u) */ /* See 0x3cu */ 1751 #define VMC_STRM_DATA_2 BlockIOTag(0x132u) 1752 /* MPP_ADDR BlockIOTag(0x132u) */ /* See 0x3du */ 1753 #define VMC_STRM_DATA_3 BlockIOTag(0x133u) 1754 /* MPP_DATA BlockIOTag(0x133u) */ /* See 0x3eu */ 1755 #define VMC_STRM_DATA_4 BlockIOTag(0x134u) 1756 #define VMC_STRM_DATA_5 BlockIOTag(0x135u) 1757 #define VMC_STRM_DATA_6 BlockIOTag(0x136u) 1758 #define VMC_STRM_DATA_7 BlockIOTag(0x137u) 1759 #define VMC_STRM_DATA_8 BlockIOTag(0x138u) 1760 #define VMC_STRM_DATA_9 BlockIOTag(0x139u) 1761 #define VMC_STRM_DATA_A BlockIOTag(0x13au) 1762 #define VMC_STRM_DATA_B BlockIOTag(0x13bu) 1763 #define VMC_STRM_DATA_C BlockIOTag(0x13cu) 1764 #define VMC_STRM_DATA_D BlockIOTag(0x13du) 1765 #define VMC_STRM_DATA_E BlockIOTag(0x13eu) 1766 #define VMC_STRM_DATA_F BlockIOTag(0x13fu) 1767 /* TVO_CNTL BlockIOTag(0x140u) */ /* See 0x3fu */ 1768 /* ? BlockIOTag(0x141u) */ 1769 /* ? BlockIOTag(0x142u) */ 1770 /* ? BlockIOTag(0x143u) */ 1771 /* ? BlockIOTag(0x144u) */ 1772 /* ? BlockIOTag(0x145u) */ 1773 /* ? BlockIOTag(0x146u) */ 1774 /* ? BlockIOTag(0x147u) */ 1775 /* ? BlockIOTag(0x148u) */ 1776 /* ? BlockIOTag(0x149u) */ 1777 /* ? BlockIOTag(0x14au) */ 1778 /* ? BlockIOTag(0x14bu) */ 1779 /* ? BlockIOTag(0x14cu) */ 1780 /* ? BlockIOTag(0x14du) */ 1781 /* ? BlockIOTag(0x14eu) */ 1782 /* ? BlockIOTag(0x14fu) */ 1783 /* ? BlockIOTag(0x150u) */ 1784 #define CRT_HORZ_VERT_LOAD BlockIOTag(0x151u) /* VTB/GTB */ 1785 #define AGP_BASE BlockIOTag(0x152u) /* GTPro */ 1786 #define AGP_CNTL BlockIOTag(0x153u) /* GTPro */ 1787 #define SCALER_COLOUR_CNTL BlockIOTag(0x154u) /* GTPro */ 1788 # define COLOUR_BRIGHTNESS 0x0000007FUL 1789 # define COLOUR_SATURATION_U 0x00001F00UL 1790 # define COLOUR_SATURATION_V 0x001F0000UL 1791 # define SCALER_VERT_ADJ_UV 0x0FE00000UL 1792 /*# define SCALER_VERT_ADJ_UV 0x0F000000UL (need testing) */ 1793 # define SCALER_HORZ_ADJ_UV 0xF0000000UL 1794 #define SCALER_H_COEFF0 BlockIOTag(0x155u) /* GTPro */ 1795 #define SCALER_H_COEFF1 BlockIOTag(0x156u) /* GTPro */ 1796 #define SCALER_H_COEFF2 BlockIOTag(0x157u) /* GTPro */ 1797 #define SCALER_H_COEFF3 BlockIOTag(0x158u) /* GTPro */ 1798 #define SCALER_H_COEFF4 BlockIOTag(0x159u) /* GTPro */ 1799 /* ? BlockIOTag(0x15au) */ 1800 /* ? BlockIOTag(0x15bu) */ 1801 #define GUI_CMDFIFO_DEBUG BlockIOTag(0x15cu) /* GT2c/VT4 */ 1802 #define GUI_CMDFIFO_DATA BlockIOTag(0x15du) /* GT2c/VT4 */ 1803 #define GUI_CNTL BlockIOTag(0x15eu) /* GT2c/VT4 */ 1804 # define CMDFIFO_SIZE_MASK 0x00000003ul 1805 # define CMDFIFO_SIZE_192 0x00000000ul 1806 # define CMDFIFO_SIZE_128 0x00000001ul 1807 # define CMDFIFO_SIZE_64 0x00000002ul 1808 /* ? 0x0000fffcul */ 1809 # define IDCT_PRSR_MODE 0x00010000ul /* XL/XC */ 1810 # define IDCT_BLOCK_GUI_INITIATOR 0x00020000ul /* XL/XC */ 1811 /* ? 0xfffc0000ul */ 1812 /* ? BlockIOTag(0x15fu) */ 1813 /* BUS MASTERING */ 1814 #define BM_FRAME_BUF_OFFSET BlockIOTag(0x160u) /* VTB/GTB read-only */ 1815 #define BM_SYSTEM_MEM_ADDR BlockIOTag(0x161u) /* VTB/GTB read-only */ 1816 #define BM_COMMAND BlockIOTag(0x162u) /* VTB/GTB read-only */ 1817 # define BM_CMD_BYTE_COUNT 0x00001FFFUL 1818 # define BM_CMD_HOLD_OFFSET 0x40000000UL 1819 # define BM_CMD_EOL 0x80000000UL 1820 #define BM_STATUS BlockIOTag(0x163u) /* VTB/GTB read-only */ 1821 /* ? BlockIOTag(0x164u) */ 1822 /* ? BlockIOTag(0x165u) */ 1823 /* ? BlockIOTag(0x166u) */ 1824 /* ? BlockIOTag(0x167u) */ 1825 /* ? BlockIOTag(0x168u) */ 1826 /* ? BlockIOTag(0x169u) */ 1827 /* ? BlockIOTag(0x16au) */ 1828 /* ? BlockIOTag(0x16bu) */ 1829 /* ? BlockIOTag(0x16cu) */ 1830 /* ? BlockIOTag(0x16du) */ 1831 #define BM_GUI_TABLE BlockIOTag(0x16eu) /* VTB/GTB */ 1832 #define BM_SYSTEM_TABLE BlockIOTag(0x16fu) /* VTB/GTB */ 1833 # define DMA_GUI_COMMAND__BYTE_COUNT_MASK 0x001ffff0 1834 # define DMA_GUI_COMMAND__HOLD_VIDEO_OFFSET 0x40000000 1835 # define DMA_GUI_COMMAND__EOL 0x80000000 1836 # define SYSTEM_TRIGGER_MASK 0x7 1837 # define SYSTEM_TRIGGER_SYSTEM_TO_VIDEO 0x0 1838 # define SYSTEM_TRIGGER_VIDEO_TO_SYSTEM 0x1 1839 # define SYSTEM_TRIGGER_VIDEO_TO_SYSTEM_AFTER_BUF0_READY 0x2 1840 # define SYSTEM_TRIGGER_VIDEO_TO_SYSTEM_AFTER_BUF1_READY 0x3 1841 # define SYSTEM_TRIGGER_VIDEO_TO_SYSTEM_AFTER_SNAPSHOT_READY 0x4 1842 # define SYSTEM_TRIGGER_SYSTEM_TO_MPP 0x5 1843 /* ? BlockIOTag(0x170u) */ 1844 /* ? BlockIOTag(0x171u) */ 1845 /* ? BlockIOTag(0x172u) */ 1846 /* ? BlockIOTag(0x173u) */ 1847 /* ? BlockIOTag(0x174u) */ 1848 #define SCALER_BUF0_OFFSET_V BlockIOTag(0x175u) /* GTPro */ 1849 #define SCALER_BUF0_OFFSET_U BlockIOTag(0x176u) /* GTPro */ 1850 #define SCALER_BUF1_OFFSET_V BlockIOTag(0x177u) /* GTPro */ 1851 #define SCALER_BUF1_OFFSET_U BlockIOTag(0x178u) /* GTPro */ 1852 /* ? BlockIOTag(0x179u) */ 1853 /* ? BlockIOTag(0x17au) */ 1854 /* ? BlockIOTag(0x17bu) */ 1855 /* ? BlockIOTag(0x17cu) */ 1856 /* ? BlockIOTag(0x17du) */ 1857 /* ? BlockIOTag(0x17eu) */ 1858 /* ? BlockIOTag(0x17fu) */ 1859 /* ? BlockIOTag(0x180u) */ 1860 /* ? BlockIOTag(0x181u) */ 1861 /* ? BlockIOTag(0x182u) */ 1862 /* ? BlockIOTag(0x183u) */ 1863 /* ? BlockIOTag(0x184u) */ 1864 /* ? BlockIOTag(0x185u) */ 1865 /* ? BlockIOTag(0x186u) */ 1866 /* ? BlockIOTag(0x187u) */ 1867 /* ? BlockIOTag(0x188u) */ 1868 /* ? BlockIOTag(0x189u) */ 1869 /* ? BlockIOTag(0x18au) */ 1870 /* ? BlockIOTag(0x18bu) */ 1871 /* ? BlockIOTag(0x18cu) */ 1872 /* ? BlockIOTag(0x18du) */ 1873 /* ? BlockIOTag(0x18eu) */ 1874 /* ? BlockIOTag(0x18fu) */ 1875 #define VERTEX_1_S BlockIOTag(0x190u) /* GTPro */ 1876 #define VERTEX_1_T BlockIOTag(0x191u) /* GTPro */ 1877 #define VERTEX_1_W BlockIOTag(0x192u) /* GTPro */ 1878 #define VERTEX_1_SPEC_ARGB BlockIOTag(0x193u) /* GTPro */ 1879 #define VERTEX_1_Z BlockIOTag(0x194u) /* GTPro */ 1880 #define VERTEX_1_ARGB BlockIOTag(0x195u) /* GTPro */ 1881 #define VERTEX_1_X_Y BlockIOTag(0x196u) /* GTPro */ 1882 #define ONE_OVER_AREA BlockIOTag(0x197u) /* GTPro */ 1883 #define VERTEX_2_S BlockIOTag(0x198u) /* GTPro */ 1884 #define VERTEX_2_T BlockIOTag(0x199u) /* GTPro */ 1885 #define VERTEX_2_W BlockIOTag(0x19au) /* GTPro */ 1886 #define VERTEX_2_SPEC_ARGB BlockIOTag(0x19bu) /* GTPro */ 1887 #define VERTEX_2_Z BlockIOTag(0x19cu) /* GTPro */ 1888 #define VERTEX_2_ARGB BlockIOTag(0x19du) /* GTPro */ 1889 #define VERTEX_2_X_Y BlockIOTag(0x19eu) /* GTPro */ 1890 /* ONE_OVER_AREA BlockIOTag(0x19fu) */ /* Duplicate */ 1891 #define VERTEX_3_S BlockIOTag(0x1a0u) /* GTPro */ 1892 #define VERTEX_3_T BlockIOTag(0x1a1u) /* GTPro */ 1893 #define VERTEX_3_W BlockIOTag(0x1a2u) /* GTPro */ 1894 #define VERTEX_3_SPEC_ARGB BlockIOTag(0x1a3u) /* GTPro */ 1895 #define VERTEX_3_Z BlockIOTag(0x1a4u) /* GTPro */ 1896 #define VERTEX_3_ARGB BlockIOTag(0x1a5u) /* GTPro */ 1897 #define VERTEX_3_X_Y BlockIOTag(0x1a6u) /* GTPro */ 1898 /* ONE_OVER_AREA BlockIOTag(0x1a7u) */ /* Duplicate */ 1899 #define VERTEX_3_SECONDARY_S BlockIOTag(0x1a8u) /* GTPro */ 1900 #define VERTEX_3_SECONDARY_T BlockIOTag(0x1a9u) /* GTPro */ 1901 #define VERTEX_3_SECONDARY_W BlockIOTag(0x1aau) /* GTPro */ 1902 /* VERTEX_1_S BlockIOTag(0x1abu) */ /* Duplicate */ 1903 /* VERTEX_1_T BlockIOTag(0x1acu) */ /* Duplicate */ 1904 /* VERTEX_1_W BlockIOTag(0x1adu) */ /* Duplicate */ 1905 /* VERTEX_2_S BlockIOTag(0x1aeu) */ /* Duplicate */ 1906 /* VERTEX_2_T BlockIOTag(0x1afu) */ /* Duplicate */ 1907 /* VERTEX_2_W BlockIOTag(0x1b0u) */ /* Duplicate */ 1908 /* VERTEX_3_S BlockIOTag(0x1b1u) */ /* Duplicate */ 1909 /* VERTEX_3_T BlockIOTag(0x1b2u) */ /* Duplicate */ 1910 /* VERTEX_3_W BlockIOTag(0x1b3u) */ /* Duplicate */ 1911 /* VERTEX_1_SPEC_ARGB BlockIOTag(0x1b4u) */ /* Duplicate */ 1912 /* VERTEX_2_SPEC_ARGB BlockIOTag(0x1b5u) */ /* Duplicate */ 1913 /* VERTEX_3_SPEC_ARGB BlockIOTag(0x1b6u) */ /* Duplicate */ 1914 /* VERTEX_1_Z BlockIOTag(0x1b7u) */ /* Duplicate */ 1915 /* VERTEX_2_Z BlockIOTag(0x1b8u) */ /* Duplicate */ 1916 /* VERTEX_3_Z BlockIOTag(0x1b9u) */ /* Duplicate */ 1917 /* VERTEX_1_ARGB BlockIOTag(0x1bau) */ /* Duplicate */ 1918 /* VERTEX_2_ARGB BlockIOTag(0x1bbu) */ /* Duplicate */ 1919 /* VERTEX_3_ARGB BlockIOTag(0x1bcu) */ /* Duplicate */ 1920 /* VERTEX_1_X_Y BlockIOTag(0x1bdu) */ /* Duplicate */ 1921 /* VERTEX_2_X_Y BlockIOTag(0x1beu) */ /* Duplicate */ 1922 /* VERTEX_3_X_Y BlockIOTag(0x1bfu) */ /* Duplicate */ 1923 #define ONE_OVER_AREA_UC BlockIOTag(0x1c0u) /* GTPro */ 1924 #define SETUP_CNTL BlockIOTag(0x1c1u) /* GTPro */ 1925 /* ? BlockIOTag(0x1c2u) */ 1926 /* ? BlockIOTag(0x1c3u) */ 1927 /* ? BlockIOTag(0x1c4u) */ 1928 /* ? BlockIOTag(0x1c5u) */ 1929 /* ? BlockIOTag(0x1c6u) */ 1930 /* ? BlockIOTag(0x1c7u) */ 1931 /* ? BlockIOTag(0x1c8u) */ 1932 /* ? BlockIOTag(0x1c9u) */ 1933 #define VERTEX_1_SECONDARY_S BlockIOTag(0x1cau) /* GTPro */ 1934 #define VERTEX_1_SECONDARY_T BlockIOTag(0x1cbu) /* GTPro */ 1935 #define VERTEX_1_SECONDARY_W BlockIOTag(0x1ccu) /* GTPro */ 1936 #define VERTEX_2_SECONDARY_S BlockIOTag(0x1cdu) /* GTPro */ 1937 #define VERTEX_2_SECONDARY_T BlockIOTag(0x1ceu) /* GTPro */ 1938 #define VERTEX_2_SECONDARY_W BlockIOTag(0x1cfu) /* GTPro */ 1939 /* IDCT and DVD's subpicture direct support (Rage Mobility only) */ 1940 #define SUBPIC_CNTL BlockIOTag(0x1d0u) 1941 # define SUBPIC_ON 0x00000001UL 1942 # define BTN_HLI_ON 0x00000002UL 1943 # define SP_HORZ_MODE 0x00000010UL 1944 # define SP_VERT_MODE 0x00000020UL 1945 # define SP_ODD_FIELD 0x00000100UL 1946 # define SP_BUF_SELECT 0x00000200UL 1947 # define SP_NO_R_EDGE_BLEND 0x00000400UL 1948 #define SUBPIC_DEFCOLON BlockIOTag(0x1d1u) 1949 # define BKGD_PIX_CON 0x0000000FUL 1950 # define PATT_PIX_CON 0x000000F0UL 1951 # define EMPH_PIX1_CON 0x00000F00UL 1952 # define EMPH_PIX2_CON 0x0000F000UL 1953 # define BKGD_PIX_CLR 0x000F0000UL 1954 # define PATT_PIX_CLR 0x00F00000UL 1955 # define EMPH_PIX1_CLR 0x0F000000UL 1956 # define EMPH_PIX2_CLR 0xF0000000UL 1957 /* ? BlockIOTag(0x1d2u) */ 1958 #define SUBPIC_Y_X_START BlockIOTag(0x1d3u) 1959 #define SUBPIC_Y_X_END BlockIOTag(0x1d4u) 1960 #define SUBPIC_V_INC BlockIOTag(0x1d5u) 1961 #define SUBPIC_H_INC BlockIOTag(0x1d6u) 1962 #define SUBPIC_BUF0_OFFSET BlockIOTag(0x1d7u) 1963 #define SUBPIC_BUF1_OFFSET BlockIOTag(0x1d8u) 1964 #define SUBPIC_LC0_OFFSET BlockIOTag(0x1d9u) 1965 #define SUBPIC_LC1_OFFSET BlockIOTag(0x1dau) 1966 #define SUBPIC_PITCH BlockIOTag(0x1dbu) 1967 # define SUBPIC_BUF_PITCH 0x00000FC0UL 1968 # define SUBPIC_LC_PITCH 0x0FC00000UL 1969 #define SUBPIC_BTN_HLI_COLCON BlockIOTag(0x1dcu) 1970 # define BTN_HLI_BKGD_PIX_CON 0x0000000FUL 1971 # define BTN_HLI_PATT_PIX_CON 0x000000F0UL 1972 # define BTN_HLI_EMPH_PIX1_CON 0x00000F00UL 1973 # define BTN_HLI_EMPH_PIX2_CON 0x0000F000UL 1974 # define BTN_HLI_BKGD_PIX_CLR 0x000F0000UL 1975 # define BTN_HLI_PATT_PIX_CLR 0x00F00000UL 1976 # define BTN_HLI_EMPH_PIX1_CLR 0x0F000000UL 1977 # define BTN_HLI_EMPH_PIX2_CLR 0xF0000000UL 1978 #define SUBPIC_BTN_Y_X_START BlockIOTag(0x1ddu) 1979 #define SUBPIC_BTN_Y_X_END BlockIOTag(0x1deu) 1980 #define SUBPIC_H_ACCUM_INIT BlockIOTag(0x1dfu) 1981 #define IDCT_RUNS BlockIOTag(0x1e0u) 1982 # define IDCT_RUNS_3 0x000000FFUL 1983 # define IDCT_RUNS_2 0x0000FF00UL 1984 # define IDCT_RUNS_1 0x00FF0000UL 1985 # define IDCT_RUNS_0 0xFF000000UL 1986 #define IDCT_LEVELS BlockIOTag(0x1e1u) 1987 # define IDCT_LEVELS_HI 0x0000FFFFUL 1988 # define IDCT_LEVELS_LO 0xFFFF0000UL 1989 #define IDCT_RESERVE_REGISTER1 BlockIOTag(0x1e2u) 1990 #define IDCT_RESERVE_REGISTER2 BlockIOTag(0x1e3u) 1991 /* ? BlockIOTag(0x1e4u) */ 1992 /* ? BlockIOTag(0x1e5u) */ 1993 #define SUBPIC_V_ACCUM_INIT BlockIOTag(0x1e6u) 1994 #define SUBPIC_PALETTE_INDEX BlockIOTag(0x1e7u) 1995 #define SUBPIC_PALETTE_DATA BlockIOTag(0x1e8u) 1996 /* ? BlockIOTag(0x1e9u) */ 1997 /* ? BlockIOTag(0x1eau) */ 1998 /* ? BlockIOTag(0x1ebu) */ 1999 /* ? BlockIOTag(0x1ecu) */ 2000 /* ? BlockIOTag(0x1edu) */ 2001 /* ? BlockIOTag(0x1eeu) */ 2002 #define IDCT_CONTROL BlockIOTag(0x1efu) 2003 # define IDCT_LUMA_RD_FORMAT_MSK 0x00000003UL 2004 # define IDCT_LUMA_RD_FORMAT_0123 0x00000000UL 2005 # define IDCT_LUMA_RD_FORMAT_0246 0x00000001UL 2006 # define IDCT_LUMA_RD_FORMAT_0819 0x00000002UL 2007 # define IDCT_CHROMA_RD_FMT_MSK 0x0000000CUL 2008 # define IDCT_CHROMA_RD_FMT_0123 0x00000000UL 2009 # define IDCT_CHROMA_RD_FMT_0246 0x00000004UL 2010 # define IDCT_CHROMA_RD_FMT_0819 0x00000008UL 2011 # define IDCT_CTL_SCAN_PATTERN 0x00000010UL 2012 # define IDCT_CTL_INTRA 0x00000020UL 2013 # define IDCT_CTL_FLUSH 0x00000040UL 2014 # define IDCT_CTL_PASSTHRU 0x00000080UL 2015 # define IDCT_CTL_SW_RESET 0x00000100UL 2016 # define IDCT_CONST_REQ 0x00000200UL 2017 # define IDCT_SCRAMBLE 0x00000400UL 2018 /* ? BlockIOTag(0x1f0u) */ 2019 /* ? BlockIOTag(0x1f1u) */ 2020 /* ? BlockIOTag(0x1f2u) */ 2021 /* ? BlockIOTag(0x1f3u) */ 2022 /* ? BlockIOTag(0x1f4u) */ 2023 /* ? BlockIOTag(0x1f5u) */ 2024 /* ? BlockIOTag(0x1f6u) */ 2025 /* ? BlockIOTag(0x1f7u) */ 2026 /* ? BlockIOTag(0x1f8u) */ 2027 /* ? BlockIOTag(0x1f9u) */ 2028 /* ? BlockIOTag(0x1fau) */ 2029 /* ? BlockIOTag(0x1fbu) */ 2030 /* ? BlockIOTag(0x1fcu) */ 2031 /* ? BlockIOTag(0x1fdu) */ 2032 /* ? BlockIOTag(0x1feu) */ 2033 /* ? BlockIOTag(0x1ffu) */ 2034 2035 /* Definitions for MEM_CNTL's CTL_MEM_?????_APER_ENDIAN fields */ 2036 #define CTL_MEM_APER_BYTE_ENDIAN 0x00u 2037 #define CTL_MEM_APER_WORD_ENDIAN 0x01u 2038 #define CTL_MEM_APER_LONG_ENDIAN 0x02u 2039 /* ? 0x03u */ 2040 2041 /* Definitions for an ICS2595's programme word */ 2042 #define ICS2595_CLOCK 0x000001f0ul 2043 #define ICS2595_FB_DIV 0x0001fe00ul /* Feedback divider */ 2044 #define ICS2595_POST_DIV 0x000c0000ul /* Post-divider */ 2045 #define ICS2595_STOP 0x00300000ul /* Stop bits */ 2046 #define ICS2595_TOGGLE (ICS2595_POST_DIV | ICS2595_STOP) 2047 2048 /* Definitions for internal PLL registers on a 264xT */ 2049 #define PLL_MPLL_CNTL 0x00u 2050 #define MPLL_PC_GAIN 0x07u 2051 #define MPLL_VC_GAIN 0x18u 2052 #define MPLL_D_CYC 0x60u 2053 #define MPLL_RANGE 0x80u 2054 #define VPLL_CNTL 0x01u 2055 #define VPLL_PC_GAIN 0x07u 2056 #define VPLL_VC_GAIN 0x18u 2057 #define VPLL_D_CYC 0x60u 2058 #define VPLL_RANGE 0x80u 2059 #define PLL_REF_DIV 0x02u 2060 #define PLL_GEN_CNTL 0x03u 2061 #define PLL_OVERRIDE 0x01u 2062 #define PLL_SLEEP 0x01u /* GTPro */ 2063 #define PLL_MCLK_RESET 0x02u 2064 #define PLL_OSC_EN 0x04u 2065 #define PLL_EXT_CLK_EN 0x08u 2066 #define PLL_MCLK_SRC_SEL 0x70u 2067 #define PLL_EXT_CLK_CNTL 0x80u /* CT/ET */ 2068 #define PLL_DLL_PWDN 0x80u /* VTB/GTB/LT */ 2069 #define PLL_MCLK_FB_DIV 0x04u 2070 #define PLL_VCLK_CNTL 0x05u 2071 #define PLL_VCLK_SRC_SEL 0x03u 2072 #define PLL_VCLK_RESET 0x04u 2073 #define PLL_VCLK_INVERT 0x08u 2074 #define PLL_ECP_DIV 0x30u /* VT/GT */ 2075 #define PLL_ERATE_GT_XRATE 0x40u /* VT/GT */ 2076 #define PLL_SCALER_LOCK_EN 0x80u /* VT/GT */ 2077 #define PLL_VCLK_POST_DIV 0x06u 2078 #define PLL_VCLK0_POST_DIV 0x03u 2079 #define PLL_VCLK1_POST_DIV 0x0cu 2080 #define PLL_VCLK2_POST_DIV 0x30u 2081 #define PLL_VCLK3_POST_DIV 0xc0u 2082 #define PLL_VCLK0_FB_DIV 0x07u 2083 #define PLL_VCLK1_FB_DIV 0x08u 2084 #define PLL_VCLK2_FB_DIV 0x09u 2085 #define PLL_VCLK3_FB_DIV 0x0au 2086 #define PLL_XCLK_CNTL 0x0bu /* VT/GT */ 2087 #define PLL_XCLK_MCLK_RATIO 0x03u 2088 #define PLL_XCLK_SRC_SEL 0x07u /* VTB/GTB/LT */ 2089 #define PLL_MFB_TIMES_4_2B 0x08u 2090 #define PLL_VCLK0_XDIV 0x10u 2091 #define PLL_VCLK1_XDIV 0x20u 2092 #define PLL_VCLK2_XDIV 0x40u 2093 #define PLL_VCLK3_XDIV 0x80u 2094 #define PLL_FCP_CNTL 0x0cu /* VT/GT */ 2095 #define PLL_FCP_POST_DIV 0x0fu 2096 #define PLL_FCP_SRC_SEL 0x70u 2097 #define PLL_DCLK_BY2_EN 0x80u 2098 #define PLL_DLL_CNTL 0x0cu /* VTB/GTB/LT */ 2099 #define PLL_DLL_REF_SRC 0x03u 2100 #define PLL_DLL_FB_SRC 0x0cu 2101 #define PLL_DLL_GAIN 0x30u 2102 #define PLL_DLL_RESET 0x40u 2103 #define PLL_DLL_HCLK_OUT_EN 0x80u 2104 #define PLL_VFC_CNTL 0x0du /* VT/GT */ 2105 #define PLL_DCLK_INVB 0x01u 2106 #define PLL_DCLKBY2_EN 0x02u 2107 #define PLL_VFC_2PHASE 0x04u 2108 #define PLL_VFC_DELAY 0x18u 2109 #define PLL_VFC_DCLKBY2_SHIFT 0x20u 2110 /* ? 0x40u */ 2111 #define PLL_TST_SRC_SEL_BIT5 0x80u /* VTB/GTB/LT */ 2112 #define PLL_TEST_CNTL 0x0eu 2113 #define PLL_TST_SRC_SEL 0x1fu 2114 #define PLL_TST_DIVIDERS 0x20u 2115 #define PLL_TST_MASK_READ 0x40u 2116 #define PLL_TST_ANALOG_MON_EN 0x80u 2117 #define PLL_TEST_COUNT 0x0fu 2118 #define PLL_LVDSPLL_CNTL0 0x10u /* LT */ 2119 #define PLL_FPDI_NS_TIMING 0x01u 2120 #define PLL_CURR_LEVEL 0x0eu 2121 #define PLL_LVDS_TEST_MODE 0xf0u 2122 #define PLL_LVDSPLL_CNTL1 0x11u /* LT */ 2123 #define PLL_LPPL_RANGE 0x01u 2124 #define PLL_LPLL_DUTY 0x06u 2125 #define PLL_LPLL_VC_GAIN 0x18u 2126 #define PLL_LPLL_CP_GAIN 0xe0u 2127 #define PLL_AGP1_CNTL 0x12u /* GTPro */ 2128 #define PLL_AGP2_CNTL 0x13u /* GTPro */ 2129 #define PLL_DLL2_CNTL 0x14u /* GTPro */ 2130 #define PLL_SCLK_FB_DIV 0x15u /* GTPro */ 2131 #define PLL_SPLL_CNTL1 0x16u /* GTPro */ 2132 #define PLL_SPLL_CNTL2 0x17u /* GTPro */ 2133 #define PLL_APLL_STRAPS 0x18u /* GTPro */ 2134 #define PLL_EXT_VPLL_CNTL 0x19u /* GTPro */ 2135 #define PLL_EXT_VPLL_REF_SRC 0x03u 2136 #define PLL_EXT_VPLL_EN 0x04u 2137 #define PLL_EXT_VPLL_VGA_EN 0x08u 2138 #define PLL_EXT_VPLL_INSYNC 0x10u 2139 /* ? 0x60u */ 2140 #define PLL_EXT_V2PLL_EN 0x80u 2141 #define PLL_EXT_VPLL_REF_DIV 0x1au /* GTPro */ 2142 #define PLL_EXT_VPLL_FB_DIV 0x1bu /* GTPro */ 2143 #define PLL_EXT_VPLL_MSB 0x1cu /* GTPro */ 2144 #define PLL_HTOTAL_CNTL 0x1du /* GTPro */ 2145 #define PLL_BYTE_CLK_CNTL 0x1eu /* GTPro */ 2146 #define PLL_TV_REF_DIV 0x1fu /* LTPro */ 2147 #define PLL_TV_FB_DIV 0x20u /* LTPro */ 2148 #define PLL_TV_CNTL 0x21u /* LTPro */ 2149 #define PLL_TV_GEN_CNTL 0x22u /* LTPro */ 2150 #define PLL_V2_CNTL 0x23u /* LTPro */ 2151 #define PLL_V2_GEN_CNTL 0x24u /* LTPro */ 2152 #define PLL_V2_REF_DIV 0x25u /* LTPro */ 2153 #define PLL_V2_FB_DIV 0x26u /* LTPro */ 2154 #define PLL_V2_MSB 0x27u /* LTPro */ 2155 #define PLL_HTOTAL2_CNTL 0x28u /* LTPro */ 2156 #define PLL_YCLK_CNTL 0x29u /* XC/XL */ 2157 #define PM_DYN_CLK_CNTL 0x2au /* XC/XL */ 2158 /* ? 0x2bu */ 2159 /* ? 0x2cu */ 2160 /* ? 0x2du */ 2161 /* ? 0x2eu */ 2162 /* ? 0x2fu */ 2163 /* ? 0x30u */ 2164 /* ? 0x31u */ 2165 /* ? 0x32u */ 2166 /* ? 0x33u */ 2167 /* ? 0x34u */ 2168 /* ? 0x35u */ 2169 /* ? 0x36u */ 2170 /* ? 0x37u */ 2171 /* ? 0x38u */ 2172 /* ? 0x39u */ 2173 /* ? 0x3au */ 2174 /* ? 0x3bu */ 2175 /* ? 0x3cu */ 2176 /* ? 0x3du */ 2177 /* ? 0x3eu */ 2178 /* ? 0x3fu */ 2179 2180 /* Definitions for an LTPro's 32-bit LCD registers */ 2181 #define LCD_CONFIG_PANEL 0x00u /* See LT's CONFIG_PANEL (0x1d) */ 2182 #define LCD_GEN_CNTL 0x01u /* See LT's LCD_GEN_CTRL (0x35) */ 2183 #define LCD_DSTN_CONTROL 0x02u /* See LT's DSTN_CONTROL (0x1f) */ 2184 #define LCD_HFB_PITCH_ADDR 0x03u /* See LT's HFB_PITCH_ADDR (0x2a) */ 2185 #define LCD_HORZ_STRETCHING 0x04u /* See LT's HORZ_STRETCHING (0x32) */ 2186 #define LCD_VERT_STRETCHING 0x05u /* See LT's VERT_STRETCHING (0x33) */ 2187 #define LCD_EXT_VERT_STRETCH 0x06u 2188 #define VERT_STRETCH_RATIO3 0x000003fful 2189 #define FORCE_DAC_DATA 0x000000fful 2190 #define FORCE_DAC_DATA_SEL 0x00000300ul 2191 #define VERT_STRETCH_MODE 0x00000400ul 2192 #define VERT_PANEL_SIZE 0x003ff800ul 2193 #define AUTO_VERT_RATIO 0x00400000ul 2194 #define USE_AUTO_FP_POS 0x00800000ul 2195 #define USE_AUTO_LCD_VSYNC 0x01000000ul 2196 /* ? 0xfe000000ul */ 2197 #define LCD_LT_GIO 0x07u /* See LT's LT_GIO (0x2f) */ 2198 #define LCD_POWER_MANAGEMENT 0x08u /* See LT's POWER_MANAGEMENT (0x36) */ 2199 #define LCD_ZVGPIO 0x09u 2200 #define LCD_ICON_CLR0 0x0au /* XC/XL */ 2201 #define LCD_ICON_CLR1 0x0bu /* XC/XL */ 2202 #define LCD_ICON_OFFSET 0x0cu /* XC/XL */ 2203 #define LCD_ICON_HORZ_VERT_POSN 0x0du /* XC/XL */ 2204 #define LCD_ICON_HORZ_VERT_OFF 0x0eu /* XC/XL */ 2205 #define LCD_ICON2_CLR0 0x0fu /* XC/XL */ 2206 #define LCD_ICON2_CLR1 0x10u /* XC/XL */ 2207 #define LCD_ICON2_OFFSET 0x11u /* XC/XL */ 2208 #define LCD_ICON2_HORZ_VERT_POSN 0x12u /* XC/XL */ 2209 #define LCD_ICON2_HORZ_VERT_OFF 0x13u /* XC/XL */ 2210 #define LCD_MISC_CNTL 0x14u /* XC/XL */ 2211 #define BL_MOD_LEVEL 0x000000fful 2212 #define BIAS_MOD_LEVEL 0x0000ff00ul 2213 #define BLMOD_EN 0x00010000ul 2214 #define BIASMOD_EN 0x00020000ul 2215 /* ? 0x00040000ul */ 2216 #define PWRSEQ_MODE 0x00080000ul 2217 #define APC_EN 0x00100000ul 2218 #define MONITOR_DET_EN 0x00200000ul 2219 #define FORCE_DAC_DATA_SEL_X 0x00c00000ul 2220 #define FORCE_DAC_DATA_X 0xff000000ul 2221 #define LCD_TMDS_CNTL 0x15u /* XC/XL */ 2222 #define LCD_TMDS_SYNC_CHAR_SETA 0x16u /* XC/XL */ 2223 #define LCD_TMDS_SYNC_CHAR_SETB 0x17u /* XC/XL */ 2224 #define LCD_TMDS_SRC 0x18u /* XC/XL */ 2225 #define LCD_PLTSTBLK_CNTL 0x19u /* XC/XL */ 2226 #define LCD_SYNC_GEN_CNTL 0x1au /* XC/XL */ 2227 #define LCD_PATTERN_GEN_SEED 0x1bu /* XC/XL */ 2228 #define LCD_APC_CNTL 0x1cu /* XC/XL */ 2229 #define LCD_POWER_MANAGEMENT_2 0x1du /* XC/XL */ 2230 #define LCD_XCLK_DISP_PM_EN 0x00000001ul 2231 #define LCD_XCLK_DISP2_PM_EN 0x00000002ul /* Mobility */ 2232 #define LCD_XCLK_VID_PM_EN 0x00000004ul 2233 #define LCD_XCLK_SCL_PM_EN 0x00000008ul 2234 #define LCD_XCLK_GUI_PM_EN 0x00000010ul 2235 #define LCD_XCLK_SUB_PM_EN 0x00000020ul 2236 /* ? 0x000000c0ul */ 2237 #define LCD_MCLK_PM_EN 0x00000100ul 2238 #define LCD_SS_EN 0x00000200ul 2239 #define LCD_BLON_DIGON_EN 0x00000400ul 2240 /* ? 0x00000800ul */ 2241 #define LCD_PM_DYN_XCLK_SYNC 0x00003000ul 2242 #define LCD_SEL_W4MS 0x00004000ul 2243 /* ? 0x00008000ul */ 2244 #define LCD_PM_DYN_XCLK_EN 0x00010000ul 2245 #define LCD_PM_XCLK_ALWAYS 0x00020000ul 2246 #define LCD_PM_DYN_XCLK_STATUS 0x00040000ul 2247 #define LCD_PCI_ACC_DIS 0x00080000ul 2248 #define LCD_PM_DYN_XCLK_DISP 0x00100000ul 2249 #define LCD_PM_DYN_XCLK_DISP2 0x00200000ul /* Mobility */ 2250 #define LCD_PM_DYN_XCLK_VID 0x00400000ul 2251 #define LCD_PM_DYN_XCLK_HFB 0x00800000ul 2252 #define LCD_PM_DYN_XCLK_SCL 0x01000000ul 2253 #define LCD_PM_DYN_XCLK_SUB 0x02000000ul 2254 #define LCD_PM_DYN_XCLK_GUI 0x04000000ul 2255 #define LCD_PM_DYN_XCLK_HOST 0x08000000ul 2256 /* ? 0xf0000000ul */ 2257 #define LCD_PRI_ERR_PATTERN 0x1eu /* XC/XL */ 2258 #define LCD_CUR_ERR_PATTERN 0x1fu /* XC/XL */ 2259 #define LCD_PLTSTBLK_RPT 0x20u /* XC/XL */ 2260 #define LCD_SYNC_RPT 0x21u /* XC/XL */ 2261 #define LCD_CRC_PATTERN_RPT 0x22u /* XC/XL */ 2262 #define LCD_PL_TRANSMITTER_CNTL 0x23u /* XC/XL */ 2263 #define LCD_PL_PLL_CNTL 0x24u /* XC/XL */ 2264 #define LCD_ALPHA_BLENDING 0x25u /* XC/XL */ 2265 #define LCD_PORTRAIT_GEN_CNTL 0x26u /* XC/XL */ 2266 #define LCD_APC_CTRL_IO 0x27u /* XC/XL */ 2267 #define LCD_TEST_IO 0x28u /* XC/XL */ 2268 /* ? 0x29u */ 2269 #define LCD_DP1_MEM_ACCESS 0x2au /* XC/XL */ 2270 #define LCD_DP0_MEM_ACCESS 0x2bu /* XC/XL */ 2271 #define LCD_DP0_DEBUG_A 0x2cu /* XC/XL */ 2272 #define LCD_DP0_DEBUG_B 0x2du /* XC/XL */ 2273 #define LCD_DP1_DEBUG_A 0x2eu /* XC/XL */ 2274 #define LCD_DP1_DEBUG_B 0x2fu /* XC/XL */ 2275 #define LCD_DPCTRL_DEBUG_A 0x30u /* XC/XL */ 2276 #define LCD_DPCTRL_DEBUG_B 0x31u /* XC/XL */ 2277 #define LCD_MEMBLK_DEBUG 0x32u /* XC/XL */ 2278 #define LCD_APC_LUT_AB 0x33u /* XC/XL */ 2279 #define LCD_APC_LUT_CD 0x34u /* XC/XL */ 2280 #define LCD_APC_LUT_EF 0x35u /* XC/XL */ 2281 #define LCD_APC_LUT_GH 0x36u /* XC/XL */ 2282 #define LCD_APC_LUT_IJ 0x37u /* XC/XL */ 2283 #define LCD_APC_LUT_KL 0x38u /* XC/XL */ 2284 #define LCD_APC_LUT_MN 0x39u /* XC/XL */ 2285 #define LCD_APC_LUT_OP 0x3au /* XC/XL */ 2286 /* ? 0x3bu */ 2287 /* ? 0x3cu */ 2288 /* ? 0x3du */ 2289 /* ? 0x3eu */ 2290 /* ? 0x3fu */ 2291 2292 /* Definitions for an LTPro's TV registers */ 2293 /* ? 0x00u */ 2294 /* ? 0x01u */ 2295 /* ? 0x02u */ 2296 /* ? 0x03u */ 2297 /* ? 0x04u */ 2298 /* ? 0x05u */ 2299 /* ? 0x06u */ 2300 /* ? 0x07u */ 2301 /* ? 0x08u */ 2302 /* ? 0x09u */ 2303 /* ? 0x0au */ 2304 /* ? 0x0bu */ 2305 /* ? 0x0cu */ 2306 /* ? 0x0du */ 2307 /* ? 0x0eu */ 2308 /* ? 0x0fu */ 2309 #define TV_MASTER_CNTL 0x10u 2310 /* ? 0x11u */ 2311 #define TV_RGB_CNTL 0x12u 2312 /* ? 0x13u */ 2313 #define TV_SYNC_CNTL 0x14u 2314 /* ? 0x15u */ 2315 /* ? 0x16u */ 2316 /* ? 0x17u */ 2317 /* ? 0x18u */ 2318 /* ? 0x19u */ 2319 /* ? 0x1au */ 2320 /* ? 0x1bu */ 2321 /* ? 0x1cu */ 2322 /* ? 0x1du */ 2323 /* ? 0x1eu */ 2324 /* ? 0x1fu */ 2325 #define TV_HTOTAL 0x20u 2326 #define TV_HDISP 0x21u 2327 #define TV_HSIZE 0x22u 2328 #define TV_HSTART 0x23u 2329 #define TV_HCOUNT 0x24u 2330 #define TV_VTOTAL 0x25u 2331 #define TV_VDISP 0x26u 2332 #define TV_VCOUNT 0x27u 2333 #define TV_FTOTAL 0x28u 2334 #define TV_FCOUNT 0x29u 2335 #define TV_FRESTART 0x2au 2336 #define TV_HRESTART 0x2bu 2337 #define TV_VRESTART 0x2cu 2338 /* ? 0x2du */ 2339 /* ? 0x2eu */ 2340 /* ? 0x2fu */ 2341 /* ? 0x30u */ 2342 /* ? 0x31u */ 2343 /* ? 0x32u */ 2344 /* ? 0x33u */ 2345 /* ? 0x34u */ 2346 /* ? 0x35u */ 2347 /* ? 0x36u */ 2348 /* ? 0x37u */ 2349 /* ? 0x38u */ 2350 /* ? 0x39u */ 2351 /* ? 0x3au */ 2352 /* ? 0x3bu */ 2353 /* ? 0x3cu */ 2354 /* ? 0x3du */ 2355 /* ? 0x3eu */ 2356 /* ? 0x3fu */ 2357 /* ? 0x40u */ 2358 /* ? 0x41u */ 2359 /* ? 0x42u */ 2360 /* ? 0x43u */ 2361 /* ? 0x44u */ 2362 /* ? 0x45u */ 2363 /* ? 0x46u */ 2364 /* ? 0x47u */ 2365 /* ? 0x48u */ 2366 /* ? 0x49u */ 2367 /* ? 0x4au */ 2368 /* ? 0x4bu */ 2369 /* ? 0x4cu */ 2370 /* ? 0x4du */ 2371 /* ? 0x4eu */ 2372 /* ? 0x4fu */ 2373 /* ? 0x50u */ 2374 /* ? 0x51u */ 2375 /* ? 0x52u */ 2376 /* ? 0x53u */ 2377 /* ? 0x54u */ 2378 /* ? 0x55u */ 2379 /* ? 0x56u */ 2380 /* ? 0x57u */ 2381 /* ? 0x58u */ 2382 /* ? 0x59u */ 2383 /* ? 0x5au */ 2384 /* ? 0x5bu */ 2385 /* ? 0x5cu */ 2386 /* ? 0x5du */ 2387 /* ? 0x5eu */ 2388 /* ? 0x5fu */ 2389 #define TV_HOST_READ_DATA 0x60u 2390 #define TV_HOST_WRITE_DATA 0x61u 2391 #define TV_HOST_RD_WT_CNTL 0x62u 2392 /* ? 0x63u */ 2393 /* ? 0x64u */ 2394 /* ? 0x65u */ 2395 /* ? 0x66u */ 2396 /* ? 0x67u */ 2397 /* ? 0x68u */ 2398 /* ? 0x69u */ 2399 /* ? 0x6au */ 2400 /* ? 0x6bu */ 2401 /* ? 0x6cu */ 2402 /* ? 0x6du */ 2403 /* ? 0x6eu */ 2404 /* ? 0x6fu */ 2405 #define TV_VSCALER_CNTL 0x70u 2406 #define TV_TIMING_CNTL 0x71u 2407 #define TV_GAMMA_CNTL 0x72u 2408 #define TV_Y_FALL_CNTL 0x73u 2409 #define TV_Y_RISE_CNTL 0x74u 2410 #define TV_Y_SAW_TOOTH_CNTL 0x75u 2411 /* ? 0x76u */ 2412 /* ? 0x77u */ 2413 /* ? 0x78u */ 2414 /* ? 0x79u */ 2415 /* ? 0x7au */ 2416 /* ? 0x7bu */ 2417 /* ? 0x7cu */ 2418 /* ? 0x7du */ 2419 /* ? 0x7eu */ 2420 /* ? 0x7fu */ 2421 #define TV_MODULATOR_CNTL1 0x80u 2422 #define TV_MODULATOR_CNTL2 0x81u 2423 /* ? 0x82u */ 2424 /* ? 0x83u */ 2425 /* ? 0x84u */ 2426 /* ? 0x85u */ 2427 /* ? 0x86u */ 2428 /* ? 0x87u */ 2429 /* ? 0x88u */ 2430 /* ? 0x89u */ 2431 /* ? 0x8au */ 2432 /* ? 0x8bu */ 2433 /* ? 0x8cu */ 2434 /* ? 0x8du */ 2435 /* ? 0x8eu */ 2436 /* ? 0x8fu */ 2437 #define TV_PRE_DAC_MUX_CNTL 0x90u 2438 /* ? 0x91u */ 2439 /* ? 0x92u */ 2440 /* ? 0x93u */ 2441 /* ? 0x94u */ 2442 /* ? 0x95u */ 2443 /* ? 0x96u */ 2444 /* ? 0x97u */ 2445 /* ? 0x98u */ 2446 /* ? 0x99u */ 2447 /* ? 0x9au */ 2448 /* ? 0x9bu */ 2449 /* ? 0x9cu */ 2450 /* ? 0x9du */ 2451 /* ? 0x9eu */ 2452 /* ? 0x9fu */ 2453 #define TV_DAC_CNTL 0xa0u 2454 /* ? 0xa1u */ 2455 /* ? 0xa2u */ 2456 /* ? 0xa3u */ 2457 /* ? 0xa4u */ 2458 /* ? 0xa5u */ 2459 /* ? 0xa6u */ 2460 /* ? 0xa7u */ 2461 /* ? 0xa8u */ 2462 /* ? 0xa9u */ 2463 /* ? 0xaau */ 2464 /* ? 0xabu */ 2465 /* ? 0xacu */ 2466 /* ? 0xadu */ 2467 /* ? 0xaeu */ 2468 /* ? 0xafu */ 2469 #define TV_CRC_CNTL 0xb0u 2470 #define TV_VIDEO_PORT_SIG 0xb1u 2471 /* ? 0xb2u */ 2472 /* ? 0xb3u */ 2473 /* ? 0xb4u */ 2474 /* ? 0xb5u */ 2475 /* ? 0xb6u */ 2476 /* ? 0xb7u */ 2477 #define TV_VBI_CC_CNTL 0xb8u 2478 #define TV_VBI_EDS_CNTL 0xb9u 2479 #define TV_VBI_20BIT_CNTL 0xbau 2480 /* ? 0xbbu */ 2481 /* ? 0xbcu */ 2482 #define TV_VBI_DTO_CNTL 0xbdu 2483 #define TV_VBI_LEVEL_CNTL 0xbeu 2484 /* ? 0xbfu */ 2485 #define TV_UV_ADR 0xc0u 2486 #define TV_FIFO_TEST_CNTL 0xc1u 2487 /* ? 0xc2u */ 2488 /* ? 0xc3u */ 2489 /* ? 0xc4u */ 2490 /* ? 0xc5u */ 2491 /* ? 0xc6u */ 2492 /* ? 0xc7u */ 2493 /* ? 0xc8u */ 2494 /* ? 0xc9u */ 2495 /* ? 0xcau */ 2496 /* ? 0xcbu */ 2497 /* ? 0xccu */ 2498 /* ? 0xcdu */ 2499 /* ? 0xceu */ 2500 /* ? 0xcfu */ 2501 /* ? 0xd0u */ 2502 /* ? 0xd1u */ 2503 /* ? 0xd2u */ 2504 /* ? 0xd3u */ 2505 /* ? 0xd4u */ 2506 /* ? 0xd5u */ 2507 /* ? 0xd6u */ 2508 /* ? 0xd7u */ 2509 /* ? 0xd8u */ 2510 /* ? 0xd9u */ 2511 /* ? 0xdau */ 2512 /* ? 0xdbu */ 2513 /* ? 0xdcu */ 2514 /* ? 0xddu */ 2515 /* ? 0xdeu */ 2516 /* ? 0xdfu */ 2517 /* ? 0xe0u */ 2518 /* ? 0xe1u */ 2519 /* ? 0xe2u */ 2520 /* ? 0xe3u */ 2521 /* ? 0xe4u */ 2522 /* ? 0xe5u */ 2523 /* ? 0xe6u */ 2524 /* ? 0xe7u */ 2525 /* ? 0xe8u */ 2526 /* ? 0xe9u */ 2527 /* ? 0xeau */ 2528 /* ? 0xebu */ 2529 /* ? 0xecu */ 2530 /* ? 0xedu */ 2531 /* ? 0xeeu */ 2532 /* ? 0xefu */ 2533 /* ? 0xf0u */ 2534 /* ? 0xf1u */ 2535 /* ? 0xf2u */ 2536 /* ? 0xf3u */ 2537 /* ? 0xf4u */ 2538 /* ? 0xf5u */ 2539 /* ? 0xf6u */ 2540 /* ? 0xf7u */ 2541 /* ? 0xf8u */ 2542 /* ? 0xf9u */ 2543 /* ? 0xfau */ 2544 /* ? 0xfbu */ 2545 /* ? 0xfcu */ 2546 /* ? 0xfdu */ 2547 /* ? 0xfeu */ 2548 /* ? 0xffu */ 2549 2550 /* Miscellaneous */ 2551 2552 /* Current X, Y & Dest X, Y mask */ 2553 #define COORD_MASK 0x07ffu 2554 2555 /* Pixel widths */ 2556 #define PIX_WIDTH_1BPP 0x00u 2557 #define PIX_WIDTH_4BPP 0x01u /* CRTC2: 8bpp */ 2558 #define PIX_WIDTH_8BPP 0x02u /* CRTC2: Undefined */ 2559 #define PIX_WIDTH_15BPP 0x03u 2560 #define PIX_WIDTH_16BPP 0x04u 2561 #define PIX_WIDTH_24BPP 0x05u 2562 #define PIX_WIDTH_32BPP 0x06u 2563 #define PIX_WIDTH_YUV422 0x07u /* CRTC2 only */ 2564 2565 /* Source definitions */ 2566 #define SRC_BKGD 0x00u 2567 #define SRC_FRGD 0x01u 2568 #define SRC_HOST 0x02u 2569 #define SRC_BLIT 0x03u 2570 #define SRC_PATTERN 0x04u 2571 #define SRC_SCALER_3D 0x05u 2572 /* ? 0x06u */ 2573 /* ? 0x07u */ 2574 2575 /* The Mixes */ 2576 #define MIX_MASK 0x001fu 2577 2578 #define MIX_NOT_DST 0x0000u 2579 #define MIX_0 0x0001u 2580 #define MIX_1 0x0002u 2581 #define MIX_DST 0x0003u 2582 #define MIX_NOT_SRC 0x0004u 2583 #define MIX_XOR 0x0005u 2584 #define MIX_XNOR 0x0006u 2585 #define MIX_SRC 0x0007u 2586 #define MIX_NAND 0x0008u 2587 #define MIX_NOT_SRC_OR_DST 0x0009u 2588 #define MIX_SRC_OR_NOT_DST 0x000au 2589 #define MIX_OR 0x000bu 2590 #define MIX_AND 0x000cu 2591 #define MIX_SRC_AND_NOT_DST 0x000du 2592 #define MIX_NOT_SRC_AND_DST 0x000eu 2593 #define MIX_NOR 0x000fu 2594 2595 #define MIX_MIN 0x0010u 2596 #define MIX_DST_MINUS_SRC 0x0011u 2597 #define MIX_SRC_MINUS_DST 0x0012u 2598 #define MIX_PLUS 0x0013u 2599 #define MIX_MAX 0x0014u 2600 #define MIX_HALF__DST_MINUS_SRC 0x0015u 2601 #define MIX_HALF__SRC_MINUS_DST 0x0016u 2602 #define MIX_AVERAGE 0x0017u 2603 #define MIX_DST_MINUS_SRC_SAT 0x0018u 2604 #define MIX_SRC_MINUS_DST_SAT 0x001au 2605 #define MIX_HALF__DST_MINUS_SRC_SAT 0x001cu 2606 #define MIX_HALF__SRC_MINUS_DST_SAT 0x001eu 2607 #define MIX_AVERAGE_SAT 0x001fu 2608 #define MIX_FN_PAINT MIX_SRC 2609 2610 2611 #endif 2612