1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 #ifndef _ASM_POWERPC_PROCESSOR_H
3 #define _ASM_POWERPC_PROCESSOR_H
4
5 /*
6 * Copyright (C) 2001 PPC 64 Team, IBM Corp
7 */
8
9 #include <vdso/processor.h>
10
11 #include <asm/reg.h>
12
13 #ifdef CONFIG_VSX
14 #define TS_FPRWIDTH 2
15
16 #ifdef __BIG_ENDIAN__
17 #define TS_FPROFFSET 0
18 #define TS_VSRLOWOFFSET 1
19 #else
20 #define TS_FPROFFSET 1
21 #define TS_VSRLOWOFFSET 0
22 #endif
23
24 #else
25 #define TS_FPRWIDTH 1
26 #define TS_FPROFFSET 0
27 #endif
28
29 #ifdef CONFIG_PPC64
30 /* Default SMT priority is set to 3. Use 11- 13bits to save priority. */
31 #define PPR_PRIORITY 3
32 #ifdef __ASSEMBLY__
33 #define DEFAULT_PPR (PPR_PRIORITY << 50)
34 #else
35 #define DEFAULT_PPR ((u64)PPR_PRIORITY << 50)
36 #endif /* __ASSEMBLY__ */
37 #endif /* CONFIG_PPC64 */
38
39 #ifndef __ASSEMBLY__
40 #include <linux/types.h>
41 #include <linux/thread_info.h>
42 #include <asm/ptrace.h>
43 #include <asm/hw_breakpoint.h>
44
45 /* We do _not_ want to define new machine types at all, those must die
46 * in favor of using the device-tree
47 * -- BenH.
48 */
49
50 /* PREP sub-platform types. Unused */
51 #define _PREP_Motorola 0x01 /* motorola prep */
52 #define _PREP_Firm 0x02 /* firmworks prep */
53 #define _PREP_IBM 0x00 /* ibm prep */
54 #define _PREP_Bull 0x03 /* bull prep */
55
56 /* CHRP sub-platform types. These are arbitrary */
57 #define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */
58 #define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */
59 #define _CHRP_Pegasos 0x06 /* Genesi/bplan's Pegasos and Pegasos2 */
60 #define _CHRP_briq 0x07 /* TotalImpact's briQ */
61
62 #if defined(__KERNEL__) && defined(CONFIG_PPC32)
63
64 extern int _chrp_type;
65
66 #endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */
67
68 #ifdef __KERNEL__
69
70 #ifdef CONFIG_PPC64
71 #include <asm/task_size_64.h>
72 #else
73 #include <asm/task_size_32.h>
74 #endif
75
76 struct task_struct;
77 void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp);
78 void release_thread(struct task_struct *);
79
80 #define TS_FPR(i) fp_state.fpr[i][TS_FPROFFSET]
81 #define TS_CKFPR(i) ckfp_state.fpr[i][TS_FPROFFSET]
82
83 /* FP and VSX 0-31 register set */
84 struct thread_fp_state {
85 u64 fpr[32][TS_FPRWIDTH] __attribute__((aligned(16)));
86 u64 fpscr; /* Floating point status */
87 };
88
89 /* Complete AltiVec register set including VSCR */
90 struct thread_vr_state {
91 vector128 vr[32] __attribute__((aligned(16)));
92 vector128 vscr __attribute__((aligned(16)));
93 };
94
95 struct debug_reg {
96 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
97 /*
98 * The following help to manage the use of Debug Control Registers
99 * om the BookE platforms.
100 */
101 uint32_t dbcr0;
102 uint32_t dbcr1;
103 #ifdef CONFIG_BOOKE
104 uint32_t dbcr2;
105 #endif
106 /*
107 * The stored value of the DBSR register will be the value at the
108 * last debug interrupt. This register can only be read from the
109 * user (will never be written to) and has value while helping to
110 * describe the reason for the last debug trap. Torez
111 */
112 uint32_t dbsr;
113 /*
114 * The following will contain addresses used by debug applications
115 * to help trace and trap on particular address locations.
116 * The bits in the Debug Control Registers above help define which
117 * of the following registers will contain valid data and/or addresses.
118 */
119 unsigned long iac1;
120 unsigned long iac2;
121 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
122 unsigned long iac3;
123 unsigned long iac4;
124 #endif
125 unsigned long dac1;
126 unsigned long dac2;
127 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
128 unsigned long dvc1;
129 unsigned long dvc2;
130 #endif
131 #endif
132 };
133
134 struct thread_struct {
135 unsigned long ksp; /* Kernel stack pointer */
136
137 #ifdef CONFIG_PPC64
138 unsigned long ksp_vsid;
139 #endif
140 struct pt_regs *regs; /* Pointer to saved register state */
141 #ifdef CONFIG_BOOKE
142 /* BookE base exception scratch space; align on cacheline */
143 unsigned long normsave[8] ____cacheline_aligned;
144 #endif
145 #ifdef CONFIG_PPC32
146 void *pgdir; /* root of page-table tree */
147 #ifdef CONFIG_PPC_RTAS
148 unsigned long rtas_sp; /* stack pointer for when in RTAS */
149 #endif
150 #if defined(CONFIG_PPC_BOOK3S_32) && defined(CONFIG_PPC_KUAP)
151 unsigned long kuap; /* opened segments for user access */
152 #endif
153 unsigned long srr0;
154 unsigned long srr1;
155 unsigned long dar;
156 unsigned long dsisr;
157 #ifdef CONFIG_PPC_BOOK3S_32
158 unsigned long r0, r3, r4, r5, r6, r8, r9, r11;
159 unsigned long lr, ctr;
160 #endif
161 #endif /* CONFIG_PPC32 */
162 /* Debug Registers */
163 struct debug_reg debug;
164 #ifdef CONFIG_PPC_FPU_REGS
165 struct thread_fp_state fp_state;
166 struct thread_fp_state *fp_save_area;
167 #endif
168 int fpexc_mode; /* floating-point exception mode */
169 unsigned int align_ctl; /* alignment handling control */
170 #ifdef CONFIG_HAVE_HW_BREAKPOINT
171 struct perf_event *ptrace_bps[HBP_NUM_MAX];
172 /*
173 * Helps identify source of single-step exception and subsequent
174 * hw-breakpoint enablement
175 */
176 struct perf_event *last_hit_ubp[HBP_NUM_MAX];
177 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
178 struct arch_hw_breakpoint hw_brk[HBP_NUM_MAX]; /* hardware breakpoint info */
179 unsigned long trap_nr; /* last trap # on this thread */
180 u8 load_slb; /* Ages out SLB preload cache entries */
181 u8 load_fp;
182 #ifdef CONFIG_ALTIVEC
183 u8 load_vec;
184 struct thread_vr_state vr_state;
185 struct thread_vr_state *vr_save_area;
186 unsigned long vrsave;
187 int used_vr; /* set if process has used altivec */
188 #endif /* CONFIG_ALTIVEC */
189 #ifdef CONFIG_VSX
190 /* VSR status */
191 int used_vsr; /* set if process has used VSX */
192 #endif /* CONFIG_VSX */
193 #ifdef CONFIG_SPE
194 unsigned long evr[32]; /* upper 32-bits of SPE regs */
195 u64 acc; /* Accumulator */
196 unsigned long spefscr; /* SPE & eFP status */
197 unsigned long spefscr_last; /* SPEFSCR value on last prctl
198 call or trap return */
199 int used_spe; /* set if process has used spe */
200 #endif /* CONFIG_SPE */
201 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
202 u8 load_tm;
203 u64 tm_tfhar; /* Transaction fail handler addr */
204 u64 tm_texasr; /* Transaction exception & summary */
205 u64 tm_tfiar; /* Transaction fail instr address reg */
206 struct pt_regs ckpt_regs; /* Checkpointed registers */
207
208 unsigned long tm_tar;
209 unsigned long tm_ppr;
210 unsigned long tm_dscr;
211 unsigned long tm_amr;
212
213 /*
214 * Checkpointed FP and VSX 0-31 register set.
215 *
216 * When a transaction is active/signalled/scheduled etc., *regs is the
217 * most recent set of/speculated GPRs with ckpt_regs being the older
218 * checkpointed regs to which we roll back if transaction aborts.
219 *
220 * These are analogous to how ckpt_regs and pt_regs work
221 */
222 struct thread_fp_state ckfp_state; /* Checkpointed FP state */
223 struct thread_vr_state ckvr_state; /* Checkpointed VR state */
224 unsigned long ckvrsave; /* Checkpointed VRSAVE */
225 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
226 #ifdef CONFIG_KVM_BOOK3S_32_HANDLER
227 void* kvm_shadow_vcpu; /* KVM internal data */
228 #endif /* CONFIG_KVM_BOOK3S_32_HANDLER */
229 #if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
230 struct kvm_vcpu *kvm_vcpu;
231 #endif
232 #ifdef CONFIG_PPC64
233 unsigned long dscr;
234 unsigned long fscr;
235 /*
236 * This member element dscr_inherit indicates that the process
237 * has explicitly attempted and changed the DSCR register value
238 * for itself. Hence kernel wont use the default CPU DSCR value
239 * contained in the PACA structure anymore during process context
240 * switch. Once this variable is set, this behaviour will also be
241 * inherited to all the children of this process from that point
242 * onwards.
243 */
244 int dscr_inherit;
245 unsigned long tidr;
246 #endif
247 #ifdef CONFIG_PPC_BOOK3S_64
248 unsigned long tar;
249 unsigned long ebbrr;
250 unsigned long ebbhr;
251 unsigned long bescr;
252 unsigned long siar;
253 unsigned long sdar;
254 unsigned long sier;
255 unsigned long mmcr2;
256 unsigned mmcr0;
257
258 unsigned used_ebb;
259 unsigned long mmcr3;
260 unsigned long sier2;
261 unsigned long sier3;
262
263 #endif
264 };
265
266 #define ARCH_MIN_TASKALIGN 16
267
268 #define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack)
269 #define INIT_SP_LIMIT ((unsigned long)&init_stack)
270
271 #ifdef CONFIG_SPE
272 #define SPEFSCR_INIT \
273 .spefscr = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE, \
274 .spefscr_last = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE,
275 #else
276 #define SPEFSCR_INIT
277 #endif
278
279 #ifdef CONFIG_PPC32
280 #define INIT_THREAD { \
281 .ksp = INIT_SP, \
282 .pgdir = swapper_pg_dir, \
283 .fpexc_mode = MSR_FE0 | MSR_FE1, \
284 SPEFSCR_INIT \
285 }
286 #else
287 #define INIT_THREAD { \
288 .ksp = INIT_SP, \
289 .fpexc_mode = 0, \
290 }
291 #endif
292
293 #define task_pt_regs(tsk) ((tsk)->thread.regs)
294
295 unsigned long get_wchan(struct task_struct *p);
296
297 #define KSTK_EIP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
298 #define KSTK_ESP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)
299
300 /* Get/set floating-point exception mode */
301 #define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr))
302 #define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val))
303
304 extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr);
305 extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val);
306
307 #define GET_ENDIAN(tsk, adr) get_endian((tsk), (adr))
308 #define SET_ENDIAN(tsk, val) set_endian((tsk), (val))
309
310 extern int get_endian(struct task_struct *tsk, unsigned long adr);
311 extern int set_endian(struct task_struct *tsk, unsigned int val);
312
313 #define GET_UNALIGN_CTL(tsk, adr) get_unalign_ctl((tsk), (adr))
314 #define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val))
315
316 extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr);
317 extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);
318
319 extern void load_fp_state(struct thread_fp_state *fp);
320 extern void store_fp_state(struct thread_fp_state *fp);
321 extern void load_vr_state(struct thread_vr_state *vr);
322 extern void store_vr_state(struct thread_vr_state *vr);
323
__unpack_fe01(unsigned long msr_bits)324 static inline unsigned int __unpack_fe01(unsigned long msr_bits)
325 {
326 return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8);
327 }
328
__pack_fe01(unsigned int fpmode)329 static inline unsigned long __pack_fe01(unsigned int fpmode)
330 {
331 return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1);
332 }
333
334 #ifdef CONFIG_PPC64
335
336 #define spin_begin() HMT_low()
337
338 #define spin_cpu_relax() barrier()
339
340 #define spin_end() HMT_medium()
341
342 #define spin_until_cond(cond) \
343 do { \
344 if (unlikely(!(cond))) { \
345 spin_begin(); \
346 do { \
347 spin_cpu_relax(); \
348 } while (!(cond)); \
349 spin_end(); \
350 } \
351 } while (0)
352
353 #endif
354
355 /* Check that a certain kernel stack pointer is valid in task_struct p */
356 int validate_sp(unsigned long sp, struct task_struct *p,
357 unsigned long nbytes);
358
359 /*
360 * Prefetch macros.
361 */
362 #define ARCH_HAS_PREFETCH
363 #define ARCH_HAS_PREFETCHW
364 #define ARCH_HAS_SPINLOCK_PREFETCH
365
prefetch(const void * x)366 static inline void prefetch(const void *x)
367 {
368 if (unlikely(!x))
369 return;
370
371 __asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
372 }
373
prefetchw(const void * x)374 static inline void prefetchw(const void *x)
375 {
376 if (unlikely(!x))
377 return;
378
379 __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
380 }
381
382 #define spin_lock_prefetch(x) prefetchw(x)
383
384 #define HAVE_ARCH_PICK_MMAP_LAYOUT
385
386 /* asm stubs */
387 extern unsigned long isa300_idle_stop_noloss(unsigned long psscr_val);
388 extern unsigned long isa300_idle_stop_mayloss(unsigned long psscr_val);
389 extern unsigned long isa206_idle_insn_mayloss(unsigned long type);
390 #ifdef CONFIG_PPC_970_NAP
391 extern void power4_idle_nap(void);
392 void power4_idle_nap_return(void);
393 #endif
394
395 extern unsigned long cpuidle_disable;
396 enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF};
397
398 extern int powersave_nap; /* set if nap mode can be used in idle loop */
399
400 extern void power7_idle_type(unsigned long type);
401 extern void arch300_idle_type(unsigned long stop_psscr_val,
402 unsigned long stop_psscr_mask);
403
404 extern int fix_alignment(struct pt_regs *);
405
406 #ifdef CONFIG_PPC64
407 /*
408 * We handle most unaligned accesses in hardware. On the other hand
409 * unaligned DMA can be very expensive on some ppc64 IO chips (it does
410 * powers of 2 writes until it reaches sufficient alignment).
411 *
412 * Based on this we disable the IP header alignment in network drivers.
413 */
414 #define NET_IP_ALIGN 0
415 #endif
416
417 int do_mathemu(struct pt_regs *regs);
418
419 #endif /* __KERNEL__ */
420 #endif /* __ASSEMBLY__ */
421 #endif /* _ASM_POWERPC_PROCESSOR_H */
422