1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
3 /*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30 #include <linux/acpi.h>
31 #include <linux/device.h>
32 #include <linux/oom.h>
33 #include <linux/module.h>
34 #include <linux/pci.h>
35 #include <linux/pm.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/pnp.h>
38 #include <linux/slab.h>
39 #include <linux/vga_switcheroo.h>
40 #include <linux/vt.h>
41
42 #include <drm/drm_atomic_helper.h>
43 #include <drm/drm_ioctl.h>
44 #include <drm/drm_irq.h>
45 #include <drm/drm_managed.h>
46 #include <drm/drm_probe_helper.h>
47
48 #include "display/intel_acpi.h"
49 #include "display/intel_bw.h"
50 #include "display/intel_cdclk.h"
51 #include "display/intel_csr.h"
52 #include "display/intel_display_types.h"
53 #include "display/intel_dp.h"
54 #include "display/intel_fbdev.h"
55 #include "display/intel_hotplug.h"
56 #include "display/intel_overlay.h"
57 #include "display/intel_pipe_crc.h"
58 #include "display/intel_pps.h"
59 #include "display/intel_sprite.h"
60 #include "display/intel_vga.h"
61
62 #include "gem/i915_gem_context.h"
63 #include "gem/i915_gem_ioctls.h"
64 #include "gem/i915_gem_mman.h"
65 #include "gem/i915_gem_pm.h"
66 #include "gt/intel_gt.h"
67 #include "gt/intel_gt_pm.h"
68 #include "gt/intel_rc6.h"
69
70 #include "i915_debugfs.h"
71 #include "i915_drv.h"
72 #include "i915_ioc32.h"
73 #include "i915_irq.h"
74 #include "i915_memcpy.h"
75 #include "i915_perf.h"
76 #include "i915_query.h"
77 #include "i915_suspend.h"
78 #include "i915_switcheroo.h"
79 #include "i915_sysfs.h"
80 #include "i915_trace.h"
81 #include "i915_vgpu.h"
82 #include "intel_dram.h"
83 #include "intel_gvt.h"
84 #include "intel_memory_region.h"
85 #include "intel_pm.h"
86 #include "intel_sideband.h"
87 #include "vlv_suspend.h"
88
89 static const struct drm_driver driver;
90
i915_get_bridge_dev(struct drm_i915_private * dev_priv)91 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
92 {
93 int domain = pci_domain_nr(to_pci_dev(dev_priv->drm.dev)->bus);
94
95 dev_priv->bridge_dev =
96 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
97 if (!dev_priv->bridge_dev) {
98 drm_err(&dev_priv->drm, "bridge device not found\n");
99 return -1;
100 }
101 return 0;
102 }
103
104 /* Allocate space for the MCH regs if needed, return nonzero on error */
105 static int
intel_alloc_mchbar_resource(struct drm_i915_private * dev_priv)106 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
107 {
108 int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
109 u32 temp_lo, temp_hi = 0;
110 u64 mchbar_addr;
111 int ret;
112
113 if (INTEL_GEN(dev_priv) >= 4)
114 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
115 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
116 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
117
118 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
119 #ifdef CONFIG_PNP
120 if (mchbar_addr &&
121 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
122 return 0;
123 #endif
124
125 /* Get some space for it */
126 dev_priv->mch_res.name = "i915 MCHBAR";
127 dev_priv->mch_res.flags = IORESOURCE_MEM;
128 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
129 &dev_priv->mch_res,
130 MCHBAR_SIZE, MCHBAR_SIZE,
131 PCIBIOS_MIN_MEM,
132 0, pcibios_align_resource,
133 dev_priv->bridge_dev);
134 if (ret) {
135 drm_dbg(&dev_priv->drm, "failed bus alloc: %d\n", ret);
136 dev_priv->mch_res.start = 0;
137 return ret;
138 }
139
140 if (INTEL_GEN(dev_priv) >= 4)
141 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
142 upper_32_bits(dev_priv->mch_res.start));
143
144 pci_write_config_dword(dev_priv->bridge_dev, reg,
145 lower_32_bits(dev_priv->mch_res.start));
146 return 0;
147 }
148
149 /* Setup MCHBAR if possible, return true if we should disable it again */
150 static void
intel_setup_mchbar(struct drm_i915_private * dev_priv)151 intel_setup_mchbar(struct drm_i915_private *dev_priv)
152 {
153 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
154 u32 temp;
155 bool enabled;
156
157 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
158 return;
159
160 dev_priv->mchbar_need_disable = false;
161
162 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
163 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
164 enabled = !!(temp & DEVEN_MCHBAR_EN);
165 } else {
166 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
167 enabled = temp & 1;
168 }
169
170 /* If it's already enabled, don't have to do anything */
171 if (enabled)
172 return;
173
174 if (intel_alloc_mchbar_resource(dev_priv))
175 return;
176
177 dev_priv->mchbar_need_disable = true;
178
179 /* Space is allocated or reserved, so enable it. */
180 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
181 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
182 temp | DEVEN_MCHBAR_EN);
183 } else {
184 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
185 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
186 }
187 }
188
189 static void
intel_teardown_mchbar(struct drm_i915_private * dev_priv)190 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
191 {
192 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
193
194 if (dev_priv->mchbar_need_disable) {
195 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
196 u32 deven_val;
197
198 pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
199 &deven_val);
200 deven_val &= ~DEVEN_MCHBAR_EN;
201 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
202 deven_val);
203 } else {
204 u32 mchbar_val;
205
206 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
207 &mchbar_val);
208 mchbar_val &= ~1;
209 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
210 mchbar_val);
211 }
212 }
213
214 if (dev_priv->mch_res.start)
215 release_resource(&dev_priv->mch_res);
216 }
217
i915_workqueues_init(struct drm_i915_private * dev_priv)218 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
219 {
220 /*
221 * The i915 workqueue is primarily used for batched retirement of
222 * requests (and thus managing bo) once the task has been completed
223 * by the GPU. i915_retire_requests() is called directly when we
224 * need high-priority retirement, such as waiting for an explicit
225 * bo.
226 *
227 * It is also used for periodic low-priority events, such as
228 * idle-timers and recording error state.
229 *
230 * All tasks on the workqueue are expected to acquire the dev mutex
231 * so there is no point in running more than one instance of the
232 * workqueue at any time. Use an ordered one.
233 */
234 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
235 if (dev_priv->wq == NULL)
236 goto out_err;
237
238 dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
239 if (dev_priv->hotplug.dp_wq == NULL)
240 goto out_free_wq;
241
242 return 0;
243
244 out_free_wq:
245 destroy_workqueue(dev_priv->wq);
246 out_err:
247 drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n");
248
249 return -ENOMEM;
250 }
251
i915_workqueues_cleanup(struct drm_i915_private * dev_priv)252 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
253 {
254 destroy_workqueue(dev_priv->hotplug.dp_wq);
255 destroy_workqueue(dev_priv->wq);
256 }
257
258 /*
259 * We don't keep the workarounds for pre-production hardware, so we expect our
260 * driver to fail on these machines in one way or another. A little warning on
261 * dmesg may help both the user and the bug triagers.
262 *
263 * Our policy for removing pre-production workarounds is to keep the
264 * current gen workarounds as a guide to the bring-up of the next gen
265 * (workarounds have a habit of persisting!). Anything older than that
266 * should be removed along with the complications they introduce.
267 */
intel_detect_preproduction_hw(struct drm_i915_private * dev_priv)268 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
269 {
270 bool pre = false;
271
272 pre |= IS_HSW_EARLY_SDV(dev_priv);
273 pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
274 pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
275 pre |= IS_KBL_GT_STEP(dev_priv, 0, STEP_A0);
276 pre |= IS_GLK_REVID(dev_priv, 0, GLK_REVID_A2);
277
278 if (pre) {
279 drm_err(&dev_priv->drm, "This is a pre-production stepping. "
280 "It may not be fully functional.\n");
281 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
282 }
283 }
284
sanitize_gpu(struct drm_i915_private * i915)285 static void sanitize_gpu(struct drm_i915_private *i915)
286 {
287 if (!INTEL_INFO(i915)->gpu_reset_clobbers_display)
288 __intel_gt_reset(&i915->gt, ALL_ENGINES);
289 }
290
291 /**
292 * i915_driver_early_probe - setup state not requiring device access
293 * @dev_priv: device private
294 *
295 * Initialize everything that is a "SW-only" state, that is state not
296 * requiring accessing the device or exposing the driver via kernel internal
297 * or userspace interfaces. Example steps belonging here: lock initialization,
298 * system memory allocation, setting up device specific attributes and
299 * function hooks not requiring accessing the device.
300 */
i915_driver_early_probe(struct drm_i915_private * dev_priv)301 static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
302 {
303 int ret = 0;
304
305 if (i915_inject_probe_failure(dev_priv))
306 return -ENODEV;
307
308 intel_device_info_subplatform_init(dev_priv);
309 intel_step_init(dev_priv);
310
311 intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug);
312 intel_uncore_init_early(&dev_priv->uncore, dev_priv);
313
314 spin_lock_init(&dev_priv->irq_lock);
315 spin_lock_init(&dev_priv->gpu_error.lock);
316 mutex_init(&dev_priv->backlight_lock);
317
318 mutex_init(&dev_priv->sb_lock);
319 cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE);
320
321 mutex_init(&dev_priv->av_mutex);
322 mutex_init(&dev_priv->wm.wm_mutex);
323 mutex_init(&dev_priv->pps_mutex);
324 mutex_init(&dev_priv->hdcp_comp_mutex);
325
326 i915_memcpy_init_early(dev_priv);
327 intel_runtime_pm_init_early(&dev_priv->runtime_pm);
328
329 ret = i915_workqueues_init(dev_priv);
330 if (ret < 0)
331 return ret;
332
333 ret = vlv_suspend_init(dev_priv);
334 if (ret < 0)
335 goto err_workqueues;
336
337 intel_wopcm_init_early(&dev_priv->wopcm);
338
339 intel_gt_init_early(&dev_priv->gt, dev_priv);
340
341 i915_gem_init_early(dev_priv);
342
343 /* This must be called before any calls to HAS_PCH_* */
344 intel_detect_pch(dev_priv);
345
346 intel_pm_setup(dev_priv);
347 ret = intel_power_domains_init(dev_priv);
348 if (ret < 0)
349 goto err_gem;
350 intel_irq_init(dev_priv);
351 intel_init_display_hooks(dev_priv);
352 intel_init_clock_gating_hooks(dev_priv);
353
354 intel_detect_preproduction_hw(dev_priv);
355
356 return 0;
357
358 err_gem:
359 i915_gem_cleanup_early(dev_priv);
360 intel_gt_driver_late_release(&dev_priv->gt);
361 vlv_suspend_cleanup(dev_priv);
362 err_workqueues:
363 i915_workqueues_cleanup(dev_priv);
364 return ret;
365 }
366
367 /**
368 * i915_driver_late_release - cleanup the setup done in
369 * i915_driver_early_probe()
370 * @dev_priv: device private
371 */
i915_driver_late_release(struct drm_i915_private * dev_priv)372 static void i915_driver_late_release(struct drm_i915_private *dev_priv)
373 {
374 intel_irq_fini(dev_priv);
375 intel_power_domains_cleanup(dev_priv);
376 i915_gem_cleanup_early(dev_priv);
377 intel_gt_driver_late_release(&dev_priv->gt);
378 vlv_suspend_cleanup(dev_priv);
379 i915_workqueues_cleanup(dev_priv);
380
381 cpu_latency_qos_remove_request(&dev_priv->sb_qos);
382 mutex_destroy(&dev_priv->sb_lock);
383
384 i915_params_free(&dev_priv->params);
385 }
386
387 /**
388 * i915_driver_mmio_probe - setup device MMIO
389 * @dev_priv: device private
390 *
391 * Setup minimal device state necessary for MMIO accesses later in the
392 * initialization sequence. The setup here should avoid any other device-wide
393 * side effects or exposing the driver via kernel internal or user space
394 * interfaces.
395 */
i915_driver_mmio_probe(struct drm_i915_private * dev_priv)396 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
397 {
398 int ret;
399
400 if (i915_inject_probe_failure(dev_priv))
401 return -ENODEV;
402
403 if (i915_get_bridge_dev(dev_priv))
404 return -EIO;
405
406 ret = intel_uncore_init_mmio(&dev_priv->uncore);
407 if (ret < 0)
408 goto err_bridge;
409
410 /* Try to make sure MCHBAR is enabled before poking at it */
411 intel_setup_mchbar(dev_priv);
412 intel_device_info_runtime_init(dev_priv);
413
414 ret = intel_gt_init_mmio(&dev_priv->gt);
415 if (ret)
416 goto err_uncore;
417
418 /* As early as possible, scrub existing GPU state before clobbering */
419 sanitize_gpu(dev_priv);
420
421 return 0;
422
423 err_uncore:
424 intel_teardown_mchbar(dev_priv);
425 intel_uncore_fini_mmio(&dev_priv->uncore);
426 err_bridge:
427 pci_dev_put(dev_priv->bridge_dev);
428
429 return ret;
430 }
431
432 /**
433 * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe()
434 * @dev_priv: device private
435 */
i915_driver_mmio_release(struct drm_i915_private * dev_priv)436 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
437 {
438 intel_teardown_mchbar(dev_priv);
439 intel_uncore_fini_mmio(&dev_priv->uncore);
440 pci_dev_put(dev_priv->bridge_dev);
441 }
442
intel_sanitize_options(struct drm_i915_private * dev_priv)443 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
444 {
445 intel_gvt_sanitize_options(dev_priv);
446 }
447
448 /**
449 * i915_set_dma_info - set all relevant PCI dma info as configured for the
450 * platform
451 * @i915: valid i915 instance
452 *
453 * Set the dma max segment size, device and coherent masks. The dma mask set
454 * needs to occur before i915_ggtt_probe_hw.
455 *
456 * A couple of platforms have special needs. Address them as well.
457 *
458 */
i915_set_dma_info(struct drm_i915_private * i915)459 static int i915_set_dma_info(struct drm_i915_private *i915)
460 {
461 unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size;
462 int ret;
463
464 GEM_BUG_ON(!mask_size);
465
466 /*
467 * We don't have a max segment size, so set it to the max so sg's
468 * debugging layer doesn't complain
469 */
470 dma_set_max_seg_size(i915->drm.dev, UINT_MAX);
471
472 ret = dma_set_mask(i915->drm.dev, DMA_BIT_MASK(mask_size));
473 if (ret)
474 goto mask_err;
475
476 /* overlay on gen2 is broken and can't address above 1G */
477 if (IS_GEN(i915, 2))
478 mask_size = 30;
479
480 /*
481 * 965GM sometimes incorrectly writes to hardware status page (HWS)
482 * using 32bit addressing, overwriting memory if HWS is located
483 * above 4GB.
484 *
485 * The documentation also mentions an issue with undefined
486 * behaviour if any general state is accessed within a page above 4GB,
487 * which also needs to be handled carefully.
488 */
489 if (IS_I965G(i915) || IS_I965GM(i915))
490 mask_size = 32;
491
492 ret = dma_set_coherent_mask(i915->drm.dev, DMA_BIT_MASK(mask_size));
493 if (ret)
494 goto mask_err;
495
496 return 0;
497
498 mask_err:
499 drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret);
500 return ret;
501 }
502
503 /**
504 * i915_driver_hw_probe - setup state requiring device access
505 * @dev_priv: device private
506 *
507 * Setup state that requires accessing the device, but doesn't require
508 * exposing the driver via kernel internal or userspace interfaces.
509 */
i915_driver_hw_probe(struct drm_i915_private * dev_priv)510 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
511 {
512 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
513 int ret;
514
515 if (i915_inject_probe_failure(dev_priv))
516 return -ENODEV;
517
518 if (HAS_PPGTT(dev_priv)) {
519 if (intel_vgpu_active(dev_priv) &&
520 !intel_vgpu_has_full_ppgtt(dev_priv)) {
521 i915_report_error(dev_priv,
522 "incompatible vGPU found, support for isolated ppGTT required\n");
523 return -ENXIO;
524 }
525 }
526
527 if (HAS_EXECLISTS(dev_priv)) {
528 /*
529 * Older GVT emulation depends upon intercepting CSB mmio,
530 * which we no longer use, preferring to use the HWSP cache
531 * instead.
532 */
533 if (intel_vgpu_active(dev_priv) &&
534 !intel_vgpu_has_hwsp_emulation(dev_priv)) {
535 i915_report_error(dev_priv,
536 "old vGPU host found, support for HWSP emulation required\n");
537 return -ENXIO;
538 }
539 }
540
541 intel_sanitize_options(dev_priv);
542
543 /* needs to be done before ggtt probe */
544 intel_dram_edram_detect(dev_priv);
545
546 ret = i915_set_dma_info(dev_priv);
547 if (ret)
548 return ret;
549
550 i915_perf_init(dev_priv);
551
552 ret = i915_ggtt_probe_hw(dev_priv);
553 if (ret)
554 goto err_perf;
555
556 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "inteldrmfb");
557 if (ret)
558 goto err_ggtt;
559
560 ret = i915_ggtt_init_hw(dev_priv);
561 if (ret)
562 goto err_ggtt;
563
564 ret = intel_memory_regions_hw_probe(dev_priv);
565 if (ret)
566 goto err_ggtt;
567
568 intel_gt_init_hw_early(&dev_priv->gt, &dev_priv->ggtt);
569
570 ret = intel_gt_probe_lmem(&dev_priv->gt);
571 if (ret)
572 goto err_mem_regions;
573
574 ret = i915_ggtt_enable_hw(dev_priv);
575 if (ret) {
576 drm_err(&dev_priv->drm, "failed to enable GGTT\n");
577 goto err_mem_regions;
578 }
579
580 pci_set_master(pdev);
581
582 intel_gt_init_workarounds(dev_priv);
583
584 /* On the 945G/GM, the chipset reports the MSI capability on the
585 * integrated graphics even though the support isn't actually there
586 * according to the published specs. It doesn't appear to function
587 * correctly in testing on 945G.
588 * This may be a side effect of MSI having been made available for PEG
589 * and the registers being closely associated.
590 *
591 * According to chipset errata, on the 965GM, MSI interrupts may
592 * be lost or delayed, and was defeatured. MSI interrupts seem to
593 * get lost on g4x as well, and interrupt delivery seems to stay
594 * properly dead afterwards. So we'll just disable them for all
595 * pre-gen5 chipsets.
596 *
597 * dp aux and gmbus irq on gen4 seems to be able to generate legacy
598 * interrupts even when in MSI mode. This results in spurious
599 * interrupt warnings if the legacy irq no. is shared with another
600 * device. The kernel then disables that interrupt source and so
601 * prevents the other device from working properly.
602 */
603 if (INTEL_GEN(dev_priv) >= 5) {
604 if (pci_enable_msi(pdev) < 0)
605 drm_dbg(&dev_priv->drm, "can't enable MSI");
606 }
607
608 ret = intel_gvt_init(dev_priv);
609 if (ret)
610 goto err_msi;
611
612 intel_opregion_setup(dev_priv);
613
614 intel_pcode_init(dev_priv);
615
616 /*
617 * Fill the dram structure to get the system dram info. This will be
618 * used for memory latency calculation.
619 */
620 intel_dram_detect(dev_priv);
621
622 intel_bw_init_hw(dev_priv);
623
624 return 0;
625
626 err_msi:
627 if (pdev->msi_enabled)
628 pci_disable_msi(pdev);
629 err_mem_regions:
630 intel_memory_regions_driver_release(dev_priv);
631 err_ggtt:
632 i915_ggtt_driver_release(dev_priv);
633 err_perf:
634 i915_perf_fini(dev_priv);
635 return ret;
636 }
637
638 /**
639 * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe()
640 * @dev_priv: device private
641 */
i915_driver_hw_remove(struct drm_i915_private * dev_priv)642 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv)
643 {
644 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
645
646 i915_perf_fini(dev_priv);
647
648 if (pdev->msi_enabled)
649 pci_disable_msi(pdev);
650 }
651
652 /**
653 * i915_driver_register - register the driver with the rest of the system
654 * @dev_priv: device private
655 *
656 * Perform any steps necessary to make the driver available via kernel
657 * internal or userspace interfaces.
658 */
i915_driver_register(struct drm_i915_private * dev_priv)659 static void i915_driver_register(struct drm_i915_private *dev_priv)
660 {
661 struct drm_device *dev = &dev_priv->drm;
662
663 i915_gem_driver_register(dev_priv);
664 i915_pmu_register(dev_priv);
665
666 intel_vgpu_register(dev_priv);
667
668 /* Reveal our presence to userspace */
669 if (drm_dev_register(dev, 0)) {
670 drm_err(&dev_priv->drm,
671 "Failed to register driver for userspace access!\n");
672 return;
673 }
674
675 i915_debugfs_register(dev_priv);
676 i915_setup_sysfs(dev_priv);
677
678 /* Depends on sysfs having been initialized */
679 i915_perf_register(dev_priv);
680
681 intel_gt_driver_register(&dev_priv->gt);
682
683 intel_display_driver_register(dev_priv);
684
685 intel_power_domains_enable(dev_priv);
686 intel_runtime_pm_enable(&dev_priv->runtime_pm);
687
688 intel_register_dsm_handler();
689
690 if (i915_switcheroo_register(dev_priv))
691 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n");
692 }
693
694 /**
695 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
696 * @dev_priv: device private
697 */
i915_driver_unregister(struct drm_i915_private * dev_priv)698 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
699 {
700 i915_switcheroo_unregister(dev_priv);
701
702 intel_unregister_dsm_handler();
703
704 intel_runtime_pm_disable(&dev_priv->runtime_pm);
705 intel_power_domains_disable(dev_priv);
706
707 intel_display_driver_unregister(dev_priv);
708
709 intel_gt_driver_unregister(&dev_priv->gt);
710
711 i915_perf_unregister(dev_priv);
712 i915_pmu_unregister(dev_priv);
713
714 i915_teardown_sysfs(dev_priv);
715 drm_dev_unplug(&dev_priv->drm);
716
717 i915_gem_driver_unregister(dev_priv);
718 }
719
i915_welcome_messages(struct drm_i915_private * dev_priv)720 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
721 {
722 if (drm_debug_enabled(DRM_UT_DRIVER)) {
723 struct drm_printer p = drm_debug_printer("i915 device info:");
724
725 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
726 INTEL_DEVID(dev_priv),
727 INTEL_REVID(dev_priv),
728 intel_platform_name(INTEL_INFO(dev_priv)->platform),
729 intel_subplatform(RUNTIME_INFO(dev_priv),
730 INTEL_INFO(dev_priv)->platform),
731 INTEL_GEN(dev_priv));
732
733 intel_device_info_print_static(INTEL_INFO(dev_priv), &p);
734 intel_device_info_print_runtime(RUNTIME_INFO(dev_priv), &p);
735 intel_gt_info_print(&dev_priv->gt.info, &p);
736 }
737
738 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
739 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n");
740 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
741 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n");
742 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
743 drm_info(&dev_priv->drm,
744 "DRM_I915_DEBUG_RUNTIME_PM enabled\n");
745 }
746
747 static struct drm_i915_private *
i915_driver_create(struct pci_dev * pdev,const struct pci_device_id * ent)748 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
749 {
750 const struct intel_device_info *match_info =
751 (struct intel_device_info *)ent->driver_data;
752 struct intel_device_info *device_info;
753 struct drm_i915_private *i915;
754
755 i915 = devm_drm_dev_alloc(&pdev->dev, &driver,
756 struct drm_i915_private, drm);
757 if (IS_ERR(i915))
758 return i915;
759
760 i915->drm.pdev = pdev;
761 pci_set_drvdata(pdev, i915);
762
763 /* Device parameters start as a copy of module parameters. */
764 i915_params_copy(&i915->params, &i915_modparams);
765
766 /* Setup the write-once "constant" device info */
767 device_info = mkwrite_device_info(i915);
768 memcpy(device_info, match_info, sizeof(*device_info));
769 RUNTIME_INFO(i915)->device_id = pdev->device;
770
771 BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask));
772
773 return i915;
774 }
775
776 /**
777 * i915_driver_probe - setup chip and create an initial config
778 * @pdev: PCI device
779 * @ent: matching PCI ID entry
780 *
781 * The driver probe routine has to do several things:
782 * - drive output discovery via intel_modeset_init()
783 * - initialize the memory manager
784 * - allocate initial config memory
785 * - setup the DRM framebuffer with the allocated memory
786 */
i915_driver_probe(struct pci_dev * pdev,const struct pci_device_id * ent)787 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
788 {
789 const struct intel_device_info *match_info =
790 (struct intel_device_info *)ent->driver_data;
791 struct drm_i915_private *i915;
792 int ret;
793
794 i915 = i915_driver_create(pdev, ent);
795 if (IS_ERR(i915))
796 return PTR_ERR(i915);
797
798 /* Disable nuclear pageflip by default on pre-ILK */
799 if (!i915->params.nuclear_pageflip && match_info->gen < 5)
800 i915->drm.driver_features &= ~DRIVER_ATOMIC;
801
802 /*
803 * Check if we support fake LMEM -- for now we only unleash this for
804 * the live selftests(test-and-exit).
805 */
806 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
807 if (IS_ENABLED(CONFIG_DRM_I915_UNSTABLE_FAKE_LMEM)) {
808 if (INTEL_GEN(i915) >= 9 && i915_selftest.live < 0 &&
809 i915->params.fake_lmem_start) {
810 mkwrite_device_info(i915)->memory_regions =
811 REGION_SMEM | REGION_LMEM | REGION_STOLEN_SMEM;
812 GEM_BUG_ON(!HAS_LMEM(i915));
813 }
814 }
815 #endif
816
817 ret = pci_enable_device(pdev);
818 if (ret)
819 goto out_fini;
820
821 ret = i915_driver_early_probe(i915);
822 if (ret < 0)
823 goto out_pci_disable;
824
825 disable_rpm_wakeref_asserts(&i915->runtime_pm);
826
827 intel_vgpu_detect(i915);
828
829 ret = i915_driver_mmio_probe(i915);
830 if (ret < 0)
831 goto out_runtime_pm_put;
832
833 ret = i915_driver_hw_probe(i915);
834 if (ret < 0)
835 goto out_cleanup_mmio;
836
837 ret = intel_modeset_init_noirq(i915);
838 if (ret < 0)
839 goto out_cleanup_hw;
840
841 ret = intel_irq_install(i915);
842 if (ret)
843 goto out_cleanup_modeset;
844
845 ret = intel_modeset_init_nogem(i915);
846 if (ret)
847 goto out_cleanup_irq;
848
849 ret = i915_gem_init(i915);
850 if (ret)
851 goto out_cleanup_modeset2;
852
853 ret = intel_modeset_init(i915);
854 if (ret)
855 goto out_cleanup_gem;
856
857 i915_driver_register(i915);
858
859 enable_rpm_wakeref_asserts(&i915->runtime_pm);
860
861 i915_welcome_messages(i915);
862
863 i915->do_release = true;
864
865 return 0;
866
867 out_cleanup_gem:
868 i915_gem_suspend(i915);
869 i915_gem_driver_remove(i915);
870 i915_gem_driver_release(i915);
871 out_cleanup_modeset2:
872 /* FIXME clean up the error path */
873 intel_modeset_driver_remove(i915);
874 intel_irq_uninstall(i915);
875 intel_modeset_driver_remove_noirq(i915);
876 goto out_cleanup_modeset;
877 out_cleanup_irq:
878 intel_irq_uninstall(i915);
879 out_cleanup_modeset:
880 intel_modeset_driver_remove_nogem(i915);
881 out_cleanup_hw:
882 i915_driver_hw_remove(i915);
883 intel_memory_regions_driver_release(i915);
884 i915_ggtt_driver_release(i915);
885 out_cleanup_mmio:
886 i915_driver_mmio_release(i915);
887 out_runtime_pm_put:
888 enable_rpm_wakeref_asserts(&i915->runtime_pm);
889 i915_driver_late_release(i915);
890 out_pci_disable:
891 pci_disable_device(pdev);
892 out_fini:
893 i915_probe_error(i915, "Device initialization failed (%d)\n", ret);
894 return ret;
895 }
896
i915_driver_remove(struct drm_i915_private * i915)897 void i915_driver_remove(struct drm_i915_private *i915)
898 {
899 disable_rpm_wakeref_asserts(&i915->runtime_pm);
900
901 i915_driver_unregister(i915);
902
903 /* Flush any external code that still may be under the RCU lock */
904 synchronize_rcu();
905
906 i915_gem_suspend(i915);
907
908 intel_gvt_driver_remove(i915);
909
910 intel_modeset_driver_remove(i915);
911
912 intel_irq_uninstall(i915);
913
914 intel_modeset_driver_remove_noirq(i915);
915
916 i915_reset_error_state(i915);
917 i915_gem_driver_remove(i915);
918
919 intel_modeset_driver_remove_nogem(i915);
920
921 i915_driver_hw_remove(i915);
922
923 enable_rpm_wakeref_asserts(&i915->runtime_pm);
924 }
925
i915_driver_release(struct drm_device * dev)926 static void i915_driver_release(struct drm_device *dev)
927 {
928 struct drm_i915_private *dev_priv = to_i915(dev);
929 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
930
931 if (!dev_priv->do_release)
932 return;
933
934 disable_rpm_wakeref_asserts(rpm);
935
936 i915_gem_driver_release(dev_priv);
937
938 intel_memory_regions_driver_release(dev_priv);
939 i915_ggtt_driver_release(dev_priv);
940 i915_gem_drain_freed_objects(dev_priv);
941
942 i915_driver_mmio_release(dev_priv);
943
944 enable_rpm_wakeref_asserts(rpm);
945 intel_runtime_pm_driver_release(rpm);
946
947 i915_driver_late_release(dev_priv);
948 }
949
i915_driver_open(struct drm_device * dev,struct drm_file * file)950 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
951 {
952 struct drm_i915_private *i915 = to_i915(dev);
953 int ret;
954
955 ret = i915_gem_open(i915, file);
956 if (ret)
957 return ret;
958
959 return 0;
960 }
961
962 /**
963 * i915_driver_lastclose - clean up after all DRM clients have exited
964 * @dev: DRM device
965 *
966 * Take care of cleaning up after all DRM clients have exited. In the
967 * mode setting case, we want to restore the kernel's initial mode (just
968 * in case the last client left us in a bad state).
969 *
970 * Additionally, in the non-mode setting case, we'll tear down the GTT
971 * and DMA structures, since the kernel won't be using them, and clea
972 * up any GEM state.
973 */
i915_driver_lastclose(struct drm_device * dev)974 static void i915_driver_lastclose(struct drm_device *dev)
975 {
976 intel_fbdev_restore_mode(dev);
977 vga_switcheroo_process_delayed_switch();
978 }
979
i915_driver_postclose(struct drm_device * dev,struct drm_file * file)980 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
981 {
982 struct drm_i915_file_private *file_priv = file->driver_priv;
983
984 i915_gem_context_close(file);
985
986 kfree_rcu(file_priv, rcu);
987
988 /* Catch up with all the deferred frees from "this" client */
989 i915_gem_flush_free_objects(to_i915(dev));
990 }
991
intel_suspend_encoders(struct drm_i915_private * dev_priv)992 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
993 {
994 struct drm_device *dev = &dev_priv->drm;
995 struct intel_encoder *encoder;
996
997 drm_modeset_lock_all(dev);
998 for_each_intel_encoder(dev, encoder)
999 if (encoder->suspend)
1000 encoder->suspend(encoder);
1001 drm_modeset_unlock_all(dev);
1002 }
1003
intel_shutdown_encoders(struct drm_i915_private * dev_priv)1004 static void intel_shutdown_encoders(struct drm_i915_private *dev_priv)
1005 {
1006 struct drm_device *dev = &dev_priv->drm;
1007 struct intel_encoder *encoder;
1008
1009 drm_modeset_lock_all(dev);
1010 for_each_intel_encoder(dev, encoder)
1011 if (encoder->shutdown)
1012 encoder->shutdown(encoder);
1013 drm_modeset_unlock_all(dev);
1014 }
1015
i915_driver_shutdown(struct drm_i915_private * i915)1016 void i915_driver_shutdown(struct drm_i915_private *i915)
1017 {
1018 disable_rpm_wakeref_asserts(&i915->runtime_pm);
1019 intel_runtime_pm_disable(&i915->runtime_pm);
1020 intel_power_domains_disable(i915);
1021
1022 i915_gem_suspend(i915);
1023
1024 drm_kms_helper_poll_disable(&i915->drm);
1025
1026 drm_atomic_helper_shutdown(&i915->drm);
1027
1028 intel_dp_mst_suspend(i915);
1029
1030 intel_runtime_pm_disable_interrupts(i915);
1031 intel_hpd_cancel_work(i915);
1032
1033 intel_suspend_encoders(i915);
1034 intel_shutdown_encoders(i915);
1035
1036 /*
1037 * The only requirement is to reboot with display DC states disabled,
1038 * for now leaving all display power wells in the INIT power domain
1039 * enabled matching the driver reload sequence.
1040 */
1041 intel_power_domains_driver_remove(i915);
1042 enable_rpm_wakeref_asserts(&i915->runtime_pm);
1043
1044 intel_runtime_pm_driver_release(&i915->runtime_pm);
1045 }
1046
suspend_to_idle(struct drm_i915_private * dev_priv)1047 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1048 {
1049 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1050 if (acpi_target_system_state() < ACPI_STATE_S3)
1051 return true;
1052 #endif
1053 return false;
1054 }
1055
i915_drm_prepare(struct drm_device * dev)1056 static int i915_drm_prepare(struct drm_device *dev)
1057 {
1058 struct drm_i915_private *i915 = to_i915(dev);
1059
1060 /*
1061 * NB intel_display_suspend() may issue new requests after we've
1062 * ostensibly marked the GPU as ready-to-sleep here. We need to
1063 * split out that work and pull it forward so that after point,
1064 * the GPU is not woken again.
1065 */
1066 i915_gem_suspend(i915);
1067
1068 return 0;
1069 }
1070
i915_drm_suspend(struct drm_device * dev)1071 static int i915_drm_suspend(struct drm_device *dev)
1072 {
1073 struct drm_i915_private *dev_priv = to_i915(dev);
1074 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1075 pci_power_t opregion_target_state;
1076
1077 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1078
1079 /* We do a lot of poking in a lot of registers, make sure they work
1080 * properly. */
1081 intel_power_domains_disable(dev_priv);
1082
1083 drm_kms_helper_poll_disable(dev);
1084
1085 pci_save_state(pdev);
1086
1087 intel_display_suspend(dev);
1088
1089 intel_dp_mst_suspend(dev_priv);
1090
1091 intel_runtime_pm_disable_interrupts(dev_priv);
1092 intel_hpd_cancel_work(dev_priv);
1093
1094 intel_suspend_encoders(dev_priv);
1095
1096 intel_suspend_hw(dev_priv);
1097
1098 i915_ggtt_suspend(&dev_priv->ggtt);
1099
1100 i915_save_display(dev_priv);
1101
1102 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1103 intel_opregion_suspend(dev_priv, opregion_target_state);
1104
1105 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1106
1107 dev_priv->suspend_count++;
1108
1109 intel_csr_ucode_suspend(dev_priv);
1110
1111 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1112
1113 return 0;
1114 }
1115
1116 static enum i915_drm_suspend_mode
get_suspend_mode(struct drm_i915_private * dev_priv,bool hibernate)1117 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate)
1118 {
1119 if (hibernate)
1120 return I915_DRM_SUSPEND_HIBERNATE;
1121
1122 if (suspend_to_idle(dev_priv))
1123 return I915_DRM_SUSPEND_IDLE;
1124
1125 return I915_DRM_SUSPEND_MEM;
1126 }
1127
i915_drm_suspend_late(struct drm_device * dev,bool hibernation)1128 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1129 {
1130 struct drm_i915_private *dev_priv = to_i915(dev);
1131 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1132 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1133 int ret;
1134
1135 disable_rpm_wakeref_asserts(rpm);
1136
1137 i915_gem_suspend_late(dev_priv);
1138
1139 intel_uncore_suspend(&dev_priv->uncore);
1140
1141 intel_power_domains_suspend(dev_priv,
1142 get_suspend_mode(dev_priv, hibernation));
1143
1144 intel_display_power_suspend_late(dev_priv);
1145
1146 ret = vlv_suspend_complete(dev_priv);
1147 if (ret) {
1148 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret);
1149 intel_power_domains_resume(dev_priv);
1150
1151 goto out;
1152 }
1153
1154 pci_disable_device(pdev);
1155 /*
1156 * During hibernation on some platforms the BIOS may try to access
1157 * the device even though it's already in D3 and hang the machine. So
1158 * leave the device in D0 on those platforms and hope the BIOS will
1159 * power down the device properly. The issue was seen on multiple old
1160 * GENs with different BIOS vendors, so having an explicit blacklist
1161 * is inpractical; apply the workaround on everything pre GEN6. The
1162 * platforms where the issue was seen:
1163 * Lenovo Thinkpad X301, X61s, X60, T60, X41
1164 * Fujitsu FSC S7110
1165 * Acer Aspire 1830T
1166 */
1167 if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1168 pci_set_power_state(pdev, PCI_D3hot);
1169
1170 out:
1171 enable_rpm_wakeref_asserts(rpm);
1172 if (!dev_priv->uncore.user_forcewake_count)
1173 intel_runtime_pm_driver_release(rpm);
1174
1175 return ret;
1176 }
1177
i915_suspend_switcheroo(struct drm_i915_private * i915,pm_message_t state)1178 int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state)
1179 {
1180 int error;
1181
1182 if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND &&
1183 state.event != PM_EVENT_FREEZE))
1184 return -EINVAL;
1185
1186 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1187 return 0;
1188
1189 error = i915_drm_suspend(&i915->drm);
1190 if (error)
1191 return error;
1192
1193 return i915_drm_suspend_late(&i915->drm, false);
1194 }
1195
i915_drm_resume(struct drm_device * dev)1196 static int i915_drm_resume(struct drm_device *dev)
1197 {
1198 struct drm_i915_private *dev_priv = to_i915(dev);
1199 int ret;
1200
1201 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1202
1203 sanitize_gpu(dev_priv);
1204
1205 ret = i915_ggtt_enable_hw(dev_priv);
1206 if (ret)
1207 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n");
1208
1209 i915_ggtt_resume(&dev_priv->ggtt);
1210
1211 intel_csr_ucode_resume(dev_priv);
1212
1213 i915_restore_display(dev_priv);
1214 intel_pps_unlock_regs_wa(dev_priv);
1215
1216 intel_init_pch_refclk(dev_priv);
1217
1218 /*
1219 * Interrupts have to be enabled before any batches are run. If not the
1220 * GPU will hang. i915_gem_init_hw() will initiate batches to
1221 * update/restore the context.
1222 *
1223 * drm_mode_config_reset() needs AUX interrupts.
1224 *
1225 * Modeset enabling in intel_modeset_init_hw() also needs working
1226 * interrupts.
1227 */
1228 intel_runtime_pm_enable_interrupts(dev_priv);
1229
1230 drm_mode_config_reset(dev);
1231
1232 i915_gem_resume(dev_priv);
1233
1234 intel_modeset_init_hw(dev_priv);
1235 intel_init_clock_gating(dev_priv);
1236 intel_hpd_init(dev_priv);
1237
1238 /* MST sideband requires HPD interrupts enabled */
1239 intel_dp_mst_resume(dev_priv);
1240 intel_display_resume(dev);
1241
1242 intel_hpd_poll_disable(dev_priv);
1243 drm_kms_helper_poll_enable(dev);
1244
1245 intel_opregion_resume(dev_priv);
1246
1247 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1248
1249 intel_power_domains_enable(dev_priv);
1250
1251 intel_gvt_resume(dev_priv);
1252
1253 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1254
1255 return 0;
1256 }
1257
i915_drm_resume_early(struct drm_device * dev)1258 static int i915_drm_resume_early(struct drm_device *dev)
1259 {
1260 struct drm_i915_private *dev_priv = to_i915(dev);
1261 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1262 int ret;
1263
1264 /*
1265 * We have a resume ordering issue with the snd-hda driver also
1266 * requiring our device to be power up. Due to the lack of a
1267 * parent/child relationship we currently solve this with an early
1268 * resume hook.
1269 *
1270 * FIXME: This should be solved with a special hdmi sink device or
1271 * similar so that power domains can be employed.
1272 */
1273
1274 /*
1275 * Note that we need to set the power state explicitly, since we
1276 * powered off the device during freeze and the PCI core won't power
1277 * it back up for us during thaw. Powering off the device during
1278 * freeze is not a hard requirement though, and during the
1279 * suspend/resume phases the PCI core makes sure we get here with the
1280 * device powered on. So in case we change our freeze logic and keep
1281 * the device powered we can also remove the following set power state
1282 * call.
1283 */
1284 ret = pci_set_power_state(pdev, PCI_D0);
1285 if (ret) {
1286 drm_err(&dev_priv->drm,
1287 "failed to set PCI D0 power state (%d)\n", ret);
1288 return ret;
1289 }
1290
1291 /*
1292 * Note that pci_enable_device() first enables any parent bridge
1293 * device and only then sets the power state for this device. The
1294 * bridge enabling is a nop though, since bridge devices are resumed
1295 * first. The order of enabling power and enabling the device is
1296 * imposed by the PCI core as described above, so here we preserve the
1297 * same order for the freeze/thaw phases.
1298 *
1299 * TODO: eventually we should remove pci_disable_device() /
1300 * pci_enable_enable_device() from suspend/resume. Due to how they
1301 * depend on the device enable refcount we can't anyway depend on them
1302 * disabling/enabling the device.
1303 */
1304 if (pci_enable_device(pdev))
1305 return -EIO;
1306
1307 pci_set_master(pdev);
1308
1309 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1310
1311 ret = vlv_resume_prepare(dev_priv, false);
1312 if (ret)
1313 drm_err(&dev_priv->drm,
1314 "Resume prepare failed: %d, continuing anyway\n", ret);
1315
1316 intel_uncore_resume_early(&dev_priv->uncore);
1317
1318 intel_gt_check_and_clear_faults(&dev_priv->gt);
1319
1320 intel_display_power_resume_early(dev_priv);
1321
1322 intel_power_domains_resume(dev_priv);
1323
1324 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1325
1326 return ret;
1327 }
1328
i915_resume_switcheroo(struct drm_i915_private * i915)1329 int i915_resume_switcheroo(struct drm_i915_private *i915)
1330 {
1331 int ret;
1332
1333 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1334 return 0;
1335
1336 ret = i915_drm_resume_early(&i915->drm);
1337 if (ret)
1338 return ret;
1339
1340 return i915_drm_resume(&i915->drm);
1341 }
1342
i915_pm_prepare(struct device * kdev)1343 static int i915_pm_prepare(struct device *kdev)
1344 {
1345 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1346
1347 if (!i915) {
1348 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1349 return -ENODEV;
1350 }
1351
1352 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1353 return 0;
1354
1355 return i915_drm_prepare(&i915->drm);
1356 }
1357
i915_pm_suspend(struct device * kdev)1358 static int i915_pm_suspend(struct device *kdev)
1359 {
1360 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1361
1362 if (!i915) {
1363 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1364 return -ENODEV;
1365 }
1366
1367 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1368 return 0;
1369
1370 return i915_drm_suspend(&i915->drm);
1371 }
1372
i915_pm_suspend_late(struct device * kdev)1373 static int i915_pm_suspend_late(struct device *kdev)
1374 {
1375 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1376
1377 /*
1378 * We have a suspend ordering issue with the snd-hda driver also
1379 * requiring our device to be power up. Due to the lack of a
1380 * parent/child relationship we currently solve this with an late
1381 * suspend hook.
1382 *
1383 * FIXME: This should be solved with a special hdmi sink device or
1384 * similar so that power domains can be employed.
1385 */
1386 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1387 return 0;
1388
1389 return i915_drm_suspend_late(&i915->drm, false);
1390 }
1391
i915_pm_poweroff_late(struct device * kdev)1392 static int i915_pm_poweroff_late(struct device *kdev)
1393 {
1394 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1395
1396 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1397 return 0;
1398
1399 return i915_drm_suspend_late(&i915->drm, true);
1400 }
1401
i915_pm_resume_early(struct device * kdev)1402 static int i915_pm_resume_early(struct device *kdev)
1403 {
1404 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1405
1406 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1407 return 0;
1408
1409 return i915_drm_resume_early(&i915->drm);
1410 }
1411
i915_pm_resume(struct device * kdev)1412 static int i915_pm_resume(struct device *kdev)
1413 {
1414 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1415
1416 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1417 return 0;
1418
1419 return i915_drm_resume(&i915->drm);
1420 }
1421
1422 /* freeze: before creating the hibernation_image */
i915_pm_freeze(struct device * kdev)1423 static int i915_pm_freeze(struct device *kdev)
1424 {
1425 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1426 int ret;
1427
1428 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1429 ret = i915_drm_suspend(&i915->drm);
1430 if (ret)
1431 return ret;
1432 }
1433
1434 ret = i915_gem_freeze(i915);
1435 if (ret)
1436 return ret;
1437
1438 return 0;
1439 }
1440
i915_pm_freeze_late(struct device * kdev)1441 static int i915_pm_freeze_late(struct device *kdev)
1442 {
1443 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1444 int ret;
1445
1446 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1447 ret = i915_drm_suspend_late(&i915->drm, true);
1448 if (ret)
1449 return ret;
1450 }
1451
1452 ret = i915_gem_freeze_late(i915);
1453 if (ret)
1454 return ret;
1455
1456 return 0;
1457 }
1458
1459 /* thaw: called after creating the hibernation image, but before turning off. */
i915_pm_thaw_early(struct device * kdev)1460 static int i915_pm_thaw_early(struct device *kdev)
1461 {
1462 return i915_pm_resume_early(kdev);
1463 }
1464
i915_pm_thaw(struct device * kdev)1465 static int i915_pm_thaw(struct device *kdev)
1466 {
1467 return i915_pm_resume(kdev);
1468 }
1469
1470 /* restore: called after loading the hibernation image. */
i915_pm_restore_early(struct device * kdev)1471 static int i915_pm_restore_early(struct device *kdev)
1472 {
1473 return i915_pm_resume_early(kdev);
1474 }
1475
i915_pm_restore(struct device * kdev)1476 static int i915_pm_restore(struct device *kdev)
1477 {
1478 return i915_pm_resume(kdev);
1479 }
1480
intel_runtime_suspend(struct device * kdev)1481 static int intel_runtime_suspend(struct device *kdev)
1482 {
1483 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1484 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1485 int ret;
1486
1487 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1488 return -ENODEV;
1489
1490 drm_dbg_kms(&dev_priv->drm, "Suspending device\n");
1491
1492 disable_rpm_wakeref_asserts(rpm);
1493
1494 /*
1495 * We are safe here against re-faults, since the fault handler takes
1496 * an RPM reference.
1497 */
1498 i915_gem_runtime_suspend(dev_priv);
1499
1500 intel_gt_runtime_suspend(&dev_priv->gt);
1501
1502 intel_runtime_pm_disable_interrupts(dev_priv);
1503
1504 intel_uncore_suspend(&dev_priv->uncore);
1505
1506 intel_display_power_suspend(dev_priv);
1507
1508 ret = vlv_suspend_complete(dev_priv);
1509 if (ret) {
1510 drm_err(&dev_priv->drm,
1511 "Runtime suspend failed, disabling it (%d)\n", ret);
1512 intel_uncore_runtime_resume(&dev_priv->uncore);
1513
1514 intel_runtime_pm_enable_interrupts(dev_priv);
1515
1516 intel_gt_runtime_resume(&dev_priv->gt);
1517
1518 enable_rpm_wakeref_asserts(rpm);
1519
1520 return ret;
1521 }
1522
1523 enable_rpm_wakeref_asserts(rpm);
1524 intel_runtime_pm_driver_release(rpm);
1525
1526 if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
1527 drm_err(&dev_priv->drm,
1528 "Unclaimed access detected prior to suspending\n");
1529
1530 rpm->suspended = true;
1531
1532 /*
1533 * FIXME: We really should find a document that references the arguments
1534 * used below!
1535 */
1536 if (IS_BROADWELL(dev_priv)) {
1537 /*
1538 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1539 * being detected, and the call we do at intel_runtime_resume()
1540 * won't be able to restore them. Since PCI_D3hot matches the
1541 * actual specification and appears to be working, use it.
1542 */
1543 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
1544 } else {
1545 /*
1546 * current versions of firmware which depend on this opregion
1547 * notification have repurposed the D1 definition to mean
1548 * "runtime suspended" vs. what you would normally expect (D3)
1549 * to distinguish it from notifications that might be sent via
1550 * the suspend path.
1551 */
1552 intel_opregion_notify_adapter(dev_priv, PCI_D1);
1553 }
1554
1555 assert_forcewakes_inactive(&dev_priv->uncore);
1556
1557 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
1558 intel_hpd_poll_enable(dev_priv);
1559
1560 drm_dbg_kms(&dev_priv->drm, "Device suspended\n");
1561 return 0;
1562 }
1563
intel_runtime_resume(struct device * kdev)1564 static int intel_runtime_resume(struct device *kdev)
1565 {
1566 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1567 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1568 int ret;
1569
1570 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1571 return -ENODEV;
1572
1573 drm_dbg_kms(&dev_priv->drm, "Resuming device\n");
1574
1575 drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count));
1576 disable_rpm_wakeref_asserts(rpm);
1577
1578 intel_opregion_notify_adapter(dev_priv, PCI_D0);
1579 rpm->suspended = false;
1580 if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
1581 drm_dbg(&dev_priv->drm,
1582 "Unclaimed access during suspend, bios?\n");
1583
1584 intel_display_power_resume(dev_priv);
1585
1586 ret = vlv_resume_prepare(dev_priv, true);
1587
1588 intel_uncore_runtime_resume(&dev_priv->uncore);
1589
1590 intel_runtime_pm_enable_interrupts(dev_priv);
1591
1592 /*
1593 * No point of rolling back things in case of an error, as the best
1594 * we can do is to hope that things will still work (and disable RPM).
1595 */
1596 intel_gt_runtime_resume(&dev_priv->gt);
1597
1598 /*
1599 * On VLV/CHV display interrupts are part of the display
1600 * power well, so hpd is reinitialized from there. For
1601 * everyone else do it here.
1602 */
1603 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
1604 intel_hpd_init(dev_priv);
1605 intel_hpd_poll_disable(dev_priv);
1606 }
1607
1608 intel_enable_ipc(dev_priv);
1609
1610 enable_rpm_wakeref_asserts(rpm);
1611
1612 if (ret)
1613 drm_err(&dev_priv->drm,
1614 "Runtime resume failed, disabling it (%d)\n", ret);
1615 else
1616 drm_dbg_kms(&dev_priv->drm, "Device resumed\n");
1617
1618 return ret;
1619 }
1620
1621 const struct dev_pm_ops i915_pm_ops = {
1622 /*
1623 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1624 * PMSG_RESUME]
1625 */
1626 .prepare = i915_pm_prepare,
1627 .suspend = i915_pm_suspend,
1628 .suspend_late = i915_pm_suspend_late,
1629 .resume_early = i915_pm_resume_early,
1630 .resume = i915_pm_resume,
1631
1632 /*
1633 * S4 event handlers
1634 * @freeze, @freeze_late : called (1) before creating the
1635 * hibernation image [PMSG_FREEZE] and
1636 * (2) after rebooting, before restoring
1637 * the image [PMSG_QUIESCE]
1638 * @thaw, @thaw_early : called (1) after creating the hibernation
1639 * image, before writing it [PMSG_THAW]
1640 * and (2) after failing to create or
1641 * restore the image [PMSG_RECOVER]
1642 * @poweroff, @poweroff_late: called after writing the hibernation
1643 * image, before rebooting [PMSG_HIBERNATE]
1644 * @restore, @restore_early : called after rebooting and restoring the
1645 * hibernation image [PMSG_RESTORE]
1646 */
1647 .freeze = i915_pm_freeze,
1648 .freeze_late = i915_pm_freeze_late,
1649 .thaw_early = i915_pm_thaw_early,
1650 .thaw = i915_pm_thaw,
1651 .poweroff = i915_pm_suspend,
1652 .poweroff_late = i915_pm_poweroff_late,
1653 .restore_early = i915_pm_restore_early,
1654 .restore = i915_pm_restore,
1655
1656 /* S0ix (via runtime suspend) event handlers */
1657 .runtime_suspend = intel_runtime_suspend,
1658 .runtime_resume = intel_runtime_resume,
1659 };
1660
1661 static const struct file_operations i915_driver_fops = {
1662 .owner = THIS_MODULE,
1663 .open = drm_open,
1664 .release = drm_release_noglobal,
1665 .unlocked_ioctl = drm_ioctl,
1666 .mmap = i915_gem_mmap,
1667 .poll = drm_poll,
1668 .read = drm_read,
1669 .compat_ioctl = i915_ioc32_compat_ioctl,
1670 .llseek = noop_llseek,
1671 };
1672
1673 static int
i915_gem_reject_pin_ioctl(struct drm_device * dev,void * data,struct drm_file * file)1674 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1675 struct drm_file *file)
1676 {
1677 return -ENODEV;
1678 }
1679
1680 static const struct drm_ioctl_desc i915_ioctls[] = {
1681 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1682 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1683 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1684 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1685 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1686 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1687 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW),
1688 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1689 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1690 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1691 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1692 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1693 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1694 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1695 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH),
1696 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1697 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1698 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1699 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, drm_invalid_op, DRM_AUTH),
1700 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW),
1701 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1702 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1703 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW),
1704 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
1705 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
1706 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
1707 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1708 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1709 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
1710 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
1711 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
1712 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
1713 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW),
1714 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
1715 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
1716 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
1717 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
1718 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
1719 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
1720 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
1721 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
1722 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
1723 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
1724 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
1725 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW),
1726 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
1727 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
1728 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
1729 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
1730 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
1731 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
1732 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
1733 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
1734 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW),
1735 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW),
1736 DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW),
1737 DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW),
1738 DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW),
1739 };
1740
1741 static const struct drm_driver driver = {
1742 /* Don't use MTRRs here; the Xserver or userspace app should
1743 * deal with them for Intel hardware.
1744 */
1745 .driver_features =
1746 DRIVER_GEM |
1747 DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ |
1748 DRIVER_SYNCOBJ_TIMELINE,
1749 .release = i915_driver_release,
1750 .open = i915_driver_open,
1751 .lastclose = i915_driver_lastclose,
1752 .postclose = i915_driver_postclose,
1753
1754 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1755 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1756 .gem_prime_import = i915_gem_prime_import,
1757
1758 .dumb_create = i915_gem_dumb_create,
1759 .dumb_map_offset = i915_gem_dumb_mmap_offset,
1760
1761 .ioctls = i915_ioctls,
1762 .num_ioctls = ARRAY_SIZE(i915_ioctls),
1763 .fops = &i915_driver_fops,
1764 .name = DRIVER_NAME,
1765 .desc = DRIVER_DESC,
1766 .date = DRIVER_DATE,
1767 .major = DRIVER_MAJOR,
1768 .minor = DRIVER_MINOR,
1769 .patchlevel = DRIVER_PATCHLEVEL,
1770 };
1771