1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2015 Broadcom
4 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
5 * Copyright (C) 2013 Red Hat
6 * Author: Rob Clark <robdclark@gmail.com>
7 */
8
9 /**
10 * DOC: VC4 Falcon HDMI module
11 *
12 * The HDMI core has a state machine and a PHY. On BCM2835, most of
13 * the unit operates off of the HSM clock from CPRMAN. It also
14 * internally uses the PLLH_PIX clock for the PHY.
15 *
16 * HDMI infoframes are kept within a small packet ram, where each
17 * packet can be individually enabled for including in a frame.
18 *
19 * HDMI audio is implemented entirely within the HDMI IP block. A
20 * register in the HDMI encoder takes SPDIF frames from the DMA engine
21 * and transfers them over an internal MAI (multi-channel audio
22 * interconnect) bus to the encoder side for insertion into the video
23 * blank regions.
24 *
25 * The driver's HDMI encoder does not yet support power management.
26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept
27 * continuously running, and only the HDMI logic and packet ram are
28 * powered off/on at disable/enable time.
29 *
30 * The driver does not yet support CEC control, though the HDMI
31 * encoder block has CEC support.
32 */
33
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_edid.h>
36 #include <drm/drm_probe_helper.h>
37 #include <drm/drm_simple_kms_helper.h>
38 #include <linux/clk.h>
39 #include <linux/component.h>
40 #include <linux/i2c.h>
41 #include <linux/of_address.h>
42 #include <linux/of_gpio.h>
43 #include <linux/of_platform.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/rational.h>
46 #include <linux/reset.h>
47 #include <sound/dmaengine_pcm.h>
48 #include <sound/pcm_drm_eld.h>
49 #include <sound/pcm_params.h>
50 #include <sound/soc.h>
51 #include "media/cec.h"
52 #include "vc4_drv.h"
53 #include "vc4_hdmi.h"
54 #include "vc4_hdmi_regs.h"
55 #include "vc4_regs.h"
56
57 #define VC5_HDMI_HORZA_HFP_SHIFT 16
58 #define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16)
59 #define VC5_HDMI_HORZA_VPOS BIT(15)
60 #define VC5_HDMI_HORZA_HPOS BIT(14)
61 #define VC5_HDMI_HORZA_HAP_SHIFT 0
62 #define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0)
63
64 #define VC5_HDMI_HORZB_HBP_SHIFT 16
65 #define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16)
66 #define VC5_HDMI_HORZB_HSP_SHIFT 0
67 #define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0)
68
69 #define VC5_HDMI_VERTA_VSP_SHIFT 24
70 #define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24)
71 #define VC5_HDMI_VERTA_VFP_SHIFT 16
72 #define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16)
73 #define VC5_HDMI_VERTA_VAL_SHIFT 0
74 #define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0)
75
76 #define VC5_HDMI_VERTB_VSPO_SHIFT 16
77 #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16)
78
79 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8
80 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8)
81
82 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT 0
83 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK VC4_MASK(3, 0)
84
85 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE BIT(31)
86
87 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT 8
88 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK VC4_MASK(15, 8)
89
90 # define VC4_HD_M_SW_RST BIT(2)
91 # define VC4_HD_M_ENABLE BIT(0)
92
93 #define CEC_CLOCK_FREQ 40000
94 #define VC4_HSM_MID_CLOCK 149985000
95
96 #define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000)
97
vc4_hdmi_debugfs_regs(struct seq_file * m,void * unused)98 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
99 {
100 struct drm_info_node *node = (struct drm_info_node *)m->private;
101 struct vc4_hdmi *vc4_hdmi = node->info_ent->data;
102 struct drm_printer p = drm_seq_file_printer(m);
103
104 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
105 drm_print_regset32(&p, &vc4_hdmi->hd_regset);
106
107 return 0;
108 }
109
vc4_hdmi_reset(struct vc4_hdmi * vc4_hdmi)110 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
111 {
112 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
113 udelay(1);
114 HDMI_WRITE(HDMI_M_CTL, 0);
115
116 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
117
118 HDMI_WRITE(HDMI_SW_RESET_CONTROL,
119 VC4_HDMI_SW_RESET_HDMI |
120 VC4_HDMI_SW_RESET_FORMAT_DETECT);
121
122 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
123 }
124
vc5_hdmi_reset(struct vc4_hdmi * vc4_hdmi)125 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
126 {
127 reset_control_reset(vc4_hdmi->reset);
128
129 HDMI_WRITE(HDMI_DVP_CTL, 0);
130
131 HDMI_WRITE(HDMI_CLOCK_STOP,
132 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
133 }
134
135 #ifdef CONFIG_DRM_VC4_HDMI_CEC
vc4_hdmi_cec_update_clk_div(struct vc4_hdmi * vc4_hdmi)136 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
137 {
138 u16 clk_cnt;
139 u32 value;
140
141 value = HDMI_READ(HDMI_CEC_CNTRL_1);
142 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
143
144 /*
145 * Set the clock divider: the hsm_clock rate and this divider
146 * setting will give a 40 kHz CEC clock.
147 */
148 clk_cnt = clk_get_rate(vc4_hdmi->cec_clock) / CEC_CLOCK_FREQ;
149 value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
150 HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
151 }
152 #else
vc4_hdmi_cec_update_clk_div(struct vc4_hdmi * vc4_hdmi)153 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
154 #endif
155
156 static enum drm_connector_status
vc4_hdmi_connector_detect(struct drm_connector * connector,bool force)157 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
158 {
159 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
160 bool connected = false;
161
162 if (vc4_hdmi->hpd_gpio) {
163 if (gpio_get_value_cansleep(vc4_hdmi->hpd_gpio) ^
164 vc4_hdmi->hpd_active_low)
165 connected = true;
166 } else if (drm_probe_ddc(vc4_hdmi->ddc)) {
167 connected = true;
168 } else if (HDMI_READ(HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED) {
169 connected = true;
170 }
171
172 if (connected) {
173 if (connector->status != connector_status_connected) {
174 struct edid *edid = drm_get_edid(connector, vc4_hdmi->ddc);
175
176 if (edid) {
177 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
178 vc4_hdmi->encoder.hdmi_monitor = drm_detect_hdmi_monitor(edid);
179 kfree(edid);
180 }
181 }
182
183 return connector_status_connected;
184 }
185
186 cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
187 return connector_status_disconnected;
188 }
189
vc4_hdmi_connector_destroy(struct drm_connector * connector)190 static void vc4_hdmi_connector_destroy(struct drm_connector *connector)
191 {
192 drm_connector_unregister(connector);
193 drm_connector_cleanup(connector);
194 }
195
vc4_hdmi_connector_get_modes(struct drm_connector * connector)196 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
197 {
198 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
199 struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder;
200 int ret = 0;
201 struct edid *edid;
202
203 edid = drm_get_edid(connector, vc4_hdmi->ddc);
204 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
205 if (!edid)
206 return -ENODEV;
207
208 vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid);
209
210 drm_connector_update_edid_property(connector, edid);
211 ret = drm_add_edid_modes(connector, edid);
212 kfree(edid);
213
214 return ret;
215 }
216
vc4_hdmi_connector_reset(struct drm_connector * connector)217 static void vc4_hdmi_connector_reset(struct drm_connector *connector)
218 {
219 struct vc4_hdmi_connector_state *old_state =
220 conn_state_to_vc4_hdmi_conn_state(connector->state);
221 struct vc4_hdmi_connector_state *new_state =
222 kzalloc(sizeof(*new_state), GFP_KERNEL);
223
224 if (connector->state)
225 __drm_atomic_helper_connector_destroy_state(connector->state);
226
227 kfree(old_state);
228 __drm_atomic_helper_connector_reset(connector, &new_state->base);
229
230 if (!new_state)
231 return;
232
233 new_state->base.max_bpc = 8;
234 new_state->base.max_requested_bpc = 8;
235 drm_atomic_helper_connector_tv_reset(connector);
236 }
237
238 static struct drm_connector_state *
vc4_hdmi_connector_duplicate_state(struct drm_connector * connector)239 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector)
240 {
241 struct drm_connector_state *conn_state = connector->state;
242 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
243 struct vc4_hdmi_connector_state *new_state;
244
245 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
246 if (!new_state)
247 return NULL;
248
249 new_state->pixel_rate = vc4_state->pixel_rate;
250 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
251
252 return &new_state->base;
253 }
254
255 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
256 .detect = vc4_hdmi_connector_detect,
257 .fill_modes = drm_helper_probe_single_connector_modes,
258 .destroy = vc4_hdmi_connector_destroy,
259 .reset = vc4_hdmi_connector_reset,
260 .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state,
261 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
262 };
263
264 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
265 .get_modes = vc4_hdmi_connector_get_modes,
266 };
267
vc4_hdmi_connector_init(struct drm_device * dev,struct vc4_hdmi * vc4_hdmi)268 static int vc4_hdmi_connector_init(struct drm_device *dev,
269 struct vc4_hdmi *vc4_hdmi)
270 {
271 struct drm_connector *connector = &vc4_hdmi->connector;
272 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
273 int ret;
274
275 drm_connector_init_with_ddc(dev, connector,
276 &vc4_hdmi_connector_funcs,
277 DRM_MODE_CONNECTOR_HDMIA,
278 vc4_hdmi->ddc);
279 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
280
281 /*
282 * Some of the properties below require access to state, like bpc.
283 * Allocate some default initial connector state with our reset helper.
284 */
285 if (connector->funcs->reset)
286 connector->funcs->reset(connector);
287
288 /* Create and attach TV margin props to this connector. */
289 ret = drm_mode_create_tv_margin_properties(dev);
290 if (ret)
291 return ret;
292
293 drm_connector_attach_tv_margin_properties(connector);
294 drm_connector_attach_max_bpc_property(connector, 8, 12);
295
296 connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
297 DRM_CONNECTOR_POLL_DISCONNECT);
298
299 connector->interlace_allowed = 1;
300 connector->doublescan_allowed = 0;
301
302 drm_connector_attach_encoder(connector, encoder);
303
304 return 0;
305 }
306
vc4_hdmi_stop_packet(struct drm_encoder * encoder,enum hdmi_infoframe_type type,bool poll)307 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
308 enum hdmi_infoframe_type type,
309 bool poll)
310 {
311 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
312 u32 packet_id = type - 0x80;
313
314 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
315 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
316
317 if (!poll)
318 return 0;
319
320 return wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
321 BIT(packet_id)), 100);
322 }
323
vc4_hdmi_write_infoframe(struct drm_encoder * encoder,union hdmi_infoframe * frame)324 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
325 union hdmi_infoframe *frame)
326 {
327 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
328 u32 packet_id = frame->any.type - 0x80;
329 const struct vc4_hdmi_register *ram_packet_start =
330 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
331 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
332 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
333 ram_packet_start->reg);
334 uint8_t buffer[VC4_HDMI_PACKET_STRIDE];
335 ssize_t len, i;
336 int ret;
337
338 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
339 VC4_HDMI_RAM_PACKET_ENABLE),
340 "Packet RAM has to be on to store the packet.");
341
342 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
343 if (len < 0)
344 return;
345
346 ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true);
347 if (ret) {
348 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
349 return;
350 }
351
352 for (i = 0; i < len; i += 7) {
353 writel(buffer[i + 0] << 0 |
354 buffer[i + 1] << 8 |
355 buffer[i + 2] << 16,
356 base + packet_reg);
357 packet_reg += 4;
358
359 writel(buffer[i + 3] << 0 |
360 buffer[i + 4] << 8 |
361 buffer[i + 5] << 16 |
362 buffer[i + 6] << 24,
363 base + packet_reg);
364 packet_reg += 4;
365 }
366
367 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
368 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
369 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
370 BIT(packet_id)), 100);
371 if (ret)
372 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
373 }
374
vc4_hdmi_set_avi_infoframe(struct drm_encoder * encoder)375 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
376 {
377 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
378 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
379 struct drm_connector *connector = &vc4_hdmi->connector;
380 struct drm_connector_state *cstate = connector->state;
381 struct drm_crtc *crtc = encoder->crtc;
382 const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
383 union hdmi_infoframe frame;
384 int ret;
385
386 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
387 connector, mode);
388 if (ret < 0) {
389 DRM_ERROR("couldn't fill AVI infoframe\n");
390 return;
391 }
392
393 drm_hdmi_avi_infoframe_quant_range(&frame.avi,
394 connector, mode,
395 vc4_encoder->limited_rgb_range ?
396 HDMI_QUANTIZATION_RANGE_LIMITED :
397 HDMI_QUANTIZATION_RANGE_FULL);
398
399 drm_hdmi_avi_infoframe_bars(&frame.avi, cstate);
400
401 vc4_hdmi_write_infoframe(encoder, &frame);
402 }
403
vc4_hdmi_set_spd_infoframe(struct drm_encoder * encoder)404 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
405 {
406 union hdmi_infoframe frame;
407 int ret;
408
409 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
410 if (ret < 0) {
411 DRM_ERROR("couldn't fill SPD infoframe\n");
412 return;
413 }
414
415 frame.spd.sdi = HDMI_SPD_SDI_PC;
416
417 vc4_hdmi_write_infoframe(encoder, &frame);
418 }
419
vc4_hdmi_set_audio_infoframe(struct drm_encoder * encoder)420 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
421 {
422 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
423 union hdmi_infoframe frame;
424
425 hdmi_audio_infoframe_init(&frame.audio);
426
427 frame.audio.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;
428 frame.audio.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;
429 frame.audio.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;
430 frame.audio.channels = vc4_hdmi->audio.channels;
431
432 vc4_hdmi_write_infoframe(encoder, &frame);
433 }
434
vc4_hdmi_set_infoframes(struct drm_encoder * encoder)435 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
436 {
437 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
438
439 vc4_hdmi_set_avi_infoframe(encoder);
440 vc4_hdmi_set_spd_infoframe(encoder);
441 /*
442 * If audio was streaming, then we need to reenabled the audio
443 * infoframe here during encoder_enable.
444 */
445 if (vc4_hdmi->audio.streaming)
446 vc4_hdmi_set_audio_infoframe(encoder);
447 }
448
vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder * encoder,struct drm_atomic_state * state)449 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
450 struct drm_atomic_state *state)
451 {
452 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
453
454 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
455
456 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) |
457 VC4_HD_VID_CTL_CLRRGB | VC4_HD_VID_CTL_CLRSYNC);
458
459 HDMI_WRITE(HDMI_VID_CTL,
460 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
461 }
462
vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder * encoder,struct drm_atomic_state * state)463 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
464 struct drm_atomic_state *state)
465 {
466 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
467 int ret;
468
469 if (vc4_hdmi->variant->phy_disable)
470 vc4_hdmi->variant->phy_disable(vc4_hdmi);
471
472 HDMI_WRITE(HDMI_VID_CTL,
473 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
474
475 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
476 clk_disable_unprepare(vc4_hdmi->hsm_clock);
477 clk_disable_unprepare(vc4_hdmi->pixel_clock);
478
479 ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
480 if (ret < 0)
481 DRM_ERROR("Failed to release power domain: %d\n", ret);
482 }
483
vc4_hdmi_encoder_disable(struct drm_encoder * encoder)484 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder)
485 {
486 }
487
vc4_hdmi_csc_setup(struct vc4_hdmi * vc4_hdmi,bool enable)488 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
489 {
490 u32 csc_ctl;
491
492 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
493 VC4_HD_CSC_CTL_ORDER);
494
495 if (enable) {
496 /* CEA VICs other than #1 requre limited range RGB
497 * output unless overridden by an AVI infoframe.
498 * Apply a colorspace conversion to squash 0-255 down
499 * to 16-235. The matrix here is:
500 *
501 * [ 0 0 0.8594 16]
502 * [ 0 0.8594 0 16]
503 * [ 0.8594 0 0 16]
504 * [ 0 0 0 1]
505 */
506 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
507 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
508 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
509 VC4_HD_CSC_CTL_MODE);
510
511 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
512 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
513 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
514 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
515 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
516 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
517 }
518
519 /* The RGB order applies even when CSC is disabled. */
520 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
521 }
522
vc5_hdmi_csc_setup(struct vc4_hdmi * vc4_hdmi,bool enable)523 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
524 {
525 u32 csc_ctl;
526
527 csc_ctl = 0x07; /* RGB_CONVERT_MODE = custom matrix, || USE_RGB_TO_YCBCR */
528
529 if (enable) {
530 /* CEA VICs other than #1 requre limited range RGB
531 * output unless overridden by an AVI infoframe.
532 * Apply a colorspace conversion to squash 0-255 down
533 * to 16-235. The matrix here is:
534 *
535 * [ 0.8594 0 0 16]
536 * [ 0 0.8594 0 16]
537 * [ 0 0 0.8594 16]
538 * [ 0 0 0 1]
539 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
540 */
541 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x1b80);
542 HDMI_WRITE(HDMI_CSC_14_13, (0x0400 << 16) | 0x0000);
543 HDMI_WRITE(HDMI_CSC_22_21, (0x1b80 << 16) | 0x0000);
544 HDMI_WRITE(HDMI_CSC_24_23, (0x0400 << 16) | 0x0000);
545 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000);
546 HDMI_WRITE(HDMI_CSC_34_33, (0x0400 << 16) | 0x1b80);
547 } else {
548 /* Still use the matrix for full range, but make it unity.
549 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
550 */
551 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x2000);
552 HDMI_WRITE(HDMI_CSC_14_13, (0x0000 << 16) | 0x0000);
553 HDMI_WRITE(HDMI_CSC_22_21, (0x2000 << 16) | 0x0000);
554 HDMI_WRITE(HDMI_CSC_24_23, (0x0000 << 16) | 0x0000);
555 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000);
556 HDMI_WRITE(HDMI_CSC_34_33, (0x0000 << 16) | 0x2000);
557 }
558
559 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
560 }
561
vc4_hdmi_set_timings(struct vc4_hdmi * vc4_hdmi,struct drm_connector_state * state,struct drm_display_mode * mode)562 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
563 struct drm_connector_state *state,
564 struct drm_display_mode *mode)
565 {
566 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
567 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
568 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
569 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
570 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
571 VC4_HDMI_VERTA_VSP) |
572 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
573 VC4_HDMI_VERTA_VFP) |
574 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
575 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
576 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
577 VC4_HDMI_VERTB_VBP));
578 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
579 VC4_SET_FIELD(mode->crtc_vtotal -
580 mode->crtc_vsync_end -
581 interlaced,
582 VC4_HDMI_VERTB_VBP));
583
584 HDMI_WRITE(HDMI_HORZA,
585 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
586 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
587 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
588 VC4_HDMI_HORZA_HAP));
589
590 HDMI_WRITE(HDMI_HORZB,
591 VC4_SET_FIELD((mode->htotal -
592 mode->hsync_end) * pixel_rep,
593 VC4_HDMI_HORZB_HBP) |
594 VC4_SET_FIELD((mode->hsync_end -
595 mode->hsync_start) * pixel_rep,
596 VC4_HDMI_HORZB_HSP) |
597 VC4_SET_FIELD((mode->hsync_start -
598 mode->hdisplay) * pixel_rep,
599 VC4_HDMI_HORZB_HFP));
600
601 HDMI_WRITE(HDMI_VERTA0, verta);
602 HDMI_WRITE(HDMI_VERTA1, verta);
603
604 HDMI_WRITE(HDMI_VERTB0, vertb_even);
605 HDMI_WRITE(HDMI_VERTB1, vertb);
606 }
607
vc5_hdmi_set_timings(struct vc4_hdmi * vc4_hdmi,struct drm_connector_state * state,struct drm_display_mode * mode)608 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
609 struct drm_connector_state *state,
610 struct drm_display_mode *mode)
611 {
612 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
613 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
614 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
615 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
616 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
617 VC5_HDMI_VERTA_VSP) |
618 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
619 VC5_HDMI_VERTA_VFP) |
620 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
621 u32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
622 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
623 VC4_HDMI_VERTB_VBP));
624 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
625 VC4_SET_FIELD(mode->crtc_vtotal -
626 mode->crtc_vsync_end -
627 interlaced,
628 VC4_HDMI_VERTB_VBP));
629 unsigned char gcp;
630 bool gcp_en;
631 u32 reg;
632
633 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, 0x354021);
634 HDMI_WRITE(HDMI_HORZA,
635 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
636 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
637 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
638 VC5_HDMI_HORZA_HAP) |
639 VC4_SET_FIELD((mode->hsync_start -
640 mode->hdisplay) * pixel_rep,
641 VC5_HDMI_HORZA_HFP));
642
643 HDMI_WRITE(HDMI_HORZB,
644 VC4_SET_FIELD((mode->htotal -
645 mode->hsync_end) * pixel_rep,
646 VC5_HDMI_HORZB_HBP) |
647 VC4_SET_FIELD((mode->hsync_end -
648 mode->hsync_start) * pixel_rep,
649 VC5_HDMI_HORZB_HSP));
650
651 HDMI_WRITE(HDMI_VERTA0, verta);
652 HDMI_WRITE(HDMI_VERTA1, verta);
653
654 HDMI_WRITE(HDMI_VERTB0, vertb_even);
655 HDMI_WRITE(HDMI_VERTB1, vertb);
656
657 switch (state->max_bpc) {
658 case 12:
659 gcp = 6;
660 gcp_en = true;
661 break;
662 case 10:
663 gcp = 5;
664 gcp_en = true;
665 break;
666 case 8:
667 default:
668 gcp = 4;
669 gcp_en = false;
670 break;
671 }
672
673 reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
674 reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK |
675 VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK);
676 reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) |
677 VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH);
678 HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg);
679
680 reg = HDMI_READ(HDMI_GCP_WORD_1);
681 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK;
682 reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);
683 HDMI_WRITE(HDMI_GCP_WORD_1, reg);
684
685 reg = HDMI_READ(HDMI_GCP_CONFIG);
686 reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE;
687 reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0;
688 HDMI_WRITE(HDMI_GCP_CONFIG, reg);
689
690 HDMI_WRITE(HDMI_CLOCK_STOP, 0);
691 }
692
vc4_hdmi_recenter_fifo(struct vc4_hdmi * vc4_hdmi)693 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
694 {
695 u32 drift;
696 int ret;
697
698 drift = HDMI_READ(HDMI_FIFO_CTL);
699 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
700
701 HDMI_WRITE(HDMI_FIFO_CTL,
702 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
703 HDMI_WRITE(HDMI_FIFO_CTL,
704 drift | VC4_HDMI_FIFO_CTL_RECENTER);
705 usleep_range(1000, 1100);
706 HDMI_WRITE(HDMI_FIFO_CTL,
707 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
708 HDMI_WRITE(HDMI_FIFO_CTL,
709 drift | VC4_HDMI_FIFO_CTL_RECENTER);
710
711 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
712 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
713 WARN_ONCE(ret, "Timeout waiting for "
714 "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
715 }
716
717 static struct drm_connector_state *
vc4_hdmi_encoder_get_connector_state(struct drm_encoder * encoder,struct drm_atomic_state * state)718 vc4_hdmi_encoder_get_connector_state(struct drm_encoder *encoder,
719 struct drm_atomic_state *state)
720 {
721 struct drm_connector_state *conn_state;
722 struct drm_connector *connector;
723 unsigned int i;
724
725 for_each_new_connector_in_state(state, connector, conn_state, i) {
726 if (conn_state->best_encoder == encoder)
727 return conn_state;
728 }
729
730 return NULL;
731 }
732
vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder * encoder,struct drm_atomic_state * state)733 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
734 struct drm_atomic_state *state)
735 {
736 struct drm_connector_state *conn_state =
737 vc4_hdmi_encoder_get_connector_state(encoder, state);
738 struct vc4_hdmi_connector_state *vc4_conn_state =
739 conn_state_to_vc4_hdmi_conn_state(conn_state);
740 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
741 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
742 unsigned long pixel_rate, hsm_rate;
743 int ret;
744
745 ret = pm_runtime_get_sync(&vc4_hdmi->pdev->dev);
746 if (ret < 0) {
747 DRM_ERROR("Failed to retain power domain: %d\n", ret);
748 return;
749 }
750
751 pixel_rate = vc4_conn_state->pixel_rate;
752 ret = clk_set_rate(vc4_hdmi->pixel_clock, pixel_rate);
753 if (ret) {
754 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
755 return;
756 }
757
758 ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
759 if (ret) {
760 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
761 return;
762 }
763
764 /*
765 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
766 * be faster than pixel clock, infinitesimally faster, tested in
767 * simulation. Otherwise, exact value is unimportant for HDMI
768 * operation." This conflicts with bcm2835's vc4 documentation, which
769 * states HSM's clock has to be at least 108% of the pixel clock.
770 *
771 * Real life tests reveal that vc4's firmware statement holds up, and
772 * users are able to use pixel clocks closer to HSM's, namely for
773 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
774 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
775 * 162MHz.
776 *
777 * Additionally, the AXI clock needs to be at least 25% of
778 * pixel clock, but HSM ends up being the limiting factor.
779 */
780 hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101);
781 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
782 if (ret) {
783 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
784 return;
785 }
786
787 ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
788 if (ret) {
789 DRM_ERROR("Failed to turn on HSM clock: %d\n", ret);
790 clk_disable_unprepare(vc4_hdmi->pixel_clock);
791 return;
792 }
793
794 vc4_hdmi_cec_update_clk_div(vc4_hdmi);
795
796 /*
797 * FIXME: When the pixel freq is 594MHz (4k60), this needs to be setup
798 * at 300MHz.
799 */
800 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock,
801 (hsm_rate > VC4_HSM_MID_CLOCK ? 150000000 : 75000000));
802 if (ret) {
803 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
804 clk_disable_unprepare(vc4_hdmi->hsm_clock);
805 clk_disable_unprepare(vc4_hdmi->pixel_clock);
806 return;
807 }
808
809 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
810 if (ret) {
811 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
812 clk_disable_unprepare(vc4_hdmi->hsm_clock);
813 clk_disable_unprepare(vc4_hdmi->pixel_clock);
814 return;
815 }
816
817 if (vc4_hdmi->variant->phy_init)
818 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state);
819
820 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
821 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
822 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
823 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
824
825 if (vc4_hdmi->variant->set_timings)
826 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);
827 }
828
vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder * encoder,struct drm_atomic_state * state)829 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,
830 struct drm_atomic_state *state)
831 {
832 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
833 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
834 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
835
836 if (vc4_encoder->hdmi_monitor &&
837 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_LIMITED) {
838 if (vc4_hdmi->variant->csc_setup)
839 vc4_hdmi->variant->csc_setup(vc4_hdmi, true);
840
841 vc4_encoder->limited_rgb_range = true;
842 } else {
843 if (vc4_hdmi->variant->csc_setup)
844 vc4_hdmi->variant->csc_setup(vc4_hdmi, false);
845
846 vc4_encoder->limited_rgb_range = false;
847 }
848
849 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
850 }
851
vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder * encoder,struct drm_atomic_state * state)852 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
853 struct drm_atomic_state *state)
854 {
855 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
856 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
857 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
858 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
859 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
860 int ret;
861
862 HDMI_WRITE(HDMI_VID_CTL,
863 VC4_HD_VID_CTL_ENABLE |
864 VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
865 VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
866 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
867 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
868
869 HDMI_WRITE(HDMI_VID_CTL,
870 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
871
872 if (vc4_encoder->hdmi_monitor) {
873 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
874 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
875 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
876
877 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
878 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
879 WARN_ONCE(ret, "Timeout waiting for "
880 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
881 } else {
882 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
883 HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
884 ~(VC4_HDMI_RAM_PACKET_ENABLE));
885 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
886 HDMI_READ(HDMI_SCHEDULER_CONTROL) &
887 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
888
889 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
890 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
891 WARN_ONCE(ret, "Timeout waiting for "
892 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
893 }
894
895 if (vc4_encoder->hdmi_monitor) {
896 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
897 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
898 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
899 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
900 VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT);
901
902 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
903 VC4_HDMI_RAM_PACKET_ENABLE);
904
905 vc4_hdmi_set_infoframes(encoder);
906 }
907
908 vc4_hdmi_recenter_fifo(vc4_hdmi);
909 }
910
vc4_hdmi_encoder_enable(struct drm_encoder * encoder)911 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
912 {
913 }
914
915 #define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL
916 #define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL
917
vc4_hdmi_encoder_atomic_check(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)918 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
919 struct drm_crtc_state *crtc_state,
920 struct drm_connector_state *conn_state)
921 {
922 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
923 struct drm_display_mode *mode = &crtc_state->adjusted_mode;
924 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
925 unsigned long long pixel_rate = mode->clock * 1000;
926 unsigned long long tmds_rate;
927
928 if (vc4_hdmi->variant->unsupported_odd_h_timings &&
929 ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
930 (mode->hsync_end % 2) || (mode->htotal % 2)))
931 return -EINVAL;
932
933 /*
934 * The 1440p@60 pixel rate is in the same range than the first
935 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
936 * bandwidth). Slightly lower the frequency to bring it out of
937 * the WiFi range.
938 */
939 tmds_rate = pixel_rate * 10;
940 if (vc4_hdmi->disable_wifi_frequencies &&
941 (tmds_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
942 tmds_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
943 mode->clock = 238560;
944 pixel_rate = mode->clock * 1000;
945 }
946
947 if (conn_state->max_bpc == 12) {
948 pixel_rate = pixel_rate * 150;
949 do_div(pixel_rate, 100);
950 } else if (conn_state->max_bpc == 10) {
951 pixel_rate = pixel_rate * 125;
952 do_div(pixel_rate, 100);
953 }
954
955 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
956 pixel_rate = pixel_rate * 2;
957
958 if (pixel_rate > vc4_hdmi->variant->max_pixel_clock)
959 return -EINVAL;
960
961 vc4_state->pixel_rate = pixel_rate;
962
963 return 0;
964 }
965
966 static enum drm_mode_status
vc4_hdmi_encoder_mode_valid(struct drm_encoder * encoder,const struct drm_display_mode * mode)967 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
968 const struct drm_display_mode *mode)
969 {
970 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
971
972 if (vc4_hdmi->variant->unsupported_odd_h_timings &&
973 ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
974 (mode->hsync_end % 2) || (mode->htotal % 2)))
975 return MODE_H_ILLEGAL;
976
977 if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock)
978 return MODE_CLOCK_HIGH;
979
980 return MODE_OK;
981 }
982
983 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
984 .atomic_check = vc4_hdmi_encoder_atomic_check,
985 .mode_valid = vc4_hdmi_encoder_mode_valid,
986 .disable = vc4_hdmi_encoder_disable,
987 .enable = vc4_hdmi_encoder_enable,
988 };
989
vc4_hdmi_channel_map(struct vc4_hdmi * vc4_hdmi,u32 channel_mask)990 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
991 {
992 int i;
993 u32 channel_map = 0;
994
995 for (i = 0; i < 8; i++) {
996 if (channel_mask & BIT(i))
997 channel_map |= i << (3 * i);
998 }
999 return channel_map;
1000 }
1001
vc5_hdmi_channel_map(struct vc4_hdmi * vc4_hdmi,u32 channel_mask)1002 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1003 {
1004 int i;
1005 u32 channel_map = 0;
1006
1007 for (i = 0; i < 8; i++) {
1008 if (channel_mask & BIT(i))
1009 channel_map |= i << (4 * i);
1010 }
1011 return channel_map;
1012 }
1013
1014 /* HDMI audio codec callbacks */
vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi * vc4_hdmi)1015 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi)
1016 {
1017 u32 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
1018 unsigned long n, m;
1019
1020 rational_best_approximation(hsm_clock, vc4_hdmi->audio.samplerate,
1021 VC4_HD_MAI_SMP_N_MASK >>
1022 VC4_HD_MAI_SMP_N_SHIFT,
1023 (VC4_HD_MAI_SMP_M_MASK >>
1024 VC4_HD_MAI_SMP_M_SHIFT) + 1,
1025 &n, &m);
1026
1027 HDMI_WRITE(HDMI_MAI_SMP,
1028 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
1029 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
1030 }
1031
vc4_hdmi_set_n_cts(struct vc4_hdmi * vc4_hdmi)1032 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi)
1033 {
1034 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1035 struct drm_crtc *crtc = encoder->crtc;
1036 const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1037 u32 samplerate = vc4_hdmi->audio.samplerate;
1038 u32 n, cts;
1039 u64 tmp;
1040
1041 n = 128 * samplerate / 1000;
1042 tmp = (u64)(mode->clock * 1000) * n;
1043 do_div(tmp, 128 * samplerate);
1044 cts = tmp;
1045
1046 HDMI_WRITE(HDMI_CRP_CFG,
1047 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
1048 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
1049
1050 /*
1051 * We could get slightly more accurate clocks in some cases by
1052 * providing a CTS_1 value. The two CTS values are alternated
1053 * between based on the period fields
1054 */
1055 HDMI_WRITE(HDMI_CTS_0, cts);
1056 HDMI_WRITE(HDMI_CTS_1, cts);
1057 }
1058
dai_to_hdmi(struct snd_soc_dai * dai)1059 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
1060 {
1061 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
1062
1063 return snd_soc_card_get_drvdata(card);
1064 }
1065
vc4_hdmi_audio_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)1066 static int vc4_hdmi_audio_startup(struct snd_pcm_substream *substream,
1067 struct snd_soc_dai *dai)
1068 {
1069 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1070 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1071 struct drm_connector *connector = &vc4_hdmi->connector;
1072 int ret;
1073
1074 if (vc4_hdmi->audio.substream && vc4_hdmi->audio.substream != substream)
1075 return -EINVAL;
1076
1077 vc4_hdmi->audio.substream = substream;
1078
1079 /*
1080 * If the HDMI encoder hasn't probed, or the encoder is
1081 * currently in DVI mode, treat the codec dai as missing.
1082 */
1083 if (!encoder->crtc || !(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1084 VC4_HDMI_RAM_PACKET_ENABLE))
1085 return -ENODEV;
1086
1087 ret = snd_pcm_hw_constraint_eld(substream->runtime, connector->eld);
1088 if (ret)
1089 return ret;
1090
1091 return 0;
1092 }
1093
vc4_hdmi_audio_set_fmt(struct snd_soc_dai * dai,unsigned int fmt)1094 static int vc4_hdmi_audio_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1095 {
1096 return 0;
1097 }
1098
vc4_hdmi_audio_reset(struct vc4_hdmi * vc4_hdmi)1099 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
1100 {
1101 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1102 struct device *dev = &vc4_hdmi->pdev->dev;
1103 int ret;
1104
1105 vc4_hdmi->audio.streaming = false;
1106 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false);
1107 if (ret)
1108 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
1109
1110 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
1111 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
1112 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
1113 }
1114
vc4_hdmi_audio_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)1115 static void vc4_hdmi_audio_shutdown(struct snd_pcm_substream *substream,
1116 struct snd_soc_dai *dai)
1117 {
1118 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1119
1120 if (substream != vc4_hdmi->audio.substream)
1121 return;
1122
1123 vc4_hdmi_audio_reset(vc4_hdmi);
1124
1125 vc4_hdmi->audio.substream = NULL;
1126 }
1127
1128 /* HDMI audio codec callbacks */
vc4_hdmi_audio_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1129 static int vc4_hdmi_audio_hw_params(struct snd_pcm_substream *substream,
1130 struct snd_pcm_hw_params *params,
1131 struct snd_soc_dai *dai)
1132 {
1133 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1134 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1135 struct device *dev = &vc4_hdmi->pdev->dev;
1136 u32 audio_packet_config, channel_mask;
1137 u32 channel_map;
1138
1139 if (substream != vc4_hdmi->audio.substream)
1140 return -EINVAL;
1141
1142 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
1143 params_rate(params), params_width(params),
1144 params_channels(params));
1145
1146 vc4_hdmi->audio.channels = params_channels(params);
1147 vc4_hdmi->audio.samplerate = params_rate(params);
1148
1149 HDMI_WRITE(HDMI_MAI_CTL,
1150 VC4_HD_MAI_CTL_RESET |
1151 VC4_HD_MAI_CTL_FLUSH |
1152 VC4_HD_MAI_CTL_DLATE |
1153 VC4_HD_MAI_CTL_ERRORE |
1154 VC4_HD_MAI_CTL_ERRORF);
1155
1156 vc4_hdmi_audio_set_mai_clock(vc4_hdmi);
1157
1158 /* The B frame identifier should match the value used by alsa-lib (8) */
1159 audio_packet_config =
1160 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
1161 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
1162 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
1163
1164 channel_mask = GENMASK(vc4_hdmi->audio.channels - 1, 0);
1165 audio_packet_config |= VC4_SET_FIELD(channel_mask,
1166 VC4_HDMI_AUDIO_PACKET_CEA_MASK);
1167
1168 /* Set the MAI threshold. This logic mimics the firmware's. */
1169 if (vc4_hdmi->audio.samplerate > 96000) {
1170 HDMI_WRITE(HDMI_MAI_THR,
1171 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQHIGH) |
1172 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW));
1173 } else if (vc4_hdmi->audio.samplerate > 48000) {
1174 HDMI_WRITE(HDMI_MAI_THR,
1175 VC4_SET_FIELD(0x14, VC4_HD_MAI_THR_DREQHIGH) |
1176 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW));
1177 } else {
1178 HDMI_WRITE(HDMI_MAI_THR,
1179 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
1180 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
1181 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) |
1182 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW));
1183 }
1184
1185 HDMI_WRITE(HDMI_MAI_CONFIG,
1186 VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
1187 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
1188
1189 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
1190 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
1191 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
1192 vc4_hdmi_set_n_cts(vc4_hdmi);
1193
1194 vc4_hdmi_set_audio_infoframe(encoder);
1195
1196 return 0;
1197 }
1198
vc4_hdmi_audio_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)1199 static int vc4_hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd,
1200 struct snd_soc_dai *dai)
1201 {
1202 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1203
1204 switch (cmd) {
1205 case SNDRV_PCM_TRIGGER_START:
1206 vc4_hdmi->audio.streaming = true;
1207
1208 if (vc4_hdmi->variant->phy_rng_enable)
1209 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
1210
1211 HDMI_WRITE(HDMI_MAI_CTL,
1212 VC4_SET_FIELD(vc4_hdmi->audio.channels,
1213 VC4_HD_MAI_CTL_CHNUM) |
1214 VC4_HD_MAI_CTL_ENABLE);
1215 break;
1216 case SNDRV_PCM_TRIGGER_STOP:
1217 HDMI_WRITE(HDMI_MAI_CTL,
1218 VC4_HD_MAI_CTL_DLATE |
1219 VC4_HD_MAI_CTL_ERRORE |
1220 VC4_HD_MAI_CTL_ERRORF);
1221
1222 if (vc4_hdmi->variant->phy_rng_disable)
1223 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
1224
1225 vc4_hdmi->audio.streaming = false;
1226
1227 break;
1228 default:
1229 break;
1230 }
1231
1232 return 0;
1233 }
1234
1235 static inline struct vc4_hdmi *
snd_component_to_hdmi(struct snd_soc_component * component)1236 snd_component_to_hdmi(struct snd_soc_component *component)
1237 {
1238 struct snd_soc_card *card = snd_soc_component_get_drvdata(component);
1239
1240 return snd_soc_card_get_drvdata(card);
1241 }
1242
vc4_hdmi_audio_eld_ctl_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1243 static int vc4_hdmi_audio_eld_ctl_info(struct snd_kcontrol *kcontrol,
1244 struct snd_ctl_elem_info *uinfo)
1245 {
1246 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1247 struct vc4_hdmi *vc4_hdmi = snd_component_to_hdmi(component);
1248 struct drm_connector *connector = &vc4_hdmi->connector;
1249
1250 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
1251 uinfo->count = sizeof(connector->eld);
1252
1253 return 0;
1254 }
1255
vc4_hdmi_audio_eld_ctl_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1256 static int vc4_hdmi_audio_eld_ctl_get(struct snd_kcontrol *kcontrol,
1257 struct snd_ctl_elem_value *ucontrol)
1258 {
1259 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1260 struct vc4_hdmi *vc4_hdmi = snd_component_to_hdmi(component);
1261 struct drm_connector *connector = &vc4_hdmi->connector;
1262
1263 memcpy(ucontrol->value.bytes.data, connector->eld,
1264 sizeof(connector->eld));
1265
1266 return 0;
1267 }
1268
1269 static const struct snd_kcontrol_new vc4_hdmi_audio_controls[] = {
1270 {
1271 .access = SNDRV_CTL_ELEM_ACCESS_READ |
1272 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
1273 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1274 .name = "ELD",
1275 .info = vc4_hdmi_audio_eld_ctl_info,
1276 .get = vc4_hdmi_audio_eld_ctl_get,
1277 },
1278 };
1279
1280 static const struct snd_soc_dapm_widget vc4_hdmi_audio_widgets[] = {
1281 SND_SOC_DAPM_OUTPUT("TX"),
1282 };
1283
1284 static const struct snd_soc_dapm_route vc4_hdmi_audio_routes[] = {
1285 { "TX", NULL, "Playback" },
1286 };
1287
1288 static const struct snd_soc_component_driver vc4_hdmi_audio_component_drv = {
1289 .name = "vc4-hdmi-codec-dai-component",
1290 .controls = vc4_hdmi_audio_controls,
1291 .num_controls = ARRAY_SIZE(vc4_hdmi_audio_controls),
1292 .dapm_widgets = vc4_hdmi_audio_widgets,
1293 .num_dapm_widgets = ARRAY_SIZE(vc4_hdmi_audio_widgets),
1294 .dapm_routes = vc4_hdmi_audio_routes,
1295 .num_dapm_routes = ARRAY_SIZE(vc4_hdmi_audio_routes),
1296 .idle_bias_on = 1,
1297 .use_pmdown_time = 1,
1298 .endianness = 1,
1299 .non_legacy_dai_naming = 1,
1300 };
1301
1302 static const struct snd_soc_dai_ops vc4_hdmi_audio_dai_ops = {
1303 .startup = vc4_hdmi_audio_startup,
1304 .shutdown = vc4_hdmi_audio_shutdown,
1305 .hw_params = vc4_hdmi_audio_hw_params,
1306 .set_fmt = vc4_hdmi_audio_set_fmt,
1307 .trigger = vc4_hdmi_audio_trigger,
1308 };
1309
1310 static struct snd_soc_dai_driver vc4_hdmi_audio_codec_dai_drv = {
1311 .name = "vc4-hdmi-hifi",
1312 .playback = {
1313 .stream_name = "Playback",
1314 .channels_min = 2,
1315 .channels_max = 8,
1316 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1317 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1318 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1319 SNDRV_PCM_RATE_192000,
1320 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1321 },
1322 };
1323
1324 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
1325 .name = "vc4-hdmi-cpu-dai-component",
1326 };
1327
vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai * dai)1328 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
1329 {
1330 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1331
1332 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
1333
1334 return 0;
1335 }
1336
1337 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
1338 .name = "vc4-hdmi-cpu-dai",
1339 .probe = vc4_hdmi_audio_cpu_dai_probe,
1340 .playback = {
1341 .stream_name = "Playback",
1342 .channels_min = 1,
1343 .channels_max = 8,
1344 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1345 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1346 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1347 SNDRV_PCM_RATE_192000,
1348 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1349 },
1350 .ops = &vc4_hdmi_audio_dai_ops,
1351 };
1352
1353 static const struct snd_dmaengine_pcm_config pcm_conf = {
1354 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
1355 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1356 };
1357
vc4_hdmi_audio_init(struct vc4_hdmi * vc4_hdmi)1358 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
1359 {
1360 const struct vc4_hdmi_register *mai_data =
1361 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
1362 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
1363 struct snd_soc_card *card = &vc4_hdmi->audio.card;
1364 struct device *dev = &vc4_hdmi->pdev->dev;
1365 const __be32 *addr;
1366 int index;
1367 int ret;
1368
1369 if (!of_find_property(dev->of_node, "dmas", NULL)) {
1370 dev_warn(dev,
1371 "'dmas' DT property is missing, no HDMI audio\n");
1372 return 0;
1373 }
1374
1375 if (mai_data->reg != VC4_HD) {
1376 WARN_ONCE(true, "MAI isn't in the HD block\n");
1377 return -EINVAL;
1378 }
1379
1380 /*
1381 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
1382 * the bus address specified in the DT, because the physical address
1383 * (the one returned by platform_get_resource()) is not appropriate
1384 * for DMA transfers.
1385 * This VC/MMU should probably be exposed to avoid this kind of hacks.
1386 */
1387 index = of_property_match_string(dev->of_node, "reg-names", "hd");
1388 /* Before BCM2711, we don't have a named register range */
1389 if (index < 0)
1390 index = 1;
1391
1392 addr = of_get_address(dev->of_node, index, NULL, NULL);
1393
1394 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
1395 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1396 vc4_hdmi->audio.dma_data.maxburst = 2;
1397
1398 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
1399 if (ret) {
1400 dev_err(dev, "Could not register PCM component: %d\n", ret);
1401 return ret;
1402 }
1403
1404 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
1405 &vc4_hdmi_audio_cpu_dai_drv, 1);
1406 if (ret) {
1407 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
1408 return ret;
1409 }
1410
1411 /* register component and codec dai */
1412 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_component_drv,
1413 &vc4_hdmi_audio_codec_dai_drv, 1);
1414 if (ret) {
1415 dev_err(dev, "Could not register component: %d\n", ret);
1416 return ret;
1417 }
1418
1419 dai_link->cpus = &vc4_hdmi->audio.cpu;
1420 dai_link->codecs = &vc4_hdmi->audio.codec;
1421 dai_link->platforms = &vc4_hdmi->audio.platform;
1422
1423 dai_link->num_cpus = 1;
1424 dai_link->num_codecs = 1;
1425 dai_link->num_platforms = 1;
1426
1427 dai_link->name = "MAI";
1428 dai_link->stream_name = "MAI PCM";
1429 dai_link->codecs->dai_name = vc4_hdmi_audio_codec_dai_drv.name;
1430 dai_link->cpus->dai_name = dev_name(dev);
1431 dai_link->codecs->name = dev_name(dev);
1432 dai_link->platforms->name = dev_name(dev);
1433
1434 card->dai_link = dai_link;
1435 card->num_links = 1;
1436 card->name = vc4_hdmi->variant->card_name;
1437 card->driver_name = "vc4-hdmi";
1438 card->dev = dev;
1439 card->owner = THIS_MODULE;
1440
1441 /*
1442 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
1443 * stores a pointer to the snd card object in dev->driver_data. This
1444 * means we cannot use it for something else. The hdmi back-pointer is
1445 * now stored in card->drvdata and should be retrieved with
1446 * snd_soc_card_get_drvdata() if needed.
1447 */
1448 snd_soc_card_set_drvdata(card, vc4_hdmi);
1449 ret = devm_snd_soc_register_card(dev, card);
1450 if (ret)
1451 dev_err(dev, "Could not register sound card: %d\n", ret);
1452
1453 return ret;
1454
1455 }
1456
1457 #ifdef CONFIG_DRM_VC4_HDMI_CEC
vc4_cec_irq_handler_rx_thread(int irq,void * priv)1458 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)
1459 {
1460 struct vc4_hdmi *vc4_hdmi = priv;
1461
1462 if (vc4_hdmi->cec_rx_msg.len)
1463 cec_received_msg(vc4_hdmi->cec_adap,
1464 &vc4_hdmi->cec_rx_msg);
1465
1466 return IRQ_HANDLED;
1467 }
1468
vc4_cec_irq_handler_tx_thread(int irq,void * priv)1469 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv)
1470 {
1471 struct vc4_hdmi *vc4_hdmi = priv;
1472
1473 if (vc4_hdmi->cec_tx_ok) {
1474 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
1475 0, 0, 0, 0);
1476 } else {
1477 /*
1478 * This CEC implementation makes 1 retry, so if we
1479 * get a NACK, then that means it made 2 attempts.
1480 */
1481 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
1482 0, 2, 0, 0);
1483 }
1484 return IRQ_HANDLED;
1485 }
1486
vc4_cec_irq_handler_thread(int irq,void * priv)1487 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
1488 {
1489 struct vc4_hdmi *vc4_hdmi = priv;
1490 irqreturn_t ret;
1491
1492 if (vc4_hdmi->cec_irq_was_rx)
1493 ret = vc4_cec_irq_handler_rx_thread(irq, priv);
1494 else
1495 ret = vc4_cec_irq_handler_tx_thread(irq, priv);
1496
1497 return ret;
1498 }
1499
vc4_cec_read_msg(struct vc4_hdmi * vc4_hdmi,u32 cntrl1)1500 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
1501 {
1502 struct drm_device *dev = vc4_hdmi->connector.dev;
1503 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
1504 unsigned int i;
1505
1506 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
1507 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
1508
1509 if (msg->len > 16) {
1510 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len);
1511 return;
1512 }
1513
1514 for (i = 0; i < msg->len; i += 4) {
1515 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
1516
1517 msg->msg[i] = val & 0xff;
1518 msg->msg[i + 1] = (val >> 8) & 0xff;
1519 msg->msg[i + 2] = (val >> 16) & 0xff;
1520 msg->msg[i + 3] = (val >> 24) & 0xff;
1521 }
1522 }
1523
vc4_cec_irq_handler_tx_bare(int irq,void * priv)1524 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv)
1525 {
1526 struct vc4_hdmi *vc4_hdmi = priv;
1527 u32 cntrl1;
1528
1529 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1530 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
1531 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1532 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1533
1534 return IRQ_WAKE_THREAD;
1535 }
1536
vc4_cec_irq_handler_rx_bare(int irq,void * priv)1537 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv)
1538 {
1539 struct vc4_hdmi *vc4_hdmi = priv;
1540 u32 cntrl1;
1541
1542 vc4_hdmi->cec_rx_msg.len = 0;
1543 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1544 vc4_cec_read_msg(vc4_hdmi, cntrl1);
1545 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1546 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1547 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1548
1549 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1550
1551 return IRQ_WAKE_THREAD;
1552 }
1553
vc4_cec_irq_handler(int irq,void * priv)1554 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
1555 {
1556 struct vc4_hdmi *vc4_hdmi = priv;
1557 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
1558 irqreturn_t ret;
1559 u32 cntrl5;
1560
1561 if (!(stat & VC4_HDMI_CPU_CEC))
1562 return IRQ_NONE;
1563
1564 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
1565 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
1566 if (vc4_hdmi->cec_irq_was_rx)
1567 ret = vc4_cec_irq_handler_rx_bare(irq, priv);
1568 else
1569 ret = vc4_cec_irq_handler_tx_bare(irq, priv);
1570
1571 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
1572 return ret;
1573 }
1574
vc4_hdmi_cec_adap_enable(struct cec_adapter * adap,bool enable)1575 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
1576 {
1577 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1578 /* clock period in microseconds */
1579 const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
1580 u32 val = HDMI_READ(HDMI_CEC_CNTRL_5);
1581
1582 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
1583 VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
1584 VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
1585 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
1586 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
1587
1588 if (enable) {
1589 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
1590 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1591 HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
1592 HDMI_WRITE(HDMI_CEC_CNTRL_2,
1593 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
1594 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
1595 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
1596 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
1597 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
1598 HDMI_WRITE(HDMI_CEC_CNTRL_3,
1599 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
1600 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
1601 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
1602 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
1603 HDMI_WRITE(HDMI_CEC_CNTRL_4,
1604 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
1605 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
1606 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
1607 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
1608
1609 if (!vc4_hdmi->variant->external_irq_controller)
1610 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
1611 } else {
1612 if (!vc4_hdmi->variant->external_irq_controller)
1613 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
1614 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
1615 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1616 }
1617 return 0;
1618 }
1619
vc4_hdmi_cec_adap_log_addr(struct cec_adapter * adap,u8 log_addr)1620 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
1621 {
1622 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1623
1624 HDMI_WRITE(HDMI_CEC_CNTRL_1,
1625 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
1626 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
1627 return 0;
1628 }
1629
vc4_hdmi_cec_adap_transmit(struct cec_adapter * adap,u8 attempts,u32 signal_free_time,struct cec_msg * msg)1630 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
1631 u32 signal_free_time, struct cec_msg *msg)
1632 {
1633 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1634 struct drm_device *dev = vc4_hdmi->connector.dev;
1635 u32 val;
1636 unsigned int i;
1637
1638 if (msg->len > 16) {
1639 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
1640 return -ENOMEM;
1641 }
1642
1643 for (i = 0; i < msg->len; i += 4)
1644 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
1645 (msg->msg[i]) |
1646 (msg->msg[i + 1] << 8) |
1647 (msg->msg[i + 2] << 16) |
1648 (msg->msg[i + 3] << 24));
1649
1650 val = HDMI_READ(HDMI_CEC_CNTRL_1);
1651 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1652 HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
1653 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
1654 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
1655 val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
1656
1657 HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
1658 return 0;
1659 }
1660
1661 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
1662 .adap_enable = vc4_hdmi_cec_adap_enable,
1663 .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
1664 .adap_transmit = vc4_hdmi_cec_adap_transmit,
1665 };
1666
vc4_hdmi_cec_init(struct vc4_hdmi * vc4_hdmi)1667 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
1668 {
1669 struct cec_connector_info conn_info;
1670 struct platform_device *pdev = vc4_hdmi->pdev;
1671 struct device *dev = &pdev->dev;
1672 u32 value;
1673 int ret;
1674
1675 if (!of_find_property(dev->of_node, "interrupts", NULL)) {
1676 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n");
1677 return 0;
1678 }
1679
1680 vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
1681 vc4_hdmi, "vc4",
1682 CEC_CAP_DEFAULTS |
1683 CEC_CAP_CONNECTOR_INFO, 1);
1684 ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
1685 if (ret < 0)
1686 return ret;
1687
1688 cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
1689 cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
1690
1691 value = HDMI_READ(HDMI_CEC_CNTRL_1);
1692 /* Set the logical address to Unregistered */
1693 value |= VC4_HDMI_CEC_ADDR_MASK;
1694 HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
1695
1696 vc4_hdmi_cec_update_clk_div(vc4_hdmi);
1697
1698 if (vc4_hdmi->variant->external_irq_controller) {
1699 ret = devm_request_threaded_irq(&pdev->dev,
1700 platform_get_irq_byname(pdev, "cec-rx"),
1701 vc4_cec_irq_handler_rx_bare,
1702 vc4_cec_irq_handler_rx_thread, 0,
1703 "vc4 hdmi cec rx", vc4_hdmi);
1704 if (ret)
1705 goto err_delete_cec_adap;
1706
1707 ret = devm_request_threaded_irq(&pdev->dev,
1708 platform_get_irq_byname(pdev, "cec-tx"),
1709 vc4_cec_irq_handler_tx_bare,
1710 vc4_cec_irq_handler_tx_thread, 0,
1711 "vc4 hdmi cec tx", vc4_hdmi);
1712 if (ret)
1713 goto err_delete_cec_adap;
1714 } else {
1715 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
1716
1717 ret = devm_request_threaded_irq(&pdev->dev, platform_get_irq(pdev, 0),
1718 vc4_cec_irq_handler,
1719 vc4_cec_irq_handler_thread, 0,
1720 "vc4 hdmi cec", vc4_hdmi);
1721 if (ret)
1722 goto err_delete_cec_adap;
1723 }
1724
1725 ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
1726 if (ret < 0)
1727 goto err_delete_cec_adap;
1728
1729 return 0;
1730
1731 err_delete_cec_adap:
1732 cec_delete_adapter(vc4_hdmi->cec_adap);
1733
1734 return ret;
1735 }
1736
vc4_hdmi_cec_exit(struct vc4_hdmi * vc4_hdmi)1737 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi)
1738 {
1739 cec_unregister_adapter(vc4_hdmi->cec_adap);
1740 }
1741 #else
vc4_hdmi_cec_init(struct vc4_hdmi * vc4_hdmi)1742 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
1743 {
1744 return 0;
1745 }
1746
vc4_hdmi_cec_exit(struct vc4_hdmi * vc4_hdmi)1747 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) {};
1748
1749 #endif
1750
vc4_hdmi_build_regset(struct vc4_hdmi * vc4_hdmi,struct debugfs_regset32 * regset,enum vc4_hdmi_regs reg)1751 static int vc4_hdmi_build_regset(struct vc4_hdmi *vc4_hdmi,
1752 struct debugfs_regset32 *regset,
1753 enum vc4_hdmi_regs reg)
1754 {
1755 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
1756 struct debugfs_reg32 *regs, *new_regs;
1757 unsigned int count = 0;
1758 unsigned int i;
1759
1760 regs = kcalloc(variant->num_registers, sizeof(*regs),
1761 GFP_KERNEL);
1762 if (!regs)
1763 return -ENOMEM;
1764
1765 for (i = 0; i < variant->num_registers; i++) {
1766 const struct vc4_hdmi_register *field = &variant->registers[i];
1767
1768 if (field->reg != reg)
1769 continue;
1770
1771 regs[count].name = field->name;
1772 regs[count].offset = field->offset;
1773 count++;
1774 }
1775
1776 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
1777 if (!new_regs)
1778 return -ENOMEM;
1779
1780 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
1781 regset->regs = new_regs;
1782 regset->nregs = count;
1783
1784 return 0;
1785 }
1786
vc4_hdmi_init_resources(struct vc4_hdmi * vc4_hdmi)1787 static int vc4_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
1788 {
1789 struct platform_device *pdev = vc4_hdmi->pdev;
1790 struct device *dev = &pdev->dev;
1791 int ret;
1792
1793 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
1794 if (IS_ERR(vc4_hdmi->hdmicore_regs))
1795 return PTR_ERR(vc4_hdmi->hdmicore_regs);
1796
1797 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
1798 if (IS_ERR(vc4_hdmi->hd_regs))
1799 return PTR_ERR(vc4_hdmi->hd_regs);
1800
1801 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
1802 if (ret)
1803 return ret;
1804
1805 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
1806 if (ret)
1807 return ret;
1808
1809 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
1810 if (IS_ERR(vc4_hdmi->pixel_clock)) {
1811 ret = PTR_ERR(vc4_hdmi->pixel_clock);
1812 if (ret != -EPROBE_DEFER)
1813 DRM_ERROR("Failed to get pixel clock\n");
1814 return ret;
1815 }
1816
1817 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
1818 if (IS_ERR(vc4_hdmi->hsm_clock)) {
1819 DRM_ERROR("Failed to get HDMI state machine clock\n");
1820 return PTR_ERR(vc4_hdmi->hsm_clock);
1821 }
1822 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
1823 vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
1824
1825 return 0;
1826 }
1827
vc5_hdmi_init_resources(struct vc4_hdmi * vc4_hdmi)1828 static int vc5_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
1829 {
1830 struct platform_device *pdev = vc4_hdmi->pdev;
1831 struct device *dev = &pdev->dev;
1832 struct resource *res;
1833
1834 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
1835 if (!res)
1836 return -ENODEV;
1837
1838 vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
1839 resource_size(res));
1840 if (!vc4_hdmi->hdmicore_regs)
1841 return -ENOMEM;
1842
1843 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
1844 if (!res)
1845 return -ENODEV;
1846
1847 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
1848 if (!vc4_hdmi->hd_regs)
1849 return -ENOMEM;
1850
1851 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
1852 if (!res)
1853 return -ENODEV;
1854
1855 vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
1856 if (!vc4_hdmi->cec_regs)
1857 return -ENOMEM;
1858
1859 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
1860 if (!res)
1861 return -ENODEV;
1862
1863 vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
1864 if (!vc4_hdmi->csc_regs)
1865 return -ENOMEM;
1866
1867 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
1868 if (!res)
1869 return -ENODEV;
1870
1871 vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
1872 if (!vc4_hdmi->dvp_regs)
1873 return -ENOMEM;
1874
1875 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
1876 if (!res)
1877 return -ENODEV;
1878
1879 vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
1880 if (!vc4_hdmi->phy_regs)
1881 return -ENOMEM;
1882
1883 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
1884 if (!res)
1885 return -ENODEV;
1886
1887 vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
1888 if (!vc4_hdmi->ram_regs)
1889 return -ENOMEM;
1890
1891 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
1892 if (!res)
1893 return -ENODEV;
1894
1895 vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
1896 if (!vc4_hdmi->rm_regs)
1897 return -ENOMEM;
1898
1899 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
1900 if (IS_ERR(vc4_hdmi->hsm_clock)) {
1901 DRM_ERROR("Failed to get HDMI state machine clock\n");
1902 return PTR_ERR(vc4_hdmi->hsm_clock);
1903 }
1904
1905 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
1906 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
1907 DRM_ERROR("Failed to get pixel bvb clock\n");
1908 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
1909 }
1910
1911 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
1912 if (IS_ERR(vc4_hdmi->audio_clock)) {
1913 DRM_ERROR("Failed to get audio clock\n");
1914 return PTR_ERR(vc4_hdmi->audio_clock);
1915 }
1916
1917 vc4_hdmi->cec_clock = devm_clk_get(dev, "cec");
1918 if (IS_ERR(vc4_hdmi->cec_clock)) {
1919 DRM_ERROR("Failed to get CEC clock\n");
1920 return PTR_ERR(vc4_hdmi->cec_clock);
1921 }
1922
1923 vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
1924 if (IS_ERR(vc4_hdmi->reset)) {
1925 DRM_ERROR("Failed to get HDMI reset line\n");
1926 return PTR_ERR(vc4_hdmi->reset);
1927 }
1928
1929 return 0;
1930 }
1931
vc4_hdmi_bind(struct device * dev,struct device * master,void * data)1932 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
1933 {
1934 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
1935 struct platform_device *pdev = to_platform_device(dev);
1936 struct drm_device *drm = dev_get_drvdata(master);
1937 struct vc4_hdmi *vc4_hdmi;
1938 struct drm_encoder *encoder;
1939 struct device_node *ddc_node;
1940 u32 value;
1941 int ret;
1942
1943 vc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL);
1944 if (!vc4_hdmi)
1945 return -ENOMEM;
1946
1947 dev_set_drvdata(dev, vc4_hdmi);
1948 encoder = &vc4_hdmi->encoder.base.base;
1949 vc4_hdmi->encoder.base.type = variant->encoder_type;
1950 vc4_hdmi->encoder.base.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
1951 vc4_hdmi->encoder.base.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
1952 vc4_hdmi->encoder.base.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
1953 vc4_hdmi->encoder.base.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
1954 vc4_hdmi->encoder.base.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
1955 vc4_hdmi->pdev = pdev;
1956 vc4_hdmi->variant = variant;
1957
1958 ret = variant->init_resources(vc4_hdmi);
1959 if (ret)
1960 return ret;
1961
1962 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
1963 if (!ddc_node) {
1964 DRM_ERROR("Failed to find ddc node in device tree\n");
1965 return -ENODEV;
1966 }
1967
1968 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
1969 of_node_put(ddc_node);
1970 if (!vc4_hdmi->ddc) {
1971 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
1972 return -EPROBE_DEFER;
1973 }
1974
1975 /* Only use the GPIO HPD pin if present in the DT, otherwise
1976 * we'll use the HDMI core's register.
1977 */
1978 if (of_find_property(dev->of_node, "hpd-gpios", &value)) {
1979 enum of_gpio_flags hpd_gpio_flags;
1980
1981 vc4_hdmi->hpd_gpio = of_get_named_gpio_flags(dev->of_node,
1982 "hpd-gpios", 0,
1983 &hpd_gpio_flags);
1984 if (vc4_hdmi->hpd_gpio < 0) {
1985 ret = vc4_hdmi->hpd_gpio;
1986 goto err_unprepare_hsm;
1987 }
1988
1989 vc4_hdmi->hpd_active_low = hpd_gpio_flags & OF_GPIO_ACTIVE_LOW;
1990 }
1991
1992 vc4_hdmi->disable_wifi_frequencies =
1993 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
1994
1995 if (vc4_hdmi->variant->reset)
1996 vc4_hdmi->variant->reset(vc4_hdmi);
1997
1998 pm_runtime_enable(dev);
1999
2000 drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
2001 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
2002
2003 ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
2004 if (ret)
2005 goto err_destroy_encoder;
2006
2007 ret = vc4_hdmi_cec_init(vc4_hdmi);
2008 if (ret)
2009 goto err_destroy_conn;
2010
2011 ret = vc4_hdmi_audio_init(vc4_hdmi);
2012 if (ret)
2013 goto err_free_cec;
2014
2015 vc4_debugfs_add_file(drm, variant->debugfs_name,
2016 vc4_hdmi_debugfs_regs,
2017 vc4_hdmi);
2018
2019 return 0;
2020
2021 err_free_cec:
2022 vc4_hdmi_cec_exit(vc4_hdmi);
2023 err_destroy_conn:
2024 vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
2025 err_destroy_encoder:
2026 drm_encoder_cleanup(encoder);
2027 err_unprepare_hsm:
2028 pm_runtime_disable(dev);
2029 put_device(&vc4_hdmi->ddc->dev);
2030
2031 return ret;
2032 }
2033
vc4_hdmi_unbind(struct device * dev,struct device * master,void * data)2034 static void vc4_hdmi_unbind(struct device *dev, struct device *master,
2035 void *data)
2036 {
2037 struct vc4_hdmi *vc4_hdmi;
2038
2039 /*
2040 * ASoC makes it a bit hard to retrieve a pointer to the
2041 * vc4_hdmi structure. Registering the card will overwrite our
2042 * device drvdata with a pointer to the snd_soc_card structure,
2043 * which can then be used to retrieve whatever drvdata we want
2044 * to associate.
2045 *
2046 * However, that doesn't fly in the case where we wouldn't
2047 * register an ASoC card (because of an old DT that is missing
2048 * the dmas properties for example), then the card isn't
2049 * registered and the device drvdata wouldn't be set.
2050 *
2051 * We can deal with both cases by making sure a snd_soc_card
2052 * pointer and a vc4_hdmi structure are pointing to the same
2053 * memory address, so we can treat them indistinctly without any
2054 * issue.
2055 */
2056 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
2057 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
2058 vc4_hdmi = dev_get_drvdata(dev);
2059
2060 kfree(vc4_hdmi->hdmi_regset.regs);
2061 kfree(vc4_hdmi->hd_regset.regs);
2062
2063 vc4_hdmi_cec_exit(vc4_hdmi);
2064 vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
2065 drm_encoder_cleanup(&vc4_hdmi->encoder.base.base);
2066
2067 pm_runtime_disable(dev);
2068
2069 put_device(&vc4_hdmi->ddc->dev);
2070 }
2071
2072 static const struct component_ops vc4_hdmi_ops = {
2073 .bind = vc4_hdmi_bind,
2074 .unbind = vc4_hdmi_unbind,
2075 };
2076
vc4_hdmi_dev_probe(struct platform_device * pdev)2077 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
2078 {
2079 return component_add(&pdev->dev, &vc4_hdmi_ops);
2080 }
2081
vc4_hdmi_dev_remove(struct platform_device * pdev)2082 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
2083 {
2084 component_del(&pdev->dev, &vc4_hdmi_ops);
2085 return 0;
2086 }
2087
2088 static const struct vc4_hdmi_variant bcm2835_variant = {
2089 .encoder_type = VC4_ENCODER_TYPE_HDMI0,
2090 .debugfs_name = "hdmi_regs",
2091 .card_name = "vc4-hdmi",
2092 .max_pixel_clock = 162000000,
2093 .registers = vc4_hdmi_fields,
2094 .num_registers = ARRAY_SIZE(vc4_hdmi_fields),
2095
2096 .init_resources = vc4_hdmi_init_resources,
2097 .csc_setup = vc4_hdmi_csc_setup,
2098 .reset = vc4_hdmi_reset,
2099 .set_timings = vc4_hdmi_set_timings,
2100 .phy_init = vc4_hdmi_phy_init,
2101 .phy_disable = vc4_hdmi_phy_disable,
2102 .phy_rng_enable = vc4_hdmi_phy_rng_enable,
2103 .phy_rng_disable = vc4_hdmi_phy_rng_disable,
2104 .channel_map = vc4_hdmi_channel_map,
2105 };
2106
2107 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
2108 .encoder_type = VC4_ENCODER_TYPE_HDMI0,
2109 .debugfs_name = "hdmi0_regs",
2110 .card_name = "vc4-hdmi-0",
2111 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK,
2112 .registers = vc5_hdmi_hdmi0_fields,
2113 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
2114 .phy_lane_mapping = {
2115 PHY_LANE_0,
2116 PHY_LANE_1,
2117 PHY_LANE_2,
2118 PHY_LANE_CK,
2119 },
2120 .unsupported_odd_h_timings = true,
2121 .external_irq_controller = true,
2122
2123 .init_resources = vc5_hdmi_init_resources,
2124 .csc_setup = vc5_hdmi_csc_setup,
2125 .reset = vc5_hdmi_reset,
2126 .set_timings = vc5_hdmi_set_timings,
2127 .phy_init = vc5_hdmi_phy_init,
2128 .phy_disable = vc5_hdmi_phy_disable,
2129 .phy_rng_enable = vc5_hdmi_phy_rng_enable,
2130 .phy_rng_disable = vc5_hdmi_phy_rng_disable,
2131 .channel_map = vc5_hdmi_channel_map,
2132 };
2133
2134 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
2135 .encoder_type = VC4_ENCODER_TYPE_HDMI1,
2136 .debugfs_name = "hdmi1_regs",
2137 .card_name = "vc4-hdmi-1",
2138 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK,
2139 .registers = vc5_hdmi_hdmi1_fields,
2140 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
2141 .phy_lane_mapping = {
2142 PHY_LANE_1,
2143 PHY_LANE_0,
2144 PHY_LANE_CK,
2145 PHY_LANE_2,
2146 },
2147 .unsupported_odd_h_timings = true,
2148 .external_irq_controller = true,
2149
2150 .init_resources = vc5_hdmi_init_resources,
2151 .csc_setup = vc5_hdmi_csc_setup,
2152 .reset = vc5_hdmi_reset,
2153 .set_timings = vc5_hdmi_set_timings,
2154 .phy_init = vc5_hdmi_phy_init,
2155 .phy_disable = vc5_hdmi_phy_disable,
2156 .phy_rng_enable = vc5_hdmi_phy_rng_enable,
2157 .phy_rng_disable = vc5_hdmi_phy_rng_disable,
2158 .channel_map = vc5_hdmi_channel_map,
2159 };
2160
2161 static const struct of_device_id vc4_hdmi_dt_match[] = {
2162 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
2163 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
2164 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
2165 {}
2166 };
2167
2168 struct platform_driver vc4_hdmi_driver = {
2169 .probe = vc4_hdmi_dev_probe,
2170 .remove = vc4_hdmi_dev_remove,
2171 .driver = {
2172 .name = "vc4_hdmi",
2173 .of_match_table = vc4_hdmi_dt_match,
2174 },
2175 };
2176