1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
3
4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
5
6 #include <linux/module.h>
7 #include <linux/types.h>
8 #include <linux/init.h>
9 #include <linux/bitops.h>
10 #include <linux/vmalloc.h>
11 #include <linux/pagemap.h>
12 #include <linux/netdevice.h>
13 #include <linux/ipv6.h>
14 #include <linux/slab.h>
15 #include <net/checksum.h>
16 #include <net/ip6_checksum.h>
17 #include <net/pkt_sched.h>
18 #include <net/pkt_cls.h>
19 #include <linux/net_tstamp.h>
20 #include <linux/mii.h>
21 #include <linux/ethtool.h>
22 #include <linux/if.h>
23 #include <linux/if_vlan.h>
24 #include <linux/pci.h>
25 #include <linux/delay.h>
26 #include <linux/interrupt.h>
27 #include <linux/ip.h>
28 #include <linux/tcp.h>
29 #include <linux/sctp.h>
30 #include <linux/if_ether.h>
31 #include <linux/aer.h>
32 #include <linux/prefetch.h>
33 #include <linux/bpf.h>
34 #include <linux/bpf_trace.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/etherdevice.h>
37 #ifdef CONFIG_IGB_DCA
38 #include <linux/dca.h>
39 #endif
40 #include <linux/i2c.h>
41 #include "igb.h"
42
43 enum queue_mode {
44 QUEUE_MODE_STRICT_PRIORITY,
45 QUEUE_MODE_STREAM_RESERVATION,
46 };
47
48 enum tx_queue_prio {
49 TX_QUEUE_PRIO_HIGH,
50 TX_QUEUE_PRIO_LOW,
51 };
52
53 char igb_driver_name[] = "igb";
54 static const char igb_driver_string[] =
55 "Intel(R) Gigabit Ethernet Network Driver";
56 static const char igb_copyright[] =
57 "Copyright (c) 2007-2014 Intel Corporation.";
58
59 static const struct e1000_info *igb_info_tbl[] = {
60 [board_82575] = &e1000_82575_info,
61 };
62
63 static const struct pci_device_id igb_pci_tbl[] = {
64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
74 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
75 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
99 /* required last entry */
100 {0, }
101 };
102
103 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
104
105 static int igb_setup_all_tx_resources(struct igb_adapter *);
106 static int igb_setup_all_rx_resources(struct igb_adapter *);
107 static void igb_free_all_tx_resources(struct igb_adapter *);
108 static void igb_free_all_rx_resources(struct igb_adapter *);
109 static void igb_setup_mrqc(struct igb_adapter *);
110 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
111 static void igb_remove(struct pci_dev *pdev);
112 static int igb_sw_init(struct igb_adapter *);
113 int igb_open(struct net_device *);
114 int igb_close(struct net_device *);
115 static void igb_configure(struct igb_adapter *);
116 static void igb_configure_tx(struct igb_adapter *);
117 static void igb_configure_rx(struct igb_adapter *);
118 static void igb_clean_all_tx_rings(struct igb_adapter *);
119 static void igb_clean_all_rx_rings(struct igb_adapter *);
120 static void igb_clean_tx_ring(struct igb_ring *);
121 static void igb_clean_rx_ring(struct igb_ring *);
122 static void igb_set_rx_mode(struct net_device *);
123 static void igb_update_phy_info(struct timer_list *);
124 static void igb_watchdog(struct timer_list *);
125 static void igb_watchdog_task(struct work_struct *);
126 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
127 static void igb_get_stats64(struct net_device *dev,
128 struct rtnl_link_stats64 *stats);
129 static int igb_change_mtu(struct net_device *, int);
130 static int igb_set_mac(struct net_device *, void *);
131 static void igb_set_uta(struct igb_adapter *adapter, bool set);
132 static irqreturn_t igb_intr(int irq, void *);
133 static irqreturn_t igb_intr_msi(int irq, void *);
134 static irqreturn_t igb_msix_other(int irq, void *);
135 static irqreturn_t igb_msix_ring(int irq, void *);
136 #ifdef CONFIG_IGB_DCA
137 static void igb_update_dca(struct igb_q_vector *);
138 static void igb_setup_dca(struct igb_adapter *);
139 #endif /* CONFIG_IGB_DCA */
140 static int igb_poll(struct napi_struct *, int);
141 static bool igb_clean_tx_irq(struct igb_q_vector *, int);
142 static int igb_clean_rx_irq(struct igb_q_vector *, int);
143 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
144 static void igb_tx_timeout(struct net_device *, unsigned int txqueue);
145 static void igb_reset_task(struct work_struct *);
146 static void igb_vlan_mode(struct net_device *netdev,
147 netdev_features_t features);
148 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
149 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
150 static void igb_restore_vlan(struct igb_adapter *);
151 static void igb_rar_set_index(struct igb_adapter *, u32);
152 static void igb_ping_all_vfs(struct igb_adapter *);
153 static void igb_msg_task(struct igb_adapter *);
154 static void igb_vmm_control(struct igb_adapter *);
155 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
156 static void igb_flush_mac_table(struct igb_adapter *);
157 static int igb_available_rars(struct igb_adapter *, u8);
158 static void igb_set_default_mac_filter(struct igb_adapter *);
159 static int igb_uc_sync(struct net_device *, const unsigned char *);
160 static int igb_uc_unsync(struct net_device *, const unsigned char *);
161 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
162 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
163 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
164 int vf, u16 vlan, u8 qos, __be16 vlan_proto);
165 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int);
166 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
167 bool setting);
168 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf,
169 bool setting);
170 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
171 struct ifla_vf_info *ivi);
172 static void igb_check_vf_rate_limit(struct igb_adapter *);
173 static void igb_nfc_filter_exit(struct igb_adapter *adapter);
174 static void igb_nfc_filter_restore(struct igb_adapter *adapter);
175
176 #ifdef CONFIG_PCI_IOV
177 static int igb_vf_configure(struct igb_adapter *adapter, int vf);
178 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs);
179 static int igb_disable_sriov(struct pci_dev *dev);
180 static int igb_pci_disable_sriov(struct pci_dev *dev);
181 #endif
182
183 static int igb_suspend(struct device *);
184 static int igb_resume(struct device *);
185 static int igb_runtime_suspend(struct device *dev);
186 static int igb_runtime_resume(struct device *dev);
187 static int igb_runtime_idle(struct device *dev);
188 static const struct dev_pm_ops igb_pm_ops = {
189 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
190 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
191 igb_runtime_idle)
192 };
193 static void igb_shutdown(struct pci_dev *);
194 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
195 #ifdef CONFIG_IGB_DCA
196 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
197 static struct notifier_block dca_notifier = {
198 .notifier_call = igb_notify_dca,
199 .next = NULL,
200 .priority = 0
201 };
202 #endif
203 #ifdef CONFIG_PCI_IOV
204 static unsigned int max_vfs;
205 module_param(max_vfs, uint, 0);
206 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function");
207 #endif /* CONFIG_PCI_IOV */
208
209 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
210 pci_channel_state_t);
211 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
212 static void igb_io_resume(struct pci_dev *);
213
214 static const struct pci_error_handlers igb_err_handler = {
215 .error_detected = igb_io_error_detected,
216 .slot_reset = igb_io_slot_reset,
217 .resume = igb_io_resume,
218 };
219
220 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
221
222 static struct pci_driver igb_driver = {
223 .name = igb_driver_name,
224 .id_table = igb_pci_tbl,
225 .probe = igb_probe,
226 .remove = igb_remove,
227 #ifdef CONFIG_PM
228 .driver.pm = &igb_pm_ops,
229 #endif
230 .shutdown = igb_shutdown,
231 .sriov_configure = igb_pci_sriov_configure,
232 .err_handler = &igb_err_handler
233 };
234
235 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
236 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
237 MODULE_LICENSE("GPL v2");
238
239 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
240 static int debug = -1;
241 module_param(debug, int, 0);
242 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
243
244 struct igb_reg_info {
245 u32 ofs;
246 char *name;
247 };
248
249 static const struct igb_reg_info igb_reg_info_tbl[] = {
250
251 /* General Registers */
252 {E1000_CTRL, "CTRL"},
253 {E1000_STATUS, "STATUS"},
254 {E1000_CTRL_EXT, "CTRL_EXT"},
255
256 /* Interrupt Registers */
257 {E1000_ICR, "ICR"},
258
259 /* RX Registers */
260 {E1000_RCTL, "RCTL"},
261 {E1000_RDLEN(0), "RDLEN"},
262 {E1000_RDH(0), "RDH"},
263 {E1000_RDT(0), "RDT"},
264 {E1000_RXDCTL(0), "RXDCTL"},
265 {E1000_RDBAL(0), "RDBAL"},
266 {E1000_RDBAH(0), "RDBAH"},
267
268 /* TX Registers */
269 {E1000_TCTL, "TCTL"},
270 {E1000_TDBAL(0), "TDBAL"},
271 {E1000_TDBAH(0), "TDBAH"},
272 {E1000_TDLEN(0), "TDLEN"},
273 {E1000_TDH(0), "TDH"},
274 {E1000_TDT(0), "TDT"},
275 {E1000_TXDCTL(0), "TXDCTL"},
276 {E1000_TDFH, "TDFH"},
277 {E1000_TDFT, "TDFT"},
278 {E1000_TDFHS, "TDFHS"},
279 {E1000_TDFPC, "TDFPC"},
280
281 /* List Terminator */
282 {}
283 };
284
285 /* igb_regdump - register printout routine */
igb_regdump(struct e1000_hw * hw,struct igb_reg_info * reginfo)286 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
287 {
288 int n = 0;
289 char rname[16];
290 u32 regs[8];
291
292 switch (reginfo->ofs) {
293 case E1000_RDLEN(0):
294 for (n = 0; n < 4; n++)
295 regs[n] = rd32(E1000_RDLEN(n));
296 break;
297 case E1000_RDH(0):
298 for (n = 0; n < 4; n++)
299 regs[n] = rd32(E1000_RDH(n));
300 break;
301 case E1000_RDT(0):
302 for (n = 0; n < 4; n++)
303 regs[n] = rd32(E1000_RDT(n));
304 break;
305 case E1000_RXDCTL(0):
306 for (n = 0; n < 4; n++)
307 regs[n] = rd32(E1000_RXDCTL(n));
308 break;
309 case E1000_RDBAL(0):
310 for (n = 0; n < 4; n++)
311 regs[n] = rd32(E1000_RDBAL(n));
312 break;
313 case E1000_RDBAH(0):
314 for (n = 0; n < 4; n++)
315 regs[n] = rd32(E1000_RDBAH(n));
316 break;
317 case E1000_TDBAL(0):
318 for (n = 0; n < 4; n++)
319 regs[n] = rd32(E1000_TDBAL(n));
320 break;
321 case E1000_TDBAH(0):
322 for (n = 0; n < 4; n++)
323 regs[n] = rd32(E1000_TDBAH(n));
324 break;
325 case E1000_TDLEN(0):
326 for (n = 0; n < 4; n++)
327 regs[n] = rd32(E1000_TDLEN(n));
328 break;
329 case E1000_TDH(0):
330 for (n = 0; n < 4; n++)
331 regs[n] = rd32(E1000_TDH(n));
332 break;
333 case E1000_TDT(0):
334 for (n = 0; n < 4; n++)
335 regs[n] = rd32(E1000_TDT(n));
336 break;
337 case E1000_TXDCTL(0):
338 for (n = 0; n < 4; n++)
339 regs[n] = rd32(E1000_TXDCTL(n));
340 break;
341 default:
342 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
343 return;
344 }
345
346 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
347 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
348 regs[2], regs[3]);
349 }
350
351 /* igb_dump - Print registers, Tx-rings and Rx-rings */
igb_dump(struct igb_adapter * adapter)352 static void igb_dump(struct igb_adapter *adapter)
353 {
354 struct net_device *netdev = adapter->netdev;
355 struct e1000_hw *hw = &adapter->hw;
356 struct igb_reg_info *reginfo;
357 struct igb_ring *tx_ring;
358 union e1000_adv_tx_desc *tx_desc;
359 struct my_u0 { u64 a; u64 b; } *u0;
360 struct igb_ring *rx_ring;
361 union e1000_adv_rx_desc *rx_desc;
362 u32 staterr;
363 u16 i, n;
364
365 if (!netif_msg_hw(adapter))
366 return;
367
368 /* Print netdevice Info */
369 if (netdev) {
370 dev_info(&adapter->pdev->dev, "Net device Info\n");
371 pr_info("Device Name state trans_start\n");
372 pr_info("%-15s %016lX %016lX\n", netdev->name,
373 netdev->state, dev_trans_start(netdev));
374 }
375
376 /* Print Registers */
377 dev_info(&adapter->pdev->dev, "Register Dump\n");
378 pr_info(" Register Name Value\n");
379 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
380 reginfo->name; reginfo++) {
381 igb_regdump(hw, reginfo);
382 }
383
384 /* Print TX Ring Summary */
385 if (!netdev || !netif_running(netdev))
386 goto exit;
387
388 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
389 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
390 for (n = 0; n < adapter->num_tx_queues; n++) {
391 struct igb_tx_buffer *buffer_info;
392 tx_ring = adapter->tx_ring[n];
393 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
394 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
395 n, tx_ring->next_to_use, tx_ring->next_to_clean,
396 (u64)dma_unmap_addr(buffer_info, dma),
397 dma_unmap_len(buffer_info, len),
398 buffer_info->next_to_watch,
399 (u64)buffer_info->time_stamp);
400 }
401
402 /* Print TX Rings */
403 if (!netif_msg_tx_done(adapter))
404 goto rx_ring_summary;
405
406 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
407
408 /* Transmit Descriptor Formats
409 *
410 * Advanced Transmit Descriptor
411 * +--------------------------------------------------------------+
412 * 0 | Buffer Address [63:0] |
413 * +--------------------------------------------------------------+
414 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
415 * +--------------------------------------------------------------+
416 * 63 46 45 40 39 38 36 35 32 31 24 15 0
417 */
418
419 for (n = 0; n < adapter->num_tx_queues; n++) {
420 tx_ring = adapter->tx_ring[n];
421 pr_info("------------------------------------\n");
422 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
423 pr_info("------------------------------------\n");
424 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n");
425
426 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
427 const char *next_desc;
428 struct igb_tx_buffer *buffer_info;
429 tx_desc = IGB_TX_DESC(tx_ring, i);
430 buffer_info = &tx_ring->tx_buffer_info[i];
431 u0 = (struct my_u0 *)tx_desc;
432 if (i == tx_ring->next_to_use &&
433 i == tx_ring->next_to_clean)
434 next_desc = " NTC/U";
435 else if (i == tx_ring->next_to_use)
436 next_desc = " NTU";
437 else if (i == tx_ring->next_to_clean)
438 next_desc = " NTC";
439 else
440 next_desc = "";
441
442 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n",
443 i, le64_to_cpu(u0->a),
444 le64_to_cpu(u0->b),
445 (u64)dma_unmap_addr(buffer_info, dma),
446 dma_unmap_len(buffer_info, len),
447 buffer_info->next_to_watch,
448 (u64)buffer_info->time_stamp,
449 buffer_info->skb, next_desc);
450
451 if (netif_msg_pktdata(adapter) && buffer_info->skb)
452 print_hex_dump(KERN_INFO, "",
453 DUMP_PREFIX_ADDRESS,
454 16, 1, buffer_info->skb->data,
455 dma_unmap_len(buffer_info, len),
456 true);
457 }
458 }
459
460 /* Print RX Rings Summary */
461 rx_ring_summary:
462 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
463 pr_info("Queue [NTU] [NTC]\n");
464 for (n = 0; n < adapter->num_rx_queues; n++) {
465 rx_ring = adapter->rx_ring[n];
466 pr_info(" %5d %5X %5X\n",
467 n, rx_ring->next_to_use, rx_ring->next_to_clean);
468 }
469
470 /* Print RX Rings */
471 if (!netif_msg_rx_status(adapter))
472 goto exit;
473
474 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
475
476 /* Advanced Receive Descriptor (Read) Format
477 * 63 1 0
478 * +-----------------------------------------------------+
479 * 0 | Packet Buffer Address [63:1] |A0/NSE|
480 * +----------------------------------------------+------+
481 * 8 | Header Buffer Address [63:1] | DD |
482 * +-----------------------------------------------------+
483 *
484 *
485 * Advanced Receive Descriptor (Write-Back) Format
486 *
487 * 63 48 47 32 31 30 21 20 17 16 4 3 0
488 * +------------------------------------------------------+
489 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
490 * | Checksum Ident | | | | Type | Type |
491 * +------------------------------------------------------+
492 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
493 * +------------------------------------------------------+
494 * 63 48 47 32 31 20 19 0
495 */
496
497 for (n = 0; n < adapter->num_rx_queues; n++) {
498 rx_ring = adapter->rx_ring[n];
499 pr_info("------------------------------------\n");
500 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
501 pr_info("------------------------------------\n");
502 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
503 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n");
504
505 for (i = 0; i < rx_ring->count; i++) {
506 const char *next_desc;
507 struct igb_rx_buffer *buffer_info;
508 buffer_info = &rx_ring->rx_buffer_info[i];
509 rx_desc = IGB_RX_DESC(rx_ring, i);
510 u0 = (struct my_u0 *)rx_desc;
511 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
512
513 if (i == rx_ring->next_to_use)
514 next_desc = " NTU";
515 else if (i == rx_ring->next_to_clean)
516 next_desc = " NTC";
517 else
518 next_desc = "";
519
520 if (staterr & E1000_RXD_STAT_DD) {
521 /* Descriptor Done */
522 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
523 "RWB", i,
524 le64_to_cpu(u0->a),
525 le64_to_cpu(u0->b),
526 next_desc);
527 } else {
528 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
529 "R ", i,
530 le64_to_cpu(u0->a),
531 le64_to_cpu(u0->b),
532 (u64)buffer_info->dma,
533 next_desc);
534
535 if (netif_msg_pktdata(adapter) &&
536 buffer_info->dma && buffer_info->page) {
537 print_hex_dump(KERN_INFO, "",
538 DUMP_PREFIX_ADDRESS,
539 16, 1,
540 page_address(buffer_info->page) +
541 buffer_info->page_offset,
542 igb_rx_bufsz(rx_ring), true);
543 }
544 }
545 }
546 }
547
548 exit:
549 return;
550 }
551
552 /**
553 * igb_get_i2c_data - Reads the I2C SDA data bit
554 * @data: opaque pointer to adapter struct
555 *
556 * Returns the I2C data bit value
557 **/
igb_get_i2c_data(void * data)558 static int igb_get_i2c_data(void *data)
559 {
560 struct igb_adapter *adapter = (struct igb_adapter *)data;
561 struct e1000_hw *hw = &adapter->hw;
562 s32 i2cctl = rd32(E1000_I2CPARAMS);
563
564 return !!(i2cctl & E1000_I2C_DATA_IN);
565 }
566
567 /**
568 * igb_set_i2c_data - Sets the I2C data bit
569 * @data: pointer to hardware structure
570 * @state: I2C data value (0 or 1) to set
571 *
572 * Sets the I2C data bit
573 **/
igb_set_i2c_data(void * data,int state)574 static void igb_set_i2c_data(void *data, int state)
575 {
576 struct igb_adapter *adapter = (struct igb_adapter *)data;
577 struct e1000_hw *hw = &adapter->hw;
578 s32 i2cctl = rd32(E1000_I2CPARAMS);
579
580 if (state)
581 i2cctl |= E1000_I2C_DATA_OUT;
582 else
583 i2cctl &= ~E1000_I2C_DATA_OUT;
584
585 i2cctl &= ~E1000_I2C_DATA_OE_N;
586 i2cctl |= E1000_I2C_CLK_OE_N;
587 wr32(E1000_I2CPARAMS, i2cctl);
588 wrfl();
589
590 }
591
592 /**
593 * igb_set_i2c_clk - Sets the I2C SCL clock
594 * @data: pointer to hardware structure
595 * @state: state to set clock
596 *
597 * Sets the I2C clock line to state
598 **/
igb_set_i2c_clk(void * data,int state)599 static void igb_set_i2c_clk(void *data, int state)
600 {
601 struct igb_adapter *adapter = (struct igb_adapter *)data;
602 struct e1000_hw *hw = &adapter->hw;
603 s32 i2cctl = rd32(E1000_I2CPARAMS);
604
605 if (state) {
606 i2cctl |= E1000_I2C_CLK_OUT;
607 i2cctl &= ~E1000_I2C_CLK_OE_N;
608 } else {
609 i2cctl &= ~E1000_I2C_CLK_OUT;
610 i2cctl &= ~E1000_I2C_CLK_OE_N;
611 }
612 wr32(E1000_I2CPARAMS, i2cctl);
613 wrfl();
614 }
615
616 /**
617 * igb_get_i2c_clk - Gets the I2C SCL clock state
618 * @data: pointer to hardware structure
619 *
620 * Gets the I2C clock state
621 **/
igb_get_i2c_clk(void * data)622 static int igb_get_i2c_clk(void *data)
623 {
624 struct igb_adapter *adapter = (struct igb_adapter *)data;
625 struct e1000_hw *hw = &adapter->hw;
626 s32 i2cctl = rd32(E1000_I2CPARAMS);
627
628 return !!(i2cctl & E1000_I2C_CLK_IN);
629 }
630
631 static const struct i2c_algo_bit_data igb_i2c_algo = {
632 .setsda = igb_set_i2c_data,
633 .setscl = igb_set_i2c_clk,
634 .getsda = igb_get_i2c_data,
635 .getscl = igb_get_i2c_clk,
636 .udelay = 5,
637 .timeout = 20,
638 };
639
640 /**
641 * igb_get_hw_dev - return device
642 * @hw: pointer to hardware structure
643 *
644 * used by hardware layer to print debugging information
645 **/
igb_get_hw_dev(struct e1000_hw * hw)646 struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
647 {
648 struct igb_adapter *adapter = hw->back;
649 return adapter->netdev;
650 }
651
652 /**
653 * igb_init_module - Driver Registration Routine
654 *
655 * igb_init_module is the first routine called when the driver is
656 * loaded. All it does is register with the PCI subsystem.
657 **/
igb_init_module(void)658 static int __init igb_init_module(void)
659 {
660 int ret;
661
662 pr_info("%s\n", igb_driver_string);
663 pr_info("%s\n", igb_copyright);
664
665 #ifdef CONFIG_IGB_DCA
666 dca_register_notify(&dca_notifier);
667 #endif
668 ret = pci_register_driver(&igb_driver);
669 return ret;
670 }
671
672 module_init(igb_init_module);
673
674 /**
675 * igb_exit_module - Driver Exit Cleanup Routine
676 *
677 * igb_exit_module is called just before the driver is removed
678 * from memory.
679 **/
igb_exit_module(void)680 static void __exit igb_exit_module(void)
681 {
682 #ifdef CONFIG_IGB_DCA
683 dca_unregister_notify(&dca_notifier);
684 #endif
685 pci_unregister_driver(&igb_driver);
686 }
687
688 module_exit(igb_exit_module);
689
690 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
691 /**
692 * igb_cache_ring_register - Descriptor ring to register mapping
693 * @adapter: board private structure to initialize
694 *
695 * Once we know the feature-set enabled for the device, we'll cache
696 * the register offset the descriptor ring is assigned to.
697 **/
igb_cache_ring_register(struct igb_adapter * adapter)698 static void igb_cache_ring_register(struct igb_adapter *adapter)
699 {
700 int i = 0, j = 0;
701 u32 rbase_offset = adapter->vfs_allocated_count;
702
703 switch (adapter->hw.mac.type) {
704 case e1000_82576:
705 /* The queues are allocated for virtualization such that VF 0
706 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
707 * In order to avoid collision we start at the first free queue
708 * and continue consuming queues in the same sequence
709 */
710 if (adapter->vfs_allocated_count) {
711 for (; i < adapter->rss_queues; i++)
712 adapter->rx_ring[i]->reg_idx = rbase_offset +
713 Q_IDX_82576(i);
714 }
715 fallthrough;
716 case e1000_82575:
717 case e1000_82580:
718 case e1000_i350:
719 case e1000_i354:
720 case e1000_i210:
721 case e1000_i211:
722 default:
723 for (; i < adapter->num_rx_queues; i++)
724 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
725 for (; j < adapter->num_tx_queues; j++)
726 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
727 break;
728 }
729 }
730
igb_rd32(struct e1000_hw * hw,u32 reg)731 u32 igb_rd32(struct e1000_hw *hw, u32 reg)
732 {
733 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw);
734 u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr);
735 u32 value = 0;
736
737 if (E1000_REMOVED(hw_addr))
738 return ~value;
739
740 value = readl(&hw_addr[reg]);
741
742 /* reads should not return all F's */
743 if (!(~value) && (!reg || !(~readl(hw_addr)))) {
744 struct net_device *netdev = igb->netdev;
745 hw->hw_addr = NULL;
746 netdev_err(netdev, "PCIe link lost\n");
747 WARN(pci_device_is_present(igb->pdev),
748 "igb: Failed to read reg 0x%x!\n", reg);
749 }
750
751 return value;
752 }
753
754 /**
755 * igb_write_ivar - configure ivar for given MSI-X vector
756 * @hw: pointer to the HW structure
757 * @msix_vector: vector number we are allocating to a given ring
758 * @index: row index of IVAR register to write within IVAR table
759 * @offset: column offset of in IVAR, should be multiple of 8
760 *
761 * This function is intended to handle the writing of the IVAR register
762 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
763 * each containing an cause allocation for an Rx and Tx ring, and a
764 * variable number of rows depending on the number of queues supported.
765 **/
igb_write_ivar(struct e1000_hw * hw,int msix_vector,int index,int offset)766 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
767 int index, int offset)
768 {
769 u32 ivar = array_rd32(E1000_IVAR0, index);
770
771 /* clear any bits that are currently set */
772 ivar &= ~((u32)0xFF << offset);
773
774 /* write vector and valid bit */
775 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
776
777 array_wr32(E1000_IVAR0, index, ivar);
778 }
779
780 #define IGB_N0_QUEUE -1
igb_assign_vector(struct igb_q_vector * q_vector,int msix_vector)781 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
782 {
783 struct igb_adapter *adapter = q_vector->adapter;
784 struct e1000_hw *hw = &adapter->hw;
785 int rx_queue = IGB_N0_QUEUE;
786 int tx_queue = IGB_N0_QUEUE;
787 u32 msixbm = 0;
788
789 if (q_vector->rx.ring)
790 rx_queue = q_vector->rx.ring->reg_idx;
791 if (q_vector->tx.ring)
792 tx_queue = q_vector->tx.ring->reg_idx;
793
794 switch (hw->mac.type) {
795 case e1000_82575:
796 /* The 82575 assigns vectors using a bitmask, which matches the
797 * bitmask for the EICR/EIMS/EIMC registers. To assign one
798 * or more queues to a vector, we write the appropriate bits
799 * into the MSIXBM register for that vector.
800 */
801 if (rx_queue > IGB_N0_QUEUE)
802 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
803 if (tx_queue > IGB_N0_QUEUE)
804 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
805 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0)
806 msixbm |= E1000_EIMS_OTHER;
807 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
808 q_vector->eims_value = msixbm;
809 break;
810 case e1000_82576:
811 /* 82576 uses a table that essentially consists of 2 columns
812 * with 8 rows. The ordering is column-major so we use the
813 * lower 3 bits as the row index, and the 4th bit as the
814 * column offset.
815 */
816 if (rx_queue > IGB_N0_QUEUE)
817 igb_write_ivar(hw, msix_vector,
818 rx_queue & 0x7,
819 (rx_queue & 0x8) << 1);
820 if (tx_queue > IGB_N0_QUEUE)
821 igb_write_ivar(hw, msix_vector,
822 tx_queue & 0x7,
823 ((tx_queue & 0x8) << 1) + 8);
824 q_vector->eims_value = BIT(msix_vector);
825 break;
826 case e1000_82580:
827 case e1000_i350:
828 case e1000_i354:
829 case e1000_i210:
830 case e1000_i211:
831 /* On 82580 and newer adapters the scheme is similar to 82576
832 * however instead of ordering column-major we have things
833 * ordered row-major. So we traverse the table by using
834 * bit 0 as the column offset, and the remaining bits as the
835 * row index.
836 */
837 if (rx_queue > IGB_N0_QUEUE)
838 igb_write_ivar(hw, msix_vector,
839 rx_queue >> 1,
840 (rx_queue & 0x1) << 4);
841 if (tx_queue > IGB_N0_QUEUE)
842 igb_write_ivar(hw, msix_vector,
843 tx_queue >> 1,
844 ((tx_queue & 0x1) << 4) + 8);
845 q_vector->eims_value = BIT(msix_vector);
846 break;
847 default:
848 BUG();
849 break;
850 }
851
852 /* add q_vector eims value to global eims_enable_mask */
853 adapter->eims_enable_mask |= q_vector->eims_value;
854
855 /* configure q_vector to set itr on first interrupt */
856 q_vector->set_itr = 1;
857 }
858
859 /**
860 * igb_configure_msix - Configure MSI-X hardware
861 * @adapter: board private structure to initialize
862 *
863 * igb_configure_msix sets up the hardware to properly
864 * generate MSI-X interrupts.
865 **/
igb_configure_msix(struct igb_adapter * adapter)866 static void igb_configure_msix(struct igb_adapter *adapter)
867 {
868 u32 tmp;
869 int i, vector = 0;
870 struct e1000_hw *hw = &adapter->hw;
871
872 adapter->eims_enable_mask = 0;
873
874 /* set vector for other causes, i.e. link changes */
875 switch (hw->mac.type) {
876 case e1000_82575:
877 tmp = rd32(E1000_CTRL_EXT);
878 /* enable MSI-X PBA support*/
879 tmp |= E1000_CTRL_EXT_PBA_CLR;
880
881 /* Auto-Mask interrupts upon ICR read. */
882 tmp |= E1000_CTRL_EXT_EIAME;
883 tmp |= E1000_CTRL_EXT_IRCA;
884
885 wr32(E1000_CTRL_EXT, tmp);
886
887 /* enable msix_other interrupt */
888 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
889 adapter->eims_other = E1000_EIMS_OTHER;
890
891 break;
892
893 case e1000_82576:
894 case e1000_82580:
895 case e1000_i350:
896 case e1000_i354:
897 case e1000_i210:
898 case e1000_i211:
899 /* Turn on MSI-X capability first, or our settings
900 * won't stick. And it will take days to debug.
901 */
902 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
903 E1000_GPIE_PBA | E1000_GPIE_EIAME |
904 E1000_GPIE_NSICR);
905
906 /* enable msix_other interrupt */
907 adapter->eims_other = BIT(vector);
908 tmp = (vector++ | E1000_IVAR_VALID) << 8;
909
910 wr32(E1000_IVAR_MISC, tmp);
911 break;
912 default:
913 /* do nothing, since nothing else supports MSI-X */
914 break;
915 } /* switch (hw->mac.type) */
916
917 adapter->eims_enable_mask |= adapter->eims_other;
918
919 for (i = 0; i < adapter->num_q_vectors; i++)
920 igb_assign_vector(adapter->q_vector[i], vector++);
921
922 wrfl();
923 }
924
925 /**
926 * igb_request_msix - Initialize MSI-X interrupts
927 * @adapter: board private structure to initialize
928 *
929 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
930 * kernel.
931 **/
igb_request_msix(struct igb_adapter * adapter)932 static int igb_request_msix(struct igb_adapter *adapter)
933 {
934 struct net_device *netdev = adapter->netdev;
935 int i, err = 0, vector = 0, free_vector = 0;
936
937 err = request_irq(adapter->msix_entries[vector].vector,
938 igb_msix_other, 0, netdev->name, adapter);
939 if (err)
940 goto err_out;
941
942 for (i = 0; i < adapter->num_q_vectors; i++) {
943 struct igb_q_vector *q_vector = adapter->q_vector[i];
944
945 vector++;
946
947 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector);
948
949 if (q_vector->rx.ring && q_vector->tx.ring)
950 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
951 q_vector->rx.ring->queue_index);
952 else if (q_vector->tx.ring)
953 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
954 q_vector->tx.ring->queue_index);
955 else if (q_vector->rx.ring)
956 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
957 q_vector->rx.ring->queue_index);
958 else
959 sprintf(q_vector->name, "%s-unused", netdev->name);
960
961 err = request_irq(adapter->msix_entries[vector].vector,
962 igb_msix_ring, 0, q_vector->name,
963 q_vector);
964 if (err)
965 goto err_free;
966 }
967
968 igb_configure_msix(adapter);
969 return 0;
970
971 err_free:
972 /* free already assigned IRQs */
973 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
974
975 vector--;
976 for (i = 0; i < vector; i++) {
977 free_irq(adapter->msix_entries[free_vector++].vector,
978 adapter->q_vector[i]);
979 }
980 err_out:
981 return err;
982 }
983
984 /**
985 * igb_free_q_vector - Free memory allocated for specific interrupt vector
986 * @adapter: board private structure to initialize
987 * @v_idx: Index of vector to be freed
988 *
989 * This function frees the memory allocated to the q_vector.
990 **/
igb_free_q_vector(struct igb_adapter * adapter,int v_idx)991 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
992 {
993 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
994
995 adapter->q_vector[v_idx] = NULL;
996
997 /* igb_get_stats64() might access the rings on this vector,
998 * we must wait a grace period before freeing it.
999 */
1000 if (q_vector)
1001 kfree_rcu(q_vector, rcu);
1002 }
1003
1004 /**
1005 * igb_reset_q_vector - Reset config for interrupt vector
1006 * @adapter: board private structure to initialize
1007 * @v_idx: Index of vector to be reset
1008 *
1009 * If NAPI is enabled it will delete any references to the
1010 * NAPI struct. This is preparation for igb_free_q_vector.
1011 **/
igb_reset_q_vector(struct igb_adapter * adapter,int v_idx)1012 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx)
1013 {
1014 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1015
1016 /* Coming from igb_set_interrupt_capability, the vectors are not yet
1017 * allocated. So, q_vector is NULL so we should stop here.
1018 */
1019 if (!q_vector)
1020 return;
1021
1022 if (q_vector->tx.ring)
1023 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1024
1025 if (q_vector->rx.ring)
1026 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL;
1027
1028 netif_napi_del(&q_vector->napi);
1029
1030 }
1031
igb_reset_interrupt_capability(struct igb_adapter * adapter)1032 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
1033 {
1034 int v_idx = adapter->num_q_vectors;
1035
1036 if (adapter->flags & IGB_FLAG_HAS_MSIX)
1037 pci_disable_msix(adapter->pdev);
1038 else if (adapter->flags & IGB_FLAG_HAS_MSI)
1039 pci_disable_msi(adapter->pdev);
1040
1041 while (v_idx--)
1042 igb_reset_q_vector(adapter, v_idx);
1043 }
1044
1045 /**
1046 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1047 * @adapter: board private structure to initialize
1048 *
1049 * This function frees the memory allocated to the q_vectors. In addition if
1050 * NAPI is enabled it will delete any references to the NAPI struct prior
1051 * to freeing the q_vector.
1052 **/
igb_free_q_vectors(struct igb_adapter * adapter)1053 static void igb_free_q_vectors(struct igb_adapter *adapter)
1054 {
1055 int v_idx = adapter->num_q_vectors;
1056
1057 adapter->num_tx_queues = 0;
1058 adapter->num_rx_queues = 0;
1059 adapter->num_q_vectors = 0;
1060
1061 while (v_idx--) {
1062 igb_reset_q_vector(adapter, v_idx);
1063 igb_free_q_vector(adapter, v_idx);
1064 }
1065 }
1066
1067 /**
1068 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1069 * @adapter: board private structure to initialize
1070 *
1071 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1072 * MSI-X interrupts allocated.
1073 */
igb_clear_interrupt_scheme(struct igb_adapter * adapter)1074 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1075 {
1076 igb_free_q_vectors(adapter);
1077 igb_reset_interrupt_capability(adapter);
1078 }
1079
1080 /**
1081 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1082 * @adapter: board private structure to initialize
1083 * @msix: boolean value of MSIX capability
1084 *
1085 * Attempt to configure interrupts using the best available
1086 * capabilities of the hardware and kernel.
1087 **/
igb_set_interrupt_capability(struct igb_adapter * adapter,bool msix)1088 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
1089 {
1090 int err;
1091 int numvecs, i;
1092
1093 if (!msix)
1094 goto msi_only;
1095 adapter->flags |= IGB_FLAG_HAS_MSIX;
1096
1097 /* Number of supported queues. */
1098 adapter->num_rx_queues = adapter->rss_queues;
1099 if (adapter->vfs_allocated_count)
1100 adapter->num_tx_queues = 1;
1101 else
1102 adapter->num_tx_queues = adapter->rss_queues;
1103
1104 /* start with one vector for every Rx queue */
1105 numvecs = adapter->num_rx_queues;
1106
1107 /* if Tx handler is separate add 1 for every Tx queue */
1108 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1109 numvecs += adapter->num_tx_queues;
1110
1111 /* store the number of vectors reserved for queues */
1112 adapter->num_q_vectors = numvecs;
1113
1114 /* add 1 vector for link status interrupts */
1115 numvecs++;
1116 for (i = 0; i < numvecs; i++)
1117 adapter->msix_entries[i].entry = i;
1118
1119 err = pci_enable_msix_range(adapter->pdev,
1120 adapter->msix_entries,
1121 numvecs,
1122 numvecs);
1123 if (err > 0)
1124 return;
1125
1126 igb_reset_interrupt_capability(adapter);
1127
1128 /* If we can't do MSI-X, try MSI */
1129 msi_only:
1130 adapter->flags &= ~IGB_FLAG_HAS_MSIX;
1131 #ifdef CONFIG_PCI_IOV
1132 /* disable SR-IOV for non MSI-X configurations */
1133 if (adapter->vf_data) {
1134 struct e1000_hw *hw = &adapter->hw;
1135 /* disable iov and allow time for transactions to clear */
1136 pci_disable_sriov(adapter->pdev);
1137 msleep(500);
1138
1139 kfree(adapter->vf_mac_list);
1140 adapter->vf_mac_list = NULL;
1141 kfree(adapter->vf_data);
1142 adapter->vf_data = NULL;
1143 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1144 wrfl();
1145 msleep(100);
1146 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1147 }
1148 #endif
1149 adapter->vfs_allocated_count = 0;
1150 adapter->rss_queues = 1;
1151 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
1152 adapter->num_rx_queues = 1;
1153 adapter->num_tx_queues = 1;
1154 adapter->num_q_vectors = 1;
1155 if (!pci_enable_msi(adapter->pdev))
1156 adapter->flags |= IGB_FLAG_HAS_MSI;
1157 }
1158
igb_add_ring(struct igb_ring * ring,struct igb_ring_container * head)1159 static void igb_add_ring(struct igb_ring *ring,
1160 struct igb_ring_container *head)
1161 {
1162 head->ring = ring;
1163 head->count++;
1164 }
1165
1166 /**
1167 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1168 * @adapter: board private structure to initialize
1169 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1170 * @v_idx: index of vector in adapter struct
1171 * @txr_count: total number of Tx rings to allocate
1172 * @txr_idx: index of first Tx ring to allocate
1173 * @rxr_count: total number of Rx rings to allocate
1174 * @rxr_idx: index of first Rx ring to allocate
1175 *
1176 * We allocate one q_vector. If allocation fails we return -ENOMEM.
1177 **/
igb_alloc_q_vector(struct igb_adapter * adapter,int v_count,int v_idx,int txr_count,int txr_idx,int rxr_count,int rxr_idx)1178 static int igb_alloc_q_vector(struct igb_adapter *adapter,
1179 int v_count, int v_idx,
1180 int txr_count, int txr_idx,
1181 int rxr_count, int rxr_idx)
1182 {
1183 struct igb_q_vector *q_vector;
1184 struct igb_ring *ring;
1185 int ring_count;
1186 size_t size;
1187
1188 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1189 if (txr_count > 1 || rxr_count > 1)
1190 return -ENOMEM;
1191
1192 ring_count = txr_count + rxr_count;
1193 size = struct_size(q_vector, ring, ring_count);
1194
1195 /* allocate q_vector and rings */
1196 q_vector = adapter->q_vector[v_idx];
1197 if (!q_vector) {
1198 q_vector = kzalloc(size, GFP_KERNEL);
1199 } else if (size > ksize(q_vector)) {
1200 kfree_rcu(q_vector, rcu);
1201 q_vector = kzalloc(size, GFP_KERNEL);
1202 } else {
1203 memset(q_vector, 0, size);
1204 }
1205 if (!q_vector)
1206 return -ENOMEM;
1207
1208 /* initialize NAPI */
1209 netif_napi_add(adapter->netdev, &q_vector->napi,
1210 igb_poll, 64);
1211
1212 /* tie q_vector and adapter together */
1213 adapter->q_vector[v_idx] = q_vector;
1214 q_vector->adapter = adapter;
1215
1216 /* initialize work limits */
1217 q_vector->tx.work_limit = adapter->tx_work_limit;
1218
1219 /* initialize ITR configuration */
1220 q_vector->itr_register = adapter->io_addr + E1000_EITR(0);
1221 q_vector->itr_val = IGB_START_ITR;
1222
1223 /* initialize pointer to rings */
1224 ring = q_vector->ring;
1225
1226 /* intialize ITR */
1227 if (rxr_count) {
1228 /* rx or rx/tx vector */
1229 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1230 q_vector->itr_val = adapter->rx_itr_setting;
1231 } else {
1232 /* tx only vector */
1233 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1234 q_vector->itr_val = adapter->tx_itr_setting;
1235 }
1236
1237 if (txr_count) {
1238 /* assign generic ring traits */
1239 ring->dev = &adapter->pdev->dev;
1240 ring->netdev = adapter->netdev;
1241
1242 /* configure backlink on ring */
1243 ring->q_vector = q_vector;
1244
1245 /* update q_vector Tx values */
1246 igb_add_ring(ring, &q_vector->tx);
1247
1248 /* For 82575, context index must be unique per ring. */
1249 if (adapter->hw.mac.type == e1000_82575)
1250 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1251
1252 /* apply Tx specific ring traits */
1253 ring->count = adapter->tx_ring_count;
1254 ring->queue_index = txr_idx;
1255
1256 ring->cbs_enable = false;
1257 ring->idleslope = 0;
1258 ring->sendslope = 0;
1259 ring->hicredit = 0;
1260 ring->locredit = 0;
1261
1262 u64_stats_init(&ring->tx_syncp);
1263 u64_stats_init(&ring->tx_syncp2);
1264
1265 /* assign ring to adapter */
1266 adapter->tx_ring[txr_idx] = ring;
1267
1268 /* push pointer to next ring */
1269 ring++;
1270 }
1271
1272 if (rxr_count) {
1273 /* assign generic ring traits */
1274 ring->dev = &adapter->pdev->dev;
1275 ring->netdev = adapter->netdev;
1276
1277 /* configure backlink on ring */
1278 ring->q_vector = q_vector;
1279
1280 /* update q_vector Rx values */
1281 igb_add_ring(ring, &q_vector->rx);
1282
1283 /* set flag indicating ring supports SCTP checksum offload */
1284 if (adapter->hw.mac.type >= e1000_82576)
1285 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
1286
1287 /* On i350, i354, i210, and i211, loopback VLAN packets
1288 * have the tag byte-swapped.
1289 */
1290 if (adapter->hw.mac.type >= e1000_i350)
1291 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
1292
1293 /* apply Rx specific ring traits */
1294 ring->count = adapter->rx_ring_count;
1295 ring->queue_index = rxr_idx;
1296
1297 u64_stats_init(&ring->rx_syncp);
1298
1299 /* assign ring to adapter */
1300 adapter->rx_ring[rxr_idx] = ring;
1301 }
1302
1303 return 0;
1304 }
1305
1306
1307 /**
1308 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1309 * @adapter: board private structure to initialize
1310 *
1311 * We allocate one q_vector per queue interrupt. If allocation fails we
1312 * return -ENOMEM.
1313 **/
igb_alloc_q_vectors(struct igb_adapter * adapter)1314 static int igb_alloc_q_vectors(struct igb_adapter *adapter)
1315 {
1316 int q_vectors = adapter->num_q_vectors;
1317 int rxr_remaining = adapter->num_rx_queues;
1318 int txr_remaining = adapter->num_tx_queues;
1319 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1320 int err;
1321
1322 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1323 for (; rxr_remaining; v_idx++) {
1324 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1325 0, 0, 1, rxr_idx);
1326
1327 if (err)
1328 goto err_out;
1329
1330 /* update counts and index */
1331 rxr_remaining--;
1332 rxr_idx++;
1333 }
1334 }
1335
1336 for (; v_idx < q_vectors; v_idx++) {
1337 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1338 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1339
1340 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1341 tqpv, txr_idx, rqpv, rxr_idx);
1342
1343 if (err)
1344 goto err_out;
1345
1346 /* update counts and index */
1347 rxr_remaining -= rqpv;
1348 txr_remaining -= tqpv;
1349 rxr_idx++;
1350 txr_idx++;
1351 }
1352
1353 return 0;
1354
1355 err_out:
1356 adapter->num_tx_queues = 0;
1357 adapter->num_rx_queues = 0;
1358 adapter->num_q_vectors = 0;
1359
1360 while (v_idx--)
1361 igb_free_q_vector(adapter, v_idx);
1362
1363 return -ENOMEM;
1364 }
1365
1366 /**
1367 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1368 * @adapter: board private structure to initialize
1369 * @msix: boolean value of MSIX capability
1370 *
1371 * This function initializes the interrupts and allocates all of the queues.
1372 **/
igb_init_interrupt_scheme(struct igb_adapter * adapter,bool msix)1373 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
1374 {
1375 struct pci_dev *pdev = adapter->pdev;
1376 int err;
1377
1378 igb_set_interrupt_capability(adapter, msix);
1379
1380 err = igb_alloc_q_vectors(adapter);
1381 if (err) {
1382 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1383 goto err_alloc_q_vectors;
1384 }
1385
1386 igb_cache_ring_register(adapter);
1387
1388 return 0;
1389
1390 err_alloc_q_vectors:
1391 igb_reset_interrupt_capability(adapter);
1392 return err;
1393 }
1394
1395 /**
1396 * igb_request_irq - initialize interrupts
1397 * @adapter: board private structure to initialize
1398 *
1399 * Attempts to configure interrupts using the best available
1400 * capabilities of the hardware and kernel.
1401 **/
igb_request_irq(struct igb_adapter * adapter)1402 static int igb_request_irq(struct igb_adapter *adapter)
1403 {
1404 struct net_device *netdev = adapter->netdev;
1405 struct pci_dev *pdev = adapter->pdev;
1406 int err = 0;
1407
1408 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1409 err = igb_request_msix(adapter);
1410 if (!err)
1411 goto request_done;
1412 /* fall back to MSI */
1413 igb_free_all_tx_resources(adapter);
1414 igb_free_all_rx_resources(adapter);
1415
1416 igb_clear_interrupt_scheme(adapter);
1417 err = igb_init_interrupt_scheme(adapter, false);
1418 if (err)
1419 goto request_done;
1420
1421 igb_setup_all_tx_resources(adapter);
1422 igb_setup_all_rx_resources(adapter);
1423 igb_configure(adapter);
1424 }
1425
1426 igb_assign_vector(adapter->q_vector[0], 0);
1427
1428 if (adapter->flags & IGB_FLAG_HAS_MSI) {
1429 err = request_irq(pdev->irq, igb_intr_msi, 0,
1430 netdev->name, adapter);
1431 if (!err)
1432 goto request_done;
1433
1434 /* fall back to legacy interrupts */
1435 igb_reset_interrupt_capability(adapter);
1436 adapter->flags &= ~IGB_FLAG_HAS_MSI;
1437 }
1438
1439 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
1440 netdev->name, adapter);
1441
1442 if (err)
1443 dev_err(&pdev->dev, "Error %d getting interrupt\n",
1444 err);
1445
1446 request_done:
1447 return err;
1448 }
1449
igb_free_irq(struct igb_adapter * adapter)1450 static void igb_free_irq(struct igb_adapter *adapter)
1451 {
1452 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1453 int vector = 0, i;
1454
1455 free_irq(adapter->msix_entries[vector++].vector, adapter);
1456
1457 for (i = 0; i < adapter->num_q_vectors; i++)
1458 free_irq(adapter->msix_entries[vector++].vector,
1459 adapter->q_vector[i]);
1460 } else {
1461 free_irq(adapter->pdev->irq, adapter);
1462 }
1463 }
1464
1465 /**
1466 * igb_irq_disable - Mask off interrupt generation on the NIC
1467 * @adapter: board private structure
1468 **/
igb_irq_disable(struct igb_adapter * adapter)1469 static void igb_irq_disable(struct igb_adapter *adapter)
1470 {
1471 struct e1000_hw *hw = &adapter->hw;
1472
1473 /* we need to be careful when disabling interrupts. The VFs are also
1474 * mapped into these registers and so clearing the bits can cause
1475 * issues on the VF drivers so we only need to clear what we set
1476 */
1477 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1478 u32 regval = rd32(E1000_EIAM);
1479
1480 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1481 wr32(E1000_EIMC, adapter->eims_enable_mask);
1482 regval = rd32(E1000_EIAC);
1483 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
1484 }
1485
1486 wr32(E1000_IAM, 0);
1487 wr32(E1000_IMC, ~0);
1488 wrfl();
1489 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1490 int i;
1491
1492 for (i = 0; i < adapter->num_q_vectors; i++)
1493 synchronize_irq(adapter->msix_entries[i].vector);
1494 } else {
1495 synchronize_irq(adapter->pdev->irq);
1496 }
1497 }
1498
1499 /**
1500 * igb_irq_enable - Enable default interrupt generation settings
1501 * @adapter: board private structure
1502 **/
igb_irq_enable(struct igb_adapter * adapter)1503 static void igb_irq_enable(struct igb_adapter *adapter)
1504 {
1505 struct e1000_hw *hw = &adapter->hw;
1506
1507 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1508 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
1509 u32 regval = rd32(E1000_EIAC);
1510
1511 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1512 regval = rd32(E1000_EIAM);
1513 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
1514 wr32(E1000_EIMS, adapter->eims_enable_mask);
1515 if (adapter->vfs_allocated_count) {
1516 wr32(E1000_MBVFIMR, 0xFF);
1517 ims |= E1000_IMS_VMMB;
1518 }
1519 wr32(E1000_IMS, ims);
1520 } else {
1521 wr32(E1000_IMS, IMS_ENABLE_MASK |
1522 E1000_IMS_DRSTA);
1523 wr32(E1000_IAM, IMS_ENABLE_MASK |
1524 E1000_IMS_DRSTA);
1525 }
1526 }
1527
igb_update_mng_vlan(struct igb_adapter * adapter)1528 static void igb_update_mng_vlan(struct igb_adapter *adapter)
1529 {
1530 struct e1000_hw *hw = &adapter->hw;
1531 u16 pf_id = adapter->vfs_allocated_count;
1532 u16 vid = adapter->hw.mng_cookie.vlan_id;
1533 u16 old_vid = adapter->mng_vlan_id;
1534
1535 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1536 /* add VID to filter table */
1537 igb_vfta_set(hw, vid, pf_id, true, true);
1538 adapter->mng_vlan_id = vid;
1539 } else {
1540 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1541 }
1542
1543 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1544 (vid != old_vid) &&
1545 !test_bit(old_vid, adapter->active_vlans)) {
1546 /* remove VID from filter table */
1547 igb_vfta_set(hw, vid, pf_id, false, true);
1548 }
1549 }
1550
1551 /**
1552 * igb_release_hw_control - release control of the h/w to f/w
1553 * @adapter: address of board private structure
1554 *
1555 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1556 * For ASF and Pass Through versions of f/w this means that the
1557 * driver is no longer loaded.
1558 **/
igb_release_hw_control(struct igb_adapter * adapter)1559 static void igb_release_hw_control(struct igb_adapter *adapter)
1560 {
1561 struct e1000_hw *hw = &adapter->hw;
1562 u32 ctrl_ext;
1563
1564 /* Let firmware take over control of h/w */
1565 ctrl_ext = rd32(E1000_CTRL_EXT);
1566 wr32(E1000_CTRL_EXT,
1567 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1568 }
1569
1570 /**
1571 * igb_get_hw_control - get control of the h/w from f/w
1572 * @adapter: address of board private structure
1573 *
1574 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1575 * For ASF and Pass Through versions of f/w this means that
1576 * the driver is loaded.
1577 **/
igb_get_hw_control(struct igb_adapter * adapter)1578 static void igb_get_hw_control(struct igb_adapter *adapter)
1579 {
1580 struct e1000_hw *hw = &adapter->hw;
1581 u32 ctrl_ext;
1582
1583 /* Let firmware know the driver has taken over */
1584 ctrl_ext = rd32(E1000_CTRL_EXT);
1585 wr32(E1000_CTRL_EXT,
1586 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1587 }
1588
enable_fqtss(struct igb_adapter * adapter,bool enable)1589 static void enable_fqtss(struct igb_adapter *adapter, bool enable)
1590 {
1591 struct net_device *netdev = adapter->netdev;
1592 struct e1000_hw *hw = &adapter->hw;
1593
1594 WARN_ON(hw->mac.type != e1000_i210);
1595
1596 if (enable)
1597 adapter->flags |= IGB_FLAG_FQTSS;
1598 else
1599 adapter->flags &= ~IGB_FLAG_FQTSS;
1600
1601 if (netif_running(netdev))
1602 schedule_work(&adapter->reset_task);
1603 }
1604
is_fqtss_enabled(struct igb_adapter * adapter)1605 static bool is_fqtss_enabled(struct igb_adapter *adapter)
1606 {
1607 return (adapter->flags & IGB_FLAG_FQTSS) ? true : false;
1608 }
1609
set_tx_desc_fetch_prio(struct e1000_hw * hw,int queue,enum tx_queue_prio prio)1610 static void set_tx_desc_fetch_prio(struct e1000_hw *hw, int queue,
1611 enum tx_queue_prio prio)
1612 {
1613 u32 val;
1614
1615 WARN_ON(hw->mac.type != e1000_i210);
1616 WARN_ON(queue < 0 || queue > 4);
1617
1618 val = rd32(E1000_I210_TXDCTL(queue));
1619
1620 if (prio == TX_QUEUE_PRIO_HIGH)
1621 val |= E1000_TXDCTL_PRIORITY;
1622 else
1623 val &= ~E1000_TXDCTL_PRIORITY;
1624
1625 wr32(E1000_I210_TXDCTL(queue), val);
1626 }
1627
set_queue_mode(struct e1000_hw * hw,int queue,enum queue_mode mode)1628 static void set_queue_mode(struct e1000_hw *hw, int queue, enum queue_mode mode)
1629 {
1630 u32 val;
1631
1632 WARN_ON(hw->mac.type != e1000_i210);
1633 WARN_ON(queue < 0 || queue > 1);
1634
1635 val = rd32(E1000_I210_TQAVCC(queue));
1636
1637 if (mode == QUEUE_MODE_STREAM_RESERVATION)
1638 val |= E1000_TQAVCC_QUEUEMODE;
1639 else
1640 val &= ~E1000_TQAVCC_QUEUEMODE;
1641
1642 wr32(E1000_I210_TQAVCC(queue), val);
1643 }
1644
is_any_cbs_enabled(struct igb_adapter * adapter)1645 static bool is_any_cbs_enabled(struct igb_adapter *adapter)
1646 {
1647 int i;
1648
1649 for (i = 0; i < adapter->num_tx_queues; i++) {
1650 if (adapter->tx_ring[i]->cbs_enable)
1651 return true;
1652 }
1653
1654 return false;
1655 }
1656
is_any_txtime_enabled(struct igb_adapter * adapter)1657 static bool is_any_txtime_enabled(struct igb_adapter *adapter)
1658 {
1659 int i;
1660
1661 for (i = 0; i < adapter->num_tx_queues; i++) {
1662 if (adapter->tx_ring[i]->launchtime_enable)
1663 return true;
1664 }
1665
1666 return false;
1667 }
1668
1669 /**
1670 * igb_config_tx_modes - Configure "Qav Tx mode" features on igb
1671 * @adapter: pointer to adapter struct
1672 * @queue: queue number
1673 *
1674 * Configure CBS and Launchtime for a given hardware queue.
1675 * Parameters are retrieved from the correct Tx ring, so
1676 * igb_save_cbs_params() and igb_save_txtime_params() should be used
1677 * for setting those correctly prior to this function being called.
1678 **/
igb_config_tx_modes(struct igb_adapter * adapter,int queue)1679 static void igb_config_tx_modes(struct igb_adapter *adapter, int queue)
1680 {
1681 struct igb_ring *ring = adapter->tx_ring[queue];
1682 struct net_device *netdev = adapter->netdev;
1683 struct e1000_hw *hw = &adapter->hw;
1684 u32 tqavcc, tqavctrl;
1685 u16 value;
1686
1687 WARN_ON(hw->mac.type != e1000_i210);
1688 WARN_ON(queue < 0 || queue > 1);
1689
1690 /* If any of the Qav features is enabled, configure queues as SR and
1691 * with HIGH PRIO. If none is, then configure them with LOW PRIO and
1692 * as SP.
1693 */
1694 if (ring->cbs_enable || ring->launchtime_enable) {
1695 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_HIGH);
1696 set_queue_mode(hw, queue, QUEUE_MODE_STREAM_RESERVATION);
1697 } else {
1698 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_LOW);
1699 set_queue_mode(hw, queue, QUEUE_MODE_STRICT_PRIORITY);
1700 }
1701
1702 /* If CBS is enabled, set DataTranARB and config its parameters. */
1703 if (ring->cbs_enable || queue == 0) {
1704 /* i210 does not allow the queue 0 to be in the Strict
1705 * Priority mode while the Qav mode is enabled, so,
1706 * instead of disabling strict priority mode, we give
1707 * queue 0 the maximum of credits possible.
1708 *
1709 * See section 8.12.19 of the i210 datasheet, "Note:
1710 * Queue0 QueueMode must be set to 1b when
1711 * TransmitMode is set to Qav."
1712 */
1713 if (queue == 0 && !ring->cbs_enable) {
1714 /* max "linkspeed" idleslope in kbps */
1715 ring->idleslope = 1000000;
1716 ring->hicredit = ETH_FRAME_LEN;
1717 }
1718
1719 /* Always set data transfer arbitration to credit-based
1720 * shaper algorithm on TQAVCTRL if CBS is enabled for any of
1721 * the queues.
1722 */
1723 tqavctrl = rd32(E1000_I210_TQAVCTRL);
1724 tqavctrl |= E1000_TQAVCTRL_DATATRANARB;
1725 wr32(E1000_I210_TQAVCTRL, tqavctrl);
1726
1727 /* According to i210 datasheet section 7.2.7.7, we should set
1728 * the 'idleSlope' field from TQAVCC register following the
1729 * equation:
1730 *
1731 * For 100 Mbps link speed:
1732 *
1733 * value = BW * 0x7735 * 0.2 (E1)
1734 *
1735 * For 1000Mbps link speed:
1736 *
1737 * value = BW * 0x7735 * 2 (E2)
1738 *
1739 * E1 and E2 can be merged into one equation as shown below.
1740 * Note that 'link-speed' is in Mbps.
1741 *
1742 * value = BW * 0x7735 * 2 * link-speed
1743 * -------------- (E3)
1744 * 1000
1745 *
1746 * 'BW' is the percentage bandwidth out of full link speed
1747 * which can be found with the following equation. Note that
1748 * idleSlope here is the parameter from this function which
1749 * is in kbps.
1750 *
1751 * BW = idleSlope
1752 * ----------------- (E4)
1753 * link-speed * 1000
1754 *
1755 * That said, we can come up with a generic equation to
1756 * calculate the value we should set it TQAVCC register by
1757 * replacing 'BW' in E3 by E4. The resulting equation is:
1758 *
1759 * value = idleSlope * 0x7735 * 2 * link-speed
1760 * ----------------- -------------- (E5)
1761 * link-speed * 1000 1000
1762 *
1763 * 'link-speed' is present in both sides of the fraction so
1764 * it is canceled out. The final equation is the following:
1765 *
1766 * value = idleSlope * 61034
1767 * ----------------- (E6)
1768 * 1000000
1769 *
1770 * NOTE: For i210, given the above, we can see that idleslope
1771 * is represented in 16.38431 kbps units by the value at
1772 * the TQAVCC register (1Gbps / 61034), which reduces
1773 * the granularity for idleslope increments.
1774 * For instance, if you want to configure a 2576kbps
1775 * idleslope, the value to be written on the register
1776 * would have to be 157.23. If rounded down, you end
1777 * up with less bandwidth available than originally
1778 * required (~2572 kbps). If rounded up, you end up
1779 * with a higher bandwidth (~2589 kbps). Below the
1780 * approach we take is to always round up the
1781 * calculated value, so the resulting bandwidth might
1782 * be slightly higher for some configurations.
1783 */
1784 value = DIV_ROUND_UP_ULL(ring->idleslope * 61034ULL, 1000000);
1785
1786 tqavcc = rd32(E1000_I210_TQAVCC(queue));
1787 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK;
1788 tqavcc |= value;
1789 wr32(E1000_I210_TQAVCC(queue), tqavcc);
1790
1791 wr32(E1000_I210_TQAVHC(queue),
1792 0x80000000 + ring->hicredit * 0x7735);
1793 } else {
1794
1795 /* Set idleSlope to zero. */
1796 tqavcc = rd32(E1000_I210_TQAVCC(queue));
1797 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK;
1798 wr32(E1000_I210_TQAVCC(queue), tqavcc);
1799
1800 /* Set hiCredit to zero. */
1801 wr32(E1000_I210_TQAVHC(queue), 0);
1802
1803 /* If CBS is not enabled for any queues anymore, then return to
1804 * the default state of Data Transmission Arbitration on
1805 * TQAVCTRL.
1806 */
1807 if (!is_any_cbs_enabled(adapter)) {
1808 tqavctrl = rd32(E1000_I210_TQAVCTRL);
1809 tqavctrl &= ~E1000_TQAVCTRL_DATATRANARB;
1810 wr32(E1000_I210_TQAVCTRL, tqavctrl);
1811 }
1812 }
1813
1814 /* If LaunchTime is enabled, set DataTranTIM. */
1815 if (ring->launchtime_enable) {
1816 /* Always set DataTranTIM on TQAVCTRL if LaunchTime is enabled
1817 * for any of the SR queues, and configure fetchtime delta.
1818 * XXX NOTE:
1819 * - LaunchTime will be enabled for all SR queues.
1820 * - A fixed offset can be added relative to the launch
1821 * time of all packets if configured at reg LAUNCH_OS0.
1822 * We are keeping it as 0 for now (default value).
1823 */
1824 tqavctrl = rd32(E1000_I210_TQAVCTRL);
1825 tqavctrl |= E1000_TQAVCTRL_DATATRANTIM |
1826 E1000_TQAVCTRL_FETCHTIME_DELTA;
1827 wr32(E1000_I210_TQAVCTRL, tqavctrl);
1828 } else {
1829 /* If Launchtime is not enabled for any SR queues anymore,
1830 * then clear DataTranTIM on TQAVCTRL and clear fetchtime delta,
1831 * effectively disabling Launchtime.
1832 */
1833 if (!is_any_txtime_enabled(adapter)) {
1834 tqavctrl = rd32(E1000_I210_TQAVCTRL);
1835 tqavctrl &= ~E1000_TQAVCTRL_DATATRANTIM;
1836 tqavctrl &= ~E1000_TQAVCTRL_FETCHTIME_DELTA;
1837 wr32(E1000_I210_TQAVCTRL, tqavctrl);
1838 }
1839 }
1840
1841 /* XXX: In i210 controller the sendSlope and loCredit parameters from
1842 * CBS are not configurable by software so we don't do any 'controller
1843 * configuration' in respect to these parameters.
1844 */
1845
1846 netdev_dbg(netdev, "Qav Tx mode: cbs %s, launchtime %s, queue %d idleslope %d sendslope %d hiCredit %d locredit %d\n",
1847 ring->cbs_enable ? "enabled" : "disabled",
1848 ring->launchtime_enable ? "enabled" : "disabled",
1849 queue,
1850 ring->idleslope, ring->sendslope,
1851 ring->hicredit, ring->locredit);
1852 }
1853
igb_save_txtime_params(struct igb_adapter * adapter,int queue,bool enable)1854 static int igb_save_txtime_params(struct igb_adapter *adapter, int queue,
1855 bool enable)
1856 {
1857 struct igb_ring *ring;
1858
1859 if (queue < 0 || queue > adapter->num_tx_queues)
1860 return -EINVAL;
1861
1862 ring = adapter->tx_ring[queue];
1863 ring->launchtime_enable = enable;
1864
1865 return 0;
1866 }
1867
igb_save_cbs_params(struct igb_adapter * adapter,int queue,bool enable,int idleslope,int sendslope,int hicredit,int locredit)1868 static int igb_save_cbs_params(struct igb_adapter *adapter, int queue,
1869 bool enable, int idleslope, int sendslope,
1870 int hicredit, int locredit)
1871 {
1872 struct igb_ring *ring;
1873
1874 if (queue < 0 || queue > adapter->num_tx_queues)
1875 return -EINVAL;
1876
1877 ring = adapter->tx_ring[queue];
1878
1879 ring->cbs_enable = enable;
1880 ring->idleslope = idleslope;
1881 ring->sendslope = sendslope;
1882 ring->hicredit = hicredit;
1883 ring->locredit = locredit;
1884
1885 return 0;
1886 }
1887
1888 /**
1889 * igb_setup_tx_mode - Switch to/from Qav Tx mode when applicable
1890 * @adapter: pointer to adapter struct
1891 *
1892 * Configure TQAVCTRL register switching the controller's Tx mode
1893 * if FQTSS mode is enabled or disabled. Additionally, will issue
1894 * a call to igb_config_tx_modes() per queue so any previously saved
1895 * Tx parameters are applied.
1896 **/
igb_setup_tx_mode(struct igb_adapter * adapter)1897 static void igb_setup_tx_mode(struct igb_adapter *adapter)
1898 {
1899 struct net_device *netdev = adapter->netdev;
1900 struct e1000_hw *hw = &adapter->hw;
1901 u32 val;
1902
1903 /* Only i210 controller supports changing the transmission mode. */
1904 if (hw->mac.type != e1000_i210)
1905 return;
1906
1907 if (is_fqtss_enabled(adapter)) {
1908 int i, max_queue;
1909
1910 /* Configure TQAVCTRL register: set transmit mode to 'Qav',
1911 * set data fetch arbitration to 'round robin', set SP_WAIT_SR
1912 * so SP queues wait for SR ones.
1913 */
1914 val = rd32(E1000_I210_TQAVCTRL);
1915 val |= E1000_TQAVCTRL_XMIT_MODE | E1000_TQAVCTRL_SP_WAIT_SR;
1916 val &= ~E1000_TQAVCTRL_DATAFETCHARB;
1917 wr32(E1000_I210_TQAVCTRL, val);
1918
1919 /* Configure Tx and Rx packet buffers sizes as described in
1920 * i210 datasheet section 7.2.7.7.
1921 */
1922 val = rd32(E1000_TXPBS);
1923 val &= ~I210_TXPBSIZE_MASK;
1924 val |= I210_TXPBSIZE_PB0_6KB | I210_TXPBSIZE_PB1_6KB |
1925 I210_TXPBSIZE_PB2_6KB | I210_TXPBSIZE_PB3_6KB;
1926 wr32(E1000_TXPBS, val);
1927
1928 val = rd32(E1000_RXPBS);
1929 val &= ~I210_RXPBSIZE_MASK;
1930 val |= I210_RXPBSIZE_PB_30KB;
1931 wr32(E1000_RXPBS, val);
1932
1933 /* Section 8.12.9 states that MAX_TPKT_SIZE from DTXMXPKTSZ
1934 * register should not exceed the buffer size programmed in
1935 * TXPBS. The smallest buffer size programmed in TXPBS is 4kB
1936 * so according to the datasheet we should set MAX_TPKT_SIZE to
1937 * 4kB / 64.
1938 *
1939 * However, when we do so, no frame from queue 2 and 3 are
1940 * transmitted. It seems the MAX_TPKT_SIZE should not be great
1941 * or _equal_ to the buffer size programmed in TXPBS. For this
1942 * reason, we set set MAX_ TPKT_SIZE to (4kB - 1) / 64.
1943 */
1944 val = (4096 - 1) / 64;
1945 wr32(E1000_I210_DTXMXPKTSZ, val);
1946
1947 /* Since FQTSS mode is enabled, apply any CBS configuration
1948 * previously set. If no previous CBS configuration has been
1949 * done, then the initial configuration is applied, which means
1950 * CBS is disabled.
1951 */
1952 max_queue = (adapter->num_tx_queues < I210_SR_QUEUES_NUM) ?
1953 adapter->num_tx_queues : I210_SR_QUEUES_NUM;
1954
1955 for (i = 0; i < max_queue; i++) {
1956 igb_config_tx_modes(adapter, i);
1957 }
1958 } else {
1959 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
1960 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
1961 wr32(E1000_I210_DTXMXPKTSZ, I210_DTXMXPKTSZ_DEFAULT);
1962
1963 val = rd32(E1000_I210_TQAVCTRL);
1964 /* According to Section 8.12.21, the other flags we've set when
1965 * enabling FQTSS are not relevant when disabling FQTSS so we
1966 * don't set they here.
1967 */
1968 val &= ~E1000_TQAVCTRL_XMIT_MODE;
1969 wr32(E1000_I210_TQAVCTRL, val);
1970 }
1971
1972 netdev_dbg(netdev, "FQTSS %s\n", (is_fqtss_enabled(adapter)) ?
1973 "enabled" : "disabled");
1974 }
1975
1976 /**
1977 * igb_configure - configure the hardware for RX and TX
1978 * @adapter: private board structure
1979 **/
igb_configure(struct igb_adapter * adapter)1980 static void igb_configure(struct igb_adapter *adapter)
1981 {
1982 struct net_device *netdev = adapter->netdev;
1983 int i;
1984
1985 igb_get_hw_control(adapter);
1986 igb_set_rx_mode(netdev);
1987 igb_setup_tx_mode(adapter);
1988
1989 igb_restore_vlan(adapter);
1990
1991 igb_setup_tctl(adapter);
1992 igb_setup_mrqc(adapter);
1993 igb_setup_rctl(adapter);
1994
1995 igb_nfc_filter_restore(adapter);
1996 igb_configure_tx(adapter);
1997 igb_configure_rx(adapter);
1998
1999 igb_rx_fifo_flush_82575(&adapter->hw);
2000
2001 /* call igb_desc_unused which always leaves
2002 * at least 1 descriptor unused to make sure
2003 * next_to_use != next_to_clean
2004 */
2005 for (i = 0; i < adapter->num_rx_queues; i++) {
2006 struct igb_ring *ring = adapter->rx_ring[i];
2007 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
2008 }
2009 }
2010
2011 /**
2012 * igb_power_up_link - Power up the phy/serdes link
2013 * @adapter: address of board private structure
2014 **/
igb_power_up_link(struct igb_adapter * adapter)2015 void igb_power_up_link(struct igb_adapter *adapter)
2016 {
2017 igb_reset_phy(&adapter->hw);
2018
2019 if (adapter->hw.phy.media_type == e1000_media_type_copper)
2020 igb_power_up_phy_copper(&adapter->hw);
2021 else
2022 igb_power_up_serdes_link_82575(&adapter->hw);
2023
2024 igb_setup_link(&adapter->hw);
2025 }
2026
2027 /**
2028 * igb_power_down_link - Power down the phy/serdes link
2029 * @adapter: address of board private structure
2030 */
igb_power_down_link(struct igb_adapter * adapter)2031 static void igb_power_down_link(struct igb_adapter *adapter)
2032 {
2033 if (adapter->hw.phy.media_type == e1000_media_type_copper)
2034 igb_power_down_phy_copper_82575(&adapter->hw);
2035 else
2036 igb_shutdown_serdes_link_82575(&adapter->hw);
2037 }
2038
2039 /**
2040 * igb_check_swap_media - Detect and switch function for Media Auto Sense
2041 * @adapter: address of the board private structure
2042 **/
igb_check_swap_media(struct igb_adapter * adapter)2043 static void igb_check_swap_media(struct igb_adapter *adapter)
2044 {
2045 struct e1000_hw *hw = &adapter->hw;
2046 u32 ctrl_ext, connsw;
2047 bool swap_now = false;
2048
2049 ctrl_ext = rd32(E1000_CTRL_EXT);
2050 connsw = rd32(E1000_CONNSW);
2051
2052 /* need to live swap if current media is copper and we have fiber/serdes
2053 * to go to.
2054 */
2055
2056 if ((hw->phy.media_type == e1000_media_type_copper) &&
2057 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) {
2058 swap_now = true;
2059 } else if ((hw->phy.media_type != e1000_media_type_copper) &&
2060 !(connsw & E1000_CONNSW_SERDESD)) {
2061 /* copper signal takes time to appear */
2062 if (adapter->copper_tries < 4) {
2063 adapter->copper_tries++;
2064 connsw |= E1000_CONNSW_AUTOSENSE_CONF;
2065 wr32(E1000_CONNSW, connsw);
2066 return;
2067 } else {
2068 adapter->copper_tries = 0;
2069 if ((connsw & E1000_CONNSW_PHYSD) &&
2070 (!(connsw & E1000_CONNSW_PHY_PDN))) {
2071 swap_now = true;
2072 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF;
2073 wr32(E1000_CONNSW, connsw);
2074 }
2075 }
2076 }
2077
2078 if (!swap_now)
2079 return;
2080
2081 switch (hw->phy.media_type) {
2082 case e1000_media_type_copper:
2083 netdev_info(adapter->netdev,
2084 "MAS: changing media to fiber/serdes\n");
2085 ctrl_ext |=
2086 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
2087 adapter->flags |= IGB_FLAG_MEDIA_RESET;
2088 adapter->copper_tries = 0;
2089 break;
2090 case e1000_media_type_internal_serdes:
2091 case e1000_media_type_fiber:
2092 netdev_info(adapter->netdev,
2093 "MAS: changing media to copper\n");
2094 ctrl_ext &=
2095 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
2096 adapter->flags |= IGB_FLAG_MEDIA_RESET;
2097 break;
2098 default:
2099 /* shouldn't get here during regular operation */
2100 netdev_err(adapter->netdev,
2101 "AMS: Invalid media type found, returning\n");
2102 break;
2103 }
2104 wr32(E1000_CTRL_EXT, ctrl_ext);
2105 }
2106
2107 /**
2108 * igb_up - Open the interface and prepare it to handle traffic
2109 * @adapter: board private structure
2110 **/
igb_up(struct igb_adapter * adapter)2111 int igb_up(struct igb_adapter *adapter)
2112 {
2113 struct e1000_hw *hw = &adapter->hw;
2114 int i;
2115
2116 /* hardware has been reset, we need to reload some things */
2117 igb_configure(adapter);
2118
2119 clear_bit(__IGB_DOWN, &adapter->state);
2120
2121 for (i = 0; i < adapter->num_q_vectors; i++)
2122 napi_enable(&(adapter->q_vector[i]->napi));
2123
2124 if (adapter->flags & IGB_FLAG_HAS_MSIX)
2125 igb_configure_msix(adapter);
2126 else
2127 igb_assign_vector(adapter->q_vector[0], 0);
2128
2129 /* Clear any pending interrupts. */
2130 rd32(E1000_TSICR);
2131 rd32(E1000_ICR);
2132 igb_irq_enable(adapter);
2133
2134 /* notify VFs that reset has been completed */
2135 if (adapter->vfs_allocated_count) {
2136 u32 reg_data = rd32(E1000_CTRL_EXT);
2137
2138 reg_data |= E1000_CTRL_EXT_PFRSTD;
2139 wr32(E1000_CTRL_EXT, reg_data);
2140 }
2141
2142 netif_tx_start_all_queues(adapter->netdev);
2143
2144 /* start the watchdog. */
2145 hw->mac.get_link_status = 1;
2146 schedule_work(&adapter->watchdog_task);
2147
2148 if ((adapter->flags & IGB_FLAG_EEE) &&
2149 (!hw->dev_spec._82575.eee_disable))
2150 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
2151
2152 return 0;
2153 }
2154
igb_down(struct igb_adapter * adapter)2155 void igb_down(struct igb_adapter *adapter)
2156 {
2157 struct net_device *netdev = adapter->netdev;
2158 struct e1000_hw *hw = &adapter->hw;
2159 u32 tctl, rctl;
2160 int i;
2161
2162 /* signal that we're down so the interrupt handler does not
2163 * reschedule our watchdog timer
2164 */
2165 set_bit(__IGB_DOWN, &adapter->state);
2166
2167 /* disable receives in the hardware */
2168 rctl = rd32(E1000_RCTL);
2169 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
2170 /* flush and sleep below */
2171
2172 igb_nfc_filter_exit(adapter);
2173
2174 netif_carrier_off(netdev);
2175 netif_tx_stop_all_queues(netdev);
2176
2177 /* disable transmits in the hardware */
2178 tctl = rd32(E1000_TCTL);
2179 tctl &= ~E1000_TCTL_EN;
2180 wr32(E1000_TCTL, tctl);
2181 /* flush both disables and wait for them to finish */
2182 wrfl();
2183 usleep_range(10000, 11000);
2184
2185 igb_irq_disable(adapter);
2186
2187 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
2188
2189 for (i = 0; i < adapter->num_q_vectors; i++) {
2190 if (adapter->q_vector[i]) {
2191 napi_synchronize(&adapter->q_vector[i]->napi);
2192 napi_disable(&adapter->q_vector[i]->napi);
2193 }
2194 }
2195
2196 del_timer_sync(&adapter->watchdog_timer);
2197 del_timer_sync(&adapter->phy_info_timer);
2198
2199 /* record the stats before reset*/
2200 spin_lock(&adapter->stats64_lock);
2201 igb_update_stats(adapter);
2202 spin_unlock(&adapter->stats64_lock);
2203
2204 adapter->link_speed = 0;
2205 adapter->link_duplex = 0;
2206
2207 if (!pci_channel_offline(adapter->pdev))
2208 igb_reset(adapter);
2209
2210 /* clear VLAN promisc flag so VFTA will be updated if necessary */
2211 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC;
2212
2213 igb_clean_all_tx_rings(adapter);
2214 igb_clean_all_rx_rings(adapter);
2215 #ifdef CONFIG_IGB_DCA
2216
2217 /* since we reset the hardware DCA settings were cleared */
2218 igb_setup_dca(adapter);
2219 #endif
2220 }
2221
igb_reinit_locked(struct igb_adapter * adapter)2222 void igb_reinit_locked(struct igb_adapter *adapter)
2223 {
2224 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
2225 usleep_range(1000, 2000);
2226 igb_down(adapter);
2227 igb_up(adapter);
2228 clear_bit(__IGB_RESETTING, &adapter->state);
2229 }
2230
2231 /** igb_enable_mas - Media Autosense re-enable after swap
2232 *
2233 * @adapter: adapter struct
2234 **/
igb_enable_mas(struct igb_adapter * adapter)2235 static void igb_enable_mas(struct igb_adapter *adapter)
2236 {
2237 struct e1000_hw *hw = &adapter->hw;
2238 u32 connsw = rd32(E1000_CONNSW);
2239
2240 /* configure for SerDes media detect */
2241 if ((hw->phy.media_type == e1000_media_type_copper) &&
2242 (!(connsw & E1000_CONNSW_SERDESD))) {
2243 connsw |= E1000_CONNSW_ENRGSRC;
2244 connsw |= E1000_CONNSW_AUTOSENSE_EN;
2245 wr32(E1000_CONNSW, connsw);
2246 wrfl();
2247 }
2248 }
2249
igb_reset(struct igb_adapter * adapter)2250 void igb_reset(struct igb_adapter *adapter)
2251 {
2252 struct pci_dev *pdev = adapter->pdev;
2253 struct e1000_hw *hw = &adapter->hw;
2254 struct e1000_mac_info *mac = &hw->mac;
2255 struct e1000_fc_info *fc = &hw->fc;
2256 u32 pba, hwm;
2257
2258 /* Repartition Pba for greater than 9k mtu
2259 * To take effect CTRL.RST is required.
2260 */
2261 switch (mac->type) {
2262 case e1000_i350:
2263 case e1000_i354:
2264 case e1000_82580:
2265 pba = rd32(E1000_RXPBS);
2266 pba = igb_rxpbs_adjust_82580(pba);
2267 break;
2268 case e1000_82576:
2269 pba = rd32(E1000_RXPBS);
2270 pba &= E1000_RXPBS_SIZE_MASK_82576;
2271 break;
2272 case e1000_82575:
2273 case e1000_i210:
2274 case e1000_i211:
2275 default:
2276 pba = E1000_PBA_34K;
2277 break;
2278 }
2279
2280 if (mac->type == e1000_82575) {
2281 u32 min_rx_space, min_tx_space, needed_tx_space;
2282
2283 /* write Rx PBA so that hardware can report correct Tx PBA */
2284 wr32(E1000_PBA, pba);
2285
2286 /* To maintain wire speed transmits, the Tx FIFO should be
2287 * large enough to accommodate two full transmit packets,
2288 * rounded up to the next 1KB and expressed in KB. Likewise,
2289 * the Rx FIFO should be large enough to accommodate at least
2290 * one full receive packet and is similarly rounded up and
2291 * expressed in KB.
2292 */
2293 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024);
2294
2295 /* The Tx FIFO also stores 16 bytes of information about the Tx
2296 * but don't include Ethernet FCS because hardware appends it.
2297 * We only need to round down to the nearest 512 byte block
2298 * count since the value we care about is 2 frames, not 1.
2299 */
2300 min_tx_space = adapter->max_frame_size;
2301 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN;
2302 min_tx_space = DIV_ROUND_UP(min_tx_space, 512);
2303
2304 /* upper 16 bits has Tx packet buffer allocation size in KB */
2305 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16);
2306
2307 /* If current Tx allocation is less than the min Tx FIFO size,
2308 * and the min Tx FIFO size is less than the current Rx FIFO
2309 * allocation, take space away from current Rx allocation.
2310 */
2311 if (needed_tx_space < pba) {
2312 pba -= needed_tx_space;
2313
2314 /* if short on Rx space, Rx wins and must trump Tx
2315 * adjustment
2316 */
2317 if (pba < min_rx_space)
2318 pba = min_rx_space;
2319 }
2320
2321 /* adjust PBA for jumbo frames */
2322 wr32(E1000_PBA, pba);
2323 }
2324
2325 /* flow control settings
2326 * The high water mark must be low enough to fit one full frame
2327 * after transmitting the pause frame. As such we must have enough
2328 * space to allow for us to complete our current transmit and then
2329 * receive the frame that is in progress from the link partner.
2330 * Set it to:
2331 * - the full Rx FIFO size minus one full Tx plus one full Rx frame
2332 */
2333 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE);
2334
2335 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
2336 fc->low_water = fc->high_water - 16;
2337 fc->pause_time = 0xFFFF;
2338 fc->send_xon = 1;
2339 fc->current_mode = fc->requested_mode;
2340
2341 /* disable receive for all VFs and wait one second */
2342 if (adapter->vfs_allocated_count) {
2343 int i;
2344
2345 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
2346 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
2347
2348 /* ping all the active vfs to let them know we are going down */
2349 igb_ping_all_vfs(adapter);
2350
2351 /* disable transmits and receives */
2352 wr32(E1000_VFRE, 0);
2353 wr32(E1000_VFTE, 0);
2354 }
2355
2356 /* Allow time for pending master requests to run */
2357 hw->mac.ops.reset_hw(hw);
2358 wr32(E1000_WUC, 0);
2359
2360 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
2361 /* need to resetup here after media swap */
2362 adapter->ei.get_invariants(hw);
2363 adapter->flags &= ~IGB_FLAG_MEDIA_RESET;
2364 }
2365 if ((mac->type == e1000_82575 || mac->type == e1000_i350) &&
2366 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
2367 igb_enable_mas(adapter);
2368 }
2369 if (hw->mac.ops.init_hw(hw))
2370 dev_err(&pdev->dev, "Hardware Error\n");
2371
2372 /* RAR registers were cleared during init_hw, clear mac table */
2373 igb_flush_mac_table(adapter);
2374 __dev_uc_unsync(adapter->netdev, NULL);
2375
2376 /* Recover default RAR entry */
2377 igb_set_default_mac_filter(adapter);
2378
2379 /* Flow control settings reset on hardware reset, so guarantee flow
2380 * control is off when forcing speed.
2381 */
2382 if (!hw->mac.autoneg)
2383 igb_force_mac_fc(hw);
2384
2385 igb_init_dmac(adapter, pba);
2386 #ifdef CONFIG_IGB_HWMON
2387 /* Re-initialize the thermal sensor on i350 devices. */
2388 if (!test_bit(__IGB_DOWN, &adapter->state)) {
2389 if (mac->type == e1000_i350 && hw->bus.func == 0) {
2390 /* If present, re-initialize the external thermal sensor
2391 * interface.
2392 */
2393 if (adapter->ets)
2394 mac->ops.init_thermal_sensor_thresh(hw);
2395 }
2396 }
2397 #endif
2398 /* Re-establish EEE setting */
2399 if (hw->phy.media_type == e1000_media_type_copper) {
2400 switch (mac->type) {
2401 case e1000_i350:
2402 case e1000_i210:
2403 case e1000_i211:
2404 igb_set_eee_i350(hw, true, true);
2405 break;
2406 case e1000_i354:
2407 igb_set_eee_i354(hw, true, true);
2408 break;
2409 default:
2410 break;
2411 }
2412 }
2413 if (!netif_running(adapter->netdev))
2414 igb_power_down_link(adapter);
2415
2416 igb_update_mng_vlan(adapter);
2417
2418 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
2419 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
2420
2421 /* Re-enable PTP, where applicable. */
2422 if (adapter->ptp_flags & IGB_PTP_ENABLED)
2423 igb_ptp_reset(adapter);
2424
2425 igb_get_phy_info(hw);
2426 }
2427
igb_fix_features(struct net_device * netdev,netdev_features_t features)2428 static netdev_features_t igb_fix_features(struct net_device *netdev,
2429 netdev_features_t features)
2430 {
2431 /* Since there is no support for separate Rx/Tx vlan accel
2432 * enable/disable make sure Tx flag is always in same state as Rx.
2433 */
2434 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2435 features |= NETIF_F_HW_VLAN_CTAG_TX;
2436 else
2437 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
2438
2439 return features;
2440 }
2441
igb_set_features(struct net_device * netdev,netdev_features_t features)2442 static int igb_set_features(struct net_device *netdev,
2443 netdev_features_t features)
2444 {
2445 netdev_features_t changed = netdev->features ^ features;
2446 struct igb_adapter *adapter = netdev_priv(netdev);
2447
2448 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
2449 igb_vlan_mode(netdev, features);
2450
2451 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE)))
2452 return 0;
2453
2454 if (!(features & NETIF_F_NTUPLE)) {
2455 struct hlist_node *node2;
2456 struct igb_nfc_filter *rule;
2457
2458 spin_lock(&adapter->nfc_lock);
2459 hlist_for_each_entry_safe(rule, node2,
2460 &adapter->nfc_filter_list, nfc_node) {
2461 igb_erase_filter(adapter, rule);
2462 hlist_del(&rule->nfc_node);
2463 kfree(rule);
2464 }
2465 spin_unlock(&adapter->nfc_lock);
2466 adapter->nfc_filter_count = 0;
2467 }
2468
2469 netdev->features = features;
2470
2471 if (netif_running(netdev))
2472 igb_reinit_locked(adapter);
2473 else
2474 igb_reset(adapter);
2475
2476 return 1;
2477 }
2478
igb_ndo_fdb_add(struct ndmsg * ndm,struct nlattr * tb[],struct net_device * dev,const unsigned char * addr,u16 vid,u16 flags,struct netlink_ext_ack * extack)2479 static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
2480 struct net_device *dev,
2481 const unsigned char *addr, u16 vid,
2482 u16 flags,
2483 struct netlink_ext_ack *extack)
2484 {
2485 /* guarantee we can provide a unique filter for the unicast address */
2486 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
2487 struct igb_adapter *adapter = netdev_priv(dev);
2488 int vfn = adapter->vfs_allocated_count;
2489
2490 if (netdev_uc_count(dev) >= igb_available_rars(adapter, vfn))
2491 return -ENOMEM;
2492 }
2493
2494 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
2495 }
2496
2497 #define IGB_MAX_MAC_HDR_LEN 127
2498 #define IGB_MAX_NETWORK_HDR_LEN 511
2499
2500 static netdev_features_t
igb_features_check(struct sk_buff * skb,struct net_device * dev,netdev_features_t features)2501 igb_features_check(struct sk_buff *skb, struct net_device *dev,
2502 netdev_features_t features)
2503 {
2504 unsigned int network_hdr_len, mac_hdr_len;
2505
2506 /* Make certain the headers can be described by a context descriptor */
2507 mac_hdr_len = skb_network_header(skb) - skb->data;
2508 if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN))
2509 return features & ~(NETIF_F_HW_CSUM |
2510 NETIF_F_SCTP_CRC |
2511 NETIF_F_GSO_UDP_L4 |
2512 NETIF_F_HW_VLAN_CTAG_TX |
2513 NETIF_F_TSO |
2514 NETIF_F_TSO6);
2515
2516 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb);
2517 if (unlikely(network_hdr_len > IGB_MAX_NETWORK_HDR_LEN))
2518 return features & ~(NETIF_F_HW_CSUM |
2519 NETIF_F_SCTP_CRC |
2520 NETIF_F_GSO_UDP_L4 |
2521 NETIF_F_TSO |
2522 NETIF_F_TSO6);
2523
2524 /* We can only support IPV4 TSO in tunnels if we can mangle the
2525 * inner IP ID field, so strip TSO if MANGLEID is not supported.
2526 */
2527 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID))
2528 features &= ~NETIF_F_TSO;
2529
2530 return features;
2531 }
2532
igb_offload_apply(struct igb_adapter * adapter,s32 queue)2533 static void igb_offload_apply(struct igb_adapter *adapter, s32 queue)
2534 {
2535 if (!is_fqtss_enabled(adapter)) {
2536 enable_fqtss(adapter, true);
2537 return;
2538 }
2539
2540 igb_config_tx_modes(adapter, queue);
2541
2542 if (!is_any_cbs_enabled(adapter) && !is_any_txtime_enabled(adapter))
2543 enable_fqtss(adapter, false);
2544 }
2545
igb_offload_cbs(struct igb_adapter * adapter,struct tc_cbs_qopt_offload * qopt)2546 static int igb_offload_cbs(struct igb_adapter *adapter,
2547 struct tc_cbs_qopt_offload *qopt)
2548 {
2549 struct e1000_hw *hw = &adapter->hw;
2550 int err;
2551
2552 /* CBS offloading is only supported by i210 controller. */
2553 if (hw->mac.type != e1000_i210)
2554 return -EOPNOTSUPP;
2555
2556 /* CBS offloading is only supported by queue 0 and queue 1. */
2557 if (qopt->queue < 0 || qopt->queue > 1)
2558 return -EINVAL;
2559
2560 err = igb_save_cbs_params(adapter, qopt->queue, qopt->enable,
2561 qopt->idleslope, qopt->sendslope,
2562 qopt->hicredit, qopt->locredit);
2563 if (err)
2564 return err;
2565
2566 igb_offload_apply(adapter, qopt->queue);
2567
2568 return 0;
2569 }
2570
2571 #define ETHER_TYPE_FULL_MASK ((__force __be16)~0)
2572 #define VLAN_PRIO_FULL_MASK (0x07)
2573
igb_parse_cls_flower(struct igb_adapter * adapter,struct flow_cls_offload * f,int traffic_class,struct igb_nfc_filter * input)2574 static int igb_parse_cls_flower(struct igb_adapter *adapter,
2575 struct flow_cls_offload *f,
2576 int traffic_class,
2577 struct igb_nfc_filter *input)
2578 {
2579 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2580 struct flow_dissector *dissector = rule->match.dissector;
2581 struct netlink_ext_ack *extack = f->common.extack;
2582
2583 if (dissector->used_keys &
2584 ~(BIT(FLOW_DISSECTOR_KEY_BASIC) |
2585 BIT(FLOW_DISSECTOR_KEY_CONTROL) |
2586 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
2587 BIT(FLOW_DISSECTOR_KEY_VLAN))) {
2588 NL_SET_ERR_MSG_MOD(extack,
2589 "Unsupported key used, only BASIC, CONTROL, ETH_ADDRS and VLAN are supported");
2590 return -EOPNOTSUPP;
2591 }
2592
2593 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
2594 struct flow_match_eth_addrs match;
2595
2596 flow_rule_match_eth_addrs(rule, &match);
2597 if (!is_zero_ether_addr(match.mask->dst)) {
2598 if (!is_broadcast_ether_addr(match.mask->dst)) {
2599 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for destination MAC address");
2600 return -EINVAL;
2601 }
2602
2603 input->filter.match_flags |=
2604 IGB_FILTER_FLAG_DST_MAC_ADDR;
2605 ether_addr_copy(input->filter.dst_addr, match.key->dst);
2606 }
2607
2608 if (!is_zero_ether_addr(match.mask->src)) {
2609 if (!is_broadcast_ether_addr(match.mask->src)) {
2610 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for source MAC address");
2611 return -EINVAL;
2612 }
2613
2614 input->filter.match_flags |=
2615 IGB_FILTER_FLAG_SRC_MAC_ADDR;
2616 ether_addr_copy(input->filter.src_addr, match.key->src);
2617 }
2618 }
2619
2620 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2621 struct flow_match_basic match;
2622
2623 flow_rule_match_basic(rule, &match);
2624 if (match.mask->n_proto) {
2625 if (match.mask->n_proto != ETHER_TYPE_FULL_MASK) {
2626 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for EtherType filter");
2627 return -EINVAL;
2628 }
2629
2630 input->filter.match_flags |= IGB_FILTER_FLAG_ETHER_TYPE;
2631 input->filter.etype = match.key->n_proto;
2632 }
2633 }
2634
2635 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) {
2636 struct flow_match_vlan match;
2637
2638 flow_rule_match_vlan(rule, &match);
2639 if (match.mask->vlan_priority) {
2640 if (match.mask->vlan_priority != VLAN_PRIO_FULL_MASK) {
2641 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for VLAN priority");
2642 return -EINVAL;
2643 }
2644
2645 input->filter.match_flags |= IGB_FILTER_FLAG_VLAN_TCI;
2646 input->filter.vlan_tci = match.key->vlan_priority;
2647 }
2648 }
2649
2650 input->action = traffic_class;
2651 input->cookie = f->cookie;
2652
2653 return 0;
2654 }
2655
igb_configure_clsflower(struct igb_adapter * adapter,struct flow_cls_offload * cls_flower)2656 static int igb_configure_clsflower(struct igb_adapter *adapter,
2657 struct flow_cls_offload *cls_flower)
2658 {
2659 struct netlink_ext_ack *extack = cls_flower->common.extack;
2660 struct igb_nfc_filter *filter, *f;
2661 int err, tc;
2662
2663 tc = tc_classid_to_hwtc(adapter->netdev, cls_flower->classid);
2664 if (tc < 0) {
2665 NL_SET_ERR_MSG_MOD(extack, "Invalid traffic class");
2666 return -EINVAL;
2667 }
2668
2669 filter = kzalloc(sizeof(*filter), GFP_KERNEL);
2670 if (!filter)
2671 return -ENOMEM;
2672
2673 err = igb_parse_cls_flower(adapter, cls_flower, tc, filter);
2674 if (err < 0)
2675 goto err_parse;
2676
2677 spin_lock(&adapter->nfc_lock);
2678
2679 hlist_for_each_entry(f, &adapter->nfc_filter_list, nfc_node) {
2680 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) {
2681 err = -EEXIST;
2682 NL_SET_ERR_MSG_MOD(extack,
2683 "This filter is already set in ethtool");
2684 goto err_locked;
2685 }
2686 }
2687
2688 hlist_for_each_entry(f, &adapter->cls_flower_list, nfc_node) {
2689 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) {
2690 err = -EEXIST;
2691 NL_SET_ERR_MSG_MOD(extack,
2692 "This filter is already set in cls_flower");
2693 goto err_locked;
2694 }
2695 }
2696
2697 err = igb_add_filter(adapter, filter);
2698 if (err < 0) {
2699 NL_SET_ERR_MSG_MOD(extack, "Could not add filter to the adapter");
2700 goto err_locked;
2701 }
2702
2703 hlist_add_head(&filter->nfc_node, &adapter->cls_flower_list);
2704
2705 spin_unlock(&adapter->nfc_lock);
2706
2707 return 0;
2708
2709 err_locked:
2710 spin_unlock(&adapter->nfc_lock);
2711
2712 err_parse:
2713 kfree(filter);
2714
2715 return err;
2716 }
2717
igb_delete_clsflower(struct igb_adapter * adapter,struct flow_cls_offload * cls_flower)2718 static int igb_delete_clsflower(struct igb_adapter *adapter,
2719 struct flow_cls_offload *cls_flower)
2720 {
2721 struct igb_nfc_filter *filter;
2722 int err;
2723
2724 spin_lock(&adapter->nfc_lock);
2725
2726 hlist_for_each_entry(filter, &adapter->cls_flower_list, nfc_node)
2727 if (filter->cookie == cls_flower->cookie)
2728 break;
2729
2730 if (!filter) {
2731 err = -ENOENT;
2732 goto out;
2733 }
2734
2735 err = igb_erase_filter(adapter, filter);
2736 if (err < 0)
2737 goto out;
2738
2739 hlist_del(&filter->nfc_node);
2740 kfree(filter);
2741
2742 out:
2743 spin_unlock(&adapter->nfc_lock);
2744
2745 return err;
2746 }
2747
igb_setup_tc_cls_flower(struct igb_adapter * adapter,struct flow_cls_offload * cls_flower)2748 static int igb_setup_tc_cls_flower(struct igb_adapter *adapter,
2749 struct flow_cls_offload *cls_flower)
2750 {
2751 switch (cls_flower->command) {
2752 case FLOW_CLS_REPLACE:
2753 return igb_configure_clsflower(adapter, cls_flower);
2754 case FLOW_CLS_DESTROY:
2755 return igb_delete_clsflower(adapter, cls_flower);
2756 case FLOW_CLS_STATS:
2757 return -EOPNOTSUPP;
2758 default:
2759 return -EOPNOTSUPP;
2760 }
2761 }
2762
igb_setup_tc_block_cb(enum tc_setup_type type,void * type_data,void * cb_priv)2763 static int igb_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
2764 void *cb_priv)
2765 {
2766 struct igb_adapter *adapter = cb_priv;
2767
2768 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data))
2769 return -EOPNOTSUPP;
2770
2771 switch (type) {
2772 case TC_SETUP_CLSFLOWER:
2773 return igb_setup_tc_cls_flower(adapter, type_data);
2774
2775 default:
2776 return -EOPNOTSUPP;
2777 }
2778 }
2779
igb_offload_txtime(struct igb_adapter * adapter,struct tc_etf_qopt_offload * qopt)2780 static int igb_offload_txtime(struct igb_adapter *adapter,
2781 struct tc_etf_qopt_offload *qopt)
2782 {
2783 struct e1000_hw *hw = &adapter->hw;
2784 int err;
2785
2786 /* Launchtime offloading is only supported by i210 controller. */
2787 if (hw->mac.type != e1000_i210)
2788 return -EOPNOTSUPP;
2789
2790 /* Launchtime offloading is only supported by queues 0 and 1. */
2791 if (qopt->queue < 0 || qopt->queue > 1)
2792 return -EINVAL;
2793
2794 err = igb_save_txtime_params(adapter, qopt->queue, qopt->enable);
2795 if (err)
2796 return err;
2797
2798 igb_offload_apply(adapter, qopt->queue);
2799
2800 return 0;
2801 }
2802
2803 static LIST_HEAD(igb_block_cb_list);
2804
igb_setup_tc(struct net_device * dev,enum tc_setup_type type,void * type_data)2805 static int igb_setup_tc(struct net_device *dev, enum tc_setup_type type,
2806 void *type_data)
2807 {
2808 struct igb_adapter *adapter = netdev_priv(dev);
2809
2810 switch (type) {
2811 case TC_SETUP_QDISC_CBS:
2812 return igb_offload_cbs(adapter, type_data);
2813 case TC_SETUP_BLOCK:
2814 return flow_block_cb_setup_simple(type_data,
2815 &igb_block_cb_list,
2816 igb_setup_tc_block_cb,
2817 adapter, adapter, true);
2818
2819 case TC_SETUP_QDISC_ETF:
2820 return igb_offload_txtime(adapter, type_data);
2821
2822 default:
2823 return -EOPNOTSUPP;
2824 }
2825 }
2826
igb_xdp_setup(struct net_device * dev,struct netdev_bpf * bpf)2827 static int igb_xdp_setup(struct net_device *dev, struct netdev_bpf *bpf)
2828 {
2829 int i, frame_size = dev->mtu + IGB_ETH_PKT_HDR_PAD;
2830 struct igb_adapter *adapter = netdev_priv(dev);
2831 struct bpf_prog *prog = bpf->prog, *old_prog;
2832 bool running = netif_running(dev);
2833 bool need_reset;
2834
2835 /* verify igb ring attributes are sufficient for XDP */
2836 for (i = 0; i < adapter->num_rx_queues; i++) {
2837 struct igb_ring *ring = adapter->rx_ring[i];
2838
2839 if (frame_size > igb_rx_bufsz(ring)) {
2840 NL_SET_ERR_MSG_MOD(bpf->extack,
2841 "The RX buffer size is too small for the frame size");
2842 netdev_warn(dev, "XDP RX buffer size %d is too small for the frame size %d\n",
2843 igb_rx_bufsz(ring), frame_size);
2844 return -EINVAL;
2845 }
2846 }
2847
2848 old_prog = xchg(&adapter->xdp_prog, prog);
2849 need_reset = (!!prog != !!old_prog);
2850
2851 /* device is up and bpf is added/removed, must setup the RX queues */
2852 if (need_reset && running) {
2853 igb_close(dev);
2854 } else {
2855 for (i = 0; i < adapter->num_rx_queues; i++)
2856 (void)xchg(&adapter->rx_ring[i]->xdp_prog,
2857 adapter->xdp_prog);
2858 }
2859
2860 if (old_prog)
2861 bpf_prog_put(old_prog);
2862
2863 /* bpf is just replaced, RXQ and MTU are already setup */
2864 if (!need_reset)
2865 return 0;
2866
2867 if (running)
2868 igb_open(dev);
2869
2870 return 0;
2871 }
2872
igb_xdp(struct net_device * dev,struct netdev_bpf * xdp)2873 static int igb_xdp(struct net_device *dev, struct netdev_bpf *xdp)
2874 {
2875 switch (xdp->command) {
2876 case XDP_SETUP_PROG:
2877 return igb_xdp_setup(dev, xdp);
2878 default:
2879 return -EINVAL;
2880 }
2881 }
2882
igb_xdp_ring_update_tail(struct igb_ring * ring)2883 static void igb_xdp_ring_update_tail(struct igb_ring *ring)
2884 {
2885 /* Force memory writes to complete before letting h/w know there
2886 * are new descriptors to fetch.
2887 */
2888 wmb();
2889 writel(ring->next_to_use, ring->tail);
2890 }
2891
igb_xdp_tx_queue_mapping(struct igb_adapter * adapter)2892 static struct igb_ring *igb_xdp_tx_queue_mapping(struct igb_adapter *adapter)
2893 {
2894 unsigned int r_idx = smp_processor_id();
2895
2896 if (r_idx >= adapter->num_tx_queues)
2897 r_idx = r_idx % adapter->num_tx_queues;
2898
2899 return adapter->tx_ring[r_idx];
2900 }
2901
igb_xdp_xmit_back(struct igb_adapter * adapter,struct xdp_buff * xdp)2902 static int igb_xdp_xmit_back(struct igb_adapter *adapter, struct xdp_buff *xdp)
2903 {
2904 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp);
2905 int cpu = smp_processor_id();
2906 struct igb_ring *tx_ring;
2907 struct netdev_queue *nq;
2908 u32 ret;
2909
2910 if (unlikely(!xdpf))
2911 return IGB_XDP_CONSUMED;
2912
2913 /* During program transitions its possible adapter->xdp_prog is assigned
2914 * but ring has not been configured yet. In this case simply abort xmit.
2915 */
2916 tx_ring = adapter->xdp_prog ? igb_xdp_tx_queue_mapping(adapter) : NULL;
2917 if (unlikely(!tx_ring))
2918 return IGB_XDP_CONSUMED;
2919
2920 nq = txring_txq(tx_ring);
2921 __netif_tx_lock(nq, cpu);
2922 /* Avoid transmit queue timeout since we share it with the slow path */
2923 nq->trans_start = jiffies;
2924 ret = igb_xmit_xdp_ring(adapter, tx_ring, xdpf);
2925 __netif_tx_unlock(nq);
2926
2927 return ret;
2928 }
2929
igb_xdp_xmit(struct net_device * dev,int n,struct xdp_frame ** frames,u32 flags)2930 static int igb_xdp_xmit(struct net_device *dev, int n,
2931 struct xdp_frame **frames, u32 flags)
2932 {
2933 struct igb_adapter *adapter = netdev_priv(dev);
2934 int cpu = smp_processor_id();
2935 struct igb_ring *tx_ring;
2936 struct netdev_queue *nq;
2937 int nxmit = 0;
2938 int i;
2939
2940 if (unlikely(test_bit(__IGB_DOWN, &adapter->state)))
2941 return -ENETDOWN;
2942
2943 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
2944 return -EINVAL;
2945
2946 /* During program transitions its possible adapter->xdp_prog is assigned
2947 * but ring has not been configured yet. In this case simply abort xmit.
2948 */
2949 tx_ring = adapter->xdp_prog ? igb_xdp_tx_queue_mapping(adapter) : NULL;
2950 if (unlikely(!tx_ring))
2951 return -ENXIO;
2952
2953 nq = txring_txq(tx_ring);
2954 __netif_tx_lock(nq, cpu);
2955
2956 /* Avoid transmit queue timeout since we share it with the slow path */
2957 nq->trans_start = jiffies;
2958
2959 for (i = 0; i < n; i++) {
2960 struct xdp_frame *xdpf = frames[i];
2961 int err;
2962
2963 err = igb_xmit_xdp_ring(adapter, tx_ring, xdpf);
2964 if (err != IGB_XDP_TX)
2965 break;
2966 nxmit++;
2967 }
2968
2969 __netif_tx_unlock(nq);
2970
2971 if (unlikely(flags & XDP_XMIT_FLUSH))
2972 igb_xdp_ring_update_tail(tx_ring);
2973
2974 return nxmit;
2975 }
2976
2977 static const struct net_device_ops igb_netdev_ops = {
2978 .ndo_open = igb_open,
2979 .ndo_stop = igb_close,
2980 .ndo_start_xmit = igb_xmit_frame,
2981 .ndo_get_stats64 = igb_get_stats64,
2982 .ndo_set_rx_mode = igb_set_rx_mode,
2983 .ndo_set_mac_address = igb_set_mac,
2984 .ndo_change_mtu = igb_change_mtu,
2985 .ndo_do_ioctl = igb_ioctl,
2986 .ndo_tx_timeout = igb_tx_timeout,
2987 .ndo_validate_addr = eth_validate_addr,
2988 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
2989 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
2990 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
2991 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
2992 .ndo_set_vf_rate = igb_ndo_set_vf_bw,
2993 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk,
2994 .ndo_set_vf_trust = igb_ndo_set_vf_trust,
2995 .ndo_get_vf_config = igb_ndo_get_vf_config,
2996 .ndo_fix_features = igb_fix_features,
2997 .ndo_set_features = igb_set_features,
2998 .ndo_fdb_add = igb_ndo_fdb_add,
2999 .ndo_features_check = igb_features_check,
3000 .ndo_setup_tc = igb_setup_tc,
3001 .ndo_bpf = igb_xdp,
3002 .ndo_xdp_xmit = igb_xdp_xmit,
3003 };
3004
3005 /**
3006 * igb_set_fw_version - Configure version string for ethtool
3007 * @adapter: adapter struct
3008 **/
igb_set_fw_version(struct igb_adapter * adapter)3009 void igb_set_fw_version(struct igb_adapter *adapter)
3010 {
3011 struct e1000_hw *hw = &adapter->hw;
3012 struct e1000_fw_version fw;
3013
3014 igb_get_fw_version(hw, &fw);
3015
3016 switch (hw->mac.type) {
3017 case e1000_i210:
3018 case e1000_i211:
3019 if (!(igb_get_flash_presence_i210(hw))) {
3020 snprintf(adapter->fw_version,
3021 sizeof(adapter->fw_version),
3022 "%2d.%2d-%d",
3023 fw.invm_major, fw.invm_minor,
3024 fw.invm_img_type);
3025 break;
3026 }
3027 fallthrough;
3028 default:
3029 /* if option is rom valid, display its version too */
3030 if (fw.or_valid) {
3031 snprintf(adapter->fw_version,
3032 sizeof(adapter->fw_version),
3033 "%d.%d, 0x%08x, %d.%d.%d",
3034 fw.eep_major, fw.eep_minor, fw.etrack_id,
3035 fw.or_major, fw.or_build, fw.or_patch);
3036 /* no option rom */
3037 } else if (fw.etrack_id != 0X0000) {
3038 snprintf(adapter->fw_version,
3039 sizeof(adapter->fw_version),
3040 "%d.%d, 0x%08x",
3041 fw.eep_major, fw.eep_minor, fw.etrack_id);
3042 } else {
3043 snprintf(adapter->fw_version,
3044 sizeof(adapter->fw_version),
3045 "%d.%d.%d",
3046 fw.eep_major, fw.eep_minor, fw.eep_build);
3047 }
3048 break;
3049 }
3050 }
3051
3052 /**
3053 * igb_init_mas - init Media Autosense feature if enabled in the NVM
3054 *
3055 * @adapter: adapter struct
3056 **/
igb_init_mas(struct igb_adapter * adapter)3057 static void igb_init_mas(struct igb_adapter *adapter)
3058 {
3059 struct e1000_hw *hw = &adapter->hw;
3060 u16 eeprom_data;
3061
3062 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data);
3063 switch (hw->bus.func) {
3064 case E1000_FUNC_0:
3065 if (eeprom_data & IGB_MAS_ENABLE_0) {
3066 adapter->flags |= IGB_FLAG_MAS_ENABLE;
3067 netdev_info(adapter->netdev,
3068 "MAS: Enabling Media Autosense for port %d\n",
3069 hw->bus.func);
3070 }
3071 break;
3072 case E1000_FUNC_1:
3073 if (eeprom_data & IGB_MAS_ENABLE_1) {
3074 adapter->flags |= IGB_FLAG_MAS_ENABLE;
3075 netdev_info(adapter->netdev,
3076 "MAS: Enabling Media Autosense for port %d\n",
3077 hw->bus.func);
3078 }
3079 break;
3080 case E1000_FUNC_2:
3081 if (eeprom_data & IGB_MAS_ENABLE_2) {
3082 adapter->flags |= IGB_FLAG_MAS_ENABLE;
3083 netdev_info(adapter->netdev,
3084 "MAS: Enabling Media Autosense for port %d\n",
3085 hw->bus.func);
3086 }
3087 break;
3088 case E1000_FUNC_3:
3089 if (eeprom_data & IGB_MAS_ENABLE_3) {
3090 adapter->flags |= IGB_FLAG_MAS_ENABLE;
3091 netdev_info(adapter->netdev,
3092 "MAS: Enabling Media Autosense for port %d\n",
3093 hw->bus.func);
3094 }
3095 break;
3096 default:
3097 /* Shouldn't get here */
3098 netdev_err(adapter->netdev,
3099 "MAS: Invalid port configuration, returning\n");
3100 break;
3101 }
3102 }
3103
3104 /**
3105 * igb_init_i2c - Init I2C interface
3106 * @adapter: pointer to adapter structure
3107 **/
igb_init_i2c(struct igb_adapter * adapter)3108 static s32 igb_init_i2c(struct igb_adapter *adapter)
3109 {
3110 s32 status = 0;
3111
3112 /* I2C interface supported on i350 devices */
3113 if (adapter->hw.mac.type != e1000_i350)
3114 return 0;
3115
3116 /* Initialize the i2c bus which is controlled by the registers.
3117 * This bus will use the i2c_algo_bit structure that implements
3118 * the protocol through toggling of the 4 bits in the register.
3119 */
3120 adapter->i2c_adap.owner = THIS_MODULE;
3121 adapter->i2c_algo = igb_i2c_algo;
3122 adapter->i2c_algo.data = adapter;
3123 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
3124 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
3125 strlcpy(adapter->i2c_adap.name, "igb BB",
3126 sizeof(adapter->i2c_adap.name));
3127 status = i2c_bit_add_bus(&adapter->i2c_adap);
3128 return status;
3129 }
3130
3131 /**
3132 * igb_probe - Device Initialization Routine
3133 * @pdev: PCI device information struct
3134 * @ent: entry in igb_pci_tbl
3135 *
3136 * Returns 0 on success, negative on failure
3137 *
3138 * igb_probe initializes an adapter identified by a pci_dev structure.
3139 * The OS initialization, configuring of the adapter private structure,
3140 * and a hardware reset occur.
3141 **/
igb_probe(struct pci_dev * pdev,const struct pci_device_id * ent)3142 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3143 {
3144 struct net_device *netdev;
3145 struct igb_adapter *adapter;
3146 struct e1000_hw *hw;
3147 u16 eeprom_data = 0;
3148 s32 ret_val;
3149 static int global_quad_port_a; /* global quad port a indication */
3150 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
3151 int err, pci_using_dac;
3152 u8 part_str[E1000_PBANUM_LENGTH];
3153
3154 /* Catch broken hardware that put the wrong VF device ID in
3155 * the PCIe SR-IOV capability.
3156 */
3157 if (pdev->is_virtfn) {
3158 WARN(1, KERN_ERR "%s (%x:%x) should not be a VF!\n",
3159 pci_name(pdev), pdev->vendor, pdev->device);
3160 return -EINVAL;
3161 }
3162
3163 err = pci_enable_device_mem(pdev);
3164 if (err)
3165 return err;
3166
3167 pci_using_dac = 0;
3168 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
3169 if (!err) {
3170 pci_using_dac = 1;
3171 } else {
3172 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
3173 if (err) {
3174 dev_err(&pdev->dev,
3175 "No usable DMA configuration, aborting\n");
3176 goto err_dma;
3177 }
3178 }
3179
3180 err = pci_request_mem_regions(pdev, igb_driver_name);
3181 if (err)
3182 goto err_pci_reg;
3183
3184 pci_enable_pcie_error_reporting(pdev);
3185
3186 pci_set_master(pdev);
3187 pci_save_state(pdev);
3188
3189 err = -ENOMEM;
3190 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
3191 IGB_MAX_TX_QUEUES);
3192 if (!netdev)
3193 goto err_alloc_etherdev;
3194
3195 SET_NETDEV_DEV(netdev, &pdev->dev);
3196
3197 pci_set_drvdata(pdev, netdev);
3198 adapter = netdev_priv(netdev);
3199 adapter->netdev = netdev;
3200 adapter->pdev = pdev;
3201 hw = &adapter->hw;
3202 hw->back = adapter;
3203 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
3204
3205 err = -EIO;
3206 adapter->io_addr = pci_iomap(pdev, 0, 0);
3207 if (!adapter->io_addr)
3208 goto err_ioremap;
3209 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */
3210 hw->hw_addr = adapter->io_addr;
3211
3212 netdev->netdev_ops = &igb_netdev_ops;
3213 igb_set_ethtool_ops(netdev);
3214 netdev->watchdog_timeo = 5 * HZ;
3215
3216 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
3217
3218 netdev->mem_start = pci_resource_start(pdev, 0);
3219 netdev->mem_end = pci_resource_end(pdev, 0);
3220
3221 /* PCI config space info */
3222 hw->vendor_id = pdev->vendor;
3223 hw->device_id = pdev->device;
3224 hw->revision_id = pdev->revision;
3225 hw->subsystem_vendor_id = pdev->subsystem_vendor;
3226 hw->subsystem_device_id = pdev->subsystem_device;
3227
3228 /* Copy the default MAC, PHY and NVM function pointers */
3229 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
3230 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
3231 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
3232 /* Initialize skew-specific constants */
3233 err = ei->get_invariants(hw);
3234 if (err)
3235 goto err_sw_init;
3236
3237 /* setup the private structure */
3238 err = igb_sw_init(adapter);
3239 if (err)
3240 goto err_sw_init;
3241
3242 igb_get_bus_info_pcie(hw);
3243
3244 hw->phy.autoneg_wait_to_complete = false;
3245
3246 /* Copper options */
3247 if (hw->phy.media_type == e1000_media_type_copper) {
3248 hw->phy.mdix = AUTO_ALL_MODES;
3249 hw->phy.disable_polarity_correction = false;
3250 hw->phy.ms_type = e1000_ms_hw_default;
3251 }
3252
3253 if (igb_check_reset_block(hw))
3254 dev_info(&pdev->dev,
3255 "PHY reset is blocked due to SOL/IDER session.\n");
3256
3257 /* features is initialized to 0 in allocation, it might have bits
3258 * set by igb_sw_init so we should use an or instead of an
3259 * assignment.
3260 */
3261 netdev->features |= NETIF_F_SG |
3262 NETIF_F_TSO |
3263 NETIF_F_TSO6 |
3264 NETIF_F_RXHASH |
3265 NETIF_F_RXCSUM |
3266 NETIF_F_HW_CSUM;
3267
3268 if (hw->mac.type >= e1000_82576)
3269 netdev->features |= NETIF_F_SCTP_CRC | NETIF_F_GSO_UDP_L4;
3270
3271 if (hw->mac.type >= e1000_i350)
3272 netdev->features |= NETIF_F_HW_TC;
3273
3274 #define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \
3275 NETIF_F_GSO_GRE_CSUM | \
3276 NETIF_F_GSO_IPXIP4 | \
3277 NETIF_F_GSO_IPXIP6 | \
3278 NETIF_F_GSO_UDP_TUNNEL | \
3279 NETIF_F_GSO_UDP_TUNNEL_CSUM)
3280
3281 netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES;
3282 netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES;
3283
3284 /* copy netdev features into list of user selectable features */
3285 netdev->hw_features |= netdev->features |
3286 NETIF_F_HW_VLAN_CTAG_RX |
3287 NETIF_F_HW_VLAN_CTAG_TX |
3288 NETIF_F_RXALL;
3289
3290 if (hw->mac.type >= e1000_i350)
3291 netdev->hw_features |= NETIF_F_NTUPLE;
3292
3293 if (pci_using_dac)
3294 netdev->features |= NETIF_F_HIGHDMA;
3295
3296 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID;
3297 netdev->mpls_features |= NETIF_F_HW_CSUM;
3298 netdev->hw_enc_features |= netdev->vlan_features;
3299
3300 /* set this bit last since it cannot be part of vlan_features */
3301 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
3302 NETIF_F_HW_VLAN_CTAG_RX |
3303 NETIF_F_HW_VLAN_CTAG_TX;
3304
3305 netdev->priv_flags |= IFF_SUPP_NOFCS;
3306
3307 netdev->priv_flags |= IFF_UNICAST_FLT;
3308
3309 /* MTU range: 68 - 9216 */
3310 netdev->min_mtu = ETH_MIN_MTU;
3311 netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE;
3312
3313 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
3314
3315 /* before reading the NVM, reset the controller to put the device in a
3316 * known good starting state
3317 */
3318 hw->mac.ops.reset_hw(hw);
3319
3320 /* make sure the NVM is good , i211/i210 parts can have special NVM
3321 * that doesn't contain a checksum
3322 */
3323 switch (hw->mac.type) {
3324 case e1000_i210:
3325 case e1000_i211:
3326 if (igb_get_flash_presence_i210(hw)) {
3327 if (hw->nvm.ops.validate(hw) < 0) {
3328 dev_err(&pdev->dev,
3329 "The NVM Checksum Is Not Valid\n");
3330 err = -EIO;
3331 goto err_eeprom;
3332 }
3333 }
3334 break;
3335 default:
3336 if (hw->nvm.ops.validate(hw) < 0) {
3337 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
3338 err = -EIO;
3339 goto err_eeprom;
3340 }
3341 break;
3342 }
3343
3344 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) {
3345 /* copy the MAC address out of the NVM */
3346 if (hw->mac.ops.read_mac_addr(hw))
3347 dev_err(&pdev->dev, "NVM Read Error\n");
3348 }
3349
3350 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
3351
3352 if (!is_valid_ether_addr(netdev->dev_addr)) {
3353 dev_err(&pdev->dev, "Invalid MAC Address\n");
3354 err = -EIO;
3355 goto err_eeprom;
3356 }
3357
3358 igb_set_default_mac_filter(adapter);
3359
3360 /* get firmware version for ethtool -i */
3361 igb_set_fw_version(adapter);
3362
3363 /* configure RXPBSIZE and TXPBSIZE */
3364 if (hw->mac.type == e1000_i210) {
3365 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
3366 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
3367 }
3368
3369 timer_setup(&adapter->watchdog_timer, igb_watchdog, 0);
3370 timer_setup(&adapter->phy_info_timer, igb_update_phy_info, 0);
3371
3372 INIT_WORK(&adapter->reset_task, igb_reset_task);
3373 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
3374
3375 /* Initialize link properties that are user-changeable */
3376 adapter->fc_autoneg = true;
3377 hw->mac.autoneg = true;
3378 hw->phy.autoneg_advertised = 0x2f;
3379
3380 hw->fc.requested_mode = e1000_fc_default;
3381 hw->fc.current_mode = e1000_fc_default;
3382
3383 igb_validate_mdi_setting(hw);
3384
3385 /* By default, support wake on port A */
3386 if (hw->bus.func == 0)
3387 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3388
3389 /* Check the NVM for wake support on non-port A ports */
3390 if (hw->mac.type >= e1000_82580)
3391 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
3392 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
3393 &eeprom_data);
3394 else if (hw->bus.func == 1)
3395 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3396
3397 if (eeprom_data & IGB_EEPROM_APME)
3398 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3399
3400 /* now that we have the eeprom settings, apply the special cases where
3401 * the eeprom may be wrong or the board simply won't support wake on
3402 * lan on a particular port
3403 */
3404 switch (pdev->device) {
3405 case E1000_DEV_ID_82575GB_QUAD_COPPER:
3406 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
3407 break;
3408 case E1000_DEV_ID_82575EB_FIBER_SERDES:
3409 case E1000_DEV_ID_82576_FIBER:
3410 case E1000_DEV_ID_82576_SERDES:
3411 /* Wake events only supported on port A for dual fiber
3412 * regardless of eeprom setting
3413 */
3414 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
3415 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
3416 break;
3417 case E1000_DEV_ID_82576_QUAD_COPPER:
3418 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
3419 /* if quad port adapter, disable WoL on all but port A */
3420 if (global_quad_port_a != 0)
3421 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
3422 else
3423 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
3424 /* Reset for multiple quad port adapters */
3425 if (++global_quad_port_a == 4)
3426 global_quad_port_a = 0;
3427 break;
3428 default:
3429 /* If the device can't wake, don't set software support */
3430 if (!device_can_wakeup(&adapter->pdev->dev))
3431 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
3432 }
3433
3434 /* initialize the wol settings based on the eeprom settings */
3435 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
3436 adapter->wol |= E1000_WUFC_MAG;
3437
3438 /* Some vendors want WoL disabled by default, but still supported */
3439 if ((hw->mac.type == e1000_i350) &&
3440 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
3441 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3442 adapter->wol = 0;
3443 }
3444
3445 /* Some vendors want the ability to Use the EEPROM setting as
3446 * enable/disable only, and not for capability
3447 */
3448 if (((hw->mac.type == e1000_i350) ||
3449 (hw->mac.type == e1000_i354)) &&
3450 (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) {
3451 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3452 adapter->wol = 0;
3453 }
3454 if (hw->mac.type == e1000_i350) {
3455 if (((pdev->subsystem_device == 0x5001) ||
3456 (pdev->subsystem_device == 0x5002)) &&
3457 (hw->bus.func == 0)) {
3458 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3459 adapter->wol = 0;
3460 }
3461 if (pdev->subsystem_device == 0x1F52)
3462 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3463 }
3464
3465 device_set_wakeup_enable(&adapter->pdev->dev,
3466 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
3467
3468 /* reset the hardware with the new settings */
3469 igb_reset(adapter);
3470
3471 /* Init the I2C interface */
3472 err = igb_init_i2c(adapter);
3473 if (err) {
3474 dev_err(&pdev->dev, "failed to init i2c interface\n");
3475 goto err_eeprom;
3476 }
3477
3478 /* let the f/w know that the h/w is now under the control of the
3479 * driver.
3480 */
3481 igb_get_hw_control(adapter);
3482
3483 strcpy(netdev->name, "eth%d");
3484 err = register_netdev(netdev);
3485 if (err)
3486 goto err_register;
3487
3488 /* carrier off reporting is important to ethtool even BEFORE open */
3489 netif_carrier_off(netdev);
3490
3491 #ifdef CONFIG_IGB_DCA
3492 if (dca_add_requester(&pdev->dev) == 0) {
3493 adapter->flags |= IGB_FLAG_DCA_ENABLED;
3494 dev_info(&pdev->dev, "DCA enabled\n");
3495 igb_setup_dca(adapter);
3496 }
3497
3498 #endif
3499 #ifdef CONFIG_IGB_HWMON
3500 /* Initialize the thermal sensor on i350 devices. */
3501 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
3502 u16 ets_word;
3503
3504 /* Read the NVM to determine if this i350 device supports an
3505 * external thermal sensor.
3506 */
3507 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
3508 if (ets_word != 0x0000 && ets_word != 0xFFFF)
3509 adapter->ets = true;
3510 else
3511 adapter->ets = false;
3512 if (igb_sysfs_init(adapter))
3513 dev_err(&pdev->dev,
3514 "failed to allocate sysfs resources\n");
3515 } else {
3516 adapter->ets = false;
3517 }
3518 #endif
3519 /* Check if Media Autosense is enabled */
3520 adapter->ei = *ei;
3521 if (hw->dev_spec._82575.mas_capable)
3522 igb_init_mas(adapter);
3523
3524 /* do hw tstamp init after resetting */
3525 igb_ptp_init(adapter);
3526
3527 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
3528 /* print bus type/speed/width info, not applicable to i354 */
3529 if (hw->mac.type != e1000_i354) {
3530 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
3531 netdev->name,
3532 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
3533 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
3534 "unknown"),
3535 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
3536 "Width x4" :
3537 (hw->bus.width == e1000_bus_width_pcie_x2) ?
3538 "Width x2" :
3539 (hw->bus.width == e1000_bus_width_pcie_x1) ?
3540 "Width x1" : "unknown"), netdev->dev_addr);
3541 }
3542
3543 if ((hw->mac.type == e1000_82576 &&
3544 rd32(E1000_EECD) & E1000_EECD_PRES) ||
3545 (hw->mac.type >= e1000_i210 ||
3546 igb_get_flash_presence_i210(hw))) {
3547 ret_val = igb_read_part_string(hw, part_str,
3548 E1000_PBANUM_LENGTH);
3549 } else {
3550 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
3551 }
3552
3553 if (ret_val)
3554 strcpy(part_str, "Unknown");
3555 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
3556 dev_info(&pdev->dev,
3557 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
3558 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" :
3559 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
3560 adapter->num_rx_queues, adapter->num_tx_queues);
3561 if (hw->phy.media_type == e1000_media_type_copper) {
3562 switch (hw->mac.type) {
3563 case e1000_i350:
3564 case e1000_i210:
3565 case e1000_i211:
3566 /* Enable EEE for internal copper PHY devices */
3567 err = igb_set_eee_i350(hw, true, true);
3568 if ((!err) &&
3569 (!hw->dev_spec._82575.eee_disable)) {
3570 adapter->eee_advert =
3571 MDIO_EEE_100TX | MDIO_EEE_1000T;
3572 adapter->flags |= IGB_FLAG_EEE;
3573 }
3574 break;
3575 case e1000_i354:
3576 if ((rd32(E1000_CTRL_EXT) &
3577 E1000_CTRL_EXT_LINK_MODE_SGMII)) {
3578 err = igb_set_eee_i354(hw, true, true);
3579 if ((!err) &&
3580 (!hw->dev_spec._82575.eee_disable)) {
3581 adapter->eee_advert =
3582 MDIO_EEE_100TX | MDIO_EEE_1000T;
3583 adapter->flags |= IGB_FLAG_EEE;
3584 }
3585 }
3586 break;
3587 default:
3588 break;
3589 }
3590 }
3591
3592 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
3593
3594 pm_runtime_put_noidle(&pdev->dev);
3595 return 0;
3596
3597 err_register:
3598 igb_release_hw_control(adapter);
3599 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
3600 err_eeprom:
3601 if (!igb_check_reset_block(hw))
3602 igb_reset_phy(hw);
3603
3604 if (hw->flash_address)
3605 iounmap(hw->flash_address);
3606 err_sw_init:
3607 kfree(adapter->mac_table);
3608 kfree(adapter->shadow_vfta);
3609 igb_clear_interrupt_scheme(adapter);
3610 #ifdef CONFIG_PCI_IOV
3611 igb_disable_sriov(pdev);
3612 #endif
3613 pci_iounmap(pdev, adapter->io_addr);
3614 err_ioremap:
3615 free_netdev(netdev);
3616 err_alloc_etherdev:
3617 pci_release_mem_regions(pdev);
3618 err_pci_reg:
3619 err_dma:
3620 pci_disable_device(pdev);
3621 return err;
3622 }
3623
3624 #ifdef CONFIG_PCI_IOV
igb_disable_sriov(struct pci_dev * pdev)3625 static int igb_disable_sriov(struct pci_dev *pdev)
3626 {
3627 struct net_device *netdev = pci_get_drvdata(pdev);
3628 struct igb_adapter *adapter = netdev_priv(netdev);
3629 struct e1000_hw *hw = &adapter->hw;
3630
3631 /* reclaim resources allocated to VFs */
3632 if (adapter->vf_data) {
3633 /* disable iov and allow time for transactions to clear */
3634 if (pci_vfs_assigned(pdev)) {
3635 dev_warn(&pdev->dev,
3636 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
3637 return -EPERM;
3638 } else {
3639 pci_disable_sriov(pdev);
3640 msleep(500);
3641 }
3642
3643 kfree(adapter->vf_mac_list);
3644 adapter->vf_mac_list = NULL;
3645 kfree(adapter->vf_data);
3646 adapter->vf_data = NULL;
3647 adapter->vfs_allocated_count = 0;
3648 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
3649 wrfl();
3650 msleep(100);
3651 dev_info(&pdev->dev, "IOV Disabled\n");
3652
3653 /* Re-enable DMA Coalescing flag since IOV is turned off */
3654 adapter->flags |= IGB_FLAG_DMAC;
3655 }
3656
3657 return 0;
3658 }
3659
igb_enable_sriov(struct pci_dev * pdev,int num_vfs)3660 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
3661 {
3662 struct net_device *netdev = pci_get_drvdata(pdev);
3663 struct igb_adapter *adapter = netdev_priv(netdev);
3664 int old_vfs = pci_num_vf(pdev);
3665 struct vf_mac_filter *mac_list;
3666 int err = 0;
3667 int num_vf_mac_filters, i;
3668
3669 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) {
3670 err = -EPERM;
3671 goto out;
3672 }
3673 if (!num_vfs)
3674 goto out;
3675
3676 if (old_vfs) {
3677 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
3678 old_vfs, max_vfs);
3679 adapter->vfs_allocated_count = old_vfs;
3680 } else
3681 adapter->vfs_allocated_count = num_vfs;
3682
3683 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
3684 sizeof(struct vf_data_storage), GFP_KERNEL);
3685
3686 /* if allocation failed then we do not support SR-IOV */
3687 if (!adapter->vf_data) {
3688 adapter->vfs_allocated_count = 0;
3689 err = -ENOMEM;
3690 goto out;
3691 }
3692
3693 /* Due to the limited number of RAR entries calculate potential
3694 * number of MAC filters available for the VFs. Reserve entries
3695 * for PF default MAC, PF MAC filters and at least one RAR entry
3696 * for each VF for VF MAC.
3697 */
3698 num_vf_mac_filters = adapter->hw.mac.rar_entry_count -
3699 (1 + IGB_PF_MAC_FILTERS_RESERVED +
3700 adapter->vfs_allocated_count);
3701
3702 adapter->vf_mac_list = kcalloc(num_vf_mac_filters,
3703 sizeof(struct vf_mac_filter),
3704 GFP_KERNEL);
3705
3706 mac_list = adapter->vf_mac_list;
3707 INIT_LIST_HEAD(&adapter->vf_macs.l);
3708
3709 if (adapter->vf_mac_list) {
3710 /* Initialize list of VF MAC filters */
3711 for (i = 0; i < num_vf_mac_filters; i++) {
3712 mac_list->vf = -1;
3713 mac_list->free = true;
3714 list_add(&mac_list->l, &adapter->vf_macs.l);
3715 mac_list++;
3716 }
3717 } else {
3718 /* If we could not allocate memory for the VF MAC filters
3719 * we can continue without this feature but warn user.
3720 */
3721 dev_err(&pdev->dev,
3722 "Unable to allocate memory for VF MAC filter list\n");
3723 }
3724
3725 /* only call pci_enable_sriov() if no VFs are allocated already */
3726 if (!old_vfs) {
3727 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
3728 if (err)
3729 goto err_out;
3730 }
3731 dev_info(&pdev->dev, "%d VFs allocated\n",
3732 adapter->vfs_allocated_count);
3733 for (i = 0; i < adapter->vfs_allocated_count; i++)
3734 igb_vf_configure(adapter, i);
3735
3736 /* DMA Coalescing is not supported in IOV mode. */
3737 adapter->flags &= ~IGB_FLAG_DMAC;
3738 goto out;
3739
3740 err_out:
3741 kfree(adapter->vf_mac_list);
3742 adapter->vf_mac_list = NULL;
3743 kfree(adapter->vf_data);
3744 adapter->vf_data = NULL;
3745 adapter->vfs_allocated_count = 0;
3746 out:
3747 return err;
3748 }
3749
3750 #endif
3751 /**
3752 * igb_remove_i2c - Cleanup I2C interface
3753 * @adapter: pointer to adapter structure
3754 **/
igb_remove_i2c(struct igb_adapter * adapter)3755 static void igb_remove_i2c(struct igb_adapter *adapter)
3756 {
3757 /* free the adapter bus structure */
3758 i2c_del_adapter(&adapter->i2c_adap);
3759 }
3760
3761 /**
3762 * igb_remove - Device Removal Routine
3763 * @pdev: PCI device information struct
3764 *
3765 * igb_remove is called by the PCI subsystem to alert the driver
3766 * that it should release a PCI device. The could be caused by a
3767 * Hot-Plug event, or because the driver is going to be removed from
3768 * memory.
3769 **/
igb_remove(struct pci_dev * pdev)3770 static void igb_remove(struct pci_dev *pdev)
3771 {
3772 struct net_device *netdev = pci_get_drvdata(pdev);
3773 struct igb_adapter *adapter = netdev_priv(netdev);
3774 struct e1000_hw *hw = &adapter->hw;
3775
3776 pm_runtime_get_noresume(&pdev->dev);
3777 #ifdef CONFIG_IGB_HWMON
3778 igb_sysfs_exit(adapter);
3779 #endif
3780 igb_remove_i2c(adapter);
3781 igb_ptp_stop(adapter);
3782 /* The watchdog timer may be rescheduled, so explicitly
3783 * disable watchdog from being rescheduled.
3784 */
3785 set_bit(__IGB_DOWN, &adapter->state);
3786 del_timer_sync(&adapter->watchdog_timer);
3787 del_timer_sync(&adapter->phy_info_timer);
3788
3789 cancel_work_sync(&adapter->reset_task);
3790 cancel_work_sync(&adapter->watchdog_task);
3791
3792 #ifdef CONFIG_IGB_DCA
3793 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
3794 dev_info(&pdev->dev, "DCA disabled\n");
3795 dca_remove_requester(&pdev->dev);
3796 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
3797 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
3798 }
3799 #endif
3800
3801 /* Release control of h/w to f/w. If f/w is AMT enabled, this
3802 * would have already happened in close and is redundant.
3803 */
3804 igb_release_hw_control(adapter);
3805
3806 #ifdef CONFIG_PCI_IOV
3807 igb_disable_sriov(pdev);
3808 #endif
3809
3810 unregister_netdev(netdev);
3811
3812 igb_clear_interrupt_scheme(adapter);
3813
3814 pci_iounmap(pdev, adapter->io_addr);
3815 if (hw->flash_address)
3816 iounmap(hw->flash_address);
3817 pci_release_mem_regions(pdev);
3818
3819 kfree(adapter->mac_table);
3820 kfree(adapter->shadow_vfta);
3821 free_netdev(netdev);
3822
3823 pci_disable_pcie_error_reporting(pdev);
3824
3825 pci_disable_device(pdev);
3826 }
3827
3828 /**
3829 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
3830 * @adapter: board private structure to initialize
3831 *
3832 * This function initializes the vf specific data storage and then attempts to
3833 * allocate the VFs. The reason for ordering it this way is because it is much
3834 * mor expensive time wise to disable SR-IOV than it is to allocate and free
3835 * the memory for the VFs.
3836 **/
igb_probe_vfs(struct igb_adapter * adapter)3837 static void igb_probe_vfs(struct igb_adapter *adapter)
3838 {
3839 #ifdef CONFIG_PCI_IOV
3840 struct pci_dev *pdev = adapter->pdev;
3841 struct e1000_hw *hw = &adapter->hw;
3842
3843 /* Virtualization features not supported on i210 family. */
3844 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
3845 return;
3846
3847 /* Of the below we really only want the effect of getting
3848 * IGB_FLAG_HAS_MSIX set (if available), without which
3849 * igb_enable_sriov() has no effect.
3850 */
3851 igb_set_interrupt_capability(adapter, true);
3852 igb_reset_interrupt_capability(adapter);
3853
3854 pci_sriov_set_totalvfs(pdev, 7);
3855 igb_enable_sriov(pdev, max_vfs);
3856
3857 #endif /* CONFIG_PCI_IOV */
3858 }
3859
igb_get_max_rss_queues(struct igb_adapter * adapter)3860 unsigned int igb_get_max_rss_queues(struct igb_adapter *adapter)
3861 {
3862 struct e1000_hw *hw = &adapter->hw;
3863 unsigned int max_rss_queues;
3864
3865 /* Determine the maximum number of RSS queues supported. */
3866 switch (hw->mac.type) {
3867 case e1000_i211:
3868 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
3869 break;
3870 case e1000_82575:
3871 case e1000_i210:
3872 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
3873 break;
3874 case e1000_i350:
3875 /* I350 cannot do RSS and SR-IOV at the same time */
3876 if (!!adapter->vfs_allocated_count) {
3877 max_rss_queues = 1;
3878 break;
3879 }
3880 fallthrough;
3881 case e1000_82576:
3882 if (!!adapter->vfs_allocated_count) {
3883 max_rss_queues = 2;
3884 break;
3885 }
3886 fallthrough;
3887 case e1000_82580:
3888 case e1000_i354:
3889 default:
3890 max_rss_queues = IGB_MAX_RX_QUEUES;
3891 break;
3892 }
3893
3894 return max_rss_queues;
3895 }
3896
igb_init_queue_configuration(struct igb_adapter * adapter)3897 static void igb_init_queue_configuration(struct igb_adapter *adapter)
3898 {
3899 u32 max_rss_queues;
3900
3901 max_rss_queues = igb_get_max_rss_queues(adapter);
3902 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
3903
3904 igb_set_flag_queue_pairs(adapter, max_rss_queues);
3905 }
3906
igb_set_flag_queue_pairs(struct igb_adapter * adapter,const u32 max_rss_queues)3907 void igb_set_flag_queue_pairs(struct igb_adapter *adapter,
3908 const u32 max_rss_queues)
3909 {
3910 struct e1000_hw *hw = &adapter->hw;
3911
3912 /* Determine if we need to pair queues. */
3913 switch (hw->mac.type) {
3914 case e1000_82575:
3915 case e1000_i211:
3916 /* Device supports enough interrupts without queue pairing. */
3917 break;
3918 case e1000_82576:
3919 case e1000_82580:
3920 case e1000_i350:
3921 case e1000_i354:
3922 case e1000_i210:
3923 default:
3924 /* If rss_queues > half of max_rss_queues, pair the queues in
3925 * order to conserve interrupts due to limited supply.
3926 */
3927 if (adapter->rss_queues > (max_rss_queues / 2))
3928 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
3929 else
3930 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS;
3931 break;
3932 }
3933 }
3934
3935 /**
3936 * igb_sw_init - Initialize general software structures (struct igb_adapter)
3937 * @adapter: board private structure to initialize
3938 *
3939 * igb_sw_init initializes the Adapter private data structure.
3940 * Fields are initialized based on PCI device information and
3941 * OS network device settings (MTU size).
3942 **/
igb_sw_init(struct igb_adapter * adapter)3943 static int igb_sw_init(struct igb_adapter *adapter)
3944 {
3945 struct e1000_hw *hw = &adapter->hw;
3946 struct net_device *netdev = adapter->netdev;
3947 struct pci_dev *pdev = adapter->pdev;
3948
3949 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
3950
3951 /* set default ring sizes */
3952 adapter->tx_ring_count = IGB_DEFAULT_TXD;
3953 adapter->rx_ring_count = IGB_DEFAULT_RXD;
3954
3955 /* set default ITR values */
3956 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
3957 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
3958
3959 /* set default work limits */
3960 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
3961
3962 adapter->max_frame_size = netdev->mtu + IGB_ETH_PKT_HDR_PAD;
3963 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
3964
3965 spin_lock_init(&adapter->nfc_lock);
3966 spin_lock_init(&adapter->stats64_lock);
3967 #ifdef CONFIG_PCI_IOV
3968 switch (hw->mac.type) {
3969 case e1000_82576:
3970 case e1000_i350:
3971 if (max_vfs > 7) {
3972 dev_warn(&pdev->dev,
3973 "Maximum of 7 VFs per PF, using max\n");
3974 max_vfs = adapter->vfs_allocated_count = 7;
3975 } else
3976 adapter->vfs_allocated_count = max_vfs;
3977 if (adapter->vfs_allocated_count)
3978 dev_warn(&pdev->dev,
3979 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
3980 break;
3981 default:
3982 break;
3983 }
3984 #endif /* CONFIG_PCI_IOV */
3985
3986 /* Assume MSI-X interrupts, will be checked during IRQ allocation */
3987 adapter->flags |= IGB_FLAG_HAS_MSIX;
3988
3989 adapter->mac_table = kcalloc(hw->mac.rar_entry_count,
3990 sizeof(struct igb_mac_addr),
3991 GFP_KERNEL);
3992 if (!adapter->mac_table)
3993 return -ENOMEM;
3994
3995 igb_probe_vfs(adapter);
3996
3997 igb_init_queue_configuration(adapter);
3998
3999 /* Setup and initialize a copy of the hw vlan table array */
4000 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
4001 GFP_KERNEL);
4002 if (!adapter->shadow_vfta)
4003 return -ENOMEM;
4004
4005 /* This call may decrease the number of queues */
4006 if (igb_init_interrupt_scheme(adapter, true)) {
4007 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
4008 return -ENOMEM;
4009 }
4010
4011 /* Explicitly disable IRQ since the NIC can be in any state. */
4012 igb_irq_disable(adapter);
4013
4014 if (hw->mac.type >= e1000_i350)
4015 adapter->flags &= ~IGB_FLAG_DMAC;
4016
4017 set_bit(__IGB_DOWN, &adapter->state);
4018 return 0;
4019 }
4020
4021 /**
4022 * __igb_open - Called when a network interface is made active
4023 * @netdev: network interface device structure
4024 * @resuming: indicates whether we are in a resume call
4025 *
4026 * Returns 0 on success, negative value on failure
4027 *
4028 * The open entry point is called when a network interface is made
4029 * active by the system (IFF_UP). At this point all resources needed
4030 * for transmit and receive operations are allocated, the interrupt
4031 * handler is registered with the OS, the watchdog timer is started,
4032 * and the stack is notified that the interface is ready.
4033 **/
__igb_open(struct net_device * netdev,bool resuming)4034 static int __igb_open(struct net_device *netdev, bool resuming)
4035 {
4036 struct igb_adapter *adapter = netdev_priv(netdev);
4037 struct e1000_hw *hw = &adapter->hw;
4038 struct pci_dev *pdev = adapter->pdev;
4039 int err;
4040 int i;
4041
4042 /* disallow open during test */
4043 if (test_bit(__IGB_TESTING, &adapter->state)) {
4044 WARN_ON(resuming);
4045 return -EBUSY;
4046 }
4047
4048 if (!resuming)
4049 pm_runtime_get_sync(&pdev->dev);
4050
4051 netif_carrier_off(netdev);
4052
4053 /* allocate transmit descriptors */
4054 err = igb_setup_all_tx_resources(adapter);
4055 if (err)
4056 goto err_setup_tx;
4057
4058 /* allocate receive descriptors */
4059 err = igb_setup_all_rx_resources(adapter);
4060 if (err)
4061 goto err_setup_rx;
4062
4063 igb_power_up_link(adapter);
4064
4065 /* before we allocate an interrupt, we must be ready to handle it.
4066 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
4067 * as soon as we call pci_request_irq, so we have to setup our
4068 * clean_rx handler before we do so.
4069 */
4070 igb_configure(adapter);
4071
4072 err = igb_request_irq(adapter);
4073 if (err)
4074 goto err_req_irq;
4075
4076 /* Notify the stack of the actual queue counts. */
4077 err = netif_set_real_num_tx_queues(adapter->netdev,
4078 adapter->num_tx_queues);
4079 if (err)
4080 goto err_set_queues;
4081
4082 err = netif_set_real_num_rx_queues(adapter->netdev,
4083 adapter->num_rx_queues);
4084 if (err)
4085 goto err_set_queues;
4086
4087 /* From here on the code is the same as igb_up() */
4088 clear_bit(__IGB_DOWN, &adapter->state);
4089
4090 for (i = 0; i < adapter->num_q_vectors; i++)
4091 napi_enable(&(adapter->q_vector[i]->napi));
4092
4093 /* Clear any pending interrupts. */
4094 rd32(E1000_TSICR);
4095 rd32(E1000_ICR);
4096
4097 igb_irq_enable(adapter);
4098
4099 /* notify VFs that reset has been completed */
4100 if (adapter->vfs_allocated_count) {
4101 u32 reg_data = rd32(E1000_CTRL_EXT);
4102
4103 reg_data |= E1000_CTRL_EXT_PFRSTD;
4104 wr32(E1000_CTRL_EXT, reg_data);
4105 }
4106
4107 netif_tx_start_all_queues(netdev);
4108
4109 if (!resuming)
4110 pm_runtime_put(&pdev->dev);
4111
4112 /* start the watchdog. */
4113 hw->mac.get_link_status = 1;
4114 schedule_work(&adapter->watchdog_task);
4115
4116 return 0;
4117
4118 err_set_queues:
4119 igb_free_irq(adapter);
4120 err_req_irq:
4121 igb_release_hw_control(adapter);
4122 igb_power_down_link(adapter);
4123 igb_free_all_rx_resources(adapter);
4124 err_setup_rx:
4125 igb_free_all_tx_resources(adapter);
4126 err_setup_tx:
4127 igb_reset(adapter);
4128 if (!resuming)
4129 pm_runtime_put(&pdev->dev);
4130
4131 return err;
4132 }
4133
igb_open(struct net_device * netdev)4134 int igb_open(struct net_device *netdev)
4135 {
4136 return __igb_open(netdev, false);
4137 }
4138
4139 /**
4140 * __igb_close - Disables a network interface
4141 * @netdev: network interface device structure
4142 * @suspending: indicates we are in a suspend call
4143 *
4144 * Returns 0, this is not allowed to fail
4145 *
4146 * The close entry point is called when an interface is de-activated
4147 * by the OS. The hardware is still under the driver's control, but
4148 * needs to be disabled. A global MAC reset is issued to stop the
4149 * hardware, and all transmit and receive resources are freed.
4150 **/
__igb_close(struct net_device * netdev,bool suspending)4151 static int __igb_close(struct net_device *netdev, bool suspending)
4152 {
4153 struct igb_adapter *adapter = netdev_priv(netdev);
4154 struct pci_dev *pdev = adapter->pdev;
4155
4156 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
4157
4158 if (!suspending)
4159 pm_runtime_get_sync(&pdev->dev);
4160
4161 igb_down(adapter);
4162 igb_free_irq(adapter);
4163
4164 igb_free_all_tx_resources(adapter);
4165 igb_free_all_rx_resources(adapter);
4166
4167 if (!suspending)
4168 pm_runtime_put_sync(&pdev->dev);
4169 return 0;
4170 }
4171
igb_close(struct net_device * netdev)4172 int igb_close(struct net_device *netdev)
4173 {
4174 if (netif_device_present(netdev) || netdev->dismantle)
4175 return __igb_close(netdev, false);
4176 return 0;
4177 }
4178
4179 /**
4180 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
4181 * @tx_ring: tx descriptor ring (for a specific queue) to setup
4182 *
4183 * Return 0 on success, negative on failure
4184 **/
igb_setup_tx_resources(struct igb_ring * tx_ring)4185 int igb_setup_tx_resources(struct igb_ring *tx_ring)
4186 {
4187 struct device *dev = tx_ring->dev;
4188 int size;
4189
4190 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
4191
4192 tx_ring->tx_buffer_info = vmalloc(size);
4193 if (!tx_ring->tx_buffer_info)
4194 goto err;
4195
4196 /* round up to nearest 4K */
4197 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
4198 tx_ring->size = ALIGN(tx_ring->size, 4096);
4199
4200 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4201 &tx_ring->dma, GFP_KERNEL);
4202 if (!tx_ring->desc)
4203 goto err;
4204
4205 tx_ring->next_to_use = 0;
4206 tx_ring->next_to_clean = 0;
4207
4208 return 0;
4209
4210 err:
4211 vfree(tx_ring->tx_buffer_info);
4212 tx_ring->tx_buffer_info = NULL;
4213 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
4214 return -ENOMEM;
4215 }
4216
4217 /**
4218 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
4219 * (Descriptors) for all queues
4220 * @adapter: board private structure
4221 *
4222 * Return 0 on success, negative on failure
4223 **/
igb_setup_all_tx_resources(struct igb_adapter * adapter)4224 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
4225 {
4226 struct pci_dev *pdev = adapter->pdev;
4227 int i, err = 0;
4228
4229 for (i = 0; i < adapter->num_tx_queues; i++) {
4230 err = igb_setup_tx_resources(adapter->tx_ring[i]);
4231 if (err) {
4232 dev_err(&pdev->dev,
4233 "Allocation for Tx Queue %u failed\n", i);
4234 for (i--; i >= 0; i--)
4235 igb_free_tx_resources(adapter->tx_ring[i]);
4236 break;
4237 }
4238 }
4239
4240 return err;
4241 }
4242
4243 /**
4244 * igb_setup_tctl - configure the transmit control registers
4245 * @adapter: Board private structure
4246 **/
igb_setup_tctl(struct igb_adapter * adapter)4247 void igb_setup_tctl(struct igb_adapter *adapter)
4248 {
4249 struct e1000_hw *hw = &adapter->hw;
4250 u32 tctl;
4251
4252 /* disable queue 0 which is enabled by default on 82575 and 82576 */
4253 wr32(E1000_TXDCTL(0), 0);
4254
4255 /* Program the Transmit Control Register */
4256 tctl = rd32(E1000_TCTL);
4257 tctl &= ~E1000_TCTL_CT;
4258 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
4259 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
4260
4261 igb_config_collision_dist(hw);
4262
4263 /* Enable transmits */
4264 tctl |= E1000_TCTL_EN;
4265
4266 wr32(E1000_TCTL, tctl);
4267 }
4268
4269 /**
4270 * igb_configure_tx_ring - Configure transmit ring after Reset
4271 * @adapter: board private structure
4272 * @ring: tx ring to configure
4273 *
4274 * Configure a transmit ring after a reset.
4275 **/
igb_configure_tx_ring(struct igb_adapter * adapter,struct igb_ring * ring)4276 void igb_configure_tx_ring(struct igb_adapter *adapter,
4277 struct igb_ring *ring)
4278 {
4279 struct e1000_hw *hw = &adapter->hw;
4280 u32 txdctl = 0;
4281 u64 tdba = ring->dma;
4282 int reg_idx = ring->reg_idx;
4283
4284 wr32(E1000_TDLEN(reg_idx),
4285 ring->count * sizeof(union e1000_adv_tx_desc));
4286 wr32(E1000_TDBAL(reg_idx),
4287 tdba & 0x00000000ffffffffULL);
4288 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
4289
4290 ring->tail = adapter->io_addr + E1000_TDT(reg_idx);
4291 wr32(E1000_TDH(reg_idx), 0);
4292 writel(0, ring->tail);
4293
4294 txdctl |= IGB_TX_PTHRESH;
4295 txdctl |= IGB_TX_HTHRESH << 8;
4296 txdctl |= IGB_TX_WTHRESH << 16;
4297
4298 /* reinitialize tx_buffer_info */
4299 memset(ring->tx_buffer_info, 0,
4300 sizeof(struct igb_tx_buffer) * ring->count);
4301
4302 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
4303 wr32(E1000_TXDCTL(reg_idx), txdctl);
4304 }
4305
4306 /**
4307 * igb_configure_tx - Configure transmit Unit after Reset
4308 * @adapter: board private structure
4309 *
4310 * Configure the Tx unit of the MAC after a reset.
4311 **/
igb_configure_tx(struct igb_adapter * adapter)4312 static void igb_configure_tx(struct igb_adapter *adapter)
4313 {
4314 struct e1000_hw *hw = &adapter->hw;
4315 int i;
4316
4317 /* disable the queues */
4318 for (i = 0; i < adapter->num_tx_queues; i++)
4319 wr32(E1000_TXDCTL(adapter->tx_ring[i]->reg_idx), 0);
4320
4321 wrfl();
4322 usleep_range(10000, 20000);
4323
4324 for (i = 0; i < adapter->num_tx_queues; i++)
4325 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
4326 }
4327
4328 /**
4329 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
4330 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
4331 *
4332 * Returns 0 on success, negative on failure
4333 **/
igb_setup_rx_resources(struct igb_ring * rx_ring)4334 int igb_setup_rx_resources(struct igb_ring *rx_ring)
4335 {
4336 struct igb_adapter *adapter = netdev_priv(rx_ring->netdev);
4337 struct device *dev = rx_ring->dev;
4338 int size;
4339
4340 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
4341
4342 rx_ring->rx_buffer_info = vmalloc(size);
4343 if (!rx_ring->rx_buffer_info)
4344 goto err;
4345
4346 /* Round up to nearest 4K */
4347 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
4348 rx_ring->size = ALIGN(rx_ring->size, 4096);
4349
4350 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4351 &rx_ring->dma, GFP_KERNEL);
4352 if (!rx_ring->desc)
4353 goto err;
4354
4355 rx_ring->next_to_alloc = 0;
4356 rx_ring->next_to_clean = 0;
4357 rx_ring->next_to_use = 0;
4358
4359 rx_ring->xdp_prog = adapter->xdp_prog;
4360
4361 /* XDP RX-queue info */
4362 if (xdp_rxq_info_reg(&rx_ring->xdp_rxq, rx_ring->netdev,
4363 rx_ring->queue_index, 0) < 0)
4364 goto err;
4365
4366 return 0;
4367
4368 err:
4369 vfree(rx_ring->rx_buffer_info);
4370 rx_ring->rx_buffer_info = NULL;
4371 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
4372 return -ENOMEM;
4373 }
4374
4375 /**
4376 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
4377 * (Descriptors) for all queues
4378 * @adapter: board private structure
4379 *
4380 * Return 0 on success, negative on failure
4381 **/
igb_setup_all_rx_resources(struct igb_adapter * adapter)4382 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
4383 {
4384 struct pci_dev *pdev = adapter->pdev;
4385 int i, err = 0;
4386
4387 for (i = 0; i < adapter->num_rx_queues; i++) {
4388 err = igb_setup_rx_resources(adapter->rx_ring[i]);
4389 if (err) {
4390 dev_err(&pdev->dev,
4391 "Allocation for Rx Queue %u failed\n", i);
4392 for (i--; i >= 0; i--)
4393 igb_free_rx_resources(adapter->rx_ring[i]);
4394 break;
4395 }
4396 }
4397
4398 return err;
4399 }
4400
4401 /**
4402 * igb_setup_mrqc - configure the multiple receive queue control registers
4403 * @adapter: Board private structure
4404 **/
igb_setup_mrqc(struct igb_adapter * adapter)4405 static void igb_setup_mrqc(struct igb_adapter *adapter)
4406 {
4407 struct e1000_hw *hw = &adapter->hw;
4408 u32 mrqc, rxcsum;
4409 u32 j, num_rx_queues;
4410 u32 rss_key[10];
4411
4412 netdev_rss_key_fill(rss_key, sizeof(rss_key));
4413 for (j = 0; j < 10; j++)
4414 wr32(E1000_RSSRK(j), rss_key[j]);
4415
4416 num_rx_queues = adapter->rss_queues;
4417
4418 switch (hw->mac.type) {
4419 case e1000_82576:
4420 /* 82576 supports 2 RSS queues for SR-IOV */
4421 if (adapter->vfs_allocated_count)
4422 num_rx_queues = 2;
4423 break;
4424 default:
4425 break;
4426 }
4427
4428 if (adapter->rss_indir_tbl_init != num_rx_queues) {
4429 for (j = 0; j < IGB_RETA_SIZE; j++)
4430 adapter->rss_indir_tbl[j] =
4431 (j * num_rx_queues) / IGB_RETA_SIZE;
4432 adapter->rss_indir_tbl_init = num_rx_queues;
4433 }
4434 igb_write_rss_indir_tbl(adapter);
4435
4436 /* Disable raw packet checksumming so that RSS hash is placed in
4437 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
4438 * offloads as they are enabled by default
4439 */
4440 rxcsum = rd32(E1000_RXCSUM);
4441 rxcsum |= E1000_RXCSUM_PCSD;
4442
4443 if (adapter->hw.mac.type >= e1000_82576)
4444 /* Enable Receive Checksum Offload for SCTP */
4445 rxcsum |= E1000_RXCSUM_CRCOFL;
4446
4447 /* Don't need to set TUOFL or IPOFL, they default to 1 */
4448 wr32(E1000_RXCSUM, rxcsum);
4449
4450 /* Generate RSS hash based on packet types, TCP/UDP
4451 * port numbers and/or IPv4/v6 src and dst addresses
4452 */
4453 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
4454 E1000_MRQC_RSS_FIELD_IPV4_TCP |
4455 E1000_MRQC_RSS_FIELD_IPV6 |
4456 E1000_MRQC_RSS_FIELD_IPV6_TCP |
4457 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
4458
4459 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
4460 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
4461 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
4462 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
4463
4464 /* If VMDq is enabled then we set the appropriate mode for that, else
4465 * we default to RSS so that an RSS hash is calculated per packet even
4466 * if we are only using one queue
4467 */
4468 if (adapter->vfs_allocated_count) {
4469 if (hw->mac.type > e1000_82575) {
4470 /* Set the default pool for the PF's first queue */
4471 u32 vtctl = rd32(E1000_VT_CTL);
4472
4473 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
4474 E1000_VT_CTL_DISABLE_DEF_POOL);
4475 vtctl |= adapter->vfs_allocated_count <<
4476 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
4477 wr32(E1000_VT_CTL, vtctl);
4478 }
4479 if (adapter->rss_queues > 1)
4480 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ;
4481 else
4482 mrqc |= E1000_MRQC_ENABLE_VMDQ;
4483 } else {
4484 mrqc |= E1000_MRQC_ENABLE_RSS_MQ;
4485 }
4486 igb_vmm_control(adapter);
4487
4488 wr32(E1000_MRQC, mrqc);
4489 }
4490
4491 /**
4492 * igb_setup_rctl - configure the receive control registers
4493 * @adapter: Board private structure
4494 **/
igb_setup_rctl(struct igb_adapter * adapter)4495 void igb_setup_rctl(struct igb_adapter *adapter)
4496 {
4497 struct e1000_hw *hw = &adapter->hw;
4498 u32 rctl;
4499
4500 rctl = rd32(E1000_RCTL);
4501
4502 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
4503 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
4504
4505 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
4506 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
4507
4508 /* enable stripping of CRC. It's unlikely this will break BMC
4509 * redirection as it did with e1000. Newer features require
4510 * that the HW strips the CRC.
4511 */
4512 rctl |= E1000_RCTL_SECRC;
4513
4514 /* disable store bad packets and clear size bits. */
4515 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
4516
4517 /* enable LPE to allow for reception of jumbo frames */
4518 rctl |= E1000_RCTL_LPE;
4519
4520 /* disable queue 0 to prevent tail write w/o re-config */
4521 wr32(E1000_RXDCTL(0), 0);
4522
4523 /* Attention!!! For SR-IOV PF driver operations you must enable
4524 * queue drop for all VF and PF queues to prevent head of line blocking
4525 * if an un-trusted VF does not provide descriptors to hardware.
4526 */
4527 if (adapter->vfs_allocated_count) {
4528 /* set all queue drop enable bits */
4529 wr32(E1000_QDE, ALL_QUEUES);
4530 }
4531
4532 /* This is useful for sniffing bad packets. */
4533 if (adapter->netdev->features & NETIF_F_RXALL) {
4534 /* UPE and MPE will be handled by normal PROMISC logic
4535 * in e1000e_set_rx_mode
4536 */
4537 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
4538 E1000_RCTL_BAM | /* RX All Bcast Pkts */
4539 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
4540
4541 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */
4542 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
4543 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
4544 * and that breaks VLANs.
4545 */
4546 }
4547
4548 wr32(E1000_RCTL, rctl);
4549 }
4550
igb_set_vf_rlpml(struct igb_adapter * adapter,int size,int vfn)4551 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
4552 int vfn)
4553 {
4554 struct e1000_hw *hw = &adapter->hw;
4555 u32 vmolr;
4556
4557 if (size > MAX_JUMBO_FRAME_SIZE)
4558 size = MAX_JUMBO_FRAME_SIZE;
4559
4560 vmolr = rd32(E1000_VMOLR(vfn));
4561 vmolr &= ~E1000_VMOLR_RLPML_MASK;
4562 vmolr |= size | E1000_VMOLR_LPE;
4563 wr32(E1000_VMOLR(vfn), vmolr);
4564
4565 return 0;
4566 }
4567
igb_set_vf_vlan_strip(struct igb_adapter * adapter,int vfn,bool enable)4568 static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter,
4569 int vfn, bool enable)
4570 {
4571 struct e1000_hw *hw = &adapter->hw;
4572 u32 val, reg;
4573
4574 if (hw->mac.type < e1000_82576)
4575 return;
4576
4577 if (hw->mac.type == e1000_i350)
4578 reg = E1000_DVMOLR(vfn);
4579 else
4580 reg = E1000_VMOLR(vfn);
4581
4582 val = rd32(reg);
4583 if (enable)
4584 val |= E1000_VMOLR_STRVLAN;
4585 else
4586 val &= ~(E1000_VMOLR_STRVLAN);
4587 wr32(reg, val);
4588 }
4589
igb_set_vmolr(struct igb_adapter * adapter,int vfn,bool aupe)4590 static inline void igb_set_vmolr(struct igb_adapter *adapter,
4591 int vfn, bool aupe)
4592 {
4593 struct e1000_hw *hw = &adapter->hw;
4594 u32 vmolr;
4595
4596 /* This register exists only on 82576 and newer so if we are older then
4597 * we should exit and do nothing
4598 */
4599 if (hw->mac.type < e1000_82576)
4600 return;
4601
4602 vmolr = rd32(E1000_VMOLR(vfn));
4603 if (aupe)
4604 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
4605 else
4606 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
4607
4608 /* clear all bits that might not be set */
4609 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
4610
4611 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
4612 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
4613 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
4614 * multicast packets
4615 */
4616 if (vfn <= adapter->vfs_allocated_count)
4617 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
4618
4619 wr32(E1000_VMOLR(vfn), vmolr);
4620 }
4621
4622 /**
4623 * igb_setup_srrctl - configure the split and replication receive control
4624 * registers
4625 * @adapter: Board private structure
4626 * @ring: receive ring to be configured
4627 **/
igb_setup_srrctl(struct igb_adapter * adapter,struct igb_ring * ring)4628 void igb_setup_srrctl(struct igb_adapter *adapter, struct igb_ring *ring)
4629 {
4630 struct e1000_hw *hw = &adapter->hw;
4631 int reg_idx = ring->reg_idx;
4632 u32 srrctl = 0;
4633
4634 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
4635 if (ring_uses_large_buffer(ring))
4636 srrctl |= IGB_RXBUFFER_3072 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
4637 else
4638 srrctl |= IGB_RXBUFFER_2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
4639 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
4640 if (hw->mac.type >= e1000_82580)
4641 srrctl |= E1000_SRRCTL_TIMESTAMP;
4642 /* Only set Drop Enable if VFs allocated, or we are supporting multiple
4643 * queues and rx flow control is disabled
4644 */
4645 if (adapter->vfs_allocated_count ||
4646 (!(hw->fc.current_mode & e1000_fc_rx_pause) &&
4647 adapter->num_rx_queues > 1))
4648 srrctl |= E1000_SRRCTL_DROP_EN;
4649
4650 wr32(E1000_SRRCTL(reg_idx), srrctl);
4651 }
4652
4653 /**
4654 * igb_configure_rx_ring - Configure a receive ring after Reset
4655 * @adapter: board private structure
4656 * @ring: receive ring to be configured
4657 *
4658 * Configure the Rx unit of the MAC after a reset.
4659 **/
igb_configure_rx_ring(struct igb_adapter * adapter,struct igb_ring * ring)4660 void igb_configure_rx_ring(struct igb_adapter *adapter,
4661 struct igb_ring *ring)
4662 {
4663 struct e1000_hw *hw = &adapter->hw;
4664 union e1000_adv_rx_desc *rx_desc;
4665 u64 rdba = ring->dma;
4666 int reg_idx = ring->reg_idx;
4667 u32 rxdctl = 0;
4668
4669 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq);
4670 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq,
4671 MEM_TYPE_PAGE_SHARED, NULL));
4672
4673 /* disable the queue */
4674 wr32(E1000_RXDCTL(reg_idx), 0);
4675
4676 /* Set DMA base address registers */
4677 wr32(E1000_RDBAL(reg_idx),
4678 rdba & 0x00000000ffffffffULL);
4679 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
4680 wr32(E1000_RDLEN(reg_idx),
4681 ring->count * sizeof(union e1000_adv_rx_desc));
4682
4683 /* initialize head and tail */
4684 ring->tail = adapter->io_addr + E1000_RDT(reg_idx);
4685 wr32(E1000_RDH(reg_idx), 0);
4686 writel(0, ring->tail);
4687
4688 /* set descriptor configuration */
4689 igb_setup_srrctl(adapter, ring);
4690
4691 /* set filtering for VMDQ pools */
4692 igb_set_vmolr(adapter, reg_idx & 0x7, true);
4693
4694 rxdctl |= IGB_RX_PTHRESH;
4695 rxdctl |= IGB_RX_HTHRESH << 8;
4696 rxdctl |= IGB_RX_WTHRESH << 16;
4697
4698 /* initialize rx_buffer_info */
4699 memset(ring->rx_buffer_info, 0,
4700 sizeof(struct igb_rx_buffer) * ring->count);
4701
4702 /* initialize Rx descriptor 0 */
4703 rx_desc = IGB_RX_DESC(ring, 0);
4704 rx_desc->wb.upper.length = 0;
4705
4706 /* enable receive descriptor fetching */
4707 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
4708 wr32(E1000_RXDCTL(reg_idx), rxdctl);
4709 }
4710
igb_set_rx_buffer_len(struct igb_adapter * adapter,struct igb_ring * rx_ring)4711 static void igb_set_rx_buffer_len(struct igb_adapter *adapter,
4712 struct igb_ring *rx_ring)
4713 {
4714 /* set build_skb and buffer size flags */
4715 clear_ring_build_skb_enabled(rx_ring);
4716 clear_ring_uses_large_buffer(rx_ring);
4717
4718 if (adapter->flags & IGB_FLAG_RX_LEGACY)
4719 return;
4720
4721 set_ring_build_skb_enabled(rx_ring);
4722
4723 #if (PAGE_SIZE < 8192)
4724 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB)
4725 return;
4726
4727 set_ring_uses_large_buffer(rx_ring);
4728 #endif
4729 }
4730
4731 /**
4732 * igb_configure_rx - Configure receive Unit after Reset
4733 * @adapter: board private structure
4734 *
4735 * Configure the Rx unit of the MAC after a reset.
4736 **/
igb_configure_rx(struct igb_adapter * adapter)4737 static void igb_configure_rx(struct igb_adapter *adapter)
4738 {
4739 int i;
4740
4741 /* set the correct pool for the PF default MAC address in entry 0 */
4742 igb_set_default_mac_filter(adapter);
4743
4744 /* Setup the HW Rx Head and Tail Descriptor Pointers and
4745 * the Base and Length of the Rx Descriptor Ring
4746 */
4747 for (i = 0; i < adapter->num_rx_queues; i++) {
4748 struct igb_ring *rx_ring = adapter->rx_ring[i];
4749
4750 igb_set_rx_buffer_len(adapter, rx_ring);
4751 igb_configure_rx_ring(adapter, rx_ring);
4752 }
4753 }
4754
4755 /**
4756 * igb_free_tx_resources - Free Tx Resources per Queue
4757 * @tx_ring: Tx descriptor ring for a specific queue
4758 *
4759 * Free all transmit software resources
4760 **/
igb_free_tx_resources(struct igb_ring * tx_ring)4761 void igb_free_tx_resources(struct igb_ring *tx_ring)
4762 {
4763 igb_clean_tx_ring(tx_ring);
4764
4765 vfree(tx_ring->tx_buffer_info);
4766 tx_ring->tx_buffer_info = NULL;
4767
4768 /* if not set, then don't free */
4769 if (!tx_ring->desc)
4770 return;
4771
4772 dma_free_coherent(tx_ring->dev, tx_ring->size,
4773 tx_ring->desc, tx_ring->dma);
4774
4775 tx_ring->desc = NULL;
4776 }
4777
4778 /**
4779 * igb_free_all_tx_resources - Free Tx Resources for All Queues
4780 * @adapter: board private structure
4781 *
4782 * Free all transmit software resources
4783 **/
igb_free_all_tx_resources(struct igb_adapter * adapter)4784 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
4785 {
4786 int i;
4787
4788 for (i = 0; i < adapter->num_tx_queues; i++)
4789 if (adapter->tx_ring[i])
4790 igb_free_tx_resources(adapter->tx_ring[i]);
4791 }
4792
4793 /**
4794 * igb_clean_tx_ring - Free Tx Buffers
4795 * @tx_ring: ring to be cleaned
4796 **/
igb_clean_tx_ring(struct igb_ring * tx_ring)4797 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
4798 {
4799 u16 i = tx_ring->next_to_clean;
4800 struct igb_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i];
4801
4802 while (i != tx_ring->next_to_use) {
4803 union e1000_adv_tx_desc *eop_desc, *tx_desc;
4804
4805 /* Free all the Tx ring sk_buffs */
4806 dev_kfree_skb_any(tx_buffer->skb);
4807
4808 /* unmap skb header data */
4809 dma_unmap_single(tx_ring->dev,
4810 dma_unmap_addr(tx_buffer, dma),
4811 dma_unmap_len(tx_buffer, len),
4812 DMA_TO_DEVICE);
4813
4814 /* check for eop_desc to determine the end of the packet */
4815 eop_desc = tx_buffer->next_to_watch;
4816 tx_desc = IGB_TX_DESC(tx_ring, i);
4817
4818 /* unmap remaining buffers */
4819 while (tx_desc != eop_desc) {
4820 tx_buffer++;
4821 tx_desc++;
4822 i++;
4823 if (unlikely(i == tx_ring->count)) {
4824 i = 0;
4825 tx_buffer = tx_ring->tx_buffer_info;
4826 tx_desc = IGB_TX_DESC(tx_ring, 0);
4827 }
4828
4829 /* unmap any remaining paged data */
4830 if (dma_unmap_len(tx_buffer, len))
4831 dma_unmap_page(tx_ring->dev,
4832 dma_unmap_addr(tx_buffer, dma),
4833 dma_unmap_len(tx_buffer, len),
4834 DMA_TO_DEVICE);
4835 }
4836
4837 /* move us one more past the eop_desc for start of next pkt */
4838 tx_buffer++;
4839 i++;
4840 if (unlikely(i == tx_ring->count)) {
4841 i = 0;
4842 tx_buffer = tx_ring->tx_buffer_info;
4843 }
4844 }
4845
4846 /* reset BQL for queue */
4847 netdev_tx_reset_queue(txring_txq(tx_ring));
4848
4849 /* reset next_to_use and next_to_clean */
4850 tx_ring->next_to_use = 0;
4851 tx_ring->next_to_clean = 0;
4852 }
4853
4854 /**
4855 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
4856 * @adapter: board private structure
4857 **/
igb_clean_all_tx_rings(struct igb_adapter * adapter)4858 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
4859 {
4860 int i;
4861
4862 for (i = 0; i < adapter->num_tx_queues; i++)
4863 if (adapter->tx_ring[i])
4864 igb_clean_tx_ring(adapter->tx_ring[i]);
4865 }
4866
4867 /**
4868 * igb_free_rx_resources - Free Rx Resources
4869 * @rx_ring: ring to clean the resources from
4870 *
4871 * Free all receive software resources
4872 **/
igb_free_rx_resources(struct igb_ring * rx_ring)4873 void igb_free_rx_resources(struct igb_ring *rx_ring)
4874 {
4875 igb_clean_rx_ring(rx_ring);
4876
4877 rx_ring->xdp_prog = NULL;
4878 xdp_rxq_info_unreg(&rx_ring->xdp_rxq);
4879 vfree(rx_ring->rx_buffer_info);
4880 rx_ring->rx_buffer_info = NULL;
4881
4882 /* if not set, then don't free */
4883 if (!rx_ring->desc)
4884 return;
4885
4886 dma_free_coherent(rx_ring->dev, rx_ring->size,
4887 rx_ring->desc, rx_ring->dma);
4888
4889 rx_ring->desc = NULL;
4890 }
4891
4892 /**
4893 * igb_free_all_rx_resources - Free Rx Resources for All Queues
4894 * @adapter: board private structure
4895 *
4896 * Free all receive software resources
4897 **/
igb_free_all_rx_resources(struct igb_adapter * adapter)4898 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
4899 {
4900 int i;
4901
4902 for (i = 0; i < adapter->num_rx_queues; i++)
4903 if (adapter->rx_ring[i])
4904 igb_free_rx_resources(adapter->rx_ring[i]);
4905 }
4906
4907 /**
4908 * igb_clean_rx_ring - Free Rx Buffers per Queue
4909 * @rx_ring: ring to free buffers from
4910 **/
igb_clean_rx_ring(struct igb_ring * rx_ring)4911 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
4912 {
4913 u16 i = rx_ring->next_to_clean;
4914
4915 dev_kfree_skb(rx_ring->skb);
4916 rx_ring->skb = NULL;
4917
4918 /* Free all the Rx ring sk_buffs */
4919 while (i != rx_ring->next_to_alloc) {
4920 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
4921
4922 /* Invalidate cache lines that may have been written to by
4923 * device so that we avoid corrupting memory.
4924 */
4925 dma_sync_single_range_for_cpu(rx_ring->dev,
4926 buffer_info->dma,
4927 buffer_info->page_offset,
4928 igb_rx_bufsz(rx_ring),
4929 DMA_FROM_DEVICE);
4930
4931 /* free resources associated with mapping */
4932 dma_unmap_page_attrs(rx_ring->dev,
4933 buffer_info->dma,
4934 igb_rx_pg_size(rx_ring),
4935 DMA_FROM_DEVICE,
4936 IGB_RX_DMA_ATTR);
4937 __page_frag_cache_drain(buffer_info->page,
4938 buffer_info->pagecnt_bias);
4939
4940 i++;
4941 if (i == rx_ring->count)
4942 i = 0;
4943 }
4944
4945 rx_ring->next_to_alloc = 0;
4946 rx_ring->next_to_clean = 0;
4947 rx_ring->next_to_use = 0;
4948 }
4949
4950 /**
4951 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
4952 * @adapter: board private structure
4953 **/
igb_clean_all_rx_rings(struct igb_adapter * adapter)4954 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
4955 {
4956 int i;
4957
4958 for (i = 0; i < adapter->num_rx_queues; i++)
4959 if (adapter->rx_ring[i])
4960 igb_clean_rx_ring(adapter->rx_ring[i]);
4961 }
4962
4963 /**
4964 * igb_set_mac - Change the Ethernet Address of the NIC
4965 * @netdev: network interface device structure
4966 * @p: pointer to an address structure
4967 *
4968 * Returns 0 on success, negative on failure
4969 **/
igb_set_mac(struct net_device * netdev,void * p)4970 static int igb_set_mac(struct net_device *netdev, void *p)
4971 {
4972 struct igb_adapter *adapter = netdev_priv(netdev);
4973 struct e1000_hw *hw = &adapter->hw;
4974 struct sockaddr *addr = p;
4975
4976 if (!is_valid_ether_addr(addr->sa_data))
4977 return -EADDRNOTAVAIL;
4978
4979 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
4980 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
4981
4982 /* set the correct pool for the new PF MAC address in entry 0 */
4983 igb_set_default_mac_filter(adapter);
4984
4985 return 0;
4986 }
4987
4988 /**
4989 * igb_write_mc_addr_list - write multicast addresses to MTA
4990 * @netdev: network interface device structure
4991 *
4992 * Writes multicast address list to the MTA hash table.
4993 * Returns: -ENOMEM on failure
4994 * 0 on no addresses written
4995 * X on writing X addresses to MTA
4996 **/
igb_write_mc_addr_list(struct net_device * netdev)4997 static int igb_write_mc_addr_list(struct net_device *netdev)
4998 {
4999 struct igb_adapter *adapter = netdev_priv(netdev);
5000 struct e1000_hw *hw = &adapter->hw;
5001 struct netdev_hw_addr *ha;
5002 u8 *mta_list;
5003 int i;
5004
5005 if (netdev_mc_empty(netdev)) {
5006 /* nothing to program, so clear mc list */
5007 igb_update_mc_addr_list(hw, NULL, 0);
5008 igb_restore_vf_multicasts(adapter);
5009 return 0;
5010 }
5011
5012 mta_list = kcalloc(netdev_mc_count(netdev), 6, GFP_ATOMIC);
5013 if (!mta_list)
5014 return -ENOMEM;
5015
5016 /* The shared function expects a packed array of only addresses. */
5017 i = 0;
5018 netdev_for_each_mc_addr(ha, netdev)
5019 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
5020
5021 igb_update_mc_addr_list(hw, mta_list, i);
5022 kfree(mta_list);
5023
5024 return netdev_mc_count(netdev);
5025 }
5026
igb_vlan_promisc_enable(struct igb_adapter * adapter)5027 static int igb_vlan_promisc_enable(struct igb_adapter *adapter)
5028 {
5029 struct e1000_hw *hw = &adapter->hw;
5030 u32 i, pf_id;
5031
5032 switch (hw->mac.type) {
5033 case e1000_i210:
5034 case e1000_i211:
5035 case e1000_i350:
5036 /* VLAN filtering needed for VLAN prio filter */
5037 if (adapter->netdev->features & NETIF_F_NTUPLE)
5038 break;
5039 fallthrough;
5040 case e1000_82576:
5041 case e1000_82580:
5042 case e1000_i354:
5043 /* VLAN filtering needed for pool filtering */
5044 if (adapter->vfs_allocated_count)
5045 break;
5046 fallthrough;
5047 default:
5048 return 1;
5049 }
5050
5051 /* We are already in VLAN promisc, nothing to do */
5052 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
5053 return 0;
5054
5055 if (!adapter->vfs_allocated_count)
5056 goto set_vfta;
5057
5058 /* Add PF to all active pools */
5059 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
5060
5061 for (i = E1000_VLVF_ARRAY_SIZE; --i;) {
5062 u32 vlvf = rd32(E1000_VLVF(i));
5063
5064 vlvf |= BIT(pf_id);
5065 wr32(E1000_VLVF(i), vlvf);
5066 }
5067
5068 set_vfta:
5069 /* Set all bits in the VLAN filter table array */
5070 for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;)
5071 hw->mac.ops.write_vfta(hw, i, ~0U);
5072
5073 /* Set flag so we don't redo unnecessary work */
5074 adapter->flags |= IGB_FLAG_VLAN_PROMISC;
5075
5076 return 0;
5077 }
5078
5079 #define VFTA_BLOCK_SIZE 8
igb_scrub_vfta(struct igb_adapter * adapter,u32 vfta_offset)5080 static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset)
5081 {
5082 struct e1000_hw *hw = &adapter->hw;
5083 u32 vfta[VFTA_BLOCK_SIZE] = { 0 };
5084 u32 vid_start = vfta_offset * 32;
5085 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32);
5086 u32 i, vid, word, bits, pf_id;
5087
5088 /* guarantee that we don't scrub out management VLAN */
5089 vid = adapter->mng_vlan_id;
5090 if (vid >= vid_start && vid < vid_end)
5091 vfta[(vid - vid_start) / 32] |= BIT(vid % 32);
5092
5093 if (!adapter->vfs_allocated_count)
5094 goto set_vfta;
5095
5096 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
5097
5098 for (i = E1000_VLVF_ARRAY_SIZE; --i;) {
5099 u32 vlvf = rd32(E1000_VLVF(i));
5100
5101 /* pull VLAN ID from VLVF */
5102 vid = vlvf & VLAN_VID_MASK;
5103
5104 /* only concern ourselves with a certain range */
5105 if (vid < vid_start || vid >= vid_end)
5106 continue;
5107
5108 if (vlvf & E1000_VLVF_VLANID_ENABLE) {
5109 /* record VLAN ID in VFTA */
5110 vfta[(vid - vid_start) / 32] |= BIT(vid % 32);
5111
5112 /* if PF is part of this then continue */
5113 if (test_bit(vid, adapter->active_vlans))
5114 continue;
5115 }
5116
5117 /* remove PF from the pool */
5118 bits = ~BIT(pf_id);
5119 bits &= rd32(E1000_VLVF(i));
5120 wr32(E1000_VLVF(i), bits);
5121 }
5122
5123 set_vfta:
5124 /* extract values from active_vlans and write back to VFTA */
5125 for (i = VFTA_BLOCK_SIZE; i--;) {
5126 vid = (vfta_offset + i) * 32;
5127 word = vid / BITS_PER_LONG;
5128 bits = vid % BITS_PER_LONG;
5129
5130 vfta[i] |= adapter->active_vlans[word] >> bits;
5131
5132 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]);
5133 }
5134 }
5135
igb_vlan_promisc_disable(struct igb_adapter * adapter)5136 static void igb_vlan_promisc_disable(struct igb_adapter *adapter)
5137 {
5138 u32 i;
5139
5140 /* We are not in VLAN promisc, nothing to do */
5141 if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC))
5142 return;
5143
5144 /* Set flag so we don't redo unnecessary work */
5145 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC;
5146
5147 for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE)
5148 igb_scrub_vfta(adapter, i);
5149 }
5150
5151 /**
5152 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
5153 * @netdev: network interface device structure
5154 *
5155 * The set_rx_mode entry point is called whenever the unicast or multicast
5156 * address lists or the network interface flags are updated. This routine is
5157 * responsible for configuring the hardware for proper unicast, multicast,
5158 * promiscuous mode, and all-multi behavior.
5159 **/
igb_set_rx_mode(struct net_device * netdev)5160 static void igb_set_rx_mode(struct net_device *netdev)
5161 {
5162 struct igb_adapter *adapter = netdev_priv(netdev);
5163 struct e1000_hw *hw = &adapter->hw;
5164 unsigned int vfn = adapter->vfs_allocated_count;
5165 u32 rctl = 0, vmolr = 0, rlpml = MAX_JUMBO_FRAME_SIZE;
5166 int count;
5167
5168 /* Check for Promiscuous and All Multicast modes */
5169 if (netdev->flags & IFF_PROMISC) {
5170 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE;
5171 vmolr |= E1000_VMOLR_MPME;
5172
5173 /* enable use of UTA filter to force packets to default pool */
5174 if (hw->mac.type == e1000_82576)
5175 vmolr |= E1000_VMOLR_ROPE;
5176 } else {
5177 if (netdev->flags & IFF_ALLMULTI) {
5178 rctl |= E1000_RCTL_MPE;
5179 vmolr |= E1000_VMOLR_MPME;
5180 } else {
5181 /* Write addresses to the MTA, if the attempt fails
5182 * then we should just turn on promiscuous mode so
5183 * that we can at least receive multicast traffic
5184 */
5185 count = igb_write_mc_addr_list(netdev);
5186 if (count < 0) {
5187 rctl |= E1000_RCTL_MPE;
5188 vmolr |= E1000_VMOLR_MPME;
5189 } else if (count) {
5190 vmolr |= E1000_VMOLR_ROMPE;
5191 }
5192 }
5193 }
5194
5195 /* Write addresses to available RAR registers, if there is not
5196 * sufficient space to store all the addresses then enable
5197 * unicast promiscuous mode
5198 */
5199 if (__dev_uc_sync(netdev, igb_uc_sync, igb_uc_unsync)) {
5200 rctl |= E1000_RCTL_UPE;
5201 vmolr |= E1000_VMOLR_ROPE;
5202 }
5203
5204 /* enable VLAN filtering by default */
5205 rctl |= E1000_RCTL_VFE;
5206
5207 /* disable VLAN filtering for modes that require it */
5208 if ((netdev->flags & IFF_PROMISC) ||
5209 (netdev->features & NETIF_F_RXALL)) {
5210 /* if we fail to set all rules then just clear VFE */
5211 if (igb_vlan_promisc_enable(adapter))
5212 rctl &= ~E1000_RCTL_VFE;
5213 } else {
5214 igb_vlan_promisc_disable(adapter);
5215 }
5216
5217 /* update state of unicast, multicast, and VLAN filtering modes */
5218 rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE |
5219 E1000_RCTL_VFE);
5220 wr32(E1000_RCTL, rctl);
5221
5222 #if (PAGE_SIZE < 8192)
5223 if (!adapter->vfs_allocated_count) {
5224 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB)
5225 rlpml = IGB_MAX_FRAME_BUILD_SKB;
5226 }
5227 #endif
5228 wr32(E1000_RLPML, rlpml);
5229
5230 /* In order to support SR-IOV and eventually VMDq it is necessary to set
5231 * the VMOLR to enable the appropriate modes. Without this workaround
5232 * we will have issues with VLAN tag stripping not being done for frames
5233 * that are only arriving because we are the default pool
5234 */
5235 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
5236 return;
5237
5238 /* set UTA to appropriate mode */
5239 igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE));
5240
5241 vmolr |= rd32(E1000_VMOLR(vfn)) &
5242 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
5243
5244 /* enable Rx jumbo frames, restrict as needed to support build_skb */
5245 vmolr &= ~E1000_VMOLR_RLPML_MASK;
5246 #if (PAGE_SIZE < 8192)
5247 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB)
5248 vmolr |= IGB_MAX_FRAME_BUILD_SKB;
5249 else
5250 #endif
5251 vmolr |= MAX_JUMBO_FRAME_SIZE;
5252 vmolr |= E1000_VMOLR_LPE;
5253
5254 wr32(E1000_VMOLR(vfn), vmolr);
5255
5256 igb_restore_vf_multicasts(adapter);
5257 }
5258
igb_check_wvbr(struct igb_adapter * adapter)5259 static void igb_check_wvbr(struct igb_adapter *adapter)
5260 {
5261 struct e1000_hw *hw = &adapter->hw;
5262 u32 wvbr = 0;
5263
5264 switch (hw->mac.type) {
5265 case e1000_82576:
5266 case e1000_i350:
5267 wvbr = rd32(E1000_WVBR);
5268 if (!wvbr)
5269 return;
5270 break;
5271 default:
5272 break;
5273 }
5274
5275 adapter->wvbr |= wvbr;
5276 }
5277
5278 #define IGB_STAGGERED_QUEUE_OFFSET 8
5279
igb_spoof_check(struct igb_adapter * adapter)5280 static void igb_spoof_check(struct igb_adapter *adapter)
5281 {
5282 int j;
5283
5284 if (!adapter->wvbr)
5285 return;
5286
5287 for (j = 0; j < adapter->vfs_allocated_count; j++) {
5288 if (adapter->wvbr & BIT(j) ||
5289 adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) {
5290 dev_warn(&adapter->pdev->dev,
5291 "Spoof event(s) detected on VF %d\n", j);
5292 adapter->wvbr &=
5293 ~(BIT(j) |
5294 BIT(j + IGB_STAGGERED_QUEUE_OFFSET));
5295 }
5296 }
5297 }
5298
5299 /* Need to wait a few seconds after link up to get diagnostic information from
5300 * the phy
5301 */
igb_update_phy_info(struct timer_list * t)5302 static void igb_update_phy_info(struct timer_list *t)
5303 {
5304 struct igb_adapter *adapter = from_timer(adapter, t, phy_info_timer);
5305 igb_get_phy_info(&adapter->hw);
5306 }
5307
5308 /**
5309 * igb_has_link - check shared code for link and determine up/down
5310 * @adapter: pointer to driver private info
5311 **/
igb_has_link(struct igb_adapter * adapter)5312 bool igb_has_link(struct igb_adapter *adapter)
5313 {
5314 struct e1000_hw *hw = &adapter->hw;
5315 bool link_active = false;
5316
5317 /* get_link_status is set on LSC (link status) interrupt or
5318 * rx sequence error interrupt. get_link_status will stay
5319 * false until the e1000_check_for_link establishes link
5320 * for copper adapters ONLY
5321 */
5322 switch (hw->phy.media_type) {
5323 case e1000_media_type_copper:
5324 if (!hw->mac.get_link_status)
5325 return true;
5326 fallthrough;
5327 case e1000_media_type_internal_serdes:
5328 hw->mac.ops.check_for_link(hw);
5329 link_active = !hw->mac.get_link_status;
5330 break;
5331 default:
5332 case e1000_media_type_unknown:
5333 break;
5334 }
5335
5336 if (((hw->mac.type == e1000_i210) ||
5337 (hw->mac.type == e1000_i211)) &&
5338 (hw->phy.id == I210_I_PHY_ID)) {
5339 if (!netif_carrier_ok(adapter->netdev)) {
5340 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
5341 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
5342 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
5343 adapter->link_check_timeout = jiffies;
5344 }
5345 }
5346
5347 return link_active;
5348 }
5349
igb_thermal_sensor_event(struct e1000_hw * hw,u32 event)5350 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
5351 {
5352 bool ret = false;
5353 u32 ctrl_ext, thstat;
5354
5355 /* check for thermal sensor event on i350 copper only */
5356 if (hw->mac.type == e1000_i350) {
5357 thstat = rd32(E1000_THSTAT);
5358 ctrl_ext = rd32(E1000_CTRL_EXT);
5359
5360 if ((hw->phy.media_type == e1000_media_type_copper) &&
5361 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
5362 ret = !!(thstat & event);
5363 }
5364
5365 return ret;
5366 }
5367
5368 /**
5369 * igb_check_lvmmc - check for malformed packets received
5370 * and indicated in LVMMC register
5371 * @adapter: pointer to adapter
5372 **/
igb_check_lvmmc(struct igb_adapter * adapter)5373 static void igb_check_lvmmc(struct igb_adapter *adapter)
5374 {
5375 struct e1000_hw *hw = &adapter->hw;
5376 u32 lvmmc;
5377
5378 lvmmc = rd32(E1000_LVMMC);
5379 if (lvmmc) {
5380 if (unlikely(net_ratelimit())) {
5381 netdev_warn(adapter->netdev,
5382 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n",
5383 lvmmc);
5384 }
5385 }
5386 }
5387
5388 /**
5389 * igb_watchdog - Timer Call-back
5390 * @t: pointer to timer_list containing our private info pointer
5391 **/
igb_watchdog(struct timer_list * t)5392 static void igb_watchdog(struct timer_list *t)
5393 {
5394 struct igb_adapter *adapter = from_timer(adapter, t, watchdog_timer);
5395 /* Do the rest outside of interrupt context */
5396 schedule_work(&adapter->watchdog_task);
5397 }
5398
igb_watchdog_task(struct work_struct * work)5399 static void igb_watchdog_task(struct work_struct *work)
5400 {
5401 struct igb_adapter *adapter = container_of(work,
5402 struct igb_adapter,
5403 watchdog_task);
5404 struct e1000_hw *hw = &adapter->hw;
5405 struct e1000_phy_info *phy = &hw->phy;
5406 struct net_device *netdev = adapter->netdev;
5407 u32 link;
5408 int i;
5409 u32 connsw;
5410 u16 phy_data, retry_count = 20;
5411
5412 link = igb_has_link(adapter);
5413
5414 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
5415 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
5416 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
5417 else
5418 link = false;
5419 }
5420
5421 /* Force link down if we have fiber to swap to */
5422 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
5423 if (hw->phy.media_type == e1000_media_type_copper) {
5424 connsw = rd32(E1000_CONNSW);
5425 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN))
5426 link = 0;
5427 }
5428 }
5429 if (link) {
5430 /* Perform a reset if the media type changed. */
5431 if (hw->dev_spec._82575.media_changed) {
5432 hw->dev_spec._82575.media_changed = false;
5433 adapter->flags |= IGB_FLAG_MEDIA_RESET;
5434 igb_reset(adapter);
5435 }
5436 /* Cancel scheduled suspend requests. */
5437 pm_runtime_resume(netdev->dev.parent);
5438
5439 if (!netif_carrier_ok(netdev)) {
5440 u32 ctrl;
5441
5442 hw->mac.ops.get_speed_and_duplex(hw,
5443 &adapter->link_speed,
5444 &adapter->link_duplex);
5445
5446 ctrl = rd32(E1000_CTRL);
5447 /* Links status message must follow this format */
5448 netdev_info(netdev,
5449 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
5450 netdev->name,
5451 adapter->link_speed,
5452 adapter->link_duplex == FULL_DUPLEX ?
5453 "Full" : "Half",
5454 (ctrl & E1000_CTRL_TFCE) &&
5455 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
5456 (ctrl & E1000_CTRL_RFCE) ? "RX" :
5457 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
5458
5459 /* disable EEE if enabled */
5460 if ((adapter->flags & IGB_FLAG_EEE) &&
5461 (adapter->link_duplex == HALF_DUPLEX)) {
5462 dev_info(&adapter->pdev->dev,
5463 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n");
5464 adapter->hw.dev_spec._82575.eee_disable = true;
5465 adapter->flags &= ~IGB_FLAG_EEE;
5466 }
5467
5468 /* check if SmartSpeed worked */
5469 igb_check_downshift(hw);
5470 if (phy->speed_downgraded)
5471 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
5472
5473 /* check for thermal sensor event */
5474 if (igb_thermal_sensor_event(hw,
5475 E1000_THSTAT_LINK_THROTTLE))
5476 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n");
5477
5478 /* adjust timeout factor according to speed/duplex */
5479 adapter->tx_timeout_factor = 1;
5480 switch (adapter->link_speed) {
5481 case SPEED_10:
5482 adapter->tx_timeout_factor = 14;
5483 break;
5484 case SPEED_100:
5485 /* maybe add some timeout factor ? */
5486 break;
5487 }
5488
5489 if (adapter->link_speed != SPEED_1000)
5490 goto no_wait;
5491
5492 /* wait for Remote receiver status OK */
5493 retry_read_status:
5494 if (!igb_read_phy_reg(hw, PHY_1000T_STATUS,
5495 &phy_data)) {
5496 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) &&
5497 retry_count) {
5498 msleep(100);
5499 retry_count--;
5500 goto retry_read_status;
5501 } else if (!retry_count) {
5502 dev_err(&adapter->pdev->dev, "exceed max 2 second\n");
5503 }
5504 } else {
5505 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n");
5506 }
5507 no_wait:
5508 netif_carrier_on(netdev);
5509
5510 igb_ping_all_vfs(adapter);
5511 igb_check_vf_rate_limit(adapter);
5512
5513 /* link state has changed, schedule phy info update */
5514 if (!test_bit(__IGB_DOWN, &adapter->state))
5515 mod_timer(&adapter->phy_info_timer,
5516 round_jiffies(jiffies + 2 * HZ));
5517 }
5518 } else {
5519 if (netif_carrier_ok(netdev)) {
5520 adapter->link_speed = 0;
5521 adapter->link_duplex = 0;
5522
5523 /* check for thermal sensor event */
5524 if (igb_thermal_sensor_event(hw,
5525 E1000_THSTAT_PWR_DOWN)) {
5526 netdev_err(netdev, "The network adapter was stopped because it overheated\n");
5527 }
5528
5529 /* Links status message must follow this format */
5530 netdev_info(netdev, "igb: %s NIC Link is Down\n",
5531 netdev->name);
5532 netif_carrier_off(netdev);
5533
5534 igb_ping_all_vfs(adapter);
5535
5536 /* link state has changed, schedule phy info update */
5537 if (!test_bit(__IGB_DOWN, &adapter->state))
5538 mod_timer(&adapter->phy_info_timer,
5539 round_jiffies(jiffies + 2 * HZ));
5540
5541 /* link is down, time to check for alternate media */
5542 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
5543 igb_check_swap_media(adapter);
5544 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
5545 schedule_work(&adapter->reset_task);
5546 /* return immediately */
5547 return;
5548 }
5549 }
5550 pm_schedule_suspend(netdev->dev.parent,
5551 MSEC_PER_SEC * 5);
5552
5553 /* also check for alternate media here */
5554 } else if (!netif_carrier_ok(netdev) &&
5555 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
5556 igb_check_swap_media(adapter);
5557 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
5558 schedule_work(&adapter->reset_task);
5559 /* return immediately */
5560 return;
5561 }
5562 }
5563 }
5564
5565 spin_lock(&adapter->stats64_lock);
5566 igb_update_stats(adapter);
5567 spin_unlock(&adapter->stats64_lock);
5568
5569 for (i = 0; i < adapter->num_tx_queues; i++) {
5570 struct igb_ring *tx_ring = adapter->tx_ring[i];
5571 if (!netif_carrier_ok(netdev)) {
5572 /* We've lost link, so the controller stops DMA,
5573 * but we've got queued Tx work that's never going
5574 * to get done, so reset controller to flush Tx.
5575 * (Do the reset outside of interrupt context).
5576 */
5577 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
5578 adapter->tx_timeout_count++;
5579 schedule_work(&adapter->reset_task);
5580 /* return immediately since reset is imminent */
5581 return;
5582 }
5583 }
5584
5585 /* Force detection of hung controller every watchdog period */
5586 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
5587 }
5588
5589 /* Cause software interrupt to ensure Rx ring is cleaned */
5590 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
5591 u32 eics = 0;
5592
5593 for (i = 0; i < adapter->num_q_vectors; i++)
5594 eics |= adapter->q_vector[i]->eims_value;
5595 wr32(E1000_EICS, eics);
5596 } else {
5597 wr32(E1000_ICS, E1000_ICS_RXDMT0);
5598 }
5599
5600 igb_spoof_check(adapter);
5601 igb_ptp_rx_hang(adapter);
5602 igb_ptp_tx_hang(adapter);
5603
5604 /* Check LVMMC register on i350/i354 only */
5605 if ((adapter->hw.mac.type == e1000_i350) ||
5606 (adapter->hw.mac.type == e1000_i354))
5607 igb_check_lvmmc(adapter);
5608
5609 /* Reset the timer */
5610 if (!test_bit(__IGB_DOWN, &adapter->state)) {
5611 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
5612 mod_timer(&adapter->watchdog_timer,
5613 round_jiffies(jiffies + HZ));
5614 else
5615 mod_timer(&adapter->watchdog_timer,
5616 round_jiffies(jiffies + 2 * HZ));
5617 }
5618 }
5619
5620 enum latency_range {
5621 lowest_latency = 0,
5622 low_latency = 1,
5623 bulk_latency = 2,
5624 latency_invalid = 255
5625 };
5626
5627 /**
5628 * igb_update_ring_itr - update the dynamic ITR value based on packet size
5629 * @q_vector: pointer to q_vector
5630 *
5631 * Stores a new ITR value based on strictly on packet size. This
5632 * algorithm is less sophisticated than that used in igb_update_itr,
5633 * due to the difficulty of synchronizing statistics across multiple
5634 * receive rings. The divisors and thresholds used by this function
5635 * were determined based on theoretical maximum wire speed and testing
5636 * data, in order to minimize response time while increasing bulk
5637 * throughput.
5638 * This functionality is controlled by ethtool's coalescing settings.
5639 * NOTE: This function is called only when operating in a multiqueue
5640 * receive environment.
5641 **/
igb_update_ring_itr(struct igb_q_vector * q_vector)5642 static void igb_update_ring_itr(struct igb_q_vector *q_vector)
5643 {
5644 int new_val = q_vector->itr_val;
5645 int avg_wire_size = 0;
5646 struct igb_adapter *adapter = q_vector->adapter;
5647 unsigned int packets;
5648
5649 /* For non-gigabit speeds, just fix the interrupt rate at 4000
5650 * ints/sec - ITR timer value of 120 ticks.
5651 */
5652 if (adapter->link_speed != SPEED_1000) {
5653 new_val = IGB_4K_ITR;
5654 goto set_itr_val;
5655 }
5656
5657 packets = q_vector->rx.total_packets;
5658 if (packets)
5659 avg_wire_size = q_vector->rx.total_bytes / packets;
5660
5661 packets = q_vector->tx.total_packets;
5662 if (packets)
5663 avg_wire_size = max_t(u32, avg_wire_size,
5664 q_vector->tx.total_bytes / packets);
5665
5666 /* if avg_wire_size isn't set no work was done */
5667 if (!avg_wire_size)
5668 goto clear_counts;
5669
5670 /* Add 24 bytes to size to account for CRC, preamble, and gap */
5671 avg_wire_size += 24;
5672
5673 /* Don't starve jumbo frames */
5674 avg_wire_size = min(avg_wire_size, 3000);
5675
5676 /* Give a little boost to mid-size frames */
5677 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
5678 new_val = avg_wire_size / 3;
5679 else
5680 new_val = avg_wire_size / 2;
5681
5682 /* conservative mode (itr 3) eliminates the lowest_latency setting */
5683 if (new_val < IGB_20K_ITR &&
5684 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
5685 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
5686 new_val = IGB_20K_ITR;
5687
5688 set_itr_val:
5689 if (new_val != q_vector->itr_val) {
5690 q_vector->itr_val = new_val;
5691 q_vector->set_itr = 1;
5692 }
5693 clear_counts:
5694 q_vector->rx.total_bytes = 0;
5695 q_vector->rx.total_packets = 0;
5696 q_vector->tx.total_bytes = 0;
5697 q_vector->tx.total_packets = 0;
5698 }
5699
5700 /**
5701 * igb_update_itr - update the dynamic ITR value based on statistics
5702 * @q_vector: pointer to q_vector
5703 * @ring_container: ring info to update the itr for
5704 *
5705 * Stores a new ITR value based on packets and byte
5706 * counts during the last interrupt. The advantage of per interrupt
5707 * computation is faster updates and more accurate ITR for the current
5708 * traffic pattern. Constants in this function were computed
5709 * based on theoretical maximum wire speed and thresholds were set based
5710 * on testing data as well as attempting to minimize response time
5711 * while increasing bulk throughput.
5712 * This functionality is controlled by ethtool's coalescing settings.
5713 * NOTE: These calculations are only valid when operating in a single-
5714 * queue environment.
5715 **/
igb_update_itr(struct igb_q_vector * q_vector,struct igb_ring_container * ring_container)5716 static void igb_update_itr(struct igb_q_vector *q_vector,
5717 struct igb_ring_container *ring_container)
5718 {
5719 unsigned int packets = ring_container->total_packets;
5720 unsigned int bytes = ring_container->total_bytes;
5721 u8 itrval = ring_container->itr;
5722
5723 /* no packets, exit with status unchanged */
5724 if (packets == 0)
5725 return;
5726
5727 switch (itrval) {
5728 case lowest_latency:
5729 /* handle TSO and jumbo frames */
5730 if (bytes/packets > 8000)
5731 itrval = bulk_latency;
5732 else if ((packets < 5) && (bytes > 512))
5733 itrval = low_latency;
5734 break;
5735 case low_latency: /* 50 usec aka 20000 ints/s */
5736 if (bytes > 10000) {
5737 /* this if handles the TSO accounting */
5738 if (bytes/packets > 8000)
5739 itrval = bulk_latency;
5740 else if ((packets < 10) || ((bytes/packets) > 1200))
5741 itrval = bulk_latency;
5742 else if ((packets > 35))
5743 itrval = lowest_latency;
5744 } else if (bytes/packets > 2000) {
5745 itrval = bulk_latency;
5746 } else if (packets <= 2 && bytes < 512) {
5747 itrval = lowest_latency;
5748 }
5749 break;
5750 case bulk_latency: /* 250 usec aka 4000 ints/s */
5751 if (bytes > 25000) {
5752 if (packets > 35)
5753 itrval = low_latency;
5754 } else if (bytes < 1500) {
5755 itrval = low_latency;
5756 }
5757 break;
5758 }
5759
5760 /* clear work counters since we have the values we need */
5761 ring_container->total_bytes = 0;
5762 ring_container->total_packets = 0;
5763
5764 /* write updated itr to ring container */
5765 ring_container->itr = itrval;
5766 }
5767
igb_set_itr(struct igb_q_vector * q_vector)5768 static void igb_set_itr(struct igb_q_vector *q_vector)
5769 {
5770 struct igb_adapter *adapter = q_vector->adapter;
5771 u32 new_itr = q_vector->itr_val;
5772 u8 current_itr = 0;
5773
5774 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
5775 if (adapter->link_speed != SPEED_1000) {
5776 current_itr = 0;
5777 new_itr = IGB_4K_ITR;
5778 goto set_itr_now;
5779 }
5780
5781 igb_update_itr(q_vector, &q_vector->tx);
5782 igb_update_itr(q_vector, &q_vector->rx);
5783
5784 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
5785
5786 /* conservative mode (itr 3) eliminates the lowest_latency setting */
5787 if (current_itr == lowest_latency &&
5788 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
5789 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
5790 current_itr = low_latency;
5791
5792 switch (current_itr) {
5793 /* counts and packets in update_itr are dependent on these numbers */
5794 case lowest_latency:
5795 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
5796 break;
5797 case low_latency:
5798 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
5799 break;
5800 case bulk_latency:
5801 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
5802 break;
5803 default:
5804 break;
5805 }
5806
5807 set_itr_now:
5808 if (new_itr != q_vector->itr_val) {
5809 /* this attempts to bias the interrupt rate towards Bulk
5810 * by adding intermediate steps when interrupt rate is
5811 * increasing
5812 */
5813 new_itr = new_itr > q_vector->itr_val ?
5814 max((new_itr * q_vector->itr_val) /
5815 (new_itr + (q_vector->itr_val >> 2)),
5816 new_itr) : new_itr;
5817 /* Don't write the value here; it resets the adapter's
5818 * internal timer, and causes us to delay far longer than
5819 * we should between interrupts. Instead, we write the ITR
5820 * value at the beginning of the next interrupt so the timing
5821 * ends up being correct.
5822 */
5823 q_vector->itr_val = new_itr;
5824 q_vector->set_itr = 1;
5825 }
5826 }
5827
igb_tx_ctxtdesc(struct igb_ring * tx_ring,struct igb_tx_buffer * first,u32 vlan_macip_lens,u32 type_tucmd,u32 mss_l4len_idx)5828 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring,
5829 struct igb_tx_buffer *first,
5830 u32 vlan_macip_lens, u32 type_tucmd,
5831 u32 mss_l4len_idx)
5832 {
5833 struct e1000_adv_tx_context_desc *context_desc;
5834 u16 i = tx_ring->next_to_use;
5835 struct timespec64 ts;
5836
5837 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
5838
5839 i++;
5840 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
5841
5842 /* set bits to identify this as an advanced context descriptor */
5843 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
5844
5845 /* For 82575, context index must be unique per ring. */
5846 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
5847 mss_l4len_idx |= tx_ring->reg_idx << 4;
5848
5849 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5850 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
5851 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5852
5853 /* We assume there is always a valid tx time available. Invalid times
5854 * should have been handled by the upper layers.
5855 */
5856 if (tx_ring->launchtime_enable) {
5857 ts = ktime_to_timespec64(first->skb->tstamp);
5858 skb_txtime_consumed(first->skb);
5859 context_desc->seqnum_seed = cpu_to_le32(ts.tv_nsec / 32);
5860 } else {
5861 context_desc->seqnum_seed = 0;
5862 }
5863 }
5864
igb_tso(struct igb_ring * tx_ring,struct igb_tx_buffer * first,u8 * hdr_len)5865 static int igb_tso(struct igb_ring *tx_ring,
5866 struct igb_tx_buffer *first,
5867 u8 *hdr_len)
5868 {
5869 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx;
5870 struct sk_buff *skb = first->skb;
5871 union {
5872 struct iphdr *v4;
5873 struct ipv6hdr *v6;
5874 unsigned char *hdr;
5875 } ip;
5876 union {
5877 struct tcphdr *tcp;
5878 struct udphdr *udp;
5879 unsigned char *hdr;
5880 } l4;
5881 u32 paylen, l4_offset;
5882 int err;
5883
5884 if (skb->ip_summed != CHECKSUM_PARTIAL)
5885 return 0;
5886
5887 if (!skb_is_gso(skb))
5888 return 0;
5889
5890 err = skb_cow_head(skb, 0);
5891 if (err < 0)
5892 return err;
5893
5894 ip.hdr = skb_network_header(skb);
5895 l4.hdr = skb_checksum_start(skb);
5896
5897 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5898 type_tucmd = (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) ?
5899 E1000_ADVTXD_TUCMD_L4T_UDP : E1000_ADVTXD_TUCMD_L4T_TCP;
5900
5901 /* initialize outer IP header fields */
5902 if (ip.v4->version == 4) {
5903 unsigned char *csum_start = skb_checksum_start(skb);
5904 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4);
5905
5906 /* IP header will have to cancel out any data that
5907 * is not a part of the outer IP header
5908 */
5909 ip.v4->check = csum_fold(csum_partial(trans_start,
5910 csum_start - trans_start,
5911 0));
5912 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
5913
5914 ip.v4->tot_len = 0;
5915 first->tx_flags |= IGB_TX_FLAGS_TSO |
5916 IGB_TX_FLAGS_CSUM |
5917 IGB_TX_FLAGS_IPV4;
5918 } else {
5919 ip.v6->payload_len = 0;
5920 first->tx_flags |= IGB_TX_FLAGS_TSO |
5921 IGB_TX_FLAGS_CSUM;
5922 }
5923
5924 /* determine offset of inner transport header */
5925 l4_offset = l4.hdr - skb->data;
5926
5927 /* remove payload length from inner checksum */
5928 paylen = skb->len - l4_offset;
5929 if (type_tucmd & E1000_ADVTXD_TUCMD_L4T_TCP) {
5930 /* compute length of segmentation header */
5931 *hdr_len = (l4.tcp->doff * 4) + l4_offset;
5932 csum_replace_by_diff(&l4.tcp->check,
5933 (__force __wsum)htonl(paylen));
5934 } else {
5935 /* compute length of segmentation header */
5936 *hdr_len = sizeof(*l4.udp) + l4_offset;
5937 csum_replace_by_diff(&l4.udp->check,
5938 (__force __wsum)htonl(paylen));
5939 }
5940
5941 /* update gso size and bytecount with header size */
5942 first->gso_segs = skb_shinfo(skb)->gso_segs;
5943 first->bytecount += (first->gso_segs - 1) * *hdr_len;
5944
5945 /* MSS L4LEN IDX */
5946 mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT;
5947 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
5948
5949 /* VLAN MACLEN IPLEN */
5950 vlan_macip_lens = l4.hdr - ip.hdr;
5951 vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT;
5952 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
5953
5954 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens,
5955 type_tucmd, mss_l4len_idx);
5956
5957 return 1;
5958 }
5959
igb_tx_csum(struct igb_ring * tx_ring,struct igb_tx_buffer * first)5960 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
5961 {
5962 struct sk_buff *skb = first->skb;
5963 u32 vlan_macip_lens = 0;
5964 u32 type_tucmd = 0;
5965
5966 if (skb->ip_summed != CHECKSUM_PARTIAL) {
5967 csum_failed:
5968 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN) &&
5969 !tx_ring->launchtime_enable)
5970 return;
5971 goto no_csum;
5972 }
5973
5974 switch (skb->csum_offset) {
5975 case offsetof(struct tcphdr, check):
5976 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
5977 fallthrough;
5978 case offsetof(struct udphdr, check):
5979 break;
5980 case offsetof(struct sctphdr, checksum):
5981 /* validate that this is actually an SCTP request */
5982 if (skb_csum_is_sctp(skb)) {
5983 type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP;
5984 break;
5985 }
5986 fallthrough;
5987 default:
5988 skb_checksum_help(skb);
5989 goto csum_failed;
5990 }
5991
5992 /* update TX checksum flag */
5993 first->tx_flags |= IGB_TX_FLAGS_CSUM;
5994 vlan_macip_lens = skb_checksum_start_offset(skb) -
5995 skb_network_offset(skb);
5996 no_csum:
5997 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
5998 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
5999
6000 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, type_tucmd, 0);
6001 }
6002
6003 #define IGB_SET_FLAG(_input, _flag, _result) \
6004 ((_flag <= _result) ? \
6005 ((u32)(_input & _flag) * (_result / _flag)) : \
6006 ((u32)(_input & _flag) / (_flag / _result)))
6007
igb_tx_cmd_type(struct sk_buff * skb,u32 tx_flags)6008 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
6009 {
6010 /* set type for advanced descriptor with frame checksum insertion */
6011 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
6012 E1000_ADVTXD_DCMD_DEXT |
6013 E1000_ADVTXD_DCMD_IFCS;
6014
6015 /* set HW vlan bit if vlan is present */
6016 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
6017 (E1000_ADVTXD_DCMD_VLE));
6018
6019 /* set segmentation bits for TSO */
6020 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
6021 (E1000_ADVTXD_DCMD_TSE));
6022
6023 /* set timestamp bit if present */
6024 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
6025 (E1000_ADVTXD_MAC_TSTAMP));
6026
6027 /* insert frame checksum */
6028 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
6029
6030 return cmd_type;
6031 }
6032
igb_tx_olinfo_status(struct igb_ring * tx_ring,union e1000_adv_tx_desc * tx_desc,u32 tx_flags,unsigned int paylen)6033 static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
6034 union e1000_adv_tx_desc *tx_desc,
6035 u32 tx_flags, unsigned int paylen)
6036 {
6037 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
6038
6039 /* 82575 requires a unique index per ring */
6040 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
6041 olinfo_status |= tx_ring->reg_idx << 4;
6042
6043 /* insert L4 checksum */
6044 olinfo_status |= IGB_SET_FLAG(tx_flags,
6045 IGB_TX_FLAGS_CSUM,
6046 (E1000_TXD_POPTS_TXSM << 8));
6047
6048 /* insert IPv4 checksum */
6049 olinfo_status |= IGB_SET_FLAG(tx_flags,
6050 IGB_TX_FLAGS_IPV4,
6051 (E1000_TXD_POPTS_IXSM << 8));
6052
6053 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6054 }
6055
__igb_maybe_stop_tx(struct igb_ring * tx_ring,const u16 size)6056 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
6057 {
6058 struct net_device *netdev = tx_ring->netdev;
6059
6060 netif_stop_subqueue(netdev, tx_ring->queue_index);
6061
6062 /* Herbert's original patch had:
6063 * smp_mb__after_netif_stop_queue();
6064 * but since that doesn't exist yet, just open code it.
6065 */
6066 smp_mb();
6067
6068 /* We need to check again in a case another CPU has just
6069 * made room available.
6070 */
6071 if (igb_desc_unused(tx_ring) < size)
6072 return -EBUSY;
6073
6074 /* A reprieve! */
6075 netif_wake_subqueue(netdev, tx_ring->queue_index);
6076
6077 u64_stats_update_begin(&tx_ring->tx_syncp2);
6078 tx_ring->tx_stats.restart_queue2++;
6079 u64_stats_update_end(&tx_ring->tx_syncp2);
6080
6081 return 0;
6082 }
6083
igb_maybe_stop_tx(struct igb_ring * tx_ring,const u16 size)6084 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
6085 {
6086 if (igb_desc_unused(tx_ring) >= size)
6087 return 0;
6088 return __igb_maybe_stop_tx(tx_ring, size);
6089 }
6090
igb_tx_map(struct igb_ring * tx_ring,struct igb_tx_buffer * first,const u8 hdr_len)6091 static int igb_tx_map(struct igb_ring *tx_ring,
6092 struct igb_tx_buffer *first,
6093 const u8 hdr_len)
6094 {
6095 struct sk_buff *skb = first->skb;
6096 struct igb_tx_buffer *tx_buffer;
6097 union e1000_adv_tx_desc *tx_desc;
6098 skb_frag_t *frag;
6099 dma_addr_t dma;
6100 unsigned int data_len, size;
6101 u32 tx_flags = first->tx_flags;
6102 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
6103 u16 i = tx_ring->next_to_use;
6104
6105 tx_desc = IGB_TX_DESC(tx_ring, i);
6106
6107 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
6108
6109 size = skb_headlen(skb);
6110 data_len = skb->data_len;
6111
6112 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
6113
6114 tx_buffer = first;
6115
6116 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
6117 if (dma_mapping_error(tx_ring->dev, dma))
6118 goto dma_error;
6119
6120 /* record length, and DMA address */
6121 dma_unmap_len_set(tx_buffer, len, size);
6122 dma_unmap_addr_set(tx_buffer, dma, dma);
6123
6124 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6125
6126 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
6127 tx_desc->read.cmd_type_len =
6128 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
6129
6130 i++;
6131 tx_desc++;
6132 if (i == tx_ring->count) {
6133 tx_desc = IGB_TX_DESC(tx_ring, 0);
6134 i = 0;
6135 }
6136 tx_desc->read.olinfo_status = 0;
6137
6138 dma += IGB_MAX_DATA_PER_TXD;
6139 size -= IGB_MAX_DATA_PER_TXD;
6140
6141 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6142 }
6143
6144 if (likely(!data_len))
6145 break;
6146
6147 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
6148
6149 i++;
6150 tx_desc++;
6151 if (i == tx_ring->count) {
6152 tx_desc = IGB_TX_DESC(tx_ring, 0);
6153 i = 0;
6154 }
6155 tx_desc->read.olinfo_status = 0;
6156
6157 size = skb_frag_size(frag);
6158 data_len -= size;
6159
6160 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
6161 size, DMA_TO_DEVICE);
6162
6163 tx_buffer = &tx_ring->tx_buffer_info[i];
6164 }
6165
6166 /* write last descriptor with RS and EOP bits */
6167 cmd_type |= size | IGB_TXD_DCMD;
6168 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
6169
6170 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
6171
6172 /* set the timestamp */
6173 first->time_stamp = jiffies;
6174
6175 skb_tx_timestamp(skb);
6176
6177 /* Force memory writes to complete before letting h/w know there
6178 * are new descriptors to fetch. (Only applicable for weak-ordered
6179 * memory model archs, such as IA-64).
6180 *
6181 * We also need this memory barrier to make certain all of the
6182 * status bits have been updated before next_to_watch is written.
6183 */
6184 dma_wmb();
6185
6186 /* set next_to_watch value indicating a packet is present */
6187 first->next_to_watch = tx_desc;
6188
6189 i++;
6190 if (i == tx_ring->count)
6191 i = 0;
6192
6193 tx_ring->next_to_use = i;
6194
6195 /* Make sure there is space in the ring for the next send. */
6196 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
6197
6198 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) {
6199 writel(i, tx_ring->tail);
6200 }
6201 return 0;
6202
6203 dma_error:
6204 dev_err(tx_ring->dev, "TX DMA map failed\n");
6205 tx_buffer = &tx_ring->tx_buffer_info[i];
6206
6207 /* clear dma mappings for failed tx_buffer_info map */
6208 while (tx_buffer != first) {
6209 if (dma_unmap_len(tx_buffer, len))
6210 dma_unmap_page(tx_ring->dev,
6211 dma_unmap_addr(tx_buffer, dma),
6212 dma_unmap_len(tx_buffer, len),
6213 DMA_TO_DEVICE);
6214 dma_unmap_len_set(tx_buffer, len, 0);
6215
6216 if (i-- == 0)
6217 i += tx_ring->count;
6218 tx_buffer = &tx_ring->tx_buffer_info[i];
6219 }
6220
6221 if (dma_unmap_len(tx_buffer, len))
6222 dma_unmap_single(tx_ring->dev,
6223 dma_unmap_addr(tx_buffer, dma),
6224 dma_unmap_len(tx_buffer, len),
6225 DMA_TO_DEVICE);
6226 dma_unmap_len_set(tx_buffer, len, 0);
6227
6228 dev_kfree_skb_any(tx_buffer->skb);
6229 tx_buffer->skb = NULL;
6230
6231 tx_ring->next_to_use = i;
6232
6233 return -1;
6234 }
6235
igb_xmit_xdp_ring(struct igb_adapter * adapter,struct igb_ring * tx_ring,struct xdp_frame * xdpf)6236 int igb_xmit_xdp_ring(struct igb_adapter *adapter,
6237 struct igb_ring *tx_ring,
6238 struct xdp_frame *xdpf)
6239 {
6240 union e1000_adv_tx_desc *tx_desc;
6241 u32 len, cmd_type, olinfo_status;
6242 struct igb_tx_buffer *tx_buffer;
6243 dma_addr_t dma;
6244 u16 i;
6245
6246 len = xdpf->len;
6247
6248 if (unlikely(!igb_desc_unused(tx_ring)))
6249 return IGB_XDP_CONSUMED;
6250
6251 dma = dma_map_single(tx_ring->dev, xdpf->data, len, DMA_TO_DEVICE);
6252 if (dma_mapping_error(tx_ring->dev, dma))
6253 return IGB_XDP_CONSUMED;
6254
6255 /* record the location of the first descriptor for this packet */
6256 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6257 tx_buffer->bytecount = len;
6258 tx_buffer->gso_segs = 1;
6259 tx_buffer->protocol = 0;
6260
6261 i = tx_ring->next_to_use;
6262 tx_desc = IGB_TX_DESC(tx_ring, i);
6263
6264 dma_unmap_len_set(tx_buffer, len, len);
6265 dma_unmap_addr_set(tx_buffer, dma, dma);
6266 tx_buffer->type = IGB_TYPE_XDP;
6267 tx_buffer->xdpf = xdpf;
6268
6269 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6270
6271 /* put descriptor type bits */
6272 cmd_type = E1000_ADVTXD_DTYP_DATA |
6273 E1000_ADVTXD_DCMD_DEXT |
6274 E1000_ADVTXD_DCMD_IFCS;
6275 cmd_type |= len | IGB_TXD_DCMD;
6276 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
6277
6278 olinfo_status = cpu_to_le32(len << E1000_ADVTXD_PAYLEN_SHIFT);
6279 /* 82575 requires a unique index per ring */
6280 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
6281 olinfo_status |= tx_ring->reg_idx << 4;
6282
6283 tx_desc->read.olinfo_status = olinfo_status;
6284
6285 netdev_tx_sent_queue(txring_txq(tx_ring), tx_buffer->bytecount);
6286
6287 /* set the timestamp */
6288 tx_buffer->time_stamp = jiffies;
6289
6290 /* Avoid any potential race with xdp_xmit and cleanup */
6291 smp_wmb();
6292
6293 /* set next_to_watch value indicating a packet is present */
6294 i++;
6295 if (i == tx_ring->count)
6296 i = 0;
6297
6298 tx_buffer->next_to_watch = tx_desc;
6299 tx_ring->next_to_use = i;
6300
6301 /* Make sure there is space in the ring for the next send. */
6302 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
6303
6304 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more())
6305 writel(i, tx_ring->tail);
6306
6307 return IGB_XDP_TX;
6308 }
6309
igb_xmit_frame_ring(struct sk_buff * skb,struct igb_ring * tx_ring)6310 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
6311 struct igb_ring *tx_ring)
6312 {
6313 struct igb_tx_buffer *first;
6314 int tso;
6315 u32 tx_flags = 0;
6316 unsigned short f;
6317 u16 count = TXD_USE_COUNT(skb_headlen(skb));
6318 __be16 protocol = vlan_get_protocol(skb);
6319 u8 hdr_len = 0;
6320
6321 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
6322 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
6323 * + 2 desc gap to keep tail from touching head,
6324 * + 1 desc for context descriptor,
6325 * otherwise try next time
6326 */
6327 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6328 count += TXD_USE_COUNT(skb_frag_size(
6329 &skb_shinfo(skb)->frags[f]));
6330
6331 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
6332 /* this is a hard error */
6333 return NETDEV_TX_BUSY;
6334 }
6335
6336 /* record the location of the first descriptor for this packet */
6337 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6338 first->type = IGB_TYPE_SKB;
6339 first->skb = skb;
6340 first->bytecount = skb->len;
6341 first->gso_segs = 1;
6342
6343 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
6344 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
6345
6346 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON &&
6347 !test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS,
6348 &adapter->state)) {
6349 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
6350 tx_flags |= IGB_TX_FLAGS_TSTAMP;
6351
6352 adapter->ptp_tx_skb = skb_get(skb);
6353 adapter->ptp_tx_start = jiffies;
6354 if (adapter->hw.mac.type == e1000_82576)
6355 schedule_work(&adapter->ptp_tx_work);
6356 } else {
6357 adapter->tx_hwtstamp_skipped++;
6358 }
6359 }
6360
6361 if (skb_vlan_tag_present(skb)) {
6362 tx_flags |= IGB_TX_FLAGS_VLAN;
6363 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
6364 }
6365
6366 /* record initial flags and protocol */
6367 first->tx_flags = tx_flags;
6368 first->protocol = protocol;
6369
6370 tso = igb_tso(tx_ring, first, &hdr_len);
6371 if (tso < 0)
6372 goto out_drop;
6373 else if (!tso)
6374 igb_tx_csum(tx_ring, first);
6375
6376 if (igb_tx_map(tx_ring, first, hdr_len))
6377 goto cleanup_tx_tstamp;
6378
6379 return NETDEV_TX_OK;
6380
6381 out_drop:
6382 dev_kfree_skb_any(first->skb);
6383 first->skb = NULL;
6384 cleanup_tx_tstamp:
6385 if (unlikely(tx_flags & IGB_TX_FLAGS_TSTAMP)) {
6386 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
6387
6388 dev_kfree_skb_any(adapter->ptp_tx_skb);
6389 adapter->ptp_tx_skb = NULL;
6390 if (adapter->hw.mac.type == e1000_82576)
6391 cancel_work_sync(&adapter->ptp_tx_work);
6392 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
6393 }
6394
6395 return NETDEV_TX_OK;
6396 }
6397
igb_tx_queue_mapping(struct igb_adapter * adapter,struct sk_buff * skb)6398 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
6399 struct sk_buff *skb)
6400 {
6401 unsigned int r_idx = skb->queue_mapping;
6402
6403 if (r_idx >= adapter->num_tx_queues)
6404 r_idx = r_idx % adapter->num_tx_queues;
6405
6406 return adapter->tx_ring[r_idx];
6407 }
6408
igb_xmit_frame(struct sk_buff * skb,struct net_device * netdev)6409 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
6410 struct net_device *netdev)
6411 {
6412 struct igb_adapter *adapter = netdev_priv(netdev);
6413
6414 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
6415 * in order to meet this minimum size requirement.
6416 */
6417 if (skb_put_padto(skb, 17))
6418 return NETDEV_TX_OK;
6419
6420 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
6421 }
6422
6423 /**
6424 * igb_tx_timeout - Respond to a Tx Hang
6425 * @netdev: network interface device structure
6426 * @txqueue: number of the Tx queue that hung (unused)
6427 **/
igb_tx_timeout(struct net_device * netdev,unsigned int __always_unused txqueue)6428 static void igb_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue)
6429 {
6430 struct igb_adapter *adapter = netdev_priv(netdev);
6431 struct e1000_hw *hw = &adapter->hw;
6432
6433 /* Do the reset outside of interrupt context */
6434 adapter->tx_timeout_count++;
6435
6436 if (hw->mac.type >= e1000_82580)
6437 hw->dev_spec._82575.global_device_reset = true;
6438
6439 schedule_work(&adapter->reset_task);
6440 wr32(E1000_EICS,
6441 (adapter->eims_enable_mask & ~adapter->eims_other));
6442 }
6443
igb_reset_task(struct work_struct * work)6444 static void igb_reset_task(struct work_struct *work)
6445 {
6446 struct igb_adapter *adapter;
6447 adapter = container_of(work, struct igb_adapter, reset_task);
6448
6449 rtnl_lock();
6450 /* If we're already down or resetting, just bail */
6451 if (test_bit(__IGB_DOWN, &adapter->state) ||
6452 test_bit(__IGB_RESETTING, &adapter->state)) {
6453 rtnl_unlock();
6454 return;
6455 }
6456
6457 igb_dump(adapter);
6458 netdev_err(adapter->netdev, "Reset adapter\n");
6459 igb_reinit_locked(adapter);
6460 rtnl_unlock();
6461 }
6462
6463 /**
6464 * igb_get_stats64 - Get System Network Statistics
6465 * @netdev: network interface device structure
6466 * @stats: rtnl_link_stats64 pointer
6467 **/
igb_get_stats64(struct net_device * netdev,struct rtnl_link_stats64 * stats)6468 static void igb_get_stats64(struct net_device *netdev,
6469 struct rtnl_link_stats64 *stats)
6470 {
6471 struct igb_adapter *adapter = netdev_priv(netdev);
6472
6473 spin_lock(&adapter->stats64_lock);
6474 igb_update_stats(adapter);
6475 memcpy(stats, &adapter->stats64, sizeof(*stats));
6476 spin_unlock(&adapter->stats64_lock);
6477 }
6478
6479 /**
6480 * igb_change_mtu - Change the Maximum Transfer Unit
6481 * @netdev: network interface device structure
6482 * @new_mtu: new value for maximum frame size
6483 *
6484 * Returns 0 on success, negative on failure
6485 **/
igb_change_mtu(struct net_device * netdev,int new_mtu)6486 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
6487 {
6488 struct igb_adapter *adapter = netdev_priv(netdev);
6489 int max_frame = new_mtu + IGB_ETH_PKT_HDR_PAD;
6490
6491 if (adapter->xdp_prog) {
6492 int i;
6493
6494 for (i = 0; i < adapter->num_rx_queues; i++) {
6495 struct igb_ring *ring = adapter->rx_ring[i];
6496
6497 if (max_frame > igb_rx_bufsz(ring)) {
6498 netdev_warn(adapter->netdev,
6499 "Requested MTU size is not supported with XDP. Max frame size is %d\n",
6500 max_frame);
6501 return -EINVAL;
6502 }
6503 }
6504 }
6505
6506 /* adjust max frame to be at least the size of a standard frame */
6507 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
6508 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
6509
6510 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
6511 usleep_range(1000, 2000);
6512
6513 /* igb_down has a dependency on max_frame_size */
6514 adapter->max_frame_size = max_frame;
6515
6516 if (netif_running(netdev))
6517 igb_down(adapter);
6518
6519 netdev_dbg(netdev, "changing MTU from %d to %d\n",
6520 netdev->mtu, new_mtu);
6521 netdev->mtu = new_mtu;
6522
6523 if (netif_running(netdev))
6524 igb_up(adapter);
6525 else
6526 igb_reset(adapter);
6527
6528 clear_bit(__IGB_RESETTING, &adapter->state);
6529
6530 return 0;
6531 }
6532
6533 /**
6534 * igb_update_stats - Update the board statistics counters
6535 * @adapter: board private structure
6536 **/
igb_update_stats(struct igb_adapter * adapter)6537 void igb_update_stats(struct igb_adapter *adapter)
6538 {
6539 struct rtnl_link_stats64 *net_stats = &adapter->stats64;
6540 struct e1000_hw *hw = &adapter->hw;
6541 struct pci_dev *pdev = adapter->pdev;
6542 u32 reg, mpc;
6543 int i;
6544 u64 bytes, packets;
6545 unsigned int start;
6546 u64 _bytes, _packets;
6547
6548 /* Prevent stats update while adapter is being reset, or if the pci
6549 * connection is down.
6550 */
6551 if (adapter->link_speed == 0)
6552 return;
6553 if (pci_channel_offline(pdev))
6554 return;
6555
6556 bytes = 0;
6557 packets = 0;
6558
6559 rcu_read_lock();
6560 for (i = 0; i < adapter->num_rx_queues; i++) {
6561 struct igb_ring *ring = adapter->rx_ring[i];
6562 u32 rqdpc = rd32(E1000_RQDPC(i));
6563 if (hw->mac.type >= e1000_i210)
6564 wr32(E1000_RQDPC(i), 0);
6565
6566 if (rqdpc) {
6567 ring->rx_stats.drops += rqdpc;
6568 net_stats->rx_fifo_errors += rqdpc;
6569 }
6570
6571 do {
6572 start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
6573 _bytes = ring->rx_stats.bytes;
6574 _packets = ring->rx_stats.packets;
6575 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
6576 bytes += _bytes;
6577 packets += _packets;
6578 }
6579
6580 net_stats->rx_bytes = bytes;
6581 net_stats->rx_packets = packets;
6582
6583 bytes = 0;
6584 packets = 0;
6585 for (i = 0; i < adapter->num_tx_queues; i++) {
6586 struct igb_ring *ring = adapter->tx_ring[i];
6587 do {
6588 start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
6589 _bytes = ring->tx_stats.bytes;
6590 _packets = ring->tx_stats.packets;
6591 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
6592 bytes += _bytes;
6593 packets += _packets;
6594 }
6595 net_stats->tx_bytes = bytes;
6596 net_stats->tx_packets = packets;
6597 rcu_read_unlock();
6598
6599 /* read stats registers */
6600 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
6601 adapter->stats.gprc += rd32(E1000_GPRC);
6602 adapter->stats.gorc += rd32(E1000_GORCL);
6603 rd32(E1000_GORCH); /* clear GORCL */
6604 adapter->stats.bprc += rd32(E1000_BPRC);
6605 adapter->stats.mprc += rd32(E1000_MPRC);
6606 adapter->stats.roc += rd32(E1000_ROC);
6607
6608 adapter->stats.prc64 += rd32(E1000_PRC64);
6609 adapter->stats.prc127 += rd32(E1000_PRC127);
6610 adapter->stats.prc255 += rd32(E1000_PRC255);
6611 adapter->stats.prc511 += rd32(E1000_PRC511);
6612 adapter->stats.prc1023 += rd32(E1000_PRC1023);
6613 adapter->stats.prc1522 += rd32(E1000_PRC1522);
6614 adapter->stats.symerrs += rd32(E1000_SYMERRS);
6615 adapter->stats.sec += rd32(E1000_SEC);
6616
6617 mpc = rd32(E1000_MPC);
6618 adapter->stats.mpc += mpc;
6619 net_stats->rx_fifo_errors += mpc;
6620 adapter->stats.scc += rd32(E1000_SCC);
6621 adapter->stats.ecol += rd32(E1000_ECOL);
6622 adapter->stats.mcc += rd32(E1000_MCC);
6623 adapter->stats.latecol += rd32(E1000_LATECOL);
6624 adapter->stats.dc += rd32(E1000_DC);
6625 adapter->stats.rlec += rd32(E1000_RLEC);
6626 adapter->stats.xonrxc += rd32(E1000_XONRXC);
6627 adapter->stats.xontxc += rd32(E1000_XONTXC);
6628 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
6629 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
6630 adapter->stats.fcruc += rd32(E1000_FCRUC);
6631 adapter->stats.gptc += rd32(E1000_GPTC);
6632 adapter->stats.gotc += rd32(E1000_GOTCL);
6633 rd32(E1000_GOTCH); /* clear GOTCL */
6634 adapter->stats.rnbc += rd32(E1000_RNBC);
6635 adapter->stats.ruc += rd32(E1000_RUC);
6636 adapter->stats.rfc += rd32(E1000_RFC);
6637 adapter->stats.rjc += rd32(E1000_RJC);
6638 adapter->stats.tor += rd32(E1000_TORH);
6639 adapter->stats.tot += rd32(E1000_TOTH);
6640 adapter->stats.tpr += rd32(E1000_TPR);
6641
6642 adapter->stats.ptc64 += rd32(E1000_PTC64);
6643 adapter->stats.ptc127 += rd32(E1000_PTC127);
6644 adapter->stats.ptc255 += rd32(E1000_PTC255);
6645 adapter->stats.ptc511 += rd32(E1000_PTC511);
6646 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
6647 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
6648
6649 adapter->stats.mptc += rd32(E1000_MPTC);
6650 adapter->stats.bptc += rd32(E1000_BPTC);
6651
6652 adapter->stats.tpt += rd32(E1000_TPT);
6653 adapter->stats.colc += rd32(E1000_COLC);
6654
6655 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
6656 /* read internal phy specific stats */
6657 reg = rd32(E1000_CTRL_EXT);
6658 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
6659 adapter->stats.rxerrc += rd32(E1000_RXERRC);
6660
6661 /* this stat has invalid values on i210/i211 */
6662 if ((hw->mac.type != e1000_i210) &&
6663 (hw->mac.type != e1000_i211))
6664 adapter->stats.tncrs += rd32(E1000_TNCRS);
6665 }
6666
6667 adapter->stats.tsctc += rd32(E1000_TSCTC);
6668 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
6669
6670 adapter->stats.iac += rd32(E1000_IAC);
6671 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
6672 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
6673 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
6674 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
6675 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
6676 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
6677 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
6678 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
6679
6680 /* Fill out the OS statistics structure */
6681 net_stats->multicast = adapter->stats.mprc;
6682 net_stats->collisions = adapter->stats.colc;
6683
6684 /* Rx Errors */
6685
6686 /* RLEC on some newer hardware can be incorrect so build
6687 * our own version based on RUC and ROC
6688 */
6689 net_stats->rx_errors = adapter->stats.rxerrc +
6690 adapter->stats.crcerrs + adapter->stats.algnerrc +
6691 adapter->stats.ruc + adapter->stats.roc +
6692 adapter->stats.cexterr;
6693 net_stats->rx_length_errors = adapter->stats.ruc +
6694 adapter->stats.roc;
6695 net_stats->rx_crc_errors = adapter->stats.crcerrs;
6696 net_stats->rx_frame_errors = adapter->stats.algnerrc;
6697 net_stats->rx_missed_errors = adapter->stats.mpc;
6698
6699 /* Tx Errors */
6700 net_stats->tx_errors = adapter->stats.ecol +
6701 adapter->stats.latecol;
6702 net_stats->tx_aborted_errors = adapter->stats.ecol;
6703 net_stats->tx_window_errors = adapter->stats.latecol;
6704 net_stats->tx_carrier_errors = adapter->stats.tncrs;
6705
6706 /* Tx Dropped needs to be maintained elsewhere */
6707
6708 /* Management Stats */
6709 adapter->stats.mgptc += rd32(E1000_MGTPTC);
6710 adapter->stats.mgprc += rd32(E1000_MGTPRC);
6711 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
6712
6713 /* OS2BMC Stats */
6714 reg = rd32(E1000_MANC);
6715 if (reg & E1000_MANC_EN_BMC2OS) {
6716 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
6717 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
6718 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
6719 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
6720 }
6721 }
6722
igb_tsync_interrupt(struct igb_adapter * adapter)6723 static void igb_tsync_interrupt(struct igb_adapter *adapter)
6724 {
6725 struct e1000_hw *hw = &adapter->hw;
6726 struct ptp_clock_event event;
6727 struct timespec64 ts;
6728 u32 ack = 0, tsauxc, sec, nsec, tsicr = rd32(E1000_TSICR);
6729
6730 if (tsicr & TSINTR_SYS_WRAP) {
6731 event.type = PTP_CLOCK_PPS;
6732 if (adapter->ptp_caps.pps)
6733 ptp_clock_event(adapter->ptp_clock, &event);
6734 ack |= TSINTR_SYS_WRAP;
6735 }
6736
6737 if (tsicr & E1000_TSICR_TXTS) {
6738 /* retrieve hardware timestamp */
6739 schedule_work(&adapter->ptp_tx_work);
6740 ack |= E1000_TSICR_TXTS;
6741 }
6742
6743 if (tsicr & TSINTR_TT0) {
6744 spin_lock(&adapter->tmreg_lock);
6745 ts = timespec64_add(adapter->perout[0].start,
6746 adapter->perout[0].period);
6747 /* u32 conversion of tv_sec is safe until y2106 */
6748 wr32(E1000_TRGTTIML0, ts.tv_nsec);
6749 wr32(E1000_TRGTTIMH0, (u32)ts.tv_sec);
6750 tsauxc = rd32(E1000_TSAUXC);
6751 tsauxc |= TSAUXC_EN_TT0;
6752 wr32(E1000_TSAUXC, tsauxc);
6753 adapter->perout[0].start = ts;
6754 spin_unlock(&adapter->tmreg_lock);
6755 ack |= TSINTR_TT0;
6756 }
6757
6758 if (tsicr & TSINTR_TT1) {
6759 spin_lock(&adapter->tmreg_lock);
6760 ts = timespec64_add(adapter->perout[1].start,
6761 adapter->perout[1].period);
6762 wr32(E1000_TRGTTIML1, ts.tv_nsec);
6763 wr32(E1000_TRGTTIMH1, (u32)ts.tv_sec);
6764 tsauxc = rd32(E1000_TSAUXC);
6765 tsauxc |= TSAUXC_EN_TT1;
6766 wr32(E1000_TSAUXC, tsauxc);
6767 adapter->perout[1].start = ts;
6768 spin_unlock(&adapter->tmreg_lock);
6769 ack |= TSINTR_TT1;
6770 }
6771
6772 if (tsicr & TSINTR_AUTT0) {
6773 nsec = rd32(E1000_AUXSTMPL0);
6774 sec = rd32(E1000_AUXSTMPH0);
6775 event.type = PTP_CLOCK_EXTTS;
6776 event.index = 0;
6777 event.timestamp = sec * 1000000000ULL + nsec;
6778 ptp_clock_event(adapter->ptp_clock, &event);
6779 ack |= TSINTR_AUTT0;
6780 }
6781
6782 if (tsicr & TSINTR_AUTT1) {
6783 nsec = rd32(E1000_AUXSTMPL1);
6784 sec = rd32(E1000_AUXSTMPH1);
6785 event.type = PTP_CLOCK_EXTTS;
6786 event.index = 1;
6787 event.timestamp = sec * 1000000000ULL + nsec;
6788 ptp_clock_event(adapter->ptp_clock, &event);
6789 ack |= TSINTR_AUTT1;
6790 }
6791
6792 /* acknowledge the interrupts */
6793 wr32(E1000_TSICR, ack);
6794 }
6795
igb_msix_other(int irq,void * data)6796 static irqreturn_t igb_msix_other(int irq, void *data)
6797 {
6798 struct igb_adapter *adapter = data;
6799 struct e1000_hw *hw = &adapter->hw;
6800 u32 icr = rd32(E1000_ICR);
6801 /* reading ICR causes bit 31 of EICR to be cleared */
6802
6803 if (icr & E1000_ICR_DRSTA)
6804 schedule_work(&adapter->reset_task);
6805
6806 if (icr & E1000_ICR_DOUTSYNC) {
6807 /* HW is reporting DMA is out of sync */
6808 adapter->stats.doosync++;
6809 /* The DMA Out of Sync is also indication of a spoof event
6810 * in IOV mode. Check the Wrong VM Behavior register to
6811 * see if it is really a spoof event.
6812 */
6813 igb_check_wvbr(adapter);
6814 }
6815
6816 /* Check for a mailbox event */
6817 if (icr & E1000_ICR_VMMB)
6818 igb_msg_task(adapter);
6819
6820 if (icr & E1000_ICR_LSC) {
6821 hw->mac.get_link_status = 1;
6822 /* guard against interrupt when we're going down */
6823 if (!test_bit(__IGB_DOWN, &adapter->state))
6824 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6825 }
6826
6827 if (icr & E1000_ICR_TS)
6828 igb_tsync_interrupt(adapter);
6829
6830 wr32(E1000_EIMS, adapter->eims_other);
6831
6832 return IRQ_HANDLED;
6833 }
6834
igb_write_itr(struct igb_q_vector * q_vector)6835 static void igb_write_itr(struct igb_q_vector *q_vector)
6836 {
6837 struct igb_adapter *adapter = q_vector->adapter;
6838 u32 itr_val = q_vector->itr_val & 0x7FFC;
6839
6840 if (!q_vector->set_itr)
6841 return;
6842
6843 if (!itr_val)
6844 itr_val = 0x4;
6845
6846 if (adapter->hw.mac.type == e1000_82575)
6847 itr_val |= itr_val << 16;
6848 else
6849 itr_val |= E1000_EITR_CNT_IGNR;
6850
6851 writel(itr_val, q_vector->itr_register);
6852 q_vector->set_itr = 0;
6853 }
6854
igb_msix_ring(int irq,void * data)6855 static irqreturn_t igb_msix_ring(int irq, void *data)
6856 {
6857 struct igb_q_vector *q_vector = data;
6858
6859 /* Write the ITR value calculated from the previous interrupt. */
6860 igb_write_itr(q_vector);
6861
6862 napi_schedule(&q_vector->napi);
6863
6864 return IRQ_HANDLED;
6865 }
6866
6867 #ifdef CONFIG_IGB_DCA
igb_update_tx_dca(struct igb_adapter * adapter,struct igb_ring * tx_ring,int cpu)6868 static void igb_update_tx_dca(struct igb_adapter *adapter,
6869 struct igb_ring *tx_ring,
6870 int cpu)
6871 {
6872 struct e1000_hw *hw = &adapter->hw;
6873 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
6874
6875 if (hw->mac.type != e1000_82575)
6876 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
6877
6878 /* We can enable relaxed ordering for reads, but not writes when
6879 * DCA is enabled. This is due to a known issue in some chipsets
6880 * which will cause the DCA tag to be cleared.
6881 */
6882 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
6883 E1000_DCA_TXCTRL_DATA_RRO_EN |
6884 E1000_DCA_TXCTRL_DESC_DCA_EN;
6885
6886 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
6887 }
6888
igb_update_rx_dca(struct igb_adapter * adapter,struct igb_ring * rx_ring,int cpu)6889 static void igb_update_rx_dca(struct igb_adapter *adapter,
6890 struct igb_ring *rx_ring,
6891 int cpu)
6892 {
6893 struct e1000_hw *hw = &adapter->hw;
6894 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
6895
6896 if (hw->mac.type != e1000_82575)
6897 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
6898
6899 /* We can enable relaxed ordering for reads, but not writes when
6900 * DCA is enabled. This is due to a known issue in some chipsets
6901 * which will cause the DCA tag to be cleared.
6902 */
6903 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
6904 E1000_DCA_RXCTRL_DESC_DCA_EN;
6905
6906 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
6907 }
6908
igb_update_dca(struct igb_q_vector * q_vector)6909 static void igb_update_dca(struct igb_q_vector *q_vector)
6910 {
6911 struct igb_adapter *adapter = q_vector->adapter;
6912 int cpu = get_cpu();
6913
6914 if (q_vector->cpu == cpu)
6915 goto out_no_update;
6916
6917 if (q_vector->tx.ring)
6918 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
6919
6920 if (q_vector->rx.ring)
6921 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
6922
6923 q_vector->cpu = cpu;
6924 out_no_update:
6925 put_cpu();
6926 }
6927
igb_setup_dca(struct igb_adapter * adapter)6928 static void igb_setup_dca(struct igb_adapter *adapter)
6929 {
6930 struct e1000_hw *hw = &adapter->hw;
6931 int i;
6932
6933 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
6934 return;
6935
6936 /* Always use CB2 mode, difference is masked in the CB driver. */
6937 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
6938
6939 for (i = 0; i < adapter->num_q_vectors; i++) {
6940 adapter->q_vector[i]->cpu = -1;
6941 igb_update_dca(adapter->q_vector[i]);
6942 }
6943 }
6944
__igb_notify_dca(struct device * dev,void * data)6945 static int __igb_notify_dca(struct device *dev, void *data)
6946 {
6947 struct net_device *netdev = dev_get_drvdata(dev);
6948 struct igb_adapter *adapter = netdev_priv(netdev);
6949 struct pci_dev *pdev = adapter->pdev;
6950 struct e1000_hw *hw = &adapter->hw;
6951 unsigned long event = *(unsigned long *)data;
6952
6953 switch (event) {
6954 case DCA_PROVIDER_ADD:
6955 /* if already enabled, don't do it again */
6956 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
6957 break;
6958 if (dca_add_requester(dev) == 0) {
6959 adapter->flags |= IGB_FLAG_DCA_ENABLED;
6960 dev_info(&pdev->dev, "DCA enabled\n");
6961 igb_setup_dca(adapter);
6962 break;
6963 }
6964 fallthrough; /* since DCA is disabled. */
6965 case DCA_PROVIDER_REMOVE:
6966 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
6967 /* without this a class_device is left
6968 * hanging around in the sysfs model
6969 */
6970 dca_remove_requester(dev);
6971 dev_info(&pdev->dev, "DCA disabled\n");
6972 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
6973 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
6974 }
6975 break;
6976 }
6977
6978 return 0;
6979 }
6980
igb_notify_dca(struct notifier_block * nb,unsigned long event,void * p)6981 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
6982 void *p)
6983 {
6984 int ret_val;
6985
6986 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
6987 __igb_notify_dca);
6988
6989 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
6990 }
6991 #endif /* CONFIG_IGB_DCA */
6992
6993 #ifdef CONFIG_PCI_IOV
igb_vf_configure(struct igb_adapter * adapter,int vf)6994 static int igb_vf_configure(struct igb_adapter *adapter, int vf)
6995 {
6996 unsigned char mac_addr[ETH_ALEN];
6997
6998 eth_zero_addr(mac_addr);
6999 igb_set_vf_mac(adapter, vf, mac_addr);
7000
7001 /* By default spoof check is enabled for all VFs */
7002 adapter->vf_data[vf].spoofchk_enabled = true;
7003
7004 /* By default VFs are not trusted */
7005 adapter->vf_data[vf].trusted = false;
7006
7007 return 0;
7008 }
7009
7010 #endif
igb_ping_all_vfs(struct igb_adapter * adapter)7011 static void igb_ping_all_vfs(struct igb_adapter *adapter)
7012 {
7013 struct e1000_hw *hw = &adapter->hw;
7014 u32 ping;
7015 int i;
7016
7017 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
7018 ping = E1000_PF_CONTROL_MSG;
7019 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
7020 ping |= E1000_VT_MSGTYPE_CTS;
7021 igb_write_mbx(hw, &ping, 1, i);
7022 }
7023 }
7024
igb_set_vf_promisc(struct igb_adapter * adapter,u32 * msgbuf,u32 vf)7025 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
7026 {
7027 struct e1000_hw *hw = &adapter->hw;
7028 u32 vmolr = rd32(E1000_VMOLR(vf));
7029 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7030
7031 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
7032 IGB_VF_FLAG_MULTI_PROMISC);
7033 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
7034
7035 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
7036 vmolr |= E1000_VMOLR_MPME;
7037 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7038 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
7039 } else {
7040 /* if we have hashes and we are clearing a multicast promisc
7041 * flag we need to write the hashes to the MTA as this step
7042 * was previously skipped
7043 */
7044 if (vf_data->num_vf_mc_hashes > 30) {
7045 vmolr |= E1000_VMOLR_MPME;
7046 } else if (vf_data->num_vf_mc_hashes) {
7047 int j;
7048
7049 vmolr |= E1000_VMOLR_ROMPE;
7050 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
7051 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
7052 }
7053 }
7054
7055 wr32(E1000_VMOLR(vf), vmolr);
7056
7057 /* there are flags left unprocessed, likely not supported */
7058 if (*msgbuf & E1000_VT_MSGINFO_MASK)
7059 return -EINVAL;
7060
7061 return 0;
7062 }
7063
igb_set_vf_multicasts(struct igb_adapter * adapter,u32 * msgbuf,u32 vf)7064 static int igb_set_vf_multicasts(struct igb_adapter *adapter,
7065 u32 *msgbuf, u32 vf)
7066 {
7067 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
7068 u16 *hash_list = (u16 *)&msgbuf[1];
7069 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7070 int i;
7071
7072 /* salt away the number of multicast addresses assigned
7073 * to this VF for later use to restore when the PF multi cast
7074 * list changes
7075 */
7076 vf_data->num_vf_mc_hashes = n;
7077
7078 /* only up to 30 hash values supported */
7079 if (n > 30)
7080 n = 30;
7081
7082 /* store the hashes for later use */
7083 for (i = 0; i < n; i++)
7084 vf_data->vf_mc_hashes[i] = hash_list[i];
7085
7086 /* Flush and reset the mta with the new values */
7087 igb_set_rx_mode(adapter->netdev);
7088
7089 return 0;
7090 }
7091
igb_restore_vf_multicasts(struct igb_adapter * adapter)7092 static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
7093 {
7094 struct e1000_hw *hw = &adapter->hw;
7095 struct vf_data_storage *vf_data;
7096 int i, j;
7097
7098 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7099 u32 vmolr = rd32(E1000_VMOLR(i));
7100
7101 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
7102
7103 vf_data = &adapter->vf_data[i];
7104
7105 if ((vf_data->num_vf_mc_hashes > 30) ||
7106 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
7107 vmolr |= E1000_VMOLR_MPME;
7108 } else if (vf_data->num_vf_mc_hashes) {
7109 vmolr |= E1000_VMOLR_ROMPE;
7110 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
7111 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
7112 }
7113 wr32(E1000_VMOLR(i), vmolr);
7114 }
7115 }
7116
igb_clear_vf_vfta(struct igb_adapter * adapter,u32 vf)7117 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
7118 {
7119 struct e1000_hw *hw = &adapter->hw;
7120 u32 pool_mask, vlvf_mask, i;
7121
7122 /* create mask for VF and other pools */
7123 pool_mask = E1000_VLVF_POOLSEL_MASK;
7124 vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf);
7125
7126 /* drop PF from pool bits */
7127 pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT +
7128 adapter->vfs_allocated_count);
7129
7130 /* Find the vlan filter for this id */
7131 for (i = E1000_VLVF_ARRAY_SIZE; i--;) {
7132 u32 vlvf = rd32(E1000_VLVF(i));
7133 u32 vfta_mask, vid, vfta;
7134
7135 /* remove the vf from the pool */
7136 if (!(vlvf & vlvf_mask))
7137 continue;
7138
7139 /* clear out bit from VLVF */
7140 vlvf ^= vlvf_mask;
7141
7142 /* if other pools are present, just remove ourselves */
7143 if (vlvf & pool_mask)
7144 goto update_vlvfb;
7145
7146 /* if PF is present, leave VFTA */
7147 if (vlvf & E1000_VLVF_POOLSEL_MASK)
7148 goto update_vlvf;
7149
7150 vid = vlvf & E1000_VLVF_VLANID_MASK;
7151 vfta_mask = BIT(vid % 32);
7152
7153 /* clear bit from VFTA */
7154 vfta = adapter->shadow_vfta[vid / 32];
7155 if (vfta & vfta_mask)
7156 hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask);
7157 update_vlvf:
7158 /* clear pool selection enable */
7159 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
7160 vlvf &= E1000_VLVF_POOLSEL_MASK;
7161 else
7162 vlvf = 0;
7163 update_vlvfb:
7164 /* clear pool bits */
7165 wr32(E1000_VLVF(i), vlvf);
7166 }
7167 }
7168
igb_find_vlvf_entry(struct e1000_hw * hw,u32 vlan)7169 static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan)
7170 {
7171 u32 vlvf;
7172 int idx;
7173
7174 /* short cut the special case */
7175 if (vlan == 0)
7176 return 0;
7177
7178 /* Search for the VLAN id in the VLVF entries */
7179 for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) {
7180 vlvf = rd32(E1000_VLVF(idx));
7181 if ((vlvf & VLAN_VID_MASK) == vlan)
7182 break;
7183 }
7184
7185 return idx;
7186 }
7187
igb_update_pf_vlvf(struct igb_adapter * adapter,u32 vid)7188 static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid)
7189 {
7190 struct e1000_hw *hw = &adapter->hw;
7191 u32 bits, pf_id;
7192 int idx;
7193
7194 idx = igb_find_vlvf_entry(hw, vid);
7195 if (!idx)
7196 return;
7197
7198 /* See if any other pools are set for this VLAN filter
7199 * entry other than the PF.
7200 */
7201 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
7202 bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK;
7203 bits &= rd32(E1000_VLVF(idx));
7204
7205 /* Disable the filter so this falls into the default pool. */
7206 if (!bits) {
7207 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
7208 wr32(E1000_VLVF(idx), BIT(pf_id));
7209 else
7210 wr32(E1000_VLVF(idx), 0);
7211 }
7212 }
7213
igb_set_vf_vlan(struct igb_adapter * adapter,u32 vid,bool add,u32 vf)7214 static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid,
7215 bool add, u32 vf)
7216 {
7217 int pf_id = adapter->vfs_allocated_count;
7218 struct e1000_hw *hw = &adapter->hw;
7219 int err;
7220
7221 /* If VLAN overlaps with one the PF is currently monitoring make
7222 * sure that we are able to allocate a VLVF entry. This may be
7223 * redundant but it guarantees PF will maintain visibility to
7224 * the VLAN.
7225 */
7226 if (add && test_bit(vid, adapter->active_vlans)) {
7227 err = igb_vfta_set(hw, vid, pf_id, true, false);
7228 if (err)
7229 return err;
7230 }
7231
7232 err = igb_vfta_set(hw, vid, vf, add, false);
7233
7234 if (add && !err)
7235 return err;
7236
7237 /* If we failed to add the VF VLAN or we are removing the VF VLAN
7238 * we may need to drop the PF pool bit in order to allow us to free
7239 * up the VLVF resources.
7240 */
7241 if (test_bit(vid, adapter->active_vlans) ||
7242 (adapter->flags & IGB_FLAG_VLAN_PROMISC))
7243 igb_update_pf_vlvf(adapter, vid);
7244
7245 return err;
7246 }
7247
igb_set_vmvir(struct igb_adapter * adapter,u32 vid,u32 vf)7248 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
7249 {
7250 struct e1000_hw *hw = &adapter->hw;
7251
7252 if (vid)
7253 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
7254 else
7255 wr32(E1000_VMVIR(vf), 0);
7256 }
7257
igb_enable_port_vlan(struct igb_adapter * adapter,int vf,u16 vlan,u8 qos)7258 static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf,
7259 u16 vlan, u8 qos)
7260 {
7261 int err;
7262
7263 err = igb_set_vf_vlan(adapter, vlan, true, vf);
7264 if (err)
7265 return err;
7266
7267 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
7268 igb_set_vmolr(adapter, vf, !vlan);
7269
7270 /* revoke access to previous VLAN */
7271 if (vlan != adapter->vf_data[vf].pf_vlan)
7272 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan,
7273 false, vf);
7274
7275 adapter->vf_data[vf].pf_vlan = vlan;
7276 adapter->vf_data[vf].pf_qos = qos;
7277 igb_set_vf_vlan_strip(adapter, vf, true);
7278 dev_info(&adapter->pdev->dev,
7279 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
7280 if (test_bit(__IGB_DOWN, &adapter->state)) {
7281 dev_warn(&adapter->pdev->dev,
7282 "The VF VLAN has been set, but the PF device is not up.\n");
7283 dev_warn(&adapter->pdev->dev,
7284 "Bring the PF device up before attempting to use the VF device.\n");
7285 }
7286
7287 return err;
7288 }
7289
igb_disable_port_vlan(struct igb_adapter * adapter,int vf)7290 static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf)
7291 {
7292 /* Restore tagless access via VLAN 0 */
7293 igb_set_vf_vlan(adapter, 0, true, vf);
7294
7295 igb_set_vmvir(adapter, 0, vf);
7296 igb_set_vmolr(adapter, vf, true);
7297
7298 /* Remove any PF assigned VLAN */
7299 if (adapter->vf_data[vf].pf_vlan)
7300 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan,
7301 false, vf);
7302
7303 adapter->vf_data[vf].pf_vlan = 0;
7304 adapter->vf_data[vf].pf_qos = 0;
7305 igb_set_vf_vlan_strip(adapter, vf, false);
7306
7307 return 0;
7308 }
7309
igb_ndo_set_vf_vlan(struct net_device * netdev,int vf,u16 vlan,u8 qos,__be16 vlan_proto)7310 static int igb_ndo_set_vf_vlan(struct net_device *netdev, int vf,
7311 u16 vlan, u8 qos, __be16 vlan_proto)
7312 {
7313 struct igb_adapter *adapter = netdev_priv(netdev);
7314
7315 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
7316 return -EINVAL;
7317
7318 if (vlan_proto != htons(ETH_P_8021Q))
7319 return -EPROTONOSUPPORT;
7320
7321 return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) :
7322 igb_disable_port_vlan(adapter, vf);
7323 }
7324
igb_set_vf_vlan_msg(struct igb_adapter * adapter,u32 * msgbuf,u32 vf)7325 static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
7326 {
7327 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
7328 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
7329 int ret;
7330
7331 if (adapter->vf_data[vf].pf_vlan)
7332 return -1;
7333
7334 /* VLAN 0 is a special case, don't allow it to be removed */
7335 if (!vid && !add)
7336 return 0;
7337
7338 ret = igb_set_vf_vlan(adapter, vid, !!add, vf);
7339 if (!ret)
7340 igb_set_vf_vlan_strip(adapter, vf, !!vid);
7341 return ret;
7342 }
7343
igb_vf_reset(struct igb_adapter * adapter,u32 vf)7344 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
7345 {
7346 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7347
7348 /* clear flags - except flag that indicates PF has set the MAC */
7349 vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC;
7350 vf_data->last_nack = jiffies;
7351
7352 /* reset vlans for device */
7353 igb_clear_vf_vfta(adapter, vf);
7354 igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf);
7355 igb_set_vmvir(adapter, vf_data->pf_vlan |
7356 (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf);
7357 igb_set_vmolr(adapter, vf, !vf_data->pf_vlan);
7358 igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan));
7359
7360 /* reset multicast table array for vf */
7361 adapter->vf_data[vf].num_vf_mc_hashes = 0;
7362
7363 /* Flush and reset the mta with the new values */
7364 igb_set_rx_mode(adapter->netdev);
7365 }
7366
igb_vf_reset_event(struct igb_adapter * adapter,u32 vf)7367 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
7368 {
7369 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
7370
7371 /* clear mac address as we were hotplug removed/added */
7372 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
7373 eth_zero_addr(vf_mac);
7374
7375 /* process remaining reset events */
7376 igb_vf_reset(adapter, vf);
7377 }
7378
igb_vf_reset_msg(struct igb_adapter * adapter,u32 vf)7379 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
7380 {
7381 struct e1000_hw *hw = &adapter->hw;
7382 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
7383 u32 reg, msgbuf[3];
7384 u8 *addr = (u8 *)(&msgbuf[1]);
7385
7386 /* process all the same items cleared in a function level reset */
7387 igb_vf_reset(adapter, vf);
7388
7389 /* set vf mac address */
7390 igb_set_vf_mac(adapter, vf, vf_mac);
7391
7392 /* enable transmit and receive for vf */
7393 reg = rd32(E1000_VFTE);
7394 wr32(E1000_VFTE, reg | BIT(vf));
7395 reg = rd32(E1000_VFRE);
7396 wr32(E1000_VFRE, reg | BIT(vf));
7397
7398 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
7399
7400 /* reply to reset with ack and vf mac address */
7401 if (!is_zero_ether_addr(vf_mac)) {
7402 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
7403 memcpy(addr, vf_mac, ETH_ALEN);
7404 } else {
7405 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK;
7406 }
7407 igb_write_mbx(hw, msgbuf, 3, vf);
7408 }
7409
igb_flush_mac_table(struct igb_adapter * adapter)7410 static void igb_flush_mac_table(struct igb_adapter *adapter)
7411 {
7412 struct e1000_hw *hw = &adapter->hw;
7413 int i;
7414
7415 for (i = 0; i < hw->mac.rar_entry_count; i++) {
7416 adapter->mac_table[i].state &= ~IGB_MAC_STATE_IN_USE;
7417 eth_zero_addr(adapter->mac_table[i].addr);
7418 adapter->mac_table[i].queue = 0;
7419 igb_rar_set_index(adapter, i);
7420 }
7421 }
7422
igb_available_rars(struct igb_adapter * adapter,u8 queue)7423 static int igb_available_rars(struct igb_adapter *adapter, u8 queue)
7424 {
7425 struct e1000_hw *hw = &adapter->hw;
7426 /* do not count rar entries reserved for VFs MAC addresses */
7427 int rar_entries = hw->mac.rar_entry_count -
7428 adapter->vfs_allocated_count;
7429 int i, count = 0;
7430
7431 for (i = 0; i < rar_entries; i++) {
7432 /* do not count default entries */
7433 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT)
7434 continue;
7435
7436 /* do not count "in use" entries for different queues */
7437 if ((adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE) &&
7438 (adapter->mac_table[i].queue != queue))
7439 continue;
7440
7441 count++;
7442 }
7443
7444 return count;
7445 }
7446
7447 /* Set default MAC address for the PF in the first RAR entry */
igb_set_default_mac_filter(struct igb_adapter * adapter)7448 static void igb_set_default_mac_filter(struct igb_adapter *adapter)
7449 {
7450 struct igb_mac_addr *mac_table = &adapter->mac_table[0];
7451
7452 ether_addr_copy(mac_table->addr, adapter->hw.mac.addr);
7453 mac_table->queue = adapter->vfs_allocated_count;
7454 mac_table->state = IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE;
7455
7456 igb_rar_set_index(adapter, 0);
7457 }
7458
7459 /* If the filter to be added and an already existing filter express
7460 * the same address and address type, it should be possible to only
7461 * override the other configurations, for example the queue to steer
7462 * traffic.
7463 */
igb_mac_entry_can_be_used(const struct igb_mac_addr * entry,const u8 * addr,const u8 flags)7464 static bool igb_mac_entry_can_be_used(const struct igb_mac_addr *entry,
7465 const u8 *addr, const u8 flags)
7466 {
7467 if (!(entry->state & IGB_MAC_STATE_IN_USE))
7468 return true;
7469
7470 if ((entry->state & IGB_MAC_STATE_SRC_ADDR) !=
7471 (flags & IGB_MAC_STATE_SRC_ADDR))
7472 return false;
7473
7474 if (!ether_addr_equal(addr, entry->addr))
7475 return false;
7476
7477 return true;
7478 }
7479
7480 /* Add a MAC filter for 'addr' directing matching traffic to 'queue',
7481 * 'flags' is used to indicate what kind of match is made, match is by
7482 * default for the destination address, if matching by source address
7483 * is desired the flag IGB_MAC_STATE_SRC_ADDR can be used.
7484 */
igb_add_mac_filter_flags(struct igb_adapter * adapter,const u8 * addr,const u8 queue,const u8 flags)7485 static int igb_add_mac_filter_flags(struct igb_adapter *adapter,
7486 const u8 *addr, const u8 queue,
7487 const u8 flags)
7488 {
7489 struct e1000_hw *hw = &adapter->hw;
7490 int rar_entries = hw->mac.rar_entry_count -
7491 adapter->vfs_allocated_count;
7492 int i;
7493
7494 if (is_zero_ether_addr(addr))
7495 return -EINVAL;
7496
7497 /* Search for the first empty entry in the MAC table.
7498 * Do not touch entries at the end of the table reserved for the VF MAC
7499 * addresses.
7500 */
7501 for (i = 0; i < rar_entries; i++) {
7502 if (!igb_mac_entry_can_be_used(&adapter->mac_table[i],
7503 addr, flags))
7504 continue;
7505
7506 ether_addr_copy(adapter->mac_table[i].addr, addr);
7507 adapter->mac_table[i].queue = queue;
7508 adapter->mac_table[i].state |= IGB_MAC_STATE_IN_USE | flags;
7509
7510 igb_rar_set_index(adapter, i);
7511 return i;
7512 }
7513
7514 return -ENOSPC;
7515 }
7516
igb_add_mac_filter(struct igb_adapter * adapter,const u8 * addr,const u8 queue)7517 static int igb_add_mac_filter(struct igb_adapter *adapter, const u8 *addr,
7518 const u8 queue)
7519 {
7520 return igb_add_mac_filter_flags(adapter, addr, queue, 0);
7521 }
7522
7523 /* Remove a MAC filter for 'addr' directing matching traffic to
7524 * 'queue', 'flags' is used to indicate what kind of match need to be
7525 * removed, match is by default for the destination address, if
7526 * matching by source address is to be removed the flag
7527 * IGB_MAC_STATE_SRC_ADDR can be used.
7528 */
igb_del_mac_filter_flags(struct igb_adapter * adapter,const u8 * addr,const u8 queue,const u8 flags)7529 static int igb_del_mac_filter_flags(struct igb_adapter *adapter,
7530 const u8 *addr, const u8 queue,
7531 const u8 flags)
7532 {
7533 struct e1000_hw *hw = &adapter->hw;
7534 int rar_entries = hw->mac.rar_entry_count -
7535 adapter->vfs_allocated_count;
7536 int i;
7537
7538 if (is_zero_ether_addr(addr))
7539 return -EINVAL;
7540
7541 /* Search for matching entry in the MAC table based on given address
7542 * and queue. Do not touch entries at the end of the table reserved
7543 * for the VF MAC addresses.
7544 */
7545 for (i = 0; i < rar_entries; i++) {
7546 if (!(adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE))
7547 continue;
7548 if ((adapter->mac_table[i].state & flags) != flags)
7549 continue;
7550 if (adapter->mac_table[i].queue != queue)
7551 continue;
7552 if (!ether_addr_equal(adapter->mac_table[i].addr, addr))
7553 continue;
7554
7555 /* When a filter for the default address is "deleted",
7556 * we return it to its initial configuration
7557 */
7558 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) {
7559 adapter->mac_table[i].state =
7560 IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE;
7561 adapter->mac_table[i].queue =
7562 adapter->vfs_allocated_count;
7563 } else {
7564 adapter->mac_table[i].state = 0;
7565 adapter->mac_table[i].queue = 0;
7566 eth_zero_addr(adapter->mac_table[i].addr);
7567 }
7568
7569 igb_rar_set_index(adapter, i);
7570 return 0;
7571 }
7572
7573 return -ENOENT;
7574 }
7575
igb_del_mac_filter(struct igb_adapter * adapter,const u8 * addr,const u8 queue)7576 static int igb_del_mac_filter(struct igb_adapter *adapter, const u8 *addr,
7577 const u8 queue)
7578 {
7579 return igb_del_mac_filter_flags(adapter, addr, queue, 0);
7580 }
7581
igb_add_mac_steering_filter(struct igb_adapter * adapter,const u8 * addr,u8 queue,u8 flags)7582 int igb_add_mac_steering_filter(struct igb_adapter *adapter,
7583 const u8 *addr, u8 queue, u8 flags)
7584 {
7585 struct e1000_hw *hw = &adapter->hw;
7586
7587 /* In theory, this should be supported on 82575 as well, but
7588 * that part wasn't easily accessible during development.
7589 */
7590 if (hw->mac.type != e1000_i210)
7591 return -EOPNOTSUPP;
7592
7593 return igb_add_mac_filter_flags(adapter, addr, queue,
7594 IGB_MAC_STATE_QUEUE_STEERING | flags);
7595 }
7596
igb_del_mac_steering_filter(struct igb_adapter * adapter,const u8 * addr,u8 queue,u8 flags)7597 int igb_del_mac_steering_filter(struct igb_adapter *adapter,
7598 const u8 *addr, u8 queue, u8 flags)
7599 {
7600 return igb_del_mac_filter_flags(adapter, addr, queue,
7601 IGB_MAC_STATE_QUEUE_STEERING | flags);
7602 }
7603
igb_uc_sync(struct net_device * netdev,const unsigned char * addr)7604 static int igb_uc_sync(struct net_device *netdev, const unsigned char *addr)
7605 {
7606 struct igb_adapter *adapter = netdev_priv(netdev);
7607 int ret;
7608
7609 ret = igb_add_mac_filter(adapter, addr, adapter->vfs_allocated_count);
7610
7611 return min_t(int, ret, 0);
7612 }
7613
igb_uc_unsync(struct net_device * netdev,const unsigned char * addr)7614 static int igb_uc_unsync(struct net_device *netdev, const unsigned char *addr)
7615 {
7616 struct igb_adapter *adapter = netdev_priv(netdev);
7617
7618 igb_del_mac_filter(adapter, addr, adapter->vfs_allocated_count);
7619
7620 return 0;
7621 }
7622
igb_set_vf_mac_filter(struct igb_adapter * adapter,const int vf,const u32 info,const u8 * addr)7623 static int igb_set_vf_mac_filter(struct igb_adapter *adapter, const int vf,
7624 const u32 info, const u8 *addr)
7625 {
7626 struct pci_dev *pdev = adapter->pdev;
7627 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7628 struct list_head *pos;
7629 struct vf_mac_filter *entry = NULL;
7630 int ret = 0;
7631
7632 switch (info) {
7633 case E1000_VF_MAC_FILTER_CLR:
7634 /* remove all unicast MAC filters related to the current VF */
7635 list_for_each(pos, &adapter->vf_macs.l) {
7636 entry = list_entry(pos, struct vf_mac_filter, l);
7637 if (entry->vf == vf) {
7638 entry->vf = -1;
7639 entry->free = true;
7640 igb_del_mac_filter(adapter, entry->vf_mac, vf);
7641 }
7642 }
7643 break;
7644 case E1000_VF_MAC_FILTER_ADD:
7645 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) &&
7646 !vf_data->trusted) {
7647 dev_warn(&pdev->dev,
7648 "VF %d requested MAC filter but is administratively denied\n",
7649 vf);
7650 return -EINVAL;
7651 }
7652 if (!is_valid_ether_addr(addr)) {
7653 dev_warn(&pdev->dev,
7654 "VF %d attempted to set invalid MAC filter\n",
7655 vf);
7656 return -EINVAL;
7657 }
7658
7659 /* try to find empty slot in the list */
7660 list_for_each(pos, &adapter->vf_macs.l) {
7661 entry = list_entry(pos, struct vf_mac_filter, l);
7662 if (entry->free)
7663 break;
7664 }
7665
7666 if (entry && entry->free) {
7667 entry->free = false;
7668 entry->vf = vf;
7669 ether_addr_copy(entry->vf_mac, addr);
7670
7671 ret = igb_add_mac_filter(adapter, addr, vf);
7672 ret = min_t(int, ret, 0);
7673 } else {
7674 ret = -ENOSPC;
7675 }
7676
7677 if (ret == -ENOSPC)
7678 dev_warn(&pdev->dev,
7679 "VF %d has requested MAC filter but there is no space for it\n",
7680 vf);
7681 break;
7682 default:
7683 ret = -EINVAL;
7684 break;
7685 }
7686
7687 return ret;
7688 }
7689
igb_set_vf_mac_addr(struct igb_adapter * adapter,u32 * msg,int vf)7690 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
7691 {
7692 struct pci_dev *pdev = adapter->pdev;
7693 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7694 u32 info = msg[0] & E1000_VT_MSGINFO_MASK;
7695
7696 /* The VF MAC Address is stored in a packed array of bytes
7697 * starting at the second 32 bit word of the msg array
7698 */
7699 unsigned char *addr = (unsigned char *)&msg[1];
7700 int ret = 0;
7701
7702 if (!info) {
7703 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) &&
7704 !vf_data->trusted) {
7705 dev_warn(&pdev->dev,
7706 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
7707 vf);
7708 return -EINVAL;
7709 }
7710
7711 if (!is_valid_ether_addr(addr)) {
7712 dev_warn(&pdev->dev,
7713 "VF %d attempted to set invalid MAC\n",
7714 vf);
7715 return -EINVAL;
7716 }
7717
7718 ret = igb_set_vf_mac(adapter, vf, addr);
7719 } else {
7720 ret = igb_set_vf_mac_filter(adapter, vf, info, addr);
7721 }
7722
7723 return ret;
7724 }
7725
igb_rcv_ack_from_vf(struct igb_adapter * adapter,u32 vf)7726 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
7727 {
7728 struct e1000_hw *hw = &adapter->hw;
7729 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7730 u32 msg = E1000_VT_MSGTYPE_NACK;
7731
7732 /* if device isn't clear to send it shouldn't be reading either */
7733 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
7734 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
7735 igb_write_mbx(hw, &msg, 1, vf);
7736 vf_data->last_nack = jiffies;
7737 }
7738 }
7739
igb_rcv_msg_from_vf(struct igb_adapter * adapter,u32 vf)7740 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
7741 {
7742 struct pci_dev *pdev = adapter->pdev;
7743 u32 msgbuf[E1000_VFMAILBOX_SIZE];
7744 struct e1000_hw *hw = &adapter->hw;
7745 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7746 s32 retval;
7747
7748 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf, false);
7749
7750 if (retval) {
7751 /* if receive failed revoke VF CTS stats and restart init */
7752 dev_err(&pdev->dev, "Error receiving message from VF\n");
7753 vf_data->flags &= ~IGB_VF_FLAG_CTS;
7754 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
7755 goto unlock;
7756 goto out;
7757 }
7758
7759 /* this is a message we already processed, do nothing */
7760 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
7761 goto unlock;
7762
7763 /* until the vf completes a reset it should not be
7764 * allowed to start any configuration.
7765 */
7766 if (msgbuf[0] == E1000_VF_RESET) {
7767 /* unlocks mailbox */
7768 igb_vf_reset_msg(adapter, vf);
7769 return;
7770 }
7771
7772 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
7773 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
7774 goto unlock;
7775 retval = -1;
7776 goto out;
7777 }
7778
7779 switch ((msgbuf[0] & 0xFFFF)) {
7780 case E1000_VF_SET_MAC_ADDR:
7781 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
7782 break;
7783 case E1000_VF_SET_PROMISC:
7784 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
7785 break;
7786 case E1000_VF_SET_MULTICAST:
7787 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
7788 break;
7789 case E1000_VF_SET_LPE:
7790 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
7791 break;
7792 case E1000_VF_SET_VLAN:
7793 retval = -1;
7794 if (vf_data->pf_vlan)
7795 dev_warn(&pdev->dev,
7796 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
7797 vf);
7798 else
7799 retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf);
7800 break;
7801 default:
7802 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
7803 retval = -1;
7804 break;
7805 }
7806
7807 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
7808 out:
7809 /* notify the VF of the results of what it sent us */
7810 if (retval)
7811 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
7812 else
7813 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
7814
7815 /* unlocks mailbox */
7816 igb_write_mbx(hw, msgbuf, 1, vf);
7817 return;
7818
7819 unlock:
7820 igb_unlock_mbx(hw, vf);
7821 }
7822
igb_msg_task(struct igb_adapter * adapter)7823 static void igb_msg_task(struct igb_adapter *adapter)
7824 {
7825 struct e1000_hw *hw = &adapter->hw;
7826 u32 vf;
7827
7828 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
7829 /* process any reset requests */
7830 if (!igb_check_for_rst(hw, vf))
7831 igb_vf_reset_event(adapter, vf);
7832
7833 /* process any messages pending */
7834 if (!igb_check_for_msg(hw, vf))
7835 igb_rcv_msg_from_vf(adapter, vf);
7836
7837 /* process any acks */
7838 if (!igb_check_for_ack(hw, vf))
7839 igb_rcv_ack_from_vf(adapter, vf);
7840 }
7841 }
7842
7843 /**
7844 * igb_set_uta - Set unicast filter table address
7845 * @adapter: board private structure
7846 * @set: boolean indicating if we are setting or clearing bits
7847 *
7848 * The unicast table address is a register array of 32-bit registers.
7849 * The table is meant to be used in a way similar to how the MTA is used
7850 * however due to certain limitations in the hardware it is necessary to
7851 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
7852 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
7853 **/
igb_set_uta(struct igb_adapter * adapter,bool set)7854 static void igb_set_uta(struct igb_adapter *adapter, bool set)
7855 {
7856 struct e1000_hw *hw = &adapter->hw;
7857 u32 uta = set ? ~0 : 0;
7858 int i;
7859
7860 /* we only need to do this if VMDq is enabled */
7861 if (!adapter->vfs_allocated_count)
7862 return;
7863
7864 for (i = hw->mac.uta_reg_count; i--;)
7865 array_wr32(E1000_UTA, i, uta);
7866 }
7867
7868 /**
7869 * igb_intr_msi - Interrupt Handler
7870 * @irq: interrupt number
7871 * @data: pointer to a network interface device structure
7872 **/
igb_intr_msi(int irq,void * data)7873 static irqreturn_t igb_intr_msi(int irq, void *data)
7874 {
7875 struct igb_adapter *adapter = data;
7876 struct igb_q_vector *q_vector = adapter->q_vector[0];
7877 struct e1000_hw *hw = &adapter->hw;
7878 /* read ICR disables interrupts using IAM */
7879 u32 icr = rd32(E1000_ICR);
7880
7881 igb_write_itr(q_vector);
7882
7883 if (icr & E1000_ICR_DRSTA)
7884 schedule_work(&adapter->reset_task);
7885
7886 if (icr & E1000_ICR_DOUTSYNC) {
7887 /* HW is reporting DMA is out of sync */
7888 adapter->stats.doosync++;
7889 }
7890
7891 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
7892 hw->mac.get_link_status = 1;
7893 if (!test_bit(__IGB_DOWN, &adapter->state))
7894 mod_timer(&adapter->watchdog_timer, jiffies + 1);
7895 }
7896
7897 if (icr & E1000_ICR_TS)
7898 igb_tsync_interrupt(adapter);
7899
7900 napi_schedule(&q_vector->napi);
7901
7902 return IRQ_HANDLED;
7903 }
7904
7905 /**
7906 * igb_intr - Legacy Interrupt Handler
7907 * @irq: interrupt number
7908 * @data: pointer to a network interface device structure
7909 **/
igb_intr(int irq,void * data)7910 static irqreturn_t igb_intr(int irq, void *data)
7911 {
7912 struct igb_adapter *adapter = data;
7913 struct igb_q_vector *q_vector = adapter->q_vector[0];
7914 struct e1000_hw *hw = &adapter->hw;
7915 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
7916 * need for the IMC write
7917 */
7918 u32 icr = rd32(E1000_ICR);
7919
7920 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
7921 * not set, then the adapter didn't send an interrupt
7922 */
7923 if (!(icr & E1000_ICR_INT_ASSERTED))
7924 return IRQ_NONE;
7925
7926 igb_write_itr(q_vector);
7927
7928 if (icr & E1000_ICR_DRSTA)
7929 schedule_work(&adapter->reset_task);
7930
7931 if (icr & E1000_ICR_DOUTSYNC) {
7932 /* HW is reporting DMA is out of sync */
7933 adapter->stats.doosync++;
7934 }
7935
7936 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
7937 hw->mac.get_link_status = 1;
7938 /* guard against interrupt when we're going down */
7939 if (!test_bit(__IGB_DOWN, &adapter->state))
7940 mod_timer(&adapter->watchdog_timer, jiffies + 1);
7941 }
7942
7943 if (icr & E1000_ICR_TS)
7944 igb_tsync_interrupt(adapter);
7945
7946 napi_schedule(&q_vector->napi);
7947
7948 return IRQ_HANDLED;
7949 }
7950
igb_ring_irq_enable(struct igb_q_vector * q_vector)7951 static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
7952 {
7953 struct igb_adapter *adapter = q_vector->adapter;
7954 struct e1000_hw *hw = &adapter->hw;
7955
7956 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
7957 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
7958 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
7959 igb_set_itr(q_vector);
7960 else
7961 igb_update_ring_itr(q_vector);
7962 }
7963
7964 if (!test_bit(__IGB_DOWN, &adapter->state)) {
7965 if (adapter->flags & IGB_FLAG_HAS_MSIX)
7966 wr32(E1000_EIMS, q_vector->eims_value);
7967 else
7968 igb_irq_enable(adapter);
7969 }
7970 }
7971
7972 /**
7973 * igb_poll - NAPI Rx polling callback
7974 * @napi: napi polling structure
7975 * @budget: count of how many packets we should handle
7976 **/
igb_poll(struct napi_struct * napi,int budget)7977 static int igb_poll(struct napi_struct *napi, int budget)
7978 {
7979 struct igb_q_vector *q_vector = container_of(napi,
7980 struct igb_q_vector,
7981 napi);
7982 bool clean_complete = true;
7983 int work_done = 0;
7984
7985 #ifdef CONFIG_IGB_DCA
7986 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
7987 igb_update_dca(q_vector);
7988 #endif
7989 if (q_vector->tx.ring)
7990 clean_complete = igb_clean_tx_irq(q_vector, budget);
7991
7992 if (q_vector->rx.ring) {
7993 int cleaned = igb_clean_rx_irq(q_vector, budget);
7994
7995 work_done += cleaned;
7996 if (cleaned >= budget)
7997 clean_complete = false;
7998 }
7999
8000 /* If all work not completed, return budget and keep polling */
8001 if (!clean_complete)
8002 return budget;
8003
8004 /* Exit the polling mode, but don't re-enable interrupts if stack might
8005 * poll us due to busy-polling
8006 */
8007 if (likely(napi_complete_done(napi, work_done)))
8008 igb_ring_irq_enable(q_vector);
8009
8010 return min(work_done, budget - 1);
8011 }
8012
8013 /**
8014 * igb_clean_tx_irq - Reclaim resources after transmit completes
8015 * @q_vector: pointer to q_vector containing needed info
8016 * @napi_budget: Used to determine if we are in netpoll
8017 *
8018 * returns true if ring is completely cleaned
8019 **/
igb_clean_tx_irq(struct igb_q_vector * q_vector,int napi_budget)8020 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector, int napi_budget)
8021 {
8022 struct igb_adapter *adapter = q_vector->adapter;
8023 struct igb_ring *tx_ring = q_vector->tx.ring;
8024 struct igb_tx_buffer *tx_buffer;
8025 union e1000_adv_tx_desc *tx_desc;
8026 unsigned int total_bytes = 0, total_packets = 0;
8027 unsigned int budget = q_vector->tx.work_limit;
8028 unsigned int i = tx_ring->next_to_clean;
8029
8030 if (test_bit(__IGB_DOWN, &adapter->state))
8031 return true;
8032
8033 tx_buffer = &tx_ring->tx_buffer_info[i];
8034 tx_desc = IGB_TX_DESC(tx_ring, i);
8035 i -= tx_ring->count;
8036
8037 do {
8038 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
8039
8040 /* if next_to_watch is not set then there is no work pending */
8041 if (!eop_desc)
8042 break;
8043
8044 /* prevent any other reads prior to eop_desc */
8045 smp_rmb();
8046
8047 /* if DD is not set pending work has not been completed */
8048 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
8049 break;
8050
8051 /* clear next_to_watch to prevent false hangs */
8052 tx_buffer->next_to_watch = NULL;
8053
8054 /* update the statistics for this packet */
8055 total_bytes += tx_buffer->bytecount;
8056 total_packets += tx_buffer->gso_segs;
8057
8058 /* free the skb */
8059 if (tx_buffer->type == IGB_TYPE_SKB)
8060 napi_consume_skb(tx_buffer->skb, napi_budget);
8061 else
8062 xdp_return_frame(tx_buffer->xdpf);
8063
8064 /* unmap skb header data */
8065 dma_unmap_single(tx_ring->dev,
8066 dma_unmap_addr(tx_buffer, dma),
8067 dma_unmap_len(tx_buffer, len),
8068 DMA_TO_DEVICE);
8069
8070 /* clear tx_buffer data */
8071 dma_unmap_len_set(tx_buffer, len, 0);
8072
8073 /* clear last DMA location and unmap remaining buffers */
8074 while (tx_desc != eop_desc) {
8075 tx_buffer++;
8076 tx_desc++;
8077 i++;
8078 if (unlikely(!i)) {
8079 i -= tx_ring->count;
8080 tx_buffer = tx_ring->tx_buffer_info;
8081 tx_desc = IGB_TX_DESC(tx_ring, 0);
8082 }
8083
8084 /* unmap any remaining paged data */
8085 if (dma_unmap_len(tx_buffer, len)) {
8086 dma_unmap_page(tx_ring->dev,
8087 dma_unmap_addr(tx_buffer, dma),
8088 dma_unmap_len(tx_buffer, len),
8089 DMA_TO_DEVICE);
8090 dma_unmap_len_set(tx_buffer, len, 0);
8091 }
8092 }
8093
8094 /* move us one more past the eop_desc for start of next pkt */
8095 tx_buffer++;
8096 tx_desc++;
8097 i++;
8098 if (unlikely(!i)) {
8099 i -= tx_ring->count;
8100 tx_buffer = tx_ring->tx_buffer_info;
8101 tx_desc = IGB_TX_DESC(tx_ring, 0);
8102 }
8103
8104 /* issue prefetch for next Tx descriptor */
8105 prefetch(tx_desc);
8106
8107 /* update budget accounting */
8108 budget--;
8109 } while (likely(budget));
8110
8111 netdev_tx_completed_queue(txring_txq(tx_ring),
8112 total_packets, total_bytes);
8113 i += tx_ring->count;
8114 tx_ring->next_to_clean = i;
8115 u64_stats_update_begin(&tx_ring->tx_syncp);
8116 tx_ring->tx_stats.bytes += total_bytes;
8117 tx_ring->tx_stats.packets += total_packets;
8118 u64_stats_update_end(&tx_ring->tx_syncp);
8119 q_vector->tx.total_bytes += total_bytes;
8120 q_vector->tx.total_packets += total_packets;
8121
8122 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
8123 struct e1000_hw *hw = &adapter->hw;
8124
8125 /* Detect a transmit hang in hardware, this serializes the
8126 * check with the clearing of time_stamp and movement of i
8127 */
8128 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
8129 if (tx_buffer->next_to_watch &&
8130 time_after(jiffies, tx_buffer->time_stamp +
8131 (adapter->tx_timeout_factor * HZ)) &&
8132 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
8133
8134 /* detected Tx unit hang */
8135 dev_err(tx_ring->dev,
8136 "Detected Tx Unit Hang\n"
8137 " Tx Queue <%d>\n"
8138 " TDH <%x>\n"
8139 " TDT <%x>\n"
8140 " next_to_use <%x>\n"
8141 " next_to_clean <%x>\n"
8142 "buffer_info[next_to_clean]\n"
8143 " time_stamp <%lx>\n"
8144 " next_to_watch <%p>\n"
8145 " jiffies <%lx>\n"
8146 " desc.status <%x>\n",
8147 tx_ring->queue_index,
8148 rd32(E1000_TDH(tx_ring->reg_idx)),
8149 readl(tx_ring->tail),
8150 tx_ring->next_to_use,
8151 tx_ring->next_to_clean,
8152 tx_buffer->time_stamp,
8153 tx_buffer->next_to_watch,
8154 jiffies,
8155 tx_buffer->next_to_watch->wb.status);
8156 netif_stop_subqueue(tx_ring->netdev,
8157 tx_ring->queue_index);
8158
8159 /* we are about to reset, no point in enabling stuff */
8160 return true;
8161 }
8162 }
8163
8164 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
8165 if (unlikely(total_packets &&
8166 netif_carrier_ok(tx_ring->netdev) &&
8167 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
8168 /* Make sure that anybody stopping the queue after this
8169 * sees the new next_to_clean.
8170 */
8171 smp_mb();
8172 if (__netif_subqueue_stopped(tx_ring->netdev,
8173 tx_ring->queue_index) &&
8174 !(test_bit(__IGB_DOWN, &adapter->state))) {
8175 netif_wake_subqueue(tx_ring->netdev,
8176 tx_ring->queue_index);
8177
8178 u64_stats_update_begin(&tx_ring->tx_syncp);
8179 tx_ring->tx_stats.restart_queue++;
8180 u64_stats_update_end(&tx_ring->tx_syncp);
8181 }
8182 }
8183
8184 return !!budget;
8185 }
8186
8187 /**
8188 * igb_reuse_rx_page - page flip buffer and store it back on the ring
8189 * @rx_ring: rx descriptor ring to store buffers on
8190 * @old_buff: donor buffer to have page reused
8191 *
8192 * Synchronizes page for reuse by the adapter
8193 **/
igb_reuse_rx_page(struct igb_ring * rx_ring,struct igb_rx_buffer * old_buff)8194 static void igb_reuse_rx_page(struct igb_ring *rx_ring,
8195 struct igb_rx_buffer *old_buff)
8196 {
8197 struct igb_rx_buffer *new_buff;
8198 u16 nta = rx_ring->next_to_alloc;
8199
8200 new_buff = &rx_ring->rx_buffer_info[nta];
8201
8202 /* update, and store next to alloc */
8203 nta++;
8204 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
8205
8206 /* Transfer page from old buffer to new buffer.
8207 * Move each member individually to avoid possible store
8208 * forwarding stalls.
8209 */
8210 new_buff->dma = old_buff->dma;
8211 new_buff->page = old_buff->page;
8212 new_buff->page_offset = old_buff->page_offset;
8213 new_buff->pagecnt_bias = old_buff->pagecnt_bias;
8214 }
8215
igb_can_reuse_rx_page(struct igb_rx_buffer * rx_buffer,int rx_buf_pgcnt)8216 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
8217 int rx_buf_pgcnt)
8218 {
8219 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias;
8220 struct page *page = rx_buffer->page;
8221
8222 /* avoid re-using remote and pfmemalloc pages */
8223 if (!dev_page_is_reusable(page))
8224 return false;
8225
8226 #if (PAGE_SIZE < 8192)
8227 /* if we are only owner of page we can reuse it */
8228 if (unlikely((rx_buf_pgcnt - pagecnt_bias) > 1))
8229 return false;
8230 #else
8231 #define IGB_LAST_OFFSET \
8232 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGB_RXBUFFER_2048)
8233
8234 if (rx_buffer->page_offset > IGB_LAST_OFFSET)
8235 return false;
8236 #endif
8237
8238 /* If we have drained the page fragment pool we need to update
8239 * the pagecnt_bias and page count so that we fully restock the
8240 * number of references the driver holds.
8241 */
8242 if (unlikely(pagecnt_bias == 1)) {
8243 page_ref_add(page, USHRT_MAX - 1);
8244 rx_buffer->pagecnt_bias = USHRT_MAX;
8245 }
8246
8247 return true;
8248 }
8249
8250 /**
8251 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
8252 * @rx_ring: rx descriptor ring to transact packets on
8253 * @rx_buffer: buffer containing page to add
8254 * @skb: sk_buff to place the data into
8255 * @size: size of buffer to be added
8256 *
8257 * This function will add the data contained in rx_buffer->page to the skb.
8258 **/
igb_add_rx_frag(struct igb_ring * rx_ring,struct igb_rx_buffer * rx_buffer,struct sk_buff * skb,unsigned int size)8259 static void igb_add_rx_frag(struct igb_ring *rx_ring,
8260 struct igb_rx_buffer *rx_buffer,
8261 struct sk_buff *skb,
8262 unsigned int size)
8263 {
8264 #if (PAGE_SIZE < 8192)
8265 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2;
8266 #else
8267 unsigned int truesize = ring_uses_build_skb(rx_ring) ?
8268 SKB_DATA_ALIGN(IGB_SKB_PAD + size) :
8269 SKB_DATA_ALIGN(size);
8270 #endif
8271 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page,
8272 rx_buffer->page_offset, size, truesize);
8273 #if (PAGE_SIZE < 8192)
8274 rx_buffer->page_offset ^= truesize;
8275 #else
8276 rx_buffer->page_offset += truesize;
8277 #endif
8278 }
8279
igb_construct_skb(struct igb_ring * rx_ring,struct igb_rx_buffer * rx_buffer,struct xdp_buff * xdp,union e1000_adv_rx_desc * rx_desc)8280 static struct sk_buff *igb_construct_skb(struct igb_ring *rx_ring,
8281 struct igb_rx_buffer *rx_buffer,
8282 struct xdp_buff *xdp,
8283 union e1000_adv_rx_desc *rx_desc)
8284 {
8285 #if (PAGE_SIZE < 8192)
8286 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2;
8287 #else
8288 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end -
8289 xdp->data_hard_start);
8290 #endif
8291 unsigned int size = xdp->data_end - xdp->data;
8292 unsigned int headlen;
8293 struct sk_buff *skb;
8294
8295 /* prefetch first cache line of first page */
8296 net_prefetch(xdp->data);
8297
8298 /* allocate a skb to store the frags */
8299 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN);
8300 if (unlikely(!skb))
8301 return NULL;
8302
8303 if (unlikely(igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))) {
8304 if (!igb_ptp_rx_pktstamp(rx_ring->q_vector, xdp->data, skb)) {
8305 xdp->data += IGB_TS_HDR_LEN;
8306 size -= IGB_TS_HDR_LEN;
8307 }
8308 }
8309
8310 /* Determine available headroom for copy */
8311 headlen = size;
8312 if (headlen > IGB_RX_HDR_LEN)
8313 headlen = eth_get_headlen(skb->dev, xdp->data, IGB_RX_HDR_LEN);
8314
8315 /* align pull length to size of long to optimize memcpy performance */
8316 memcpy(__skb_put(skb, headlen), xdp->data, ALIGN(headlen, sizeof(long)));
8317
8318 /* update all of the pointers */
8319 size -= headlen;
8320 if (size) {
8321 skb_add_rx_frag(skb, 0, rx_buffer->page,
8322 (xdp->data + headlen) - page_address(rx_buffer->page),
8323 size, truesize);
8324 #if (PAGE_SIZE < 8192)
8325 rx_buffer->page_offset ^= truesize;
8326 #else
8327 rx_buffer->page_offset += truesize;
8328 #endif
8329 } else {
8330 rx_buffer->pagecnt_bias++;
8331 }
8332
8333 return skb;
8334 }
8335
igb_build_skb(struct igb_ring * rx_ring,struct igb_rx_buffer * rx_buffer,struct xdp_buff * xdp,union e1000_adv_rx_desc * rx_desc)8336 static struct sk_buff *igb_build_skb(struct igb_ring *rx_ring,
8337 struct igb_rx_buffer *rx_buffer,
8338 struct xdp_buff *xdp,
8339 union e1000_adv_rx_desc *rx_desc)
8340 {
8341 #if (PAGE_SIZE < 8192)
8342 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2;
8343 #else
8344 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
8345 SKB_DATA_ALIGN(xdp->data_end -
8346 xdp->data_hard_start);
8347 #endif
8348 unsigned int metasize = xdp->data - xdp->data_meta;
8349 struct sk_buff *skb;
8350
8351 /* prefetch first cache line of first page */
8352 net_prefetch(xdp->data_meta);
8353
8354 /* build an skb around the page buffer */
8355 skb = build_skb(xdp->data_hard_start, truesize);
8356 if (unlikely(!skb))
8357 return NULL;
8358
8359 /* update pointers within the skb to store the data */
8360 skb_reserve(skb, xdp->data - xdp->data_hard_start);
8361 __skb_put(skb, xdp->data_end - xdp->data);
8362
8363 if (metasize)
8364 skb_metadata_set(skb, metasize);
8365
8366 /* pull timestamp out of packet data */
8367 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
8368 if (!igb_ptp_rx_pktstamp(rx_ring->q_vector, skb->data, skb))
8369 __skb_pull(skb, IGB_TS_HDR_LEN);
8370 }
8371
8372 /* update buffer offset */
8373 #if (PAGE_SIZE < 8192)
8374 rx_buffer->page_offset ^= truesize;
8375 #else
8376 rx_buffer->page_offset += truesize;
8377 #endif
8378
8379 return skb;
8380 }
8381
igb_run_xdp(struct igb_adapter * adapter,struct igb_ring * rx_ring,struct xdp_buff * xdp)8382 static struct sk_buff *igb_run_xdp(struct igb_adapter *adapter,
8383 struct igb_ring *rx_ring,
8384 struct xdp_buff *xdp)
8385 {
8386 int err, result = IGB_XDP_PASS;
8387 struct bpf_prog *xdp_prog;
8388 u32 act;
8389
8390 rcu_read_lock();
8391 xdp_prog = READ_ONCE(rx_ring->xdp_prog);
8392
8393 if (!xdp_prog)
8394 goto xdp_out;
8395
8396 prefetchw(xdp->data_hard_start); /* xdp_frame write */
8397
8398 act = bpf_prog_run_xdp(xdp_prog, xdp);
8399 switch (act) {
8400 case XDP_PASS:
8401 break;
8402 case XDP_TX:
8403 result = igb_xdp_xmit_back(adapter, xdp);
8404 break;
8405 case XDP_REDIRECT:
8406 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog);
8407 if (!err)
8408 result = IGB_XDP_REDIR;
8409 else
8410 result = IGB_XDP_CONSUMED;
8411 break;
8412 default:
8413 bpf_warn_invalid_xdp_action(act);
8414 fallthrough;
8415 case XDP_ABORTED:
8416 trace_xdp_exception(rx_ring->netdev, xdp_prog, act);
8417 fallthrough;
8418 case XDP_DROP:
8419 result = IGB_XDP_CONSUMED;
8420 break;
8421 }
8422 xdp_out:
8423 rcu_read_unlock();
8424 return ERR_PTR(-result);
8425 }
8426
igb_rx_frame_truesize(struct igb_ring * rx_ring,unsigned int size)8427 static unsigned int igb_rx_frame_truesize(struct igb_ring *rx_ring,
8428 unsigned int size)
8429 {
8430 unsigned int truesize;
8431
8432 #if (PAGE_SIZE < 8192)
8433 truesize = igb_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */
8434 #else
8435 truesize = ring_uses_build_skb(rx_ring) ?
8436 SKB_DATA_ALIGN(IGB_SKB_PAD + size) +
8437 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) :
8438 SKB_DATA_ALIGN(size);
8439 #endif
8440 return truesize;
8441 }
8442
igb_rx_buffer_flip(struct igb_ring * rx_ring,struct igb_rx_buffer * rx_buffer,unsigned int size)8443 static void igb_rx_buffer_flip(struct igb_ring *rx_ring,
8444 struct igb_rx_buffer *rx_buffer,
8445 unsigned int size)
8446 {
8447 unsigned int truesize = igb_rx_frame_truesize(rx_ring, size);
8448 #if (PAGE_SIZE < 8192)
8449 rx_buffer->page_offset ^= truesize;
8450 #else
8451 rx_buffer->page_offset += truesize;
8452 #endif
8453 }
8454
igb_rx_checksum(struct igb_ring * ring,union e1000_adv_rx_desc * rx_desc,struct sk_buff * skb)8455 static inline void igb_rx_checksum(struct igb_ring *ring,
8456 union e1000_adv_rx_desc *rx_desc,
8457 struct sk_buff *skb)
8458 {
8459 skb_checksum_none_assert(skb);
8460
8461 /* Ignore Checksum bit is set */
8462 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
8463 return;
8464
8465 /* Rx checksum disabled via ethtool */
8466 if (!(ring->netdev->features & NETIF_F_RXCSUM))
8467 return;
8468
8469 /* TCP/UDP checksum error bit is set */
8470 if (igb_test_staterr(rx_desc,
8471 E1000_RXDEXT_STATERR_TCPE |
8472 E1000_RXDEXT_STATERR_IPE)) {
8473 /* work around errata with sctp packets where the TCPE aka
8474 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
8475 * packets, (aka let the stack check the crc32c)
8476 */
8477 if (!((skb->len == 60) &&
8478 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
8479 u64_stats_update_begin(&ring->rx_syncp);
8480 ring->rx_stats.csum_err++;
8481 u64_stats_update_end(&ring->rx_syncp);
8482 }
8483 /* let the stack verify checksum errors */
8484 return;
8485 }
8486 /* It must be a TCP or UDP packet with a valid checksum */
8487 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
8488 E1000_RXD_STAT_UDPCS))
8489 skb->ip_summed = CHECKSUM_UNNECESSARY;
8490
8491 dev_dbg(ring->dev, "cksum success: bits %08X\n",
8492 le32_to_cpu(rx_desc->wb.upper.status_error));
8493 }
8494
igb_rx_hash(struct igb_ring * ring,union e1000_adv_rx_desc * rx_desc,struct sk_buff * skb)8495 static inline void igb_rx_hash(struct igb_ring *ring,
8496 union e1000_adv_rx_desc *rx_desc,
8497 struct sk_buff *skb)
8498 {
8499 if (ring->netdev->features & NETIF_F_RXHASH)
8500 skb_set_hash(skb,
8501 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
8502 PKT_HASH_TYPE_L3);
8503 }
8504
8505 /**
8506 * igb_is_non_eop - process handling of non-EOP buffers
8507 * @rx_ring: Rx ring being processed
8508 * @rx_desc: Rx descriptor for current buffer
8509 *
8510 * This function updates next to clean. If the buffer is an EOP buffer
8511 * this function exits returning false, otherwise it will place the
8512 * sk_buff in the next buffer to be chained and return true indicating
8513 * that this is in fact a non-EOP buffer.
8514 **/
igb_is_non_eop(struct igb_ring * rx_ring,union e1000_adv_rx_desc * rx_desc)8515 static bool igb_is_non_eop(struct igb_ring *rx_ring,
8516 union e1000_adv_rx_desc *rx_desc)
8517 {
8518 u32 ntc = rx_ring->next_to_clean + 1;
8519
8520 /* fetch, update, and store next to clean */
8521 ntc = (ntc < rx_ring->count) ? ntc : 0;
8522 rx_ring->next_to_clean = ntc;
8523
8524 prefetch(IGB_RX_DESC(rx_ring, ntc));
8525
8526 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
8527 return false;
8528
8529 return true;
8530 }
8531
8532 /**
8533 * igb_cleanup_headers - Correct corrupted or empty headers
8534 * @rx_ring: rx descriptor ring packet is being transacted on
8535 * @rx_desc: pointer to the EOP Rx descriptor
8536 * @skb: pointer to current skb being fixed
8537 *
8538 * Address the case where we are pulling data in on pages only
8539 * and as such no data is present in the skb header.
8540 *
8541 * In addition if skb is not at least 60 bytes we need to pad it so that
8542 * it is large enough to qualify as a valid Ethernet frame.
8543 *
8544 * Returns true if an error was encountered and skb was freed.
8545 **/
igb_cleanup_headers(struct igb_ring * rx_ring,union e1000_adv_rx_desc * rx_desc,struct sk_buff * skb)8546 static bool igb_cleanup_headers(struct igb_ring *rx_ring,
8547 union e1000_adv_rx_desc *rx_desc,
8548 struct sk_buff *skb)
8549 {
8550 /* XDP packets use error pointer so abort at this point */
8551 if (IS_ERR(skb))
8552 return true;
8553
8554 if (unlikely((igb_test_staterr(rx_desc,
8555 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
8556 struct net_device *netdev = rx_ring->netdev;
8557 if (!(netdev->features & NETIF_F_RXALL)) {
8558 dev_kfree_skb_any(skb);
8559 return true;
8560 }
8561 }
8562
8563 /* if eth_skb_pad returns an error the skb was freed */
8564 if (eth_skb_pad(skb))
8565 return true;
8566
8567 return false;
8568 }
8569
8570 /**
8571 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
8572 * @rx_ring: rx descriptor ring packet is being transacted on
8573 * @rx_desc: pointer to the EOP Rx descriptor
8574 * @skb: pointer to current skb being populated
8575 *
8576 * This function checks the ring, descriptor, and packet information in
8577 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
8578 * other fields within the skb.
8579 **/
igb_process_skb_fields(struct igb_ring * rx_ring,union e1000_adv_rx_desc * rx_desc,struct sk_buff * skb)8580 static void igb_process_skb_fields(struct igb_ring *rx_ring,
8581 union e1000_adv_rx_desc *rx_desc,
8582 struct sk_buff *skb)
8583 {
8584 struct net_device *dev = rx_ring->netdev;
8585
8586 igb_rx_hash(rx_ring, rx_desc, skb);
8587
8588 igb_rx_checksum(rx_ring, rx_desc, skb);
8589
8590 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
8591 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
8592 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
8593
8594 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
8595 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
8596 u16 vid;
8597
8598 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
8599 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
8600 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
8601 else
8602 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
8603
8604 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
8605 }
8606
8607 skb_record_rx_queue(skb, rx_ring->queue_index);
8608
8609 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
8610 }
8611
igb_rx_offset(struct igb_ring * rx_ring)8612 static unsigned int igb_rx_offset(struct igb_ring *rx_ring)
8613 {
8614 return ring_uses_build_skb(rx_ring) ? IGB_SKB_PAD : 0;
8615 }
8616
igb_get_rx_buffer(struct igb_ring * rx_ring,const unsigned int size,int * rx_buf_pgcnt)8617 static struct igb_rx_buffer *igb_get_rx_buffer(struct igb_ring *rx_ring,
8618 const unsigned int size, int *rx_buf_pgcnt)
8619 {
8620 struct igb_rx_buffer *rx_buffer;
8621
8622 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
8623 *rx_buf_pgcnt =
8624 #if (PAGE_SIZE < 8192)
8625 page_count(rx_buffer->page);
8626 #else
8627 0;
8628 #endif
8629 prefetchw(rx_buffer->page);
8630
8631 /* we are reusing so sync this buffer for CPU use */
8632 dma_sync_single_range_for_cpu(rx_ring->dev,
8633 rx_buffer->dma,
8634 rx_buffer->page_offset,
8635 size,
8636 DMA_FROM_DEVICE);
8637
8638 rx_buffer->pagecnt_bias--;
8639
8640 return rx_buffer;
8641 }
8642
igb_put_rx_buffer(struct igb_ring * rx_ring,struct igb_rx_buffer * rx_buffer,int rx_buf_pgcnt)8643 static void igb_put_rx_buffer(struct igb_ring *rx_ring,
8644 struct igb_rx_buffer *rx_buffer, int rx_buf_pgcnt)
8645 {
8646 if (igb_can_reuse_rx_page(rx_buffer, rx_buf_pgcnt)) {
8647 /* hand second half of page back to the ring */
8648 igb_reuse_rx_page(rx_ring, rx_buffer);
8649 } else {
8650 /* We are not reusing the buffer so unmap it and free
8651 * any references we are holding to it
8652 */
8653 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,
8654 igb_rx_pg_size(rx_ring), DMA_FROM_DEVICE,
8655 IGB_RX_DMA_ATTR);
8656 __page_frag_cache_drain(rx_buffer->page,
8657 rx_buffer->pagecnt_bias);
8658 }
8659
8660 /* clear contents of rx_buffer */
8661 rx_buffer->page = NULL;
8662 }
8663
igb_clean_rx_irq(struct igb_q_vector * q_vector,const int budget)8664 static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
8665 {
8666 struct igb_adapter *adapter = q_vector->adapter;
8667 struct igb_ring *rx_ring = q_vector->rx.ring;
8668 struct sk_buff *skb = rx_ring->skb;
8669 unsigned int total_bytes = 0, total_packets = 0;
8670 u16 cleaned_count = igb_desc_unused(rx_ring);
8671 unsigned int xdp_xmit = 0;
8672 struct xdp_buff xdp;
8673 u32 frame_sz = 0;
8674 int rx_buf_pgcnt;
8675
8676 /* Frame size depend on rx_ring setup when PAGE_SIZE=4K */
8677 #if (PAGE_SIZE < 8192)
8678 frame_sz = igb_rx_frame_truesize(rx_ring, 0);
8679 #endif
8680 xdp_init_buff(&xdp, frame_sz, &rx_ring->xdp_rxq);
8681
8682 while (likely(total_packets < budget)) {
8683 union e1000_adv_rx_desc *rx_desc;
8684 struct igb_rx_buffer *rx_buffer;
8685 unsigned int size;
8686
8687 /* return some buffers to hardware, one at a time is too slow */
8688 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
8689 igb_alloc_rx_buffers(rx_ring, cleaned_count);
8690 cleaned_count = 0;
8691 }
8692
8693 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
8694 size = le16_to_cpu(rx_desc->wb.upper.length);
8695 if (!size)
8696 break;
8697
8698 /* This memory barrier is needed to keep us from reading
8699 * any other fields out of the rx_desc until we know the
8700 * descriptor has been written back
8701 */
8702 dma_rmb();
8703
8704 rx_buffer = igb_get_rx_buffer(rx_ring, size, &rx_buf_pgcnt);
8705
8706 /* retrieve a buffer from the ring */
8707 if (!skb) {
8708 unsigned int offset = igb_rx_offset(rx_ring);
8709 unsigned char *hard_start;
8710
8711 hard_start = page_address(rx_buffer->page) +
8712 rx_buffer->page_offset - offset;
8713 xdp_prepare_buff(&xdp, hard_start, offset, size, true);
8714 #if (PAGE_SIZE > 4096)
8715 /* At larger PAGE_SIZE, frame_sz depend on len size */
8716 xdp.frame_sz = igb_rx_frame_truesize(rx_ring, size);
8717 #endif
8718 skb = igb_run_xdp(adapter, rx_ring, &xdp);
8719 }
8720
8721 if (IS_ERR(skb)) {
8722 unsigned int xdp_res = -PTR_ERR(skb);
8723
8724 if (xdp_res & (IGB_XDP_TX | IGB_XDP_REDIR)) {
8725 xdp_xmit |= xdp_res;
8726 igb_rx_buffer_flip(rx_ring, rx_buffer, size);
8727 } else {
8728 rx_buffer->pagecnt_bias++;
8729 }
8730 total_packets++;
8731 total_bytes += size;
8732 } else if (skb)
8733 igb_add_rx_frag(rx_ring, rx_buffer, skb, size);
8734 else if (ring_uses_build_skb(rx_ring))
8735 skb = igb_build_skb(rx_ring, rx_buffer, &xdp, rx_desc);
8736 else
8737 skb = igb_construct_skb(rx_ring, rx_buffer,
8738 &xdp, rx_desc);
8739
8740 /* exit if we failed to retrieve a buffer */
8741 if (!skb) {
8742 rx_ring->rx_stats.alloc_failed++;
8743 rx_buffer->pagecnt_bias++;
8744 break;
8745 }
8746
8747 igb_put_rx_buffer(rx_ring, rx_buffer, rx_buf_pgcnt);
8748 cleaned_count++;
8749
8750 /* fetch next buffer in frame if non-eop */
8751 if (igb_is_non_eop(rx_ring, rx_desc))
8752 continue;
8753
8754 /* verify the packet layout is correct */
8755 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
8756 skb = NULL;
8757 continue;
8758 }
8759
8760 /* probably a little skewed due to removing CRC */
8761 total_bytes += skb->len;
8762
8763 /* populate checksum, timestamp, VLAN, and protocol */
8764 igb_process_skb_fields(rx_ring, rx_desc, skb);
8765
8766 napi_gro_receive(&q_vector->napi, skb);
8767
8768 /* reset skb pointer */
8769 skb = NULL;
8770
8771 /* update budget accounting */
8772 total_packets++;
8773 }
8774
8775 /* place incomplete frames back on ring for completion */
8776 rx_ring->skb = skb;
8777
8778 if (xdp_xmit & IGB_XDP_REDIR)
8779 xdp_do_flush();
8780
8781 if (xdp_xmit & IGB_XDP_TX) {
8782 struct igb_ring *tx_ring = igb_xdp_tx_queue_mapping(adapter);
8783
8784 igb_xdp_ring_update_tail(tx_ring);
8785 }
8786
8787 u64_stats_update_begin(&rx_ring->rx_syncp);
8788 rx_ring->rx_stats.packets += total_packets;
8789 rx_ring->rx_stats.bytes += total_bytes;
8790 u64_stats_update_end(&rx_ring->rx_syncp);
8791 q_vector->rx.total_packets += total_packets;
8792 q_vector->rx.total_bytes += total_bytes;
8793
8794 if (cleaned_count)
8795 igb_alloc_rx_buffers(rx_ring, cleaned_count);
8796
8797 return total_packets;
8798 }
8799
igb_alloc_mapped_page(struct igb_ring * rx_ring,struct igb_rx_buffer * bi)8800 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
8801 struct igb_rx_buffer *bi)
8802 {
8803 struct page *page = bi->page;
8804 dma_addr_t dma;
8805
8806 /* since we are recycling buffers we should seldom need to alloc */
8807 if (likely(page))
8808 return true;
8809
8810 /* alloc new page for storage */
8811 page = dev_alloc_pages(igb_rx_pg_order(rx_ring));
8812 if (unlikely(!page)) {
8813 rx_ring->rx_stats.alloc_failed++;
8814 return false;
8815 }
8816
8817 /* map page for use */
8818 dma = dma_map_page_attrs(rx_ring->dev, page, 0,
8819 igb_rx_pg_size(rx_ring),
8820 DMA_FROM_DEVICE,
8821 IGB_RX_DMA_ATTR);
8822
8823 /* if mapping failed free memory back to system since
8824 * there isn't much point in holding memory we can't use
8825 */
8826 if (dma_mapping_error(rx_ring->dev, dma)) {
8827 __free_pages(page, igb_rx_pg_order(rx_ring));
8828
8829 rx_ring->rx_stats.alloc_failed++;
8830 return false;
8831 }
8832
8833 bi->dma = dma;
8834 bi->page = page;
8835 bi->page_offset = igb_rx_offset(rx_ring);
8836 page_ref_add(page, USHRT_MAX - 1);
8837 bi->pagecnt_bias = USHRT_MAX;
8838
8839 return true;
8840 }
8841
8842 /**
8843 * igb_alloc_rx_buffers - Replace used receive buffers
8844 * @rx_ring: rx descriptor ring to allocate new receive buffers
8845 * @cleaned_count: count of buffers to allocate
8846 **/
igb_alloc_rx_buffers(struct igb_ring * rx_ring,u16 cleaned_count)8847 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
8848 {
8849 union e1000_adv_rx_desc *rx_desc;
8850 struct igb_rx_buffer *bi;
8851 u16 i = rx_ring->next_to_use;
8852 u16 bufsz;
8853
8854 /* nothing to do */
8855 if (!cleaned_count)
8856 return;
8857
8858 rx_desc = IGB_RX_DESC(rx_ring, i);
8859 bi = &rx_ring->rx_buffer_info[i];
8860 i -= rx_ring->count;
8861
8862 bufsz = igb_rx_bufsz(rx_ring);
8863
8864 do {
8865 if (!igb_alloc_mapped_page(rx_ring, bi))
8866 break;
8867
8868 /* sync the buffer for use by the device */
8869 dma_sync_single_range_for_device(rx_ring->dev, bi->dma,
8870 bi->page_offset, bufsz,
8871 DMA_FROM_DEVICE);
8872
8873 /* Refresh the desc even if buffer_addrs didn't change
8874 * because each write-back erases this info.
8875 */
8876 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
8877
8878 rx_desc++;
8879 bi++;
8880 i++;
8881 if (unlikely(!i)) {
8882 rx_desc = IGB_RX_DESC(rx_ring, 0);
8883 bi = rx_ring->rx_buffer_info;
8884 i -= rx_ring->count;
8885 }
8886
8887 /* clear the length for the next_to_use descriptor */
8888 rx_desc->wb.upper.length = 0;
8889
8890 cleaned_count--;
8891 } while (cleaned_count);
8892
8893 i += rx_ring->count;
8894
8895 if (rx_ring->next_to_use != i) {
8896 /* record the next descriptor to use */
8897 rx_ring->next_to_use = i;
8898
8899 /* update next to alloc since we have filled the ring */
8900 rx_ring->next_to_alloc = i;
8901
8902 /* Force memory writes to complete before letting h/w
8903 * know there are new descriptors to fetch. (Only
8904 * applicable for weak-ordered memory model archs,
8905 * such as IA-64).
8906 */
8907 dma_wmb();
8908 writel(i, rx_ring->tail);
8909 }
8910 }
8911
8912 /**
8913 * igb_mii_ioctl -
8914 * @netdev: pointer to netdev struct
8915 * @ifr: interface structure
8916 * @cmd: ioctl command to execute
8917 **/
igb_mii_ioctl(struct net_device * netdev,struct ifreq * ifr,int cmd)8918 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
8919 {
8920 struct igb_adapter *adapter = netdev_priv(netdev);
8921 struct mii_ioctl_data *data = if_mii(ifr);
8922
8923 if (adapter->hw.phy.media_type != e1000_media_type_copper)
8924 return -EOPNOTSUPP;
8925
8926 switch (cmd) {
8927 case SIOCGMIIPHY:
8928 data->phy_id = adapter->hw.phy.addr;
8929 break;
8930 case SIOCGMIIREG:
8931 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
8932 &data->val_out))
8933 return -EIO;
8934 break;
8935 case SIOCSMIIREG:
8936 default:
8937 return -EOPNOTSUPP;
8938 }
8939 return 0;
8940 }
8941
8942 /**
8943 * igb_ioctl -
8944 * @netdev: pointer to netdev struct
8945 * @ifr: interface structure
8946 * @cmd: ioctl command to execute
8947 **/
igb_ioctl(struct net_device * netdev,struct ifreq * ifr,int cmd)8948 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
8949 {
8950 switch (cmd) {
8951 case SIOCGMIIPHY:
8952 case SIOCGMIIREG:
8953 case SIOCSMIIREG:
8954 return igb_mii_ioctl(netdev, ifr, cmd);
8955 case SIOCGHWTSTAMP:
8956 return igb_ptp_get_ts_config(netdev, ifr);
8957 case SIOCSHWTSTAMP:
8958 return igb_ptp_set_ts_config(netdev, ifr);
8959 default:
8960 return -EOPNOTSUPP;
8961 }
8962 }
8963
igb_read_pci_cfg(struct e1000_hw * hw,u32 reg,u16 * value)8964 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
8965 {
8966 struct igb_adapter *adapter = hw->back;
8967
8968 pci_read_config_word(adapter->pdev, reg, value);
8969 }
8970
igb_write_pci_cfg(struct e1000_hw * hw,u32 reg,u16 * value)8971 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
8972 {
8973 struct igb_adapter *adapter = hw->back;
8974
8975 pci_write_config_word(adapter->pdev, reg, *value);
8976 }
8977
igb_read_pcie_cap_reg(struct e1000_hw * hw,u32 reg,u16 * value)8978 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
8979 {
8980 struct igb_adapter *adapter = hw->back;
8981
8982 if (pcie_capability_read_word(adapter->pdev, reg, value))
8983 return -E1000_ERR_CONFIG;
8984
8985 return 0;
8986 }
8987
igb_write_pcie_cap_reg(struct e1000_hw * hw,u32 reg,u16 * value)8988 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
8989 {
8990 struct igb_adapter *adapter = hw->back;
8991
8992 if (pcie_capability_write_word(adapter->pdev, reg, *value))
8993 return -E1000_ERR_CONFIG;
8994
8995 return 0;
8996 }
8997
igb_vlan_mode(struct net_device * netdev,netdev_features_t features)8998 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
8999 {
9000 struct igb_adapter *adapter = netdev_priv(netdev);
9001 struct e1000_hw *hw = &adapter->hw;
9002 u32 ctrl, rctl;
9003 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
9004
9005 if (enable) {
9006 /* enable VLAN tag insert/strip */
9007 ctrl = rd32(E1000_CTRL);
9008 ctrl |= E1000_CTRL_VME;
9009 wr32(E1000_CTRL, ctrl);
9010
9011 /* Disable CFI check */
9012 rctl = rd32(E1000_RCTL);
9013 rctl &= ~E1000_RCTL_CFIEN;
9014 wr32(E1000_RCTL, rctl);
9015 } else {
9016 /* disable VLAN tag insert/strip */
9017 ctrl = rd32(E1000_CTRL);
9018 ctrl &= ~E1000_CTRL_VME;
9019 wr32(E1000_CTRL, ctrl);
9020 }
9021
9022 igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable);
9023 }
9024
igb_vlan_rx_add_vid(struct net_device * netdev,__be16 proto,u16 vid)9025 static int igb_vlan_rx_add_vid(struct net_device *netdev,
9026 __be16 proto, u16 vid)
9027 {
9028 struct igb_adapter *adapter = netdev_priv(netdev);
9029 struct e1000_hw *hw = &adapter->hw;
9030 int pf_id = adapter->vfs_allocated_count;
9031
9032 /* add the filter since PF can receive vlans w/o entry in vlvf */
9033 if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC))
9034 igb_vfta_set(hw, vid, pf_id, true, !!vid);
9035
9036 set_bit(vid, adapter->active_vlans);
9037
9038 return 0;
9039 }
9040
igb_vlan_rx_kill_vid(struct net_device * netdev,__be16 proto,u16 vid)9041 static int igb_vlan_rx_kill_vid(struct net_device *netdev,
9042 __be16 proto, u16 vid)
9043 {
9044 struct igb_adapter *adapter = netdev_priv(netdev);
9045 int pf_id = adapter->vfs_allocated_count;
9046 struct e1000_hw *hw = &adapter->hw;
9047
9048 /* remove VID from filter table */
9049 if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC))
9050 igb_vfta_set(hw, vid, pf_id, false, true);
9051
9052 clear_bit(vid, adapter->active_vlans);
9053
9054 return 0;
9055 }
9056
igb_restore_vlan(struct igb_adapter * adapter)9057 static void igb_restore_vlan(struct igb_adapter *adapter)
9058 {
9059 u16 vid = 1;
9060
9061 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
9062 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
9063
9064 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID)
9065 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9066 }
9067
igb_set_spd_dplx(struct igb_adapter * adapter,u32 spd,u8 dplx)9068 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9069 {
9070 struct pci_dev *pdev = adapter->pdev;
9071 struct e1000_mac_info *mac = &adapter->hw.mac;
9072
9073 mac->autoneg = 0;
9074
9075 /* Make sure dplx is at most 1 bit and lsb of speed is not set
9076 * for the switch() below to work
9077 */
9078 if ((spd & 1) || (dplx & ~1))
9079 goto err_inval;
9080
9081 /* Fiber NIC's only allow 1000 gbps Full duplex
9082 * and 100Mbps Full duplex for 100baseFx sfp
9083 */
9084 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
9085 switch (spd + dplx) {
9086 case SPEED_10 + DUPLEX_HALF:
9087 case SPEED_10 + DUPLEX_FULL:
9088 case SPEED_100 + DUPLEX_HALF:
9089 goto err_inval;
9090 default:
9091 break;
9092 }
9093 }
9094
9095 switch (spd + dplx) {
9096 case SPEED_10 + DUPLEX_HALF:
9097 mac->forced_speed_duplex = ADVERTISE_10_HALF;
9098 break;
9099 case SPEED_10 + DUPLEX_FULL:
9100 mac->forced_speed_duplex = ADVERTISE_10_FULL;
9101 break;
9102 case SPEED_100 + DUPLEX_HALF:
9103 mac->forced_speed_duplex = ADVERTISE_100_HALF;
9104 break;
9105 case SPEED_100 + DUPLEX_FULL:
9106 mac->forced_speed_duplex = ADVERTISE_100_FULL;
9107 break;
9108 case SPEED_1000 + DUPLEX_FULL:
9109 mac->autoneg = 1;
9110 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
9111 break;
9112 case SPEED_1000 + DUPLEX_HALF: /* not supported */
9113 default:
9114 goto err_inval;
9115 }
9116
9117 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
9118 adapter->hw.phy.mdix = AUTO_ALL_MODES;
9119
9120 return 0;
9121
9122 err_inval:
9123 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
9124 return -EINVAL;
9125 }
9126
__igb_shutdown(struct pci_dev * pdev,bool * enable_wake,bool runtime)9127 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
9128 bool runtime)
9129 {
9130 struct net_device *netdev = pci_get_drvdata(pdev);
9131 struct igb_adapter *adapter = netdev_priv(netdev);
9132 struct e1000_hw *hw = &adapter->hw;
9133 u32 ctrl, rctl, status;
9134 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
9135 bool wake;
9136
9137 rtnl_lock();
9138 netif_device_detach(netdev);
9139
9140 if (netif_running(netdev))
9141 __igb_close(netdev, true);
9142
9143 igb_ptp_suspend(adapter);
9144
9145 igb_clear_interrupt_scheme(adapter);
9146 rtnl_unlock();
9147
9148 status = rd32(E1000_STATUS);
9149 if (status & E1000_STATUS_LU)
9150 wufc &= ~E1000_WUFC_LNKC;
9151
9152 if (wufc) {
9153 igb_setup_rctl(adapter);
9154 igb_set_rx_mode(netdev);
9155
9156 /* turn on all-multi mode if wake on multicast is enabled */
9157 if (wufc & E1000_WUFC_MC) {
9158 rctl = rd32(E1000_RCTL);
9159 rctl |= E1000_RCTL_MPE;
9160 wr32(E1000_RCTL, rctl);
9161 }
9162
9163 ctrl = rd32(E1000_CTRL);
9164 ctrl |= E1000_CTRL_ADVD3WUC;
9165 wr32(E1000_CTRL, ctrl);
9166
9167 /* Allow time for pending master requests to run */
9168 igb_disable_pcie_master(hw);
9169
9170 wr32(E1000_WUC, E1000_WUC_PME_EN);
9171 wr32(E1000_WUFC, wufc);
9172 } else {
9173 wr32(E1000_WUC, 0);
9174 wr32(E1000_WUFC, 0);
9175 }
9176
9177 wake = wufc || adapter->en_mng_pt;
9178 if (!wake)
9179 igb_power_down_link(adapter);
9180 else
9181 igb_power_up_link(adapter);
9182
9183 if (enable_wake)
9184 *enable_wake = wake;
9185
9186 /* Release control of h/w to f/w. If f/w is AMT enabled, this
9187 * would have already happened in close and is redundant.
9188 */
9189 igb_release_hw_control(adapter);
9190
9191 pci_disable_device(pdev);
9192
9193 return 0;
9194 }
9195
igb_deliver_wake_packet(struct net_device * netdev)9196 static void igb_deliver_wake_packet(struct net_device *netdev)
9197 {
9198 struct igb_adapter *adapter = netdev_priv(netdev);
9199 struct e1000_hw *hw = &adapter->hw;
9200 struct sk_buff *skb;
9201 u32 wupl;
9202
9203 wupl = rd32(E1000_WUPL) & E1000_WUPL_MASK;
9204
9205 /* WUPM stores only the first 128 bytes of the wake packet.
9206 * Read the packet only if we have the whole thing.
9207 */
9208 if ((wupl == 0) || (wupl > E1000_WUPM_BYTES))
9209 return;
9210
9211 skb = netdev_alloc_skb_ip_align(netdev, E1000_WUPM_BYTES);
9212 if (!skb)
9213 return;
9214
9215 skb_put(skb, wupl);
9216
9217 /* Ensure reads are 32-bit aligned */
9218 wupl = roundup(wupl, 4);
9219
9220 memcpy_fromio(skb->data, hw->hw_addr + E1000_WUPM_REG(0), wupl);
9221
9222 skb->protocol = eth_type_trans(skb, netdev);
9223 netif_rx(skb);
9224 }
9225
igb_suspend(struct device * dev)9226 static int __maybe_unused igb_suspend(struct device *dev)
9227 {
9228 return __igb_shutdown(to_pci_dev(dev), NULL, 0);
9229 }
9230
igb_resume(struct device * dev)9231 static int __maybe_unused igb_resume(struct device *dev)
9232 {
9233 struct pci_dev *pdev = to_pci_dev(dev);
9234 struct net_device *netdev = pci_get_drvdata(pdev);
9235 struct igb_adapter *adapter = netdev_priv(netdev);
9236 struct e1000_hw *hw = &adapter->hw;
9237 u32 err, val;
9238
9239 pci_set_power_state(pdev, PCI_D0);
9240 pci_restore_state(pdev);
9241 pci_save_state(pdev);
9242
9243 if (!pci_device_is_present(pdev))
9244 return -ENODEV;
9245 err = pci_enable_device_mem(pdev);
9246 if (err) {
9247 dev_err(&pdev->dev,
9248 "igb: Cannot enable PCI device from suspend\n");
9249 return err;
9250 }
9251 pci_set_master(pdev);
9252
9253 pci_enable_wake(pdev, PCI_D3hot, 0);
9254 pci_enable_wake(pdev, PCI_D3cold, 0);
9255
9256 if (igb_init_interrupt_scheme(adapter, true)) {
9257 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
9258 return -ENOMEM;
9259 }
9260
9261 igb_reset(adapter);
9262
9263 /* let the f/w know that the h/w is now under the control of the
9264 * driver.
9265 */
9266 igb_get_hw_control(adapter);
9267
9268 val = rd32(E1000_WUS);
9269 if (val & WAKE_PKT_WUS)
9270 igb_deliver_wake_packet(netdev);
9271
9272 wr32(E1000_WUS, ~0);
9273
9274 rtnl_lock();
9275 if (!err && netif_running(netdev))
9276 err = __igb_open(netdev, true);
9277
9278 if (!err)
9279 netif_device_attach(netdev);
9280 rtnl_unlock();
9281
9282 return err;
9283 }
9284
igb_runtime_idle(struct device * dev)9285 static int __maybe_unused igb_runtime_idle(struct device *dev)
9286 {
9287 struct net_device *netdev = dev_get_drvdata(dev);
9288 struct igb_adapter *adapter = netdev_priv(netdev);
9289
9290 if (!igb_has_link(adapter))
9291 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
9292
9293 return -EBUSY;
9294 }
9295
igb_runtime_suspend(struct device * dev)9296 static int __maybe_unused igb_runtime_suspend(struct device *dev)
9297 {
9298 return __igb_shutdown(to_pci_dev(dev), NULL, 1);
9299 }
9300
igb_runtime_resume(struct device * dev)9301 static int __maybe_unused igb_runtime_resume(struct device *dev)
9302 {
9303 return igb_resume(dev);
9304 }
9305
igb_shutdown(struct pci_dev * pdev)9306 static void igb_shutdown(struct pci_dev *pdev)
9307 {
9308 bool wake;
9309
9310 __igb_shutdown(pdev, &wake, 0);
9311
9312 if (system_state == SYSTEM_POWER_OFF) {
9313 pci_wake_from_d3(pdev, wake);
9314 pci_set_power_state(pdev, PCI_D3hot);
9315 }
9316 }
9317
9318 #ifdef CONFIG_PCI_IOV
igb_sriov_reinit(struct pci_dev * dev)9319 static int igb_sriov_reinit(struct pci_dev *dev)
9320 {
9321 struct net_device *netdev = pci_get_drvdata(dev);
9322 struct igb_adapter *adapter = netdev_priv(netdev);
9323 struct pci_dev *pdev = adapter->pdev;
9324
9325 rtnl_lock();
9326
9327 if (netif_running(netdev))
9328 igb_close(netdev);
9329 else
9330 igb_reset(adapter);
9331
9332 igb_clear_interrupt_scheme(adapter);
9333
9334 igb_init_queue_configuration(adapter);
9335
9336 if (igb_init_interrupt_scheme(adapter, true)) {
9337 rtnl_unlock();
9338 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
9339 return -ENOMEM;
9340 }
9341
9342 if (netif_running(netdev))
9343 igb_open(netdev);
9344
9345 rtnl_unlock();
9346
9347 return 0;
9348 }
9349
igb_pci_disable_sriov(struct pci_dev * dev)9350 static int igb_pci_disable_sriov(struct pci_dev *dev)
9351 {
9352 int err = igb_disable_sriov(dev);
9353
9354 if (!err)
9355 err = igb_sriov_reinit(dev);
9356
9357 return err;
9358 }
9359
igb_pci_enable_sriov(struct pci_dev * dev,int num_vfs)9360 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
9361 {
9362 int err = igb_enable_sriov(dev, num_vfs);
9363
9364 if (err)
9365 goto out;
9366
9367 err = igb_sriov_reinit(dev);
9368 if (!err)
9369 return num_vfs;
9370
9371 out:
9372 return err;
9373 }
9374
9375 #endif
igb_pci_sriov_configure(struct pci_dev * dev,int num_vfs)9376 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
9377 {
9378 #ifdef CONFIG_PCI_IOV
9379 if (num_vfs == 0)
9380 return igb_pci_disable_sriov(dev);
9381 else
9382 return igb_pci_enable_sriov(dev, num_vfs);
9383 #endif
9384 return 0;
9385 }
9386
9387 /**
9388 * igb_io_error_detected - called when PCI error is detected
9389 * @pdev: Pointer to PCI device
9390 * @state: The current pci connection state
9391 *
9392 * This function is called after a PCI bus error affecting
9393 * this device has been detected.
9394 **/
igb_io_error_detected(struct pci_dev * pdev,pci_channel_state_t state)9395 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
9396 pci_channel_state_t state)
9397 {
9398 struct net_device *netdev = pci_get_drvdata(pdev);
9399 struct igb_adapter *adapter = netdev_priv(netdev);
9400
9401 netif_device_detach(netdev);
9402
9403 if (state == pci_channel_io_perm_failure)
9404 return PCI_ERS_RESULT_DISCONNECT;
9405
9406 if (netif_running(netdev))
9407 igb_down(adapter);
9408 pci_disable_device(pdev);
9409
9410 /* Request a slot slot reset. */
9411 return PCI_ERS_RESULT_NEED_RESET;
9412 }
9413
9414 /**
9415 * igb_io_slot_reset - called after the pci bus has been reset.
9416 * @pdev: Pointer to PCI device
9417 *
9418 * Restart the card from scratch, as if from a cold-boot. Implementation
9419 * resembles the first-half of the igb_resume routine.
9420 **/
igb_io_slot_reset(struct pci_dev * pdev)9421 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
9422 {
9423 struct net_device *netdev = pci_get_drvdata(pdev);
9424 struct igb_adapter *adapter = netdev_priv(netdev);
9425 struct e1000_hw *hw = &adapter->hw;
9426 pci_ers_result_t result;
9427
9428 if (pci_enable_device_mem(pdev)) {
9429 dev_err(&pdev->dev,
9430 "Cannot re-enable PCI device after reset.\n");
9431 result = PCI_ERS_RESULT_DISCONNECT;
9432 } else {
9433 pci_set_master(pdev);
9434 pci_restore_state(pdev);
9435 pci_save_state(pdev);
9436
9437 pci_enable_wake(pdev, PCI_D3hot, 0);
9438 pci_enable_wake(pdev, PCI_D3cold, 0);
9439
9440 /* In case of PCI error, adapter lose its HW address
9441 * so we should re-assign it here.
9442 */
9443 hw->hw_addr = adapter->io_addr;
9444
9445 igb_reset(adapter);
9446 wr32(E1000_WUS, ~0);
9447 result = PCI_ERS_RESULT_RECOVERED;
9448 }
9449
9450 return result;
9451 }
9452
9453 /**
9454 * igb_io_resume - called when traffic can start flowing again.
9455 * @pdev: Pointer to PCI device
9456 *
9457 * This callback is called when the error recovery driver tells us that
9458 * its OK to resume normal operation. Implementation resembles the
9459 * second-half of the igb_resume routine.
9460 */
igb_io_resume(struct pci_dev * pdev)9461 static void igb_io_resume(struct pci_dev *pdev)
9462 {
9463 struct net_device *netdev = pci_get_drvdata(pdev);
9464 struct igb_adapter *adapter = netdev_priv(netdev);
9465
9466 if (netif_running(netdev)) {
9467 if (igb_up(adapter)) {
9468 dev_err(&pdev->dev, "igb_up failed after reset\n");
9469 return;
9470 }
9471 }
9472
9473 netif_device_attach(netdev);
9474
9475 /* let the f/w know that the h/w is now under the control of the
9476 * driver.
9477 */
9478 igb_get_hw_control(adapter);
9479 }
9480
9481 /**
9482 * igb_rar_set_index - Sync RAL[index] and RAH[index] registers with MAC table
9483 * @adapter: Pointer to adapter structure
9484 * @index: Index of the RAR entry which need to be synced with MAC table
9485 **/
igb_rar_set_index(struct igb_adapter * adapter,u32 index)9486 static void igb_rar_set_index(struct igb_adapter *adapter, u32 index)
9487 {
9488 struct e1000_hw *hw = &adapter->hw;
9489 u32 rar_low, rar_high;
9490 u8 *addr = adapter->mac_table[index].addr;
9491
9492 /* HW expects these to be in network order when they are plugged
9493 * into the registers which are little endian. In order to guarantee
9494 * that ordering we need to do an leXX_to_cpup here in order to be
9495 * ready for the byteswap that occurs with writel
9496 */
9497 rar_low = le32_to_cpup((__le32 *)(addr));
9498 rar_high = le16_to_cpup((__le16 *)(addr + 4));
9499
9500 /* Indicate to hardware the Address is Valid. */
9501 if (adapter->mac_table[index].state & IGB_MAC_STATE_IN_USE) {
9502 if (is_valid_ether_addr(addr))
9503 rar_high |= E1000_RAH_AV;
9504
9505 if (adapter->mac_table[index].state & IGB_MAC_STATE_SRC_ADDR)
9506 rar_high |= E1000_RAH_ASEL_SRC_ADDR;
9507
9508 switch (hw->mac.type) {
9509 case e1000_82575:
9510 case e1000_i210:
9511 if (adapter->mac_table[index].state &
9512 IGB_MAC_STATE_QUEUE_STEERING)
9513 rar_high |= E1000_RAH_QSEL_ENABLE;
9514
9515 rar_high |= E1000_RAH_POOL_1 *
9516 adapter->mac_table[index].queue;
9517 break;
9518 default:
9519 rar_high |= E1000_RAH_POOL_1 <<
9520 adapter->mac_table[index].queue;
9521 break;
9522 }
9523 }
9524
9525 wr32(E1000_RAL(index), rar_low);
9526 wrfl();
9527 wr32(E1000_RAH(index), rar_high);
9528 wrfl();
9529 }
9530
igb_set_vf_mac(struct igb_adapter * adapter,int vf,unsigned char * mac_addr)9531 static int igb_set_vf_mac(struct igb_adapter *adapter,
9532 int vf, unsigned char *mac_addr)
9533 {
9534 struct e1000_hw *hw = &adapter->hw;
9535 /* VF MAC addresses start at end of receive addresses and moves
9536 * towards the first, as a result a collision should not be possible
9537 */
9538 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
9539 unsigned char *vf_mac_addr = adapter->vf_data[vf].vf_mac_addresses;
9540
9541 ether_addr_copy(vf_mac_addr, mac_addr);
9542 ether_addr_copy(adapter->mac_table[rar_entry].addr, mac_addr);
9543 adapter->mac_table[rar_entry].queue = vf;
9544 adapter->mac_table[rar_entry].state |= IGB_MAC_STATE_IN_USE;
9545 igb_rar_set_index(adapter, rar_entry);
9546
9547 return 0;
9548 }
9549
igb_ndo_set_vf_mac(struct net_device * netdev,int vf,u8 * mac)9550 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
9551 {
9552 struct igb_adapter *adapter = netdev_priv(netdev);
9553
9554 if (vf >= adapter->vfs_allocated_count)
9555 return -EINVAL;
9556
9557 /* Setting the VF MAC to 0 reverts the IGB_VF_FLAG_PF_SET_MAC
9558 * flag and allows to overwrite the MAC via VF netdev. This
9559 * is necessary to allow libvirt a way to restore the original
9560 * MAC after unbinding vfio-pci and reloading igbvf after shutting
9561 * down a VM.
9562 */
9563 if (is_zero_ether_addr(mac)) {
9564 adapter->vf_data[vf].flags &= ~IGB_VF_FLAG_PF_SET_MAC;
9565 dev_info(&adapter->pdev->dev,
9566 "remove administratively set MAC on VF %d\n",
9567 vf);
9568 } else if (is_valid_ether_addr(mac)) {
9569 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
9570 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n",
9571 mac, vf);
9572 dev_info(&adapter->pdev->dev,
9573 "Reload the VF driver to make this change effective.");
9574 /* Generate additional warning if PF is down */
9575 if (test_bit(__IGB_DOWN, &adapter->state)) {
9576 dev_warn(&adapter->pdev->dev,
9577 "The VF MAC address has been set, but the PF device is not up.\n");
9578 dev_warn(&adapter->pdev->dev,
9579 "Bring the PF device up before attempting to use the VF device.\n");
9580 }
9581 } else {
9582 return -EINVAL;
9583 }
9584 return igb_set_vf_mac(adapter, vf, mac);
9585 }
9586
igb_link_mbps(int internal_link_speed)9587 static int igb_link_mbps(int internal_link_speed)
9588 {
9589 switch (internal_link_speed) {
9590 case SPEED_100:
9591 return 100;
9592 case SPEED_1000:
9593 return 1000;
9594 default:
9595 return 0;
9596 }
9597 }
9598
igb_set_vf_rate_limit(struct e1000_hw * hw,int vf,int tx_rate,int link_speed)9599 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
9600 int link_speed)
9601 {
9602 int rf_dec, rf_int;
9603 u32 bcnrc_val;
9604
9605 if (tx_rate != 0) {
9606 /* Calculate the rate factor values to set */
9607 rf_int = link_speed / tx_rate;
9608 rf_dec = (link_speed - (rf_int * tx_rate));
9609 rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) /
9610 tx_rate;
9611
9612 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
9613 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
9614 E1000_RTTBCNRC_RF_INT_MASK);
9615 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
9616 } else {
9617 bcnrc_val = 0;
9618 }
9619
9620 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
9621 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
9622 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
9623 */
9624 wr32(E1000_RTTBCNRM, 0x14);
9625 wr32(E1000_RTTBCNRC, bcnrc_val);
9626 }
9627
igb_check_vf_rate_limit(struct igb_adapter * adapter)9628 static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
9629 {
9630 int actual_link_speed, i;
9631 bool reset_rate = false;
9632
9633 /* VF TX rate limit was not set or not supported */
9634 if ((adapter->vf_rate_link_speed == 0) ||
9635 (adapter->hw.mac.type != e1000_82576))
9636 return;
9637
9638 actual_link_speed = igb_link_mbps(adapter->link_speed);
9639 if (actual_link_speed != adapter->vf_rate_link_speed) {
9640 reset_rate = true;
9641 adapter->vf_rate_link_speed = 0;
9642 dev_info(&adapter->pdev->dev,
9643 "Link speed has been changed. VF Transmit rate is disabled\n");
9644 }
9645
9646 for (i = 0; i < adapter->vfs_allocated_count; i++) {
9647 if (reset_rate)
9648 adapter->vf_data[i].tx_rate = 0;
9649
9650 igb_set_vf_rate_limit(&adapter->hw, i,
9651 adapter->vf_data[i].tx_rate,
9652 actual_link_speed);
9653 }
9654 }
9655
igb_ndo_set_vf_bw(struct net_device * netdev,int vf,int min_tx_rate,int max_tx_rate)9656 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf,
9657 int min_tx_rate, int max_tx_rate)
9658 {
9659 struct igb_adapter *adapter = netdev_priv(netdev);
9660 struct e1000_hw *hw = &adapter->hw;
9661 int actual_link_speed;
9662
9663 if (hw->mac.type != e1000_82576)
9664 return -EOPNOTSUPP;
9665
9666 if (min_tx_rate)
9667 return -EINVAL;
9668
9669 actual_link_speed = igb_link_mbps(adapter->link_speed);
9670 if ((vf >= adapter->vfs_allocated_count) ||
9671 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
9672 (max_tx_rate < 0) ||
9673 (max_tx_rate > actual_link_speed))
9674 return -EINVAL;
9675
9676 adapter->vf_rate_link_speed = actual_link_speed;
9677 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate;
9678 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed);
9679
9680 return 0;
9681 }
9682
igb_ndo_set_vf_spoofchk(struct net_device * netdev,int vf,bool setting)9683 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
9684 bool setting)
9685 {
9686 struct igb_adapter *adapter = netdev_priv(netdev);
9687 struct e1000_hw *hw = &adapter->hw;
9688 u32 reg_val, reg_offset;
9689
9690 if (!adapter->vfs_allocated_count)
9691 return -EOPNOTSUPP;
9692
9693 if (vf >= adapter->vfs_allocated_count)
9694 return -EINVAL;
9695
9696 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
9697 reg_val = rd32(reg_offset);
9698 if (setting)
9699 reg_val |= (BIT(vf) |
9700 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT));
9701 else
9702 reg_val &= ~(BIT(vf) |
9703 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT));
9704 wr32(reg_offset, reg_val);
9705
9706 adapter->vf_data[vf].spoofchk_enabled = setting;
9707 return 0;
9708 }
9709
igb_ndo_set_vf_trust(struct net_device * netdev,int vf,bool setting)9710 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, bool setting)
9711 {
9712 struct igb_adapter *adapter = netdev_priv(netdev);
9713
9714 if (vf >= adapter->vfs_allocated_count)
9715 return -EINVAL;
9716 if (adapter->vf_data[vf].trusted == setting)
9717 return 0;
9718
9719 adapter->vf_data[vf].trusted = setting;
9720
9721 dev_info(&adapter->pdev->dev, "VF %u is %strusted\n",
9722 vf, setting ? "" : "not ");
9723 return 0;
9724 }
9725
igb_ndo_get_vf_config(struct net_device * netdev,int vf,struct ifla_vf_info * ivi)9726 static int igb_ndo_get_vf_config(struct net_device *netdev,
9727 int vf, struct ifla_vf_info *ivi)
9728 {
9729 struct igb_adapter *adapter = netdev_priv(netdev);
9730 if (vf >= adapter->vfs_allocated_count)
9731 return -EINVAL;
9732 ivi->vf = vf;
9733 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
9734 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate;
9735 ivi->min_tx_rate = 0;
9736 ivi->vlan = adapter->vf_data[vf].pf_vlan;
9737 ivi->qos = adapter->vf_data[vf].pf_qos;
9738 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
9739 ivi->trusted = adapter->vf_data[vf].trusted;
9740 return 0;
9741 }
9742
igb_vmm_control(struct igb_adapter * adapter)9743 static void igb_vmm_control(struct igb_adapter *adapter)
9744 {
9745 struct e1000_hw *hw = &adapter->hw;
9746 u32 reg;
9747
9748 switch (hw->mac.type) {
9749 case e1000_82575:
9750 case e1000_i210:
9751 case e1000_i211:
9752 case e1000_i354:
9753 default:
9754 /* replication is not supported for 82575 */
9755 return;
9756 case e1000_82576:
9757 /* notify HW that the MAC is adding vlan tags */
9758 reg = rd32(E1000_DTXCTL);
9759 reg |= E1000_DTXCTL_VLAN_ADDED;
9760 wr32(E1000_DTXCTL, reg);
9761 fallthrough;
9762 case e1000_82580:
9763 /* enable replication vlan tag stripping */
9764 reg = rd32(E1000_RPLOLR);
9765 reg |= E1000_RPLOLR_STRVLAN;
9766 wr32(E1000_RPLOLR, reg);
9767 fallthrough;
9768 case e1000_i350:
9769 /* none of the above registers are supported by i350 */
9770 break;
9771 }
9772
9773 if (adapter->vfs_allocated_count) {
9774 igb_vmdq_set_loopback_pf(hw, true);
9775 igb_vmdq_set_replication_pf(hw, true);
9776 igb_vmdq_set_anti_spoofing_pf(hw, true,
9777 adapter->vfs_allocated_count);
9778 } else {
9779 igb_vmdq_set_loopback_pf(hw, false);
9780 igb_vmdq_set_replication_pf(hw, false);
9781 }
9782 }
9783
igb_init_dmac(struct igb_adapter * adapter,u32 pba)9784 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
9785 {
9786 struct e1000_hw *hw = &adapter->hw;
9787 u32 dmac_thr;
9788 u16 hwm;
9789
9790 if (hw->mac.type > e1000_82580) {
9791 if (adapter->flags & IGB_FLAG_DMAC) {
9792 u32 reg;
9793
9794 /* force threshold to 0. */
9795 wr32(E1000_DMCTXTH, 0);
9796
9797 /* DMA Coalescing high water mark needs to be greater
9798 * than the Rx threshold. Set hwm to PBA - max frame
9799 * size in 16B units, capping it at PBA - 6KB.
9800 */
9801 hwm = 64 * (pba - 6);
9802 reg = rd32(E1000_FCRTC);
9803 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
9804 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
9805 & E1000_FCRTC_RTH_COAL_MASK);
9806 wr32(E1000_FCRTC, reg);
9807
9808 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
9809 * frame size, capping it at PBA - 10KB.
9810 */
9811 dmac_thr = pba - 10;
9812 reg = rd32(E1000_DMACR);
9813 reg &= ~E1000_DMACR_DMACTHR_MASK;
9814 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
9815 & E1000_DMACR_DMACTHR_MASK);
9816
9817 /* transition to L0x or L1 if available..*/
9818 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
9819
9820 /* watchdog timer= +-1000 usec in 32usec intervals */
9821 reg |= (1000 >> 5);
9822
9823 /* Disable BMC-to-OS Watchdog Enable */
9824 if (hw->mac.type != e1000_i354)
9825 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
9826
9827 wr32(E1000_DMACR, reg);
9828
9829 /* no lower threshold to disable
9830 * coalescing(smart fifb)-UTRESH=0
9831 */
9832 wr32(E1000_DMCRTRH, 0);
9833
9834 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
9835
9836 wr32(E1000_DMCTLX, reg);
9837
9838 /* free space in tx packet buffer to wake from
9839 * DMA coal
9840 */
9841 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
9842 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
9843
9844 /* make low power state decision controlled
9845 * by DMA coal
9846 */
9847 reg = rd32(E1000_PCIEMISC);
9848 reg &= ~E1000_PCIEMISC_LX_DECISION;
9849 wr32(E1000_PCIEMISC, reg);
9850 } /* endif adapter->dmac is not disabled */
9851 } else if (hw->mac.type == e1000_82580) {
9852 u32 reg = rd32(E1000_PCIEMISC);
9853
9854 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
9855 wr32(E1000_DMACR, 0);
9856 }
9857 }
9858
9859 /**
9860 * igb_read_i2c_byte - Reads 8 bit word over I2C
9861 * @hw: pointer to hardware structure
9862 * @byte_offset: byte offset to read
9863 * @dev_addr: device address
9864 * @data: value read
9865 *
9866 * Performs byte read operation over I2C interface at
9867 * a specified device address.
9868 **/
igb_read_i2c_byte(struct e1000_hw * hw,u8 byte_offset,u8 dev_addr,u8 * data)9869 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
9870 u8 dev_addr, u8 *data)
9871 {
9872 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
9873 struct i2c_client *this_client = adapter->i2c_client;
9874 s32 status;
9875 u16 swfw_mask = 0;
9876
9877 if (!this_client)
9878 return E1000_ERR_I2C;
9879
9880 swfw_mask = E1000_SWFW_PHY0_SM;
9881
9882 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
9883 return E1000_ERR_SWFW_SYNC;
9884
9885 status = i2c_smbus_read_byte_data(this_client, byte_offset);
9886 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
9887
9888 if (status < 0)
9889 return E1000_ERR_I2C;
9890 else {
9891 *data = status;
9892 return 0;
9893 }
9894 }
9895
9896 /**
9897 * igb_write_i2c_byte - Writes 8 bit word over I2C
9898 * @hw: pointer to hardware structure
9899 * @byte_offset: byte offset to write
9900 * @dev_addr: device address
9901 * @data: value to write
9902 *
9903 * Performs byte write operation over I2C interface at
9904 * a specified device address.
9905 **/
igb_write_i2c_byte(struct e1000_hw * hw,u8 byte_offset,u8 dev_addr,u8 data)9906 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
9907 u8 dev_addr, u8 data)
9908 {
9909 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
9910 struct i2c_client *this_client = adapter->i2c_client;
9911 s32 status;
9912 u16 swfw_mask = E1000_SWFW_PHY0_SM;
9913
9914 if (!this_client)
9915 return E1000_ERR_I2C;
9916
9917 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
9918 return E1000_ERR_SWFW_SYNC;
9919 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
9920 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
9921
9922 if (status)
9923 return E1000_ERR_I2C;
9924 else
9925 return 0;
9926
9927 }
9928
igb_reinit_queues(struct igb_adapter * adapter)9929 int igb_reinit_queues(struct igb_adapter *adapter)
9930 {
9931 struct net_device *netdev = adapter->netdev;
9932 struct pci_dev *pdev = adapter->pdev;
9933 int err = 0;
9934
9935 if (netif_running(netdev))
9936 igb_close(netdev);
9937
9938 igb_reset_interrupt_capability(adapter);
9939
9940 if (igb_init_interrupt_scheme(adapter, true)) {
9941 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
9942 return -ENOMEM;
9943 }
9944
9945 if (netif_running(netdev))
9946 err = igb_open(netdev);
9947
9948 return err;
9949 }
9950
igb_nfc_filter_exit(struct igb_adapter * adapter)9951 static void igb_nfc_filter_exit(struct igb_adapter *adapter)
9952 {
9953 struct igb_nfc_filter *rule;
9954
9955 spin_lock(&adapter->nfc_lock);
9956
9957 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node)
9958 igb_erase_filter(adapter, rule);
9959
9960 hlist_for_each_entry(rule, &adapter->cls_flower_list, nfc_node)
9961 igb_erase_filter(adapter, rule);
9962
9963 spin_unlock(&adapter->nfc_lock);
9964 }
9965
igb_nfc_filter_restore(struct igb_adapter * adapter)9966 static void igb_nfc_filter_restore(struct igb_adapter *adapter)
9967 {
9968 struct igb_nfc_filter *rule;
9969
9970 spin_lock(&adapter->nfc_lock);
9971
9972 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node)
9973 igb_add_filter(adapter, rule);
9974
9975 spin_unlock(&adapter->nfc_lock);
9976 }
9977 /* igb_main.c */
9978