1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * AMx3 Wkup M3 IPC driver
4 *
5 * Copyright (C) 2015 Texas Instruments, Inc.
6 *
7 * Dave Gerlach <d-gerlach@ti.com>
8 */
9
10 #include <linux/err.h>
11 #include <linux/kernel.h>
12 #include <linux/kthread.h>
13 #include <linux/interrupt.h>
14 #include <linux/irq.h>
15 #include <linux/module.h>
16 #include <linux/of.h>
17 #include <linux/omap-mailbox.h>
18 #include <linux/platform_device.h>
19 #include <linux/remoteproc.h>
20 #include <linux/suspend.h>
21 #include <linux/wkup_m3_ipc.h>
22
23 #define AM33XX_CTRL_IPC_REG_COUNT 0x8
24 #define AM33XX_CTRL_IPC_REG_OFFSET(m) (0x4 + 4 * (m))
25
26 /* AM33XX M3_TXEV_EOI register */
27 #define AM33XX_CONTROL_M3_TXEV_EOI 0x00
28
29 #define AM33XX_M3_TXEV_ACK (0x1 << 0)
30 #define AM33XX_M3_TXEV_ENABLE (0x0 << 0)
31
32 #define IPC_CMD_DS0 0x4
33 #define IPC_CMD_STANDBY 0xc
34 #define IPC_CMD_IDLE 0x10
35 #define IPC_CMD_RESET 0xe
36 #define DS_IPC_DEFAULT 0xffffffff
37 #define M3_VERSION_UNKNOWN 0x0000ffff
38 #define M3_BASELINE_VERSION 0x191
39 #define M3_STATUS_RESP_MASK (0xffff << 16)
40 #define M3_FW_VERSION_MASK 0xffff
41 #define M3_WAKE_SRC_MASK 0xff
42
43 #define M3_STATE_UNKNOWN 0
44 #define M3_STATE_RESET 1
45 #define M3_STATE_INITED 2
46 #define M3_STATE_MSG_FOR_LP 3
47 #define M3_STATE_MSG_FOR_RESET 4
48
49 static struct wkup_m3_ipc *m3_ipc_state;
50
51 static const struct wkup_m3_wakeup_src wakeups[] = {
52 {.irq_nr = 16, .src = "PRCM"},
53 {.irq_nr = 35, .src = "USB0_PHY"},
54 {.irq_nr = 36, .src = "USB1_PHY"},
55 {.irq_nr = 40, .src = "I2C0"},
56 {.irq_nr = 41, .src = "RTC Timer"},
57 {.irq_nr = 42, .src = "RTC Alarm"},
58 {.irq_nr = 43, .src = "Timer0"},
59 {.irq_nr = 44, .src = "Timer1"},
60 {.irq_nr = 45, .src = "UART"},
61 {.irq_nr = 46, .src = "GPIO0"},
62 {.irq_nr = 48, .src = "MPU_WAKE"},
63 {.irq_nr = 49, .src = "WDT0"},
64 {.irq_nr = 50, .src = "WDT1"},
65 {.irq_nr = 51, .src = "ADC_TSC"},
66 {.irq_nr = 0, .src = "Unknown"},
67 };
68
am33xx_txev_eoi(struct wkup_m3_ipc * m3_ipc)69 static void am33xx_txev_eoi(struct wkup_m3_ipc *m3_ipc)
70 {
71 writel(AM33XX_M3_TXEV_ACK,
72 m3_ipc->ipc_mem_base + AM33XX_CONTROL_M3_TXEV_EOI);
73 }
74
am33xx_txev_enable(struct wkup_m3_ipc * m3_ipc)75 static void am33xx_txev_enable(struct wkup_m3_ipc *m3_ipc)
76 {
77 writel(AM33XX_M3_TXEV_ENABLE,
78 m3_ipc->ipc_mem_base + AM33XX_CONTROL_M3_TXEV_EOI);
79 }
80
wkup_m3_ctrl_ipc_write(struct wkup_m3_ipc * m3_ipc,u32 val,int ipc_reg_num)81 static void wkup_m3_ctrl_ipc_write(struct wkup_m3_ipc *m3_ipc,
82 u32 val, int ipc_reg_num)
83 {
84 if (WARN(ipc_reg_num < 0 || ipc_reg_num > AM33XX_CTRL_IPC_REG_COUNT,
85 "ipc register operation out of range"))
86 return;
87
88 writel(val, m3_ipc->ipc_mem_base +
89 AM33XX_CTRL_IPC_REG_OFFSET(ipc_reg_num));
90 }
91
wkup_m3_ctrl_ipc_read(struct wkup_m3_ipc * m3_ipc,int ipc_reg_num)92 static unsigned int wkup_m3_ctrl_ipc_read(struct wkup_m3_ipc *m3_ipc,
93 int ipc_reg_num)
94 {
95 if (WARN(ipc_reg_num < 0 || ipc_reg_num > AM33XX_CTRL_IPC_REG_COUNT,
96 "ipc register operation out of range"))
97 return 0;
98
99 return readl(m3_ipc->ipc_mem_base +
100 AM33XX_CTRL_IPC_REG_OFFSET(ipc_reg_num));
101 }
102
wkup_m3_fw_version_read(struct wkup_m3_ipc * m3_ipc)103 static int wkup_m3_fw_version_read(struct wkup_m3_ipc *m3_ipc)
104 {
105 int val;
106
107 val = wkup_m3_ctrl_ipc_read(m3_ipc, 2);
108
109 return val & M3_FW_VERSION_MASK;
110 }
111
wkup_m3_txev_handler(int irq,void * ipc_data)112 static irqreturn_t wkup_m3_txev_handler(int irq, void *ipc_data)
113 {
114 struct wkup_m3_ipc *m3_ipc = ipc_data;
115 struct device *dev = m3_ipc->dev;
116 int ver = 0;
117
118 am33xx_txev_eoi(m3_ipc);
119
120 switch (m3_ipc->state) {
121 case M3_STATE_RESET:
122 ver = wkup_m3_fw_version_read(m3_ipc);
123
124 if (ver == M3_VERSION_UNKNOWN ||
125 ver < M3_BASELINE_VERSION) {
126 dev_warn(dev, "CM3 Firmware Version %x not supported\n",
127 ver);
128 } else {
129 dev_info(dev, "CM3 Firmware Version = 0x%x\n", ver);
130 }
131
132 m3_ipc->state = M3_STATE_INITED;
133 complete(&m3_ipc->sync_complete);
134 break;
135 case M3_STATE_MSG_FOR_RESET:
136 m3_ipc->state = M3_STATE_INITED;
137 complete(&m3_ipc->sync_complete);
138 break;
139 case M3_STATE_MSG_FOR_LP:
140 complete(&m3_ipc->sync_complete);
141 break;
142 case M3_STATE_UNKNOWN:
143 dev_warn(dev, "Unknown CM3 State\n");
144 }
145
146 am33xx_txev_enable(m3_ipc);
147
148 return IRQ_HANDLED;
149 }
150
wkup_m3_ping(struct wkup_m3_ipc * m3_ipc)151 static int wkup_m3_ping(struct wkup_m3_ipc *m3_ipc)
152 {
153 struct device *dev = m3_ipc->dev;
154 mbox_msg_t dummy_msg = 0;
155 int ret;
156
157 if (!m3_ipc->mbox) {
158 dev_err(dev,
159 "No IPC channel to communicate with wkup_m3!\n");
160 return -EIO;
161 }
162
163 /*
164 * Write a dummy message to the mailbox in order to trigger the RX
165 * interrupt to alert the M3 that data is available in the IPC
166 * registers. We must enable the IRQ here and disable it after in
167 * the RX callback to avoid multiple interrupts being received
168 * by the CM3.
169 */
170 ret = mbox_send_message(m3_ipc->mbox, &dummy_msg);
171 if (ret < 0) {
172 dev_err(dev, "%s: mbox_send_message() failed: %d\n",
173 __func__, ret);
174 return ret;
175 }
176
177 ret = wait_for_completion_timeout(&m3_ipc->sync_complete,
178 msecs_to_jiffies(500));
179 if (!ret) {
180 dev_err(dev, "MPU<->CM3 sync failure\n");
181 m3_ipc->state = M3_STATE_UNKNOWN;
182 return -EIO;
183 }
184
185 mbox_client_txdone(m3_ipc->mbox, 0);
186 return 0;
187 }
188
wkup_m3_ping_noirq(struct wkup_m3_ipc * m3_ipc)189 static int wkup_m3_ping_noirq(struct wkup_m3_ipc *m3_ipc)
190 {
191 struct device *dev = m3_ipc->dev;
192 mbox_msg_t dummy_msg = 0;
193 int ret;
194
195 if (!m3_ipc->mbox) {
196 dev_err(dev,
197 "No IPC channel to communicate with wkup_m3!\n");
198 return -EIO;
199 }
200
201 ret = mbox_send_message(m3_ipc->mbox, &dummy_msg);
202 if (ret < 0) {
203 dev_err(dev, "%s: mbox_send_message() failed: %d\n",
204 __func__, ret);
205 return ret;
206 }
207
208 mbox_client_txdone(m3_ipc->mbox, 0);
209 return 0;
210 }
211
wkup_m3_is_available(struct wkup_m3_ipc * m3_ipc)212 static int wkup_m3_is_available(struct wkup_m3_ipc *m3_ipc)
213 {
214 return ((m3_ipc->state != M3_STATE_RESET) &&
215 (m3_ipc->state != M3_STATE_UNKNOWN));
216 }
217
218 /* Public functions */
219 /**
220 * wkup_m3_set_mem_type - Pass wkup_m3 which type of memory is in use
221 * @m3_ipc: Pointer to wkup_m3_ipc context
222 * @mem_type: memory type value read directly from emif
223 *
224 * wkup_m3 must know what memory type is in use to properly suspend
225 * and resume.
226 */
wkup_m3_set_mem_type(struct wkup_m3_ipc * m3_ipc,int mem_type)227 static void wkup_m3_set_mem_type(struct wkup_m3_ipc *m3_ipc, int mem_type)
228 {
229 m3_ipc->mem_type = mem_type;
230 }
231
232 /**
233 * wkup_m3_set_resume_address - Pass wkup_m3 resume address
234 * @m3_ipc: Pointer to wkup_m3_ipc context
235 * @addr: Physical address from which resume code should execute
236 */
wkup_m3_set_resume_address(struct wkup_m3_ipc * m3_ipc,void * addr)237 static void wkup_m3_set_resume_address(struct wkup_m3_ipc *m3_ipc, void *addr)
238 {
239 m3_ipc->resume_addr = (unsigned long)addr;
240 }
241
242 /**
243 * wkup_m3_request_pm_status - Retrieve wkup_m3 status code after suspend
244 * @m3_ipc: Pointer to wkup_m3_ipc context
245 *
246 * Returns code representing the status of a low power mode transition.
247 * 0 - Successful transition
248 * 1 - Failure to transition to low power state
249 */
wkup_m3_request_pm_status(struct wkup_m3_ipc * m3_ipc)250 static int wkup_m3_request_pm_status(struct wkup_m3_ipc *m3_ipc)
251 {
252 unsigned int i;
253 int val;
254
255 val = wkup_m3_ctrl_ipc_read(m3_ipc, 1);
256
257 i = M3_STATUS_RESP_MASK & val;
258 i >>= __ffs(M3_STATUS_RESP_MASK);
259
260 return i;
261 }
262
263 /**
264 * wkup_m3_prepare_low_power - Request preparation for transition to
265 * low power state
266 * @m3_ipc: Pointer to wkup_m3_ipc context
267 * @state: A kernel suspend state to enter, either MEM or STANDBY
268 *
269 * Returns 0 if preparation was successful, otherwise returns error code
270 */
wkup_m3_prepare_low_power(struct wkup_m3_ipc * m3_ipc,int state)271 static int wkup_m3_prepare_low_power(struct wkup_m3_ipc *m3_ipc, int state)
272 {
273 struct device *dev = m3_ipc->dev;
274 int m3_power_state;
275 int ret = 0;
276
277 if (!wkup_m3_is_available(m3_ipc))
278 return -ENODEV;
279
280 switch (state) {
281 case WKUP_M3_DEEPSLEEP:
282 m3_power_state = IPC_CMD_DS0;
283 break;
284 case WKUP_M3_STANDBY:
285 m3_power_state = IPC_CMD_STANDBY;
286 break;
287 case WKUP_M3_IDLE:
288 m3_power_state = IPC_CMD_IDLE;
289 break;
290 default:
291 return 1;
292 }
293
294 /* Program each required IPC register then write defaults to others */
295 wkup_m3_ctrl_ipc_write(m3_ipc, m3_ipc->resume_addr, 0);
296 wkup_m3_ctrl_ipc_write(m3_ipc, m3_power_state, 1);
297 wkup_m3_ctrl_ipc_write(m3_ipc, m3_ipc->mem_type, 4);
298
299 wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 2);
300 wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 3);
301 wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 5);
302 wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 6);
303 wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 7);
304
305 m3_ipc->state = M3_STATE_MSG_FOR_LP;
306
307 if (state == WKUP_M3_IDLE)
308 ret = wkup_m3_ping_noirq(m3_ipc);
309 else
310 ret = wkup_m3_ping(m3_ipc);
311
312 if (ret) {
313 dev_err(dev, "Unable to ping CM3\n");
314 return ret;
315 }
316
317 return 0;
318 }
319
320 /**
321 * wkup_m3_finish_low_power - Return m3 to reset state
322 * @m3_ipc: Pointer to wkup_m3_ipc context
323 *
324 * Returns 0 if reset was successful, otherwise returns error code
325 */
wkup_m3_finish_low_power(struct wkup_m3_ipc * m3_ipc)326 static int wkup_m3_finish_low_power(struct wkup_m3_ipc *m3_ipc)
327 {
328 struct device *dev = m3_ipc->dev;
329 int ret = 0;
330
331 if (!wkup_m3_is_available(m3_ipc))
332 return -ENODEV;
333
334 wkup_m3_ctrl_ipc_write(m3_ipc, IPC_CMD_RESET, 1);
335 wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 2);
336
337 m3_ipc->state = M3_STATE_MSG_FOR_RESET;
338
339 ret = wkup_m3_ping(m3_ipc);
340 if (ret) {
341 dev_err(dev, "Unable to ping CM3\n");
342 return ret;
343 }
344
345 return 0;
346 }
347
348 /**
349 * wkup_m3_request_wake_src - Get the wakeup source info passed from wkup_m3
350 * @m3_ipc: Pointer to wkup_m3_ipc context
351 */
wkup_m3_request_wake_src(struct wkup_m3_ipc * m3_ipc)352 static const char *wkup_m3_request_wake_src(struct wkup_m3_ipc *m3_ipc)
353 {
354 unsigned int wakeup_src_idx;
355 int j, val;
356
357 val = wkup_m3_ctrl_ipc_read(m3_ipc, 6);
358
359 wakeup_src_idx = val & M3_WAKE_SRC_MASK;
360
361 for (j = 0; j < ARRAY_SIZE(wakeups) - 1; j++) {
362 if (wakeups[j].irq_nr == wakeup_src_idx)
363 return wakeups[j].src;
364 }
365 return wakeups[j].src;
366 }
367
368 /**
369 * wkup_m3_set_rtc_only - Set the rtc_only flag
370 * @m3_ipc: Pointer to wkup_m3_ipc context
371 */
wkup_m3_set_rtc_only(struct wkup_m3_ipc * m3_ipc)372 static void wkup_m3_set_rtc_only(struct wkup_m3_ipc *m3_ipc)
373 {
374 if (m3_ipc_state)
375 m3_ipc_state->is_rtc_only = true;
376 }
377
378 static struct wkup_m3_ipc_ops ipc_ops = {
379 .set_mem_type = wkup_m3_set_mem_type,
380 .set_resume_address = wkup_m3_set_resume_address,
381 .prepare_low_power = wkup_m3_prepare_low_power,
382 .finish_low_power = wkup_m3_finish_low_power,
383 .request_pm_status = wkup_m3_request_pm_status,
384 .request_wake_src = wkup_m3_request_wake_src,
385 .set_rtc_only = wkup_m3_set_rtc_only,
386 };
387
388 /**
389 * wkup_m3_ipc_get - Return handle to wkup_m3_ipc
390 *
391 * Returns NULL if the wkup_m3 is not yet available, otherwise returns
392 * pointer to wkup_m3_ipc struct.
393 */
wkup_m3_ipc_get(void)394 struct wkup_m3_ipc *wkup_m3_ipc_get(void)
395 {
396 if (m3_ipc_state)
397 get_device(m3_ipc_state->dev);
398 else
399 return NULL;
400
401 return m3_ipc_state;
402 }
403 EXPORT_SYMBOL_GPL(wkup_m3_ipc_get);
404
405 /**
406 * wkup_m3_ipc_put - Free handle to wkup_m3_ipc returned from wkup_m3_ipc_get
407 * @m3_ipc: A pointer to wkup_m3_ipc struct returned by wkup_m3_ipc_get
408 */
wkup_m3_ipc_put(struct wkup_m3_ipc * m3_ipc)409 void wkup_m3_ipc_put(struct wkup_m3_ipc *m3_ipc)
410 {
411 if (m3_ipc_state)
412 put_device(m3_ipc_state->dev);
413 }
414 EXPORT_SYMBOL_GPL(wkup_m3_ipc_put);
415
wkup_m3_rproc_boot_thread(struct wkup_m3_ipc * m3_ipc)416 static void wkup_m3_rproc_boot_thread(struct wkup_m3_ipc *m3_ipc)
417 {
418 struct device *dev = m3_ipc->dev;
419 int ret;
420
421 init_completion(&m3_ipc->sync_complete);
422
423 ret = rproc_boot(m3_ipc->rproc);
424 if (ret)
425 dev_err(dev, "rproc_boot failed\n");
426 else
427 m3_ipc_state = m3_ipc;
428
429 do_exit(0);
430 }
431
wkup_m3_ipc_probe(struct platform_device * pdev)432 static int wkup_m3_ipc_probe(struct platform_device *pdev)
433 {
434 struct device *dev = &pdev->dev;
435 int irq, ret;
436 phandle rproc_phandle;
437 struct rproc *m3_rproc;
438 struct resource *res;
439 struct task_struct *task;
440 struct wkup_m3_ipc *m3_ipc;
441
442 m3_ipc = devm_kzalloc(dev, sizeof(*m3_ipc), GFP_KERNEL);
443 if (!m3_ipc)
444 return -ENOMEM;
445
446 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
447 m3_ipc->ipc_mem_base = devm_ioremap_resource(dev, res);
448 if (IS_ERR(m3_ipc->ipc_mem_base)) {
449 dev_err(dev, "could not ioremap ipc_mem\n");
450 return PTR_ERR(m3_ipc->ipc_mem_base);
451 }
452
453 irq = platform_get_irq(pdev, 0);
454 if (!irq) {
455 dev_err(&pdev->dev, "no irq resource\n");
456 return -ENXIO;
457 }
458
459 ret = devm_request_irq(dev, irq, wkup_m3_txev_handler,
460 0, "wkup_m3_txev", m3_ipc);
461 if (ret) {
462 dev_err(dev, "request_irq failed\n");
463 return ret;
464 }
465
466 m3_ipc->mbox_client.dev = dev;
467 m3_ipc->mbox_client.tx_done = NULL;
468 m3_ipc->mbox_client.tx_prepare = NULL;
469 m3_ipc->mbox_client.rx_callback = NULL;
470 m3_ipc->mbox_client.tx_block = false;
471 m3_ipc->mbox_client.knows_txdone = false;
472
473 m3_ipc->mbox = mbox_request_channel(&m3_ipc->mbox_client, 0);
474
475 if (IS_ERR(m3_ipc->mbox)) {
476 dev_err(dev, "IPC Request for A8->M3 Channel failed! %ld\n",
477 PTR_ERR(m3_ipc->mbox));
478 return PTR_ERR(m3_ipc->mbox);
479 }
480
481 if (of_property_read_u32(dev->of_node, "ti,rproc", &rproc_phandle)) {
482 dev_err(&pdev->dev, "could not get rproc phandle\n");
483 ret = -ENODEV;
484 goto err_free_mbox;
485 }
486
487 m3_rproc = rproc_get_by_phandle(rproc_phandle);
488 if (!m3_rproc) {
489 dev_err(&pdev->dev, "could not get rproc handle\n");
490 ret = -EPROBE_DEFER;
491 goto err_free_mbox;
492 }
493
494 m3_ipc->rproc = m3_rproc;
495 m3_ipc->dev = dev;
496 m3_ipc->state = M3_STATE_RESET;
497
498 m3_ipc->ops = &ipc_ops;
499
500 /*
501 * Wait for firmware loading completion in a thread so we
502 * can boot the wkup_m3 as soon as it's ready without holding
503 * up kernel boot
504 */
505 task = kthread_run((void *)wkup_m3_rproc_boot_thread, m3_ipc,
506 "wkup_m3_rproc_loader");
507
508 if (IS_ERR(task)) {
509 dev_err(dev, "can't create rproc_boot thread\n");
510 ret = PTR_ERR(task);
511 goto err_put_rproc;
512 }
513
514 return 0;
515
516 err_put_rproc:
517 rproc_put(m3_rproc);
518 err_free_mbox:
519 mbox_free_channel(m3_ipc->mbox);
520 return ret;
521 }
522
wkup_m3_ipc_remove(struct platform_device * pdev)523 static int wkup_m3_ipc_remove(struct platform_device *pdev)
524 {
525 mbox_free_channel(m3_ipc_state->mbox);
526
527 rproc_shutdown(m3_ipc_state->rproc);
528 rproc_put(m3_ipc_state->rproc);
529
530 m3_ipc_state = NULL;
531
532 return 0;
533 }
534
wkup_m3_ipc_suspend(struct device * dev)535 static int __maybe_unused wkup_m3_ipc_suspend(struct device *dev)
536 {
537 /*
538 * Nothing needs to be done on suspend even with rtc_only flag set
539 */
540 return 0;
541 }
542
wkup_m3_ipc_resume(struct device * dev)543 static int __maybe_unused wkup_m3_ipc_resume(struct device *dev)
544 {
545 if (m3_ipc_state->is_rtc_only) {
546 rproc_shutdown(m3_ipc_state->rproc);
547 rproc_boot(m3_ipc_state->rproc);
548 }
549
550 m3_ipc_state->is_rtc_only = false;
551
552 return 0;
553 }
554
555 static const struct dev_pm_ops wkup_m3_ipc_pm_ops = {
556 SET_SYSTEM_SLEEP_PM_OPS(wkup_m3_ipc_suspend, wkup_m3_ipc_resume)
557 };
558
559 static const struct of_device_id wkup_m3_ipc_of_match[] = {
560 { .compatible = "ti,am3352-wkup-m3-ipc", },
561 { .compatible = "ti,am4372-wkup-m3-ipc", },
562 {},
563 };
564 MODULE_DEVICE_TABLE(of, wkup_m3_ipc_of_match);
565
566 static struct platform_driver wkup_m3_ipc_driver = {
567 .probe = wkup_m3_ipc_probe,
568 .remove = wkup_m3_ipc_remove,
569 .driver = {
570 .name = "wkup_m3_ipc",
571 .of_match_table = wkup_m3_ipc_of_match,
572 .pm = &wkup_m3_ipc_pm_ops,
573 },
574 };
575
576 module_platform_driver(wkup_m3_ipc_driver);
577
578 MODULE_LICENSE("GPL v2");
579 MODULE_DESCRIPTION("wkup m3 remote processor ipc driver");
580 MODULE_AUTHOR("Dave Gerlach <d-gerlach@ti.com>");
581