1 /* SPDX-License-Identifier: GPL-2.0-or-later
2 *
3 * Copyright (C) 2005 David Brownell
4 */
5
6 #ifndef __LINUX_SPI_H
7 #define __LINUX_SPI_H
8
9 #include <linux/bits.h>
10 #include <linux/device.h>
11 #include <linux/mod_devicetable.h>
12 #include <linux/slab.h>
13 #include <linux/kthread.h>
14 #include <linux/completion.h>
15 #include <linux/scatterlist.h>
16 #include <linux/gpio/consumer.h>
17 #include <linux/ptp_clock_kernel.h>
18
19 #include <uapi/linux/spi/spi.h>
20
21 struct dma_chan;
22 struct software_node;
23 struct spi_controller;
24 struct spi_transfer;
25 struct spi_controller_mem_ops;
26
27 /*
28 * INTERFACES between SPI master-side drivers and SPI slave protocol handlers,
29 * and SPI infrastructure.
30 */
31 extern struct bus_type spi_bus_type;
32
33 /**
34 * struct spi_statistics - statistics for spi transfers
35 * @lock: lock protecting this structure
36 *
37 * @messages: number of spi-messages handled
38 * @transfers: number of spi_transfers handled
39 * @errors: number of errors during spi_transfer
40 * @timedout: number of timeouts during spi_transfer
41 *
42 * @spi_sync: number of times spi_sync is used
43 * @spi_sync_immediate:
44 * number of times spi_sync is executed immediately
45 * in calling context without queuing and scheduling
46 * @spi_async: number of times spi_async is used
47 *
48 * @bytes: number of bytes transferred to/from device
49 * @bytes_tx: number of bytes sent to device
50 * @bytes_rx: number of bytes received from device
51 *
52 * @transfer_bytes_histo:
53 * transfer bytes histogramm
54 *
55 * @transfers_split_maxsize:
56 * number of transfers that have been split because of
57 * maxsize limit
58 */
59 struct spi_statistics {
60 spinlock_t lock; /* lock for the whole structure */
61
62 unsigned long messages;
63 unsigned long transfers;
64 unsigned long errors;
65 unsigned long timedout;
66
67 unsigned long spi_sync;
68 unsigned long spi_sync_immediate;
69 unsigned long spi_async;
70
71 unsigned long long bytes;
72 unsigned long long bytes_rx;
73 unsigned long long bytes_tx;
74
75 #define SPI_STATISTICS_HISTO_SIZE 17
76 unsigned long transfer_bytes_histo[SPI_STATISTICS_HISTO_SIZE];
77
78 unsigned long transfers_split_maxsize;
79 };
80
81 void spi_statistics_add_transfer_stats(struct spi_statistics *stats,
82 struct spi_transfer *xfer,
83 struct spi_controller *ctlr);
84
85 #define SPI_STATISTICS_ADD_TO_FIELD(stats, field, count) \
86 do { \
87 unsigned long flags; \
88 spin_lock_irqsave(&(stats)->lock, flags); \
89 (stats)->field += count; \
90 spin_unlock_irqrestore(&(stats)->lock, flags); \
91 } while (0)
92
93 #define SPI_STATISTICS_INCREMENT_FIELD(stats, field) \
94 SPI_STATISTICS_ADD_TO_FIELD(stats, field, 1)
95
96 /**
97 * struct spi_delay - SPI delay information
98 * @value: Value for the delay
99 * @unit: Unit for the delay
100 */
101 struct spi_delay {
102 #define SPI_DELAY_UNIT_USECS 0
103 #define SPI_DELAY_UNIT_NSECS 1
104 #define SPI_DELAY_UNIT_SCK 2
105 u16 value;
106 u8 unit;
107 };
108
109 extern int spi_delay_to_ns(struct spi_delay *_delay, struct spi_transfer *xfer);
110 extern int spi_delay_exec(struct spi_delay *_delay, struct spi_transfer *xfer);
111
112 /**
113 * struct spi_device - Controller side proxy for an SPI slave device
114 * @dev: Driver model representation of the device.
115 * @controller: SPI controller used with the device.
116 * @master: Copy of controller, for backwards compatibility.
117 * @max_speed_hz: Maximum clock rate to be used with this chip
118 * (on this board); may be changed by the device's driver.
119 * The spi_transfer.speed_hz can override this for each transfer.
120 * @chip_select: Chipselect, distinguishing chips handled by @controller.
121 * @mode: The spi mode defines how data is clocked out and in.
122 * This may be changed by the device's driver.
123 * The "active low" default for chipselect mode can be overridden
124 * (by specifying SPI_CS_HIGH) as can the "MSB first" default for
125 * each word in a transfer (by specifying SPI_LSB_FIRST).
126 * @bits_per_word: Data transfers involve one or more words; word sizes
127 * like eight or 12 bits are common. In-memory wordsizes are
128 * powers of two bytes (e.g. 20 bit samples use 32 bits).
129 * This may be changed by the device's driver, or left at the
130 * default (0) indicating protocol words are eight bit bytes.
131 * The spi_transfer.bits_per_word can override this for each transfer.
132 * @rt: Make the pump thread real time priority.
133 * @irq: Negative, or the number passed to request_irq() to receive
134 * interrupts from this device.
135 * @controller_state: Controller's runtime state
136 * @controller_data: Board-specific definitions for controller, such as
137 * FIFO initialization parameters; from board_info.controller_data
138 * @modalias: Name of the driver to use with this device, or an alias
139 * for that name. This appears in the sysfs "modalias" attribute
140 * for driver coldplugging, and in uevents used for hotplugging
141 * @driver_override: If the name of a driver is written to this attribute, then
142 * the device will bind to the named driver and only the named driver.
143 * @cs_gpio: LEGACY: gpio number of the chipselect line (optional, -ENOENT when
144 * not using a GPIO line) use cs_gpiod in new drivers by opting in on
145 * the spi_master.
146 * @cs_gpiod: gpio descriptor of the chipselect line (optional, NULL when
147 * not using a GPIO line)
148 * @word_delay: delay to be inserted between consecutive
149 * words of a transfer
150 *
151 * @statistics: statistics for the spi_device
152 *
153 * A @spi_device is used to interchange data between an SPI slave
154 * (usually a discrete chip) and CPU memory.
155 *
156 * In @dev, the platform_data is used to hold information about this
157 * device that's meaningful to the device's protocol driver, but not
158 * to its controller. One example might be an identifier for a chip
159 * variant with slightly different functionality; another might be
160 * information about how this particular board wires the chip's pins.
161 */
162 struct spi_device {
163 struct device dev;
164 struct spi_controller *controller;
165 struct spi_controller *master; /* compatibility layer */
166 u32 max_speed_hz;
167 u8 chip_select;
168 u8 bits_per_word;
169 bool rt;
170 #define SPI_NO_TX BIT(31) /* no transmit wire */
171 #define SPI_NO_RX BIT(30) /* no receive wire */
172 /*
173 * All bits defined above should be covered by SPI_MODE_KERNEL_MASK.
174 * The SPI_MODE_KERNEL_MASK has the SPI_MODE_USER_MASK counterpart,
175 * which is defined in 'include/uapi/linux/spi/spi.h'.
176 * The bits defined here are from bit 31 downwards, while in
177 * SPI_MODE_USER_MASK are from 0 upwards.
178 * These bits must not overlap. A static assert check should make sure of that.
179 * If adding extra bits, make sure to decrease the bit index below as well.
180 */
181 #define SPI_MODE_KERNEL_MASK (~(BIT(30) - 1))
182 u32 mode;
183 int irq;
184 void *controller_state;
185 void *controller_data;
186 char modalias[SPI_NAME_SIZE];
187 const char *driver_override;
188 int cs_gpio; /* LEGACY: chip select gpio */
189 struct gpio_desc *cs_gpiod; /* chip select gpio desc */
190 struct spi_delay word_delay; /* inter-word delay */
191
192 /* the statistics */
193 struct spi_statistics statistics;
194
195 /*
196 * likely need more hooks for more protocol options affecting how
197 * the controller talks to each chip, like:
198 * - memory packing (12 bit samples into low bits, others zeroed)
199 * - priority
200 * - chipselect delays
201 * - ...
202 */
203 };
204
205 /* Make sure that SPI_MODE_KERNEL_MASK & SPI_MODE_USER_MASK don't overlap */
206 static_assert((SPI_MODE_KERNEL_MASK & SPI_MODE_USER_MASK) == 0,
207 "SPI_MODE_USER_MASK & SPI_MODE_KERNEL_MASK must not overlap");
208
to_spi_device(struct device * dev)209 static inline struct spi_device *to_spi_device(struct device *dev)
210 {
211 return dev ? container_of(dev, struct spi_device, dev) : NULL;
212 }
213
214 /* most drivers won't need to care about device refcounting */
spi_dev_get(struct spi_device * spi)215 static inline struct spi_device *spi_dev_get(struct spi_device *spi)
216 {
217 return (spi && get_device(&spi->dev)) ? spi : NULL;
218 }
219
spi_dev_put(struct spi_device * spi)220 static inline void spi_dev_put(struct spi_device *spi)
221 {
222 if (spi)
223 put_device(&spi->dev);
224 }
225
226 /* ctldata is for the bus_controller driver's runtime state */
spi_get_ctldata(struct spi_device * spi)227 static inline void *spi_get_ctldata(struct spi_device *spi)
228 {
229 return spi->controller_state;
230 }
231
spi_set_ctldata(struct spi_device * spi,void * state)232 static inline void spi_set_ctldata(struct spi_device *spi, void *state)
233 {
234 spi->controller_state = state;
235 }
236
237 /* device driver data */
238
spi_set_drvdata(struct spi_device * spi,void * data)239 static inline void spi_set_drvdata(struct spi_device *spi, void *data)
240 {
241 dev_set_drvdata(&spi->dev, data);
242 }
243
spi_get_drvdata(struct spi_device * spi)244 static inline void *spi_get_drvdata(struct spi_device *spi)
245 {
246 return dev_get_drvdata(&spi->dev);
247 }
248
249 struct spi_message;
250
251 /**
252 * struct spi_driver - Host side "protocol" driver
253 * @id_table: List of SPI devices supported by this driver
254 * @probe: Binds this driver to the spi device. Drivers can verify
255 * that the device is actually present, and may need to configure
256 * characteristics (such as bits_per_word) which weren't needed for
257 * the initial configuration done during system setup.
258 * @remove: Unbinds this driver from the spi device
259 * @shutdown: Standard shutdown callback used during system state
260 * transitions such as powerdown/halt and kexec
261 * @driver: SPI device drivers should initialize the name and owner
262 * field of this structure.
263 *
264 * This represents the kind of device driver that uses SPI messages to
265 * interact with the hardware at the other end of a SPI link. It's called
266 * a "protocol" driver because it works through messages rather than talking
267 * directly to SPI hardware (which is what the underlying SPI controller
268 * driver does to pass those messages). These protocols are defined in the
269 * specification for the device(s) supported by the driver.
270 *
271 * As a rule, those device protocols represent the lowest level interface
272 * supported by a driver, and it will support upper level interfaces too.
273 * Examples of such upper levels include frameworks like MTD, networking,
274 * MMC, RTC, filesystem character device nodes, and hardware monitoring.
275 */
276 struct spi_driver {
277 const struct spi_device_id *id_table;
278 int (*probe)(struct spi_device *spi);
279 int (*remove)(struct spi_device *spi);
280 void (*shutdown)(struct spi_device *spi);
281 struct device_driver driver;
282 };
283
to_spi_driver(struct device_driver * drv)284 static inline struct spi_driver *to_spi_driver(struct device_driver *drv)
285 {
286 return drv ? container_of(drv, struct spi_driver, driver) : NULL;
287 }
288
289 extern int __spi_register_driver(struct module *owner, struct spi_driver *sdrv);
290
291 /**
292 * spi_unregister_driver - reverse effect of spi_register_driver
293 * @sdrv: the driver to unregister
294 * Context: can sleep
295 */
spi_unregister_driver(struct spi_driver * sdrv)296 static inline void spi_unregister_driver(struct spi_driver *sdrv)
297 {
298 if (sdrv)
299 driver_unregister(&sdrv->driver);
300 }
301
302 /* use a define to avoid include chaining to get THIS_MODULE */
303 #define spi_register_driver(driver) \
304 __spi_register_driver(THIS_MODULE, driver)
305
306 /**
307 * module_spi_driver() - Helper macro for registering a SPI driver
308 * @__spi_driver: spi_driver struct
309 *
310 * Helper macro for SPI drivers which do not do anything special in module
311 * init/exit. This eliminates a lot of boilerplate. Each module may only
312 * use this macro once, and calling it replaces module_init() and module_exit()
313 */
314 #define module_spi_driver(__spi_driver) \
315 module_driver(__spi_driver, spi_register_driver, \
316 spi_unregister_driver)
317
318 /**
319 * struct spi_controller - interface to SPI master or slave controller
320 * @dev: device interface to this driver
321 * @list: link with the global spi_controller list
322 * @bus_num: board-specific (and often SOC-specific) identifier for a
323 * given SPI controller.
324 * @num_chipselect: chipselects are used to distinguish individual
325 * SPI slaves, and are numbered from zero to num_chipselects.
326 * each slave has a chipselect signal, but it's common that not
327 * every chipselect is connected to a slave.
328 * @dma_alignment: SPI controller constraint on DMA buffers alignment.
329 * @mode_bits: flags understood by this controller driver
330 * @buswidth_override_bits: flags to override for this controller driver
331 * @bits_per_word_mask: A mask indicating which values of bits_per_word are
332 * supported by the driver. Bit n indicates that a bits_per_word n+1 is
333 * supported. If set, the SPI core will reject any transfer with an
334 * unsupported bits_per_word. If not set, this value is simply ignored,
335 * and it's up to the individual driver to perform any validation.
336 * @min_speed_hz: Lowest supported transfer speed
337 * @max_speed_hz: Highest supported transfer speed
338 * @flags: other constraints relevant to this driver
339 * @slave: indicates that this is an SPI slave controller
340 * @max_transfer_size: function that returns the max transfer size for
341 * a &spi_device; may be %NULL, so the default %SIZE_MAX will be used.
342 * @max_message_size: function that returns the max message size for
343 * a &spi_device; may be %NULL, so the default %SIZE_MAX will be used.
344 * @io_mutex: mutex for physical bus access
345 * @bus_lock_spinlock: spinlock for SPI bus locking
346 * @bus_lock_mutex: mutex for exclusion of multiple callers
347 * @bus_lock_flag: indicates that the SPI bus is locked for exclusive use
348 * @setup: updates the device mode and clocking records used by a
349 * device's SPI controller; protocol code may call this. This
350 * must fail if an unrecognized or unsupported mode is requested.
351 * It's always safe to call this unless transfers are pending on
352 * the device whose settings are being modified.
353 * @set_cs_timing: optional hook for SPI devices to request SPI master
354 * controller for configuring specific CS setup time, hold time and inactive
355 * delay interms of clock counts
356 * @transfer: adds a message to the controller's transfer queue.
357 * @cleanup: frees controller-specific state
358 * @can_dma: determine whether this controller supports DMA
359 * @queued: whether this controller is providing an internal message queue
360 * @kworker: pointer to thread struct for message pump
361 * @pump_messages: work struct for scheduling work to the message pump
362 * @queue_lock: spinlock to syncronise access to message queue
363 * @queue: message queue
364 * @idling: the device is entering idle state
365 * @cur_msg: the currently in-flight message
366 * @cur_msg_prepared: spi_prepare_message was called for the currently
367 * in-flight message
368 * @cur_msg_mapped: message has been mapped for DMA
369 * @last_cs_enable: was enable true on the last call to set_cs.
370 * @last_cs_mode_high: was (mode & SPI_CS_HIGH) true on the last call to set_cs.
371 * @xfer_completion: used by core transfer_one_message()
372 * @busy: message pump is busy
373 * @running: message pump is running
374 * @rt: whether this queue is set to run as a realtime task
375 * @auto_runtime_pm: the core should ensure a runtime PM reference is held
376 * while the hardware is prepared, using the parent
377 * device for the spidev
378 * @max_dma_len: Maximum length of a DMA transfer for the device.
379 * @prepare_transfer_hardware: a message will soon arrive from the queue
380 * so the subsystem requests the driver to prepare the transfer hardware
381 * by issuing this call
382 * @transfer_one_message: the subsystem calls the driver to transfer a single
383 * message while queuing transfers that arrive in the meantime. When the
384 * driver is finished with this message, it must call
385 * spi_finalize_current_message() so the subsystem can issue the next
386 * message
387 * @unprepare_transfer_hardware: there are currently no more messages on the
388 * queue so the subsystem notifies the driver that it may relax the
389 * hardware by issuing this call
390 *
391 * @set_cs: set the logic level of the chip select line. May be called
392 * from interrupt context.
393 * @prepare_message: set up the controller to transfer a single message,
394 * for example doing DMA mapping. Called from threaded
395 * context.
396 * @transfer_one: transfer a single spi_transfer.
397 *
398 * - return 0 if the transfer is finished,
399 * - return 1 if the transfer is still in progress. When
400 * the driver is finished with this transfer it must
401 * call spi_finalize_current_transfer() so the subsystem
402 * can issue the next transfer. Note: transfer_one and
403 * transfer_one_message are mutually exclusive; when both
404 * are set, the generic subsystem does not call your
405 * transfer_one callback.
406 * @handle_err: the subsystem calls the driver to handle an error that occurs
407 * in the generic implementation of transfer_one_message().
408 * @mem_ops: optimized/dedicated operations for interactions with SPI memory.
409 * This field is optional and should only be implemented if the
410 * controller has native support for memory like operations.
411 * @unprepare_message: undo any work done by prepare_message().
412 * @slave_abort: abort the ongoing transfer request on an SPI slave controller
413 * @cs_setup: delay to be introduced by the controller after CS is asserted
414 * @cs_hold: delay to be introduced by the controller before CS is deasserted
415 * @cs_inactive: delay to be introduced by the controller after CS is
416 * deasserted. If @cs_change_delay is used from @spi_transfer, then the
417 * two delays will be added up.
418 * @cs_gpios: LEGACY: array of GPIO descs to use as chip select lines; one per
419 * CS number. Any individual value may be -ENOENT for CS lines that
420 * are not GPIOs (driven by the SPI controller itself). Use the cs_gpiods
421 * in new drivers.
422 * @cs_gpiods: Array of GPIO descs to use as chip select lines; one per CS
423 * number. Any individual value may be NULL for CS lines that
424 * are not GPIOs (driven by the SPI controller itself).
425 * @use_gpio_descriptors: Turns on the code in the SPI core to parse and grab
426 * GPIO descriptors rather than using global GPIO numbers grabbed by the
427 * driver. This will fill in @cs_gpiods and @cs_gpios should not be used,
428 * and SPI devices will have the cs_gpiod assigned rather than cs_gpio.
429 * @unused_native_cs: When cs_gpiods is used, spi_register_controller() will
430 * fill in this field with the first unused native CS, to be used by SPI
431 * controller drivers that need to drive a native CS when using GPIO CS.
432 * @max_native_cs: When cs_gpiods is used, and this field is filled in,
433 * spi_register_controller() will validate all native CS (including the
434 * unused native CS) against this value.
435 * @statistics: statistics for the spi_controller
436 * @dma_tx: DMA transmit channel
437 * @dma_rx: DMA receive channel
438 * @dummy_rx: dummy receive buffer for full-duplex devices
439 * @dummy_tx: dummy transmit buffer for full-duplex devices
440 * @fw_translate_cs: If the boot firmware uses different numbering scheme
441 * what Linux expects, this optional hook can be used to translate
442 * between the two.
443 * @ptp_sts_supported: If the driver sets this to true, it must provide a
444 * time snapshot in @spi_transfer->ptp_sts as close as possible to the
445 * moment in time when @spi_transfer->ptp_sts_word_pre and
446 * @spi_transfer->ptp_sts_word_post were transmitted.
447 * If the driver does not set this, the SPI core takes the snapshot as
448 * close to the driver hand-over as possible.
449 * @irq_flags: Interrupt enable state during PTP system timestamping
450 * @fallback: fallback to pio if dma transfer return failure with
451 * SPI_TRANS_FAIL_NO_START.
452 *
453 * Each SPI controller can communicate with one or more @spi_device
454 * children. These make a small bus, sharing MOSI, MISO and SCK signals
455 * but not chip select signals. Each device may be configured to use a
456 * different clock rate, since those shared signals are ignored unless
457 * the chip is selected.
458 *
459 * The driver for an SPI controller manages access to those devices through
460 * a queue of spi_message transactions, copying data between CPU memory and
461 * an SPI slave device. For each such message it queues, it calls the
462 * message's completion function when the transaction completes.
463 */
464 struct spi_controller {
465 struct device dev;
466
467 struct list_head list;
468
469 /* other than negative (== assign one dynamically), bus_num is fully
470 * board-specific. usually that simplifies to being SOC-specific.
471 * example: one SOC has three SPI controllers, numbered 0..2,
472 * and one board's schematics might show it using SPI-2. software
473 * would normally use bus_num=2 for that controller.
474 */
475 s16 bus_num;
476
477 /* chipselects will be integral to many controllers; some others
478 * might use board-specific GPIOs.
479 */
480 u16 num_chipselect;
481
482 /* some SPI controllers pose alignment requirements on DMAable
483 * buffers; let protocol drivers know about these requirements.
484 */
485 u16 dma_alignment;
486
487 /* spi_device.mode flags understood by this controller driver */
488 u32 mode_bits;
489
490 /* spi_device.mode flags override flags for this controller */
491 u32 buswidth_override_bits;
492
493 /* bitmask of supported bits_per_word for transfers */
494 u32 bits_per_word_mask;
495 #define SPI_BPW_MASK(bits) BIT((bits) - 1)
496 #define SPI_BPW_RANGE_MASK(min, max) GENMASK((max) - 1, (min) - 1)
497
498 /* limits on transfer speed */
499 u32 min_speed_hz;
500 u32 max_speed_hz;
501
502 /* other constraints relevant to this driver */
503 u16 flags;
504 #define SPI_CONTROLLER_HALF_DUPLEX BIT(0) /* can't do full duplex */
505 #define SPI_CONTROLLER_NO_RX BIT(1) /* can't do buffer read */
506 #define SPI_CONTROLLER_NO_TX BIT(2) /* can't do buffer write */
507 #define SPI_CONTROLLER_MUST_RX BIT(3) /* requires rx */
508 #define SPI_CONTROLLER_MUST_TX BIT(4) /* requires tx */
509
510 #define SPI_MASTER_GPIO_SS BIT(5) /* GPIO CS must select slave */
511
512 /* flag indicating this is a non-devres managed controller */
513 bool devm_allocated;
514
515 /* flag indicating this is an SPI slave controller */
516 bool slave;
517
518 /*
519 * on some hardware transfer / message size may be constrained
520 * the limit may depend on device transfer settings
521 */
522 size_t (*max_transfer_size)(struct spi_device *spi);
523 size_t (*max_message_size)(struct spi_device *spi);
524
525 /* I/O mutex */
526 struct mutex io_mutex;
527
528 /* lock and mutex for SPI bus locking */
529 spinlock_t bus_lock_spinlock;
530 struct mutex bus_lock_mutex;
531
532 /* flag indicating that the SPI bus is locked for exclusive use */
533 bool bus_lock_flag;
534
535 /* Setup mode and clock, etc (spi driver may call many times).
536 *
537 * IMPORTANT: this may be called when transfers to another
538 * device are active. DO NOT UPDATE SHARED REGISTERS in ways
539 * which could break those transfers.
540 */
541 int (*setup)(struct spi_device *spi);
542
543 /*
544 * set_cs_timing() method is for SPI controllers that supports
545 * configuring CS timing.
546 *
547 * This hook allows SPI client drivers to request SPI controllers
548 * to configure specific CS timing through spi_set_cs_timing() after
549 * spi_setup().
550 */
551 int (*set_cs_timing)(struct spi_device *spi, struct spi_delay *setup,
552 struct spi_delay *hold, struct spi_delay *inactive);
553
554 /* bidirectional bulk transfers
555 *
556 * + The transfer() method may not sleep; its main role is
557 * just to add the message to the queue.
558 * + For now there's no remove-from-queue operation, or
559 * any other request management
560 * + To a given spi_device, message queueing is pure fifo
561 *
562 * + The controller's main job is to process its message queue,
563 * selecting a chip (for masters), then transferring data
564 * + If there are multiple spi_device children, the i/o queue
565 * arbitration algorithm is unspecified (round robin, fifo,
566 * priority, reservations, preemption, etc)
567 *
568 * + Chipselect stays active during the entire message
569 * (unless modified by spi_transfer.cs_change != 0).
570 * + The message transfers use clock and SPI mode parameters
571 * previously established by setup() for this device
572 */
573 int (*transfer)(struct spi_device *spi,
574 struct spi_message *mesg);
575
576 /* called on release() to free memory provided by spi_controller */
577 void (*cleanup)(struct spi_device *spi);
578
579 /*
580 * Used to enable core support for DMA handling, if can_dma()
581 * exists and returns true then the transfer will be mapped
582 * prior to transfer_one() being called. The driver should
583 * not modify or store xfer and dma_tx and dma_rx must be set
584 * while the device is prepared.
585 */
586 bool (*can_dma)(struct spi_controller *ctlr,
587 struct spi_device *spi,
588 struct spi_transfer *xfer);
589
590 /*
591 * These hooks are for drivers that want to use the generic
592 * controller transfer queueing mechanism. If these are used, the
593 * transfer() function above must NOT be specified by the driver.
594 * Over time we expect SPI drivers to be phased over to this API.
595 */
596 bool queued;
597 struct kthread_worker *kworker;
598 struct kthread_work pump_messages;
599 spinlock_t queue_lock;
600 struct list_head queue;
601 struct spi_message *cur_msg;
602 bool idling;
603 bool busy;
604 bool running;
605 bool rt;
606 bool auto_runtime_pm;
607 bool cur_msg_prepared;
608 bool cur_msg_mapped;
609 bool last_cs_enable;
610 bool last_cs_mode_high;
611 bool fallback;
612 struct completion xfer_completion;
613 size_t max_dma_len;
614
615 int (*prepare_transfer_hardware)(struct spi_controller *ctlr);
616 int (*transfer_one_message)(struct spi_controller *ctlr,
617 struct spi_message *mesg);
618 int (*unprepare_transfer_hardware)(struct spi_controller *ctlr);
619 int (*prepare_message)(struct spi_controller *ctlr,
620 struct spi_message *message);
621 int (*unprepare_message)(struct spi_controller *ctlr,
622 struct spi_message *message);
623 int (*slave_abort)(struct spi_controller *ctlr);
624
625 /*
626 * These hooks are for drivers that use a generic implementation
627 * of transfer_one_message() provided by the core.
628 */
629 void (*set_cs)(struct spi_device *spi, bool enable);
630 int (*transfer_one)(struct spi_controller *ctlr, struct spi_device *spi,
631 struct spi_transfer *transfer);
632 void (*handle_err)(struct spi_controller *ctlr,
633 struct spi_message *message);
634
635 /* Optimized handlers for SPI memory-like operations. */
636 const struct spi_controller_mem_ops *mem_ops;
637
638 /* CS delays */
639 struct spi_delay cs_setup;
640 struct spi_delay cs_hold;
641 struct spi_delay cs_inactive;
642
643 /* gpio chip select */
644 int *cs_gpios;
645 struct gpio_desc **cs_gpiods;
646 bool use_gpio_descriptors;
647 u8 unused_native_cs;
648 u8 max_native_cs;
649
650 /* statistics */
651 struct spi_statistics statistics;
652
653 /* DMA channels for use with core dmaengine helpers */
654 struct dma_chan *dma_tx;
655 struct dma_chan *dma_rx;
656
657 /* dummy data for full duplex devices */
658 void *dummy_rx;
659 void *dummy_tx;
660
661 int (*fw_translate_cs)(struct spi_controller *ctlr, unsigned cs);
662
663 /*
664 * Driver sets this field to indicate it is able to snapshot SPI
665 * transfers (needed e.g. for reading the time of POSIX clocks)
666 */
667 bool ptp_sts_supported;
668
669 /* Interrupt enable state during PTP system timestamping */
670 unsigned long irq_flags;
671 };
672
spi_controller_get_devdata(struct spi_controller * ctlr)673 static inline void *spi_controller_get_devdata(struct spi_controller *ctlr)
674 {
675 return dev_get_drvdata(&ctlr->dev);
676 }
677
spi_controller_set_devdata(struct spi_controller * ctlr,void * data)678 static inline void spi_controller_set_devdata(struct spi_controller *ctlr,
679 void *data)
680 {
681 dev_set_drvdata(&ctlr->dev, data);
682 }
683
spi_controller_get(struct spi_controller * ctlr)684 static inline struct spi_controller *spi_controller_get(struct spi_controller *ctlr)
685 {
686 if (!ctlr || !get_device(&ctlr->dev))
687 return NULL;
688 return ctlr;
689 }
690
spi_controller_put(struct spi_controller * ctlr)691 static inline void spi_controller_put(struct spi_controller *ctlr)
692 {
693 if (ctlr)
694 put_device(&ctlr->dev);
695 }
696
spi_controller_is_slave(struct spi_controller * ctlr)697 static inline bool spi_controller_is_slave(struct spi_controller *ctlr)
698 {
699 return IS_ENABLED(CONFIG_SPI_SLAVE) && ctlr->slave;
700 }
701
702 /* PM calls that need to be issued by the driver */
703 extern int spi_controller_suspend(struct spi_controller *ctlr);
704 extern int spi_controller_resume(struct spi_controller *ctlr);
705
706 /* Calls the driver make to interact with the message queue */
707 extern struct spi_message *spi_get_next_queued_message(struct spi_controller *ctlr);
708 extern void spi_finalize_current_message(struct spi_controller *ctlr);
709 extern void spi_finalize_current_transfer(struct spi_controller *ctlr);
710
711 /* Helper calls for driver to timestamp transfer */
712 void spi_take_timestamp_pre(struct spi_controller *ctlr,
713 struct spi_transfer *xfer,
714 size_t progress, bool irqs_off);
715 void spi_take_timestamp_post(struct spi_controller *ctlr,
716 struct spi_transfer *xfer,
717 size_t progress, bool irqs_off);
718
719 /* the spi driver core manages memory for the spi_controller classdev */
720 extern struct spi_controller *__spi_alloc_controller(struct device *host,
721 unsigned int size, bool slave);
722
spi_alloc_master(struct device * host,unsigned int size)723 static inline struct spi_controller *spi_alloc_master(struct device *host,
724 unsigned int size)
725 {
726 return __spi_alloc_controller(host, size, false);
727 }
728
spi_alloc_slave(struct device * host,unsigned int size)729 static inline struct spi_controller *spi_alloc_slave(struct device *host,
730 unsigned int size)
731 {
732 if (!IS_ENABLED(CONFIG_SPI_SLAVE))
733 return NULL;
734
735 return __spi_alloc_controller(host, size, true);
736 }
737
738 struct spi_controller *__devm_spi_alloc_controller(struct device *dev,
739 unsigned int size,
740 bool slave);
741
devm_spi_alloc_master(struct device * dev,unsigned int size)742 static inline struct spi_controller *devm_spi_alloc_master(struct device *dev,
743 unsigned int size)
744 {
745 return __devm_spi_alloc_controller(dev, size, false);
746 }
747
devm_spi_alloc_slave(struct device * dev,unsigned int size)748 static inline struct spi_controller *devm_spi_alloc_slave(struct device *dev,
749 unsigned int size)
750 {
751 if (!IS_ENABLED(CONFIG_SPI_SLAVE))
752 return NULL;
753
754 return __devm_spi_alloc_controller(dev, size, true);
755 }
756
757 extern int spi_register_controller(struct spi_controller *ctlr);
758 extern int devm_spi_register_controller(struct device *dev,
759 struct spi_controller *ctlr);
760 extern void spi_unregister_controller(struct spi_controller *ctlr);
761
762 extern struct spi_controller *spi_busnum_to_master(u16 busnum);
763
764 /*
765 * SPI resource management while processing a SPI message
766 */
767
768 typedef void (*spi_res_release_t)(struct spi_controller *ctlr,
769 struct spi_message *msg,
770 void *res);
771
772 /**
773 * struct spi_res - spi resource management structure
774 * @entry: list entry
775 * @release: release code called prior to freeing this resource
776 * @data: extra data allocated for the specific use-case
777 *
778 * this is based on ideas from devres, but focused on life-cycle
779 * management during spi_message processing
780 */
781 struct spi_res {
782 struct list_head entry;
783 spi_res_release_t release;
784 unsigned long long data[]; /* guarantee ull alignment */
785 };
786
787 extern void *spi_res_alloc(struct spi_device *spi,
788 spi_res_release_t release,
789 size_t size, gfp_t gfp);
790 extern void spi_res_add(struct spi_message *message, void *res);
791 extern void spi_res_free(void *res);
792
793 extern void spi_res_release(struct spi_controller *ctlr,
794 struct spi_message *message);
795
796 /*---------------------------------------------------------------------------*/
797
798 /*
799 * I/O INTERFACE between SPI controller and protocol drivers
800 *
801 * Protocol drivers use a queue of spi_messages, each transferring data
802 * between the controller and memory buffers.
803 *
804 * The spi_messages themselves consist of a series of read+write transfer
805 * segments. Those segments always read the same number of bits as they
806 * write; but one or the other is easily ignored by passing a null buffer
807 * pointer. (This is unlike most types of I/O API, because SPI hardware
808 * is full duplex.)
809 *
810 * NOTE: Allocation of spi_transfer and spi_message memory is entirely
811 * up to the protocol driver, which guarantees the integrity of both (as
812 * well as the data buffers) for as long as the message is queued.
813 */
814
815 /**
816 * struct spi_transfer - a read/write buffer pair
817 * @tx_buf: data to be written (dma-safe memory), or NULL
818 * @rx_buf: data to be read (dma-safe memory), or NULL
819 * @tx_dma: DMA address of tx_buf, if @spi_message.is_dma_mapped
820 * @rx_dma: DMA address of rx_buf, if @spi_message.is_dma_mapped
821 * @tx_nbits: number of bits used for writing. If 0 the default
822 * (SPI_NBITS_SINGLE) is used.
823 * @rx_nbits: number of bits used for reading. If 0 the default
824 * (SPI_NBITS_SINGLE) is used.
825 * @len: size of rx and tx buffers (in bytes)
826 * @speed_hz: Select a speed other than the device default for this
827 * transfer. If 0 the default (from @spi_device) is used.
828 * @bits_per_word: select a bits_per_word other than the device default
829 * for this transfer. If 0 the default (from @spi_device) is used.
830 * @dummy_data: indicates transfer is dummy bytes transfer.
831 * @cs_change: affects chipselect after this transfer completes
832 * @cs_change_delay: delay between cs deassert and assert when
833 * @cs_change is set and @spi_transfer is not the last in @spi_message
834 * @delay: delay to be introduced after this transfer before
835 * (optionally) changing the chipselect status, then starting
836 * the next transfer or completing this @spi_message.
837 * @word_delay: inter word delay to be introduced after each word size
838 * (set by bits_per_word) transmission.
839 * @effective_speed_hz: the effective SCK-speed that was used to
840 * transfer this transfer. Set to 0 if the spi bus driver does
841 * not support it.
842 * @transfer_list: transfers are sequenced through @spi_message.transfers
843 * @tx_sg: Scatterlist for transmit, currently not for client use
844 * @rx_sg: Scatterlist for receive, currently not for client use
845 * @ptp_sts_word_pre: The word (subject to bits_per_word semantics) offset
846 * within @tx_buf for which the SPI device is requesting that the time
847 * snapshot for this transfer begins. Upon completing the SPI transfer,
848 * this value may have changed compared to what was requested, depending
849 * on the available snapshotting resolution (DMA transfer,
850 * @ptp_sts_supported is false, etc).
851 * @ptp_sts_word_post: See @ptp_sts_word_post. The two can be equal (meaning
852 * that a single byte should be snapshotted).
853 * If the core takes care of the timestamp (if @ptp_sts_supported is false
854 * for this controller), it will set @ptp_sts_word_pre to 0, and
855 * @ptp_sts_word_post to the length of the transfer. This is done
856 * purposefully (instead of setting to spi_transfer->len - 1) to denote
857 * that a transfer-level snapshot taken from within the driver may still
858 * be of higher quality.
859 * @ptp_sts: Pointer to a memory location held by the SPI slave device where a
860 * PTP system timestamp structure may lie. If drivers use PIO or their
861 * hardware has some sort of assist for retrieving exact transfer timing,
862 * they can (and should) assert @ptp_sts_supported and populate this
863 * structure using the ptp_read_system_*ts helper functions.
864 * The timestamp must represent the time at which the SPI slave device has
865 * processed the word, i.e. the "pre" timestamp should be taken before
866 * transmitting the "pre" word, and the "post" timestamp after receiving
867 * transmit confirmation from the controller for the "post" word.
868 * @timestamped: true if the transfer has been timestamped
869 * @error: Error status logged by spi controller driver.
870 *
871 * SPI transfers always write the same number of bytes as they read.
872 * Protocol drivers should always provide @rx_buf and/or @tx_buf.
873 * In some cases, they may also want to provide DMA addresses for
874 * the data being transferred; that may reduce overhead, when the
875 * underlying driver uses dma.
876 *
877 * If the transmit buffer is null, zeroes will be shifted out
878 * while filling @rx_buf. If the receive buffer is null, the data
879 * shifted in will be discarded. Only "len" bytes shift out (or in).
880 * It's an error to try to shift out a partial word. (For example, by
881 * shifting out three bytes with word size of sixteen or twenty bits;
882 * the former uses two bytes per word, the latter uses four bytes.)
883 *
884 * In-memory data values are always in native CPU byte order, translated
885 * from the wire byte order (big-endian except with SPI_LSB_FIRST). So
886 * for example when bits_per_word is sixteen, buffers are 2N bytes long
887 * (@len = 2N) and hold N sixteen bit words in CPU byte order.
888 *
889 * When the word size of the SPI transfer is not a power-of-two multiple
890 * of eight bits, those in-memory words include extra bits. In-memory
891 * words are always seen by protocol drivers as right-justified, so the
892 * undefined (rx) or unused (tx) bits are always the most significant bits.
893 *
894 * All SPI transfers start with the relevant chipselect active. Normally
895 * it stays selected until after the last transfer in a message. Drivers
896 * can affect the chipselect signal using cs_change.
897 *
898 * (i) If the transfer isn't the last one in the message, this flag is
899 * used to make the chipselect briefly go inactive in the middle of the
900 * message. Toggling chipselect in this way may be needed to terminate
901 * a chip command, letting a single spi_message perform all of group of
902 * chip transactions together.
903 *
904 * (ii) When the transfer is the last one in the message, the chip may
905 * stay selected until the next transfer. On multi-device SPI busses
906 * with nothing blocking messages going to other devices, this is just
907 * a performance hint; starting a message to another device deselects
908 * this one. But in other cases, this can be used to ensure correctness.
909 * Some devices need protocol transactions to be built from a series of
910 * spi_message submissions, where the content of one message is determined
911 * by the results of previous messages and where the whole transaction
912 * ends when the chipselect goes intactive.
913 *
914 * When SPI can transfer in 1x,2x or 4x. It can get this transfer information
915 * from device through @tx_nbits and @rx_nbits. In Bi-direction, these
916 * two should both be set. User can set transfer mode with SPI_NBITS_SINGLE(1x)
917 * SPI_NBITS_DUAL(2x) and SPI_NBITS_QUAD(4x) to support these three transfer.
918 *
919 * The code that submits an spi_message (and its spi_transfers)
920 * to the lower layers is responsible for managing its memory.
921 * Zero-initialize every field you don't set up explicitly, to
922 * insulate against future API updates. After you submit a message
923 * and its transfers, ignore them until its completion callback.
924 */
925 struct spi_transfer {
926 /* it's ok if tx_buf == rx_buf (right?)
927 * for MicroWire, one buffer must be null
928 * buffers must work with dma_*map_single() calls, unless
929 * spi_message.is_dma_mapped reports a pre-existing mapping
930 */
931 const void *tx_buf;
932 void *rx_buf;
933 unsigned len;
934
935 dma_addr_t tx_dma;
936 dma_addr_t rx_dma;
937 struct sg_table tx_sg;
938 struct sg_table rx_sg;
939
940 unsigned dummy_data:1;
941 unsigned cs_change:1;
942 unsigned tx_nbits:3;
943 unsigned rx_nbits:3;
944 #define SPI_NBITS_SINGLE 0x01 /* 1bit transfer */
945 #define SPI_NBITS_DUAL 0x02 /* 2bits transfer */
946 #define SPI_NBITS_QUAD 0x04 /* 4bits transfer */
947 u8 bits_per_word;
948 struct spi_delay delay;
949 struct spi_delay cs_change_delay;
950 struct spi_delay word_delay;
951 u32 speed_hz;
952
953 u32 effective_speed_hz;
954
955 unsigned int ptp_sts_word_pre;
956 unsigned int ptp_sts_word_post;
957
958 struct ptp_system_timestamp *ptp_sts;
959
960 bool timestamped;
961
962 struct list_head transfer_list;
963
964 #define SPI_TRANS_FAIL_NO_START BIT(0)
965 u16 error;
966 };
967
968 /**
969 * struct spi_message - one multi-segment SPI transaction
970 * @transfers: list of transfer segments in this transaction
971 * @spi: SPI device to which the transaction is queued
972 * @is_dma_mapped: if true, the caller provided both dma and cpu virtual
973 * addresses for each transfer buffer
974 * @complete: called to report transaction completions
975 * @context: the argument to complete() when it's called
976 * @frame_length: the total number of bytes in the message
977 * @actual_length: the total number of bytes that were transferred in all
978 * successful segments
979 * @status: zero for success, else negative errno
980 * @queue: for use by whichever driver currently owns the message
981 * @state: for use by whichever driver currently owns the message
982 * @resources: for resource management when the spi message is processed
983 *
984 * A @spi_message is used to execute an atomic sequence of data transfers,
985 * each represented by a struct spi_transfer. The sequence is "atomic"
986 * in the sense that no other spi_message may use that SPI bus until that
987 * sequence completes. On some systems, many such sequences can execute as
988 * a single programmed DMA transfer. On all systems, these messages are
989 * queued, and might complete after transactions to other devices. Messages
990 * sent to a given spi_device are always executed in FIFO order.
991 *
992 * The code that submits an spi_message (and its spi_transfers)
993 * to the lower layers is responsible for managing its memory.
994 * Zero-initialize every field you don't set up explicitly, to
995 * insulate against future API updates. After you submit a message
996 * and its transfers, ignore them until its completion callback.
997 */
998 struct spi_message {
999 struct list_head transfers;
1000
1001 struct spi_device *spi;
1002
1003 unsigned is_dma_mapped:1;
1004
1005 /* REVISIT: we might want a flag affecting the behavior of the
1006 * last transfer ... allowing things like "read 16 bit length L"
1007 * immediately followed by "read L bytes". Basically imposing
1008 * a specific message scheduling algorithm.
1009 *
1010 * Some controller drivers (message-at-a-time queue processing)
1011 * could provide that as their default scheduling algorithm. But
1012 * others (with multi-message pipelines) could need a flag to
1013 * tell them about such special cases.
1014 */
1015
1016 /* completion is reported through a callback */
1017 void (*complete)(void *context);
1018 void *context;
1019 unsigned frame_length;
1020 unsigned actual_length;
1021 int status;
1022
1023 /* for optional use by whatever driver currently owns the
1024 * spi_message ... between calls to spi_async and then later
1025 * complete(), that's the spi_controller controller driver.
1026 */
1027 struct list_head queue;
1028 void *state;
1029
1030 /* list of spi_res reources when the spi message is processed */
1031 struct list_head resources;
1032 };
1033
spi_message_init_no_memset(struct spi_message * m)1034 static inline void spi_message_init_no_memset(struct spi_message *m)
1035 {
1036 INIT_LIST_HEAD(&m->transfers);
1037 INIT_LIST_HEAD(&m->resources);
1038 }
1039
spi_message_init(struct spi_message * m)1040 static inline void spi_message_init(struct spi_message *m)
1041 {
1042 memset(m, 0, sizeof *m);
1043 spi_message_init_no_memset(m);
1044 }
1045
1046 static inline void
spi_message_add_tail(struct spi_transfer * t,struct spi_message * m)1047 spi_message_add_tail(struct spi_transfer *t, struct spi_message *m)
1048 {
1049 list_add_tail(&t->transfer_list, &m->transfers);
1050 }
1051
1052 static inline void
spi_transfer_del(struct spi_transfer * t)1053 spi_transfer_del(struct spi_transfer *t)
1054 {
1055 list_del(&t->transfer_list);
1056 }
1057
1058 static inline int
spi_transfer_delay_exec(struct spi_transfer * t)1059 spi_transfer_delay_exec(struct spi_transfer *t)
1060 {
1061 return spi_delay_exec(&t->delay, t);
1062 }
1063
1064 /**
1065 * spi_message_init_with_transfers - Initialize spi_message and append transfers
1066 * @m: spi_message to be initialized
1067 * @xfers: An array of spi transfers
1068 * @num_xfers: Number of items in the xfer array
1069 *
1070 * This function initializes the given spi_message and adds each spi_transfer in
1071 * the given array to the message.
1072 */
1073 static inline void
spi_message_init_with_transfers(struct spi_message * m,struct spi_transfer * xfers,unsigned int num_xfers)1074 spi_message_init_with_transfers(struct spi_message *m,
1075 struct spi_transfer *xfers, unsigned int num_xfers)
1076 {
1077 unsigned int i;
1078
1079 spi_message_init(m);
1080 for (i = 0; i < num_xfers; ++i)
1081 spi_message_add_tail(&xfers[i], m);
1082 }
1083
1084 /* It's fine to embed message and transaction structures in other data
1085 * structures so long as you don't free them while they're in use.
1086 */
1087
spi_message_alloc(unsigned ntrans,gfp_t flags)1088 static inline struct spi_message *spi_message_alloc(unsigned ntrans, gfp_t flags)
1089 {
1090 struct spi_message *m;
1091
1092 m = kzalloc(sizeof(struct spi_message)
1093 + ntrans * sizeof(struct spi_transfer),
1094 flags);
1095 if (m) {
1096 unsigned i;
1097 struct spi_transfer *t = (struct spi_transfer *)(m + 1);
1098
1099 spi_message_init_no_memset(m);
1100 for (i = 0; i < ntrans; i++, t++)
1101 spi_message_add_tail(t, m);
1102 }
1103 return m;
1104 }
1105
spi_message_free(struct spi_message * m)1106 static inline void spi_message_free(struct spi_message *m)
1107 {
1108 kfree(m);
1109 }
1110
1111 extern int spi_set_cs_timing(struct spi_device *spi,
1112 struct spi_delay *setup,
1113 struct spi_delay *hold,
1114 struct spi_delay *inactive);
1115
1116 extern int spi_setup(struct spi_device *spi);
1117 extern int spi_async(struct spi_device *spi, struct spi_message *message);
1118 extern int spi_async_locked(struct spi_device *spi,
1119 struct spi_message *message);
1120 extern int spi_slave_abort(struct spi_device *spi);
1121
1122 static inline size_t
spi_max_message_size(struct spi_device * spi)1123 spi_max_message_size(struct spi_device *spi)
1124 {
1125 struct spi_controller *ctlr = spi->controller;
1126
1127 if (!ctlr->max_message_size)
1128 return SIZE_MAX;
1129 return ctlr->max_message_size(spi);
1130 }
1131
1132 static inline size_t
spi_max_transfer_size(struct spi_device * spi)1133 spi_max_transfer_size(struct spi_device *spi)
1134 {
1135 struct spi_controller *ctlr = spi->controller;
1136 size_t tr_max = SIZE_MAX;
1137 size_t msg_max = spi_max_message_size(spi);
1138
1139 if (ctlr->max_transfer_size)
1140 tr_max = ctlr->max_transfer_size(spi);
1141
1142 /* transfer size limit must not be greater than messsage size limit */
1143 return min(tr_max, msg_max);
1144 }
1145
1146 /**
1147 * spi_is_bpw_supported - Check if bits per word is supported
1148 * @spi: SPI device
1149 * @bpw: Bits per word
1150 *
1151 * This function checks to see if the SPI controller supports @bpw.
1152 *
1153 * Returns:
1154 * True if @bpw is supported, false otherwise.
1155 */
spi_is_bpw_supported(struct spi_device * spi,u32 bpw)1156 static inline bool spi_is_bpw_supported(struct spi_device *spi, u32 bpw)
1157 {
1158 u32 bpw_mask = spi->master->bits_per_word_mask;
1159
1160 if (bpw == 8 || (bpw <= 32 && bpw_mask & SPI_BPW_MASK(bpw)))
1161 return true;
1162
1163 return false;
1164 }
1165
1166 /*---------------------------------------------------------------------------*/
1167
1168 /* SPI transfer replacement methods which make use of spi_res */
1169
1170 struct spi_replaced_transfers;
1171 typedef void (*spi_replaced_release_t)(struct spi_controller *ctlr,
1172 struct spi_message *msg,
1173 struct spi_replaced_transfers *res);
1174 /**
1175 * struct spi_replaced_transfers - structure describing the spi_transfer
1176 * replacements that have occurred
1177 * so that they can get reverted
1178 * @release: some extra release code to get executed prior to
1179 * relasing this structure
1180 * @extradata: pointer to some extra data if requested or NULL
1181 * @replaced_transfers: transfers that have been replaced and which need
1182 * to get restored
1183 * @replaced_after: the transfer after which the @replaced_transfers
1184 * are to get re-inserted
1185 * @inserted: number of transfers inserted
1186 * @inserted_transfers: array of spi_transfers of array-size @inserted,
1187 * that have been replacing replaced_transfers
1188 *
1189 * note: that @extradata will point to @inserted_transfers[@inserted]
1190 * if some extra allocation is requested, so alignment will be the same
1191 * as for spi_transfers
1192 */
1193 struct spi_replaced_transfers {
1194 spi_replaced_release_t release;
1195 void *extradata;
1196 struct list_head replaced_transfers;
1197 struct list_head *replaced_after;
1198 size_t inserted;
1199 struct spi_transfer inserted_transfers[];
1200 };
1201
1202 extern struct spi_replaced_transfers *spi_replace_transfers(
1203 struct spi_message *msg,
1204 struct spi_transfer *xfer_first,
1205 size_t remove,
1206 size_t insert,
1207 spi_replaced_release_t release,
1208 size_t extradatasize,
1209 gfp_t gfp);
1210
1211 /*---------------------------------------------------------------------------*/
1212
1213 /* SPI transfer transformation methods */
1214
1215 extern int spi_split_transfers_maxsize(struct spi_controller *ctlr,
1216 struct spi_message *msg,
1217 size_t maxsize,
1218 gfp_t gfp);
1219
1220 /*---------------------------------------------------------------------------*/
1221
1222 /* All these synchronous SPI transfer routines are utilities layered
1223 * over the core async transfer primitive. Here, "synchronous" means
1224 * they will sleep uninterruptibly until the async transfer completes.
1225 */
1226
1227 extern int spi_sync(struct spi_device *spi, struct spi_message *message);
1228 extern int spi_sync_locked(struct spi_device *spi, struct spi_message *message);
1229 extern int spi_bus_lock(struct spi_controller *ctlr);
1230 extern int spi_bus_unlock(struct spi_controller *ctlr);
1231
1232 /**
1233 * spi_sync_transfer - synchronous SPI data transfer
1234 * @spi: device with which data will be exchanged
1235 * @xfers: An array of spi_transfers
1236 * @num_xfers: Number of items in the xfer array
1237 * Context: can sleep
1238 *
1239 * Does a synchronous SPI data transfer of the given spi_transfer array.
1240 *
1241 * For more specific semantics see spi_sync().
1242 *
1243 * Return: zero on success, else a negative error code.
1244 */
1245 static inline int
spi_sync_transfer(struct spi_device * spi,struct spi_transfer * xfers,unsigned int num_xfers)1246 spi_sync_transfer(struct spi_device *spi, struct spi_transfer *xfers,
1247 unsigned int num_xfers)
1248 {
1249 struct spi_message msg;
1250
1251 spi_message_init_with_transfers(&msg, xfers, num_xfers);
1252
1253 return spi_sync(spi, &msg);
1254 }
1255
1256 /**
1257 * spi_write - SPI synchronous write
1258 * @spi: device to which data will be written
1259 * @buf: data buffer
1260 * @len: data buffer size
1261 * Context: can sleep
1262 *
1263 * This function writes the buffer @buf.
1264 * Callable only from contexts that can sleep.
1265 *
1266 * Return: zero on success, else a negative error code.
1267 */
1268 static inline int
spi_write(struct spi_device * spi,const void * buf,size_t len)1269 spi_write(struct spi_device *spi, const void *buf, size_t len)
1270 {
1271 struct spi_transfer t = {
1272 .tx_buf = buf,
1273 .len = len,
1274 };
1275
1276 return spi_sync_transfer(spi, &t, 1);
1277 }
1278
1279 /**
1280 * spi_read - SPI synchronous read
1281 * @spi: device from which data will be read
1282 * @buf: data buffer
1283 * @len: data buffer size
1284 * Context: can sleep
1285 *
1286 * This function reads the buffer @buf.
1287 * Callable only from contexts that can sleep.
1288 *
1289 * Return: zero on success, else a negative error code.
1290 */
1291 static inline int
spi_read(struct spi_device * spi,void * buf,size_t len)1292 spi_read(struct spi_device *spi, void *buf, size_t len)
1293 {
1294 struct spi_transfer t = {
1295 .rx_buf = buf,
1296 .len = len,
1297 };
1298
1299 return spi_sync_transfer(spi, &t, 1);
1300 }
1301
1302 /* this copies txbuf and rxbuf data; for small transfers only! */
1303 extern int spi_write_then_read(struct spi_device *spi,
1304 const void *txbuf, unsigned n_tx,
1305 void *rxbuf, unsigned n_rx);
1306
1307 /**
1308 * spi_w8r8 - SPI synchronous 8 bit write followed by 8 bit read
1309 * @spi: device with which data will be exchanged
1310 * @cmd: command to be written before data is read back
1311 * Context: can sleep
1312 *
1313 * Callable only from contexts that can sleep.
1314 *
1315 * Return: the (unsigned) eight bit number returned by the
1316 * device, or else a negative error code.
1317 */
spi_w8r8(struct spi_device * spi,u8 cmd)1318 static inline ssize_t spi_w8r8(struct spi_device *spi, u8 cmd)
1319 {
1320 ssize_t status;
1321 u8 result;
1322
1323 status = spi_write_then_read(spi, &cmd, 1, &result, 1);
1324
1325 /* return negative errno or unsigned value */
1326 return (status < 0) ? status : result;
1327 }
1328
1329 /**
1330 * spi_w8r16 - SPI synchronous 8 bit write followed by 16 bit read
1331 * @spi: device with which data will be exchanged
1332 * @cmd: command to be written before data is read back
1333 * Context: can sleep
1334 *
1335 * The number is returned in wire-order, which is at least sometimes
1336 * big-endian.
1337 *
1338 * Callable only from contexts that can sleep.
1339 *
1340 * Return: the (unsigned) sixteen bit number returned by the
1341 * device, or else a negative error code.
1342 */
spi_w8r16(struct spi_device * spi,u8 cmd)1343 static inline ssize_t spi_w8r16(struct spi_device *spi, u8 cmd)
1344 {
1345 ssize_t status;
1346 u16 result;
1347
1348 status = spi_write_then_read(spi, &cmd, 1, &result, 2);
1349
1350 /* return negative errno or unsigned value */
1351 return (status < 0) ? status : result;
1352 }
1353
1354 /**
1355 * spi_w8r16be - SPI synchronous 8 bit write followed by 16 bit big-endian read
1356 * @spi: device with which data will be exchanged
1357 * @cmd: command to be written before data is read back
1358 * Context: can sleep
1359 *
1360 * This function is similar to spi_w8r16, with the exception that it will
1361 * convert the read 16 bit data word from big-endian to native endianness.
1362 *
1363 * Callable only from contexts that can sleep.
1364 *
1365 * Return: the (unsigned) sixteen bit number returned by the device in cpu
1366 * endianness, or else a negative error code.
1367 */
spi_w8r16be(struct spi_device * spi,u8 cmd)1368 static inline ssize_t spi_w8r16be(struct spi_device *spi, u8 cmd)
1369
1370 {
1371 ssize_t status;
1372 __be16 result;
1373
1374 status = spi_write_then_read(spi, &cmd, 1, &result, 2);
1375 if (status < 0)
1376 return status;
1377
1378 return be16_to_cpu(result);
1379 }
1380
1381 /*---------------------------------------------------------------------------*/
1382
1383 /*
1384 * INTERFACE between board init code and SPI infrastructure.
1385 *
1386 * No SPI driver ever sees these SPI device table segments, but
1387 * it's how the SPI core (or adapters that get hotplugged) grows
1388 * the driver model tree.
1389 *
1390 * As a rule, SPI devices can't be probed. Instead, board init code
1391 * provides a table listing the devices which are present, with enough
1392 * information to bind and set up the device's driver. There's basic
1393 * support for nonstatic configurations too; enough to handle adding
1394 * parport adapters, or microcontrollers acting as USB-to-SPI bridges.
1395 */
1396
1397 /**
1398 * struct spi_board_info - board-specific template for a SPI device
1399 * @modalias: Initializes spi_device.modalias; identifies the driver.
1400 * @platform_data: Initializes spi_device.platform_data; the particular
1401 * data stored there is driver-specific.
1402 * @swnode: Software node for the device.
1403 * @controller_data: Initializes spi_device.controller_data; some
1404 * controllers need hints about hardware setup, e.g. for DMA.
1405 * @irq: Initializes spi_device.irq; depends on how the board is wired.
1406 * @max_speed_hz: Initializes spi_device.max_speed_hz; based on limits
1407 * from the chip datasheet and board-specific signal quality issues.
1408 * @bus_num: Identifies which spi_controller parents the spi_device; unused
1409 * by spi_new_device(), and otherwise depends on board wiring.
1410 * @chip_select: Initializes spi_device.chip_select; depends on how
1411 * the board is wired.
1412 * @mode: Initializes spi_device.mode; based on the chip datasheet, board
1413 * wiring (some devices support both 3WIRE and standard modes), and
1414 * possibly presence of an inverter in the chipselect path.
1415 *
1416 * When adding new SPI devices to the device tree, these structures serve
1417 * as a partial device template. They hold information which can't always
1418 * be determined by drivers. Information that probe() can establish (such
1419 * as the default transfer wordsize) is not included here.
1420 *
1421 * These structures are used in two places. Their primary role is to
1422 * be stored in tables of board-specific device descriptors, which are
1423 * declared early in board initialization and then used (much later) to
1424 * populate a controller's device tree after the that controller's driver
1425 * initializes. A secondary (and atypical) role is as a parameter to
1426 * spi_new_device() call, which happens after those controller drivers
1427 * are active in some dynamic board configuration models.
1428 */
1429 struct spi_board_info {
1430 /* the device name and module name are coupled, like platform_bus;
1431 * "modalias" is normally the driver name.
1432 *
1433 * platform_data goes to spi_device.dev.platform_data,
1434 * controller_data goes to spi_device.controller_data,
1435 * irq is copied too
1436 */
1437 char modalias[SPI_NAME_SIZE];
1438 const void *platform_data;
1439 const struct software_node *swnode;
1440 void *controller_data;
1441 int irq;
1442
1443 /* slower signaling on noisy or low voltage boards */
1444 u32 max_speed_hz;
1445
1446
1447 /* bus_num is board specific and matches the bus_num of some
1448 * spi_controller that will probably be registered later.
1449 *
1450 * chip_select reflects how this chip is wired to that master;
1451 * it's less than num_chipselect.
1452 */
1453 u16 bus_num;
1454 u16 chip_select;
1455
1456 /* mode becomes spi_device.mode, and is essential for chips
1457 * where the default of SPI_CS_HIGH = 0 is wrong.
1458 */
1459 u32 mode;
1460
1461 /* ... may need additional spi_device chip config data here.
1462 * avoid stuff protocol drivers can set; but include stuff
1463 * needed to behave without being bound to a driver:
1464 * - quirks like clock rate mattering when not selected
1465 */
1466 };
1467
1468 #ifdef CONFIG_SPI
1469 extern int
1470 spi_register_board_info(struct spi_board_info const *info, unsigned n);
1471 #else
1472 /* board init code may ignore whether SPI is configured or not */
1473 static inline int
spi_register_board_info(struct spi_board_info const * info,unsigned n)1474 spi_register_board_info(struct spi_board_info const *info, unsigned n)
1475 { return 0; }
1476 #endif
1477
1478 /* If you're hotplugging an adapter with devices (parport, usb, etc)
1479 * use spi_new_device() to describe each device. You can also call
1480 * spi_unregister_device() to start making that device vanish, but
1481 * normally that would be handled by spi_unregister_controller().
1482 *
1483 * You can also use spi_alloc_device() and spi_add_device() to use a two
1484 * stage registration sequence for each spi_device. This gives the caller
1485 * some more control over the spi_device structure before it is registered,
1486 * but requires that caller to initialize fields that would otherwise
1487 * be defined using the board info.
1488 */
1489 extern struct spi_device *
1490 spi_alloc_device(struct spi_controller *ctlr);
1491
1492 extern int
1493 spi_add_device(struct spi_device *spi);
1494
1495 extern struct spi_device *
1496 spi_new_device(struct spi_controller *, struct spi_board_info *);
1497
1498 extern void spi_unregister_device(struct spi_device *spi);
1499
1500 extern const struct spi_device_id *
1501 spi_get_device_id(const struct spi_device *sdev);
1502
1503 static inline bool
spi_transfer_is_last(struct spi_controller * ctlr,struct spi_transfer * xfer)1504 spi_transfer_is_last(struct spi_controller *ctlr, struct spi_transfer *xfer)
1505 {
1506 return list_is_last(&xfer->transfer_list, &ctlr->cur_msg->transfers);
1507 }
1508
1509 /* OF support code */
1510 #if IS_ENABLED(CONFIG_OF)
1511
1512 /* must call put_device() when done with returned spi_device device */
1513 extern struct spi_device *
1514 of_find_spi_device_by_node(struct device_node *node);
1515
1516 #else
1517
1518 static inline struct spi_device *
of_find_spi_device_by_node(struct device_node * node)1519 of_find_spi_device_by_node(struct device_node *node)
1520 {
1521 return NULL;
1522 }
1523
1524 #endif /* IS_ENABLED(CONFIG_OF) */
1525
1526 /* Compatibility layer */
1527 #define spi_master spi_controller
1528
1529 #define SPI_MASTER_HALF_DUPLEX SPI_CONTROLLER_HALF_DUPLEX
1530 #define SPI_MASTER_NO_RX SPI_CONTROLLER_NO_RX
1531 #define SPI_MASTER_NO_TX SPI_CONTROLLER_NO_TX
1532 #define SPI_MASTER_MUST_RX SPI_CONTROLLER_MUST_RX
1533 #define SPI_MASTER_MUST_TX SPI_CONTROLLER_MUST_TX
1534
1535 #define spi_master_get_devdata(_ctlr) spi_controller_get_devdata(_ctlr)
1536 #define spi_master_set_devdata(_ctlr, _data) \
1537 spi_controller_set_devdata(_ctlr, _data)
1538 #define spi_master_get(_ctlr) spi_controller_get(_ctlr)
1539 #define spi_master_put(_ctlr) spi_controller_put(_ctlr)
1540 #define spi_master_suspend(_ctlr) spi_controller_suspend(_ctlr)
1541 #define spi_master_resume(_ctlr) spi_controller_resume(_ctlr)
1542
1543 #define spi_register_master(_ctlr) spi_register_controller(_ctlr)
1544 #define devm_spi_register_master(_dev, _ctlr) \
1545 devm_spi_register_controller(_dev, _ctlr)
1546 #define spi_unregister_master(_ctlr) spi_unregister_controller(_ctlr)
1547
1548 #endif /* __LINUX_SPI_H */
1549