1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note 2 * 3 * Copyright 2016-2020 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 #ifndef HABANALABS_H_ 9 #define HABANALABS_H_ 10 11 #include <linux/types.h> 12 #include <sys/ioctl.h> 13 14 /* 15 * Defines that are asic-specific but constitutes as ABI between kernel driver 16 * and userspace 17 */ 18 #define GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START 0x8000 /* 32KB */ 19 #define GAUDI_DRIVER_SRAM_RESERVED_SIZE_FROM_START 0x80 /* 128 bytes */ 20 21 /* 22 * 128 SOBs reserved for collective wait 23 * 16 SOBs reserved for sync stream 24 */ 25 #define GAUDI_FIRST_AVAILABLE_W_S_SYNC_OBJECT 144 26 27 /* 28 * 64 monitors reserved for collective wait 29 * 8 monitors reserved for sync stream 30 */ 31 #define GAUDI_FIRST_AVAILABLE_W_S_MONITOR 72 32 33 /* 34 * Goya queue Numbering 35 * 36 * The external queues (PCI DMA channels) MUST be before the internal queues 37 * and each group (PCI DMA channels and internal) must be contiguous inside 38 * itself but there can be a gap between the two groups (although not 39 * recommended) 40 */ 41 42 enum goya_queue_id { 43 GOYA_QUEUE_ID_DMA_0 = 0, 44 GOYA_QUEUE_ID_DMA_1 = 1, 45 GOYA_QUEUE_ID_DMA_2 = 2, 46 GOYA_QUEUE_ID_DMA_3 = 3, 47 GOYA_QUEUE_ID_DMA_4 = 4, 48 GOYA_QUEUE_ID_CPU_PQ = 5, 49 GOYA_QUEUE_ID_MME = 6, /* Internal queues start here */ 50 GOYA_QUEUE_ID_TPC0 = 7, 51 GOYA_QUEUE_ID_TPC1 = 8, 52 GOYA_QUEUE_ID_TPC2 = 9, 53 GOYA_QUEUE_ID_TPC3 = 10, 54 GOYA_QUEUE_ID_TPC4 = 11, 55 GOYA_QUEUE_ID_TPC5 = 12, 56 GOYA_QUEUE_ID_TPC6 = 13, 57 GOYA_QUEUE_ID_TPC7 = 14, 58 GOYA_QUEUE_ID_SIZE 59 }; 60 61 /* 62 * Gaudi queue Numbering 63 * External queues (PCI DMA channels) are DMA_0_*, DMA_1_* and DMA_5_*. 64 * Except one CPU queue, all the rest are internal queues. 65 */ 66 67 enum gaudi_queue_id { 68 GAUDI_QUEUE_ID_DMA_0_0 = 0, /* external */ 69 GAUDI_QUEUE_ID_DMA_0_1 = 1, /* external */ 70 GAUDI_QUEUE_ID_DMA_0_2 = 2, /* external */ 71 GAUDI_QUEUE_ID_DMA_0_3 = 3, /* external */ 72 GAUDI_QUEUE_ID_DMA_1_0 = 4, /* external */ 73 GAUDI_QUEUE_ID_DMA_1_1 = 5, /* external */ 74 GAUDI_QUEUE_ID_DMA_1_2 = 6, /* external */ 75 GAUDI_QUEUE_ID_DMA_1_3 = 7, /* external */ 76 GAUDI_QUEUE_ID_CPU_PQ = 8, /* CPU */ 77 GAUDI_QUEUE_ID_DMA_2_0 = 9, /* internal */ 78 GAUDI_QUEUE_ID_DMA_2_1 = 10, /* internal */ 79 GAUDI_QUEUE_ID_DMA_2_2 = 11, /* internal */ 80 GAUDI_QUEUE_ID_DMA_2_3 = 12, /* internal */ 81 GAUDI_QUEUE_ID_DMA_3_0 = 13, /* internal */ 82 GAUDI_QUEUE_ID_DMA_3_1 = 14, /* internal */ 83 GAUDI_QUEUE_ID_DMA_3_2 = 15, /* internal */ 84 GAUDI_QUEUE_ID_DMA_3_3 = 16, /* internal */ 85 GAUDI_QUEUE_ID_DMA_4_0 = 17, /* internal */ 86 GAUDI_QUEUE_ID_DMA_4_1 = 18, /* internal */ 87 GAUDI_QUEUE_ID_DMA_4_2 = 19, /* internal */ 88 GAUDI_QUEUE_ID_DMA_4_3 = 20, /* internal */ 89 GAUDI_QUEUE_ID_DMA_5_0 = 21, /* internal */ 90 GAUDI_QUEUE_ID_DMA_5_1 = 22, /* internal */ 91 GAUDI_QUEUE_ID_DMA_5_2 = 23, /* internal */ 92 GAUDI_QUEUE_ID_DMA_5_3 = 24, /* internal */ 93 GAUDI_QUEUE_ID_DMA_6_0 = 25, /* internal */ 94 GAUDI_QUEUE_ID_DMA_6_1 = 26, /* internal */ 95 GAUDI_QUEUE_ID_DMA_6_2 = 27, /* internal */ 96 GAUDI_QUEUE_ID_DMA_6_3 = 28, /* internal */ 97 GAUDI_QUEUE_ID_DMA_7_0 = 29, /* internal */ 98 GAUDI_QUEUE_ID_DMA_7_1 = 30, /* internal */ 99 GAUDI_QUEUE_ID_DMA_7_2 = 31, /* internal */ 100 GAUDI_QUEUE_ID_DMA_7_3 = 32, /* internal */ 101 GAUDI_QUEUE_ID_MME_0_0 = 33, /* internal */ 102 GAUDI_QUEUE_ID_MME_0_1 = 34, /* internal */ 103 GAUDI_QUEUE_ID_MME_0_2 = 35, /* internal */ 104 GAUDI_QUEUE_ID_MME_0_3 = 36, /* internal */ 105 GAUDI_QUEUE_ID_MME_1_0 = 37, /* internal */ 106 GAUDI_QUEUE_ID_MME_1_1 = 38, /* internal */ 107 GAUDI_QUEUE_ID_MME_1_2 = 39, /* internal */ 108 GAUDI_QUEUE_ID_MME_1_3 = 40, /* internal */ 109 GAUDI_QUEUE_ID_TPC_0_0 = 41, /* internal */ 110 GAUDI_QUEUE_ID_TPC_0_1 = 42, /* internal */ 111 GAUDI_QUEUE_ID_TPC_0_2 = 43, /* internal */ 112 GAUDI_QUEUE_ID_TPC_0_3 = 44, /* internal */ 113 GAUDI_QUEUE_ID_TPC_1_0 = 45, /* internal */ 114 GAUDI_QUEUE_ID_TPC_1_1 = 46, /* internal */ 115 GAUDI_QUEUE_ID_TPC_1_2 = 47, /* internal */ 116 GAUDI_QUEUE_ID_TPC_1_3 = 48, /* internal */ 117 GAUDI_QUEUE_ID_TPC_2_0 = 49, /* internal */ 118 GAUDI_QUEUE_ID_TPC_2_1 = 50, /* internal */ 119 GAUDI_QUEUE_ID_TPC_2_2 = 51, /* internal */ 120 GAUDI_QUEUE_ID_TPC_2_3 = 52, /* internal */ 121 GAUDI_QUEUE_ID_TPC_3_0 = 53, /* internal */ 122 GAUDI_QUEUE_ID_TPC_3_1 = 54, /* internal */ 123 GAUDI_QUEUE_ID_TPC_3_2 = 55, /* internal */ 124 GAUDI_QUEUE_ID_TPC_3_3 = 56, /* internal */ 125 GAUDI_QUEUE_ID_TPC_4_0 = 57, /* internal */ 126 GAUDI_QUEUE_ID_TPC_4_1 = 58, /* internal */ 127 GAUDI_QUEUE_ID_TPC_4_2 = 59, /* internal */ 128 GAUDI_QUEUE_ID_TPC_4_3 = 60, /* internal */ 129 GAUDI_QUEUE_ID_TPC_5_0 = 61, /* internal */ 130 GAUDI_QUEUE_ID_TPC_5_1 = 62, /* internal */ 131 GAUDI_QUEUE_ID_TPC_5_2 = 63, /* internal */ 132 GAUDI_QUEUE_ID_TPC_5_3 = 64, /* internal */ 133 GAUDI_QUEUE_ID_TPC_6_0 = 65, /* internal */ 134 GAUDI_QUEUE_ID_TPC_6_1 = 66, /* internal */ 135 GAUDI_QUEUE_ID_TPC_6_2 = 67, /* internal */ 136 GAUDI_QUEUE_ID_TPC_6_3 = 68, /* internal */ 137 GAUDI_QUEUE_ID_TPC_7_0 = 69, /* internal */ 138 GAUDI_QUEUE_ID_TPC_7_1 = 70, /* internal */ 139 GAUDI_QUEUE_ID_TPC_7_2 = 71, /* internal */ 140 GAUDI_QUEUE_ID_TPC_7_3 = 72, /* internal */ 141 GAUDI_QUEUE_ID_NIC_0_0 = 73, /* internal */ 142 GAUDI_QUEUE_ID_NIC_0_1 = 74, /* internal */ 143 GAUDI_QUEUE_ID_NIC_0_2 = 75, /* internal */ 144 GAUDI_QUEUE_ID_NIC_0_3 = 76, /* internal */ 145 GAUDI_QUEUE_ID_NIC_1_0 = 77, /* internal */ 146 GAUDI_QUEUE_ID_NIC_1_1 = 78, /* internal */ 147 GAUDI_QUEUE_ID_NIC_1_2 = 79, /* internal */ 148 GAUDI_QUEUE_ID_NIC_1_3 = 80, /* internal */ 149 GAUDI_QUEUE_ID_NIC_2_0 = 81, /* internal */ 150 GAUDI_QUEUE_ID_NIC_2_1 = 82, /* internal */ 151 GAUDI_QUEUE_ID_NIC_2_2 = 83, /* internal */ 152 GAUDI_QUEUE_ID_NIC_2_3 = 84, /* internal */ 153 GAUDI_QUEUE_ID_NIC_3_0 = 85, /* internal */ 154 GAUDI_QUEUE_ID_NIC_3_1 = 86, /* internal */ 155 GAUDI_QUEUE_ID_NIC_3_2 = 87, /* internal */ 156 GAUDI_QUEUE_ID_NIC_3_3 = 88, /* internal */ 157 GAUDI_QUEUE_ID_NIC_4_0 = 89, /* internal */ 158 GAUDI_QUEUE_ID_NIC_4_1 = 90, /* internal */ 159 GAUDI_QUEUE_ID_NIC_4_2 = 91, /* internal */ 160 GAUDI_QUEUE_ID_NIC_4_3 = 92, /* internal */ 161 GAUDI_QUEUE_ID_NIC_5_0 = 93, /* internal */ 162 GAUDI_QUEUE_ID_NIC_5_1 = 94, /* internal */ 163 GAUDI_QUEUE_ID_NIC_5_2 = 95, /* internal */ 164 GAUDI_QUEUE_ID_NIC_5_3 = 96, /* internal */ 165 GAUDI_QUEUE_ID_NIC_6_0 = 97, /* internal */ 166 GAUDI_QUEUE_ID_NIC_6_1 = 98, /* internal */ 167 GAUDI_QUEUE_ID_NIC_6_2 = 99, /* internal */ 168 GAUDI_QUEUE_ID_NIC_6_3 = 100, /* internal */ 169 GAUDI_QUEUE_ID_NIC_7_0 = 101, /* internal */ 170 GAUDI_QUEUE_ID_NIC_7_1 = 102, /* internal */ 171 GAUDI_QUEUE_ID_NIC_7_2 = 103, /* internal */ 172 GAUDI_QUEUE_ID_NIC_7_3 = 104, /* internal */ 173 GAUDI_QUEUE_ID_NIC_8_0 = 105, /* internal */ 174 GAUDI_QUEUE_ID_NIC_8_1 = 106, /* internal */ 175 GAUDI_QUEUE_ID_NIC_8_2 = 107, /* internal */ 176 GAUDI_QUEUE_ID_NIC_8_3 = 108, /* internal */ 177 GAUDI_QUEUE_ID_NIC_9_0 = 109, /* internal */ 178 GAUDI_QUEUE_ID_NIC_9_1 = 110, /* internal */ 179 GAUDI_QUEUE_ID_NIC_9_2 = 111, /* internal */ 180 GAUDI_QUEUE_ID_NIC_9_3 = 112, /* internal */ 181 GAUDI_QUEUE_ID_SIZE 182 }; 183 184 /* 185 * Engine Numbering 186 * 187 * Used in the "busy_engines_mask" field in `struct hl_info_hw_idle' 188 */ 189 190 enum goya_engine_id { 191 GOYA_ENGINE_ID_DMA_0 = 0, 192 GOYA_ENGINE_ID_DMA_1, 193 GOYA_ENGINE_ID_DMA_2, 194 GOYA_ENGINE_ID_DMA_3, 195 GOYA_ENGINE_ID_DMA_4, 196 GOYA_ENGINE_ID_MME_0, 197 GOYA_ENGINE_ID_TPC_0, 198 GOYA_ENGINE_ID_TPC_1, 199 GOYA_ENGINE_ID_TPC_2, 200 GOYA_ENGINE_ID_TPC_3, 201 GOYA_ENGINE_ID_TPC_4, 202 GOYA_ENGINE_ID_TPC_5, 203 GOYA_ENGINE_ID_TPC_6, 204 GOYA_ENGINE_ID_TPC_7, 205 GOYA_ENGINE_ID_SIZE 206 }; 207 208 enum gaudi_engine_id { 209 GAUDI_ENGINE_ID_DMA_0 = 0, 210 GAUDI_ENGINE_ID_DMA_1, 211 GAUDI_ENGINE_ID_DMA_2, 212 GAUDI_ENGINE_ID_DMA_3, 213 GAUDI_ENGINE_ID_DMA_4, 214 GAUDI_ENGINE_ID_DMA_5, 215 GAUDI_ENGINE_ID_DMA_6, 216 GAUDI_ENGINE_ID_DMA_7, 217 GAUDI_ENGINE_ID_MME_0, 218 GAUDI_ENGINE_ID_MME_1, 219 GAUDI_ENGINE_ID_MME_2, 220 GAUDI_ENGINE_ID_MME_3, 221 GAUDI_ENGINE_ID_TPC_0, 222 GAUDI_ENGINE_ID_TPC_1, 223 GAUDI_ENGINE_ID_TPC_2, 224 GAUDI_ENGINE_ID_TPC_3, 225 GAUDI_ENGINE_ID_TPC_4, 226 GAUDI_ENGINE_ID_TPC_5, 227 GAUDI_ENGINE_ID_TPC_6, 228 GAUDI_ENGINE_ID_TPC_7, 229 GAUDI_ENGINE_ID_NIC_0, 230 GAUDI_ENGINE_ID_NIC_1, 231 GAUDI_ENGINE_ID_NIC_2, 232 GAUDI_ENGINE_ID_NIC_3, 233 GAUDI_ENGINE_ID_NIC_4, 234 GAUDI_ENGINE_ID_NIC_5, 235 GAUDI_ENGINE_ID_NIC_6, 236 GAUDI_ENGINE_ID_NIC_7, 237 GAUDI_ENGINE_ID_NIC_8, 238 GAUDI_ENGINE_ID_NIC_9, 239 GAUDI_ENGINE_ID_SIZE 240 }; 241 242 enum hl_device_status { 243 HL_DEVICE_STATUS_OPERATIONAL, 244 HL_DEVICE_STATUS_IN_RESET, 245 HL_DEVICE_STATUS_MALFUNCTION, 246 HL_DEVICE_STATUS_NEEDS_RESET 247 }; 248 249 /* Opcode for management ioctl 250 * 251 * HW_IP_INFO - Receive information about different IP blocks in the 252 * device. 253 * HL_INFO_HW_EVENTS - Receive an array describing how many times each event 254 * occurred since the last hard reset. 255 * HL_INFO_DRAM_USAGE - Retrieve the dram usage inside the device and of the 256 * specific context. This is relevant only for devices 257 * where the dram is managed by the kernel driver 258 * HL_INFO_HW_IDLE - Retrieve information about the idle status of each 259 * internal engine. 260 * HL_INFO_DEVICE_STATUS - Retrieve the device's status. This opcode doesn't 261 * require an open context. 262 * HL_INFO_DEVICE_UTILIZATION - Retrieve the total utilization of the device 263 * over the last period specified by the user. 264 * The period can be between 100ms to 1s, in 265 * resolution of 100ms. The return value is a 266 * percentage of the utilization rate. 267 * HL_INFO_HW_EVENTS_AGGREGATE - Receive an array describing how many times each 268 * event occurred since the driver was loaded. 269 * HL_INFO_CLK_RATE - Retrieve the current and maximum clock rate 270 * of the device in MHz. The maximum clock rate is 271 * configurable via sysfs parameter 272 * HL_INFO_RESET_COUNT - Retrieve the counts of the soft and hard reset 273 * operations performed on the device since the last 274 * time the driver was loaded. 275 * HL_INFO_TIME_SYNC - Retrieve the device's time alongside the host's time 276 * for synchronization. 277 * HL_INFO_CS_COUNTERS - Retrieve command submission counters 278 * HL_INFO_PCI_COUNTERS - Retrieve PCI counters 279 * HL_INFO_CLK_THROTTLE_REASON - Retrieve clock throttling reason 280 * HL_INFO_SYNC_MANAGER - Retrieve sync manager info per dcore 281 * HL_INFO_TOTAL_ENERGY - Retrieve total energy consumption 282 * HL_INFO_PLL_FREQUENCY - Retrieve PLL frequency 283 */ 284 #define HL_INFO_HW_IP_INFO 0 285 #define HL_INFO_HW_EVENTS 1 286 #define HL_INFO_DRAM_USAGE 2 287 #define HL_INFO_HW_IDLE 3 288 #define HL_INFO_DEVICE_STATUS 4 289 #define HL_INFO_DEVICE_UTILIZATION 6 290 #define HL_INFO_HW_EVENTS_AGGREGATE 7 291 #define HL_INFO_CLK_RATE 8 292 #define HL_INFO_RESET_COUNT 9 293 #define HL_INFO_TIME_SYNC 10 294 #define HL_INFO_CS_COUNTERS 11 295 #define HL_INFO_PCI_COUNTERS 12 296 #define HL_INFO_CLK_THROTTLE_REASON 13 297 #define HL_INFO_SYNC_MANAGER 14 298 #define HL_INFO_TOTAL_ENERGY 15 299 #define HL_INFO_PLL_FREQUENCY 16 300 #define HL_INFO_POWER 17 301 302 #define HL_INFO_VERSION_MAX_LEN 128 303 #define HL_INFO_CARD_NAME_MAX_LEN 16 304 305 struct hl_info_hw_ip_info { 306 uint64_t sram_base_address; 307 uint64_t dram_base_address; 308 uint64_t dram_size; 309 uint32_t sram_size; 310 uint32_t num_of_events; 311 uint32_t device_id; /* PCI Device ID */ 312 uint32_t module_id; /* For mezzanine cards in servers (From OCP spec.) */ 313 uint32_t reserved; 314 uint16_t first_available_interrupt_id; 315 uint16_t reserved2; 316 uint32_t cpld_version; 317 uint32_t psoc_pci_pll_nr; 318 uint32_t psoc_pci_pll_nf; 319 uint32_t psoc_pci_pll_od; 320 uint32_t psoc_pci_pll_div_factor; 321 uint8_t tpc_enabled_mask; 322 uint8_t dram_enabled; 323 uint8_t pad[2]; 324 uint8_t cpucp_version[HL_INFO_VERSION_MAX_LEN]; 325 uint8_t card_name[HL_INFO_CARD_NAME_MAX_LEN]; 326 uint64_t reserved3; 327 uint64_t dram_page_size; 328 }; 329 330 struct hl_info_dram_usage { 331 uint64_t dram_free_mem; 332 uint64_t ctx_dram_mem; 333 }; 334 335 #define HL_BUSY_ENGINES_MASK_EXT_SIZE 2 336 337 struct hl_info_hw_idle { 338 uint32_t is_idle; 339 /* 340 * Bitmask of busy engines. 341 * Bits definition is according to `enum <chip>_enging_id'. 342 */ 343 uint32_t busy_engines_mask; 344 345 /* 346 * Extended Bitmask of busy engines. 347 * Bits definition is according to `enum <chip>_enging_id'. 348 */ 349 uint64_t busy_engines_mask_ext[HL_BUSY_ENGINES_MASK_EXT_SIZE]; 350 }; 351 352 struct hl_info_device_status { 353 uint32_t status; 354 uint32_t pad; 355 }; 356 357 struct hl_info_device_utilization { 358 uint32_t utilization; 359 uint32_t pad; 360 }; 361 362 struct hl_info_clk_rate { 363 uint32_t cur_clk_rate_mhz; 364 uint32_t max_clk_rate_mhz; 365 }; 366 367 struct hl_info_reset_count { 368 uint32_t hard_reset_cnt; 369 uint32_t soft_reset_cnt; 370 }; 371 372 struct hl_info_time_sync { 373 uint64_t device_time; 374 uint64_t host_time; 375 }; 376 377 /** 378 * struct hl_info_pci_counters - pci counters 379 * @rx_throughput: PCI rx throughput KBps 380 * @tx_throughput: PCI tx throughput KBps 381 * @replay_cnt: PCI replay counter 382 */ 383 struct hl_info_pci_counters { 384 uint64_t rx_throughput; 385 uint64_t tx_throughput; 386 uint64_t replay_cnt; 387 }; 388 389 #define HL_CLK_THROTTLE_POWER 0x1 390 #define HL_CLK_THROTTLE_THERMAL 0x2 391 392 /** 393 * struct hl_info_clk_throttle - clock throttling reason 394 * @clk_throttling_reason: each bit represents a clk throttling reason 395 */ 396 struct hl_info_clk_throttle { 397 uint32_t clk_throttling_reason; 398 }; 399 400 /** 401 * struct hl_info_energy - device energy information 402 * @total_energy_consumption: total device energy consumption 403 */ 404 struct hl_info_energy { 405 uint64_t total_energy_consumption; 406 }; 407 408 #define HL_PLL_NUM_OUTPUTS 4 409 410 struct hl_pll_frequency_info { 411 uint16_t output[HL_PLL_NUM_OUTPUTS]; 412 }; 413 414 /** 415 * struct hl_power_info - power information 416 * @power: power consumption 417 */ 418 struct hl_power_info { 419 uint64_t power; 420 }; 421 422 /** 423 * struct hl_info_sync_manager - sync manager information 424 * @first_available_sync_object: first available sob 425 * @first_available_monitor: first available monitor 426 * @first_available_cq: first available cq 427 */ 428 struct hl_info_sync_manager { 429 uint32_t first_available_sync_object; 430 uint32_t first_available_monitor; 431 uint32_t first_available_cq; 432 uint32_t reserved; 433 }; 434 435 /** 436 * struct hl_info_cs_counters - command submission counters 437 * @total_out_of_mem_drop_cnt: total dropped due to memory allocation issue 438 * @ctx_out_of_mem_drop_cnt: context dropped due to memory allocation issue 439 * @total_parsing_drop_cnt: total dropped due to error in packet parsing 440 * @ctx_parsing_drop_cnt: context dropped due to error in packet parsing 441 * @total_queue_full_drop_cnt: total dropped due to queue full 442 * @ctx_queue_full_drop_cnt: context dropped due to queue full 443 * @total_device_in_reset_drop_cnt: total dropped due to device in reset 444 * @ctx_device_in_reset_drop_cnt: context dropped due to device in reset 445 * @total_max_cs_in_flight_drop_cnt: total dropped due to maximum CS in-flight 446 * @ctx_max_cs_in_flight_drop_cnt: context dropped due to maximum CS in-flight 447 * @total_validation_drop_cnt: total dropped due to validation error 448 * @ctx_validation_drop_cnt: context dropped due to validation error 449 */ 450 struct hl_info_cs_counters { 451 uint64_t total_out_of_mem_drop_cnt; 452 uint64_t ctx_out_of_mem_drop_cnt; 453 uint64_t total_parsing_drop_cnt; 454 uint64_t ctx_parsing_drop_cnt; 455 uint64_t total_queue_full_drop_cnt; 456 uint64_t ctx_queue_full_drop_cnt; 457 uint64_t total_device_in_reset_drop_cnt; 458 uint64_t ctx_device_in_reset_drop_cnt; 459 uint64_t total_max_cs_in_flight_drop_cnt; 460 uint64_t ctx_max_cs_in_flight_drop_cnt; 461 uint64_t total_validation_drop_cnt; 462 uint64_t ctx_validation_drop_cnt; 463 }; 464 465 enum gaudi_dcores { 466 HL_GAUDI_WS_DCORE, 467 HL_GAUDI_WN_DCORE, 468 HL_GAUDI_EN_DCORE, 469 HL_GAUDI_ES_DCORE 470 }; 471 472 struct hl_info_args { 473 /* Location of relevant struct in userspace */ 474 uint64_t return_pointer; 475 /* 476 * The size of the return value. Just like "size" in "snprintf", 477 * it limits how many bytes the kernel can write 478 * 479 * For hw_events array, the size should be 480 * hl_info_hw_ip_info.num_of_events * sizeof(uint32_t) 481 */ 482 uint32_t return_size; 483 484 /* HL_INFO_* */ 485 uint32_t op; 486 487 union { 488 /* Dcore id for which the information is relevant. 489 * For Gaudi refer to 'enum gaudi_dcores' 490 */ 491 uint32_t dcore_id; 492 /* Context ID - Currently not in use */ 493 uint32_t ctx_id; 494 /* Period value for utilization rate (100ms - 1000ms, in 100ms 495 * resolution. 496 */ 497 uint32_t period_ms; 498 /* PLL frequency retrieval */ 499 uint32_t pll_index; 500 }; 501 502 uint32_t pad; 503 }; 504 505 /* Opcode to create a new command buffer */ 506 #define HL_CB_OP_CREATE 0 507 /* Opcode to destroy previously created command buffer */ 508 #define HL_CB_OP_DESTROY 1 509 /* Opcode to retrieve information about a command buffer */ 510 #define HL_CB_OP_INFO 2 511 512 /* 2MB minus 32 bytes for 2xMSG_PROT */ 513 #define HL_MAX_CB_SIZE (0x200000 - 32) 514 515 /* Indicates whether the command buffer should be mapped to the device's MMU */ 516 #define HL_CB_FLAGS_MAP 0x1 517 518 struct hl_cb_in { 519 /* Handle of CB or 0 if we want to create one */ 520 uint64_t cb_handle; 521 /* HL_CB_OP_* */ 522 uint32_t op; 523 /* Size of CB. Maximum size is HL_MAX_CB_SIZE. The minimum size that 524 * will be allocated, regardless of this parameter's value, is PAGE_SIZE 525 */ 526 uint32_t cb_size; 527 /* Context ID - Currently not in use */ 528 uint32_t ctx_id; 529 /* HL_CB_FLAGS_* */ 530 uint32_t flags; 531 }; 532 533 struct hl_cb_out { 534 union { 535 /* Handle of CB */ 536 uint64_t cb_handle; 537 538 /* Information about CB */ 539 struct { 540 /* Usage count of CB */ 541 uint32_t usage_cnt; 542 uint32_t pad; 543 }; 544 }; 545 }; 546 547 union hl_cb_args { 548 struct hl_cb_in in; 549 struct hl_cb_out out; 550 }; 551 552 /* HL_CS_CHUNK_FLAGS_ values 553 * 554 * HL_CS_CHUNK_FLAGS_USER_ALLOC_CB: 555 * Indicates if the CB was allocated and mapped by userspace. 556 * User allocated CB is a command buffer allocated by the user, via malloc 557 * (or similar). After allocating the CB, the user invokes “memory ioctl” 558 * to map the user memory into a device virtual address. The user provides 559 * this address via the cb_handle field. The interface provides the 560 * ability to create a large CBs, Which aren’t limited to 561 * “HL_MAX_CB_SIZE”. Therefore, it increases the PCI-DMA queues 562 * throughput. This CB allocation method also reduces the use of Linux 563 * DMA-able memory pool. Which are limited and used by other Linux 564 * sub-systems. 565 */ 566 #define HL_CS_CHUNK_FLAGS_USER_ALLOC_CB 0x1 567 568 /* 569 * This structure size must always be fixed to 64-bytes for backward 570 * compatibility 571 */ 572 struct hl_cs_chunk { 573 union { 574 /* For external queue, this represents a Handle of CB on the 575 * Host. 576 * For internal queue in Goya, this represents an SRAM or 577 * a DRAM address of the internal CB. In Gaudi, this might also 578 * represent a mapped host address of the CB. 579 * 580 * A mapped host address is in the device address space, after 581 * a host address was mapped by the device MMU. 582 */ 583 uint64_t cb_handle; 584 585 /* Relevant only when HL_CS_FLAGS_WAIT or 586 * HL_CS_FLAGS_COLLECTIVE_WAIT is set. 587 * This holds address of array of u64 values that contain 588 * signal CS sequence numbers. The wait described by this job 589 * will listen on all those signals (wait event per signal) 590 */ 591 uint64_t signal_seq_arr; 592 }; 593 594 /* Index of queue to put the CB on */ 595 uint32_t queue_index; 596 597 union { 598 /* 599 * Size of command buffer with valid packets 600 * Can be smaller then actual CB size 601 */ 602 uint32_t cb_size; 603 604 /* Relevant only when HL_CS_FLAGS_WAIT or 605 * HL_CS_FLAGS_COLLECTIVE_WAIT is set. 606 * Number of entries in signal_seq_arr 607 */ 608 uint32_t num_signal_seq_arr; 609 }; 610 611 /* HL_CS_CHUNK_FLAGS_* */ 612 uint32_t cs_chunk_flags; 613 614 /* Relevant only when HL_CS_FLAGS_COLLECTIVE_WAIT is set. 615 * This holds the collective engine ID. The wait described by this job 616 * will sync with this engine and with all NICs before completion. 617 */ 618 uint32_t collective_engine_id; 619 620 /* Align structure to 64 bytes */ 621 uint32_t pad[10]; 622 }; 623 624 /* SIGNAL and WAIT/COLLECTIVE_WAIT flags are mutually exclusive */ 625 #define HL_CS_FLAGS_FORCE_RESTORE 0x1 626 #define HL_CS_FLAGS_SIGNAL 0x2 627 #define HL_CS_FLAGS_WAIT 0x4 628 #define HL_CS_FLAGS_COLLECTIVE_WAIT 0x8 629 #define HL_CS_FLAGS_TIMESTAMP 0x20 630 #define HL_CS_FLAGS_STAGED_SUBMISSION 0x40 631 #define HL_CS_FLAGS_STAGED_SUBMISSION_FIRST 0x80 632 #define HL_CS_FLAGS_STAGED_SUBMISSION_LAST 0x100 633 #define HL_CS_FLAGS_CUSTOM_TIMEOUT 0x200 634 635 #define HL_CS_STATUS_SUCCESS 0 636 637 #define HL_MAX_JOBS_PER_CS 512 638 639 struct hl_cs_in { 640 641 /* this holds address of array of hl_cs_chunk for restore phase */ 642 uint64_t chunks_restore; 643 644 /* holds address of array of hl_cs_chunk for execution phase */ 645 uint64_t chunks_execute; 646 647 /* Sequence number of a staged submission CS 648 * valid only if HL_CS_FLAGS_STAGED_SUBMISSION is set 649 */ 650 uint64_t seq; 651 652 /* Number of chunks in restore phase array. Maximum number is 653 * HL_MAX_JOBS_PER_CS 654 */ 655 uint32_t num_chunks_restore; 656 657 /* Number of chunks in execution array. Maximum number is 658 * HL_MAX_JOBS_PER_CS 659 */ 660 uint32_t num_chunks_execute; 661 662 /* timeout in seconds - valid only if HL_CS_FLAGS_CUSTOM_TIMEOUT 663 * is set 664 */ 665 uint32_t timeout; 666 667 /* HL_CS_FLAGS_* */ 668 uint32_t cs_flags; 669 670 /* Context ID - Currently not in use */ 671 uint32_t ctx_id; 672 }; 673 674 struct hl_cs_out { 675 /* 676 * seq holds the sequence number of the CS to pass to wait ioctl. All 677 * values are valid except for 0 and ULLONG_MAX 678 */ 679 uint64_t seq; 680 /* HL_CS_STATUS_* */ 681 uint32_t status; 682 uint32_t pad; 683 }; 684 685 union hl_cs_args { 686 struct hl_cs_in in; 687 struct hl_cs_out out; 688 }; 689 690 #define HL_WAIT_CS_FLAGS_INTERRUPT 0x2 691 #define HL_WAIT_CS_FLAGS_INTERRUPT_MASK 0xFFF00000 692 693 struct hl_wait_cs_in { 694 union { 695 struct { 696 /* Command submission sequence number */ 697 uint64_t seq; 698 /* Absolute timeout to wait for command submission 699 * in microseconds 700 */ 701 uint64_t timeout_us; 702 }; 703 704 struct { 705 /* User address for completion comparison. 706 * upon interrupt, driver will compare the value pointed 707 * by this address with the supplied target value. 708 * in order not to perform any comparison, set address 709 * to all 1s. 710 * Relevant only when HL_WAIT_CS_FLAGS_INTERRUPT is set 711 */ 712 uint64_t addr; 713 /* Target value for completion comparison */ 714 uint32_t target; 715 /* Absolute timeout to wait for interrupt 716 * in microseconds 717 */ 718 uint32_t interrupt_timeout_us; 719 }; 720 }; 721 722 /* Context ID - Currently not in use */ 723 uint32_t ctx_id; 724 /* HL_WAIT_CS_FLAGS_* 725 * If HL_WAIT_CS_FLAGS_INTERRUPT is set, this field should include 726 * interrupt id according to HL_WAIT_CS_FLAGS_INTERRUPT_MASK, in order 727 * not to specify an interrupt id ,set mask to all 1s. 728 */ 729 uint32_t flags; 730 }; 731 732 #define HL_WAIT_CS_STATUS_COMPLETED 0 733 #define HL_WAIT_CS_STATUS_BUSY 1 734 #define HL_WAIT_CS_STATUS_TIMEDOUT 2 735 #define HL_WAIT_CS_STATUS_ABORTED 3 736 #define HL_WAIT_CS_STATUS_INTERRUPTED 4 737 738 #define HL_WAIT_CS_STATUS_FLAG_GONE 0x1 739 #define HL_WAIT_CS_STATUS_FLAG_TIMESTAMP_VLD 0x2 740 741 struct hl_wait_cs_out { 742 /* HL_WAIT_CS_STATUS_* */ 743 uint32_t status; 744 /* HL_WAIT_CS_STATUS_FLAG* */ 745 uint32_t flags; 746 /* valid only if HL_WAIT_CS_STATUS_FLAG_TIMESTAMP_VLD is set */ 747 int64_t timestamp_nsec; 748 }; 749 750 union hl_wait_cs_args { 751 struct hl_wait_cs_in in; 752 struct hl_wait_cs_out out; 753 }; 754 755 /* Opcode to allocate device memory */ 756 #define HL_MEM_OP_ALLOC 0 757 /* Opcode to free previously allocated device memory */ 758 #define HL_MEM_OP_FREE 1 759 /* Opcode to map host and device memory */ 760 #define HL_MEM_OP_MAP 2 761 /* Opcode to unmap previously mapped host and device memory */ 762 #define HL_MEM_OP_UNMAP 3 763 /* Opcode to map a hw block */ 764 #define HL_MEM_OP_MAP_BLOCK 4 765 766 /* Memory flags */ 767 #define HL_MEM_CONTIGUOUS 0x1 768 #define HL_MEM_SHARED 0x2 769 #define HL_MEM_USERPTR 0x4 770 771 struct hl_mem_in { 772 union { 773 /* HL_MEM_OP_ALLOC- allocate device memory */ 774 struct { 775 /* Size to alloc */ 776 uint64_t mem_size; 777 } alloc; 778 779 /* HL_MEM_OP_FREE - free device memory */ 780 struct { 781 /* Handle returned from HL_MEM_OP_ALLOC */ 782 uint64_t handle; 783 } free; 784 785 /* HL_MEM_OP_MAP - map device memory */ 786 struct { 787 /* 788 * Requested virtual address of mapped memory. 789 * The driver will try to map the requested region to 790 * this hint address, as long as the address is valid 791 * and not already mapped. The user should check the 792 * returned address of the IOCTL to make sure he got 793 * the hint address. Passing 0 here means that the 794 * driver will choose the address itself. 795 */ 796 uint64_t hint_addr; 797 /* Handle returned from HL_MEM_OP_ALLOC */ 798 uint64_t handle; 799 } map_device; 800 801 /* HL_MEM_OP_MAP - map host memory */ 802 struct { 803 /* Address of allocated host memory */ 804 uint64_t host_virt_addr; 805 /* 806 * Requested virtual address of mapped memory. 807 * The driver will try to map the requested region to 808 * this hint address, as long as the address is valid 809 * and not already mapped. The user should check the 810 * returned address of the IOCTL to make sure he got 811 * the hint address. Passing 0 here means that the 812 * driver will choose the address itself. 813 */ 814 uint64_t hint_addr; 815 /* Size of allocated host memory */ 816 uint64_t mem_size; 817 } map_host; 818 819 /* HL_MEM_OP_MAP_BLOCK - map a hw block */ 820 struct { 821 /* 822 * HW block address to map, a handle and size will be 823 * returned to the user and will be used to mmap the 824 * relevant block. Only addresses from configuration 825 * space are allowed. 826 */ 827 uint64_t block_addr; 828 } map_block; 829 830 /* HL_MEM_OP_UNMAP - unmap host memory */ 831 struct { 832 /* Virtual address returned from HL_MEM_OP_MAP */ 833 uint64_t device_virt_addr; 834 } unmap; 835 }; 836 837 /* HL_MEM_OP_* */ 838 uint32_t op; 839 /* HL_MEM_* flags */ 840 uint32_t flags; 841 /* Context ID - Currently not in use */ 842 uint32_t ctx_id; 843 uint32_t pad; 844 }; 845 846 struct hl_mem_out { 847 union { 848 /* 849 * Used for HL_MEM_OP_MAP as the virtual address that was 850 * assigned in the device VA space. 851 * A value of 0 means the requested operation failed. 852 */ 853 uint64_t device_virt_addr; 854 855 /* 856 * Used in HL_MEM_OP_ALLOC 857 * This is the assigned handle for the allocated memory 858 */ 859 uint64_t handle; 860 861 struct { 862 /* 863 * Used in HL_MEM_OP_MAP_BLOCK. 864 * This is the assigned handle for the mapped block 865 */ 866 uint64_t block_handle; 867 868 /* 869 * Used in HL_MEM_OP_MAP_BLOCK 870 * This is the size of the mapped block 871 */ 872 uint32_t block_size; 873 874 uint32_t pad; 875 }; 876 }; 877 }; 878 879 union hl_mem_args { 880 struct hl_mem_in in; 881 struct hl_mem_out out; 882 }; 883 884 #define HL_DEBUG_MAX_AUX_VALUES 10 885 886 struct hl_debug_params_etr { 887 /* Address in memory to allocate buffer */ 888 uint64_t buffer_address; 889 890 /* Size of buffer to allocate */ 891 uint64_t buffer_size; 892 893 /* Sink operation mode: SW fifo, HW fifo, Circular buffer */ 894 uint32_t sink_mode; 895 uint32_t pad; 896 }; 897 898 struct hl_debug_params_etf { 899 /* Address in memory to allocate buffer */ 900 uint64_t buffer_address; 901 902 /* Size of buffer to allocate */ 903 uint64_t buffer_size; 904 905 /* Sink operation mode: SW fifo, HW fifo, Circular buffer */ 906 uint32_t sink_mode; 907 uint32_t pad; 908 }; 909 910 struct hl_debug_params_stm { 911 /* Two bit masks for HW event and Stimulus Port */ 912 uint64_t he_mask; 913 uint64_t sp_mask; 914 915 /* Trace source ID */ 916 uint32_t id; 917 918 /* Frequency for the timestamp register */ 919 uint32_t frequency; 920 }; 921 922 struct hl_debug_params_bmon { 923 /* Two address ranges that the user can request to filter */ 924 uint64_t start_addr0; 925 uint64_t addr_mask0; 926 927 uint64_t start_addr1; 928 uint64_t addr_mask1; 929 930 /* Capture window configuration */ 931 uint32_t bw_win; 932 uint32_t win_capture; 933 934 /* Trace source ID */ 935 uint32_t id; 936 uint32_t pad; 937 }; 938 939 struct hl_debug_params_spmu { 940 /* Event types selection */ 941 uint64_t event_types[HL_DEBUG_MAX_AUX_VALUES]; 942 943 /* Number of event types selection */ 944 uint32_t event_types_num; 945 uint32_t pad; 946 }; 947 948 /* Opcode for ETR component */ 949 #define HL_DEBUG_OP_ETR 0 950 /* Opcode for ETF component */ 951 #define HL_DEBUG_OP_ETF 1 952 /* Opcode for STM component */ 953 #define HL_DEBUG_OP_STM 2 954 /* Opcode for FUNNEL component */ 955 #define HL_DEBUG_OP_FUNNEL 3 956 /* Opcode for BMON component */ 957 #define HL_DEBUG_OP_BMON 4 958 /* Opcode for SPMU component */ 959 #define HL_DEBUG_OP_SPMU 5 960 /* Opcode for timestamp (deprecated) */ 961 #define HL_DEBUG_OP_TIMESTAMP 6 962 /* Opcode for setting the device into or out of debug mode. The enable 963 * variable should be 1 for enabling debug mode and 0 for disabling it 964 */ 965 #define HL_DEBUG_OP_SET_MODE 7 966 967 struct hl_debug_args { 968 /* 969 * Pointer to user input structure. 970 * This field is relevant to specific opcodes. 971 */ 972 uint64_t input_ptr; 973 /* Pointer to user output structure */ 974 uint64_t output_ptr; 975 /* Size of user input structure */ 976 uint32_t input_size; 977 /* Size of user output structure */ 978 uint32_t output_size; 979 /* HL_DEBUG_OP_* */ 980 uint32_t op; 981 /* 982 * Register index in the component, taken from the debug_regs_index enum 983 * in the various ASIC header files 984 */ 985 uint32_t reg_idx; 986 /* Enable/disable */ 987 uint32_t enable; 988 /* Context ID - Currently not in use */ 989 uint32_t ctx_id; 990 }; 991 992 /* 993 * Various information operations such as: 994 * - H/W IP information 995 * - Current dram usage 996 * 997 * The user calls this IOCTL with an opcode that describes the required 998 * information. The user should supply a pointer to a user-allocated memory 999 * chunk, which will be filled by the driver with the requested information. 1000 * 1001 * The user supplies the maximum amount of size to copy into the user's memory, 1002 * in order to prevent data corruption in case of differences between the 1003 * definitions of structures in kernel and userspace, e.g. in case of old 1004 * userspace and new kernel driver 1005 */ 1006 #define HL_IOCTL_INFO \ 1007 _IOWR('H', 0x01, struct hl_info_args) 1008 1009 /* 1010 * Command Buffer 1011 * - Request a Command Buffer 1012 * - Destroy a Command Buffer 1013 * 1014 * The command buffers are memory blocks that reside in DMA-able address 1015 * space and are physically contiguous so they can be accessed by the device 1016 * directly. They are allocated using the coherent DMA API. 1017 * 1018 * When creating a new CB, the IOCTL returns a handle of it, and the user-space 1019 * process needs to use that handle to mmap the buffer so it can access them. 1020 * 1021 * In some instances, the device must access the command buffer through the 1022 * device's MMU, and thus its memory should be mapped. In these cases, user can 1023 * indicate the driver that such a mapping is required. 1024 * The resulting device virtual address will be used internally by the driver, 1025 * and won't be returned to user. 1026 * 1027 */ 1028 #define HL_IOCTL_CB \ 1029 _IOWR('H', 0x02, union hl_cb_args) 1030 1031 /* 1032 * Command Submission 1033 * 1034 * To submit work to the device, the user need to call this IOCTL with a set 1035 * of JOBS. That set of JOBS constitutes a CS object. 1036 * Each JOB will be enqueued on a specific queue, according to the user's input. 1037 * There can be more then one JOB per queue. 1038 * 1039 * The CS IOCTL will receive two sets of JOBS. One set is for "restore" phase 1040 * and a second set is for "execution" phase. 1041 * The JOBS on the "restore" phase are enqueued only after context-switch 1042 * (or if its the first CS for this context). The user can also order the 1043 * driver to run the "restore" phase explicitly 1044 * 1045 * There are two types of queues - external and internal. External queues 1046 * are DMA queues which transfer data from/to the Host. All other queues are 1047 * internal. The driver will get completion notifications from the device only 1048 * on JOBS which are enqueued in the external queues. 1049 * 1050 * For jobs on external queues, the user needs to create command buffers 1051 * through the CB ioctl and give the CB's handle to the CS ioctl. For jobs on 1052 * internal queues, the user needs to prepare a "command buffer" with packets 1053 * on either the device SRAM/DRAM or the host, and give the device address of 1054 * that buffer to the CS ioctl. 1055 * 1056 * This IOCTL is asynchronous in regard to the actual execution of the CS. This 1057 * means it returns immediately after ALL the JOBS were enqueued on their 1058 * relevant queues. Therefore, the user mustn't assume the CS has been completed 1059 * or has even started to execute. 1060 * 1061 * Upon successful enqueue, the IOCTL returns a sequence number which the user 1062 * can use with the "Wait for CS" IOCTL to check whether the handle's CS 1063 * external JOBS have been completed. Note that if the CS has internal JOBS 1064 * which can execute AFTER the external JOBS have finished, the driver might 1065 * report that the CS has finished executing BEFORE the internal JOBS have 1066 * actually finished executing. 1067 * 1068 * Even though the sequence number increments per CS, the user can NOT 1069 * automatically assume that if CS with sequence number N finished, then CS 1070 * with sequence number N-1 also finished. The user can make this assumption if 1071 * and only if CS N and CS N-1 are exactly the same (same CBs for the same 1072 * queues). 1073 */ 1074 #define HL_IOCTL_CS \ 1075 _IOWR('H', 0x03, union hl_cs_args) 1076 1077 /* 1078 * Wait for Command Submission 1079 * 1080 * The user can call this IOCTL with a handle it received from the CS IOCTL 1081 * to wait until the handle's CS has finished executing. The user will wait 1082 * inside the kernel until the CS has finished or until the user-requested 1083 * timeout has expired. 1084 * 1085 * If the timeout value is 0, the driver won't sleep at all. It will check 1086 * the status of the CS and return immediately 1087 * 1088 * The return value of the IOCTL is a standard Linux error code. The possible 1089 * values are: 1090 * 1091 * EINTR - Kernel waiting has been interrupted, e.g. due to OS signal 1092 * that the user process received 1093 * ETIMEDOUT - The CS has caused a timeout on the device 1094 * EIO - The CS was aborted (usually because the device was reset) 1095 * ENODEV - The device wants to do hard-reset (so user need to close FD) 1096 * 1097 * The driver also returns a custom define inside the IOCTL which can be: 1098 * 1099 * HL_WAIT_CS_STATUS_COMPLETED - The CS has been completed successfully (0) 1100 * HL_WAIT_CS_STATUS_BUSY - The CS is still executing (0) 1101 * HL_WAIT_CS_STATUS_TIMEDOUT - The CS has caused a timeout on the device 1102 * (ETIMEDOUT) 1103 * HL_WAIT_CS_STATUS_ABORTED - The CS was aborted, usually because the 1104 * device was reset (EIO) 1105 * HL_WAIT_CS_STATUS_INTERRUPTED - Waiting for the CS was interrupted (EINTR) 1106 * 1107 */ 1108 1109 #define HL_IOCTL_WAIT_CS \ 1110 _IOWR('H', 0x04, union hl_wait_cs_args) 1111 1112 /* 1113 * Memory 1114 * - Map host memory to device MMU 1115 * - Unmap host memory from device MMU 1116 * 1117 * This IOCTL allows the user to map host memory to the device MMU 1118 * 1119 * For host memory, the IOCTL doesn't allocate memory. The user is supposed 1120 * to allocate the memory in user-space (malloc/new). The driver pins the 1121 * physical pages (up to the allowed limit by the OS), assigns a virtual 1122 * address in the device VA space and initializes the device MMU. 1123 * 1124 * There is an option for the user to specify the requested virtual address. 1125 * 1126 */ 1127 #define HL_IOCTL_MEMORY \ 1128 _IOWR('H', 0x05, union hl_mem_args) 1129 1130 /* 1131 * Debug 1132 * - Enable/disable the ETR/ETF/FUNNEL/STM/BMON/SPMU debug traces 1133 * 1134 * This IOCTL allows the user to get debug traces from the chip. 1135 * 1136 * Before the user can send configuration requests of the various 1137 * debug/profile engines, it needs to set the device into debug mode. 1138 * This is because the debug/profile infrastructure is shared component in the 1139 * device and we can't allow multiple users to access it at the same time. 1140 * 1141 * Once a user set the device into debug mode, the driver won't allow other 1142 * users to "work" with the device, i.e. open a FD. If there are multiple users 1143 * opened on the device, the driver won't allow any user to debug the device. 1144 * 1145 * For each configuration request, the user needs to provide the register index 1146 * and essential data such as buffer address and size. 1147 * 1148 * Once the user has finished using the debug/profile engines, he should 1149 * set the device into non-debug mode, i.e. disable debug mode. 1150 * 1151 * The driver can decide to "kick out" the user if he abuses this interface. 1152 * 1153 */ 1154 #define HL_IOCTL_DEBUG \ 1155 _IOWR('H', 0x06, struct hl_debug_args) 1156 1157 #define HL_COMMAND_START 0x01 1158 #define HL_COMMAND_END 0x07 1159 1160 #endif /* HABANALABS_H_ */ 1161