1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include <dt-bindings/input/gpio-keys.h>
5#include <dt-bindings/input/input.h>
6#include <dt-bindings/thermal/thermal.h>
7
8#include "tegra20.dtsi"
9#include "tegra20-cpu-opp.dtsi"
10#include "tegra20-cpu-opp-microvolt.dtsi"
11
12/ {
13	model = "Acer Iconia Tab A500";
14	compatible = "acer,picasso", "nvidia,tegra20";
15
16	aliases {
17		mmc0 = &sdmmc4; /* eMMC */
18		mmc1 = &sdmmc3; /* MicroSD */
19		mmc2 = &sdmmc1; /* WiFi */
20
21		rtc0 = &pmic;
22		rtc1 = "/rtc@7000e000";
23
24		serial0 = &uartd; /* Docking station */
25		serial1 = &uartc; /* Bluetooth */
26		serial2 = &uartb; /* GPS */
27	};
28
29	/*
30	 * The decompressor and also some bootloaders rely on a
31	 * pre-existing /chosen node to be available to insert the
32	 * command line and merge other ATAGS info.
33	 */
34	chosen {};
35
36	memory@0 {
37		reg = <0x00000000 0x40000000>;
38	};
39
40	reserved-memory {
41		#address-cells = <1>;
42		#size-cells = <1>;
43		ranges;
44
45		ramoops@2ffe0000 {
46			compatible = "ramoops";
47			reg = <0x2ffe0000 0x10000>;	/* 64kB */
48			console-size = <0x8000>;	/* 32kB */
49			record-size = <0x400>;		/*  1kB */
50			ecc-size = <16>;
51		};
52
53		linux,cma@30000000 {
54			compatible = "shared-dma-pool";
55			alloc-ranges = <0x30000000 0x10000000>;
56			size = <0x10000000>; /* 256MiB */
57			linux,cma-default;
58			reusable;
59		};
60	};
61
62	host1x@50000000 {
63		dc@54200000 {
64			rgb {
65				status = "okay";
66
67				port@0 {
68					lcd_output: endpoint {
69						remote-endpoint = <&lvds_encoder_input>;
70						bus-width = <18>;
71					};
72				};
73			};
74		};
75
76		hdmi@54280000 {
77			status = "okay";
78
79			vdd-supply = <&hdmi_vdd_reg>;
80			pll-supply = <&hdmi_pll_reg>;
81			hdmi-supply = <&vdd_5v0_sys>;
82
83			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
84			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
85				GPIO_ACTIVE_HIGH>;
86		};
87	};
88
89	pinmux@70000014 {
90		pinctrl-names = "default";
91		pinctrl-0 = <&state_default>;
92
93		state_default: pinmux {
94			ata {
95				nvidia,pins = "ata";
96				nvidia,function = "ide";
97			};
98			atb {
99				nvidia,pins = "atb", "gma", "gme";
100				nvidia,function = "sdio4";
101			};
102			atc {
103				nvidia,pins = "atc";
104				nvidia,function = "nand";
105			};
106			atd {
107				nvidia,pins = "atd", "ate", "gmb", "spia",
108					"spib", "spic";
109				nvidia,function = "gmi";
110			};
111			cdev1 {
112				nvidia,pins = "cdev1";
113				nvidia,function = "plla_out";
114			};
115			cdev2 {
116				nvidia,pins = "cdev2";
117				nvidia,function = "pllp_out4";
118			};
119			crtp {
120				nvidia,pins = "crtp", "lm1";
121				nvidia,function = "crt";
122			};
123			csus {
124				nvidia,pins = "csus";
125				nvidia,function = "vi_sensor_clk";
126			};
127			dap1 {
128				nvidia,pins = "dap1";
129				nvidia,function = "dap1";
130			};
131			dap2 {
132				nvidia,pins = "dap2";
133				nvidia,function = "dap2";
134			};
135			dap3 {
136				nvidia,pins = "dap3";
137				nvidia,function = "dap3";
138			};
139			dap4 {
140				nvidia,pins = "dap4";
141				nvidia,function = "dap4";
142			};
143			dta {
144				nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
145				nvidia,function = "vi";
146			};
147			dtf {
148				nvidia,pins = "dtf";
149				nvidia,function = "i2c3";
150			};
151			gmc {
152				nvidia,pins = "gmc";
153				nvidia,function = "uartd";
154			};
155			gmd {
156				nvidia,pins = "gmd";
157				nvidia,function = "sflash";
158			};
159			gpu {
160				nvidia,pins = "gpu";
161				nvidia,function = "pwm";
162			};
163			gpu7 {
164				nvidia,pins = "gpu7";
165				nvidia,function = "rtck";
166			};
167			gpv {
168				nvidia,pins = "gpv", "slxa";
169				nvidia,function = "pcie";
170			};
171			hdint {
172				nvidia,pins = "hdint";
173				nvidia,function = "hdmi";
174			};
175			i2cp {
176				nvidia,pins = "i2cp";
177				nvidia,function = "i2cp";
178			};
179			irrx {
180				nvidia,pins = "irrx", "irtx";
181				nvidia,function = "uartb";
182			};
183			kbca {
184				nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
185					"kbce", "kbcf";
186				nvidia,function = "kbc";
187			};
188			lcsn {
189				nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
190					"lsdi", "lvp0";
191				nvidia,function = "rsvd4";
192			};
193			ld0 {
194				nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
195					"ld5", "ld6", "ld7", "ld8", "ld9",
196					"ld10", "ld11", "ld12", "ld13", "ld14",
197					"ld15", "ld16", "ld17", "ldi", "lhp0",
198					"lhp1", "lhp2", "lhs", "lpp", "lsc0",
199					"lsc1", "lsck", "lsda", "lspi", "lvp1",
200					"lvs";
201				nvidia,function = "displaya";
202			};
203			owc {
204				nvidia,pins = "owc", "spdi", "spdo", "uac";
205				nvidia,function = "rsvd2";
206			};
207			pmc {
208				nvidia,pins = "pmc";
209				nvidia,function = "pwr_on";
210			};
211			rm {
212				nvidia,pins = "rm";
213				nvidia,function = "i2c1";
214			};
215			sdb {
216				nvidia,pins = "sdb", "sdc", "sdd", "slxc", "slxk";
217				nvidia,function = "sdio3";
218			};
219			sdio1 {
220				nvidia,pins = "sdio1";
221				nvidia,function = "sdio1";
222			};
223			slxd {
224				nvidia,pins = "slxd";
225				nvidia,function = "spdif";
226			};
227			spid {
228				nvidia,pins = "spid", "spie", "spif";
229				nvidia,function = "spi1";
230			};
231			spig {
232				nvidia,pins = "spig", "spih";
233				nvidia,function = "spi2_alt";
234			};
235			uaa {
236				nvidia,pins = "uaa", "uab", "uda";
237				nvidia,function = "ulpi";
238			};
239			uad {
240				nvidia,pins = "uad";
241				nvidia,function = "irda";
242			};
243			uca {
244				nvidia,pins = "uca", "ucb";
245				nvidia,function = "uartc";
246			};
247			conf_ata {
248				nvidia,pins = "ata", "atb", "atc", "atd",
249					"cdev1", "cdev2", "csus", "dap1",
250					"dap4", "dte", "dtf", "gma", "gmc",
251					"gme", "gpu", "gpu7", "gpv", "i2cp",
252					"irrx", "irtx", "pta", "rm",
253					"sdc", "sdd", "slxc", "slxd", "slxk",
254					"spdi", "spdo", "uac", "uad", "uda";
255				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
256				nvidia,tristate = <TEGRA_PIN_DISABLE>;
257			};
258			conf_ate {
259				nvidia,pins = "ate", "dap2", "dap3",
260					"gmd", "owc", "spia", "spib", "spic",
261					"spid", "spie";
262				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
263				nvidia,tristate = <TEGRA_PIN_ENABLE>;
264			};
265			conf_ck32 {
266				nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
267					"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
268				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
269			};
270			conf_crtp {
271				nvidia,pins = "crtp", "gmb", "slxa", "spig",
272					"spih";
273				nvidia,pull = <TEGRA_PIN_PULL_UP>;
274				nvidia,tristate = <TEGRA_PIN_ENABLE>;
275			};
276			conf_dta {
277				nvidia,pins = "dta", "dtb", "dtc", "dtd", "kbcb";
278				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
279				nvidia,tristate = <TEGRA_PIN_DISABLE>;
280			};
281			conf_dte {
282				nvidia,pins = "spif";
283				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
284				nvidia,tristate = <TEGRA_PIN_ENABLE>;
285			};
286			conf_hdint {
287				nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
288					"lpw1", "lsck", "lsda", "lsdi",
289					"lvp0";
290				nvidia,tristate = <TEGRA_PIN_ENABLE>;
291			};
292			conf_kbca {
293				nvidia,pins = "kbca", "kbcc", "kbcd",
294					"kbce", "kbcf", "sdio1", "uaa",
295					"uab", "uca", "ucb";
296				nvidia,pull = <TEGRA_PIN_PULL_UP>;
297				nvidia,tristate = <TEGRA_PIN_DISABLE>;
298			};
299			conf_lc {
300				nvidia,pins = "lc", "ls";
301				nvidia,pull = <TEGRA_PIN_PULL_UP>;
302			};
303			conf_ld0 {
304				nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
305					"ld5", "ld6", "ld7", "ld8", "ld9",
306					"ld10", "ld11", "ld12", "ld13", "ld14",
307					"ld15", "ld16", "ld17", "ldi", "lhp0",
308					"lhp1", "lhp2", "lhs", "lm0", "lpp",
309					"lpw0", "lpw2", "lsc0", "lsc1", "lspi",
310					"lvp1", "lvs", "pmc", "sdb";
311				nvidia,tristate = <TEGRA_PIN_DISABLE>;
312			};
313			conf_ld17_0 {
314				nvidia,pins = "ld17_0";
315				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
316			};
317			drive_ddc {
318				nvidia,pins = "drive_ddc",
319						"drive_vi1",
320						"drive_sdio1";
321				nvidia,pull-up-strength = <31>;
322				nvidia,pull-down-strength = <31>;
323				nvidia,schmitt = <TEGRA_PIN_ENABLE>;
324				nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
325				nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
326				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
327				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
328			};
329			drive_dbg {
330				nvidia,pins = "drive_dbg",
331						"drive_vi2",
332						"drive_at1",
333						"drive_ao1";
334				nvidia,pull-up-strength = <31>;
335				nvidia,pull-down-strength = <31>;
336				nvidia,schmitt = <TEGRA_PIN_ENABLE>;
337				nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
338				nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
339				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
340				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
341			};
342		};
343
344		state_i2cmux_ddc: pinmux_i2cmux_ddc {
345			ddc {
346				nvidia,pins = "ddc";
347				nvidia,function = "i2c2";
348			};
349			pta {
350				nvidia,pins = "pta";
351				nvidia,function = "rsvd4";
352			};
353		};
354
355		state_i2cmux_pta: pinmux_i2cmux_pta {
356			ddc {
357				nvidia,pins = "ddc";
358				nvidia,function = "rsvd4";
359			};
360			pta {
361				nvidia,pins = "pta";
362				nvidia,function = "i2c2";
363			};
364		};
365
366		state_i2cmux_idle: pinmux_i2cmux_idle {
367			ddc {
368				nvidia,pins = "ddc";
369				nvidia,function = "rsvd4";
370			};
371			pta {
372				nvidia,pins = "pta";
373				nvidia,function = "rsvd4";
374			};
375		};
376	};
377
378	tegra_i2s1: i2s@70002800 {
379		status = "okay";
380	};
381
382	uartb: serial@70006040 {
383		compatible = "nvidia,tegra20-hsuart";
384		/* GPS BCM4751 */
385	};
386
387	uartc: serial@70006200 {
388		compatible = "nvidia,tegra20-hsuart";
389		status = "okay";
390
391		/* Azurewave AW-NH665 BCM4329B1 */
392		bluetooth {
393			compatible = "brcm,bcm4329-bt";
394
395			/* PLLP 216MHz / 16 / 4 */
396			max-speed = <3375000>;
397
398			clocks = <&rtc_32k_wifi>;
399			clock-names = "txco";
400
401			vbat-supply  = <&vdd_3v3_sys>;
402			vddio-supply = <&vdd_1v8_sys>;
403
404			device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>;
405			host-wakeup-gpios =   <&gpio TEGRA_GPIO(U, 6) GPIO_ACTIVE_HIGH>;
406			shutdown-gpios =      <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
407		};
408	};
409
410	uartd: serial@70006300 {
411		/* Docking station */
412	};
413
414	i2c@7000c000 {
415		clock-frequency = <400000>;
416		status = "okay";
417
418		wm8903: audio-codec@1a {
419			compatible = "wlf,wm8903";
420			reg = <0x1a>;
421
422			interrupt-parent = <&gpio>;
423			interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
424
425			gpio-controller;
426			#gpio-cells = <2>;
427
428			gpio-cfg = <
429				0x0000 /* MIC_LR_OUT#    GPIO, output, low */
430				0x0000 /* FM2018-enable  GPIO, output, low */
431				0x0000 /* Speaker-enable GPIO, output, low */
432				0x0200 /* Interrupt, output */
433				0x01a0 /* BCLK, input, active high */
434			>;
435
436			AVDD-supply  = <&vdd_1v8_sys>;
437			CPVDD-supply = <&vdd_1v8_sys>;
438			DBVDD-supply = <&vdd_1v8_sys>;
439			DCVDD-supply = <&vdd_1v8_sys>;
440		};
441
442		touchscreen@4c {
443			compatible = "atmel,maxtouch";
444			reg = <0x4c>;
445
446			interrupt-parent = <&gpio>;
447			interrupts = <TEGRA_GPIO(V, 6) IRQ_TYPE_LEVEL_LOW>;
448
449			reset-gpios = <&gpio TEGRA_GPIO(Q, 7) GPIO_ACTIVE_LOW>;
450
451			vdda-supply = <&vdd_3v3_sys>;
452			vdd-supply  = <&vdd_3v3_sys>;
453
454			atmel,wakeup-method = <1>;
455		};
456
457		gyroscope@68 {
458			compatible = "invensense,mpu3050";
459			reg = <0x68>;
460
461			interrupt-parent = <&gpio>;
462			interrupts = <TEGRA_GPIO(Z, 4) IRQ_TYPE_EDGE_RISING>;
463
464			vdd-supply    = <&vdd_3v3_sys>;
465			vlogic-supply = <&vdd_1v8_sys>;
466
467			mount-matrix =	 "0",  "1",  "0",
468					 "1",  "0",  "0",
469					 "0",  "0", "-1";
470
471			i2c-gate {
472				#address-cells = <1>;
473				#size-cells = <0>;
474
475				accelerometer@f {
476					compatible = "kionix,kxtf9";
477					reg = <0x0f>;
478
479					interrupt-parent = <&gpio>;
480					interrupts = <TEGRA_GPIO(S, 7) IRQ_TYPE_EDGE_RISING>;
481
482					mount-matrix =	 "0",  "1",  "0",
483							 "1",  "0",  "0",
484							 "0",  "0", "-1";
485				};
486			};
487		};
488	};
489
490	i2c@7000c400 {
491		clock-frequency = <10000>;
492		status = "okay";
493	};
494
495	i2cmux {
496		compatible = "i2c-mux-pinctrl";
497		#address-cells = <1>;
498		#size-cells = <0>;
499
500		i2c-parent = <&{/i2c@7000c400}>;
501
502		pinctrl-names = "ddc", "pta", "idle";
503		pinctrl-0 = <&state_i2cmux_ddc>;
504		pinctrl-1 = <&state_i2cmux_pta>;
505		pinctrl-2 = <&state_i2cmux_idle>;
506
507		hdmi_ddc: i2c@0 {
508			reg = <0>;
509			#address-cells = <1>;
510			#size-cells = <0>;
511		};
512
513		panel_ddc: i2c@1 {
514			reg = <1>;
515			#address-cells = <1>;
516			#size-cells = <0>;
517
518			embedded-controller@58 {
519				compatible = "acer,a500-iconia-ec", "ene,kb930";
520				reg = <0x58>;
521
522				system-power-controller;
523
524				monitored-battery = <&bat1010>;
525				power-supplies = <&mains>;
526			};
527		};
528	};
529
530	pwm: pwm@7000a000 {
531		status = "okay";
532	};
533
534	i2c@7000d000 {
535		clock-frequency = <100000>;
536		status = "okay";
537
538		magnetometer@c {
539			compatible = "ak,ak8975";
540			reg = <0x0c>;
541
542			interrupt-parent = <&gpio>;
543			interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_EDGE_RISING>;
544
545			vdd-supply = <&vdd_3v3_sys>;
546			vid-supply = <&vdd_1v8_sys>;
547
548			mount-matrix =	"1",  "0",  "0",
549					"0", "-1",  "0",
550					"0",  "0", "-1";
551		};
552
553		pmic: pmic@34 {
554			compatible = "ti,tps6586x";
555			reg = <0x34>;
556
557			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
558
559			#gpio-cells = <2>;
560			gpio-controller;
561
562			sys-supply       = <&vdd_5v0_sys>;
563			vin-sm0-supply   = <&sys_reg>;
564			vin-sm1-supply   = <&sys_reg>;
565			vin-sm2-supply   = <&sys_reg>;
566			vinldo01-supply  = <&sm2_reg>;
567			vinldo23-supply  = <&sm2_reg>;
568			vinldo4-supply   = <&sm2_reg>;
569			vinldo678-supply = <&sm2_reg>;
570			vinldo9-supply   = <&sm2_reg>;
571
572			regulators {
573				sys_reg: sys {
574					regulator-name = "vdd_sys";
575					regulator-always-on;
576				};
577
578				vdd_core: sm0 {
579					regulator-name = "vdd_sm0,vdd_core";
580					regulator-min-microvolt = <950000>;
581					regulator-max-microvolt = <1300000>;
582					regulator-coupled-with = <&rtc_vdd &vdd_cpu>;
583					regulator-coupled-max-spread = <170000 550000>;
584					regulator-always-on;
585					regulator-boot-on;
586
587					nvidia,tegra-core-regulator;
588				};
589
590				vdd_cpu: sm1 {
591					regulator-name = "vdd_sm1,vdd_cpu";
592					regulator-min-microvolt = <750000>;
593					regulator-max-microvolt = <1125000>;
594					regulator-coupled-with = <&vdd_core &rtc_vdd>;
595					regulator-coupled-max-spread = <550000 550000>;
596					regulator-always-on;
597					regulator-boot-on;
598
599					nvidia,tegra-cpu-regulator;
600				};
601
602				sm2_reg: sm2 {
603					regulator-name = "vdd_sm2,vin_ldo*";
604					regulator-min-microvolt = <3700000>;
605					regulator-max-microvolt = <3700000>;
606					regulator-always-on;
607				};
608
609				/* LDO0 is not connected to anything */
610
611				ldo1 {
612					regulator-name = "vdd_ldo1,avdd_pll*";
613					regulator-min-microvolt = <1100000>;
614					regulator-max-microvolt = <1100000>;
615					regulator-always-on;
616					regulator-boot-on;
617				};
618
619				rtc_vdd: ldo2 {
620					regulator-name = "vdd_ldo2,vdd_rtc";
621					regulator-min-microvolt = <950000>;
622					regulator-max-microvolt = <1300000>;
623					regulator-coupled-with = <&vdd_core &vdd_cpu>;
624					regulator-coupled-max-spread = <170000 550000>;
625					regulator-always-on;
626					regulator-boot-on;
627
628					nvidia,tegra-rtc-regulator;
629				};
630
631				ldo3 {
632					regulator-name = "vdd_ldo3,avdd_usb*";
633					regulator-min-microvolt = <3300000>;
634					regulator-max-microvolt = <3300000>;
635					regulator-always-on;
636				};
637
638				ldo4 {
639					regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
640					regulator-min-microvolt = <1800000>;
641					regulator-max-microvolt = <1800000>;
642					regulator-always-on;
643					regulator-boot-on;
644				};
645
646				vcore_emmc: ldo5 {
647					regulator-name = "vdd_ldo5,vcore_mmc";
648					regulator-min-microvolt = <2850000>;
649					regulator-max-microvolt = <2850000>;
650					regulator-always-on;
651				};
652
653				avdd_vdac_reg: ldo6 {
654					regulator-name = "vdd_ldo6,avdd_vdac";
655					regulator-min-microvolt = <2850000>;
656					regulator-max-microvolt = <2850000>;
657				};
658
659				hdmi_vdd_reg: ldo7 {
660					regulator-name = "vdd_ldo7,avdd_hdmi";
661					regulator-min-microvolt = <3300000>;
662					regulator-max-microvolt = <3300000>;
663				};
664
665				hdmi_pll_reg: ldo8 {
666					regulator-name = "vdd_ldo8,avdd_hdmi_pll";
667					regulator-min-microvolt = <1800000>;
668					regulator-max-microvolt = <1800000>;
669				};
670
671				ldo9 {
672					regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
673					regulator-min-microvolt = <2850000>;
674					regulator-max-microvolt = <2850000>;
675					regulator-always-on;
676					regulator-boot-on;
677				};
678
679				ldo_rtc {
680					regulator-name = "vdd_rtc_out,vdd_cell";
681					regulator-min-microvolt = <3300000>;
682					regulator-max-microvolt = <3300000>;
683					regulator-always-on;
684					regulator-boot-on;
685				};
686			};
687		};
688
689		nct1008: temperature-sensor@4c {
690			compatible = "onnn,nct1008";
691			reg = <0x4c>;
692			vcc-supply = <&vdd_3v3_sys>;
693			#thermal-sensor-cells = <1>;
694		};
695	};
696
697	pmc@7000e400 {
698		nvidia,invert-interrupt;
699		nvidia,suspend-mode = <1>;
700		nvidia,cpu-pwr-good-time = <2000>;
701		nvidia,cpu-pwr-off-time = <100>;
702		nvidia,core-pwr-good-time = <3845 3845>;
703		nvidia,core-pwr-off-time = <458>;
704		nvidia,sys-clock-req-active-high;
705	};
706
707	usb@c5000000 {
708		compatible = "nvidia,tegra20-udc";
709		status = "okay";
710		dr_mode = "peripheral";
711	};
712
713	usb-phy@c5000000 {
714		status = "okay";
715		dr_mode = "peripheral";
716		nvidia,xcvr-setup-use-fuses;
717		nvidia,xcvr-lsfslew = <2>;
718		nvidia,xcvr-lsrslew = <2>;
719		vbus-supply = <&vdd_vbus1>;
720	};
721
722	usb@c5008000 {
723		status = "okay";
724	};
725
726	usb-phy@c5008000 {
727		status = "okay";
728		nvidia,xcvr-setup-use-fuses;
729		nvidia,xcvr-lsfslew = <2>;
730		nvidia,xcvr-lsrslew = <2>;
731		vbus-supply = <&vdd_vbus3>;
732	};
733
734	brcm_wifi_pwrseq: wifi-pwrseq {
735		compatible = "mmc-pwrseq-simple";
736
737		clocks = <&rtc_32k_wifi>;
738		clock-names = "ext_clock";
739
740		reset-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_LOW>;
741		post-power-on-delay-ms = <300>;
742		power-off-delay-us = <300>;
743	};
744
745	sdmmc1: mmc@c8000000 {
746		status = "okay";
747
748		#address-cells = <1>;
749		#size-cells = <0>;
750
751		assigned-clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
752		assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_C>;
753		assigned-clock-rates = <50000000>;
754
755		max-frequency = <50000000>;
756		keep-power-in-suspend;
757		bus-width = <4>;
758		non-removable;
759
760		mmc-pwrseq = <&brcm_wifi_pwrseq>;
761		vmmc-supply = <&vdd_3v3_sys>;
762		vqmmc-supply = <&vdd_3v3_sys>;
763
764		/* Azurewave AW-NH611 BCM4329 */
765		wifi@1 {
766			reg = <1>;
767			compatible = "brcm,bcm4329-fmac";
768			interrupt-parent = <&gpio>;
769			interrupts = <TEGRA_GPIO(S, 0) IRQ_TYPE_LEVEL_HIGH>;
770			interrupt-names = "host-wake";
771		};
772	};
773
774	sdmmc3: mmc@c8000400 {
775		status = "okay";
776		bus-width = <4>;
777		cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
778		power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
779		vmmc-supply = <&vdd_3v3_sys>;
780		vqmmc-supply = <&vdd_3v3_sys>;
781	};
782
783	sdmmc4: mmc@c8000600 {
784		status = "okay";
785		bus-width = <8>;
786		vmmc-supply = <&vcore_emmc>;
787		vqmmc-supply = <&vdd_3v3_sys>;
788		non-removable;
789	};
790
791	mains: ac-adapter-detect {
792		compatible = "gpio-charger";
793		charger-type = "mains";
794		gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>;
795	};
796
797	backlight: backlight {
798		compatible = "pwm-backlight";
799
800		enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
801		power-supply = <&vdd_3v3_sys>;
802		pwms = <&pwm 2 41667>;
803
804		brightness-levels = <7 255>;
805		num-interpolated-steps = <248>;
806		default-brightness-level = <20>;
807	};
808
809	bat1010: battery-2s1p {
810		compatible = "simple-battery";
811		charge-full-design-microamp-hours = <3260000>;
812		energy-full-design-microwatt-hours = <24000000>;
813		operating-range-celsius = <0 40>;
814	};
815
816	/* PMIC has a built-in 32KHz oscillator which is used by PMC */
817	clk32k_in: clock@0 {
818		compatible = "fixed-clock";
819		#clock-cells = <0>;
820		clock-frequency = <32768>;
821		clock-output-names = "tps658621-out32k";
822	};
823
824	/*
825	 * This standalone onboard fixed-clock always-ON 32KHz
826	 * oscillator is used as a reference clock-source by the
827	 * Azurewave WiFi/BT module.
828	 */
829	rtc_32k_wifi: clock@1 {
830		compatible = "fixed-clock";
831		#clock-cells = <0>;
832		clock-frequency = <32768>;
833		clock-output-names = "kk3270032";
834	};
835
836	cpus {
837		cpu0: cpu@0 {
838			cpu-supply = <&vdd_cpu>;
839			operating-points-v2 = <&cpu0_opp_table>;
840			#cooling-cells = <2>;
841		};
842
843		cpu1: cpu@1 {
844			cpu-supply = <&vdd_cpu>;
845			operating-points-v2 = <&cpu0_opp_table>;
846			#cooling-cells = <2>;
847		};
848	};
849
850	display-panel {
851		compatible = "auo,b101ew05", "panel-lvds";
852
853		ddc-i2c-bus = <&panel_ddc>;
854		power-supply = <&vdd_pnl>;
855		backlight = <&backlight>;
856
857		width-mm = <218>;
858		height-mm = <135>;
859
860		data-mapping = "jeida-18";
861
862		panel-timing {
863			clock-frequency = <71200000>;
864			hactive = <1280>;
865			vactive = <800>;
866			hfront-porch = <8>;
867			hback-porch = <18>;
868			hsync-len = <184>;
869			vsync-len = <3>;
870			vfront-porch = <4>;
871			vback-porch = <8>;
872		};
873
874		port {
875			panel_input: endpoint {
876				remote-endpoint = <&lvds_encoder_output>;
877			};
878		};
879	};
880
881	gpio-keys {
882		compatible = "gpio-keys";
883
884		power {
885			label = "Power";
886			gpios = <&gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH>;
887			linux,code = <KEY_POWER>;
888			debounce-interval = <10>;
889			wakeup-event-action = <EV_ACT_ASSERTED>;
890			wakeup-source;
891		};
892
893		rotation-lock {
894			label = "Rotate-lock";
895			gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_HIGH>;
896			linux,code = <SW_ROTATE_LOCK>;
897			linux,input-type = <EV_SW>;
898			debounce-interval = <10>;
899		};
900
901		volume-up {
902			label = "Volume Up";
903			gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
904			linux,code = <KEY_VOLUMEUP>;
905			debounce-interval = <10>;
906			wakeup-event-action = <EV_ACT_ASSERTED>;
907			wakeup-source;
908		};
909
910		volume-down {
911			label = "Volume Down";
912			gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>;
913			linux,code = <KEY_VOLUMEDOWN>;
914			debounce-interval = <10>;
915			wakeup-event-action = <EV_ACT_ASSERTED>;
916			wakeup-source;
917		};
918	};
919
920	haptic-feedback {
921		compatible = "gpio-vibrator";
922		enable-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>;
923		vcc-supply = <&vdd_3v3_sys>;
924	};
925
926	lvds-encoder {
927		compatible = "ti,sn75lvds83", "lvds-encoder";
928
929		powerdown-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_LOW>;
930		power-supply = <&vdd_3v3_sys>;
931
932		ports {
933			#address-cells = <1>;
934			#size-cells = <0>;
935
936			port@0 {
937				reg = <0>;
938
939				lvds_encoder_input: endpoint {
940					remote-endpoint = <&lcd_output>;
941				};
942			};
943
944			port@1 {
945				reg = <1>;
946
947				lvds_encoder_output: endpoint {
948					remote-endpoint = <&panel_input>;
949				};
950			};
951		};
952	};
953
954	vdd_5v0_sys: regulator@0 {
955		compatible = "regulator-fixed";
956		regulator-name = "vdd_5v0";
957		regulator-min-microvolt = <5000000>;
958		regulator-max-microvolt = <5000000>;
959		regulator-always-on;
960	};
961
962	vdd_3v3_sys: regulator@1 {
963		compatible = "regulator-fixed";
964		regulator-name = "vdd_3v3_vs";
965		regulator-min-microvolt = <3300000>;
966		regulator-max-microvolt = <3300000>;
967		regulator-always-on;
968		vin-supply = <&vdd_5v0_sys>;
969	};
970
971	vdd_1v8_sys: regulator@2 {
972		compatible = "regulator-fixed";
973		regulator-name = "vdd_1v8_vs";
974		regulator-min-microvolt = <1800000>;
975		regulator-max-microvolt = <1800000>;
976		regulator-always-on;
977		vin-supply = <&vdd_5v0_sys>;
978	};
979
980	vdd_pnl: regulator@3 {
981		compatible = "regulator-fixed";
982		regulator-name = "vdd_panel";
983		regulator-min-microvolt = <3300000>;
984		regulator-max-microvolt = <3300000>;
985		regulator-enable-ramp-delay = <300000>;
986		gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
987		enable-active-high;
988		vin-supply = <&vdd_5v0_sys>;
989	};
990
991	vdd_vbus1: regulator@4 {
992		compatible = "regulator-fixed";
993		regulator-name = "vdd_usb1_vbus";
994		regulator-min-microvolt = <5000000>;
995		regulator-max-microvolt = <5000000>;
996		regulator-always-on;
997		gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
998		enable-active-high;
999		vin-supply = <&vdd_5v0_sys>;
1000	};
1001
1002	vdd_vbus3: regulator@5 {
1003		compatible = "regulator-fixed";
1004		regulator-name = "vdd_usb3_vbus";
1005		regulator-min-microvolt = <5000000>;
1006		regulator-max-microvolt = <5000000>;
1007		regulator-always-on;
1008		gpio = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_HIGH>;
1009		enable-active-high;
1010		vin-supply = <&vdd_5v0_sys>;
1011	};
1012
1013	sound {
1014		compatible = "nvidia,tegra-audio-wm8903-picasso",
1015			     "nvidia,tegra-audio-wm8903";
1016		nvidia,model = "Acer Iconia Tab A500 WM8903";
1017
1018		nvidia,audio-routing =
1019			"Headphone Jack", "HPOUTR",
1020			"Headphone Jack", "HPOUTL",
1021			"Int Spk", "LINEOUTL",
1022			"Int Spk", "LINEOUTR",
1023			"Mic Jack", "MICBIAS",
1024			"IN2L", "Mic Jack",
1025			"IN2R", "Mic Jack",
1026			"IN1L", "Int Mic",
1027			"IN1R", "Int Mic";
1028
1029		nvidia,i2s-controller = <&tegra_i2s1>;
1030		nvidia,audio-codec = <&wm8903>;
1031
1032		nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
1033		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
1034		nvidia,int-mic-en-gpios = <&wm8903 1 GPIO_ACTIVE_HIGH>;
1035		nvidia,headset;
1036
1037		clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
1038			 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
1039			 <&tegra_car TEGRA20_CLK_CDEV1>;
1040		clock-names = "pll_a", "pll_a_out0", "mclk";
1041	};
1042
1043	thermal-zones {
1044		skin-thermal {
1045			polling-delay-passive = <1000>; /* milliseconds */
1046			polling-delay = <0>; /* milliseconds */
1047
1048			thermal-sensors = <&nct1008 0>;
1049		};
1050
1051		cpu-thermal {
1052			polling-delay-passive = <1000>; /* milliseconds */
1053			polling-delay = <5000>; /* milliseconds */
1054
1055			thermal-sensors = <&nct1008 1>;
1056
1057			trips {
1058				trip0: cpu-alert0 {
1059					/* start throttling at 50C */
1060					temperature = <50000>;
1061					hysteresis = <200>;
1062					type = "passive";
1063				};
1064
1065				trip1: cpu-crit {
1066					/* shut down at 60C */
1067					temperature = <60000>;
1068					hysteresis = <2000>;
1069					type = "critical";
1070				};
1071			};
1072
1073			cooling-maps {
1074				map0 {
1075					trip = <&trip0>;
1076					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1077							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1078				};
1079			};
1080		};
1081	};
1082
1083	memory-controller@7000f400 {
1084		nvidia,use-ram-code;
1085
1086		emc-tables@0 {
1087			nvidia,ram-code = <0>; /* elpida-8gb */
1088
1089			#address-cells = <1>;
1090			#size-cells = <0>;
1091
1092			emc-table@25000 {
1093				reg = <25000>;
1094				compatible = "nvidia,tegra20-emc-table";
1095				clock-frequency = <25000>;
1096				nvidia,emc-registers = <0x00000002 0x00000006
1097					0x00000003 0x00000003 0x00000006 0x00000004
1098					0x00000002 0x00000009 0x00000003 0x00000003
1099					0x00000002 0x00000002 0x00000002 0x00000004
1100					0x00000003 0x00000008 0x0000000b 0x0000004d
1101					0x00000000 0x00000003 0x00000003 0x00000003
1102					0x00000008 0x00000001 0x0000000a 0x00000004
1103					0x00000003 0x00000008 0x00000004 0x00000006
1104					0x00000002 0x00000068 0x00000000 0x00000003
1105					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1106					0x00070000 0x00000000 0x00000000 0x00000003
1107					0x00000000 0x00000000 0x00000000 0x00000000>;
1108			};
1109
1110			emc-table@50000 {
1111				reg = <50000>;
1112				compatible = "nvidia,tegra20-emc-table";
1113				clock-frequency = <50000>;
1114				nvidia,emc-registers = <0x00000003 0x00000007
1115					0x00000003 0x00000003 0x00000006 0x00000004
1116					0x00000002 0x00000009 0x00000003 0x00000003
1117					0x00000002 0x00000002 0x00000002 0x00000005
1118					0x00000003 0x00000008 0x0000000b 0x0000009f
1119					0x00000000 0x00000003 0x00000003 0x00000003
1120					0x00000008 0x00000001 0x0000000a 0x00000007
1121					0x00000003 0x00000008 0x00000004 0x00000006
1122					0x00000002 0x000000d0 0x00000000 0x00000000
1123					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1124					0x00070000 0x00000000 0x00000000 0x00000005
1125					0x00000000 0x00000000 0x00000000 0x00000000>;
1126			};
1127
1128			emc-table@75000 {
1129				reg = <75000>;
1130				compatible = "nvidia,tegra20-emc-table";
1131				clock-frequency = <75000>;
1132				nvidia,emc-registers = <0x00000005 0x0000000a
1133					0x00000004 0x00000003 0x00000006 0x00000004
1134					0x00000002 0x00000009 0x00000003 0x00000003
1135					0x00000002 0x00000002 0x00000002 0x00000005
1136					0x00000003 0x00000008 0x0000000b 0x000000ff
1137					0x00000000 0x00000003 0x00000003 0x00000003
1138					0x00000008 0x00000001 0x0000000a 0x0000000b
1139					0x00000003 0x00000008 0x00000004 0x00000006
1140					0x00000002 0x00000138 0x00000000 0x00000000
1141					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1142					0x00070000 0x00000000 0x00000000 0x00000007
1143					0x00000000 0x00000000 0x00000000 0x00000000>;
1144			};
1145
1146			emc-table@150000 {
1147				reg = <150000>;
1148				compatible = "nvidia,tegra20-emc-table";
1149				clock-frequency = <150000>;
1150				nvidia,emc-registers = <0x00000009 0x00000014
1151					0x00000007 0x00000003 0x00000006 0x00000004
1152					0x00000002 0x00000009 0x00000003 0x00000003
1153					0x00000002 0x00000002 0x00000002 0x00000005
1154					0x00000003 0x00000008 0x0000000b 0x0000021f
1155					0x00000000 0x00000003 0x00000003 0x00000003
1156					0x00000008 0x00000001 0x0000000a 0x00000015
1157					0x00000003 0x00000008 0x00000004 0x00000006
1158					0x00000002 0x00000270 0x00000000 0x00000001
1159					0x00000000 0x00000000 0x00000282 0xa07c04ae
1160					0x007dd510 0x00000000 0x00000000 0x0000000e
1161					0x00000000 0x00000000 0x00000000 0x00000000>;
1162			};
1163
1164			emc-table@300000 {
1165				reg = <300000>;
1166				compatible = "nvidia,tegra20-emc-table";
1167				clock-frequency = <300000>;
1168				nvidia,emc-registers = <0x00000012 0x00000027
1169					0x0000000d 0x00000006 0x00000007 0x00000005
1170					0x00000003 0x00000009 0x00000006 0x00000006
1171					0x00000003 0x00000003 0x00000002 0x00000006
1172					0x00000003 0x00000009 0x0000000c 0x0000045f
1173					0x00000000 0x00000004 0x00000004 0x00000006
1174					0x00000008 0x00000001 0x0000000e 0x0000002a
1175					0x00000003 0x0000000f 0x00000007 0x00000005
1176					0x00000002 0x000004e1 0x00000005 0x00000002
1177					0x00000000 0x00000000 0x00000282 0xe059048b
1178					0x007e1510 0x00000000 0x00000000 0x0000001b
1179					0x00000000 0x00000000 0x00000000 0x00000000>;
1180			};
1181		};
1182
1183		emc-tables@1 {
1184			nvidia,ram-code = <1>; /* elpida-4gb */
1185
1186			#address-cells = <1>;
1187			#size-cells = <0>;
1188
1189			emc-table@25000 {
1190				reg = <25000>;
1191				compatible = "nvidia,tegra20-emc-table";
1192				clock-frequency = <25000>;
1193				nvidia,emc-registers = <0x00000002 0x00000006
1194					0x00000003 0x00000003 0x00000006 0x00000004
1195					0x00000002 0x00000009 0x00000003 0x00000003
1196					0x00000002 0x00000002 0x00000002 0x00000004
1197					0x00000003 0x00000008 0x0000000b 0x0000004d
1198					0x00000000 0x00000003 0x00000003 0x00000003
1199					0x00000008 0x00000001 0x0000000a 0x00000004
1200					0x00000003 0x00000008 0x00000004 0x00000006
1201					0x00000002 0x00000068 0x00000000 0x00000003
1202					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1203					0x0007c000 0x00000000 0x00000000 0x00000003
1204					0x00000000 0x00000000 0x00000000 0x00000000>;
1205			};
1206
1207			emc-table@50000 {
1208				reg = <50000>;
1209				compatible = "nvidia,tegra20-emc-table";
1210				clock-frequency = <50000>;
1211				nvidia,emc-registers = <0x00000003 0x00000007
1212					0x00000003 0x00000003 0x00000006 0x00000004
1213					0x00000002 0x00000009 0x00000003 0x00000003
1214					0x00000002 0x00000002 0x00000002 0x00000005
1215					0x00000003 0x00000008 0x0000000b 0x0000009f
1216					0x00000000 0x00000003 0x00000003 0x00000003
1217					0x00000008 0x00000001 0x0000000a 0x00000007
1218					0x00000003 0x00000008 0x00000004 0x00000006
1219					0x00000002 0x000000d0 0x00000000 0x00000000
1220					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1221					0x0007c000 0x00000000 0x00000000 0x00000005
1222					0x00000000 0x00000000 0x00000000 0x00000000>;
1223			};
1224
1225			emc-table@75000 {
1226				reg = <75000>;
1227				compatible = "nvidia,tegra20-emc-table";
1228				clock-frequency = <75000>;
1229				nvidia,emc-registers = <0x00000005 0x0000000a
1230					0x00000004 0x00000003 0x00000006 0x00000004
1231					0x00000002 0x00000009 0x00000003 0x00000003
1232					0x00000002 0x00000002 0x00000002 0x00000005
1233					0x00000003 0x00000008 0x0000000b 0x000000ff
1234					0x00000000 0x00000003 0x00000003 0x00000003
1235					0x00000008 0x00000001 0x0000000a 0x0000000b
1236					0x00000003 0x00000008 0x00000004 0x00000006
1237					0x00000002 0x00000138 0x00000000 0x00000000
1238					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1239					0x0007c000 0x00000000 0x00000000 0x00000007
1240					0x00000000 0x00000000 0x00000000 0x00000000>;
1241			};
1242
1243			emc-table@150000 {
1244				reg = <150000>;
1245				compatible = "nvidia,tegra20-emc-table";
1246				clock-frequency = <150000>;
1247				nvidia,emc-registers = <0x00000009 0x00000014
1248					0x00000007 0x00000003 0x00000006 0x00000004
1249					0x00000002 0x00000009 0x00000003 0x00000003
1250					0x00000002 0x00000002 0x00000002 0x00000005
1251					0x00000003 0x00000008 0x0000000b 0x0000021f
1252					0x00000000 0x00000003 0x00000003 0x00000003
1253					0x00000008 0x00000001 0x0000000a 0x00000015
1254					0x00000003 0x00000008 0x00000004 0x00000006
1255					0x00000002 0x00000270 0x00000000 0x00000001
1256					0x00000000 0x00000000 0x00000282 0xa07c04ae
1257					0x007e4010 0x00000000 0x00000000 0x0000000e
1258					0x00000000 0x00000000 0x00000000 0x00000000>;
1259			};
1260
1261			emc-table@300000 {
1262				reg = <300000>;
1263				compatible = "nvidia,tegra20-emc-table";
1264				clock-frequency = <300000>;
1265				nvidia,emc-registers = <0x00000012 0x00000027
1266					0x0000000d 0x00000006 0x00000007 0x00000005
1267					0x00000003 0x00000009 0x00000006 0x00000006
1268					0x00000003 0x00000003 0x00000002 0x00000006
1269					0x00000003 0x00000009 0x0000000c 0x0000045f
1270					0x00000000 0x00000004 0x00000004 0x00000006
1271					0x00000008 0x00000001 0x0000000e 0x0000002a
1272					0x00000003 0x0000000f 0x00000007 0x00000005
1273					0x00000002 0x000004e1 0x00000005 0x00000002
1274					0x00000000 0x00000000 0x00000282 0xe059048b
1275					0x007e0010 0x00000000 0x00000000 0x0000001b
1276					0x00000000 0x00000000 0x00000000 0x00000000>;
1277			};
1278		};
1279
1280		emc-tables@2 {
1281			nvidia,ram-code = <2>; /* hynix-8gb */
1282
1283			#address-cells = <1>;
1284			#size-cells = <0>;
1285
1286			emc-table@25000 {
1287				reg = <25000>;
1288				compatible = "nvidia,tegra20-emc-table";
1289				clock-frequency = <25000>;
1290				nvidia,emc-registers = <0x00000002 0x00000006
1291					0x00000003 0x00000003 0x00000006 0x00000004
1292					0x00000002 0x00000009 0x00000003 0x00000003
1293					0x00000002 0x00000002 0x00000002 0x00000004
1294					0x00000003 0x00000008 0x0000000b 0x0000004d
1295					0x00000000 0x00000003 0x00000003 0x00000003
1296					0x00000008 0x00000001 0x0000000a 0x00000004
1297					0x00000003 0x00000008 0x00000004 0x00000006
1298					0x00000002 0x00000068 0x00000000 0x00000003
1299					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1300					0x00070000 0x00000000 0x00000000 0x00000003
1301					0x00000000 0x00000000 0x00000000 0x00000000>;
1302			};
1303
1304			emc-table@50000 {
1305				reg = <50000>;
1306				compatible = "nvidia,tegra20-emc-table";
1307				clock-frequency = <50000>;
1308				nvidia,emc-registers = <0x00000003 0x00000007
1309					0x00000003 0x00000003 0x00000006 0x00000004
1310					0x00000002 0x00000009 0x00000003 0x00000003
1311					0x00000002 0x00000002 0x00000002 0x00000005
1312					0x00000003 0x00000008 0x0000000b 0x0000009f
1313					0x00000000 0x00000003 0x00000003 0x00000003
1314					0x00000008 0x00000001 0x0000000a 0x00000007
1315					0x00000003 0x00000008 0x00000004 0x00000006
1316					0x00000002 0x000000d0 0x00000000 0x00000000
1317					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1318					0x00070000 0x00000000 0x00000000 0x00000005
1319					0x00000000 0x00000000 0x00000000 0x00000000>;
1320			};
1321
1322			emc-table@75000 {
1323				reg = <75000>;
1324				compatible = "nvidia,tegra20-emc-table";
1325				clock-frequency = <75000>;
1326				nvidia,emc-registers = <0x00000005 0x0000000a
1327					0x00000004 0x00000003 0x00000006 0x00000004
1328					0x00000002 0x00000009 0x00000003 0x00000003
1329					0x00000002 0x00000002 0x00000002 0x00000005
1330					0x00000003 0x00000008 0x0000000b 0x000000ff
1331					0x00000000 0x00000003 0x00000003 0x00000003
1332					0x00000008 0x00000001 0x0000000a 0x0000000b
1333					0x00000003 0x00000008 0x00000004 0x00000006
1334					0x00000002 0x00000138 0x00000000 0x00000000
1335					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1336					0x00070000 0x00000000 0x00000000 0x00000007
1337					0x00000000 0x00000000 0x00000000 0x00000000>;
1338			};
1339
1340			emc-table@150000 {
1341				reg = <150000>;
1342				compatible = "nvidia,tegra20-emc-table";
1343				clock-frequency = <150000>;
1344				nvidia,emc-registers = <0x00000009 0x00000014
1345					0x00000007 0x00000003 0x00000006 0x00000004
1346					0x00000002 0x00000009 0x00000003 0x00000003
1347					0x00000002 0x00000002 0x00000002 0x00000005
1348					0x00000003 0x00000008 0x0000000b 0x0000021f
1349					0x00000000 0x00000003 0x00000003 0x00000003
1350					0x00000008 0x00000001 0x0000000a 0x00000015
1351					0x00000003 0x00000008 0x00000004 0x00000006
1352					0x00000002 0x00000270 0x00000000 0x00000001
1353					0x00000000 0x00000000 0x00000282 0xa07c04ae
1354					0x007dd010 0x00000000 0x00000000 0x0000000e
1355					0x00000000 0x00000000 0x00000000 0x00000000>;
1356			};
1357
1358			emc-table@300000 {
1359				reg = <300000>;
1360				compatible = "nvidia,tegra20-emc-table";
1361				clock-frequency = <300000>;
1362				nvidia,emc-registers = <0x00000012 0x00000027
1363					0x0000000d 0x00000006 0x00000007 0x00000005
1364					0x00000003 0x00000009 0x00000006 0x00000006
1365					0x00000003 0x00000003 0x00000002 0x00000006
1366					0x00000003 0x00000009 0x0000000c 0x0000045f
1367					0x00000000 0x00000004 0x00000004 0x00000006
1368					0x00000008 0x00000001 0x0000000e 0x0000002a
1369					0x00000003 0x0000000f 0x00000007 0x00000005
1370					0x00000002 0x000004e1 0x00000005 0x00000002
1371					0x00000000 0x00000000 0x00000282 0xe059048b
1372					0x007e2010 0x00000000 0x00000000 0x0000001b
1373					0x00000000 0x00000000 0x00000000 0x00000000>;
1374			};
1375		};
1376
1377		emc-tables@3 {
1378			nvidia,ram-code = <3>; /* hynix-4gb */
1379
1380			#address-cells = <1>;
1381			#size-cells = <0>;
1382
1383			emc-table@25000 {
1384				reg = <25000>;
1385				compatible = "nvidia,tegra20-emc-table";
1386				clock-frequency = <25000>;
1387				nvidia,emc-registers = <0x00000002 0x00000006
1388					0x00000003 0x00000003 0x00000006 0x00000004
1389					0x00000002 0x00000009 0x00000003 0x00000003
1390					0x00000002 0x00000002 0x00000002 0x00000004
1391					0x00000003 0x00000008 0x0000000b 0x0000004d
1392					0x00000000 0x00000003 0x00000003 0x00000003
1393					0x00000008 0x00000001 0x0000000a 0x00000004
1394					0x00000003 0x00000008 0x00000004 0x00000006
1395					0x00000002 0x00000068 0x00000000 0x00000003
1396					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1397					0x0007c000 0x00000000 0x00000000 0x00000003
1398					0x00000000 0x00000000 0x00000000 0x00000000>;
1399			};
1400
1401			emc-table@50000 {
1402				reg = <50000>;
1403				compatible = "nvidia,tegra20-emc-table";
1404				clock-frequency = <50000>;
1405				nvidia,emc-registers = <0x00000003 0x00000007
1406					0x00000003 0x00000003 0x00000006 0x00000004
1407					0x00000002 0x00000009 0x00000003 0x00000003
1408					0x00000002 0x00000002 0x00000002 0x00000005
1409					0x00000003 0x00000008 0x0000000b 0x0000009f
1410					0x00000000 0x00000003 0x00000003 0x00000003
1411					0x00000008 0x00000001 0x0000000a 0x00000007
1412					0x00000003 0x00000008 0x00000004 0x00000006
1413					0x00000002 0x000000d0 0x00000000 0x00000000
1414					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1415					0x0007c000 0x00078000 0x00000000 0x00000005
1416					0x00000000 0x00000000 0x00000000 0x00000000>;
1417			};
1418
1419			emc-table@75000 {
1420				reg = <75000>;
1421				compatible = "nvidia,tegra20-emc-table";
1422				clock-frequency = <75000>;
1423				nvidia,emc-registers = <0x00000005 0x0000000a
1424					0x00000004 0x00000003 0x00000006 0x00000004
1425					0x00000002 0x00000009 0x00000003 0x00000003
1426					0x00000002 0x00000002 0x00000002 0x00000005
1427					0x00000003 0x00000008 0x0000000b 0x000000ff
1428					0x00000000 0x00000003 0x00000003 0x00000003
1429					0x00000008 0x00000001 0x0000000a 0x0000000b
1430					0x00000003 0x00000008 0x00000004 0x00000006
1431					0x00000002 0x00000138 0x00000000 0x00000000
1432					0x00000000 0x00000000 0x00000282 0xa0ae04ae
1433					0x0007c000 0x00000000 0x00000000 0x00000007
1434					0x00000000 0x00000000 0x00000000 0x00000000>;
1435			};
1436
1437			emc-table@150000 {
1438				reg = <150000>;
1439				compatible = "nvidia,tegra20-emc-table";
1440				clock-frequency = <150000>;
1441				nvidia,emc-registers = <0x00000009 0x00000014
1442					0x00000007 0x00000003 0x00000006 0x00000004
1443					0x00000002 0x00000009 0x00000003 0x00000003
1444					0x00000002 0x00000002 0x00000002 0x00000005
1445					0x00000003 0x00000008 0x0000000b 0x0000021f
1446					0x00000000 0x00000003 0x00000003 0x00000003
1447					0x00000008 0x00000001 0x0000000a 0x00000015
1448					0x00000003 0x00000008 0x00000004 0x00000006
1449					0x00000002 0x00000270 0x00000000 0x00000001
1450					0x00000000 0x00000000 0x00000282 0xa07c04ae
1451					0x007e4010 0x00000000 0x00000000 0x0000000e
1452					0x00000000 0x00000000 0x00000000 0x00000000>;
1453			};
1454
1455			emc-table@300000 {
1456				reg = <300000>;
1457				compatible = "nvidia,tegra20-emc-table";
1458				clock-frequency = <300000>;
1459				nvidia,emc-registers = <0x00000012 0x00000027
1460					0x0000000d 0x00000006 0x00000007 0x00000005
1461					0x00000003 0x00000009 0x00000006 0x00000006
1462					0x00000003 0x00000003 0x00000002 0x00000006
1463					0x00000003 0x00000009 0x0000000c 0x0000045f
1464					0x00000000 0x00000004 0x00000004 0x00000006
1465					0x00000008 0x00000001 0x0000000e 0x0000002a
1466					0x00000003 0x0000000f 0x00000007 0x00000005
1467					0x00000002 0x000004e1 0x00000005 0x00000002
1468					0x00000000 0x00000000 0x00000282 0xe059048b
1469					0x007e0010 0x00000000 0x00000000 0x0000001b
1470					0x00000000 0x00000000 0x00000000 0x00000000>;
1471			};
1472		};
1473	};
1474};
1475
1476&emc_icc_dvfs_opp_table {
1477	/delete-node/ opp@666000000;
1478	/delete-node/ opp@760000000;
1479};
1480