1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <linux/firmware.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27
28 #include <drm/amdgpu_drm.h>
29
30 #include "amdgpu.h"
31 #include "amdgpu_atombios.h"
32 #include "amdgpu_ih.h"
33 #include "amdgpu_uvd.h"
34 #include "amdgpu_vce.h"
35 #include "amdgpu_ucode.h"
36 #include "amdgpu_psp.h"
37 #include "atom.h"
38 #include "amd_pcie.h"
39
40 #include "uvd/uvd_7_0_offset.h"
41 #include "gc/gc_9_0_offset.h"
42 #include "gc/gc_9_0_sh_mask.h"
43 #include "sdma0/sdma0_4_0_offset.h"
44 #include "sdma1/sdma1_4_0_offset.h"
45 #include "nbio/nbio_7_0_default.h"
46 #include "nbio/nbio_7_0_offset.h"
47 #include "nbio/nbio_7_0_sh_mask.h"
48 #include "nbio/nbio_7_0_smn.h"
49 #include "mp/mp_9_0_offset.h"
50
51 #include "soc15.h"
52 #include "soc15_common.h"
53 #include "gfx_v9_0.h"
54 #include "gmc_v9_0.h"
55 #include "gfxhub_v1_0.h"
56 #include "mmhub_v1_0.h"
57 #include "df_v1_7.h"
58 #include "df_v3_6.h"
59 #include "nbio_v6_1.h"
60 #include "nbio_v7_0.h"
61 #include "nbio_v7_4.h"
62 #include "hdp_v4_0.h"
63 #include "vega10_ih.h"
64 #include "vega20_ih.h"
65 #include "navi10_ih.h"
66 #include "sdma_v4_0.h"
67 #include "uvd_v7_0.h"
68 #include "vce_v4_0.h"
69 #include "vcn_v1_0.h"
70 #include "vcn_v2_0.h"
71 #include "jpeg_v2_0.h"
72 #include "vcn_v2_5.h"
73 #include "jpeg_v2_5.h"
74 #include "smuio_v9_0.h"
75 #include "smuio_v11_0.h"
76 #include "smuio_v13_0.h"
77 #include "dce_virtual.h"
78 #include "mxgpu_ai.h"
79 #include "amdgpu_ras.h"
80 #include "amdgpu_xgmi.h"
81 #include <uapi/linux/kfd_ioctl.h>
82
83 #define mmMP0_MISC_CGTT_CTRL0 0x01b9
84 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0
85 #define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba
86 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0
87
88 /* Vega, Raven, Arcturus */
89 static const struct amdgpu_video_codec_info vega_video_codecs_encode_array[] =
90 {
91 {
92 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
93 .max_width = 4096,
94 .max_height = 2304,
95 .max_pixels_per_frame = 4096 * 2304,
96 .max_level = 0,
97 },
98 {
99 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
100 .max_width = 4096,
101 .max_height = 2304,
102 .max_pixels_per_frame = 4096 * 2304,
103 .max_level = 0,
104 },
105 };
106
107 static const struct amdgpu_video_codecs vega_video_codecs_encode =
108 {
109 .codec_count = ARRAY_SIZE(vega_video_codecs_encode_array),
110 .codec_array = vega_video_codecs_encode_array,
111 };
112
113 /* Vega */
114 static const struct amdgpu_video_codec_info vega_video_codecs_decode_array[] =
115 {
116 {
117 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,
118 .max_width = 4096,
119 .max_height = 4096,
120 .max_pixels_per_frame = 4096 * 4096,
121 .max_level = 3,
122 },
123 {
124 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
125 .max_width = 4096,
126 .max_height = 4096,
127 .max_pixels_per_frame = 4096 * 4096,
128 .max_level = 5,
129 },
130 {
131 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
132 .max_width = 4096,
133 .max_height = 4096,
134 .max_pixels_per_frame = 4096 * 4096,
135 .max_level = 52,
136 },
137 {
138 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,
139 .max_width = 4096,
140 .max_height = 4096,
141 .max_pixels_per_frame = 4096 * 4096,
142 .max_level = 4,
143 },
144 {
145 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
146 .max_width = 4096,
147 .max_height = 4096,
148 .max_pixels_per_frame = 4096 * 4096,
149 .max_level = 186,
150 },
151 {
152 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG,
153 .max_width = 4096,
154 .max_height = 4096,
155 .max_pixels_per_frame = 4096 * 4096,
156 .max_level = 0,
157 },
158 };
159
160 static const struct amdgpu_video_codecs vega_video_codecs_decode =
161 {
162 .codec_count = ARRAY_SIZE(vega_video_codecs_decode_array),
163 .codec_array = vega_video_codecs_decode_array,
164 };
165
166 /* Raven */
167 static const struct amdgpu_video_codec_info rv_video_codecs_decode_array[] =
168 {
169 {
170 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,
171 .max_width = 4096,
172 .max_height = 4096,
173 .max_pixels_per_frame = 4096 * 4096,
174 .max_level = 3,
175 },
176 {
177 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
178 .max_width = 4096,
179 .max_height = 4096,
180 .max_pixels_per_frame = 4096 * 4096,
181 .max_level = 5,
182 },
183 {
184 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
185 .max_width = 4096,
186 .max_height = 4096,
187 .max_pixels_per_frame = 4096 * 4096,
188 .max_level = 52,
189 },
190 {
191 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,
192 .max_width = 4096,
193 .max_height = 4096,
194 .max_pixels_per_frame = 4096 * 4096,
195 .max_level = 4,
196 },
197 {
198 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
199 .max_width = 4096,
200 .max_height = 4096,
201 .max_pixels_per_frame = 4096 * 4096,
202 .max_level = 186,
203 },
204 {
205 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG,
206 .max_width = 4096,
207 .max_height = 4096,
208 .max_pixels_per_frame = 4096 * 4096,
209 .max_level = 0,
210 },
211 {
212 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9,
213 .max_width = 4096,
214 .max_height = 4096,
215 .max_pixels_per_frame = 4096 * 4096,
216 .max_level = 0,
217 },
218 };
219
220 static const struct amdgpu_video_codecs rv_video_codecs_decode =
221 {
222 .codec_count = ARRAY_SIZE(rv_video_codecs_decode_array),
223 .codec_array = rv_video_codecs_decode_array,
224 };
225
226 /* Renoir, Arcturus */
227 static const struct amdgpu_video_codec_info rn_video_codecs_decode_array[] =
228 {
229 {
230 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,
231 .max_width = 4096,
232 .max_height = 4096,
233 .max_pixels_per_frame = 4096 * 4096,
234 .max_level = 3,
235 },
236 {
237 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
238 .max_width = 4096,
239 .max_height = 4096,
240 .max_pixels_per_frame = 4096 * 4096,
241 .max_level = 5,
242 },
243 {
244 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
245 .max_width = 4096,
246 .max_height = 4096,
247 .max_pixels_per_frame = 4096 * 4096,
248 .max_level = 52,
249 },
250 {
251 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,
252 .max_width = 4096,
253 .max_height = 4096,
254 .max_pixels_per_frame = 4096 * 4096,
255 .max_level = 4,
256 },
257 {
258 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
259 .max_width = 8192,
260 .max_height = 4352,
261 .max_pixels_per_frame = 4096 * 4096,
262 .max_level = 186,
263 },
264 {
265 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG,
266 .max_width = 4096,
267 .max_height = 4096,
268 .max_pixels_per_frame = 4096 * 4096,
269 .max_level = 0,
270 },
271 {
272 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9,
273 .max_width = 8192,
274 .max_height = 4352,
275 .max_pixels_per_frame = 4096 * 4096,
276 .max_level = 0,
277 },
278 };
279
280 static const struct amdgpu_video_codecs rn_video_codecs_decode =
281 {
282 .codec_count = ARRAY_SIZE(rn_video_codecs_decode_array),
283 .codec_array = rn_video_codecs_decode_array,
284 };
285
soc15_query_video_codecs(struct amdgpu_device * adev,bool encode,const struct amdgpu_video_codecs ** codecs)286 static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode,
287 const struct amdgpu_video_codecs **codecs)
288 {
289 switch (adev->asic_type) {
290 case CHIP_VEGA20:
291 case CHIP_VEGA10:
292 case CHIP_VEGA12:
293 if (encode)
294 *codecs = &vega_video_codecs_encode;
295 else
296 *codecs = &vega_video_codecs_decode;
297 return 0;
298 case CHIP_RAVEN:
299 if (encode)
300 *codecs = &vega_video_codecs_encode;
301 else
302 *codecs = &rv_video_codecs_decode;
303 return 0;
304 case CHIP_ARCTURUS:
305 case CHIP_RENOIR:
306 if (encode)
307 *codecs = &vega_video_codecs_encode;
308 else
309 *codecs = &rn_video_codecs_decode;
310 return 0;
311 default:
312 return -EINVAL;
313 }
314 }
315
316 /*
317 * Indirect registers accessor
318 */
soc15_pcie_rreg(struct amdgpu_device * adev,u32 reg)319 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
320 {
321 unsigned long address, data;
322 address = adev->nbio.funcs->get_pcie_index_offset(adev);
323 data = adev->nbio.funcs->get_pcie_data_offset(adev);
324
325 return amdgpu_device_indirect_rreg(adev, address, data, reg);
326 }
327
soc15_pcie_wreg(struct amdgpu_device * adev,u32 reg,u32 v)328 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
329 {
330 unsigned long address, data;
331
332 address = adev->nbio.funcs->get_pcie_index_offset(adev);
333 data = adev->nbio.funcs->get_pcie_data_offset(adev);
334
335 amdgpu_device_indirect_wreg(adev, address, data, reg, v);
336 }
337
soc15_pcie_rreg64(struct amdgpu_device * adev,u32 reg)338 static u64 soc15_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
339 {
340 unsigned long address, data;
341 address = adev->nbio.funcs->get_pcie_index_offset(adev);
342 data = adev->nbio.funcs->get_pcie_data_offset(adev);
343
344 return amdgpu_device_indirect_rreg64(adev, address, data, reg);
345 }
346
soc15_pcie_wreg64(struct amdgpu_device * adev,u32 reg,u64 v)347 static void soc15_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
348 {
349 unsigned long address, data;
350
351 address = adev->nbio.funcs->get_pcie_index_offset(adev);
352 data = adev->nbio.funcs->get_pcie_data_offset(adev);
353
354 amdgpu_device_indirect_wreg64(adev, address, data, reg, v);
355 }
356
soc15_uvd_ctx_rreg(struct amdgpu_device * adev,u32 reg)357 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
358 {
359 unsigned long flags, address, data;
360 u32 r;
361
362 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
363 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
364
365 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
366 WREG32(address, ((reg) & 0x1ff));
367 r = RREG32(data);
368 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
369 return r;
370 }
371
soc15_uvd_ctx_wreg(struct amdgpu_device * adev,u32 reg,u32 v)372 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
373 {
374 unsigned long flags, address, data;
375
376 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
377 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
378
379 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
380 WREG32(address, ((reg) & 0x1ff));
381 WREG32(data, (v));
382 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
383 }
384
soc15_didt_rreg(struct amdgpu_device * adev,u32 reg)385 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
386 {
387 unsigned long flags, address, data;
388 u32 r;
389
390 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
391 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
392
393 spin_lock_irqsave(&adev->didt_idx_lock, flags);
394 WREG32(address, (reg));
395 r = RREG32(data);
396 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
397 return r;
398 }
399
soc15_didt_wreg(struct amdgpu_device * adev,u32 reg,u32 v)400 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
401 {
402 unsigned long flags, address, data;
403
404 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
405 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
406
407 spin_lock_irqsave(&adev->didt_idx_lock, flags);
408 WREG32(address, (reg));
409 WREG32(data, (v));
410 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
411 }
412
soc15_gc_cac_rreg(struct amdgpu_device * adev,u32 reg)413 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
414 {
415 unsigned long flags;
416 u32 r;
417
418 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
419 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
420 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
421 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
422 return r;
423 }
424
soc15_gc_cac_wreg(struct amdgpu_device * adev,u32 reg,u32 v)425 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
426 {
427 unsigned long flags;
428
429 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
430 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
431 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
432 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
433 }
434
soc15_se_cac_rreg(struct amdgpu_device * adev,u32 reg)435 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
436 {
437 unsigned long flags;
438 u32 r;
439
440 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
441 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
442 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
443 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
444 return r;
445 }
446
soc15_se_cac_wreg(struct amdgpu_device * adev,u32 reg,u32 v)447 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
448 {
449 unsigned long flags;
450
451 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
452 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
453 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
454 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
455 }
456
soc15_get_config_memsize(struct amdgpu_device * adev)457 static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
458 {
459 return adev->nbio.funcs->get_memsize(adev);
460 }
461
soc15_get_xclk(struct amdgpu_device * adev)462 static u32 soc15_get_xclk(struct amdgpu_device *adev)
463 {
464 u32 reference_clock = adev->clock.spll.reference_freq;
465
466 if (adev->asic_type == CHIP_RENOIR)
467 return 10000;
468 if (adev->asic_type == CHIP_RAVEN)
469 return reference_clock / 4;
470
471 return reference_clock;
472 }
473
474
soc15_grbm_select(struct amdgpu_device * adev,u32 me,u32 pipe,u32 queue,u32 vmid)475 void soc15_grbm_select(struct amdgpu_device *adev,
476 u32 me, u32 pipe, u32 queue, u32 vmid)
477 {
478 u32 grbm_gfx_cntl = 0;
479 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
480 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
481 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
482 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
483
484 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
485 }
486
soc15_vga_set_state(struct amdgpu_device * adev,bool state)487 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
488 {
489 /* todo */
490 }
491
soc15_read_disabled_bios(struct amdgpu_device * adev)492 static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
493 {
494 /* todo */
495 return false;
496 }
497
soc15_read_bios_from_rom(struct amdgpu_device * adev,u8 * bios,u32 length_bytes)498 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
499 u8 *bios, u32 length_bytes)
500 {
501 u32 *dw_ptr;
502 u32 i, length_dw;
503 uint32_t rom_index_offset;
504 uint32_t rom_data_offset;
505
506 if (bios == NULL)
507 return false;
508 if (length_bytes == 0)
509 return false;
510 /* APU vbios image is part of sbios image */
511 if (adev->flags & AMD_IS_APU)
512 return false;
513
514 dw_ptr = (u32 *)bios;
515 length_dw = ALIGN(length_bytes, 4) / 4;
516
517 rom_index_offset =
518 adev->smuio.funcs->get_rom_index_offset(adev);
519 rom_data_offset =
520 adev->smuio.funcs->get_rom_data_offset(adev);
521
522 /* set rom index to 0 */
523 WREG32(rom_index_offset, 0);
524 /* read out the rom data */
525 for (i = 0; i < length_dw; i++)
526 dw_ptr[i] = RREG32(rom_data_offset);
527
528 return true;
529 }
530
531 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
532 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
533 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
534 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
535 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
536 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
537 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
538 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
539 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
540 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
541 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
542 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
543 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
544 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
545 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
546 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
547 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
548 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
549 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
550 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
551 { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
552 };
553
soc15_read_indexed_register(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 reg_offset)554 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
555 u32 sh_num, u32 reg_offset)
556 {
557 uint32_t val;
558
559 mutex_lock(&adev->grbm_idx_mutex);
560 if (se_num != 0xffffffff || sh_num != 0xffffffff)
561 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
562
563 val = RREG32(reg_offset);
564
565 if (se_num != 0xffffffff || sh_num != 0xffffffff)
566 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
567 mutex_unlock(&adev->grbm_idx_mutex);
568 return val;
569 }
570
soc15_get_register_value(struct amdgpu_device * adev,bool indexed,u32 se_num,u32 sh_num,u32 reg_offset)571 static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
572 bool indexed, u32 se_num,
573 u32 sh_num, u32 reg_offset)
574 {
575 if (indexed) {
576 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
577 } else {
578 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
579 return adev->gfx.config.gb_addr_config;
580 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
581 return adev->gfx.config.db_debug2;
582 return RREG32(reg_offset);
583 }
584 }
585
soc15_read_register(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 reg_offset,u32 * value)586 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
587 u32 sh_num, u32 reg_offset, u32 *value)
588 {
589 uint32_t i;
590 struct soc15_allowed_register_entry *en;
591
592 *value = 0;
593 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
594 en = &soc15_allowed_read_registers[i];
595 if (adev->reg_offset[en->hwip][en->inst] &&
596 reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
597 + en->reg_offset))
598 continue;
599
600 *value = soc15_get_register_value(adev,
601 soc15_allowed_read_registers[i].grbm_indexed,
602 se_num, sh_num, reg_offset);
603 return 0;
604 }
605 return -EINVAL;
606 }
607
608
609 /**
610 * soc15_program_register_sequence - program an array of registers.
611 *
612 * @adev: amdgpu_device pointer
613 * @regs: pointer to the register array
614 * @array_size: size of the register array
615 *
616 * Programs an array or registers with and and or masks.
617 * This is a helper for setting golden registers.
618 */
619
soc15_program_register_sequence(struct amdgpu_device * adev,const struct soc15_reg_golden * regs,const u32 array_size)620 void soc15_program_register_sequence(struct amdgpu_device *adev,
621 const struct soc15_reg_golden *regs,
622 const u32 array_size)
623 {
624 const struct soc15_reg_golden *entry;
625 u32 tmp, reg;
626 int i;
627
628 for (i = 0; i < array_size; ++i) {
629 entry = ®s[i];
630 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
631
632 if (entry->and_mask == 0xffffffff) {
633 tmp = entry->or_mask;
634 } else {
635 tmp = RREG32(reg);
636 tmp &= ~(entry->and_mask);
637 tmp |= (entry->or_mask & entry->and_mask);
638 }
639
640 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) ||
641 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) ||
642 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) ||
643 reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG))
644 WREG32_RLC(reg, tmp);
645 else
646 WREG32(reg, tmp);
647
648 }
649
650 }
651
soc15_asic_baco_reset(struct amdgpu_device * adev)652 static int soc15_asic_baco_reset(struct amdgpu_device *adev)
653 {
654 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
655 int ret = 0;
656
657 /* avoid NBIF got stuck when do RAS recovery in BACO reset */
658 if (ras && ras->supported)
659 adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
660
661 ret = amdgpu_dpm_baco_reset(adev);
662 if (ret)
663 return ret;
664
665 /* re-enable doorbell interrupt after BACO exit */
666 if (ras && ras->supported)
667 adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
668
669 return 0;
670 }
671
672 static enum amd_reset_method
soc15_asic_reset_method(struct amdgpu_device * adev)673 soc15_asic_reset_method(struct amdgpu_device *adev)
674 {
675 bool baco_reset = false;
676 bool connected_to_cpu = false;
677 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
678
679 if (adev->gmc.xgmi.supported && adev->gmc.xgmi.connected_to_cpu)
680 connected_to_cpu = true;
681
682 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
683 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
684 amdgpu_reset_method == AMD_RESET_METHOD_BACO ||
685 amdgpu_reset_method == AMD_RESET_METHOD_PCI) {
686 /* If connected to cpu, driver only support mode2 */
687 if (connected_to_cpu)
688 return AMD_RESET_METHOD_MODE2;
689 return amdgpu_reset_method;
690 }
691
692 if (amdgpu_reset_method != -1)
693 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
694 amdgpu_reset_method);
695
696 switch (adev->asic_type) {
697 case CHIP_RAVEN:
698 case CHIP_RENOIR:
699 return AMD_RESET_METHOD_MODE2;
700 case CHIP_VEGA10:
701 case CHIP_VEGA12:
702 case CHIP_ARCTURUS:
703 baco_reset = amdgpu_dpm_is_baco_supported(adev);
704 break;
705 case CHIP_VEGA20:
706 if (adev->psp.sos_fw_version >= 0x80067)
707 baco_reset = amdgpu_dpm_is_baco_supported(adev);
708
709 /*
710 * 1. PMFW version > 0x284300: all cases use baco
711 * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco
712 */
713 if ((ras && ras->supported) && adev->pm.fw_version <= 0x283400)
714 baco_reset = false;
715 break;
716 case CHIP_ALDEBARAN:
717 /*
718 * 1.connected to cpu: driver issue mode2 reset
719 * 2.discret gpu: driver issue mode1 reset
720 */
721 if (connected_to_cpu)
722 return AMD_RESET_METHOD_MODE2;
723 break;
724 default:
725 break;
726 }
727
728 if (baco_reset)
729 return AMD_RESET_METHOD_BACO;
730 else
731 return AMD_RESET_METHOD_MODE1;
732 }
733
soc15_asic_reset(struct amdgpu_device * adev)734 static int soc15_asic_reset(struct amdgpu_device *adev)
735 {
736 /* original raven doesn't have full asic reset */
737 if ((adev->apu_flags & AMD_APU_IS_RAVEN) &&
738 !(adev->apu_flags & AMD_APU_IS_RAVEN2))
739 return 0;
740
741 switch (soc15_asic_reset_method(adev)) {
742 case AMD_RESET_METHOD_PCI:
743 dev_info(adev->dev, "PCI reset\n");
744 return amdgpu_device_pci_reset(adev);
745 case AMD_RESET_METHOD_BACO:
746 dev_info(adev->dev, "BACO reset\n");
747 return soc15_asic_baco_reset(adev);
748 case AMD_RESET_METHOD_MODE2:
749 dev_info(adev->dev, "MODE2 reset\n");
750 return amdgpu_dpm_mode2_reset(adev);
751 default:
752 dev_info(adev->dev, "MODE1 reset\n");
753 return amdgpu_device_mode1_reset(adev);
754 }
755 }
756
soc15_supports_baco(struct amdgpu_device * adev)757 static bool soc15_supports_baco(struct amdgpu_device *adev)
758 {
759 switch (adev->asic_type) {
760 case CHIP_VEGA10:
761 case CHIP_VEGA12:
762 case CHIP_ARCTURUS:
763 return amdgpu_dpm_is_baco_supported(adev);
764 case CHIP_VEGA20:
765 if (adev->psp.sos_fw_version >= 0x80067)
766 return amdgpu_dpm_is_baco_supported(adev);
767 return false;
768 default:
769 return false;
770 }
771 }
772
773 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
774 u32 cntl_reg, u32 status_reg)
775 {
776 return 0;
777 }*/
778
soc15_set_uvd_clocks(struct amdgpu_device * adev,u32 vclk,u32 dclk)779 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
780 {
781 /*int r;
782
783 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
784 if (r)
785 return r;
786
787 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
788 */
789 return 0;
790 }
791
soc15_set_vce_clocks(struct amdgpu_device * adev,u32 evclk,u32 ecclk)792 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
793 {
794 /* todo */
795
796 return 0;
797 }
798
soc15_pcie_gen3_enable(struct amdgpu_device * adev)799 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
800 {
801 if (pci_is_root_bus(adev->pdev->bus))
802 return;
803
804 if (amdgpu_pcie_gen2 == 0)
805 return;
806
807 if (adev->flags & AMD_IS_APU)
808 return;
809
810 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
811 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
812 return;
813
814 /* todo */
815 }
816
soc15_program_aspm(struct amdgpu_device * adev)817 static void soc15_program_aspm(struct amdgpu_device *adev)
818 {
819 if (amdgpu_aspm != 1)
820 return;
821
822 if (!(adev->flags & AMD_IS_APU) &&
823 (adev->nbio.funcs->program_aspm))
824 adev->nbio.funcs->program_aspm(adev);
825 }
826
soc15_enable_doorbell_aperture(struct amdgpu_device * adev,bool enable)827 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
828 bool enable)
829 {
830 adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
831 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
832 }
833
834 static const struct amdgpu_ip_block_version vega10_common_ip_block =
835 {
836 .type = AMD_IP_BLOCK_TYPE_COMMON,
837 .major = 2,
838 .minor = 0,
839 .rev = 0,
840 .funcs = &soc15_common_ip_funcs,
841 };
842
soc15_get_rev_id(struct amdgpu_device * adev)843 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
844 {
845 return adev->nbio.funcs->get_rev_id(adev);
846 }
847
soc15_reg_base_init(struct amdgpu_device * adev)848 static void soc15_reg_base_init(struct amdgpu_device *adev)
849 {
850 int r;
851
852 /* Set IP register base before any HW register access */
853 switch (adev->asic_type) {
854 case CHIP_VEGA10:
855 case CHIP_VEGA12:
856 case CHIP_RAVEN:
857 vega10_reg_base_init(adev);
858 break;
859 case CHIP_RENOIR:
860 /* It's safe to do ip discovery here for Renior,
861 * it doesn't support SRIOV. */
862 if (amdgpu_discovery) {
863 r = amdgpu_discovery_reg_base_init(adev);
864 if (r == 0)
865 break;
866 DRM_WARN("failed to init reg base from ip discovery table, "
867 "fallback to legacy init method\n");
868 }
869 vega10_reg_base_init(adev);
870 break;
871 case CHIP_VEGA20:
872 vega20_reg_base_init(adev);
873 break;
874 case CHIP_ARCTURUS:
875 arct_reg_base_init(adev);
876 break;
877 case CHIP_ALDEBARAN:
878 aldebaran_reg_base_init(adev);
879 break;
880 default:
881 DRM_ERROR("Unsupported asic type: %d!\n", adev->asic_type);
882 break;
883 }
884 }
885
soc15_set_virt_ops(struct amdgpu_device * adev)886 void soc15_set_virt_ops(struct amdgpu_device *adev)
887 {
888 adev->virt.ops = &xgpu_ai_virt_ops;
889
890 /* init soc15 reg base early enough so we can
891 * request request full access for sriov before
892 * set_ip_blocks. */
893 soc15_reg_base_init(adev);
894 }
895
soc15_set_ip_blocks(struct amdgpu_device * adev)896 int soc15_set_ip_blocks(struct amdgpu_device *adev)
897 {
898 /* for bare metal case */
899 if (!amdgpu_sriov_vf(adev))
900 soc15_reg_base_init(adev);
901
902 if (adev->flags & AMD_IS_APU) {
903 adev->nbio.funcs = &nbio_v7_0_funcs;
904 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
905 } else if (adev->asic_type == CHIP_VEGA20 ||
906 adev->asic_type == CHIP_ARCTURUS ||
907 adev->asic_type == CHIP_ALDEBARAN) {
908 adev->nbio.funcs = &nbio_v7_4_funcs;
909 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
910 } else {
911 adev->nbio.funcs = &nbio_v6_1_funcs;
912 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
913 }
914 adev->hdp.funcs = &hdp_v4_0_funcs;
915
916 if (adev->asic_type == CHIP_VEGA20 ||
917 adev->asic_type == CHIP_ARCTURUS ||
918 adev->asic_type == CHIP_ALDEBARAN)
919 adev->df.funcs = &df_v3_6_funcs;
920 else
921 adev->df.funcs = &df_v1_7_funcs;
922
923 if (adev->asic_type == CHIP_VEGA20 ||
924 adev->asic_type == CHIP_ARCTURUS)
925 adev->smuio.funcs = &smuio_v11_0_funcs;
926 else if (adev->asic_type == CHIP_ALDEBARAN)
927 adev->smuio.funcs = &smuio_v13_0_funcs;
928 else
929 adev->smuio.funcs = &smuio_v9_0_funcs;
930
931 adev->rev_id = soc15_get_rev_id(adev);
932
933 switch (adev->asic_type) {
934 case CHIP_VEGA10:
935 case CHIP_VEGA12:
936 case CHIP_VEGA20:
937 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
938 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
939
940 /* For Vega10 SR-IOV, PSP need to be initialized before IH */
941 if (amdgpu_sriov_vf(adev)) {
942 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
943 if (adev->asic_type == CHIP_VEGA20)
944 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
945 else
946 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
947 }
948 if (adev->asic_type == CHIP_VEGA20)
949 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
950 else
951 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
952 } else {
953 if (adev->asic_type == CHIP_VEGA20)
954 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
955 else
956 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
957 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
958 if (adev->asic_type == CHIP_VEGA20)
959 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
960 else
961 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
962 }
963 }
964 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
965 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
966 if (is_support_sw_smu(adev)) {
967 if (!amdgpu_sriov_vf(adev))
968 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
969 } else {
970 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
971 }
972 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
973 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
974 #if defined(CONFIG_DRM_AMD_DC)
975 else if (amdgpu_device_has_dc_support(adev))
976 amdgpu_device_ip_block_add(adev, &dm_ip_block);
977 #endif
978 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) {
979 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
980 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
981 }
982 break;
983 case CHIP_RAVEN:
984 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
985 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
986 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
987 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
988 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
989 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
990 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
991 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
992 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
993 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
994 #if defined(CONFIG_DRM_AMD_DC)
995 else if (amdgpu_device_has_dc_support(adev))
996 amdgpu_device_ip_block_add(adev, &dm_ip_block);
997 #endif
998 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
999 break;
1000 case CHIP_ARCTURUS:
1001 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
1002 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
1003
1004 if (amdgpu_sriov_vf(adev)) {
1005 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
1006 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
1007 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
1008 } else {
1009 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
1010 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
1011 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
1012 }
1013
1014 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
1015 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1016 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
1017 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
1018 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
1019
1020 if (amdgpu_sriov_vf(adev)) {
1021 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
1022 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
1023 } else {
1024 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
1025 }
1026 if (!amdgpu_sriov_vf(adev))
1027 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
1028 break;
1029 case CHIP_RENOIR:
1030 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
1031 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
1032 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
1033 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
1034 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
1035 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
1036 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
1037 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
1038 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
1039 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1040 #if defined(CONFIG_DRM_AMD_DC)
1041 else if (amdgpu_device_has_dc_support(adev))
1042 amdgpu_device_ip_block_add(adev, &dm_ip_block);
1043 #endif
1044 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
1045 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
1046 break;
1047 case CHIP_ALDEBARAN:
1048 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
1049 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
1050
1051 if (amdgpu_sriov_vf(adev)) {
1052 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
1053 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
1054 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
1055 } else {
1056 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
1057 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
1058 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
1059 }
1060
1061 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
1062 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
1063
1064 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
1065 amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block);
1066 amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block);
1067 break;
1068 default:
1069 return -EINVAL;
1070 }
1071
1072 return 0;
1073 }
1074
soc15_need_full_reset(struct amdgpu_device * adev)1075 static bool soc15_need_full_reset(struct amdgpu_device *adev)
1076 {
1077 /* change this when we implement soft reset */
1078 return true;
1079 }
1080
soc15_get_pcie_usage(struct amdgpu_device * adev,uint64_t * count0,uint64_t * count1)1081 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
1082 uint64_t *count1)
1083 {
1084 uint32_t perfctr = 0;
1085 uint64_t cnt0_of, cnt1_of;
1086 int tmp;
1087
1088 /* This reports 0 on APUs, so return to avoid writing/reading registers
1089 * that may or may not be different from their GPU counterparts
1090 */
1091 if (adev->flags & AMD_IS_APU)
1092 return;
1093
1094 /* Set the 2 events that we wish to watch, defined above */
1095 /* Reg 40 is # received msgs */
1096 /* Reg 104 is # of posted requests sent */
1097 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
1098 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
1099
1100 /* Write to enable desired perf counters */
1101 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr);
1102 /* Zero out and enable the perf counters
1103 * Write 0x5:
1104 * Bit 0 = Start all counters(1)
1105 * Bit 2 = Global counter reset enable(1)
1106 */
1107 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
1108
1109 msleep(1000);
1110
1111 /* Load the shadow and disable the perf counters
1112 * Write 0x2:
1113 * Bit 0 = Stop counters(0)
1114 * Bit 1 = Load the shadow counters(1)
1115 */
1116 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
1117
1118 /* Read register values to get any >32bit overflow */
1119 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK);
1120 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
1121 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
1122
1123 /* Get the values and add the overflow */
1124 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
1125 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
1126 }
1127
vega20_get_pcie_usage(struct amdgpu_device * adev,uint64_t * count0,uint64_t * count1)1128 static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
1129 uint64_t *count1)
1130 {
1131 uint32_t perfctr = 0;
1132 uint64_t cnt0_of, cnt1_of;
1133 int tmp;
1134
1135 /* This reports 0 on APUs, so return to avoid writing/reading registers
1136 * that may or may not be different from their GPU counterparts
1137 */
1138 if (adev->flags & AMD_IS_APU)
1139 return;
1140
1141 /* Set the 2 events that we wish to watch, defined above */
1142 /* Reg 40 is # received msgs */
1143 /* Reg 108 is # of posted requests sent on VG20 */
1144 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
1145 EVENT0_SEL, 40);
1146 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
1147 EVENT1_SEL, 108);
1148
1149 /* Write to enable desired perf counters */
1150 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr);
1151 /* Zero out and enable the perf counters
1152 * Write 0x5:
1153 * Bit 0 = Start all counters(1)
1154 * Bit 2 = Global counter reset enable(1)
1155 */
1156 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
1157
1158 msleep(1000);
1159
1160 /* Load the shadow and disable the perf counters
1161 * Write 0x2:
1162 * Bit 0 = Stop counters(0)
1163 * Bit 1 = Load the shadow counters(1)
1164 */
1165 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
1166
1167 /* Read register values to get any >32bit overflow */
1168 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3);
1169 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER);
1170 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER);
1171
1172 /* Get the values and add the overflow */
1173 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32);
1174 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32);
1175 }
1176
soc15_need_reset_on_init(struct amdgpu_device * adev)1177 static bool soc15_need_reset_on_init(struct amdgpu_device *adev)
1178 {
1179 u32 sol_reg;
1180
1181 /* Just return false for soc15 GPUs. Reset does not seem to
1182 * be necessary.
1183 */
1184 if (!amdgpu_passthrough(adev))
1185 return false;
1186
1187 if (adev->flags & AMD_IS_APU)
1188 return false;
1189
1190 /* Check sOS sign of life register to confirm sys driver and sOS
1191 * are already been loaded.
1192 */
1193 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
1194 if (sol_reg)
1195 return true;
1196
1197 return false;
1198 }
1199
soc15_get_pcie_replay_count(struct amdgpu_device * adev)1200 static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev)
1201 {
1202 uint64_t nak_r, nak_g;
1203
1204 /* Get the number of NAKs received and generated */
1205 nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK);
1206 nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED);
1207
1208 /* Add the total number of NAKs, i.e the number of replays */
1209 return (nak_r + nak_g);
1210 }
1211
soc15_pre_asic_init(struct amdgpu_device * adev)1212 static void soc15_pre_asic_init(struct amdgpu_device *adev)
1213 {
1214 gmc_v9_0_restore_registers(adev);
1215 }
1216
1217 static const struct amdgpu_asic_funcs soc15_asic_funcs =
1218 {
1219 .read_disabled_bios = &soc15_read_disabled_bios,
1220 .read_bios_from_rom = &soc15_read_bios_from_rom,
1221 .read_register = &soc15_read_register,
1222 .reset = &soc15_asic_reset,
1223 .reset_method = &soc15_asic_reset_method,
1224 .set_vga_state = &soc15_vga_set_state,
1225 .get_xclk = &soc15_get_xclk,
1226 .set_uvd_clocks = &soc15_set_uvd_clocks,
1227 .set_vce_clocks = &soc15_set_vce_clocks,
1228 .get_config_memsize = &soc15_get_config_memsize,
1229 .need_full_reset = &soc15_need_full_reset,
1230 .init_doorbell_index = &vega10_doorbell_index_init,
1231 .get_pcie_usage = &soc15_get_pcie_usage,
1232 .need_reset_on_init = &soc15_need_reset_on_init,
1233 .get_pcie_replay_count = &soc15_get_pcie_replay_count,
1234 .supports_baco = &soc15_supports_baco,
1235 .pre_asic_init = &soc15_pre_asic_init,
1236 .query_video_codecs = &soc15_query_video_codecs,
1237 };
1238
1239 static const struct amdgpu_asic_funcs vega20_asic_funcs =
1240 {
1241 .read_disabled_bios = &soc15_read_disabled_bios,
1242 .read_bios_from_rom = &soc15_read_bios_from_rom,
1243 .read_register = &soc15_read_register,
1244 .reset = &soc15_asic_reset,
1245 .reset_method = &soc15_asic_reset_method,
1246 .set_vga_state = &soc15_vga_set_state,
1247 .get_xclk = &soc15_get_xclk,
1248 .set_uvd_clocks = &soc15_set_uvd_clocks,
1249 .set_vce_clocks = &soc15_set_vce_clocks,
1250 .get_config_memsize = &soc15_get_config_memsize,
1251 .need_full_reset = &soc15_need_full_reset,
1252 .init_doorbell_index = &vega20_doorbell_index_init,
1253 .get_pcie_usage = &vega20_get_pcie_usage,
1254 .need_reset_on_init = &soc15_need_reset_on_init,
1255 .get_pcie_replay_count = &soc15_get_pcie_replay_count,
1256 .supports_baco = &soc15_supports_baco,
1257 .pre_asic_init = &soc15_pre_asic_init,
1258 .query_video_codecs = &soc15_query_video_codecs,
1259 };
1260
soc15_common_early_init(void * handle)1261 static int soc15_common_early_init(void *handle)
1262 {
1263 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
1264 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1265
1266 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
1267 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
1268 adev->smc_rreg = NULL;
1269 adev->smc_wreg = NULL;
1270 adev->pcie_rreg = &soc15_pcie_rreg;
1271 adev->pcie_wreg = &soc15_pcie_wreg;
1272 adev->pcie_rreg64 = &soc15_pcie_rreg64;
1273 adev->pcie_wreg64 = &soc15_pcie_wreg64;
1274 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
1275 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
1276 adev->didt_rreg = &soc15_didt_rreg;
1277 adev->didt_wreg = &soc15_didt_wreg;
1278 adev->gc_cac_rreg = &soc15_gc_cac_rreg;
1279 adev->gc_cac_wreg = &soc15_gc_cac_wreg;
1280 adev->se_cac_rreg = &soc15_se_cac_rreg;
1281 adev->se_cac_wreg = &soc15_se_cac_wreg;
1282
1283
1284 adev->external_rev_id = 0xFF;
1285 switch (adev->asic_type) {
1286 case CHIP_VEGA10:
1287 adev->asic_funcs = &soc15_asic_funcs;
1288 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1289 AMD_CG_SUPPORT_GFX_MGLS |
1290 AMD_CG_SUPPORT_GFX_RLC_LS |
1291 AMD_CG_SUPPORT_GFX_CP_LS |
1292 AMD_CG_SUPPORT_GFX_3D_CGCG |
1293 AMD_CG_SUPPORT_GFX_3D_CGLS |
1294 AMD_CG_SUPPORT_GFX_CGCG |
1295 AMD_CG_SUPPORT_GFX_CGLS |
1296 AMD_CG_SUPPORT_BIF_MGCG |
1297 AMD_CG_SUPPORT_BIF_LS |
1298 AMD_CG_SUPPORT_HDP_LS |
1299 AMD_CG_SUPPORT_DRM_MGCG |
1300 AMD_CG_SUPPORT_DRM_LS |
1301 AMD_CG_SUPPORT_ROM_MGCG |
1302 AMD_CG_SUPPORT_DF_MGCG |
1303 AMD_CG_SUPPORT_SDMA_MGCG |
1304 AMD_CG_SUPPORT_SDMA_LS |
1305 AMD_CG_SUPPORT_MC_MGCG |
1306 AMD_CG_SUPPORT_MC_LS;
1307 adev->pg_flags = 0;
1308 adev->external_rev_id = 0x1;
1309 break;
1310 case CHIP_VEGA12:
1311 adev->asic_funcs = &soc15_asic_funcs;
1312 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1313 AMD_CG_SUPPORT_GFX_MGLS |
1314 AMD_CG_SUPPORT_GFX_CGCG |
1315 AMD_CG_SUPPORT_GFX_CGLS |
1316 AMD_CG_SUPPORT_GFX_3D_CGCG |
1317 AMD_CG_SUPPORT_GFX_3D_CGLS |
1318 AMD_CG_SUPPORT_GFX_CP_LS |
1319 AMD_CG_SUPPORT_MC_LS |
1320 AMD_CG_SUPPORT_MC_MGCG |
1321 AMD_CG_SUPPORT_SDMA_MGCG |
1322 AMD_CG_SUPPORT_SDMA_LS |
1323 AMD_CG_SUPPORT_BIF_MGCG |
1324 AMD_CG_SUPPORT_BIF_LS |
1325 AMD_CG_SUPPORT_HDP_MGCG |
1326 AMD_CG_SUPPORT_HDP_LS |
1327 AMD_CG_SUPPORT_ROM_MGCG |
1328 AMD_CG_SUPPORT_VCE_MGCG |
1329 AMD_CG_SUPPORT_UVD_MGCG;
1330 adev->pg_flags = 0;
1331 adev->external_rev_id = adev->rev_id + 0x14;
1332 break;
1333 case CHIP_VEGA20:
1334 adev->asic_funcs = &vega20_asic_funcs;
1335 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1336 AMD_CG_SUPPORT_GFX_MGLS |
1337 AMD_CG_SUPPORT_GFX_CGCG |
1338 AMD_CG_SUPPORT_GFX_CGLS |
1339 AMD_CG_SUPPORT_GFX_3D_CGCG |
1340 AMD_CG_SUPPORT_GFX_3D_CGLS |
1341 AMD_CG_SUPPORT_GFX_CP_LS |
1342 AMD_CG_SUPPORT_MC_LS |
1343 AMD_CG_SUPPORT_MC_MGCG |
1344 AMD_CG_SUPPORT_SDMA_MGCG |
1345 AMD_CG_SUPPORT_SDMA_LS |
1346 AMD_CG_SUPPORT_BIF_MGCG |
1347 AMD_CG_SUPPORT_BIF_LS |
1348 AMD_CG_SUPPORT_HDP_MGCG |
1349 AMD_CG_SUPPORT_HDP_LS |
1350 AMD_CG_SUPPORT_ROM_MGCG |
1351 AMD_CG_SUPPORT_VCE_MGCG |
1352 AMD_CG_SUPPORT_UVD_MGCG;
1353 adev->pg_flags = 0;
1354 adev->external_rev_id = adev->rev_id + 0x28;
1355 break;
1356 case CHIP_RAVEN:
1357 adev->asic_funcs = &soc15_asic_funcs;
1358 if (adev->pdev->device == 0x15dd)
1359 adev->apu_flags |= AMD_APU_IS_RAVEN;
1360 if (adev->pdev->device == 0x15d8)
1361 adev->apu_flags |= AMD_APU_IS_PICASSO;
1362 if (adev->rev_id >= 0x8)
1363 adev->apu_flags |= AMD_APU_IS_RAVEN2;
1364
1365 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1366 adev->external_rev_id = adev->rev_id + 0x79;
1367 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1368 adev->external_rev_id = adev->rev_id + 0x41;
1369 else if (adev->rev_id == 1)
1370 adev->external_rev_id = adev->rev_id + 0x20;
1371 else
1372 adev->external_rev_id = adev->rev_id + 0x01;
1373
1374 if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
1375 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1376 AMD_CG_SUPPORT_GFX_MGLS |
1377 AMD_CG_SUPPORT_GFX_CP_LS |
1378 AMD_CG_SUPPORT_GFX_3D_CGCG |
1379 AMD_CG_SUPPORT_GFX_3D_CGLS |
1380 AMD_CG_SUPPORT_GFX_CGCG |
1381 AMD_CG_SUPPORT_GFX_CGLS |
1382 AMD_CG_SUPPORT_BIF_LS |
1383 AMD_CG_SUPPORT_HDP_LS |
1384 AMD_CG_SUPPORT_MC_MGCG |
1385 AMD_CG_SUPPORT_MC_LS |
1386 AMD_CG_SUPPORT_SDMA_MGCG |
1387 AMD_CG_SUPPORT_SDMA_LS |
1388 AMD_CG_SUPPORT_VCN_MGCG;
1389
1390 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1391 } else if (adev->apu_flags & AMD_APU_IS_PICASSO) {
1392 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1393 AMD_CG_SUPPORT_GFX_MGLS |
1394 AMD_CG_SUPPORT_GFX_CP_LS |
1395 AMD_CG_SUPPORT_GFX_3D_CGCG |
1396 AMD_CG_SUPPORT_GFX_3D_CGLS |
1397 AMD_CG_SUPPORT_GFX_CGCG |
1398 AMD_CG_SUPPORT_GFX_CGLS |
1399 AMD_CG_SUPPORT_BIF_LS |
1400 AMD_CG_SUPPORT_HDP_LS |
1401 AMD_CG_SUPPORT_MC_MGCG |
1402 AMD_CG_SUPPORT_MC_LS |
1403 AMD_CG_SUPPORT_SDMA_MGCG |
1404 AMD_CG_SUPPORT_SDMA_LS |
1405 AMD_CG_SUPPORT_VCN_MGCG;
1406
1407 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1408 AMD_PG_SUPPORT_MMHUB |
1409 AMD_PG_SUPPORT_VCN;
1410 } else {
1411 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1412 AMD_CG_SUPPORT_GFX_MGLS |
1413 AMD_CG_SUPPORT_GFX_RLC_LS |
1414 AMD_CG_SUPPORT_GFX_CP_LS |
1415 AMD_CG_SUPPORT_GFX_3D_CGCG |
1416 AMD_CG_SUPPORT_GFX_3D_CGLS |
1417 AMD_CG_SUPPORT_GFX_CGCG |
1418 AMD_CG_SUPPORT_GFX_CGLS |
1419 AMD_CG_SUPPORT_BIF_MGCG |
1420 AMD_CG_SUPPORT_BIF_LS |
1421 AMD_CG_SUPPORT_HDP_MGCG |
1422 AMD_CG_SUPPORT_HDP_LS |
1423 AMD_CG_SUPPORT_DRM_MGCG |
1424 AMD_CG_SUPPORT_DRM_LS |
1425 AMD_CG_SUPPORT_MC_MGCG |
1426 AMD_CG_SUPPORT_MC_LS |
1427 AMD_CG_SUPPORT_SDMA_MGCG |
1428 AMD_CG_SUPPORT_SDMA_LS |
1429 AMD_CG_SUPPORT_VCN_MGCG;
1430
1431 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1432 }
1433 break;
1434 case CHIP_ARCTURUS:
1435 adev->asic_funcs = &vega20_asic_funcs;
1436 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1437 AMD_CG_SUPPORT_GFX_MGLS |
1438 AMD_CG_SUPPORT_GFX_CGCG |
1439 AMD_CG_SUPPORT_GFX_CGLS |
1440 AMD_CG_SUPPORT_GFX_CP_LS |
1441 AMD_CG_SUPPORT_HDP_MGCG |
1442 AMD_CG_SUPPORT_HDP_LS |
1443 AMD_CG_SUPPORT_SDMA_MGCG |
1444 AMD_CG_SUPPORT_SDMA_LS |
1445 AMD_CG_SUPPORT_MC_MGCG |
1446 AMD_CG_SUPPORT_MC_LS |
1447 AMD_CG_SUPPORT_IH_CG |
1448 AMD_CG_SUPPORT_VCN_MGCG |
1449 AMD_CG_SUPPORT_JPEG_MGCG;
1450 adev->pg_flags = AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG;
1451 adev->external_rev_id = adev->rev_id + 0x32;
1452 break;
1453 case CHIP_RENOIR:
1454 adev->asic_funcs = &soc15_asic_funcs;
1455 if ((adev->pdev->device == 0x1636) ||
1456 (adev->pdev->device == 0x164c))
1457 adev->apu_flags |= AMD_APU_IS_RENOIR;
1458 else
1459 adev->apu_flags |= AMD_APU_IS_GREEN_SARDINE;
1460
1461 if (adev->apu_flags & AMD_APU_IS_RENOIR)
1462 adev->external_rev_id = adev->rev_id + 0x91;
1463 else
1464 adev->external_rev_id = adev->rev_id + 0xa1;
1465 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1466 AMD_CG_SUPPORT_GFX_MGLS |
1467 AMD_CG_SUPPORT_GFX_3D_CGCG |
1468 AMD_CG_SUPPORT_GFX_3D_CGLS |
1469 AMD_CG_SUPPORT_GFX_CGCG |
1470 AMD_CG_SUPPORT_GFX_CGLS |
1471 AMD_CG_SUPPORT_GFX_CP_LS |
1472 AMD_CG_SUPPORT_MC_MGCG |
1473 AMD_CG_SUPPORT_MC_LS |
1474 AMD_CG_SUPPORT_SDMA_MGCG |
1475 AMD_CG_SUPPORT_SDMA_LS |
1476 AMD_CG_SUPPORT_BIF_LS |
1477 AMD_CG_SUPPORT_HDP_LS |
1478 AMD_CG_SUPPORT_VCN_MGCG |
1479 AMD_CG_SUPPORT_JPEG_MGCG |
1480 AMD_CG_SUPPORT_IH_CG |
1481 AMD_CG_SUPPORT_ATHUB_LS |
1482 AMD_CG_SUPPORT_ATHUB_MGCG |
1483 AMD_CG_SUPPORT_DF_MGCG;
1484 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1485 AMD_PG_SUPPORT_VCN |
1486 AMD_PG_SUPPORT_JPEG |
1487 AMD_PG_SUPPORT_VCN_DPG;
1488 break;
1489 case CHIP_ALDEBARAN:
1490 adev->asic_funcs = &vega20_asic_funcs;
1491 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1492 AMD_CG_SUPPORT_GFX_MGLS |
1493 AMD_CG_SUPPORT_GFX_CGCG |
1494 AMD_CG_SUPPORT_GFX_CGLS |
1495 AMD_CG_SUPPORT_GFX_CP_LS |
1496 AMD_CG_SUPPORT_HDP_LS |
1497 AMD_CG_SUPPORT_SDMA_MGCG |
1498 AMD_CG_SUPPORT_SDMA_LS |
1499 AMD_CG_SUPPORT_IH_CG |
1500 AMD_CG_SUPPORT_VCN_MGCG | AMD_CG_SUPPORT_JPEG_MGCG;
1501 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG;
1502 adev->external_rev_id = adev->rev_id + 0x3c;
1503 break;
1504 default:
1505 /* FIXME: not supported yet */
1506 return -EINVAL;
1507 }
1508
1509 if (amdgpu_sriov_vf(adev)) {
1510 amdgpu_virt_init_setting(adev);
1511 xgpu_ai_mailbox_set_irq_funcs(adev);
1512 }
1513
1514 return 0;
1515 }
1516
soc15_common_late_init(void * handle)1517 static int soc15_common_late_init(void *handle)
1518 {
1519 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1520 int r = 0;
1521
1522 if (amdgpu_sriov_vf(adev))
1523 xgpu_ai_mailbox_get_irq(adev);
1524
1525 if (adev->hdp.funcs->reset_ras_error_count)
1526 adev->hdp.funcs->reset_ras_error_count(adev);
1527
1528 if (adev->nbio.ras_funcs &&
1529 adev->nbio.ras_funcs->ras_late_init)
1530 r = adev->nbio.ras_funcs->ras_late_init(adev);
1531
1532 return r;
1533 }
1534
soc15_common_sw_init(void * handle)1535 static int soc15_common_sw_init(void *handle)
1536 {
1537 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1538
1539 if (amdgpu_sriov_vf(adev))
1540 xgpu_ai_mailbox_add_irq_id(adev);
1541
1542 adev->df.funcs->sw_init(adev);
1543
1544 return 0;
1545 }
1546
soc15_common_sw_fini(void * handle)1547 static int soc15_common_sw_fini(void *handle)
1548 {
1549 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1550
1551 if (adev->nbio.ras_funcs &&
1552 adev->nbio.ras_funcs->ras_fini)
1553 adev->nbio.ras_funcs->ras_fini(adev);
1554 adev->df.funcs->sw_fini(adev);
1555 return 0;
1556 }
1557
soc15_doorbell_range_init(struct amdgpu_device * adev)1558 static void soc15_doorbell_range_init(struct amdgpu_device *adev)
1559 {
1560 int i;
1561 struct amdgpu_ring *ring;
1562
1563 /* sdma/ih doorbell range are programed by hypervisor */
1564 if (!amdgpu_sriov_vf(adev)) {
1565 for (i = 0; i < adev->sdma.num_instances; i++) {
1566 ring = &adev->sdma.instance[i].ring;
1567 adev->nbio.funcs->sdma_doorbell_range(adev, i,
1568 ring->use_doorbell, ring->doorbell_index,
1569 adev->doorbell_index.sdma_doorbell_range);
1570 }
1571
1572 adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
1573 adev->irq.ih.doorbell_index);
1574 }
1575 }
1576
soc15_common_hw_init(void * handle)1577 static int soc15_common_hw_init(void *handle)
1578 {
1579 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1580
1581 /* enable pcie gen2/3 link */
1582 soc15_pcie_gen3_enable(adev);
1583 /* enable aspm */
1584 soc15_program_aspm(adev);
1585 /* setup nbio registers */
1586 adev->nbio.funcs->init_registers(adev);
1587 /* remap HDP registers to a hole in mmio space,
1588 * for the purpose of expose those registers
1589 * to process space
1590 */
1591 if (adev->nbio.funcs->remap_hdp_registers)
1592 adev->nbio.funcs->remap_hdp_registers(adev);
1593
1594 /* enable the doorbell aperture */
1595 soc15_enable_doorbell_aperture(adev, true);
1596 /* HW doorbell routing policy: doorbell writing not
1597 * in SDMA/IH/MM/ACV range will be routed to CP. So
1598 * we need to init SDMA/IH/MM/ACV doorbell range prior
1599 * to CP ip block init and ring test.
1600 */
1601 soc15_doorbell_range_init(adev);
1602
1603 return 0;
1604 }
1605
soc15_common_hw_fini(void * handle)1606 static int soc15_common_hw_fini(void *handle)
1607 {
1608 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1609
1610 /* disable the doorbell aperture */
1611 soc15_enable_doorbell_aperture(adev, false);
1612 if (amdgpu_sriov_vf(adev))
1613 xgpu_ai_mailbox_put_irq(adev);
1614
1615 if (adev->nbio.ras_if &&
1616 amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {
1617 if (adev->nbio.ras_funcs &&
1618 adev->nbio.ras_funcs->init_ras_controller_interrupt)
1619 amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0);
1620 if (adev->nbio.ras_funcs &&
1621 adev->nbio.ras_funcs->init_ras_err_event_athub_interrupt)
1622 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0);
1623 }
1624
1625 return 0;
1626 }
1627
soc15_common_suspend(void * handle)1628 static int soc15_common_suspend(void *handle)
1629 {
1630 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1631
1632 return soc15_common_hw_fini(adev);
1633 }
1634
soc15_common_resume(void * handle)1635 static int soc15_common_resume(void *handle)
1636 {
1637 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1638
1639 return soc15_common_hw_init(adev);
1640 }
1641
soc15_common_is_idle(void * handle)1642 static bool soc15_common_is_idle(void *handle)
1643 {
1644 return true;
1645 }
1646
soc15_common_wait_for_idle(void * handle)1647 static int soc15_common_wait_for_idle(void *handle)
1648 {
1649 return 0;
1650 }
1651
soc15_common_soft_reset(void * handle)1652 static int soc15_common_soft_reset(void *handle)
1653 {
1654 return 0;
1655 }
1656
soc15_update_drm_clock_gating(struct amdgpu_device * adev,bool enable)1657 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
1658 {
1659 uint32_t def, data;
1660
1661 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1662
1663 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
1664 data &= ~(0x01000000 |
1665 0x02000000 |
1666 0x04000000 |
1667 0x08000000 |
1668 0x10000000 |
1669 0x20000000 |
1670 0x40000000 |
1671 0x80000000);
1672 else
1673 data |= (0x01000000 |
1674 0x02000000 |
1675 0x04000000 |
1676 0x08000000 |
1677 0x10000000 |
1678 0x20000000 |
1679 0x40000000 |
1680 0x80000000);
1681
1682 if (def != data)
1683 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
1684 }
1685
soc15_update_drm_light_sleep(struct amdgpu_device * adev,bool enable)1686 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
1687 {
1688 uint32_t def, data;
1689
1690 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1691
1692 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1693 data |= 1;
1694 else
1695 data &= ~1;
1696
1697 if (def != data)
1698 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
1699 }
1700
soc15_common_set_clockgating_state(void * handle,enum amd_clockgating_state state)1701 static int soc15_common_set_clockgating_state(void *handle,
1702 enum amd_clockgating_state state)
1703 {
1704 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1705
1706 if (amdgpu_sriov_vf(adev))
1707 return 0;
1708
1709 switch (adev->asic_type) {
1710 case CHIP_VEGA10:
1711 case CHIP_VEGA12:
1712 case CHIP_VEGA20:
1713 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1714 state == AMD_CG_STATE_GATE);
1715 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1716 state == AMD_CG_STATE_GATE);
1717 adev->hdp.funcs->update_clock_gating(adev,
1718 state == AMD_CG_STATE_GATE);
1719 soc15_update_drm_clock_gating(adev,
1720 state == AMD_CG_STATE_GATE);
1721 soc15_update_drm_light_sleep(adev,
1722 state == AMD_CG_STATE_GATE);
1723 adev->smuio.funcs->update_rom_clock_gating(adev,
1724 state == AMD_CG_STATE_GATE);
1725 adev->df.funcs->update_medium_grain_clock_gating(adev,
1726 state == AMD_CG_STATE_GATE);
1727 break;
1728 case CHIP_RAVEN:
1729 case CHIP_RENOIR:
1730 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1731 state == AMD_CG_STATE_GATE);
1732 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1733 state == AMD_CG_STATE_GATE);
1734 adev->hdp.funcs->update_clock_gating(adev,
1735 state == AMD_CG_STATE_GATE);
1736 soc15_update_drm_clock_gating(adev,
1737 state == AMD_CG_STATE_GATE);
1738 soc15_update_drm_light_sleep(adev,
1739 state == AMD_CG_STATE_GATE);
1740 break;
1741 case CHIP_ARCTURUS:
1742 case CHIP_ALDEBARAN:
1743 adev->hdp.funcs->update_clock_gating(adev,
1744 state == AMD_CG_STATE_GATE);
1745 break;
1746 default:
1747 break;
1748 }
1749 return 0;
1750 }
1751
soc15_common_get_clockgating_state(void * handle,u32 * flags)1752 static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
1753 {
1754 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1755 int data;
1756
1757 if (amdgpu_sriov_vf(adev))
1758 *flags = 0;
1759
1760 adev->nbio.funcs->get_clockgating_state(adev, flags);
1761
1762 adev->hdp.funcs->get_clock_gating_state(adev, flags);
1763
1764 if (adev->asic_type != CHIP_ALDEBARAN) {
1765
1766 /* AMD_CG_SUPPORT_DRM_MGCG */
1767 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1768 if (!(data & 0x01000000))
1769 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
1770
1771 /* AMD_CG_SUPPORT_DRM_LS */
1772 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1773 if (data & 0x1)
1774 *flags |= AMD_CG_SUPPORT_DRM_LS;
1775 }
1776
1777 /* AMD_CG_SUPPORT_ROM_MGCG */
1778 adev->smuio.funcs->get_clock_gating_state(adev, flags);
1779
1780 adev->df.funcs->get_clockgating_state(adev, flags);
1781 }
1782
soc15_common_set_powergating_state(void * handle,enum amd_powergating_state state)1783 static int soc15_common_set_powergating_state(void *handle,
1784 enum amd_powergating_state state)
1785 {
1786 /* todo */
1787 return 0;
1788 }
1789
1790 const struct amd_ip_funcs soc15_common_ip_funcs = {
1791 .name = "soc15_common",
1792 .early_init = soc15_common_early_init,
1793 .late_init = soc15_common_late_init,
1794 .sw_init = soc15_common_sw_init,
1795 .sw_fini = soc15_common_sw_fini,
1796 .hw_init = soc15_common_hw_init,
1797 .hw_fini = soc15_common_hw_fini,
1798 .suspend = soc15_common_suspend,
1799 .resume = soc15_common_resume,
1800 .is_idle = soc15_common_is_idle,
1801 .wait_for_idle = soc15_common_wait_for_idle,
1802 .soft_reset = soc15_common_soft_reset,
1803 .set_clockgating_state = soc15_common_set_clockgating_state,
1804 .set_powergating_state = soc15_common_set_powergating_state,
1805 .get_clockgating_state= soc15_common_get_clockgating_state,
1806 };
1807