1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 /**
25 * DOC: Frame Buffer Compression (FBC)
26 *
27 * FBC tries to save memory bandwidth (and so power consumption) by
28 * compressing the amount of memory used by the display. It is total
29 * transparent to user space and completely handled in the kernel.
30 *
31 * The benefits of FBC are mostly visible with solid backgrounds and
32 * variation-less patterns. It comes from keeping the memory footprint small
33 * and having fewer memory pages opened and accessed for refreshing the display.
34 *
35 * i915 is responsible to reserve stolen memory for FBC and configure its
36 * offset on proper registers. The hardware takes care of all
37 * compress/decompress. However there are many known cases where we have to
38 * forcibly disable it to allow proper screen updates.
39 */
40
41 #include <drm/drm_fourcc.h>
42
43 #include "i915_drv.h"
44 #include "i915_trace.h"
45 #include "i915_vgpu.h"
46 #include "intel_display_types.h"
47 #include "intel_fbc.h"
48 #include "intel_frontbuffer.h"
49
50 /*
51 * For SKL+, the plane source size used by the hardware is based on the value we
52 * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value
53 * we wrote to PIPESRC.
54 */
intel_fbc_get_plane_source_size(const struct intel_fbc_state_cache * cache,int * width,int * height)55 static void intel_fbc_get_plane_source_size(const struct intel_fbc_state_cache *cache,
56 int *width, int *height)
57 {
58 if (width)
59 *width = cache->plane.src_w;
60 if (height)
61 *height = cache->plane.src_h;
62 }
63
intel_fbc_calculate_cfb_size(struct drm_i915_private * dev_priv,const struct intel_fbc_state_cache * cache)64 static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
65 const struct intel_fbc_state_cache *cache)
66 {
67 int lines;
68
69 intel_fbc_get_plane_source_size(cache, NULL, &lines);
70 if (IS_DISPLAY_VER(dev_priv, 7))
71 lines = min(lines, 2048);
72 else if (DISPLAY_VER(dev_priv) >= 8)
73 lines = min(lines, 2560);
74
75 /* Hardware needs the full buffer stride, not just the active area. */
76 return lines * cache->fb.stride;
77 }
78
i8xx_fbc_deactivate(struct drm_i915_private * dev_priv)79 static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv)
80 {
81 u32 fbc_ctl;
82
83 /* Disable compression */
84 fbc_ctl = intel_de_read(dev_priv, FBC_CONTROL);
85 if ((fbc_ctl & FBC_CTL_EN) == 0)
86 return;
87
88 fbc_ctl &= ~FBC_CTL_EN;
89 intel_de_write(dev_priv, FBC_CONTROL, fbc_ctl);
90
91 /* Wait for compressing bit to clear */
92 if (intel_de_wait_for_clear(dev_priv, FBC_STATUS,
93 FBC_STAT_COMPRESSING, 10)) {
94 drm_dbg_kms(&dev_priv->drm, "FBC idle timed out\n");
95 return;
96 }
97 }
98
i8xx_fbc_activate(struct drm_i915_private * dev_priv)99 static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
100 {
101 struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
102 int cfb_pitch;
103 int i;
104 u32 fbc_ctl;
105
106 /* Note: fbc.threshold == 1 for i8xx */
107 cfb_pitch = params->cfb_size / FBC_LL_SIZE;
108 if (params->fb.stride < cfb_pitch)
109 cfb_pitch = params->fb.stride;
110
111 /* FBC_CTL wants 32B or 64B units */
112 if (IS_DISPLAY_VER(dev_priv, 2))
113 cfb_pitch = (cfb_pitch / 32) - 1;
114 else
115 cfb_pitch = (cfb_pitch / 64) - 1;
116
117 /* Clear old tags */
118 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
119 intel_de_write(dev_priv, FBC_TAG(i), 0);
120
121 if (IS_DISPLAY_VER(dev_priv, 4)) {
122 u32 fbc_ctl2;
123
124 /* Set it up... */
125 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM;
126 fbc_ctl2 |= FBC_CTL_PLANE(params->crtc.i9xx_plane);
127 if (params->fence_id >= 0)
128 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
129 intel_de_write(dev_priv, FBC_CONTROL2, fbc_ctl2);
130 intel_de_write(dev_priv, FBC_FENCE_OFF,
131 params->fence_y_offset);
132 }
133
134 /* enable it... */
135 fbc_ctl = FBC_CTL_INTERVAL(params->interval);
136 fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
137 if (IS_I945GM(dev_priv))
138 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
139 fbc_ctl |= FBC_CTL_STRIDE(cfb_pitch & 0xff);
140 if (params->fence_id >= 0)
141 fbc_ctl |= FBC_CTL_FENCENO(params->fence_id);
142 intel_de_write(dev_priv, FBC_CONTROL, fbc_ctl);
143 }
144
i8xx_fbc_is_active(struct drm_i915_private * dev_priv)145 static bool i8xx_fbc_is_active(struct drm_i915_private *dev_priv)
146 {
147 return intel_de_read(dev_priv, FBC_CONTROL) & FBC_CTL_EN;
148 }
149
g4x_fbc_activate(struct drm_i915_private * dev_priv)150 static void g4x_fbc_activate(struct drm_i915_private *dev_priv)
151 {
152 struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
153 u32 dpfc_ctl;
154
155 dpfc_ctl = DPFC_CTL_PLANE(params->crtc.i9xx_plane) | DPFC_SR_EN;
156 if (params->fb.format->cpp[0] == 2)
157 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
158 else
159 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
160
161 if (params->fence_id >= 0) {
162 dpfc_ctl |= DPFC_CTL_FENCE_EN | params->fence_id;
163 intel_de_write(dev_priv, DPFC_FENCE_YOFF,
164 params->fence_y_offset);
165 } else {
166 intel_de_write(dev_priv, DPFC_FENCE_YOFF, 0);
167 }
168
169 /* enable it... */
170 intel_de_write(dev_priv, DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
171 }
172
g4x_fbc_deactivate(struct drm_i915_private * dev_priv)173 static void g4x_fbc_deactivate(struct drm_i915_private *dev_priv)
174 {
175 u32 dpfc_ctl;
176
177 /* Disable compression */
178 dpfc_ctl = intel_de_read(dev_priv, DPFC_CONTROL);
179 if (dpfc_ctl & DPFC_CTL_EN) {
180 dpfc_ctl &= ~DPFC_CTL_EN;
181 intel_de_write(dev_priv, DPFC_CONTROL, dpfc_ctl);
182 }
183 }
184
g4x_fbc_is_active(struct drm_i915_private * dev_priv)185 static bool g4x_fbc_is_active(struct drm_i915_private *dev_priv)
186 {
187 return intel_de_read(dev_priv, DPFC_CONTROL) & DPFC_CTL_EN;
188 }
189
i8xx_fbc_recompress(struct drm_i915_private * dev_priv)190 static void i8xx_fbc_recompress(struct drm_i915_private *dev_priv)
191 {
192 struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
193 enum i9xx_plane_id i9xx_plane = params->crtc.i9xx_plane;
194
195 spin_lock_irq(&dev_priv->uncore.lock);
196 intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane),
197 intel_de_read_fw(dev_priv, DSPADDR(i9xx_plane)));
198 spin_unlock_irq(&dev_priv->uncore.lock);
199 }
200
i965_fbc_recompress(struct drm_i915_private * dev_priv)201 static void i965_fbc_recompress(struct drm_i915_private *dev_priv)
202 {
203 struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
204 enum i9xx_plane_id i9xx_plane = params->crtc.i9xx_plane;
205
206 spin_lock_irq(&dev_priv->uncore.lock);
207 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
208 intel_de_read_fw(dev_priv, DSPSURF(i9xx_plane)));
209 spin_unlock_irq(&dev_priv->uncore.lock);
210 }
211
212 /* This function forces a CFB recompression through the nuke operation. */
snb_fbc_recompress(struct drm_i915_private * dev_priv)213 static void snb_fbc_recompress(struct drm_i915_private *dev_priv)
214 {
215 struct intel_fbc *fbc = &dev_priv->fbc;
216
217 trace_intel_fbc_nuke(fbc->crtc);
218
219 intel_de_write(dev_priv, MSG_FBC_REND_STATE, FBC_REND_NUKE);
220 intel_de_posting_read(dev_priv, MSG_FBC_REND_STATE);
221 }
222
intel_fbc_recompress(struct drm_i915_private * dev_priv)223 static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
224 {
225 if (DISPLAY_VER(dev_priv) >= 6)
226 snb_fbc_recompress(dev_priv);
227 else if (DISPLAY_VER(dev_priv) >= 4)
228 i965_fbc_recompress(dev_priv);
229 else
230 i8xx_fbc_recompress(dev_priv);
231 }
232
ilk_fbc_activate(struct drm_i915_private * dev_priv)233 static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
234 {
235 struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
236 u32 dpfc_ctl;
237 int threshold = dev_priv->fbc.threshold;
238
239 dpfc_ctl = DPFC_CTL_PLANE(params->crtc.i9xx_plane);
240 if (params->fb.format->cpp[0] == 2)
241 threshold++;
242
243 switch (threshold) {
244 case 4:
245 case 3:
246 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
247 break;
248 case 2:
249 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
250 break;
251 case 1:
252 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
253 break;
254 }
255
256 if (params->fence_id >= 0) {
257 dpfc_ctl |= DPFC_CTL_FENCE_EN;
258 if (IS_IRONLAKE(dev_priv))
259 dpfc_ctl |= params->fence_id;
260 if (IS_SANDYBRIDGE(dev_priv)) {
261 intel_de_write(dev_priv, SNB_DPFC_CTL_SA,
262 SNB_CPU_FENCE_ENABLE | params->fence_id);
263 intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET,
264 params->fence_y_offset);
265 }
266 } else {
267 if (IS_SANDYBRIDGE(dev_priv)) {
268 intel_de_write(dev_priv, SNB_DPFC_CTL_SA, 0);
269 intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET, 0);
270 }
271 }
272
273 intel_de_write(dev_priv, ILK_DPFC_FENCE_YOFF,
274 params->fence_y_offset);
275 /* enable it... */
276 intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
277
278 intel_fbc_recompress(dev_priv);
279 }
280
ilk_fbc_deactivate(struct drm_i915_private * dev_priv)281 static void ilk_fbc_deactivate(struct drm_i915_private *dev_priv)
282 {
283 u32 dpfc_ctl;
284
285 /* Disable compression */
286 dpfc_ctl = intel_de_read(dev_priv, ILK_DPFC_CONTROL);
287 if (dpfc_ctl & DPFC_CTL_EN) {
288 dpfc_ctl &= ~DPFC_CTL_EN;
289 intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl);
290 }
291 }
292
ilk_fbc_is_active(struct drm_i915_private * dev_priv)293 static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv)
294 {
295 return intel_de_read(dev_priv, ILK_DPFC_CONTROL) & DPFC_CTL_EN;
296 }
297
gen7_fbc_activate(struct drm_i915_private * dev_priv)298 static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
299 {
300 struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
301 u32 dpfc_ctl;
302 int threshold = dev_priv->fbc.threshold;
303
304 /* Display WA #0529: skl, kbl, bxt. */
305 if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) {
306 u32 val = intel_de_read(dev_priv, CHICKEN_MISC_4);
307
308 val &= ~(FBC_STRIDE_OVERRIDE | FBC_STRIDE_MASK);
309
310 if (params->gen9_wa_cfb_stride)
311 val |= FBC_STRIDE_OVERRIDE | params->gen9_wa_cfb_stride;
312
313 intel_de_write(dev_priv, CHICKEN_MISC_4, val);
314 }
315
316 dpfc_ctl = 0;
317 if (IS_IVYBRIDGE(dev_priv))
318 dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.i9xx_plane);
319
320 if (params->fb.format->cpp[0] == 2)
321 threshold++;
322
323 switch (threshold) {
324 case 4:
325 case 3:
326 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
327 break;
328 case 2:
329 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
330 break;
331 case 1:
332 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
333 break;
334 }
335
336 if (params->fence_id >= 0) {
337 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
338 intel_de_write(dev_priv, SNB_DPFC_CTL_SA,
339 SNB_CPU_FENCE_ENABLE | params->fence_id);
340 intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET,
341 params->fence_y_offset);
342 } else if (dev_priv->ggtt.num_fences) {
343 intel_de_write(dev_priv, SNB_DPFC_CTL_SA, 0);
344 intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET, 0);
345 }
346
347 if (dev_priv->fbc.false_color)
348 dpfc_ctl |= FBC_CTL_FALSE_COLOR;
349
350 intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
351
352 intel_fbc_recompress(dev_priv);
353 }
354
intel_fbc_hw_is_active(struct drm_i915_private * dev_priv)355 static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv)
356 {
357 if (DISPLAY_VER(dev_priv) >= 5)
358 return ilk_fbc_is_active(dev_priv);
359 else if (IS_GM45(dev_priv))
360 return g4x_fbc_is_active(dev_priv);
361 else
362 return i8xx_fbc_is_active(dev_priv);
363 }
364
intel_fbc_hw_activate(struct drm_i915_private * dev_priv)365 static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv)
366 {
367 struct intel_fbc *fbc = &dev_priv->fbc;
368
369 trace_intel_fbc_activate(fbc->crtc);
370
371 fbc->active = true;
372 fbc->activated = true;
373
374 if (DISPLAY_VER(dev_priv) >= 7)
375 gen7_fbc_activate(dev_priv);
376 else if (DISPLAY_VER(dev_priv) >= 5)
377 ilk_fbc_activate(dev_priv);
378 else if (IS_GM45(dev_priv))
379 g4x_fbc_activate(dev_priv);
380 else
381 i8xx_fbc_activate(dev_priv);
382 }
383
intel_fbc_hw_deactivate(struct drm_i915_private * dev_priv)384 static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv)
385 {
386 struct intel_fbc *fbc = &dev_priv->fbc;
387
388 trace_intel_fbc_deactivate(fbc->crtc);
389
390 fbc->active = false;
391
392 if (DISPLAY_VER(dev_priv) >= 5)
393 ilk_fbc_deactivate(dev_priv);
394 else if (IS_GM45(dev_priv))
395 g4x_fbc_deactivate(dev_priv);
396 else
397 i8xx_fbc_deactivate(dev_priv);
398 }
399
400 /**
401 * intel_fbc_is_active - Is FBC active?
402 * @dev_priv: i915 device instance
403 *
404 * This function is used to verify the current state of FBC.
405 *
406 * FIXME: This should be tracked in the plane config eventually
407 * instead of queried at runtime for most callers.
408 */
intel_fbc_is_active(struct drm_i915_private * dev_priv)409 bool intel_fbc_is_active(struct drm_i915_private *dev_priv)
410 {
411 return dev_priv->fbc.active;
412 }
413
intel_fbc_deactivate(struct drm_i915_private * dev_priv,const char * reason)414 static void intel_fbc_deactivate(struct drm_i915_private *dev_priv,
415 const char *reason)
416 {
417 struct intel_fbc *fbc = &dev_priv->fbc;
418
419 drm_WARN_ON(&dev_priv->drm, !mutex_is_locked(&fbc->lock));
420
421 if (fbc->active)
422 intel_fbc_hw_deactivate(dev_priv);
423
424 fbc->no_fbc_reason = reason;
425 }
426
intel_fbc_cfb_base_max(struct drm_i915_private * i915)427 static u64 intel_fbc_cfb_base_max(struct drm_i915_private *i915)
428 {
429 if (DISPLAY_VER(i915) >= 5 || IS_G4X(i915))
430 return BIT_ULL(28);
431 else
432 return BIT_ULL(32);
433 }
434
find_compression_threshold(struct drm_i915_private * dev_priv,struct drm_mm_node * node,unsigned int size,unsigned int fb_cpp)435 static int find_compression_threshold(struct drm_i915_private *dev_priv,
436 struct drm_mm_node *node,
437 unsigned int size,
438 unsigned int fb_cpp)
439 {
440 int compression_threshold = 1;
441 int ret;
442 u64 end;
443
444 /* The FBC hardware for BDW/SKL doesn't have access to the stolen
445 * reserved range size, so it always assumes the maximum (8mb) is used.
446 * If we enable FBC using a CFB on that memory range we'll get FIFO
447 * underruns, even if that range is not reserved by the BIOS. */
448 if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv))
449 end = resource_size(&dev_priv->dsm) - 8 * 1024 * 1024;
450 else
451 end = U64_MAX;
452
453 end = min(end, intel_fbc_cfb_base_max(dev_priv));
454
455 /* HACK: This code depends on what we will do in *_enable_fbc. If that
456 * code changes, this code needs to change as well.
457 *
458 * The enable_fbc code will attempt to use one of our 2 compression
459 * thresholds, therefore, in that case, we only have 1 resort.
460 */
461
462 /* Try to over-allocate to reduce reallocations and fragmentation. */
463 ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size <<= 1,
464 4096, 0, end);
465 if (ret == 0)
466 return compression_threshold;
467
468 again:
469 /* HW's ability to limit the CFB is 1:4 */
470 if (compression_threshold > 4 ||
471 (fb_cpp == 2 && compression_threshold == 2))
472 return 0;
473
474 ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1,
475 4096, 0, end);
476 if (ret && DISPLAY_VER(dev_priv) <= 4) {
477 return 0;
478 } else if (ret) {
479 compression_threshold <<= 1;
480 goto again;
481 } else {
482 return compression_threshold;
483 }
484 }
485
intel_fbc_alloc_cfb(struct drm_i915_private * dev_priv,unsigned int size,unsigned int fb_cpp)486 static int intel_fbc_alloc_cfb(struct drm_i915_private *dev_priv,
487 unsigned int size, unsigned int fb_cpp)
488 {
489 struct intel_fbc *fbc = &dev_priv->fbc;
490 struct drm_mm_node *compressed_llb;
491 int ret;
492
493 drm_WARN_ON(&dev_priv->drm,
494 drm_mm_node_allocated(&fbc->compressed_fb));
495
496 ret = find_compression_threshold(dev_priv, &fbc->compressed_fb,
497 size, fb_cpp);
498 if (!ret)
499 goto err_llb;
500 else if (ret > 1) {
501 drm_info_once(&dev_priv->drm,
502 "Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n");
503 }
504
505 fbc->threshold = ret;
506
507 if (DISPLAY_VER(dev_priv) >= 5)
508 intel_de_write(dev_priv, ILK_DPFC_CB_BASE,
509 fbc->compressed_fb.start);
510 else if (IS_GM45(dev_priv)) {
511 intel_de_write(dev_priv, DPFC_CB_BASE,
512 fbc->compressed_fb.start);
513 } else {
514 compressed_llb = kzalloc(sizeof(*compressed_llb), GFP_KERNEL);
515 if (!compressed_llb)
516 goto err_fb;
517
518 ret = i915_gem_stolen_insert_node(dev_priv, compressed_llb,
519 4096, 4096);
520 if (ret)
521 goto err_fb;
522
523 fbc->compressed_llb = compressed_llb;
524
525 GEM_BUG_ON(range_overflows_end_t(u64, dev_priv->dsm.start,
526 fbc->compressed_fb.start,
527 U32_MAX));
528 GEM_BUG_ON(range_overflows_end_t(u64, dev_priv->dsm.start,
529 fbc->compressed_llb->start,
530 U32_MAX));
531 intel_de_write(dev_priv, FBC_CFB_BASE,
532 dev_priv->dsm.start + fbc->compressed_fb.start);
533 intel_de_write(dev_priv, FBC_LL_BASE,
534 dev_priv->dsm.start + compressed_llb->start);
535 }
536
537 drm_dbg_kms(&dev_priv->drm,
538 "reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n",
539 fbc->compressed_fb.size, fbc->threshold);
540
541 return 0;
542
543 err_fb:
544 kfree(compressed_llb);
545 i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
546 err_llb:
547 if (drm_mm_initialized(&dev_priv->mm.stolen))
548 drm_info_once(&dev_priv->drm, "not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size);
549 return -ENOSPC;
550 }
551
__intel_fbc_cleanup_cfb(struct drm_i915_private * dev_priv)552 static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
553 {
554 struct intel_fbc *fbc = &dev_priv->fbc;
555
556 if (WARN_ON(intel_fbc_hw_is_active(dev_priv)))
557 return;
558
559 if (!drm_mm_node_allocated(&fbc->compressed_fb))
560 return;
561
562 if (fbc->compressed_llb) {
563 i915_gem_stolen_remove_node(dev_priv, fbc->compressed_llb);
564 kfree(fbc->compressed_llb);
565 }
566
567 i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
568 }
569
intel_fbc_cleanup_cfb(struct drm_i915_private * dev_priv)570 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
571 {
572 struct intel_fbc *fbc = &dev_priv->fbc;
573
574 if (!HAS_FBC(dev_priv))
575 return;
576
577 mutex_lock(&fbc->lock);
578 __intel_fbc_cleanup_cfb(dev_priv);
579 mutex_unlock(&fbc->lock);
580 }
581
stride_is_valid(struct drm_i915_private * dev_priv,u64 modifier,unsigned int stride)582 static bool stride_is_valid(struct drm_i915_private *dev_priv,
583 u64 modifier, unsigned int stride)
584 {
585 /* This should have been caught earlier. */
586 if (drm_WARN_ON_ONCE(&dev_priv->drm, (stride & (64 - 1)) != 0))
587 return false;
588
589 /* Below are the additional FBC restrictions. */
590 if (stride < 512)
591 return false;
592
593 if (IS_DISPLAY_VER(dev_priv, 2) || IS_DISPLAY_VER(dev_priv, 3))
594 return stride == 4096 || stride == 8192;
595
596 if (IS_DISPLAY_VER(dev_priv, 4) && !IS_G4X(dev_priv) && stride < 2048)
597 return false;
598
599 /* Display WA #1105: skl,bxt,kbl,cfl,glk */
600 if ((IS_DISPLAY_VER(dev_priv, 9) || IS_GEMINILAKE(dev_priv)) &&
601 modifier == DRM_FORMAT_MOD_LINEAR && stride & 511)
602 return false;
603
604 if (stride > 16384)
605 return false;
606
607 return true;
608 }
609
pixel_format_is_valid(struct drm_i915_private * dev_priv,u32 pixel_format)610 static bool pixel_format_is_valid(struct drm_i915_private *dev_priv,
611 u32 pixel_format)
612 {
613 switch (pixel_format) {
614 case DRM_FORMAT_XRGB8888:
615 case DRM_FORMAT_XBGR8888:
616 return true;
617 case DRM_FORMAT_XRGB1555:
618 case DRM_FORMAT_RGB565:
619 /* 16bpp not supported on gen2 */
620 if (IS_DISPLAY_VER(dev_priv, 2))
621 return false;
622 /* WaFbcOnly1to1Ratio:ctg */
623 if (IS_G4X(dev_priv))
624 return false;
625 return true;
626 default:
627 return false;
628 }
629 }
630
rotation_is_valid(struct drm_i915_private * dev_priv,u32 pixel_format,unsigned int rotation)631 static bool rotation_is_valid(struct drm_i915_private *dev_priv,
632 u32 pixel_format, unsigned int rotation)
633 {
634 if (DISPLAY_VER(dev_priv) >= 9 && pixel_format == DRM_FORMAT_RGB565 &&
635 drm_rotation_90_or_270(rotation))
636 return false;
637 else if (DISPLAY_VER(dev_priv) <= 4 && !IS_G4X(dev_priv) &&
638 rotation != DRM_MODE_ROTATE_0)
639 return false;
640
641 return true;
642 }
643
644 /*
645 * For some reason, the hardware tracking starts looking at whatever we
646 * programmed as the display plane base address register. It does not look at
647 * the X and Y offset registers. That's why we include the src x/y offsets
648 * instead of just looking at the plane size.
649 */
intel_fbc_hw_tracking_covers_screen(struct intel_crtc * crtc)650 static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
651 {
652 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
653 struct intel_fbc *fbc = &dev_priv->fbc;
654 unsigned int effective_w, effective_h, max_w, max_h;
655
656 if (DISPLAY_VER(dev_priv) >= 10) {
657 max_w = 5120;
658 max_h = 4096;
659 } else if (DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv)) {
660 max_w = 4096;
661 max_h = 4096;
662 } else if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5) {
663 max_w = 4096;
664 max_h = 2048;
665 } else {
666 max_w = 2048;
667 max_h = 1536;
668 }
669
670 intel_fbc_get_plane_source_size(&fbc->state_cache, &effective_w,
671 &effective_h);
672 effective_w += fbc->state_cache.plane.adjusted_x;
673 effective_h += fbc->state_cache.plane.adjusted_y;
674
675 return effective_w <= max_w && effective_h <= max_h;
676 }
677
tiling_is_valid(struct drm_i915_private * dev_priv,u64 modifier)678 static bool tiling_is_valid(struct drm_i915_private *dev_priv,
679 u64 modifier)
680 {
681 switch (modifier) {
682 case DRM_FORMAT_MOD_LINEAR:
683 if (DISPLAY_VER(dev_priv) >= 9)
684 return true;
685 return false;
686 case I915_FORMAT_MOD_X_TILED:
687 case I915_FORMAT_MOD_Y_TILED:
688 return true;
689 default:
690 return false;
691 }
692 }
693
intel_fbc_update_state_cache(struct intel_crtc * crtc,const struct intel_crtc_state * crtc_state,const struct intel_plane_state * plane_state)694 static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
695 const struct intel_crtc_state *crtc_state,
696 const struct intel_plane_state *plane_state)
697 {
698 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
699 struct intel_fbc *fbc = &dev_priv->fbc;
700 struct intel_fbc_state_cache *cache = &fbc->state_cache;
701 struct drm_framebuffer *fb = plane_state->hw.fb;
702
703 cache->plane.visible = plane_state->uapi.visible;
704 if (!cache->plane.visible)
705 return;
706
707 cache->crtc.mode_flags = crtc_state->hw.adjusted_mode.flags;
708 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
709 cache->crtc.hsw_bdw_pixel_rate = crtc_state->pixel_rate;
710
711 cache->plane.rotation = plane_state->hw.rotation;
712 /*
713 * Src coordinates are already rotated by 270 degrees for
714 * the 90/270 degree plane rotation cases (to match the
715 * GTT mapping), hence no need to account for rotation here.
716 */
717 cache->plane.src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
718 cache->plane.src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
719 cache->plane.adjusted_x = plane_state->view.color_plane[0].x;
720 cache->plane.adjusted_y = plane_state->view.color_plane[0].y;
721
722 cache->plane.pixel_blend_mode = plane_state->hw.pixel_blend_mode;
723
724 cache->fb.format = fb->format;
725 cache->fb.modifier = fb->modifier;
726
727 /* FIXME is this correct? */
728 cache->fb.stride = plane_state->view.color_plane[0].stride;
729 if (drm_rotation_90_or_270(plane_state->hw.rotation))
730 cache->fb.stride *= fb->format->cpp[0];
731
732 /* FBC1 compression interval: arbitrary choice of 1 second */
733 cache->interval = drm_mode_vrefresh(&crtc_state->hw.adjusted_mode);
734
735 cache->fence_y_offset = intel_plane_fence_y_offset(plane_state);
736
737 drm_WARN_ON(&dev_priv->drm, plane_state->flags & PLANE_HAS_FENCE &&
738 !plane_state->vma->fence);
739
740 if (plane_state->flags & PLANE_HAS_FENCE &&
741 plane_state->vma->fence)
742 cache->fence_id = plane_state->vma->fence->id;
743 else
744 cache->fence_id = -1;
745
746 cache->psr2_active = crtc_state->has_psr2;
747 }
748
intel_fbc_cfb_size_changed(struct drm_i915_private * dev_priv)749 static bool intel_fbc_cfb_size_changed(struct drm_i915_private *dev_priv)
750 {
751 struct intel_fbc *fbc = &dev_priv->fbc;
752
753 return intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache) >
754 fbc->compressed_fb.size * fbc->threshold;
755 }
756
intel_fbc_gen9_wa_cfb_stride(struct drm_i915_private * dev_priv)757 static u16 intel_fbc_gen9_wa_cfb_stride(struct drm_i915_private *dev_priv)
758 {
759 struct intel_fbc *fbc = &dev_priv->fbc;
760 struct intel_fbc_state_cache *cache = &fbc->state_cache;
761
762 if ((IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) &&
763 cache->fb.modifier != I915_FORMAT_MOD_X_TILED)
764 return DIV_ROUND_UP(cache->plane.src_w, 32 * fbc->threshold) * 8;
765 else
766 return 0;
767 }
768
intel_fbc_gen9_wa_cfb_stride_changed(struct drm_i915_private * dev_priv)769 static bool intel_fbc_gen9_wa_cfb_stride_changed(struct drm_i915_private *dev_priv)
770 {
771 struct intel_fbc *fbc = &dev_priv->fbc;
772
773 return fbc->params.gen9_wa_cfb_stride != intel_fbc_gen9_wa_cfb_stride(dev_priv);
774 }
775
intel_fbc_can_enable(struct drm_i915_private * dev_priv)776 static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv)
777 {
778 struct intel_fbc *fbc = &dev_priv->fbc;
779
780 if (intel_vgpu_active(dev_priv)) {
781 fbc->no_fbc_reason = "VGPU is active";
782 return false;
783 }
784
785 if (!dev_priv->params.enable_fbc) {
786 fbc->no_fbc_reason = "disabled per module param or by default";
787 return false;
788 }
789
790 if (fbc->underrun_detected) {
791 fbc->no_fbc_reason = "underrun detected";
792 return false;
793 }
794
795 return true;
796 }
797
intel_fbc_can_activate(struct intel_crtc * crtc)798 static bool intel_fbc_can_activate(struct intel_crtc *crtc)
799 {
800 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
801 struct intel_fbc *fbc = &dev_priv->fbc;
802 struct intel_fbc_state_cache *cache = &fbc->state_cache;
803
804 if (!intel_fbc_can_enable(dev_priv))
805 return false;
806
807 if (!cache->plane.visible) {
808 fbc->no_fbc_reason = "primary plane not visible";
809 return false;
810 }
811
812 /* We don't need to use a state cache here since this information is
813 * global for all CRTC.
814 */
815 if (fbc->underrun_detected) {
816 fbc->no_fbc_reason = "underrun detected";
817 return false;
818 }
819
820 if (cache->crtc.mode_flags & DRM_MODE_FLAG_INTERLACE) {
821 fbc->no_fbc_reason = "incompatible mode";
822 return false;
823 }
824
825 if (!intel_fbc_hw_tracking_covers_screen(crtc)) {
826 fbc->no_fbc_reason = "mode too large for compression";
827 return false;
828 }
829
830 /* The use of a CPU fence is one of two ways to detect writes by the
831 * CPU to the scanout and trigger updates to the FBC.
832 *
833 * The other method is by software tracking (see
834 * intel_fbc_invalidate/flush()), it will manually notify FBC and nuke
835 * the current compressed buffer and recompress it.
836 *
837 * Note that is possible for a tiled surface to be unmappable (and
838 * so have no fence associated with it) due to aperture constraints
839 * at the time of pinning.
840 *
841 * FIXME with 90/270 degree rotation we should use the fence on
842 * the normal GTT view (the rotated view doesn't even have a
843 * fence). Would need changes to the FBC fence Y offset as well.
844 * For now this will effectively disable FBC with 90/270 degree
845 * rotation.
846 */
847 if (DISPLAY_VER(dev_priv) < 9 && cache->fence_id < 0) {
848 fbc->no_fbc_reason = "framebuffer not tiled or fenced";
849 return false;
850 }
851
852 if (!pixel_format_is_valid(dev_priv, cache->fb.format->format)) {
853 fbc->no_fbc_reason = "pixel format is invalid";
854 return false;
855 }
856
857 if (!rotation_is_valid(dev_priv, cache->fb.format->format,
858 cache->plane.rotation)) {
859 fbc->no_fbc_reason = "rotation unsupported";
860 return false;
861 }
862
863 if (!tiling_is_valid(dev_priv, cache->fb.modifier)) {
864 fbc->no_fbc_reason = "tiling unsupported";
865 return false;
866 }
867
868 if (!stride_is_valid(dev_priv, cache->fb.modifier, cache->fb.stride)) {
869 fbc->no_fbc_reason = "framebuffer stride not supported";
870 return false;
871 }
872
873 if (cache->plane.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE &&
874 cache->fb.format->has_alpha) {
875 fbc->no_fbc_reason = "per-pixel alpha blending is incompatible with FBC";
876 return false;
877 }
878
879 /* WaFbcExceedCdClockThreshold:hsw,bdw */
880 if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) &&
881 cache->crtc.hsw_bdw_pixel_rate >= dev_priv->cdclk.hw.cdclk * 95 / 100) {
882 fbc->no_fbc_reason = "pixel rate is too big";
883 return false;
884 }
885
886 /* It is possible for the required CFB size change without a
887 * crtc->disable + crtc->enable since it is possible to change the
888 * stride without triggering a full modeset. Since we try to
889 * over-allocate the CFB, there's a chance we may keep FBC enabled even
890 * if this happens, but if we exceed the current CFB size we'll have to
891 * disable FBC. Notice that it would be possible to disable FBC, wait
892 * for a frame, free the stolen node, then try to reenable FBC in case
893 * we didn't get any invalidate/deactivate calls, but this would require
894 * a lot of tracking just for a specific case. If we conclude it's an
895 * important case, we can implement it later. */
896 if (intel_fbc_cfb_size_changed(dev_priv)) {
897 fbc->no_fbc_reason = "CFB requirements changed";
898 return false;
899 }
900
901 /*
902 * Work around a problem on GEN9+ HW, where enabling FBC on a plane
903 * having a Y offset that isn't divisible by 4 causes FIFO underrun
904 * and screen flicker.
905 */
906 if (DISPLAY_VER(dev_priv) >= 9 &&
907 (fbc->state_cache.plane.adjusted_y & 3)) {
908 fbc->no_fbc_reason = "plane Y offset is misaligned";
909 return false;
910 }
911
912 /* Wa_22010751166: icl, ehl, tgl, dg1, rkl */
913 if (DISPLAY_VER(dev_priv) >= 11 &&
914 (cache->plane.src_h + cache->plane.adjusted_y) % 4) {
915 fbc->no_fbc_reason = "plane height + offset is non-modulo of 4";
916 return false;
917 }
918
919 /*
920 * Tigerlake is not supporting FBC with PSR2.
921 * Recommendation is to keep this combination disabled
922 * Bspec: 50422 HSD: 14010260002
923 */
924 if (fbc->state_cache.psr2_active && IS_TIGERLAKE(dev_priv)) {
925 fbc->no_fbc_reason = "not supported with PSR2";
926 return false;
927 }
928
929 return true;
930 }
931
intel_fbc_get_reg_params(struct intel_crtc * crtc,struct intel_fbc_reg_params * params)932 static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
933 struct intel_fbc_reg_params *params)
934 {
935 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
936 struct intel_fbc *fbc = &dev_priv->fbc;
937 struct intel_fbc_state_cache *cache = &fbc->state_cache;
938
939 /* Since all our fields are integer types, use memset here so the
940 * comparison function can rely on memcmp because the padding will be
941 * zero. */
942 memset(params, 0, sizeof(*params));
943
944 params->fence_id = cache->fence_id;
945 params->fence_y_offset = cache->fence_y_offset;
946
947 params->interval = cache->interval;
948
949 params->crtc.pipe = crtc->pipe;
950 params->crtc.i9xx_plane = to_intel_plane(crtc->base.primary)->i9xx_plane;
951
952 params->fb.format = cache->fb.format;
953 params->fb.modifier = cache->fb.modifier;
954 params->fb.stride = cache->fb.stride;
955
956 params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache);
957
958 params->gen9_wa_cfb_stride = cache->gen9_wa_cfb_stride;
959
960 params->plane_visible = cache->plane.visible;
961 }
962
intel_fbc_can_flip_nuke(const struct intel_crtc_state * crtc_state)963 static bool intel_fbc_can_flip_nuke(const struct intel_crtc_state *crtc_state)
964 {
965 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
966 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
967 const struct intel_fbc *fbc = &dev_priv->fbc;
968 const struct intel_fbc_state_cache *cache = &fbc->state_cache;
969 const struct intel_fbc_reg_params *params = &fbc->params;
970
971 if (drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
972 return false;
973
974 if (!params->plane_visible)
975 return false;
976
977 if (!intel_fbc_can_activate(crtc))
978 return false;
979
980 if (params->fb.format != cache->fb.format)
981 return false;
982
983 if (params->fb.modifier != cache->fb.modifier)
984 return false;
985
986 if (params->fb.stride != cache->fb.stride)
987 return false;
988
989 if (params->cfb_size != intel_fbc_calculate_cfb_size(dev_priv, cache))
990 return false;
991
992 if (params->gen9_wa_cfb_stride != cache->gen9_wa_cfb_stride)
993 return false;
994
995 return true;
996 }
997
intel_fbc_pre_update(struct intel_atomic_state * state,struct intel_crtc * crtc)998 bool intel_fbc_pre_update(struct intel_atomic_state *state,
999 struct intel_crtc *crtc)
1000 {
1001 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1002 const struct intel_crtc_state *crtc_state =
1003 intel_atomic_get_new_crtc_state(state, crtc);
1004 const struct intel_plane_state *plane_state =
1005 intel_atomic_get_new_plane_state(state, plane);
1006 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1007 struct intel_fbc *fbc = &dev_priv->fbc;
1008 const char *reason = "update pending";
1009 bool need_vblank_wait = false;
1010
1011 if (!plane->has_fbc || !plane_state)
1012 return need_vblank_wait;
1013
1014 mutex_lock(&fbc->lock);
1015
1016 if (fbc->crtc != crtc)
1017 goto unlock;
1018
1019 intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
1020 fbc->flip_pending = true;
1021
1022 if (!intel_fbc_can_flip_nuke(crtc_state)) {
1023 intel_fbc_deactivate(dev_priv, reason);
1024
1025 /*
1026 * Display WA #1198: glk+
1027 * Need an extra vblank wait between FBC disable and most plane
1028 * updates. Bspec says this is only needed for plane disable, but
1029 * that is not true. Touching most plane registers will cause the
1030 * corruption to appear. Also SKL/derivatives do not seem to be
1031 * affected.
1032 *
1033 * TODO: could optimize this a bit by sampling the frame
1034 * counter when we disable FBC (if it was already done earlier)
1035 * and skipping the extra vblank wait before the plane update
1036 * if at least one frame has already passed.
1037 */
1038 if (fbc->activated &&
1039 DISPLAY_VER(dev_priv) >= 10)
1040 need_vblank_wait = true;
1041 fbc->activated = false;
1042 }
1043 unlock:
1044 mutex_unlock(&fbc->lock);
1045
1046 return need_vblank_wait;
1047 }
1048
1049 /**
1050 * __intel_fbc_disable - disable FBC
1051 * @dev_priv: i915 device instance
1052 *
1053 * This is the low level function that actually disables FBC. Callers should
1054 * grab the FBC lock.
1055 */
__intel_fbc_disable(struct drm_i915_private * dev_priv)1056 static void __intel_fbc_disable(struct drm_i915_private *dev_priv)
1057 {
1058 struct intel_fbc *fbc = &dev_priv->fbc;
1059 struct intel_crtc *crtc = fbc->crtc;
1060
1061 drm_WARN_ON(&dev_priv->drm, !mutex_is_locked(&fbc->lock));
1062 drm_WARN_ON(&dev_priv->drm, !fbc->crtc);
1063 drm_WARN_ON(&dev_priv->drm, fbc->active);
1064
1065 drm_dbg_kms(&dev_priv->drm, "Disabling FBC on pipe %c\n",
1066 pipe_name(crtc->pipe));
1067
1068 __intel_fbc_cleanup_cfb(dev_priv);
1069
1070 fbc->crtc = NULL;
1071 }
1072
__intel_fbc_post_update(struct intel_crtc * crtc)1073 static void __intel_fbc_post_update(struct intel_crtc *crtc)
1074 {
1075 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1076 struct intel_fbc *fbc = &dev_priv->fbc;
1077
1078 drm_WARN_ON(&dev_priv->drm, !mutex_is_locked(&fbc->lock));
1079
1080 if (fbc->crtc != crtc)
1081 return;
1082
1083 fbc->flip_pending = false;
1084
1085 if (!dev_priv->params.enable_fbc) {
1086 intel_fbc_deactivate(dev_priv, "disabled at runtime per module param");
1087 __intel_fbc_disable(dev_priv);
1088
1089 return;
1090 }
1091
1092 intel_fbc_get_reg_params(crtc, &fbc->params);
1093
1094 if (!intel_fbc_can_activate(crtc))
1095 return;
1096
1097 if (!fbc->busy_bits)
1098 intel_fbc_hw_activate(dev_priv);
1099 else
1100 intel_fbc_deactivate(dev_priv, "frontbuffer write");
1101 }
1102
intel_fbc_post_update(struct intel_atomic_state * state,struct intel_crtc * crtc)1103 void intel_fbc_post_update(struct intel_atomic_state *state,
1104 struct intel_crtc *crtc)
1105 {
1106 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1107 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1108 const struct intel_plane_state *plane_state =
1109 intel_atomic_get_new_plane_state(state, plane);
1110 struct intel_fbc *fbc = &dev_priv->fbc;
1111
1112 if (!plane->has_fbc || !plane_state)
1113 return;
1114
1115 mutex_lock(&fbc->lock);
1116 __intel_fbc_post_update(crtc);
1117 mutex_unlock(&fbc->lock);
1118 }
1119
intel_fbc_get_frontbuffer_bit(struct intel_fbc * fbc)1120 static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc)
1121 {
1122 if (fbc->crtc)
1123 return to_intel_plane(fbc->crtc->base.primary)->frontbuffer_bit;
1124 else
1125 return fbc->possible_framebuffer_bits;
1126 }
1127
intel_fbc_invalidate(struct drm_i915_private * dev_priv,unsigned int frontbuffer_bits,enum fb_op_origin origin)1128 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1129 unsigned int frontbuffer_bits,
1130 enum fb_op_origin origin)
1131 {
1132 struct intel_fbc *fbc = &dev_priv->fbc;
1133
1134 if (!HAS_FBC(dev_priv))
1135 return;
1136
1137 if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
1138 return;
1139
1140 mutex_lock(&fbc->lock);
1141
1142 fbc->busy_bits |= intel_fbc_get_frontbuffer_bit(fbc) & frontbuffer_bits;
1143
1144 if (fbc->crtc && fbc->busy_bits)
1145 intel_fbc_deactivate(dev_priv, "frontbuffer write");
1146
1147 mutex_unlock(&fbc->lock);
1148 }
1149
intel_fbc_flush(struct drm_i915_private * dev_priv,unsigned int frontbuffer_bits,enum fb_op_origin origin)1150 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1151 unsigned int frontbuffer_bits, enum fb_op_origin origin)
1152 {
1153 struct intel_fbc *fbc = &dev_priv->fbc;
1154
1155 if (!HAS_FBC(dev_priv))
1156 return;
1157
1158 /*
1159 * GTT tracking does not nuke the entire cfb
1160 * so don't clear busy_bits set for some other
1161 * reason.
1162 */
1163 if (origin == ORIGIN_GTT)
1164 return;
1165
1166 mutex_lock(&fbc->lock);
1167
1168 fbc->busy_bits &= ~frontbuffer_bits;
1169
1170 if (origin == ORIGIN_FLIP)
1171 goto out;
1172
1173 if (!fbc->busy_bits && fbc->crtc &&
1174 (frontbuffer_bits & intel_fbc_get_frontbuffer_bit(fbc))) {
1175 if (fbc->active)
1176 intel_fbc_recompress(dev_priv);
1177 else if (!fbc->flip_pending)
1178 __intel_fbc_post_update(fbc->crtc);
1179 }
1180
1181 out:
1182 mutex_unlock(&fbc->lock);
1183 }
1184
1185 /**
1186 * intel_fbc_choose_crtc - select a CRTC to enable FBC on
1187 * @dev_priv: i915 device instance
1188 * @state: the atomic state structure
1189 *
1190 * This function looks at the proposed state for CRTCs and planes, then chooses
1191 * which pipe is going to have FBC by setting intel_crtc_state->enable_fbc to
1192 * true.
1193 *
1194 * Later, intel_fbc_enable is going to look for state->enable_fbc and then maybe
1195 * enable FBC for the chosen CRTC. If it does, it will set dev_priv->fbc.crtc.
1196 */
intel_fbc_choose_crtc(struct drm_i915_private * dev_priv,struct intel_atomic_state * state)1197 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1198 struct intel_atomic_state *state)
1199 {
1200 struct intel_fbc *fbc = &dev_priv->fbc;
1201 struct intel_plane *plane;
1202 struct intel_plane_state *plane_state;
1203 bool crtc_chosen = false;
1204 int i;
1205
1206 mutex_lock(&fbc->lock);
1207
1208 /* Does this atomic commit involve the CRTC currently tied to FBC? */
1209 if (fbc->crtc &&
1210 !intel_atomic_get_new_crtc_state(state, fbc->crtc))
1211 goto out;
1212
1213 if (!intel_fbc_can_enable(dev_priv))
1214 goto out;
1215
1216 /* Simply choose the first CRTC that is compatible and has a visible
1217 * plane. We could go for fancier schemes such as checking the plane
1218 * size, but this would just affect the few platforms that don't tie FBC
1219 * to pipe or plane A. */
1220 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1221 struct intel_crtc_state *crtc_state;
1222 struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);
1223
1224 if (!plane->has_fbc)
1225 continue;
1226
1227 if (!plane_state->uapi.visible)
1228 continue;
1229
1230 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
1231
1232 crtc_state->enable_fbc = true;
1233 crtc_chosen = true;
1234 break;
1235 }
1236
1237 if (!crtc_chosen)
1238 fbc->no_fbc_reason = "no suitable CRTC for FBC";
1239
1240 out:
1241 mutex_unlock(&fbc->lock);
1242 }
1243
1244 /**
1245 * intel_fbc_enable: tries to enable FBC on the CRTC
1246 * @crtc: the CRTC
1247 * @state: corresponding &drm_crtc_state for @crtc
1248 *
1249 * This function checks if the given CRTC was chosen for FBC, then enables it if
1250 * possible. Notice that it doesn't activate FBC. It is valid to call
1251 * intel_fbc_enable multiple times for the same pipe without an
1252 * intel_fbc_disable in the middle, as long as it is deactivated.
1253 */
intel_fbc_enable(struct intel_atomic_state * state,struct intel_crtc * crtc)1254 void intel_fbc_enable(struct intel_atomic_state *state,
1255 struct intel_crtc *crtc)
1256 {
1257 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1258 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1259 const struct intel_crtc_state *crtc_state =
1260 intel_atomic_get_new_crtc_state(state, crtc);
1261 const struct intel_plane_state *plane_state =
1262 intel_atomic_get_new_plane_state(state, plane);
1263 struct intel_fbc *fbc = &dev_priv->fbc;
1264 struct intel_fbc_state_cache *cache = &fbc->state_cache;
1265
1266 if (!plane->has_fbc || !plane_state)
1267 return;
1268
1269 mutex_lock(&fbc->lock);
1270
1271 if (fbc->crtc) {
1272 if (fbc->crtc != crtc ||
1273 (!intel_fbc_cfb_size_changed(dev_priv) &&
1274 !intel_fbc_gen9_wa_cfb_stride_changed(dev_priv)))
1275 goto out;
1276
1277 __intel_fbc_disable(dev_priv);
1278 }
1279
1280 drm_WARN_ON(&dev_priv->drm, fbc->active);
1281
1282 intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
1283
1284 /* FIXME crtc_state->enable_fbc lies :( */
1285 if (!cache->plane.visible)
1286 goto out;
1287
1288 if (intel_fbc_alloc_cfb(dev_priv,
1289 intel_fbc_calculate_cfb_size(dev_priv, cache),
1290 plane_state->hw.fb->format->cpp[0])) {
1291 cache->plane.visible = false;
1292 fbc->no_fbc_reason = "not enough stolen memory";
1293 goto out;
1294 }
1295
1296 cache->gen9_wa_cfb_stride = intel_fbc_gen9_wa_cfb_stride(dev_priv);
1297
1298 drm_dbg_kms(&dev_priv->drm, "Enabling FBC on pipe %c\n",
1299 pipe_name(crtc->pipe));
1300 fbc->no_fbc_reason = "FBC enabled but not active yet\n";
1301
1302 fbc->crtc = crtc;
1303 out:
1304 mutex_unlock(&fbc->lock);
1305 }
1306
1307 /**
1308 * intel_fbc_disable - disable FBC if it's associated with crtc
1309 * @crtc: the CRTC
1310 *
1311 * This function disables FBC if it's associated with the provided CRTC.
1312 */
intel_fbc_disable(struct intel_crtc * crtc)1313 void intel_fbc_disable(struct intel_crtc *crtc)
1314 {
1315 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1316 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1317 struct intel_fbc *fbc = &dev_priv->fbc;
1318
1319 if (!plane->has_fbc)
1320 return;
1321
1322 mutex_lock(&fbc->lock);
1323 if (fbc->crtc == crtc)
1324 __intel_fbc_disable(dev_priv);
1325 mutex_unlock(&fbc->lock);
1326 }
1327
1328 /**
1329 * intel_fbc_global_disable - globally disable FBC
1330 * @dev_priv: i915 device instance
1331 *
1332 * This function disables FBC regardless of which CRTC is associated with it.
1333 */
intel_fbc_global_disable(struct drm_i915_private * dev_priv)1334 void intel_fbc_global_disable(struct drm_i915_private *dev_priv)
1335 {
1336 struct intel_fbc *fbc = &dev_priv->fbc;
1337
1338 if (!HAS_FBC(dev_priv))
1339 return;
1340
1341 mutex_lock(&fbc->lock);
1342 if (fbc->crtc) {
1343 drm_WARN_ON(&dev_priv->drm, fbc->crtc->active);
1344 __intel_fbc_disable(dev_priv);
1345 }
1346 mutex_unlock(&fbc->lock);
1347 }
1348
intel_fbc_underrun_work_fn(struct work_struct * work)1349 static void intel_fbc_underrun_work_fn(struct work_struct *work)
1350 {
1351 struct drm_i915_private *dev_priv =
1352 container_of(work, struct drm_i915_private, fbc.underrun_work);
1353 struct intel_fbc *fbc = &dev_priv->fbc;
1354
1355 mutex_lock(&fbc->lock);
1356
1357 /* Maybe we were scheduled twice. */
1358 if (fbc->underrun_detected || !fbc->crtc)
1359 goto out;
1360
1361 drm_dbg_kms(&dev_priv->drm, "Disabling FBC due to FIFO underrun.\n");
1362 fbc->underrun_detected = true;
1363
1364 intel_fbc_deactivate(dev_priv, "FIFO underrun");
1365 out:
1366 mutex_unlock(&fbc->lock);
1367 }
1368
1369 /*
1370 * intel_fbc_reset_underrun - reset FBC fifo underrun status.
1371 * @dev_priv: i915 device instance
1372 *
1373 * See intel_fbc_handle_fifo_underrun_irq(). For automated testing we
1374 * want to re-enable FBC after an underrun to increase test coverage.
1375 */
intel_fbc_reset_underrun(struct drm_i915_private * dev_priv)1376 int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv)
1377 {
1378 int ret;
1379
1380 cancel_work_sync(&dev_priv->fbc.underrun_work);
1381
1382 ret = mutex_lock_interruptible(&dev_priv->fbc.lock);
1383 if (ret)
1384 return ret;
1385
1386 if (dev_priv->fbc.underrun_detected) {
1387 drm_dbg_kms(&dev_priv->drm,
1388 "Re-allowing FBC after fifo underrun\n");
1389 dev_priv->fbc.no_fbc_reason = "FIFO underrun cleared";
1390 }
1391
1392 dev_priv->fbc.underrun_detected = false;
1393 mutex_unlock(&dev_priv->fbc.lock);
1394
1395 return 0;
1396 }
1397
1398 /**
1399 * intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun
1400 * @dev_priv: i915 device instance
1401 *
1402 * Without FBC, most underruns are harmless and don't really cause too many
1403 * problems, except for an annoying message on dmesg. With FBC, underruns can
1404 * become black screens or even worse, especially when paired with bad
1405 * watermarks. So in order for us to be on the safe side, completely disable FBC
1406 * in case we ever detect a FIFO underrun on any pipe. An underrun on any pipe
1407 * already suggests that watermarks may be bad, so try to be as safe as
1408 * possible.
1409 *
1410 * This function is called from the IRQ handler.
1411 */
intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private * dev_priv)1412 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv)
1413 {
1414 struct intel_fbc *fbc = &dev_priv->fbc;
1415
1416 if (!HAS_FBC(dev_priv))
1417 return;
1418
1419 /* There's no guarantee that underrun_detected won't be set to true
1420 * right after this check and before the work is scheduled, but that's
1421 * not a problem since we'll check it again under the work function
1422 * while FBC is locked. This check here is just to prevent us from
1423 * unnecessarily scheduling the work, and it relies on the fact that we
1424 * never switch underrun_detect back to false after it's true. */
1425 if (READ_ONCE(fbc->underrun_detected))
1426 return;
1427
1428 schedule_work(&fbc->underrun_work);
1429 }
1430
1431 /*
1432 * The DDX driver changes its behavior depending on the value it reads from
1433 * i915.enable_fbc, so sanitize it by translating the default value into either
1434 * 0 or 1 in order to allow it to know what's going on.
1435 *
1436 * Notice that this is done at driver initialization and we still allow user
1437 * space to change the value during runtime without sanitizing it again. IGT
1438 * relies on being able to change i915.enable_fbc at runtime.
1439 */
intel_sanitize_fbc_option(struct drm_i915_private * dev_priv)1440 static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv)
1441 {
1442 if (dev_priv->params.enable_fbc >= 0)
1443 return !!dev_priv->params.enable_fbc;
1444
1445 if (!HAS_FBC(dev_priv))
1446 return 0;
1447
1448 if (IS_BROADWELL(dev_priv) || DISPLAY_VER(dev_priv) >= 9)
1449 return 1;
1450
1451 return 0;
1452 }
1453
need_fbc_vtd_wa(struct drm_i915_private * dev_priv)1454 static bool need_fbc_vtd_wa(struct drm_i915_private *dev_priv)
1455 {
1456 /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */
1457 if (intel_vtd_active() &&
1458 (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))) {
1459 drm_info(&dev_priv->drm,
1460 "Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled\n");
1461 return true;
1462 }
1463
1464 return false;
1465 }
1466
1467 /**
1468 * intel_fbc_init - Initialize FBC
1469 * @dev_priv: the i915 device
1470 *
1471 * This function might be called during PM init process.
1472 */
intel_fbc_init(struct drm_i915_private * dev_priv)1473 void intel_fbc_init(struct drm_i915_private *dev_priv)
1474 {
1475 struct intel_fbc *fbc = &dev_priv->fbc;
1476
1477 INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn);
1478 mutex_init(&fbc->lock);
1479 fbc->active = false;
1480
1481 if (!drm_mm_initialized(&dev_priv->mm.stolen))
1482 mkwrite_device_info(dev_priv)->display.has_fbc = false;
1483
1484 if (need_fbc_vtd_wa(dev_priv))
1485 mkwrite_device_info(dev_priv)->display.has_fbc = false;
1486
1487 dev_priv->params.enable_fbc = intel_sanitize_fbc_option(dev_priv);
1488 drm_dbg_kms(&dev_priv->drm, "Sanitized enable_fbc value: %d\n",
1489 dev_priv->params.enable_fbc);
1490
1491 if (!HAS_FBC(dev_priv)) {
1492 fbc->no_fbc_reason = "unsupported by this chipset";
1493 return;
1494 }
1495
1496 /* We still don't have any sort of hardware state readout for FBC, so
1497 * deactivate it in case the BIOS activated it to make sure software
1498 * matches the hardware state. */
1499 if (intel_fbc_hw_is_active(dev_priv))
1500 intel_fbc_hw_deactivate(dev_priv);
1501 }
1502