1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * IIO accel core driver for Freescale MMA7455L 3-axis 10-bit accelerometer
4 * Copyright 2015 Joachim Eastwood <manabian@gmail.com>
5 *
6 * UNSUPPORTED hardware features:
7 * - 8-bit mode with different scales
8 * - INT1/INT2 interrupts
9 * - Offset calibration
10 * - Events
11 */
12
13 #include <linux/delay.h>
14 #include <linux/iio/iio.h>
15 #include <linux/iio/sysfs.h>
16 #include <linux/iio/buffer.h>
17 #include <linux/iio/trigger.h>
18 #include <linux/iio/trigger_consumer.h>
19 #include <linux/iio/triggered_buffer.h>
20 #include <linux/module.h>
21 #include <linux/regmap.h>
22
23 #include "mma7455.h"
24
25 #define MMA7455_REG_XOUTL 0x00
26 #define MMA7455_REG_XOUTH 0x01
27 #define MMA7455_REG_YOUTL 0x02
28 #define MMA7455_REG_YOUTH 0x03
29 #define MMA7455_REG_ZOUTL 0x04
30 #define MMA7455_REG_ZOUTH 0x05
31 #define MMA7455_REG_STATUS 0x09
32 #define MMA7455_STATUS_DRDY BIT(0)
33 #define MMA7455_REG_WHOAMI 0x0f
34 #define MMA7455_WHOAMI_ID 0x55
35 #define MMA7455_REG_MCTL 0x16
36 #define MMA7455_MCTL_MODE_STANDBY 0x00
37 #define MMA7455_MCTL_MODE_MEASURE 0x01
38 #define MMA7455_REG_CTL1 0x18
39 #define MMA7455_CTL1_DFBW_MASK BIT(7)
40 #define MMA7455_CTL1_DFBW_125HZ BIT(7)
41 #define MMA7455_CTL1_DFBW_62_5HZ 0
42 #define MMA7455_REG_TW 0x1e
43
44 /*
45 * When MMA7455 is used in 10-bit it has a fullscale of -8g
46 * corresponding to raw value -512. The userspace interface
47 * uses m/s^2 and we declare micro units.
48 * So scale factor is given by:
49 * g * 8 * 1e6 / 512 = 153228.90625, with g = 9.80665
50 */
51 #define MMA7455_10BIT_SCALE 153229
52
53 struct mma7455_data {
54 struct regmap *regmap;
55 /*
56 * Used to reorganize data. Will ensure correct alignment of
57 * the timestamp if present
58 */
59 struct {
60 __le16 channels[3];
61 s64 ts __aligned(8);
62 } scan;
63 };
64
mma7455_drdy(struct mma7455_data * mma7455)65 static int mma7455_drdy(struct mma7455_data *mma7455)
66 {
67 struct device *dev = regmap_get_device(mma7455->regmap);
68 unsigned int reg;
69 int tries = 3;
70 int ret;
71
72 while (tries-- > 0) {
73 ret = regmap_read(mma7455->regmap, MMA7455_REG_STATUS, ®);
74 if (ret)
75 return ret;
76
77 if (reg & MMA7455_STATUS_DRDY)
78 return 0;
79
80 msleep(20);
81 }
82
83 dev_warn(dev, "data not ready\n");
84
85 return -EIO;
86 }
87
mma7455_trigger_handler(int irq,void * p)88 static irqreturn_t mma7455_trigger_handler(int irq, void *p)
89 {
90 struct iio_poll_func *pf = p;
91 struct iio_dev *indio_dev = pf->indio_dev;
92 struct mma7455_data *mma7455 = iio_priv(indio_dev);
93 int ret;
94
95 ret = mma7455_drdy(mma7455);
96 if (ret)
97 goto done;
98
99 ret = regmap_bulk_read(mma7455->regmap, MMA7455_REG_XOUTL,
100 mma7455->scan.channels,
101 sizeof(mma7455->scan.channels));
102 if (ret)
103 goto done;
104
105 iio_push_to_buffers_with_timestamp(indio_dev, &mma7455->scan,
106 iio_get_time_ns(indio_dev));
107
108 done:
109 iio_trigger_notify_done(indio_dev->trig);
110
111 return IRQ_HANDLED;
112 }
113
mma7455_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)114 static int mma7455_read_raw(struct iio_dev *indio_dev,
115 struct iio_chan_spec const *chan,
116 int *val, int *val2, long mask)
117 {
118 struct mma7455_data *mma7455 = iio_priv(indio_dev);
119 unsigned int reg;
120 __le16 data;
121 int ret;
122
123 switch (mask) {
124 case IIO_CHAN_INFO_RAW:
125 if (iio_buffer_enabled(indio_dev))
126 return -EBUSY;
127
128 ret = mma7455_drdy(mma7455);
129 if (ret)
130 return ret;
131
132 ret = regmap_bulk_read(mma7455->regmap, chan->address, &data,
133 sizeof(data));
134 if (ret)
135 return ret;
136
137 *val = sign_extend32(le16_to_cpu(data), 9);
138
139 return IIO_VAL_INT;
140
141 case IIO_CHAN_INFO_SCALE:
142 *val = 0;
143 *val2 = MMA7455_10BIT_SCALE;
144
145 return IIO_VAL_INT_PLUS_MICRO;
146
147 case IIO_CHAN_INFO_SAMP_FREQ:
148 ret = regmap_read(mma7455->regmap, MMA7455_REG_CTL1, ®);
149 if (ret)
150 return ret;
151
152 if (reg & MMA7455_CTL1_DFBW_MASK)
153 *val = 250;
154 else
155 *val = 125;
156
157 return IIO_VAL_INT;
158 }
159
160 return -EINVAL;
161 }
162
mma7455_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)163 static int mma7455_write_raw(struct iio_dev *indio_dev,
164 struct iio_chan_spec const *chan,
165 int val, int val2, long mask)
166 {
167 struct mma7455_data *mma7455 = iio_priv(indio_dev);
168 int i;
169
170 switch (mask) {
171 case IIO_CHAN_INFO_SAMP_FREQ:
172 if (val == 250 && val2 == 0)
173 i = MMA7455_CTL1_DFBW_125HZ;
174 else if (val == 125 && val2 == 0)
175 i = MMA7455_CTL1_DFBW_62_5HZ;
176 else
177 return -EINVAL;
178
179 return regmap_update_bits(mma7455->regmap, MMA7455_REG_CTL1,
180 MMA7455_CTL1_DFBW_MASK, i);
181
182 case IIO_CHAN_INFO_SCALE:
183 /* In 10-bit mode there is only one scale available */
184 if (val == 0 && val2 == MMA7455_10BIT_SCALE)
185 return 0;
186 break;
187 }
188
189 return -EINVAL;
190 }
191
192 static IIO_CONST_ATTR(sampling_frequency_available, "125 250");
193
194 static struct attribute *mma7455_attributes[] = {
195 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
196 NULL
197 };
198
199 static const struct attribute_group mma7455_group = {
200 .attrs = mma7455_attributes,
201 };
202
203 static const struct iio_info mma7455_info = {
204 .attrs = &mma7455_group,
205 .read_raw = mma7455_read_raw,
206 .write_raw = mma7455_write_raw,
207 };
208
209 #define MMA7455_CHANNEL(axis, idx) { \
210 .type = IIO_ACCEL, \
211 .modified = 1, \
212 .address = MMA7455_REG_##axis##OUTL,\
213 .channel2 = IIO_MOD_##axis, \
214 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
215 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
216 BIT(IIO_CHAN_INFO_SCALE), \
217 .scan_index = idx, \
218 .scan_type = { \
219 .sign = 's', \
220 .realbits = 10, \
221 .storagebits = 16, \
222 .endianness = IIO_LE, \
223 }, \
224 }
225
226 static const struct iio_chan_spec mma7455_channels[] = {
227 MMA7455_CHANNEL(X, 0),
228 MMA7455_CHANNEL(Y, 1),
229 MMA7455_CHANNEL(Z, 2),
230 IIO_CHAN_SOFT_TIMESTAMP(3),
231 };
232
233 static const unsigned long mma7455_scan_masks[] = {0x7, 0};
234
235 const struct regmap_config mma7455_core_regmap = {
236 .reg_bits = 8,
237 .val_bits = 8,
238 .max_register = MMA7455_REG_TW,
239 };
240 EXPORT_SYMBOL_GPL(mma7455_core_regmap);
241
mma7455_core_probe(struct device * dev,struct regmap * regmap,const char * name)242 int mma7455_core_probe(struct device *dev, struct regmap *regmap,
243 const char *name)
244 {
245 struct mma7455_data *mma7455;
246 struct iio_dev *indio_dev;
247 unsigned int reg;
248 int ret;
249
250 ret = regmap_read(regmap, MMA7455_REG_WHOAMI, ®);
251 if (ret) {
252 dev_err(dev, "unable to read reg\n");
253 return ret;
254 }
255
256 if (reg != MMA7455_WHOAMI_ID) {
257 dev_err(dev, "device id mismatch\n");
258 return -ENODEV;
259 }
260
261 indio_dev = devm_iio_device_alloc(dev, sizeof(*mma7455));
262 if (!indio_dev)
263 return -ENOMEM;
264
265 dev_set_drvdata(dev, indio_dev);
266 mma7455 = iio_priv(indio_dev);
267 mma7455->regmap = regmap;
268
269 indio_dev->info = &mma7455_info;
270 indio_dev->name = name;
271 indio_dev->modes = INDIO_DIRECT_MODE;
272 indio_dev->channels = mma7455_channels;
273 indio_dev->num_channels = ARRAY_SIZE(mma7455_channels);
274 indio_dev->available_scan_masks = mma7455_scan_masks;
275
276 regmap_write(mma7455->regmap, MMA7455_REG_MCTL,
277 MMA7455_MCTL_MODE_MEASURE);
278
279 ret = iio_triggered_buffer_setup(indio_dev, NULL,
280 mma7455_trigger_handler, NULL);
281 if (ret) {
282 dev_err(dev, "unable to setup triggered buffer\n");
283 return ret;
284 }
285
286 ret = iio_device_register(indio_dev);
287 if (ret) {
288 dev_err(dev, "unable to register device\n");
289 iio_triggered_buffer_cleanup(indio_dev);
290 return ret;
291 }
292
293 return 0;
294 }
295 EXPORT_SYMBOL_GPL(mma7455_core_probe);
296
mma7455_core_remove(struct device * dev)297 int mma7455_core_remove(struct device *dev)
298 {
299 struct iio_dev *indio_dev = dev_get_drvdata(dev);
300 struct mma7455_data *mma7455 = iio_priv(indio_dev);
301
302 iio_device_unregister(indio_dev);
303 iio_triggered_buffer_cleanup(indio_dev);
304
305 regmap_write(mma7455->regmap, MMA7455_REG_MCTL,
306 MMA7455_MCTL_MODE_STANDBY);
307
308 return 0;
309 }
310 EXPORT_SYMBOL_GPL(mma7455_core_remove);
311
312 MODULE_AUTHOR("Joachim Eastwood <manabian@gmail.com>");
313 MODULE_DESCRIPTION("Freescale MMA7455L core accelerometer driver");
314 MODULE_LICENSE("GPL v2");
315