1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /****************************************************************************
3 * Driver for Solarflare network controllers and boards
4 * Copyright 2005-2006 Fen Systems Ltd.
5 * Copyright 2005-2013 Solarflare Communications Inc.
6 */
7
8 /* Common definitions for all Efx net driver code */
9
10 #ifndef EFX_NET_DRIVER_H
11 #define EFX_NET_DRIVER_H
12
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/ethtool.h>
16 #include <linux/if_vlan.h>
17 #include <linux/timer.h>
18 #include <linux/mdio.h>
19 #include <linux/list.h>
20 #include <linux/pci.h>
21 #include <linux/device.h>
22 #include <linux/highmem.h>
23 #include <linux/workqueue.h>
24 #include <linux/mutex.h>
25 #include <linux/rwsem.h>
26 #include <linux/vmalloc.h>
27 #include <linux/mtd/mtd.h>
28 #include <net/busy_poll.h>
29 #include <net/xdp.h>
30
31 #include "enum.h"
32 #include "bitfield.h"
33 #include "filter.h"
34
35 /**************************************************************************
36 *
37 * Build definitions
38 *
39 **************************************************************************/
40
41 #ifdef DEBUG
42 #define EFX_WARN_ON_ONCE_PARANOID(x) WARN_ON_ONCE(x)
43 #define EFX_WARN_ON_PARANOID(x) WARN_ON(x)
44 #else
45 #define EFX_WARN_ON_ONCE_PARANOID(x) do {} while (0)
46 #define EFX_WARN_ON_PARANOID(x) do {} while (0)
47 #endif
48
49 /**************************************************************************
50 *
51 * Efx data structures
52 *
53 **************************************************************************/
54
55 #define EFX_MAX_CHANNELS 32U
56 #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS
57 #define EFX_EXTRA_CHANNEL_IOV 0
58 #define EFX_EXTRA_CHANNEL_PTP 1
59 #define EFX_MAX_EXTRA_CHANNELS 2U
60
61 /* Checksum generation is a per-queue option in hardware, so each
62 * queue visible to the networking core is backed by two hardware TX
63 * queues. */
64 #define EFX_MAX_TX_TC 2
65 #define EFX_MAX_CORE_TX_QUEUES (EFX_MAX_TX_TC * EFX_MAX_CHANNELS)
66 #define EFX_TXQ_TYPE_OUTER_CSUM 1 /* Outer checksum offload */
67 #define EFX_TXQ_TYPE_INNER_CSUM 2 /* Inner checksum offload */
68 #define EFX_TXQ_TYPE_HIGHPRI 4 /* High-priority (for TC) */
69 #define EFX_TXQ_TYPES 8
70 /* HIGHPRI is Siena-only, and INNER_CSUM is EF10, so no need for both */
71 #define EFX_MAX_TXQ_PER_CHANNEL 4
72 #define EFX_MAX_TX_QUEUES (EFX_MAX_TXQ_PER_CHANNEL * EFX_MAX_CHANNELS)
73
74 /* Maximum possible MTU the driver supports */
75 #define EFX_MAX_MTU (9 * 1024)
76
77 /* Minimum MTU, from RFC791 (IP) */
78 #define EFX_MIN_MTU 68
79
80 /* Maximum total header length for TSOv2 */
81 #define EFX_TSO2_MAX_HDRLEN 208
82
83 /* Size of an RX scatter buffer. Small enough to pack 2 into a 4K page,
84 * and should be a multiple of the cache line size.
85 */
86 #define EFX_RX_USR_BUF_SIZE (2048 - 256)
87
88 /* If possible, we should ensure cache line alignment at start and end
89 * of every buffer. Otherwise, we just need to ensure 4-byte
90 * alignment of the network header.
91 */
92 #if NET_IP_ALIGN == 0
93 #define EFX_RX_BUF_ALIGNMENT L1_CACHE_BYTES
94 #else
95 #define EFX_RX_BUF_ALIGNMENT 4
96 #endif
97
98 /* Non-standard XDP_PACKET_HEADROOM and tailroom to satisfy XDP_REDIRECT and
99 * still fit two standard MTU size packets into a single 4K page.
100 */
101 #define EFX_XDP_HEADROOM 128
102 #define EFX_XDP_TAILROOM SKB_DATA_ALIGN(sizeof(struct skb_shared_info))
103
104 /* Forward declare Precision Time Protocol (PTP) support structure. */
105 struct efx_ptp_data;
106 struct hwtstamp_config;
107
108 struct efx_self_tests;
109
110 /**
111 * struct efx_buffer - A general-purpose DMA buffer
112 * @addr: host base address of the buffer
113 * @dma_addr: DMA base address of the buffer
114 * @len: Buffer length, in bytes
115 *
116 * The NIC uses these buffers for its interrupt status registers and
117 * MAC stats dumps.
118 */
119 struct efx_buffer {
120 void *addr;
121 dma_addr_t dma_addr;
122 unsigned int len;
123 };
124
125 /**
126 * struct efx_special_buffer - DMA buffer entered into buffer table
127 * @buf: Standard &struct efx_buffer
128 * @index: Buffer index within controller;s buffer table
129 * @entries: Number of buffer table entries
130 *
131 * The NIC has a buffer table that maps buffers of size %EFX_BUF_SIZE.
132 * Event and descriptor rings are addressed via one or more buffer
133 * table entries (and so can be physically non-contiguous, although we
134 * currently do not take advantage of that). On Falcon and Siena we
135 * have to take care of allocating and initialising the entries
136 * ourselves. On later hardware this is managed by the firmware and
137 * @index and @entries are left as 0.
138 */
139 struct efx_special_buffer {
140 struct efx_buffer buf;
141 unsigned int index;
142 unsigned int entries;
143 };
144
145 /**
146 * struct efx_tx_buffer - buffer state for a TX descriptor
147 * @skb: When @flags & %EFX_TX_BUF_SKB, the associated socket buffer to be
148 * freed when descriptor completes
149 * @xdpf: When @flags & %EFX_TX_BUF_XDP, the XDP frame information; its @data
150 * member is the associated buffer to drop a page reference on.
151 * @option: When @flags & %EFX_TX_BUF_OPTION, an EF10-specific option
152 * descriptor.
153 * @dma_addr: DMA address of the fragment.
154 * @flags: Flags for allocation and DMA mapping type
155 * @len: Length of this fragment.
156 * This field is zero when the queue slot is empty.
157 * @unmap_len: Length of this fragment to unmap
158 * @dma_offset: Offset of @dma_addr from the address of the backing DMA mapping.
159 * Only valid if @unmap_len != 0.
160 */
161 struct efx_tx_buffer {
162 union {
163 const struct sk_buff *skb;
164 struct xdp_frame *xdpf;
165 };
166 union {
167 efx_qword_t option; /* EF10 */
168 dma_addr_t dma_addr;
169 };
170 unsigned short flags;
171 unsigned short len;
172 unsigned short unmap_len;
173 unsigned short dma_offset;
174 };
175 #define EFX_TX_BUF_CONT 1 /* not last descriptor of packet */
176 #define EFX_TX_BUF_SKB 2 /* buffer is last part of skb */
177 #define EFX_TX_BUF_MAP_SINGLE 8 /* buffer was mapped with dma_map_single() */
178 #define EFX_TX_BUF_OPTION 0x10 /* empty buffer for option descriptor */
179 #define EFX_TX_BUF_XDP 0x20 /* buffer was sent with XDP */
180 #define EFX_TX_BUF_TSO_V3 0x40 /* empty buffer for a TSO_V3 descriptor */
181
182 /**
183 * struct efx_tx_queue - An Efx TX queue
184 *
185 * This is a ring buffer of TX fragments.
186 * Since the TX completion path always executes on the same
187 * CPU and the xmit path can operate on different CPUs,
188 * performance is increased by ensuring that the completion
189 * path and the xmit path operate on different cache lines.
190 * This is particularly important if the xmit path is always
191 * executing on one CPU which is different from the completion
192 * path. There is also a cache line for members which are
193 * read but not written on the fast path.
194 *
195 * @efx: The associated Efx NIC
196 * @queue: DMA queue number
197 * @label: Label for TX completion events.
198 * Is our index within @channel->tx_queue array.
199 * @type: configuration type of this TX queue. A bitmask of %EFX_TXQ_TYPE_* flags.
200 * @tso_version: Version of TSO in use for this queue.
201 * @tso_encap: Is encapsulated TSO supported? Supported in TSOv2 on 8000 series.
202 * @channel: The associated channel
203 * @core_txq: The networking core TX queue structure
204 * @buffer: The software buffer ring
205 * @cb_page: Array of pages of copy buffers. Carved up according to
206 * %EFX_TX_CB_ORDER into %EFX_TX_CB_SIZE-sized chunks.
207 * @txd: The hardware descriptor ring
208 * @ptr_mask: The size of the ring minus 1.
209 * @piobuf: PIO buffer region for this TX queue (shared with its partner).
210 * Size of the region is efx_piobuf_size.
211 * @piobuf_offset: Buffer offset to be specified in PIO descriptors
212 * @initialised: Has hardware queue been initialised?
213 * @timestamping: Is timestamping enabled for this channel?
214 * @xdp_tx: Is this an XDP tx queue?
215 * @read_count: Current read pointer.
216 * This is the number of buffers that have been removed from both rings.
217 * @old_write_count: The value of @write_count when last checked.
218 * This is here for performance reasons. The xmit path will
219 * only get the up-to-date value of @write_count if this
220 * variable indicates that the queue is empty. This is to
221 * avoid cache-line ping-pong between the xmit path and the
222 * completion path.
223 * @merge_events: Number of TX merged completion events
224 * @completed_timestamp_major: Top part of the most recent tx timestamp.
225 * @completed_timestamp_minor: Low part of the most recent tx timestamp.
226 * @insert_count: Current insert pointer
227 * This is the number of buffers that have been added to the
228 * software ring.
229 * @write_count: Current write pointer
230 * This is the number of buffers that have been added to the
231 * hardware ring.
232 * @packet_write_count: Completable write pointer
233 * This is the write pointer of the last packet written.
234 * Normally this will equal @write_count, but as option descriptors
235 * don't produce completion events, they won't update this.
236 * Filled in iff @efx->type->option_descriptors; only used for PIO.
237 * Thus, this is written and used on EF10, and neither on farch.
238 * @old_read_count: The value of read_count when last checked.
239 * This is here for performance reasons. The xmit path will
240 * only get the up-to-date value of read_count if this
241 * variable indicates that the queue is full. This is to
242 * avoid cache-line ping-pong between the xmit path and the
243 * completion path.
244 * @tso_bursts: Number of times TSO xmit invoked by kernel
245 * @tso_long_headers: Number of packets with headers too long for standard
246 * blocks
247 * @tso_packets: Number of packets via the TSO xmit path
248 * @tso_fallbacks: Number of times TSO fallback used
249 * @pushes: Number of times the TX push feature has been used
250 * @pio_packets: Number of times the TX PIO feature has been used
251 * @xmit_pending: Are any packets waiting to be pushed to the NIC
252 * @cb_packets: Number of times the TX copybreak feature has been used
253 * @notify_count: Count of notified descriptors to the NIC
254 * @empty_read_count: If the completion path has seen the queue as empty
255 * and the transmission path has not yet checked this, the value of
256 * @read_count bitwise-added to %EFX_EMPTY_COUNT_VALID; otherwise 0.
257 */
258 struct efx_tx_queue {
259 /* Members which don't change on the fast path */
260 struct efx_nic *efx ____cacheline_aligned_in_smp;
261 unsigned int queue;
262 unsigned int label;
263 unsigned int type;
264 unsigned int tso_version;
265 bool tso_encap;
266 struct efx_channel *channel;
267 struct netdev_queue *core_txq;
268 struct efx_tx_buffer *buffer;
269 struct efx_buffer *cb_page;
270 struct efx_special_buffer txd;
271 unsigned int ptr_mask;
272 void __iomem *piobuf;
273 unsigned int piobuf_offset;
274 bool initialised;
275 bool timestamping;
276 bool xdp_tx;
277
278 /* Members used mainly on the completion path */
279 unsigned int read_count ____cacheline_aligned_in_smp;
280 unsigned int old_write_count;
281 unsigned int merge_events;
282 unsigned int bytes_compl;
283 unsigned int pkts_compl;
284 u32 completed_timestamp_major;
285 u32 completed_timestamp_minor;
286
287 /* Members used only on the xmit path */
288 unsigned int insert_count ____cacheline_aligned_in_smp;
289 unsigned int write_count;
290 unsigned int packet_write_count;
291 unsigned int old_read_count;
292 unsigned int tso_bursts;
293 unsigned int tso_long_headers;
294 unsigned int tso_packets;
295 unsigned int tso_fallbacks;
296 unsigned int pushes;
297 unsigned int pio_packets;
298 bool xmit_pending;
299 unsigned int cb_packets;
300 unsigned int notify_count;
301 /* Statistics to supplement MAC stats */
302 unsigned long tx_packets;
303
304 /* Members shared between paths and sometimes updated */
305 unsigned int empty_read_count ____cacheline_aligned_in_smp;
306 #define EFX_EMPTY_COUNT_VALID 0x80000000
307 atomic_t flush_outstanding;
308 };
309
310 #define EFX_TX_CB_ORDER 7
311 #define EFX_TX_CB_SIZE (1 << EFX_TX_CB_ORDER) - NET_IP_ALIGN
312
313 /**
314 * struct efx_rx_buffer - An Efx RX data buffer
315 * @dma_addr: DMA base address of the buffer
316 * @page: The associated page buffer.
317 * Will be %NULL if the buffer slot is currently free.
318 * @page_offset: If pending: offset in @page of DMA base address.
319 * If completed: offset in @page of Ethernet header.
320 * @len: If pending: length for DMA descriptor.
321 * If completed: received length, excluding hash prefix.
322 * @flags: Flags for buffer and packet state. These are only set on the
323 * first buffer of a scattered packet.
324 */
325 struct efx_rx_buffer {
326 dma_addr_t dma_addr;
327 struct page *page;
328 u16 page_offset;
329 u16 len;
330 u16 flags;
331 };
332 #define EFX_RX_BUF_LAST_IN_PAGE 0x0001
333 #define EFX_RX_PKT_CSUMMED 0x0002
334 #define EFX_RX_PKT_DISCARD 0x0004
335 #define EFX_RX_PKT_TCP 0x0040
336 #define EFX_RX_PKT_PREFIX_LEN 0x0080 /* length is in prefix only */
337 #define EFX_RX_PKT_CSUM_LEVEL 0x0200
338
339 /**
340 * struct efx_rx_page_state - Page-based rx buffer state
341 *
342 * Inserted at the start of every page allocated for receive buffers.
343 * Used to facilitate sharing dma mappings between recycled rx buffers
344 * and those passed up to the kernel.
345 *
346 * @dma_addr: The dma address of this page.
347 */
348 struct efx_rx_page_state {
349 dma_addr_t dma_addr;
350
351 unsigned int __pad[] ____cacheline_aligned;
352 };
353
354 /**
355 * struct efx_rx_queue - An Efx RX queue
356 * @efx: The associated Efx NIC
357 * @core_index: Index of network core RX queue. Will be >= 0 iff this
358 * is associated with a real RX queue.
359 * @buffer: The software buffer ring
360 * @rxd: The hardware descriptor ring
361 * @ptr_mask: The size of the ring minus 1.
362 * @refill_enabled: Enable refill whenever fill level is low
363 * @flush_pending: Set when a RX flush is pending. Has the same lifetime as
364 * @rxq_flush_pending.
365 * @added_count: Number of buffers added to the receive queue.
366 * @notified_count: Number of buffers given to NIC (<= @added_count).
367 * @removed_count: Number of buffers removed from the receive queue.
368 * @scatter_n: Used by NIC specific receive code.
369 * @scatter_len: Used by NIC specific receive code.
370 * @page_ring: The ring to store DMA mapped pages for reuse.
371 * @page_add: Counter to calculate the write pointer for the recycle ring.
372 * @page_remove: Counter to calculate the read pointer for the recycle ring.
373 * @page_recycle_count: The number of pages that have been recycled.
374 * @page_recycle_failed: The number of pages that couldn't be recycled because
375 * the kernel still held a reference to them.
376 * @page_recycle_full: The number of pages that were released because the
377 * recycle ring was full.
378 * @page_ptr_mask: The number of pages in the RX recycle ring minus 1.
379 * @max_fill: RX descriptor maximum fill level (<= ring size)
380 * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill
381 * (<= @max_fill)
382 * @min_fill: RX descriptor minimum non-zero fill level.
383 * This records the minimum fill level observed when a ring
384 * refill was triggered.
385 * @recycle_count: RX buffer recycle counter.
386 * @slow_fill: Timer used to defer efx_nic_generate_fill_event().
387 * @xdp_rxq_info: XDP specific RX queue information.
388 * @xdp_rxq_info_valid: Is xdp_rxq_info valid data?.
389 */
390 struct efx_rx_queue {
391 struct efx_nic *efx;
392 int core_index;
393 struct efx_rx_buffer *buffer;
394 struct efx_special_buffer rxd;
395 unsigned int ptr_mask;
396 bool refill_enabled;
397 bool flush_pending;
398
399 unsigned int added_count;
400 unsigned int notified_count;
401 unsigned int removed_count;
402 unsigned int scatter_n;
403 unsigned int scatter_len;
404 struct page **page_ring;
405 unsigned int page_add;
406 unsigned int page_remove;
407 unsigned int page_recycle_count;
408 unsigned int page_recycle_failed;
409 unsigned int page_recycle_full;
410 unsigned int page_ptr_mask;
411 unsigned int max_fill;
412 unsigned int fast_fill_trigger;
413 unsigned int min_fill;
414 unsigned int min_overfill;
415 unsigned int recycle_count;
416 struct timer_list slow_fill;
417 unsigned int slow_fill_count;
418 /* Statistics to supplement MAC stats */
419 unsigned long rx_packets;
420 struct xdp_rxq_info xdp_rxq_info;
421 bool xdp_rxq_info_valid;
422 };
423
424 enum efx_sync_events_state {
425 SYNC_EVENTS_DISABLED = 0,
426 SYNC_EVENTS_QUIESCENT,
427 SYNC_EVENTS_REQUESTED,
428 SYNC_EVENTS_VALID,
429 };
430
431 /**
432 * struct efx_channel - An Efx channel
433 *
434 * A channel comprises an event queue, at least one TX queue, at least
435 * one RX queue, and an associated tasklet for processing the event
436 * queue.
437 *
438 * @efx: Associated Efx NIC
439 * @channel: Channel instance number
440 * @type: Channel type definition
441 * @eventq_init: Event queue initialised flag
442 * @enabled: Channel enabled indicator
443 * @irq: IRQ number (MSI and MSI-X only)
444 * @irq_moderation_us: IRQ moderation value (in microseconds)
445 * @napi_dev: Net device used with NAPI
446 * @napi_str: NAPI control structure
447 * @state: state for NAPI vs busy polling
448 * @state_lock: lock protecting @state
449 * @eventq: Event queue buffer
450 * @eventq_mask: Event queue pointer mask
451 * @eventq_read_ptr: Event queue read pointer
452 * @event_test_cpu: Last CPU to handle interrupt or test event for this channel
453 * @irq_count: Number of IRQs since last adaptive moderation decision
454 * @irq_mod_score: IRQ moderation score
455 * @rfs_filter_count: number of accelerated RFS filters currently in place;
456 * equals the count of @rps_flow_id slots filled
457 * @rfs_last_expiry: value of jiffies last time some accelerated RFS filters
458 * were checked for expiry
459 * @rfs_expire_index: next accelerated RFS filter ID to check for expiry
460 * @n_rfs_succeeded: number of successful accelerated RFS filter insertions
461 * @n_rfs_failed: number of failed accelerated RFS filter insertions
462 * @filter_work: Work item for efx_filter_rfs_expire()
463 * @rps_flow_id: Flow IDs of filters allocated for accelerated RFS,
464 * indexed by filter ID
465 * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors
466 * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors
467 * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors
468 * @n_rx_mcast_mismatch: Count of unmatched multicast frames
469 * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors
470 * @n_rx_overlength: Count of RX_OVERLENGTH errors
471 * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun
472 * @n_rx_nodesc_trunc: Number of RX packets truncated and then dropped due to
473 * lack of descriptors
474 * @n_rx_merge_events: Number of RX merged completion events
475 * @n_rx_merge_packets: Number of RX packets completed by merged events
476 * @n_rx_xdp_drops: Count of RX packets intentionally dropped due to XDP
477 * @n_rx_xdp_bad_drops: Count of RX packets dropped due to XDP errors
478 * @n_rx_xdp_tx: Count of RX packets retransmitted due to XDP
479 * @n_rx_xdp_redirect: Count of RX packets redirected to a different NIC by XDP
480 * @rx_pkt_n_frags: Number of fragments in next packet to be delivered by
481 * __efx_rx_packet(), or zero if there is none
482 * @rx_pkt_index: Ring index of first buffer for next packet to be delivered
483 * by __efx_rx_packet(), if @rx_pkt_n_frags != 0
484 * @rx_list: list of SKBs from current RX, awaiting processing
485 * @rx_queue: RX queue for this channel
486 * @tx_queue: TX queues for this channel
487 * @tx_queue_by_type: pointers into @tx_queue, or %NULL, indexed by txq type
488 * @sync_events_state: Current state of sync events on this channel
489 * @sync_timestamp_major: Major part of the last ptp sync event
490 * @sync_timestamp_minor: Minor part of the last ptp sync event
491 */
492 struct efx_channel {
493 struct efx_nic *efx;
494 int channel;
495 const struct efx_channel_type *type;
496 bool eventq_init;
497 bool enabled;
498 int irq;
499 unsigned int irq_moderation_us;
500 struct net_device *napi_dev;
501 struct napi_struct napi_str;
502 #ifdef CONFIG_NET_RX_BUSY_POLL
503 unsigned long busy_poll_state;
504 #endif
505 struct efx_special_buffer eventq;
506 unsigned int eventq_mask;
507 unsigned int eventq_read_ptr;
508 int event_test_cpu;
509
510 unsigned int irq_count;
511 unsigned int irq_mod_score;
512 #ifdef CONFIG_RFS_ACCEL
513 unsigned int rfs_filter_count;
514 unsigned int rfs_last_expiry;
515 unsigned int rfs_expire_index;
516 unsigned int n_rfs_succeeded;
517 unsigned int n_rfs_failed;
518 struct delayed_work filter_work;
519 #define RPS_FLOW_ID_INVALID 0xFFFFFFFF
520 u32 *rps_flow_id;
521 #endif
522
523 unsigned int n_rx_tobe_disc;
524 unsigned int n_rx_ip_hdr_chksum_err;
525 unsigned int n_rx_tcp_udp_chksum_err;
526 unsigned int n_rx_outer_ip_hdr_chksum_err;
527 unsigned int n_rx_outer_tcp_udp_chksum_err;
528 unsigned int n_rx_inner_ip_hdr_chksum_err;
529 unsigned int n_rx_inner_tcp_udp_chksum_err;
530 unsigned int n_rx_eth_crc_err;
531 unsigned int n_rx_mcast_mismatch;
532 unsigned int n_rx_frm_trunc;
533 unsigned int n_rx_overlength;
534 unsigned int n_skbuff_leaks;
535 unsigned int n_rx_nodesc_trunc;
536 unsigned int n_rx_merge_events;
537 unsigned int n_rx_merge_packets;
538 unsigned int n_rx_xdp_drops;
539 unsigned int n_rx_xdp_bad_drops;
540 unsigned int n_rx_xdp_tx;
541 unsigned int n_rx_xdp_redirect;
542
543 unsigned int rx_pkt_n_frags;
544 unsigned int rx_pkt_index;
545
546 struct list_head *rx_list;
547
548 struct efx_rx_queue rx_queue;
549 struct efx_tx_queue tx_queue[EFX_MAX_TXQ_PER_CHANNEL];
550 struct efx_tx_queue *tx_queue_by_type[EFX_TXQ_TYPES];
551
552 enum efx_sync_events_state sync_events_state;
553 u32 sync_timestamp_major;
554 u32 sync_timestamp_minor;
555 };
556
557 /**
558 * struct efx_msi_context - Context for each MSI
559 * @efx: The associated NIC
560 * @index: Index of the channel/IRQ
561 * @name: Name of the channel/IRQ
562 *
563 * Unlike &struct efx_channel, this is never reallocated and is always
564 * safe for the IRQ handler to access.
565 */
566 struct efx_msi_context {
567 struct efx_nic *efx;
568 unsigned int index;
569 char name[IFNAMSIZ + 6];
570 };
571
572 /**
573 * struct efx_channel_type - distinguishes traffic and extra channels
574 * @handle_no_channel: Handle failure to allocate an extra channel
575 * @pre_probe: Set up extra state prior to initialisation
576 * @post_remove: Tear down extra state after finalisation, if allocated.
577 * May be called on channels that have not been probed.
578 * @get_name: Generate the channel's name (used for its IRQ handler)
579 * @copy: Copy the channel state prior to reallocation. May be %NULL if
580 * reallocation is not supported.
581 * @receive_skb: Handle an skb ready to be passed to netif_receive_skb()
582 * @want_txqs: Determine whether this channel should have TX queues
583 * created. If %NULL, TX queues are not created.
584 * @keep_eventq: Flag for whether event queue should be kept initialised
585 * while the device is stopped
586 * @want_pio: Flag for whether PIO buffers should be linked to this
587 * channel's TX queues.
588 */
589 struct efx_channel_type {
590 void (*handle_no_channel)(struct efx_nic *);
591 int (*pre_probe)(struct efx_channel *);
592 void (*post_remove)(struct efx_channel *);
593 void (*get_name)(struct efx_channel *, char *buf, size_t len);
594 struct efx_channel *(*copy)(const struct efx_channel *);
595 bool (*receive_skb)(struct efx_channel *, struct sk_buff *);
596 bool (*want_txqs)(struct efx_channel *);
597 bool keep_eventq;
598 bool want_pio;
599 };
600
601 enum efx_led_mode {
602 EFX_LED_OFF = 0,
603 EFX_LED_ON = 1,
604 EFX_LED_DEFAULT = 2
605 };
606
607 #define STRING_TABLE_LOOKUP(val, member) \
608 ((val) < member ## _max) ? member ## _names[val] : "(invalid)"
609
610 extern const char *const efx_loopback_mode_names[];
611 extern const unsigned int efx_loopback_mode_max;
612 #define LOOPBACK_MODE(efx) \
613 STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode)
614
615 extern const char *const efx_reset_type_names[];
616 extern const unsigned int efx_reset_type_max;
617 #define RESET_TYPE(type) \
618 STRING_TABLE_LOOKUP(type, efx_reset_type)
619
620 enum efx_int_mode {
621 /* Be careful if altering to correct macro below */
622 EFX_INT_MODE_MSIX = 0,
623 EFX_INT_MODE_MSI = 1,
624 EFX_INT_MODE_LEGACY = 2,
625 EFX_INT_MODE_MAX /* Insert any new items before this */
626 };
627 #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI)
628
629 enum nic_state {
630 STATE_UNINIT = 0, /* device being probed/removed or is frozen */
631 STATE_READY = 1, /* hardware ready and netdev registered */
632 STATE_DISABLED = 2, /* device disabled due to hardware errors */
633 STATE_RECOVERY = 3, /* device recovering from PCI error */
634 };
635
636 /* Forward declaration */
637 struct efx_nic;
638
639 /* Pseudo bit-mask flow control field */
640 #define EFX_FC_RX FLOW_CTRL_RX
641 #define EFX_FC_TX FLOW_CTRL_TX
642 #define EFX_FC_AUTO 4
643
644 /**
645 * struct efx_link_state - Current state of the link
646 * @up: Link is up
647 * @fd: Link is full-duplex
648 * @fc: Actual flow control flags
649 * @speed: Link speed (Mbps)
650 */
651 struct efx_link_state {
652 bool up;
653 bool fd;
654 u8 fc;
655 unsigned int speed;
656 };
657
efx_link_state_equal(const struct efx_link_state * left,const struct efx_link_state * right)658 static inline bool efx_link_state_equal(const struct efx_link_state *left,
659 const struct efx_link_state *right)
660 {
661 return left->up == right->up && left->fd == right->fd &&
662 left->fc == right->fc && left->speed == right->speed;
663 }
664
665 /**
666 * enum efx_phy_mode - PHY operating mode flags
667 * @PHY_MODE_NORMAL: on and should pass traffic
668 * @PHY_MODE_TX_DISABLED: on with TX disabled
669 * @PHY_MODE_LOW_POWER: set to low power through MDIO
670 * @PHY_MODE_OFF: switched off through external control
671 * @PHY_MODE_SPECIAL: on but will not pass traffic
672 */
673 enum efx_phy_mode {
674 PHY_MODE_NORMAL = 0,
675 PHY_MODE_TX_DISABLED = 1,
676 PHY_MODE_LOW_POWER = 2,
677 PHY_MODE_OFF = 4,
678 PHY_MODE_SPECIAL = 8,
679 };
680
efx_phy_mode_disabled(enum efx_phy_mode mode)681 static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode)
682 {
683 return !!(mode & ~PHY_MODE_TX_DISABLED);
684 }
685
686 /**
687 * struct efx_hw_stat_desc - Description of a hardware statistic
688 * @name: Name of the statistic as visible through ethtool, or %NULL if
689 * it should not be exposed
690 * @dma_width: Width in bits (0 for non-DMA statistics)
691 * @offset: Offset within stats (ignored for non-DMA statistics)
692 */
693 struct efx_hw_stat_desc {
694 const char *name;
695 u16 dma_width;
696 u16 offset;
697 };
698
699 /* Number of bits used in a multicast filter hash address */
700 #define EFX_MCAST_HASH_BITS 8
701
702 /* Number of (single-bit) entries in a multicast filter hash */
703 #define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS)
704
705 /* An Efx multicast filter hash */
706 union efx_multicast_hash {
707 u8 byte[EFX_MCAST_HASH_ENTRIES / 8];
708 efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8];
709 };
710
711 struct vfdi_status;
712
713 /* The reserved RSS context value */
714 #define EFX_MCDI_RSS_CONTEXT_INVALID 0xffffffff
715 /**
716 * struct efx_rss_context - A user-defined RSS context for filtering
717 * @list: node of linked list on which this struct is stored
718 * @context_id: the RSS_CONTEXT_ID returned by MC firmware, or
719 * %EFX_MCDI_RSS_CONTEXT_INVALID if this context is not present on the NIC.
720 * For Siena, 0 if RSS is active, else %EFX_MCDI_RSS_CONTEXT_INVALID.
721 * @user_id: the rss_context ID exposed to userspace over ethtool.
722 * @rx_hash_udp_4tuple: UDP 4-tuple hashing enabled
723 * @rx_hash_key: Toeplitz hash key for this RSS context
724 * @indir_table: Indirection table for this RSS context
725 */
726 struct efx_rss_context {
727 struct list_head list;
728 u32 context_id;
729 u32 user_id;
730 bool rx_hash_udp_4tuple;
731 u8 rx_hash_key[40];
732 u32 rx_indir_table[128];
733 };
734
735 #ifdef CONFIG_RFS_ACCEL
736 /* Order of these is important, since filter_id >= %EFX_ARFS_FILTER_ID_PENDING
737 * is used to test if filter does or will exist.
738 */
739 #define EFX_ARFS_FILTER_ID_PENDING -1
740 #define EFX_ARFS_FILTER_ID_ERROR -2
741 #define EFX_ARFS_FILTER_ID_REMOVING -3
742 /**
743 * struct efx_arfs_rule - record of an ARFS filter and its IDs
744 * @node: linkage into hash table
745 * @spec: details of the filter (used as key for hash table). Use efx->type to
746 * determine which member to use.
747 * @rxq_index: channel to which the filter will steer traffic.
748 * @arfs_id: filter ID which was returned to ARFS
749 * @filter_id: index in software filter table. May be
750 * %EFX_ARFS_FILTER_ID_PENDING if filter was not inserted yet,
751 * %EFX_ARFS_FILTER_ID_ERROR if filter insertion failed, or
752 * %EFX_ARFS_FILTER_ID_REMOVING if expiry is currently removing the filter.
753 */
754 struct efx_arfs_rule {
755 struct hlist_node node;
756 struct efx_filter_spec spec;
757 u16 rxq_index;
758 u16 arfs_id;
759 s32 filter_id;
760 };
761
762 /* Size chosen so that the table is one page (4kB) */
763 #define EFX_ARFS_HASH_TABLE_SIZE 512
764
765 /**
766 * struct efx_async_filter_insertion - Request to asynchronously insert a filter
767 * @net_dev: Reference to the netdevice
768 * @spec: The filter to insert
769 * @work: Workitem for this request
770 * @rxq_index: Identifies the channel for which this request was made
771 * @flow_id: Identifies the kernel-side flow for which this request was made
772 */
773 struct efx_async_filter_insertion {
774 struct net_device *net_dev;
775 struct efx_filter_spec spec;
776 struct work_struct work;
777 u16 rxq_index;
778 u32 flow_id;
779 };
780
781 /* Maximum number of ARFS workitems that may be in flight on an efx_nic */
782 #define EFX_RPS_MAX_IN_FLIGHT 8
783 #endif /* CONFIG_RFS_ACCEL */
784
785 /**
786 * struct efx_nic - an Efx NIC
787 * @name: Device name (net device name or bus id before net device registered)
788 * @pci_dev: The PCI device
789 * @node: List node for maintaning primary/secondary function lists
790 * @primary: &struct efx_nic instance for the primary function of this
791 * controller. May be the same structure, and may be %NULL if no
792 * primary function is bound. Serialised by rtnl_lock.
793 * @secondary_list: List of &struct efx_nic instances for the secondary PCI
794 * functions of the controller, if this is for the primary function.
795 * Serialised by rtnl_lock.
796 * @type: Controller type attributes
797 * @legacy_irq: IRQ number
798 * @workqueue: Workqueue for port reconfigures and the HW monitor.
799 * Work items do not hold and must not acquire RTNL.
800 * @workqueue_name: Name of workqueue
801 * @reset_work: Scheduled reset workitem
802 * @membase_phys: Memory BAR value as physical address
803 * @membase: Memory BAR value
804 * @vi_stride: step between per-VI registers / memory regions
805 * @interrupt_mode: Interrupt mode
806 * @timer_quantum_ns: Interrupt timer quantum, in nanoseconds
807 * @timer_max_ns: Interrupt timer maximum value, in nanoseconds
808 * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues
809 * @irqs_hooked: Channel interrupts are hooked
810 * @irq_rx_mod_step_us: Step size for IRQ moderation for RX event queues
811 * @irq_rx_moderation_us: IRQ moderation time for RX event queues
812 * @msg_enable: Log message enable flags
813 * @state: Device state number (%STATE_*). Serialised by the rtnl_lock.
814 * @reset_pending: Bitmask for pending resets
815 * @tx_queue: TX DMA queues
816 * @rx_queue: RX DMA queues
817 * @channel: Channels
818 * @msi_context: Context for each MSI
819 * @extra_channel_types: Types of extra (non-traffic) channels that
820 * should be allocated for this NIC
821 * @xdp_tx_queue_count: Number of entries in %xdp_tx_queues.
822 * @xdp_tx_queues: Array of pointers to tx queues used for XDP transmit.
823 * @rxq_entries: Size of receive queues requested by user.
824 * @txq_entries: Size of transmit queues requested by user.
825 * @txq_stop_thresh: TX queue fill level at or above which we stop it.
826 * @txq_wake_thresh: TX queue fill level at or below which we wake it.
827 * @tx_dc_base: Base qword address in SRAM of TX queue descriptor caches
828 * @rx_dc_base: Base qword address in SRAM of RX queue descriptor caches
829 * @sram_lim_qw: Qword address limit of SRAM
830 * @next_buffer_table: First available buffer table id
831 * @n_channels: Number of channels in use
832 * @n_rx_channels: Number of channels used for RX (= number of RX queues)
833 * @n_tx_channels: Number of channels used for TX
834 * @n_extra_tx_channels: Number of extra channels with TX queues
835 * @tx_queues_per_channel: number of TX queues probed on each channel
836 * @n_xdp_channels: Number of channels used for XDP TX
837 * @xdp_channel_offset: Offset of zeroth channel used for XPD TX.
838 * @xdp_tx_per_channel: Max number of TX queues on an XDP TX channel.
839 * @rx_ip_align: RX DMA address offset to have IP header aligned in
840 * in accordance with NET_IP_ALIGN
841 * @rx_dma_len: Current maximum RX DMA length
842 * @rx_buffer_order: Order (log2) of number of pages for each RX buffer
843 * @rx_buffer_truesize: Amortised allocation size of an RX buffer,
844 * for use in sk_buff::truesize
845 * @rx_prefix_size: Size of RX prefix before packet data
846 * @rx_packet_hash_offset: Offset of RX flow hash from start of packet data
847 * (valid only if @rx_prefix_size != 0; always negative)
848 * @rx_packet_len_offset: Offset of RX packet length from start of packet data
849 * (valid only for NICs that set %EFX_RX_PKT_PREFIX_LEN; always negative)
850 * @rx_packet_ts_offset: Offset of timestamp from start of packet data
851 * (valid only if channel->sync_timestamps_enabled; always negative)
852 * @rx_scatter: Scatter mode enabled for receives
853 * @rss_context: Main RSS context. Its @list member is the head of the list of
854 * RSS contexts created by user requests
855 * @rss_lock: Protects custom RSS context software state in @rss_context.list
856 * @vport_id: The function's vport ID, only relevant for PFs
857 * @int_error_count: Number of internal errors seen recently
858 * @int_error_expire: Time at which error count will be expired
859 * @must_realloc_vis: Flag: VIs have yet to be reallocated after MC reboot
860 * @irq_soft_enabled: Are IRQs soft-enabled? If not, IRQ handler will
861 * acknowledge but do nothing else.
862 * @irq_status: Interrupt status buffer
863 * @irq_zero_count: Number of legacy IRQs seen with queue flags == 0
864 * @irq_level: IRQ level/index for IRQs not triggered by an event queue
865 * @selftest_work: Work item for asynchronous self-test
866 * @mtd_list: List of MTDs attached to the NIC
867 * @nic_data: Hardware dependent state
868 * @mcdi: Management-Controller-to-Driver Interface state
869 * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode,
870 * efx_monitor() and efx_reconfigure_port()
871 * @port_enabled: Port enabled indicator.
872 * Serialises efx_stop_all(), efx_start_all(), efx_monitor() and
873 * efx_mac_work() with kernel interfaces. Safe to read under any
874 * one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must
875 * be held to modify it.
876 * @port_initialized: Port initialized?
877 * @net_dev: Operating system network device. Consider holding the rtnl lock
878 * @fixed_features: Features which cannot be turned off
879 * @num_mac_stats: Number of MAC stats reported by firmware (MAC_STATS_NUM_STATS
880 * field of %MC_CMD_GET_CAPABILITIES_V4 response, or %MC_CMD_MAC_NSTATS)
881 * @stats_buffer: DMA buffer for statistics
882 * @phy_type: PHY type
883 * @phy_data: PHY private data (including PHY-specific stats)
884 * @mdio: PHY MDIO interface
885 * @mdio_bus: PHY MDIO bus ID (only used by Siena)
886 * @phy_mode: PHY operating mode. Serialised by @mac_lock.
887 * @link_advertising: Autonegotiation advertising flags
888 * @fec_config: Forward Error Correction configuration flags. For bit positions
889 * see &enum ethtool_fec_config_bits.
890 * @link_state: Current state of the link
891 * @n_link_state_changes: Number of times the link has changed state
892 * @unicast_filter: Flag for Falcon-arch simple unicast filter.
893 * Protected by @mac_lock.
894 * @multicast_hash: Multicast hash table for Falcon-arch.
895 * Protected by @mac_lock.
896 * @wanted_fc: Wanted flow control flags
897 * @fc_disable: When non-zero flow control is disabled. Typically used to
898 * ensure that network back pressure doesn't delay dma queue flushes.
899 * Serialised by the rtnl lock.
900 * @mac_work: Work item for changing MAC promiscuity and multicast hash
901 * @loopback_mode: Loopback status
902 * @loopback_modes: Supported loopback mode bitmask
903 * @loopback_selftest: Offline self-test private state
904 * @xdp_prog: Current XDP programme for this interface
905 * @filter_sem: Filter table rw_semaphore, protects existence of @filter_state
906 * @filter_state: Architecture-dependent filter table state
907 * @rps_mutex: Protects RPS state of all channels
908 * @rps_slot_map: bitmap of in-flight entries in @rps_slot
909 * @rps_slot: array of ARFS insertion requests for efx_filter_rfs_work()
910 * @rps_hash_lock: Protects ARFS filter mapping state (@rps_hash_table and
911 * @rps_next_id).
912 * @rps_hash_table: Mapping between ARFS filters and their various IDs
913 * @rps_next_id: next arfs_id for an ARFS filter
914 * @active_queues: Count of RX and TX queues that haven't been flushed and drained.
915 * @rxq_flush_pending: Count of number of receive queues that need to be flushed.
916 * Decremented when the efx_flush_rx_queue() is called.
917 * @rxq_flush_outstanding: Count of number of RX flushes started but not yet
918 * completed (either success or failure). Not used when MCDI is used to
919 * flush receive queues.
920 * @flush_wq: wait queue used by efx_nic_flush_queues() to wait for flush completions.
921 * @vf_count: Number of VFs intended to be enabled.
922 * @vf_init_count: Number of VFs that have been fully initialised.
923 * @vi_scale: log2 number of vnics per VF.
924 * @ptp_data: PTP state data
925 * @ptp_warned: has this NIC seen and warned about unexpected PTP events?
926 * @vpd_sn: Serial number read from VPD
927 * @xdp_rxq_info_failed: Have any of the rx queues failed to initialise their
928 * xdp_rxq_info structures?
929 * @netdev_notifier: Netdevice notifier.
930 * @mem_bar: The BAR that is mapped into membase.
931 * @reg_base: Offset from the start of the bar to the function control window.
932 * @monitor_work: Hardware monitor workitem
933 * @biu_lock: BIU (bus interface unit) lock
934 * @last_irq_cpu: Last CPU to handle a possible test interrupt. This
935 * field is used by efx_test_interrupts() to verify that an
936 * interrupt has occurred.
937 * @stats_lock: Statistics update lock. Must be held when calling
938 * efx_nic_type::{update,start,stop}_stats.
939 * @n_rx_noskb_drops: Count of RX packets dropped due to failure to allocate an skb
940 *
941 * This is stored in the private area of the &struct net_device.
942 */
943 struct efx_nic {
944 /* The following fields should be written very rarely */
945
946 char name[IFNAMSIZ];
947 struct list_head node;
948 struct efx_nic *primary;
949 struct list_head secondary_list;
950 struct pci_dev *pci_dev;
951 unsigned int port_num;
952 const struct efx_nic_type *type;
953 int legacy_irq;
954 bool eeh_disabled_legacy_irq;
955 struct workqueue_struct *workqueue;
956 char workqueue_name[16];
957 struct work_struct reset_work;
958 resource_size_t membase_phys;
959 void __iomem *membase;
960
961 unsigned int vi_stride;
962
963 enum efx_int_mode interrupt_mode;
964 unsigned int timer_quantum_ns;
965 unsigned int timer_max_ns;
966 bool irq_rx_adaptive;
967 bool irqs_hooked;
968 unsigned int irq_mod_step_us;
969 unsigned int irq_rx_moderation_us;
970 u32 msg_enable;
971
972 enum nic_state state;
973 unsigned long reset_pending;
974
975 struct efx_channel *channel[EFX_MAX_CHANNELS];
976 struct efx_msi_context msi_context[EFX_MAX_CHANNELS];
977 const struct efx_channel_type *
978 extra_channel_type[EFX_MAX_EXTRA_CHANNELS];
979
980 unsigned int xdp_tx_queue_count;
981 struct efx_tx_queue **xdp_tx_queues;
982
983 unsigned rxq_entries;
984 unsigned txq_entries;
985 unsigned int txq_stop_thresh;
986 unsigned int txq_wake_thresh;
987
988 unsigned tx_dc_base;
989 unsigned rx_dc_base;
990 unsigned sram_lim_qw;
991 unsigned next_buffer_table;
992
993 unsigned int max_channels;
994 unsigned int max_vis;
995 unsigned int max_tx_channels;
996 unsigned n_channels;
997 unsigned n_rx_channels;
998 unsigned rss_spread;
999 unsigned tx_channel_offset;
1000 unsigned n_tx_channels;
1001 unsigned n_extra_tx_channels;
1002 unsigned int tx_queues_per_channel;
1003 unsigned int n_xdp_channels;
1004 unsigned int xdp_channel_offset;
1005 unsigned int xdp_tx_per_channel;
1006 unsigned int rx_ip_align;
1007 unsigned int rx_dma_len;
1008 unsigned int rx_buffer_order;
1009 unsigned int rx_buffer_truesize;
1010 unsigned int rx_page_buf_step;
1011 unsigned int rx_bufs_per_page;
1012 unsigned int rx_pages_per_batch;
1013 unsigned int rx_prefix_size;
1014 int rx_packet_hash_offset;
1015 int rx_packet_len_offset;
1016 int rx_packet_ts_offset;
1017 bool rx_scatter;
1018 struct efx_rss_context rss_context;
1019 struct mutex rss_lock;
1020 u32 vport_id;
1021
1022 unsigned int_error_count;
1023 unsigned long int_error_expire;
1024
1025 bool must_realloc_vis;
1026 bool irq_soft_enabled;
1027 struct efx_buffer irq_status;
1028 unsigned irq_zero_count;
1029 unsigned irq_level;
1030 struct delayed_work selftest_work;
1031
1032 #ifdef CONFIG_SFC_MTD
1033 struct list_head mtd_list;
1034 #endif
1035
1036 void *nic_data;
1037 struct efx_mcdi_data *mcdi;
1038
1039 struct mutex mac_lock;
1040 struct work_struct mac_work;
1041 bool port_enabled;
1042
1043 bool mc_bist_for_other_fn;
1044 bool port_initialized;
1045 struct net_device *net_dev;
1046
1047 netdev_features_t fixed_features;
1048
1049 u16 num_mac_stats;
1050 struct efx_buffer stats_buffer;
1051 u64 rx_nodesc_drops_total;
1052 u64 rx_nodesc_drops_while_down;
1053 bool rx_nodesc_drops_prev_state;
1054
1055 unsigned int phy_type;
1056 void *phy_data;
1057 struct mdio_if_info mdio;
1058 unsigned int mdio_bus;
1059 enum efx_phy_mode phy_mode;
1060
1061 __ETHTOOL_DECLARE_LINK_MODE_MASK(link_advertising);
1062 u32 fec_config;
1063 struct efx_link_state link_state;
1064 unsigned int n_link_state_changes;
1065
1066 bool unicast_filter;
1067 union efx_multicast_hash multicast_hash;
1068 u8 wanted_fc;
1069 unsigned fc_disable;
1070
1071 atomic_t rx_reset;
1072 enum efx_loopback_mode loopback_mode;
1073 u64 loopback_modes;
1074
1075 void *loopback_selftest;
1076 /* We access loopback_selftest immediately before running XDP,
1077 * so we want them next to each other.
1078 */
1079 struct bpf_prog __rcu *xdp_prog;
1080
1081 struct rw_semaphore filter_sem;
1082 void *filter_state;
1083 #ifdef CONFIG_RFS_ACCEL
1084 struct mutex rps_mutex;
1085 unsigned long rps_slot_map;
1086 struct efx_async_filter_insertion rps_slot[EFX_RPS_MAX_IN_FLIGHT];
1087 spinlock_t rps_hash_lock;
1088 struct hlist_head *rps_hash_table;
1089 u32 rps_next_id;
1090 #endif
1091
1092 atomic_t active_queues;
1093 atomic_t rxq_flush_pending;
1094 atomic_t rxq_flush_outstanding;
1095 wait_queue_head_t flush_wq;
1096
1097 #ifdef CONFIG_SFC_SRIOV
1098 unsigned vf_count;
1099 unsigned vf_init_count;
1100 unsigned vi_scale;
1101 #endif
1102
1103 struct efx_ptp_data *ptp_data;
1104 bool ptp_warned;
1105
1106 char *vpd_sn;
1107 bool xdp_rxq_info_failed;
1108
1109 struct notifier_block netdev_notifier;
1110
1111 unsigned int mem_bar;
1112 u32 reg_base;
1113
1114 /* The following fields may be written more often */
1115
1116 struct delayed_work monitor_work ____cacheline_aligned_in_smp;
1117 spinlock_t biu_lock;
1118 int last_irq_cpu;
1119 spinlock_t stats_lock;
1120 atomic_t n_rx_noskb_drops;
1121 };
1122
efx_dev_registered(struct efx_nic * efx)1123 static inline int efx_dev_registered(struct efx_nic *efx)
1124 {
1125 return efx->net_dev->reg_state == NETREG_REGISTERED;
1126 }
1127
efx_port_num(struct efx_nic * efx)1128 static inline unsigned int efx_port_num(struct efx_nic *efx)
1129 {
1130 return efx->port_num;
1131 }
1132
1133 struct efx_mtd_partition {
1134 struct list_head node;
1135 struct mtd_info mtd;
1136 const char *dev_type_name;
1137 const char *type_name;
1138 char name[IFNAMSIZ + 20];
1139 };
1140
1141 struct efx_udp_tunnel {
1142 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_INVALID 0xffff
1143 u16 type; /* TUNNEL_ENCAP_UDP_PORT_ENTRY_foo, see mcdi_pcol.h */
1144 __be16 port;
1145 };
1146
1147 /**
1148 * struct efx_nic_type - Efx device type definition
1149 * @mem_bar: Get the memory BAR
1150 * @mem_map_size: Get memory BAR mapped size
1151 * @probe: Probe the controller
1152 * @remove: Free resources allocated by probe()
1153 * @init: Initialise the controller
1154 * @dimension_resources: Dimension controller resources (buffer table,
1155 * and VIs once the available interrupt resources are clear)
1156 * @fini: Shut down the controller
1157 * @monitor: Periodic function for polling link state and hardware monitor
1158 * @map_reset_reason: Map ethtool reset reason to a reset method
1159 * @map_reset_flags: Map ethtool reset flags to a reset method, if possible
1160 * @reset: Reset the controller hardware and possibly the PHY. This will
1161 * be called while the controller is uninitialised.
1162 * @probe_port: Probe the MAC and PHY
1163 * @remove_port: Free resources allocated by probe_port()
1164 * @handle_global_event: Handle a "global" event (may be %NULL)
1165 * @fini_dmaq: Flush and finalise DMA queues (RX and TX queues)
1166 * @prepare_flush: Prepare the hardware for flushing the DMA queues
1167 * (for Falcon architecture)
1168 * @finish_flush: Clean up after flushing the DMA queues (for Falcon
1169 * architecture)
1170 * @prepare_flr: Prepare for an FLR
1171 * @finish_flr: Clean up after an FLR
1172 * @describe_stats: Describe statistics for ethtool
1173 * @update_stats: Update statistics not provided by event handling.
1174 * Either argument may be %NULL.
1175 * @update_stats_atomic: Update statistics while in atomic context, if that
1176 * is more limiting than @update_stats. Otherwise, leave %NULL and
1177 * driver core will call @update_stats.
1178 * @start_stats: Start the regular fetching of statistics
1179 * @pull_stats: Pull stats from the NIC and wait until they arrive.
1180 * @stop_stats: Stop the regular fetching of statistics
1181 * @push_irq_moderation: Apply interrupt moderation value
1182 * @reconfigure_port: Push loopback/power/txdis changes to the MAC and PHY
1183 * @prepare_enable_fc_tx: Prepare MAC to enable pause frame TX (may be %NULL)
1184 * @reconfigure_mac: Push MAC address, MTU, flow control and filter settings
1185 * to the hardware. Serialised by the mac_lock.
1186 * @check_mac_fault: Check MAC fault state. True if fault present.
1187 * @get_wol: Get WoL configuration from driver state
1188 * @set_wol: Push WoL configuration to the NIC
1189 * @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume)
1190 * @get_fec_stats: Get standard FEC statistics.
1191 * @test_chip: Test registers. May use efx_farch_test_registers(), and is
1192 * expected to reset the NIC.
1193 * @test_nvram: Test validity of NVRAM contents
1194 * @mcdi_request: Send an MCDI request with the given header and SDU.
1195 * The SDU length may be any value from 0 up to the protocol-
1196 * defined maximum, but its buffer will be padded to a multiple
1197 * of 4 bytes.
1198 * @mcdi_poll_response: Test whether an MCDI response is available.
1199 * @mcdi_read_response: Read the MCDI response PDU. The offset will
1200 * be a multiple of 4. The length may not be, but the buffer
1201 * will be padded so it is safe to round up.
1202 * @mcdi_poll_reboot: Test whether the MCDI has rebooted. If so,
1203 * return an appropriate error code for aborting any current
1204 * request; otherwise return 0.
1205 * @irq_enable_master: Enable IRQs on the NIC. Each event queue must
1206 * be separately enabled after this.
1207 * @irq_test_generate: Generate a test IRQ
1208 * @irq_disable_non_ev: Disable non-event IRQs on the NIC. Each event
1209 * queue must be separately disabled before this.
1210 * @irq_handle_msi: Handle MSI for a channel. The @dev_id argument is
1211 * a pointer to the &struct efx_msi_context for the channel.
1212 * @irq_handle_legacy: Handle legacy interrupt. The @dev_id argument
1213 * is a pointer to the &struct efx_nic.
1214 * @tx_probe: Allocate resources for TX queue (and select TXQ type)
1215 * @tx_init: Initialise TX queue on the NIC
1216 * @tx_remove: Free resources for TX queue
1217 * @tx_write: Write TX descriptors and doorbell
1218 * @tx_enqueue: Add an SKB to TX queue
1219 * @rx_push_rss_config: Write RSS hash key and indirection table to the NIC
1220 * @rx_pull_rss_config: Read RSS hash key and indirection table back from the NIC
1221 * @rx_push_rss_context_config: Write RSS hash key and indirection table for
1222 * user RSS context to the NIC
1223 * @rx_pull_rss_context_config: Read RSS hash key and indirection table for user
1224 * RSS context back from the NIC
1225 * @rx_probe: Allocate resources for RX queue
1226 * @rx_init: Initialise RX queue on the NIC
1227 * @rx_remove: Free resources for RX queue
1228 * @rx_write: Write RX descriptors and doorbell
1229 * @rx_defer_refill: Generate a refill reminder event
1230 * @rx_packet: Receive the queued RX buffer on a channel
1231 * @rx_buf_hash_valid: Determine whether the RX prefix contains a valid hash
1232 * @ev_probe: Allocate resources for event queue
1233 * @ev_init: Initialise event queue on the NIC
1234 * @ev_fini: Deinitialise event queue on the NIC
1235 * @ev_remove: Free resources for event queue
1236 * @ev_process: Process events for a queue, up to the given NAPI quota
1237 * @ev_read_ack: Acknowledge read events on a queue, rearming its IRQ
1238 * @ev_test_generate: Generate a test event
1239 * @filter_table_probe: Probe filter capabilities and set up filter software state
1240 * @filter_table_restore: Restore filters removed from hardware
1241 * @filter_table_remove: Remove filters from hardware and tear down software state
1242 * @filter_update_rx_scatter: Update filters after change to rx scatter setting
1243 * @filter_insert: add or replace a filter
1244 * @filter_remove_safe: remove a filter by ID, carefully
1245 * @filter_get_safe: retrieve a filter by ID, carefully
1246 * @filter_clear_rx: Remove all RX filters whose priority is less than or
1247 * equal to the given priority and is not %EFX_FILTER_PRI_AUTO
1248 * @filter_count_rx_used: Get the number of filters in use at a given priority
1249 * @filter_get_rx_id_limit: Get maximum value of a filter id, plus 1
1250 * @filter_get_rx_ids: Get list of RX filters at a given priority
1251 * @filter_rfs_expire_one: Consider expiring a filter inserted for RFS.
1252 * This must check whether the specified table entry is used by RFS
1253 * and that rps_may_expire_flow() returns true for it.
1254 * @mtd_probe: Probe and add MTD partitions associated with this net device,
1255 * using efx_mtd_add()
1256 * @mtd_rename: Set an MTD partition name using the net device name
1257 * @mtd_read: Read from an MTD partition
1258 * @mtd_erase: Erase part of an MTD partition
1259 * @mtd_write: Write to an MTD partition
1260 * @mtd_sync: Wait for write-back to complete on MTD partition. This
1261 * also notifies the driver that a writer has finished using this
1262 * partition.
1263 * @ptp_write_host_time: Send host time to MC as part of sync protocol
1264 * @ptp_set_ts_sync_events: Enable or disable sync events for inline RX
1265 * timestamping, possibly only temporarily for the purposes of a reset.
1266 * @ptp_set_ts_config: Set hardware timestamp configuration. The flags
1267 * and tx_type will already have been validated but this operation
1268 * must validate and update rx_filter.
1269 * @get_phys_port_id: Get the underlying physical port id.
1270 * @set_mac_address: Set the MAC address of the device
1271 * @tso_versions: Returns mask of firmware-assisted TSO versions supported.
1272 * If %NULL, then device does not support any TSO version.
1273 * @udp_tnl_push_ports: Push the list of UDP tunnel ports to the NIC if required.
1274 * @udp_tnl_has_port: Check if a port has been added as UDP tunnel
1275 * @print_additional_fwver: Dump NIC-specific additional FW version info
1276 * @sensor_event: Handle a sensor event from MCDI
1277 * @revision: Hardware architecture revision
1278 * @txd_ptr_tbl_base: TX descriptor ring base address
1279 * @rxd_ptr_tbl_base: RX descriptor ring base address
1280 * @buf_tbl_base: Buffer table base address
1281 * @evq_ptr_tbl_base: Event queue pointer table base address
1282 * @evq_rptr_tbl_base: Event queue read-pointer table base address
1283 * @max_dma_mask: Maximum possible DMA mask
1284 * @rx_prefix_size: Size of RX prefix before packet data
1285 * @rx_hash_offset: Offset of RX flow hash within prefix
1286 * @rx_ts_offset: Offset of timestamp within prefix
1287 * @rx_buffer_padding: Size of padding at end of RX packet
1288 * @can_rx_scatter: NIC is able to scatter packets to multiple buffers
1289 * @always_rx_scatter: NIC will always scatter packets to multiple buffers
1290 * @option_descriptors: NIC supports TX option descriptors
1291 * @min_interrupt_mode: Lowest capability interrupt mode supported
1292 * from &enum efx_int_mode.
1293 * @timer_period_max: Maximum period of interrupt timer (in ticks)
1294 * @offload_features: net_device feature flags for protocol offload
1295 * features implemented in hardware
1296 * @mcdi_max_ver: Maximum MCDI version supported
1297 * @hwtstamp_filters: Mask of hardware timestamp filter types supported
1298 */
1299 struct efx_nic_type {
1300 bool is_vf;
1301 unsigned int (*mem_bar)(struct efx_nic *efx);
1302 unsigned int (*mem_map_size)(struct efx_nic *efx);
1303 int (*probe)(struct efx_nic *efx);
1304 void (*remove)(struct efx_nic *efx);
1305 int (*init)(struct efx_nic *efx);
1306 int (*dimension_resources)(struct efx_nic *efx);
1307 void (*fini)(struct efx_nic *efx);
1308 void (*monitor)(struct efx_nic *efx);
1309 enum reset_type (*map_reset_reason)(enum reset_type reason);
1310 int (*map_reset_flags)(u32 *flags);
1311 int (*reset)(struct efx_nic *efx, enum reset_type method);
1312 int (*probe_port)(struct efx_nic *efx);
1313 void (*remove_port)(struct efx_nic *efx);
1314 bool (*handle_global_event)(struct efx_channel *channel, efx_qword_t *);
1315 int (*fini_dmaq)(struct efx_nic *efx);
1316 void (*prepare_flush)(struct efx_nic *efx);
1317 void (*finish_flush)(struct efx_nic *efx);
1318 void (*prepare_flr)(struct efx_nic *efx);
1319 void (*finish_flr)(struct efx_nic *efx);
1320 size_t (*describe_stats)(struct efx_nic *efx, u8 *names);
1321 size_t (*update_stats)(struct efx_nic *efx, u64 *full_stats,
1322 struct rtnl_link_stats64 *core_stats);
1323 size_t (*update_stats_atomic)(struct efx_nic *efx, u64 *full_stats,
1324 struct rtnl_link_stats64 *core_stats);
1325 void (*start_stats)(struct efx_nic *efx);
1326 void (*pull_stats)(struct efx_nic *efx);
1327 void (*stop_stats)(struct efx_nic *efx);
1328 void (*push_irq_moderation)(struct efx_channel *channel);
1329 int (*reconfigure_port)(struct efx_nic *efx);
1330 void (*prepare_enable_fc_tx)(struct efx_nic *efx);
1331 int (*reconfigure_mac)(struct efx_nic *efx, bool mtu_only);
1332 bool (*check_mac_fault)(struct efx_nic *efx);
1333 void (*get_wol)(struct efx_nic *efx, struct ethtool_wolinfo *wol);
1334 int (*set_wol)(struct efx_nic *efx, u32 type);
1335 void (*resume_wol)(struct efx_nic *efx);
1336 void (*get_fec_stats)(struct efx_nic *efx,
1337 struct ethtool_fec_stats *fec_stats);
1338 unsigned int (*check_caps)(const struct efx_nic *efx,
1339 u8 flag,
1340 u32 offset);
1341 int (*test_chip)(struct efx_nic *efx, struct efx_self_tests *tests);
1342 int (*test_nvram)(struct efx_nic *efx);
1343 void (*mcdi_request)(struct efx_nic *efx,
1344 const efx_dword_t *hdr, size_t hdr_len,
1345 const efx_dword_t *sdu, size_t sdu_len);
1346 bool (*mcdi_poll_response)(struct efx_nic *efx);
1347 void (*mcdi_read_response)(struct efx_nic *efx, efx_dword_t *pdu,
1348 size_t pdu_offset, size_t pdu_len);
1349 int (*mcdi_poll_reboot)(struct efx_nic *efx);
1350 void (*mcdi_reboot_detected)(struct efx_nic *efx);
1351 void (*irq_enable_master)(struct efx_nic *efx);
1352 int (*irq_test_generate)(struct efx_nic *efx);
1353 void (*irq_disable_non_ev)(struct efx_nic *efx);
1354 irqreturn_t (*irq_handle_msi)(int irq, void *dev_id);
1355 irqreturn_t (*irq_handle_legacy)(int irq, void *dev_id);
1356 int (*tx_probe)(struct efx_tx_queue *tx_queue);
1357 void (*tx_init)(struct efx_tx_queue *tx_queue);
1358 void (*tx_remove)(struct efx_tx_queue *tx_queue);
1359 void (*tx_write)(struct efx_tx_queue *tx_queue);
1360 netdev_tx_t (*tx_enqueue)(struct efx_tx_queue *tx_queue, struct sk_buff *skb);
1361 unsigned int (*tx_limit_len)(struct efx_tx_queue *tx_queue,
1362 dma_addr_t dma_addr, unsigned int len);
1363 int (*rx_push_rss_config)(struct efx_nic *efx, bool user,
1364 const u32 *rx_indir_table, const u8 *key);
1365 int (*rx_pull_rss_config)(struct efx_nic *efx);
1366 int (*rx_push_rss_context_config)(struct efx_nic *efx,
1367 struct efx_rss_context *ctx,
1368 const u32 *rx_indir_table,
1369 const u8 *key);
1370 int (*rx_pull_rss_context_config)(struct efx_nic *efx,
1371 struct efx_rss_context *ctx);
1372 void (*rx_restore_rss_contexts)(struct efx_nic *efx);
1373 int (*rx_probe)(struct efx_rx_queue *rx_queue);
1374 void (*rx_init)(struct efx_rx_queue *rx_queue);
1375 void (*rx_remove)(struct efx_rx_queue *rx_queue);
1376 void (*rx_write)(struct efx_rx_queue *rx_queue);
1377 void (*rx_defer_refill)(struct efx_rx_queue *rx_queue);
1378 void (*rx_packet)(struct efx_channel *channel);
1379 bool (*rx_buf_hash_valid)(const u8 *prefix);
1380 int (*ev_probe)(struct efx_channel *channel);
1381 int (*ev_init)(struct efx_channel *channel);
1382 void (*ev_fini)(struct efx_channel *channel);
1383 void (*ev_remove)(struct efx_channel *channel);
1384 int (*ev_process)(struct efx_channel *channel, int quota);
1385 void (*ev_read_ack)(struct efx_channel *channel);
1386 void (*ev_test_generate)(struct efx_channel *channel);
1387 int (*filter_table_probe)(struct efx_nic *efx);
1388 void (*filter_table_restore)(struct efx_nic *efx);
1389 void (*filter_table_remove)(struct efx_nic *efx);
1390 void (*filter_update_rx_scatter)(struct efx_nic *efx);
1391 s32 (*filter_insert)(struct efx_nic *efx,
1392 struct efx_filter_spec *spec, bool replace);
1393 int (*filter_remove_safe)(struct efx_nic *efx,
1394 enum efx_filter_priority priority,
1395 u32 filter_id);
1396 int (*filter_get_safe)(struct efx_nic *efx,
1397 enum efx_filter_priority priority,
1398 u32 filter_id, struct efx_filter_spec *);
1399 int (*filter_clear_rx)(struct efx_nic *efx,
1400 enum efx_filter_priority priority);
1401 u32 (*filter_count_rx_used)(struct efx_nic *efx,
1402 enum efx_filter_priority priority);
1403 u32 (*filter_get_rx_id_limit)(struct efx_nic *efx);
1404 s32 (*filter_get_rx_ids)(struct efx_nic *efx,
1405 enum efx_filter_priority priority,
1406 u32 *buf, u32 size);
1407 #ifdef CONFIG_RFS_ACCEL
1408 bool (*filter_rfs_expire_one)(struct efx_nic *efx, u32 flow_id,
1409 unsigned int index);
1410 #endif
1411 #ifdef CONFIG_SFC_MTD
1412 int (*mtd_probe)(struct efx_nic *efx);
1413 void (*mtd_rename)(struct efx_mtd_partition *part);
1414 int (*mtd_read)(struct mtd_info *mtd, loff_t start, size_t len,
1415 size_t *retlen, u8 *buffer);
1416 int (*mtd_erase)(struct mtd_info *mtd, loff_t start, size_t len);
1417 int (*mtd_write)(struct mtd_info *mtd, loff_t start, size_t len,
1418 size_t *retlen, const u8 *buffer);
1419 int (*mtd_sync)(struct mtd_info *mtd);
1420 #endif
1421 void (*ptp_write_host_time)(struct efx_nic *efx, u32 host_time);
1422 int (*ptp_set_ts_sync_events)(struct efx_nic *efx, bool en, bool temp);
1423 int (*ptp_set_ts_config)(struct efx_nic *efx,
1424 struct hwtstamp_config *init);
1425 int (*sriov_configure)(struct efx_nic *efx, int num_vfs);
1426 int (*vlan_rx_add_vid)(struct efx_nic *efx, __be16 proto, u16 vid);
1427 int (*vlan_rx_kill_vid)(struct efx_nic *efx, __be16 proto, u16 vid);
1428 int (*get_phys_port_id)(struct efx_nic *efx,
1429 struct netdev_phys_item_id *ppid);
1430 int (*sriov_init)(struct efx_nic *efx);
1431 void (*sriov_fini)(struct efx_nic *efx);
1432 bool (*sriov_wanted)(struct efx_nic *efx);
1433 void (*sriov_reset)(struct efx_nic *efx);
1434 void (*sriov_flr)(struct efx_nic *efx, unsigned vf_i);
1435 int (*sriov_set_vf_mac)(struct efx_nic *efx, int vf_i, u8 *mac);
1436 int (*sriov_set_vf_vlan)(struct efx_nic *efx, int vf_i, u16 vlan,
1437 u8 qos);
1438 int (*sriov_set_vf_spoofchk)(struct efx_nic *efx, int vf_i,
1439 bool spoofchk);
1440 int (*sriov_get_vf_config)(struct efx_nic *efx, int vf_i,
1441 struct ifla_vf_info *ivi);
1442 int (*sriov_set_vf_link_state)(struct efx_nic *efx, int vf_i,
1443 int link_state);
1444 int (*vswitching_probe)(struct efx_nic *efx);
1445 int (*vswitching_restore)(struct efx_nic *efx);
1446 void (*vswitching_remove)(struct efx_nic *efx);
1447 int (*get_mac_address)(struct efx_nic *efx, unsigned char *perm_addr);
1448 int (*set_mac_address)(struct efx_nic *efx);
1449 u32 (*tso_versions)(struct efx_nic *efx);
1450 int (*udp_tnl_push_ports)(struct efx_nic *efx);
1451 bool (*udp_tnl_has_port)(struct efx_nic *efx, __be16 port);
1452 size_t (*print_additional_fwver)(struct efx_nic *efx, char *buf,
1453 size_t len);
1454 void (*sensor_event)(struct efx_nic *efx, efx_qword_t *ev);
1455
1456 int revision;
1457 unsigned int txd_ptr_tbl_base;
1458 unsigned int rxd_ptr_tbl_base;
1459 unsigned int buf_tbl_base;
1460 unsigned int evq_ptr_tbl_base;
1461 unsigned int evq_rptr_tbl_base;
1462 u64 max_dma_mask;
1463 unsigned int rx_prefix_size;
1464 unsigned int rx_hash_offset;
1465 unsigned int rx_ts_offset;
1466 unsigned int rx_buffer_padding;
1467 bool can_rx_scatter;
1468 bool always_rx_scatter;
1469 bool option_descriptors;
1470 unsigned int min_interrupt_mode;
1471 unsigned int timer_period_max;
1472 netdev_features_t offload_features;
1473 int mcdi_max_ver;
1474 unsigned int max_rx_ip_filters;
1475 u32 hwtstamp_filters;
1476 unsigned int rx_hash_key_size;
1477 };
1478
1479 /**************************************************************************
1480 *
1481 * Prototypes and inline functions
1482 *
1483 *************************************************************************/
1484
1485 static inline struct efx_channel *
efx_get_channel(struct efx_nic * efx,unsigned index)1486 efx_get_channel(struct efx_nic *efx, unsigned index)
1487 {
1488 EFX_WARN_ON_ONCE_PARANOID(index >= efx->n_channels);
1489 return efx->channel[index];
1490 }
1491
1492 /* Iterate over all used channels */
1493 #define efx_for_each_channel(_channel, _efx) \
1494 for (_channel = (_efx)->channel[0]; \
1495 _channel; \
1496 _channel = (_channel->channel + 1 < (_efx)->n_channels) ? \
1497 (_efx)->channel[_channel->channel + 1] : NULL)
1498
1499 /* Iterate over all used channels in reverse */
1500 #define efx_for_each_channel_rev(_channel, _efx) \
1501 for (_channel = (_efx)->channel[(_efx)->n_channels - 1]; \
1502 _channel; \
1503 _channel = _channel->channel ? \
1504 (_efx)->channel[_channel->channel - 1] : NULL)
1505
1506 static inline struct efx_channel *
efx_get_tx_channel(struct efx_nic * efx,unsigned int index)1507 efx_get_tx_channel(struct efx_nic *efx, unsigned int index)
1508 {
1509 EFX_WARN_ON_ONCE_PARANOID(index >= efx->n_tx_channels);
1510 return efx->channel[efx->tx_channel_offset + index];
1511 }
1512
1513 static inline struct efx_channel *
efx_get_xdp_channel(struct efx_nic * efx,unsigned int index)1514 efx_get_xdp_channel(struct efx_nic *efx, unsigned int index)
1515 {
1516 EFX_WARN_ON_ONCE_PARANOID(index >= efx->n_xdp_channels);
1517 return efx->channel[efx->xdp_channel_offset + index];
1518 }
1519
efx_channel_is_xdp_tx(struct efx_channel * channel)1520 static inline bool efx_channel_is_xdp_tx(struct efx_channel *channel)
1521 {
1522 return channel->channel - channel->efx->xdp_channel_offset <
1523 channel->efx->n_xdp_channels;
1524 }
1525
efx_channel_has_tx_queues(struct efx_channel * channel)1526 static inline bool efx_channel_has_tx_queues(struct efx_channel *channel)
1527 {
1528 return true;
1529 }
1530
efx_channel_num_tx_queues(struct efx_channel * channel)1531 static inline unsigned int efx_channel_num_tx_queues(struct efx_channel *channel)
1532 {
1533 if (efx_channel_is_xdp_tx(channel))
1534 return channel->efx->xdp_tx_per_channel;
1535 return channel->efx->tx_queues_per_channel;
1536 }
1537
1538 static inline struct efx_tx_queue *
efx_channel_get_tx_queue(struct efx_channel * channel,unsigned int type)1539 efx_channel_get_tx_queue(struct efx_channel *channel, unsigned int type)
1540 {
1541 EFX_WARN_ON_ONCE_PARANOID(type >= EFX_TXQ_TYPES);
1542 return channel->tx_queue_by_type[type];
1543 }
1544
1545 static inline struct efx_tx_queue *
efx_get_tx_queue(struct efx_nic * efx,unsigned int index,unsigned int type)1546 efx_get_tx_queue(struct efx_nic *efx, unsigned int index, unsigned int type)
1547 {
1548 struct efx_channel *channel = efx_get_tx_channel(efx, index);
1549
1550 return efx_channel_get_tx_queue(channel, type);
1551 }
1552
1553 /* Iterate over all TX queues belonging to a channel */
1554 #define efx_for_each_channel_tx_queue(_tx_queue, _channel) \
1555 if (!efx_channel_has_tx_queues(_channel)) \
1556 ; \
1557 else \
1558 for (_tx_queue = (_channel)->tx_queue; \
1559 _tx_queue < (_channel)->tx_queue + \
1560 efx_channel_num_tx_queues(_channel); \
1561 _tx_queue++)
1562
efx_channel_has_rx_queue(struct efx_channel * channel)1563 static inline bool efx_channel_has_rx_queue(struct efx_channel *channel)
1564 {
1565 return channel->rx_queue.core_index >= 0;
1566 }
1567
1568 static inline struct efx_rx_queue *
efx_channel_get_rx_queue(struct efx_channel * channel)1569 efx_channel_get_rx_queue(struct efx_channel *channel)
1570 {
1571 EFX_WARN_ON_ONCE_PARANOID(!efx_channel_has_rx_queue(channel));
1572 return &channel->rx_queue;
1573 }
1574
1575 /* Iterate over all RX queues belonging to a channel */
1576 #define efx_for_each_channel_rx_queue(_rx_queue, _channel) \
1577 if (!efx_channel_has_rx_queue(_channel)) \
1578 ; \
1579 else \
1580 for (_rx_queue = &(_channel)->rx_queue; \
1581 _rx_queue; \
1582 _rx_queue = NULL)
1583
1584 static inline struct efx_channel *
efx_rx_queue_channel(struct efx_rx_queue * rx_queue)1585 efx_rx_queue_channel(struct efx_rx_queue *rx_queue)
1586 {
1587 return container_of(rx_queue, struct efx_channel, rx_queue);
1588 }
1589
efx_rx_queue_index(struct efx_rx_queue * rx_queue)1590 static inline int efx_rx_queue_index(struct efx_rx_queue *rx_queue)
1591 {
1592 return efx_rx_queue_channel(rx_queue)->channel;
1593 }
1594
1595 /* Returns a pointer to the specified receive buffer in the RX
1596 * descriptor queue.
1597 */
efx_rx_buffer(struct efx_rx_queue * rx_queue,unsigned int index)1598 static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue,
1599 unsigned int index)
1600 {
1601 return &rx_queue->buffer[index];
1602 }
1603
1604 static inline struct efx_rx_buffer *
efx_rx_buf_next(struct efx_rx_queue * rx_queue,struct efx_rx_buffer * rx_buf)1605 efx_rx_buf_next(struct efx_rx_queue *rx_queue, struct efx_rx_buffer *rx_buf)
1606 {
1607 if (unlikely(rx_buf == efx_rx_buffer(rx_queue, rx_queue->ptr_mask)))
1608 return efx_rx_buffer(rx_queue, 0);
1609 else
1610 return rx_buf + 1;
1611 }
1612
1613 /**
1614 * EFX_MAX_FRAME_LEN - calculate maximum frame length
1615 *
1616 * This calculates the maximum frame length that will be used for a
1617 * given MTU. The frame length will be equal to the MTU plus a
1618 * constant amount of header space and padding. This is the quantity
1619 * that the net driver will program into the MAC as the maximum frame
1620 * length.
1621 *
1622 * The 10G MAC requires 8-byte alignment on the frame
1623 * length, so we round up to the nearest 8.
1624 *
1625 * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an
1626 * XGMII cycle). If the frame length reaches the maximum value in the
1627 * same cycle, the XMAC can miss the IPG altogether. We work around
1628 * this by adding a further 16 bytes.
1629 */
1630 #define EFX_FRAME_PAD 16
1631 #define EFX_MAX_FRAME_LEN(mtu) \
1632 (ALIGN(((mtu) + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN + EFX_FRAME_PAD), 8))
1633
efx_xmit_with_hwtstamp(struct sk_buff * skb)1634 static inline bool efx_xmit_with_hwtstamp(struct sk_buff *skb)
1635 {
1636 return skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP;
1637 }
efx_xmit_hwtstamp_pending(struct sk_buff * skb)1638 static inline void efx_xmit_hwtstamp_pending(struct sk_buff *skb)
1639 {
1640 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1641 }
1642
1643 /* Get the max fill level of the TX queues on this channel */
1644 static inline unsigned int
efx_channel_tx_fill_level(struct efx_channel * channel)1645 efx_channel_tx_fill_level(struct efx_channel *channel)
1646 {
1647 struct efx_tx_queue *tx_queue;
1648 unsigned int fill_level = 0;
1649
1650 efx_for_each_channel_tx_queue(tx_queue, channel)
1651 fill_level = max(fill_level,
1652 tx_queue->insert_count - tx_queue->read_count);
1653
1654 return fill_level;
1655 }
1656
1657 /* Conservative approximation of efx_channel_tx_fill_level using cached value */
1658 static inline unsigned int
efx_channel_tx_old_fill_level(struct efx_channel * channel)1659 efx_channel_tx_old_fill_level(struct efx_channel *channel)
1660 {
1661 struct efx_tx_queue *tx_queue;
1662 unsigned int fill_level = 0;
1663
1664 efx_for_each_channel_tx_queue(tx_queue, channel)
1665 fill_level = max(fill_level,
1666 tx_queue->insert_count - tx_queue->old_read_count);
1667
1668 return fill_level;
1669 }
1670
1671 /* Get all supported features.
1672 * If a feature is not fixed, it is present in hw_features.
1673 * If a feature is fixed, it does not present in hw_features, but
1674 * always in features.
1675 */
efx_supported_features(const struct efx_nic * efx)1676 static inline netdev_features_t efx_supported_features(const struct efx_nic *efx)
1677 {
1678 const struct net_device *net_dev = efx->net_dev;
1679
1680 return net_dev->features | net_dev->hw_features;
1681 }
1682
1683 /* Get the current TX queue insert index. */
1684 static inline unsigned int
efx_tx_queue_get_insert_index(const struct efx_tx_queue * tx_queue)1685 efx_tx_queue_get_insert_index(const struct efx_tx_queue *tx_queue)
1686 {
1687 return tx_queue->insert_count & tx_queue->ptr_mask;
1688 }
1689
1690 /* Get a TX buffer. */
1691 static inline struct efx_tx_buffer *
__efx_tx_queue_get_insert_buffer(const struct efx_tx_queue * tx_queue)1692 __efx_tx_queue_get_insert_buffer(const struct efx_tx_queue *tx_queue)
1693 {
1694 return &tx_queue->buffer[efx_tx_queue_get_insert_index(tx_queue)];
1695 }
1696
1697 /* Get a TX buffer, checking it's not currently in use. */
1698 static inline struct efx_tx_buffer *
efx_tx_queue_get_insert_buffer(const struct efx_tx_queue * tx_queue)1699 efx_tx_queue_get_insert_buffer(const struct efx_tx_queue *tx_queue)
1700 {
1701 struct efx_tx_buffer *buffer =
1702 __efx_tx_queue_get_insert_buffer(tx_queue);
1703
1704 EFX_WARN_ON_ONCE_PARANOID(buffer->len);
1705 EFX_WARN_ON_ONCE_PARANOID(buffer->flags);
1706 EFX_WARN_ON_ONCE_PARANOID(buffer->unmap_len);
1707
1708 return buffer;
1709 }
1710
1711 #endif /* EFX_NET_DRIVER_H */
1712