1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
3 */
4
5 #include <linux/bcd.h>
6
7 #include "main.h"
8 #include "reg.h"
9 #include "fw.h"
10 #include "phy.h"
11 #include "debug.h"
12
13 struct phy_cfg_pair {
14 u32 addr;
15 u32 data;
16 };
17
18 union phy_table_tile {
19 struct rtw_phy_cond cond;
20 struct phy_cfg_pair cfg;
21 };
22
23 static const u32 db_invert_table[12][8] = {
24 {10, 13, 16, 20,
25 25, 32, 40, 50},
26 {64, 80, 101, 128,
27 160, 201, 256, 318},
28 {401, 505, 635, 800,
29 1007, 1268, 1596, 2010},
30 {316, 398, 501, 631,
31 794, 1000, 1259, 1585},
32 {1995, 2512, 3162, 3981,
33 5012, 6310, 7943, 10000},
34 {12589, 15849, 19953, 25119,
35 31623, 39811, 50119, 63098},
36 {79433, 100000, 125893, 158489,
37 199526, 251189, 316228, 398107},
38 {501187, 630957, 794328, 1000000,
39 1258925, 1584893, 1995262, 2511886},
40 {3162278, 3981072, 5011872, 6309573,
41 7943282, 1000000, 12589254, 15848932},
42 {19952623, 25118864, 31622777, 39810717,
43 50118723, 63095734, 79432823, 100000000},
44 {125892541, 158489319, 199526232, 251188643,
45 316227766, 398107171, 501187234, 630957345},
46 {794328235, 1000000000, 1258925412, 1584893192,
47 1995262315, 2511886432U, 3162277660U, 3981071706U}
48 };
49
50 u8 rtw_cck_rates[] = { DESC_RATE1M, DESC_RATE2M, DESC_RATE5_5M, DESC_RATE11M };
51 u8 rtw_ofdm_rates[] = {
52 DESC_RATE6M, DESC_RATE9M, DESC_RATE12M,
53 DESC_RATE18M, DESC_RATE24M, DESC_RATE36M,
54 DESC_RATE48M, DESC_RATE54M
55 };
56 u8 rtw_ht_1s_rates[] = {
57 DESC_RATEMCS0, DESC_RATEMCS1, DESC_RATEMCS2,
58 DESC_RATEMCS3, DESC_RATEMCS4, DESC_RATEMCS5,
59 DESC_RATEMCS6, DESC_RATEMCS7
60 };
61 u8 rtw_ht_2s_rates[] = {
62 DESC_RATEMCS8, DESC_RATEMCS9, DESC_RATEMCS10,
63 DESC_RATEMCS11, DESC_RATEMCS12, DESC_RATEMCS13,
64 DESC_RATEMCS14, DESC_RATEMCS15
65 };
66 u8 rtw_vht_1s_rates[] = {
67 DESC_RATEVHT1SS_MCS0, DESC_RATEVHT1SS_MCS1,
68 DESC_RATEVHT1SS_MCS2, DESC_RATEVHT1SS_MCS3,
69 DESC_RATEVHT1SS_MCS4, DESC_RATEVHT1SS_MCS5,
70 DESC_RATEVHT1SS_MCS6, DESC_RATEVHT1SS_MCS7,
71 DESC_RATEVHT1SS_MCS8, DESC_RATEVHT1SS_MCS9
72 };
73 u8 rtw_vht_2s_rates[] = {
74 DESC_RATEVHT2SS_MCS0, DESC_RATEVHT2SS_MCS1,
75 DESC_RATEVHT2SS_MCS2, DESC_RATEVHT2SS_MCS3,
76 DESC_RATEVHT2SS_MCS4, DESC_RATEVHT2SS_MCS5,
77 DESC_RATEVHT2SS_MCS6, DESC_RATEVHT2SS_MCS7,
78 DESC_RATEVHT2SS_MCS8, DESC_RATEVHT2SS_MCS9
79 };
80 u8 *rtw_rate_section[RTW_RATE_SECTION_MAX] = {
81 rtw_cck_rates, rtw_ofdm_rates,
82 rtw_ht_1s_rates, rtw_ht_2s_rates,
83 rtw_vht_1s_rates, rtw_vht_2s_rates
84 };
85 EXPORT_SYMBOL(rtw_rate_section);
86
87 u8 rtw_rate_size[RTW_RATE_SECTION_MAX] = {
88 ARRAY_SIZE(rtw_cck_rates),
89 ARRAY_SIZE(rtw_ofdm_rates),
90 ARRAY_SIZE(rtw_ht_1s_rates),
91 ARRAY_SIZE(rtw_ht_2s_rates),
92 ARRAY_SIZE(rtw_vht_1s_rates),
93 ARRAY_SIZE(rtw_vht_2s_rates)
94 };
95 EXPORT_SYMBOL(rtw_rate_size);
96
97 static const u8 rtw_cck_size = ARRAY_SIZE(rtw_cck_rates);
98 static const u8 rtw_ofdm_size = ARRAY_SIZE(rtw_ofdm_rates);
99 static const u8 rtw_ht_1s_size = ARRAY_SIZE(rtw_ht_1s_rates);
100 static const u8 rtw_ht_2s_size = ARRAY_SIZE(rtw_ht_2s_rates);
101 static const u8 rtw_vht_1s_size = ARRAY_SIZE(rtw_vht_1s_rates);
102 static const u8 rtw_vht_2s_size = ARRAY_SIZE(rtw_vht_2s_rates);
103
104 enum rtw_phy_band_type {
105 PHY_BAND_2G = 0,
106 PHY_BAND_5G = 1,
107 };
108
rtw_phy_cck_pd_init(struct rtw_dev * rtwdev)109 static void rtw_phy_cck_pd_init(struct rtw_dev *rtwdev)
110 {
111 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
112 u8 i, j;
113
114 for (i = 0; i <= RTW_CHANNEL_WIDTH_40; i++) {
115 for (j = 0; j < RTW_RF_PATH_MAX; j++)
116 dm_info->cck_pd_lv[i][j] = CCK_PD_LV0;
117 }
118
119 dm_info->cck_fa_avg = CCK_FA_AVG_RESET;
120 }
121
rtw_phy_cfo_init(struct rtw_dev * rtwdev)122 static void rtw_phy_cfo_init(struct rtw_dev *rtwdev)
123 {
124 struct rtw_chip_info *chip = rtwdev->chip;
125
126 if (chip->ops->cfo_init)
127 chip->ops->cfo_init(rtwdev);
128 }
129
rtw_phy_init(struct rtw_dev * rtwdev)130 void rtw_phy_init(struct rtw_dev *rtwdev)
131 {
132 struct rtw_chip_info *chip = rtwdev->chip;
133 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
134 u32 addr, mask;
135
136 dm_info->fa_history[3] = 0;
137 dm_info->fa_history[2] = 0;
138 dm_info->fa_history[1] = 0;
139 dm_info->fa_history[0] = 0;
140 dm_info->igi_bitmap = 0;
141 dm_info->igi_history[3] = 0;
142 dm_info->igi_history[2] = 0;
143 dm_info->igi_history[1] = 0;
144
145 addr = chip->dig[0].addr;
146 mask = chip->dig[0].mask;
147 dm_info->igi_history[0] = rtw_read32_mask(rtwdev, addr, mask);
148 rtw_phy_cck_pd_init(rtwdev);
149
150 dm_info->iqk.done = false;
151 rtw_phy_cfo_init(rtwdev);
152 }
153 EXPORT_SYMBOL(rtw_phy_init);
154
rtw_phy_dig_write(struct rtw_dev * rtwdev,u8 igi)155 void rtw_phy_dig_write(struct rtw_dev *rtwdev, u8 igi)
156 {
157 struct rtw_chip_info *chip = rtwdev->chip;
158 struct rtw_hal *hal = &rtwdev->hal;
159 u32 addr, mask;
160 u8 path;
161
162 if (chip->dig_cck) {
163 const struct rtw_hw_reg *dig_cck = &chip->dig_cck[0];
164 rtw_write32_mask(rtwdev, dig_cck->addr, dig_cck->mask, igi >> 1);
165 }
166
167 for (path = 0; path < hal->rf_path_num; path++) {
168 addr = chip->dig[path].addr;
169 mask = chip->dig[path].mask;
170 rtw_write32_mask(rtwdev, addr, mask, igi);
171 }
172 }
173
rtw_phy_stat_false_alarm(struct rtw_dev * rtwdev)174 static void rtw_phy_stat_false_alarm(struct rtw_dev *rtwdev)
175 {
176 struct rtw_chip_info *chip = rtwdev->chip;
177
178 chip->ops->false_alarm_statistics(rtwdev);
179 }
180
181 #define RA_FLOOR_TABLE_SIZE 7
182 #define RA_FLOOR_UP_GAP 3
183
rtw_phy_get_rssi_level(u8 old_level,u8 rssi)184 static u8 rtw_phy_get_rssi_level(u8 old_level, u8 rssi)
185 {
186 u8 table[RA_FLOOR_TABLE_SIZE] = {20, 34, 38, 42, 46, 50, 100};
187 u8 new_level = 0;
188 int i;
189
190 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++)
191 if (i >= old_level)
192 table[i] += RA_FLOOR_UP_GAP;
193
194 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) {
195 if (rssi < table[i]) {
196 new_level = i;
197 break;
198 }
199 }
200
201 return new_level;
202 }
203
204 struct rtw_phy_stat_iter_data {
205 struct rtw_dev *rtwdev;
206 u8 min_rssi;
207 };
208
rtw_phy_stat_rssi_iter(void * data,struct ieee80211_sta * sta)209 static void rtw_phy_stat_rssi_iter(void *data, struct ieee80211_sta *sta)
210 {
211 struct rtw_phy_stat_iter_data *iter_data = data;
212 struct rtw_dev *rtwdev = iter_data->rtwdev;
213 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
214 u8 rssi;
215
216 rssi = ewma_rssi_read(&si->avg_rssi);
217 si->rssi_level = rtw_phy_get_rssi_level(si->rssi_level, rssi);
218
219 rtw_fw_send_rssi_info(rtwdev, si);
220
221 iter_data->min_rssi = min_t(u8, rssi, iter_data->min_rssi);
222 }
223
rtw_phy_stat_rssi(struct rtw_dev * rtwdev)224 static void rtw_phy_stat_rssi(struct rtw_dev *rtwdev)
225 {
226 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
227 struct rtw_phy_stat_iter_data data = {};
228
229 data.rtwdev = rtwdev;
230 data.min_rssi = U8_MAX;
231 rtw_iterate_stas_atomic(rtwdev, rtw_phy_stat_rssi_iter, &data);
232
233 dm_info->pre_min_rssi = dm_info->min_rssi;
234 dm_info->min_rssi = data.min_rssi;
235 }
236
rtw_phy_stat_rate_cnt(struct rtw_dev * rtwdev)237 static void rtw_phy_stat_rate_cnt(struct rtw_dev *rtwdev)
238 {
239 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
240
241 dm_info->last_pkt_count = dm_info->cur_pkt_count;
242 memset(&dm_info->cur_pkt_count, 0, sizeof(dm_info->cur_pkt_count));
243 }
244
rtw_phy_statistics(struct rtw_dev * rtwdev)245 static void rtw_phy_statistics(struct rtw_dev *rtwdev)
246 {
247 rtw_phy_stat_rssi(rtwdev);
248 rtw_phy_stat_false_alarm(rtwdev);
249 rtw_phy_stat_rate_cnt(rtwdev);
250 }
251
252 #define DIG_PERF_FA_TH_LOW 250
253 #define DIG_PERF_FA_TH_HIGH 500
254 #define DIG_PERF_FA_TH_EXTRA_HIGH 750
255 #define DIG_PERF_MAX 0x5a
256 #define DIG_PERF_MID 0x40
257 #define DIG_CVRG_FA_TH_LOW 2000
258 #define DIG_CVRG_FA_TH_HIGH 4000
259 #define DIG_CVRG_FA_TH_EXTRA_HIGH 5000
260 #define DIG_CVRG_MAX 0x2a
261 #define DIG_CVRG_MID 0x26
262 #define DIG_CVRG_MIN 0x1c
263 #define DIG_RSSI_GAIN_OFFSET 15
264
265 static bool
rtw_phy_dig_check_damping(struct rtw_dm_info * dm_info)266 rtw_phy_dig_check_damping(struct rtw_dm_info *dm_info)
267 {
268 u16 fa_lo = DIG_PERF_FA_TH_LOW;
269 u16 fa_hi = DIG_PERF_FA_TH_HIGH;
270 u16 *fa_history;
271 u8 *igi_history;
272 u8 damping_rssi;
273 u8 min_rssi;
274 u8 diff;
275 u8 igi_bitmap;
276 bool damping = false;
277
278 min_rssi = dm_info->min_rssi;
279 if (dm_info->damping) {
280 damping_rssi = dm_info->damping_rssi;
281 diff = min_rssi > damping_rssi ? min_rssi - damping_rssi :
282 damping_rssi - min_rssi;
283 if (diff > 3 || dm_info->damping_cnt++ > 20) {
284 dm_info->damping = false;
285 return false;
286 }
287
288 return true;
289 }
290
291 igi_history = dm_info->igi_history;
292 fa_history = dm_info->fa_history;
293 igi_bitmap = dm_info->igi_bitmap & 0xf;
294 switch (igi_bitmap) {
295 case 5:
296 /* down -> up -> down -> up */
297 if (igi_history[0] > igi_history[1] &&
298 igi_history[2] > igi_history[3] &&
299 igi_history[0] - igi_history[1] >= 2 &&
300 igi_history[2] - igi_history[3] >= 2 &&
301 fa_history[0] > fa_hi && fa_history[1] < fa_lo &&
302 fa_history[2] > fa_hi && fa_history[3] < fa_lo)
303 damping = true;
304 break;
305 case 9:
306 /* up -> down -> down -> up */
307 if (igi_history[0] > igi_history[1] &&
308 igi_history[3] > igi_history[2] &&
309 igi_history[0] - igi_history[1] >= 4 &&
310 igi_history[3] - igi_history[2] >= 2 &&
311 fa_history[0] > fa_hi && fa_history[1] < fa_lo &&
312 fa_history[2] < fa_lo && fa_history[3] > fa_hi)
313 damping = true;
314 break;
315 default:
316 return false;
317 }
318
319 if (damping) {
320 dm_info->damping = true;
321 dm_info->damping_cnt = 0;
322 dm_info->damping_rssi = min_rssi;
323 }
324
325 return damping;
326 }
327
rtw_phy_dig_get_boundary(struct rtw_dev * rtwdev,struct rtw_dm_info * dm_info,u8 * upper,u8 * lower,bool linked)328 static void rtw_phy_dig_get_boundary(struct rtw_dev *rtwdev,
329 struct rtw_dm_info *dm_info,
330 u8 *upper, u8 *lower, bool linked)
331 {
332 u8 dig_max, dig_min, dig_mid;
333 u8 min_rssi;
334
335 if (linked) {
336 dig_max = DIG_PERF_MAX;
337 dig_mid = DIG_PERF_MID;
338 dig_min = rtwdev->chip->dig_min;
339 min_rssi = max_t(u8, dm_info->min_rssi, dig_min);
340 } else {
341 dig_max = DIG_CVRG_MAX;
342 dig_mid = DIG_CVRG_MID;
343 dig_min = DIG_CVRG_MIN;
344 min_rssi = dig_min;
345 }
346
347 /* DIG MAX should be bounded by minimum RSSI with offset +15 */
348 dig_max = min_t(u8, dig_max, min_rssi + DIG_RSSI_GAIN_OFFSET);
349
350 *lower = clamp_t(u8, min_rssi, dig_min, dig_mid);
351 *upper = clamp_t(u8, *lower + DIG_RSSI_GAIN_OFFSET, dig_min, dig_max);
352 }
353
rtw_phy_dig_get_threshold(struct rtw_dm_info * dm_info,u16 * fa_th,u8 * step,bool linked)354 static void rtw_phy_dig_get_threshold(struct rtw_dm_info *dm_info,
355 u16 *fa_th, u8 *step, bool linked)
356 {
357 u8 min_rssi, pre_min_rssi;
358
359 min_rssi = dm_info->min_rssi;
360 pre_min_rssi = dm_info->pre_min_rssi;
361 step[0] = 4;
362 step[1] = 3;
363 step[2] = 2;
364
365 if (linked) {
366 fa_th[0] = DIG_PERF_FA_TH_EXTRA_HIGH;
367 fa_th[1] = DIG_PERF_FA_TH_HIGH;
368 fa_th[2] = DIG_PERF_FA_TH_LOW;
369 if (pre_min_rssi > min_rssi) {
370 step[0] = 6;
371 step[1] = 4;
372 step[2] = 2;
373 }
374 } else {
375 fa_th[0] = DIG_CVRG_FA_TH_EXTRA_HIGH;
376 fa_th[1] = DIG_CVRG_FA_TH_HIGH;
377 fa_th[2] = DIG_CVRG_FA_TH_LOW;
378 }
379 }
380
rtw_phy_dig_recorder(struct rtw_dm_info * dm_info,u8 igi,u16 fa)381 static void rtw_phy_dig_recorder(struct rtw_dm_info *dm_info, u8 igi, u16 fa)
382 {
383 u8 *igi_history;
384 u16 *fa_history;
385 u8 igi_bitmap;
386 bool up;
387
388 igi_bitmap = dm_info->igi_bitmap << 1 & 0xfe;
389 igi_history = dm_info->igi_history;
390 fa_history = dm_info->fa_history;
391
392 up = igi > igi_history[0];
393 igi_bitmap |= up;
394
395 igi_history[3] = igi_history[2];
396 igi_history[2] = igi_history[1];
397 igi_history[1] = igi_history[0];
398 igi_history[0] = igi;
399
400 fa_history[3] = fa_history[2];
401 fa_history[2] = fa_history[1];
402 fa_history[1] = fa_history[0];
403 fa_history[0] = fa;
404
405 dm_info->igi_bitmap = igi_bitmap;
406 }
407
rtw_phy_dig(struct rtw_dev * rtwdev)408 static void rtw_phy_dig(struct rtw_dev *rtwdev)
409 {
410 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
411 u8 upper_bound, lower_bound;
412 u8 pre_igi, cur_igi;
413 u16 fa_th[3], fa_cnt;
414 u8 level;
415 u8 step[3];
416 bool linked;
417
418 if (test_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags))
419 return;
420
421 if (rtw_phy_dig_check_damping(dm_info))
422 return;
423
424 linked = !!rtwdev->sta_cnt;
425
426 fa_cnt = dm_info->total_fa_cnt;
427 pre_igi = dm_info->igi_history[0];
428
429 rtw_phy_dig_get_threshold(dm_info, fa_th, step, linked);
430
431 /* test the false alarm count from the highest threshold level first,
432 * and increase it by corresponding step size
433 *
434 * note that the step size is offset by -2, compensate it afterall
435 */
436 cur_igi = pre_igi;
437 for (level = 0; level < 3; level++) {
438 if (fa_cnt > fa_th[level]) {
439 cur_igi += step[level];
440 break;
441 }
442 }
443 cur_igi -= 2;
444
445 /* calculate the upper/lower bound by the minimum rssi we have among
446 * the peers connected with us, meanwhile make sure the igi value does
447 * not beyond the hardware limitation
448 */
449 rtw_phy_dig_get_boundary(rtwdev, dm_info, &upper_bound, &lower_bound,
450 linked);
451 cur_igi = clamp_t(u8, cur_igi, lower_bound, upper_bound);
452
453 /* record current igi value and false alarm statistics for further
454 * damping checks, and record the trend of igi values
455 */
456 rtw_phy_dig_recorder(dm_info, cur_igi, fa_cnt);
457
458 if (cur_igi != pre_igi)
459 rtw_phy_dig_write(rtwdev, cur_igi);
460 }
461
rtw_phy_ra_info_update_iter(void * data,struct ieee80211_sta * sta)462 static void rtw_phy_ra_info_update_iter(void *data, struct ieee80211_sta *sta)
463 {
464 struct rtw_dev *rtwdev = data;
465 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
466
467 rtw_update_sta_info(rtwdev, si);
468 }
469
rtw_phy_ra_info_update(struct rtw_dev * rtwdev)470 static void rtw_phy_ra_info_update(struct rtw_dev *rtwdev)
471 {
472 if (rtwdev->watch_dog_cnt & 0x3)
473 return;
474
475 rtw_iterate_stas_atomic(rtwdev, rtw_phy_ra_info_update_iter, rtwdev);
476 }
477
rtw_phy_get_rrsr_mask(struct rtw_dev * rtwdev,u8 rate_idx)478 static u32 rtw_phy_get_rrsr_mask(struct rtw_dev *rtwdev, u8 rate_idx)
479 {
480 u8 rate_order;
481
482 rate_order = rate_idx;
483
484 if (rate_idx >= DESC_RATEVHT4SS_MCS0)
485 rate_order -= DESC_RATEVHT4SS_MCS0;
486 else if (rate_idx >= DESC_RATEVHT3SS_MCS0)
487 rate_order -= DESC_RATEVHT3SS_MCS0;
488 else if (rate_idx >= DESC_RATEVHT2SS_MCS0)
489 rate_order -= DESC_RATEVHT2SS_MCS0;
490 else if (rate_idx >= DESC_RATEVHT1SS_MCS0)
491 rate_order -= DESC_RATEVHT1SS_MCS0;
492 else if (rate_idx >= DESC_RATEMCS24)
493 rate_order -= DESC_RATEMCS24;
494 else if (rate_idx >= DESC_RATEMCS16)
495 rate_order -= DESC_RATEMCS16;
496 else if (rate_idx >= DESC_RATEMCS8)
497 rate_order -= DESC_RATEMCS8;
498 else if (rate_idx >= DESC_RATEMCS0)
499 rate_order -= DESC_RATEMCS0;
500 else if (rate_idx >= DESC_RATE6M)
501 rate_order -= DESC_RATE6M;
502 else
503 rate_order -= DESC_RATE1M;
504
505 if (rate_idx >= DESC_RATEMCS0 || rate_order == 0)
506 rate_order++;
507
508 return GENMASK(rate_order + RRSR_RATE_ORDER_CCK_LEN - 1, 0);
509 }
510
rtw_phy_rrsr_mask_min_iter(void * data,struct ieee80211_sta * sta)511 static void rtw_phy_rrsr_mask_min_iter(void *data, struct ieee80211_sta *sta)
512 {
513 struct rtw_dev *rtwdev = (struct rtw_dev *)data;
514 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
515 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
516 u32 mask = 0;
517
518 mask = rtw_phy_get_rrsr_mask(rtwdev, si->ra_report.desc_rate);
519 if (mask < dm_info->rrsr_mask_min)
520 dm_info->rrsr_mask_min = mask;
521 }
522
rtw_phy_rrsr_update(struct rtw_dev * rtwdev)523 static void rtw_phy_rrsr_update(struct rtw_dev *rtwdev)
524 {
525 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
526
527 dm_info->rrsr_mask_min = RRSR_RATE_ORDER_MAX;
528 rtw_iterate_stas_atomic(rtwdev, rtw_phy_rrsr_mask_min_iter, rtwdev);
529 rtw_write32(rtwdev, REG_RRSR, dm_info->rrsr_val_init & dm_info->rrsr_mask_min);
530 }
531
rtw_phy_dpk_track(struct rtw_dev * rtwdev)532 static void rtw_phy_dpk_track(struct rtw_dev *rtwdev)
533 {
534 struct rtw_chip_info *chip = rtwdev->chip;
535
536 if (chip->ops->dpk_track)
537 chip->ops->dpk_track(rtwdev);
538 }
539
540 struct rtw_rx_addr_match_data {
541 struct rtw_dev *rtwdev;
542 struct ieee80211_hdr *hdr;
543 struct rtw_rx_pkt_stat *pkt_stat;
544 u8 *bssid;
545 };
546
rtw_phy_parsing_cfo_iter(void * data,u8 * mac,struct ieee80211_vif * vif)547 static void rtw_phy_parsing_cfo_iter(void *data, u8 *mac,
548 struct ieee80211_vif *vif)
549 {
550 struct rtw_rx_addr_match_data *iter_data = data;
551 struct rtw_dev *rtwdev = iter_data->rtwdev;
552 struct rtw_rx_pkt_stat *pkt_stat = iter_data->pkt_stat;
553 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
554 struct rtw_cfo_track *cfo = &dm_info->cfo_track;
555 u8 *bssid = iter_data->bssid;
556 u8 i;
557
558 if (!ether_addr_equal(vif->bss_conf.bssid, bssid))
559 return;
560
561 for (i = 0; i < rtwdev->hal.rf_path_num; i++) {
562 cfo->cfo_tail[i] += pkt_stat->cfo_tail[i];
563 cfo->cfo_cnt[i]++;
564 }
565
566 cfo->packet_count++;
567 }
568
rtw_phy_parsing_cfo(struct rtw_dev * rtwdev,struct rtw_rx_pkt_stat * pkt_stat)569 void rtw_phy_parsing_cfo(struct rtw_dev *rtwdev,
570 struct rtw_rx_pkt_stat *pkt_stat)
571 {
572 struct ieee80211_hdr *hdr = pkt_stat->hdr;
573 struct rtw_rx_addr_match_data data = {};
574
575 if (pkt_stat->crc_err || pkt_stat->icv_err || !pkt_stat->phy_status ||
576 ieee80211_is_ctl(hdr->frame_control))
577 return;
578
579 data.rtwdev = rtwdev;
580 data.hdr = hdr;
581 data.pkt_stat = pkt_stat;
582 data.bssid = get_hdr_bssid(hdr);
583
584 rtw_iterate_vifs_atomic(rtwdev, rtw_phy_parsing_cfo_iter, &data);
585 }
586 EXPORT_SYMBOL(rtw_phy_parsing_cfo);
587
rtw_phy_cfo_track(struct rtw_dev * rtwdev)588 static void rtw_phy_cfo_track(struct rtw_dev *rtwdev)
589 {
590 struct rtw_chip_info *chip = rtwdev->chip;
591
592 if (chip->ops->cfo_track)
593 chip->ops->cfo_track(rtwdev);
594 }
595
596 #define CCK_PD_FA_LV1_MIN 1000
597 #define CCK_PD_FA_LV0_MAX 500
598
rtw_phy_cck_pd_lv_unlink(struct rtw_dev * rtwdev)599 static u8 rtw_phy_cck_pd_lv_unlink(struct rtw_dev *rtwdev)
600 {
601 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
602 u32 cck_fa_avg = dm_info->cck_fa_avg;
603
604 if (cck_fa_avg > CCK_PD_FA_LV1_MIN)
605 return CCK_PD_LV1;
606
607 if (cck_fa_avg < CCK_PD_FA_LV0_MAX)
608 return CCK_PD_LV0;
609
610 return CCK_PD_LV_MAX;
611 }
612
613 #define CCK_PD_IGI_LV4_VAL 0x38
614 #define CCK_PD_IGI_LV3_VAL 0x2a
615 #define CCK_PD_IGI_LV2_VAL 0x24
616 #define CCK_PD_RSSI_LV4_VAL 32
617 #define CCK_PD_RSSI_LV3_VAL 32
618 #define CCK_PD_RSSI_LV2_VAL 24
619
rtw_phy_cck_pd_lv_link(struct rtw_dev * rtwdev)620 static u8 rtw_phy_cck_pd_lv_link(struct rtw_dev *rtwdev)
621 {
622 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
623 u8 igi = dm_info->igi_history[0];
624 u8 rssi = dm_info->min_rssi;
625 u32 cck_fa_avg = dm_info->cck_fa_avg;
626
627 if (igi > CCK_PD_IGI_LV4_VAL && rssi > CCK_PD_RSSI_LV4_VAL)
628 return CCK_PD_LV4;
629 if (igi > CCK_PD_IGI_LV3_VAL && rssi > CCK_PD_RSSI_LV3_VAL)
630 return CCK_PD_LV3;
631 if (igi > CCK_PD_IGI_LV2_VAL || rssi > CCK_PD_RSSI_LV2_VAL)
632 return CCK_PD_LV2;
633 if (cck_fa_avg > CCK_PD_FA_LV1_MIN)
634 return CCK_PD_LV1;
635 if (cck_fa_avg < CCK_PD_FA_LV0_MAX)
636 return CCK_PD_LV0;
637
638 return CCK_PD_LV_MAX;
639 }
640
rtw_phy_cck_pd_lv(struct rtw_dev * rtwdev)641 static u8 rtw_phy_cck_pd_lv(struct rtw_dev *rtwdev)
642 {
643 if (!rtw_is_assoc(rtwdev))
644 return rtw_phy_cck_pd_lv_unlink(rtwdev);
645 else
646 return rtw_phy_cck_pd_lv_link(rtwdev);
647 }
648
rtw_phy_cck_pd(struct rtw_dev * rtwdev)649 static void rtw_phy_cck_pd(struct rtw_dev *rtwdev)
650 {
651 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
652 struct rtw_chip_info *chip = rtwdev->chip;
653 u32 cck_fa = dm_info->cck_fa_cnt;
654 u8 level;
655
656 if (rtwdev->hal.current_band_type != RTW_BAND_2G)
657 return;
658
659 if (dm_info->cck_fa_avg == CCK_FA_AVG_RESET)
660 dm_info->cck_fa_avg = cck_fa;
661 else
662 dm_info->cck_fa_avg = (dm_info->cck_fa_avg * 3 + cck_fa) >> 2;
663
664 rtw_dbg(rtwdev, RTW_DBG_PHY, "IGI=0x%x, rssi_min=%d, cck_fa=%d\n",
665 dm_info->igi_history[0], dm_info->min_rssi,
666 dm_info->fa_history[0]);
667 rtw_dbg(rtwdev, RTW_DBG_PHY, "cck_fa_avg=%d, cck_pd_default=%d\n",
668 dm_info->cck_fa_avg, dm_info->cck_pd_default);
669
670 level = rtw_phy_cck_pd_lv(rtwdev);
671
672 if (level >= CCK_PD_LV_MAX)
673 return;
674
675 if (chip->ops->cck_pd_set)
676 chip->ops->cck_pd_set(rtwdev, level);
677 }
678
rtw_phy_pwr_track(struct rtw_dev * rtwdev)679 static void rtw_phy_pwr_track(struct rtw_dev *rtwdev)
680 {
681 rtwdev->chip->ops->pwr_track(rtwdev);
682 }
683
rtw_phy_ra_track(struct rtw_dev * rtwdev)684 static void rtw_phy_ra_track(struct rtw_dev *rtwdev)
685 {
686 rtw_fw_update_wl_phy_info(rtwdev);
687 rtw_phy_ra_info_update(rtwdev);
688 rtw_phy_rrsr_update(rtwdev);
689 }
690
rtw_phy_dynamic_mechanism(struct rtw_dev * rtwdev)691 void rtw_phy_dynamic_mechanism(struct rtw_dev *rtwdev)
692 {
693 /* for further calculation */
694 rtw_phy_statistics(rtwdev);
695 rtw_phy_dig(rtwdev);
696 rtw_phy_cck_pd(rtwdev);
697 rtw_phy_ra_track(rtwdev);
698 rtw_phy_cfo_track(rtwdev);
699 rtw_phy_dpk_track(rtwdev);
700 rtw_phy_pwr_track(rtwdev);
701 }
702
703 #define FRAC_BITS 3
704
rtw_phy_power_2_db(s8 power)705 static u8 rtw_phy_power_2_db(s8 power)
706 {
707 if (power <= -100 || power >= 20)
708 return 0;
709 else if (power >= 0)
710 return 100;
711 else
712 return 100 + power;
713 }
714
rtw_phy_db_2_linear(u8 power_db)715 static u64 rtw_phy_db_2_linear(u8 power_db)
716 {
717 u8 i, j;
718 u64 linear;
719
720 if (power_db > 96)
721 power_db = 96;
722 else if (power_db < 1)
723 return 1;
724
725 /* 1dB ~ 96dB */
726 i = (power_db - 1) >> 3;
727 j = (power_db - 1) - (i << 3);
728
729 linear = db_invert_table[i][j];
730 linear = i > 2 ? linear << FRAC_BITS : linear;
731
732 return linear;
733 }
734
rtw_phy_linear_2_db(u64 linear)735 static u8 rtw_phy_linear_2_db(u64 linear)
736 {
737 u8 i;
738 u8 j;
739 u32 dB;
740
741 if (linear >= db_invert_table[11][7])
742 return 96; /* maximum 96 dB */
743
744 for (i = 0; i < 12; i++) {
745 if (i <= 2 && (linear << FRAC_BITS) <= db_invert_table[i][7])
746 break;
747 else if (i > 2 && linear <= db_invert_table[i][7])
748 break;
749 }
750
751 for (j = 0; j < 8; j++) {
752 if (i <= 2 && (linear << FRAC_BITS) <= db_invert_table[i][j])
753 break;
754 else if (i > 2 && linear <= db_invert_table[i][j])
755 break;
756 }
757
758 if (j == 0 && i == 0)
759 goto end;
760
761 if (j == 0) {
762 if (i != 3) {
763 if (db_invert_table[i][0] - linear >
764 linear - db_invert_table[i - 1][7]) {
765 i = i - 1;
766 j = 7;
767 }
768 } else {
769 if (db_invert_table[3][0] - linear >
770 linear - db_invert_table[2][7]) {
771 i = 2;
772 j = 7;
773 }
774 }
775 } else {
776 if (db_invert_table[i][j] - linear >
777 linear - db_invert_table[i][j - 1]) {
778 j = j - 1;
779 }
780 }
781 end:
782 dB = (i << 3) + j + 1;
783
784 return dB;
785 }
786
rtw_phy_rf_power_2_rssi(s8 * rf_power,u8 path_num)787 u8 rtw_phy_rf_power_2_rssi(s8 *rf_power, u8 path_num)
788 {
789 s8 power;
790 u8 power_db;
791 u64 linear;
792 u64 sum = 0;
793 u8 path;
794
795 for (path = 0; path < path_num; path++) {
796 power = rf_power[path];
797 power_db = rtw_phy_power_2_db(power);
798 linear = rtw_phy_db_2_linear(power_db);
799 sum += linear;
800 }
801
802 sum = (sum + (1 << (FRAC_BITS - 1))) >> FRAC_BITS;
803 switch (path_num) {
804 case 2:
805 sum >>= 1;
806 break;
807 case 3:
808 sum = ((sum) + ((sum) << 1) + ((sum) << 3)) >> 5;
809 break;
810 case 4:
811 sum >>= 2;
812 break;
813 default:
814 break;
815 }
816
817 return rtw_phy_linear_2_db(sum);
818 }
819 EXPORT_SYMBOL(rtw_phy_rf_power_2_rssi);
820
rtw_phy_read_rf(struct rtw_dev * rtwdev,enum rtw_rf_path rf_path,u32 addr,u32 mask)821 u32 rtw_phy_read_rf(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
822 u32 addr, u32 mask)
823 {
824 struct rtw_hal *hal = &rtwdev->hal;
825 struct rtw_chip_info *chip = rtwdev->chip;
826 const u32 *base_addr = chip->rf_base_addr;
827 u32 val, direct_addr;
828
829 if (rf_path >= hal->rf_phy_num) {
830 rtw_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
831 return INV_RF_DATA;
832 }
833
834 addr &= 0xff;
835 direct_addr = base_addr[rf_path] + (addr << 2);
836 mask &= RFREG_MASK;
837
838 val = rtw_read32_mask(rtwdev, direct_addr, mask);
839
840 return val;
841 }
842 EXPORT_SYMBOL(rtw_phy_read_rf);
843
rtw_phy_read_rf_sipi(struct rtw_dev * rtwdev,enum rtw_rf_path rf_path,u32 addr,u32 mask)844 u32 rtw_phy_read_rf_sipi(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
845 u32 addr, u32 mask)
846 {
847 struct rtw_hal *hal = &rtwdev->hal;
848 struct rtw_chip_info *chip = rtwdev->chip;
849 const struct rtw_rf_sipi_addr *rf_sipi_addr;
850 const struct rtw_rf_sipi_addr *rf_sipi_addr_a;
851 u32 val32;
852 u32 en_pi;
853 u32 r_addr;
854 u32 shift;
855
856 if (rf_path >= hal->rf_phy_num) {
857 rtw_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
858 return INV_RF_DATA;
859 }
860
861 if (!chip->rf_sipi_read_addr) {
862 rtw_err(rtwdev, "rf_sipi_read_addr isn't defined\n");
863 return INV_RF_DATA;
864 }
865
866 rf_sipi_addr = &chip->rf_sipi_read_addr[rf_path];
867 rf_sipi_addr_a = &chip->rf_sipi_read_addr[RF_PATH_A];
868
869 addr &= 0xff;
870
871 val32 = rtw_read32(rtwdev, rf_sipi_addr->hssi_2);
872 val32 = (val32 & ~LSSI_READ_ADDR_MASK) | (addr << 23);
873 rtw_write32(rtwdev, rf_sipi_addr->hssi_2, val32);
874
875 /* toggle read edge of path A */
876 val32 = rtw_read32(rtwdev, rf_sipi_addr_a->hssi_2);
877 rtw_write32(rtwdev, rf_sipi_addr_a->hssi_2, val32 & ~LSSI_READ_EDGE_MASK);
878 rtw_write32(rtwdev, rf_sipi_addr_a->hssi_2, val32 | LSSI_READ_EDGE_MASK);
879
880 udelay(120);
881
882 en_pi = rtw_read32_mask(rtwdev, rf_sipi_addr->hssi_1, BIT(8));
883 r_addr = en_pi ? rf_sipi_addr->lssi_read_pi : rf_sipi_addr->lssi_read;
884
885 val32 = rtw_read32_mask(rtwdev, r_addr, LSSI_READ_DATA_MASK);
886
887 shift = __ffs(mask);
888
889 return (val32 & mask) >> shift;
890 }
891 EXPORT_SYMBOL(rtw_phy_read_rf_sipi);
892
rtw_phy_write_rf_reg_sipi(struct rtw_dev * rtwdev,enum rtw_rf_path rf_path,u32 addr,u32 mask,u32 data)893 bool rtw_phy_write_rf_reg_sipi(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
894 u32 addr, u32 mask, u32 data)
895 {
896 struct rtw_hal *hal = &rtwdev->hal;
897 struct rtw_chip_info *chip = rtwdev->chip;
898 u32 *sipi_addr = chip->rf_sipi_addr;
899 u32 data_and_addr;
900 u32 old_data = 0;
901 u32 shift;
902
903 if (rf_path >= hal->rf_phy_num) {
904 rtw_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
905 return false;
906 }
907
908 addr &= 0xff;
909 mask &= RFREG_MASK;
910
911 if (mask != RFREG_MASK) {
912 old_data = chip->ops->read_rf(rtwdev, rf_path, addr, RFREG_MASK);
913
914 if (old_data == INV_RF_DATA) {
915 rtw_err(rtwdev, "Write fail, rf is disabled\n");
916 return false;
917 }
918
919 shift = __ffs(mask);
920 data = ((old_data) & (~mask)) | (data << shift);
921 }
922
923 data_and_addr = ((addr << 20) | (data & 0x000fffff)) & 0x0fffffff;
924
925 rtw_write32(rtwdev, sipi_addr[rf_path], data_and_addr);
926
927 udelay(13);
928
929 return true;
930 }
931 EXPORT_SYMBOL(rtw_phy_write_rf_reg_sipi);
932
rtw_phy_write_rf_reg(struct rtw_dev * rtwdev,enum rtw_rf_path rf_path,u32 addr,u32 mask,u32 data)933 bool rtw_phy_write_rf_reg(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
934 u32 addr, u32 mask, u32 data)
935 {
936 struct rtw_hal *hal = &rtwdev->hal;
937 struct rtw_chip_info *chip = rtwdev->chip;
938 const u32 *base_addr = chip->rf_base_addr;
939 u32 direct_addr;
940
941 if (rf_path >= hal->rf_phy_num) {
942 rtw_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
943 return false;
944 }
945
946 addr &= 0xff;
947 direct_addr = base_addr[rf_path] + (addr << 2);
948 mask &= RFREG_MASK;
949
950 rtw_write32_mask(rtwdev, direct_addr, mask, data);
951
952 udelay(1);
953
954 return true;
955 }
956
rtw_phy_write_rf_reg_mix(struct rtw_dev * rtwdev,enum rtw_rf_path rf_path,u32 addr,u32 mask,u32 data)957 bool rtw_phy_write_rf_reg_mix(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
958 u32 addr, u32 mask, u32 data)
959 {
960 if (addr != 0x00)
961 return rtw_phy_write_rf_reg(rtwdev, rf_path, addr, mask, data);
962
963 return rtw_phy_write_rf_reg_sipi(rtwdev, rf_path, addr, mask, data);
964 }
965 EXPORT_SYMBOL(rtw_phy_write_rf_reg_mix);
966
rtw_phy_setup_phy_cond(struct rtw_dev * rtwdev,u32 pkg)967 void rtw_phy_setup_phy_cond(struct rtw_dev *rtwdev, u32 pkg)
968 {
969 struct rtw_hal *hal = &rtwdev->hal;
970 struct rtw_efuse *efuse = &rtwdev->efuse;
971 struct rtw_phy_cond cond = {0};
972
973 cond.cut = hal->cut_version ? hal->cut_version : 15;
974 cond.pkg = pkg ? pkg : 15;
975 cond.plat = 0x04;
976 cond.rfe = efuse->rfe_option;
977
978 switch (rtw_hci_type(rtwdev)) {
979 case RTW_HCI_TYPE_USB:
980 cond.intf = INTF_USB;
981 break;
982 case RTW_HCI_TYPE_SDIO:
983 cond.intf = INTF_SDIO;
984 break;
985 case RTW_HCI_TYPE_PCIE:
986 default:
987 cond.intf = INTF_PCIE;
988 break;
989 }
990
991 hal->phy_cond = cond;
992
993 rtw_dbg(rtwdev, RTW_DBG_PHY, "phy cond=0x%08x\n", *((u32 *)&hal->phy_cond));
994 }
995
check_positive(struct rtw_dev * rtwdev,struct rtw_phy_cond cond)996 static bool check_positive(struct rtw_dev *rtwdev, struct rtw_phy_cond cond)
997 {
998 struct rtw_hal *hal = &rtwdev->hal;
999 struct rtw_phy_cond drv_cond = hal->phy_cond;
1000
1001 if (cond.cut && cond.cut != drv_cond.cut)
1002 return false;
1003
1004 if (cond.pkg && cond.pkg != drv_cond.pkg)
1005 return false;
1006
1007 if (cond.intf && cond.intf != drv_cond.intf)
1008 return false;
1009
1010 if (cond.rfe != drv_cond.rfe)
1011 return false;
1012
1013 return true;
1014 }
1015
rtw_parse_tbl_phy_cond(struct rtw_dev * rtwdev,const struct rtw_table * tbl)1016 void rtw_parse_tbl_phy_cond(struct rtw_dev *rtwdev, const struct rtw_table *tbl)
1017 {
1018 const union phy_table_tile *p = tbl->data;
1019 const union phy_table_tile *end = p + tbl->size / 2;
1020 struct rtw_phy_cond pos_cond = {0};
1021 bool is_matched = true, is_skipped = false;
1022
1023 BUILD_BUG_ON(sizeof(union phy_table_tile) != sizeof(struct phy_cfg_pair));
1024
1025 for (; p < end; p++) {
1026 if (p->cond.pos) {
1027 switch (p->cond.branch) {
1028 case BRANCH_ENDIF:
1029 is_matched = true;
1030 is_skipped = false;
1031 break;
1032 case BRANCH_ELSE:
1033 is_matched = is_skipped ? false : true;
1034 break;
1035 case BRANCH_IF:
1036 case BRANCH_ELIF:
1037 default:
1038 pos_cond = p->cond;
1039 break;
1040 }
1041 } else if (p->cond.neg) {
1042 if (!is_skipped) {
1043 if (check_positive(rtwdev, pos_cond)) {
1044 is_matched = true;
1045 is_skipped = true;
1046 } else {
1047 is_matched = false;
1048 is_skipped = false;
1049 }
1050 } else {
1051 is_matched = false;
1052 }
1053 } else if (is_matched) {
1054 (*tbl->do_cfg)(rtwdev, tbl, p->cfg.addr, p->cfg.data);
1055 }
1056 }
1057 }
1058 EXPORT_SYMBOL(rtw_parse_tbl_phy_cond);
1059
1060 #define bcd_to_dec_pwr_by_rate(val, i) bcd2bin(val >> (i * 8))
1061
tbl_to_dec_pwr_by_rate(struct rtw_dev * rtwdev,u32 hex,u8 i)1062 static u8 tbl_to_dec_pwr_by_rate(struct rtw_dev *rtwdev, u32 hex, u8 i)
1063 {
1064 if (rtwdev->chip->is_pwr_by_rate_dec)
1065 return bcd_to_dec_pwr_by_rate(hex, i);
1066
1067 return (hex >> (i * 8)) & 0xFF;
1068 }
1069
1070 static void
rtw_phy_get_rate_values_of_txpwr_by_rate(struct rtw_dev * rtwdev,u32 addr,u32 mask,u32 val,u8 * rate,u8 * pwr_by_rate,u8 * rate_num)1071 rtw_phy_get_rate_values_of_txpwr_by_rate(struct rtw_dev *rtwdev,
1072 u32 addr, u32 mask, u32 val, u8 *rate,
1073 u8 *pwr_by_rate, u8 *rate_num)
1074 {
1075 int i;
1076
1077 switch (addr) {
1078 case 0xE00:
1079 case 0x830:
1080 rate[0] = DESC_RATE6M;
1081 rate[1] = DESC_RATE9M;
1082 rate[2] = DESC_RATE12M;
1083 rate[3] = DESC_RATE18M;
1084 for (i = 0; i < 4; ++i)
1085 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1086 *rate_num = 4;
1087 break;
1088 case 0xE04:
1089 case 0x834:
1090 rate[0] = DESC_RATE24M;
1091 rate[1] = DESC_RATE36M;
1092 rate[2] = DESC_RATE48M;
1093 rate[3] = DESC_RATE54M;
1094 for (i = 0; i < 4; ++i)
1095 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1096 *rate_num = 4;
1097 break;
1098 case 0xE08:
1099 rate[0] = DESC_RATE1M;
1100 pwr_by_rate[0] = bcd_to_dec_pwr_by_rate(val, 1);
1101 *rate_num = 1;
1102 break;
1103 case 0x86C:
1104 if (mask == 0xffffff00) {
1105 rate[0] = DESC_RATE2M;
1106 rate[1] = DESC_RATE5_5M;
1107 rate[2] = DESC_RATE11M;
1108 for (i = 1; i < 4; ++i)
1109 pwr_by_rate[i - 1] =
1110 tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1111 *rate_num = 3;
1112 } else if (mask == 0x000000ff) {
1113 rate[0] = DESC_RATE11M;
1114 pwr_by_rate[0] = bcd_to_dec_pwr_by_rate(val, 0);
1115 *rate_num = 1;
1116 }
1117 break;
1118 case 0xE10:
1119 case 0x83C:
1120 rate[0] = DESC_RATEMCS0;
1121 rate[1] = DESC_RATEMCS1;
1122 rate[2] = DESC_RATEMCS2;
1123 rate[3] = DESC_RATEMCS3;
1124 for (i = 0; i < 4; ++i)
1125 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1126 *rate_num = 4;
1127 break;
1128 case 0xE14:
1129 case 0x848:
1130 rate[0] = DESC_RATEMCS4;
1131 rate[1] = DESC_RATEMCS5;
1132 rate[2] = DESC_RATEMCS6;
1133 rate[3] = DESC_RATEMCS7;
1134 for (i = 0; i < 4; ++i)
1135 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1136 *rate_num = 4;
1137 break;
1138 case 0xE18:
1139 case 0x84C:
1140 rate[0] = DESC_RATEMCS8;
1141 rate[1] = DESC_RATEMCS9;
1142 rate[2] = DESC_RATEMCS10;
1143 rate[3] = DESC_RATEMCS11;
1144 for (i = 0; i < 4; ++i)
1145 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1146 *rate_num = 4;
1147 break;
1148 case 0xE1C:
1149 case 0x868:
1150 rate[0] = DESC_RATEMCS12;
1151 rate[1] = DESC_RATEMCS13;
1152 rate[2] = DESC_RATEMCS14;
1153 rate[3] = DESC_RATEMCS15;
1154 for (i = 0; i < 4; ++i)
1155 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1156 *rate_num = 4;
1157 break;
1158 case 0x838:
1159 rate[0] = DESC_RATE1M;
1160 rate[1] = DESC_RATE2M;
1161 rate[2] = DESC_RATE5_5M;
1162 for (i = 1; i < 4; ++i)
1163 pwr_by_rate[i - 1] = tbl_to_dec_pwr_by_rate(rtwdev,
1164 val, i);
1165 *rate_num = 3;
1166 break;
1167 case 0xC20:
1168 case 0xE20:
1169 case 0x1820:
1170 case 0x1A20:
1171 rate[0] = DESC_RATE1M;
1172 rate[1] = DESC_RATE2M;
1173 rate[2] = DESC_RATE5_5M;
1174 rate[3] = DESC_RATE11M;
1175 for (i = 0; i < 4; ++i)
1176 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1177 *rate_num = 4;
1178 break;
1179 case 0xC24:
1180 case 0xE24:
1181 case 0x1824:
1182 case 0x1A24:
1183 rate[0] = DESC_RATE6M;
1184 rate[1] = DESC_RATE9M;
1185 rate[2] = DESC_RATE12M;
1186 rate[3] = DESC_RATE18M;
1187 for (i = 0; i < 4; ++i)
1188 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1189 *rate_num = 4;
1190 break;
1191 case 0xC28:
1192 case 0xE28:
1193 case 0x1828:
1194 case 0x1A28:
1195 rate[0] = DESC_RATE24M;
1196 rate[1] = DESC_RATE36M;
1197 rate[2] = DESC_RATE48M;
1198 rate[3] = DESC_RATE54M;
1199 for (i = 0; i < 4; ++i)
1200 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1201 *rate_num = 4;
1202 break;
1203 case 0xC2C:
1204 case 0xE2C:
1205 case 0x182C:
1206 case 0x1A2C:
1207 rate[0] = DESC_RATEMCS0;
1208 rate[1] = DESC_RATEMCS1;
1209 rate[2] = DESC_RATEMCS2;
1210 rate[3] = DESC_RATEMCS3;
1211 for (i = 0; i < 4; ++i)
1212 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1213 *rate_num = 4;
1214 break;
1215 case 0xC30:
1216 case 0xE30:
1217 case 0x1830:
1218 case 0x1A30:
1219 rate[0] = DESC_RATEMCS4;
1220 rate[1] = DESC_RATEMCS5;
1221 rate[2] = DESC_RATEMCS6;
1222 rate[3] = DESC_RATEMCS7;
1223 for (i = 0; i < 4; ++i)
1224 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1225 *rate_num = 4;
1226 break;
1227 case 0xC34:
1228 case 0xE34:
1229 case 0x1834:
1230 case 0x1A34:
1231 rate[0] = DESC_RATEMCS8;
1232 rate[1] = DESC_RATEMCS9;
1233 rate[2] = DESC_RATEMCS10;
1234 rate[3] = DESC_RATEMCS11;
1235 for (i = 0; i < 4; ++i)
1236 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1237 *rate_num = 4;
1238 break;
1239 case 0xC38:
1240 case 0xE38:
1241 case 0x1838:
1242 case 0x1A38:
1243 rate[0] = DESC_RATEMCS12;
1244 rate[1] = DESC_RATEMCS13;
1245 rate[2] = DESC_RATEMCS14;
1246 rate[3] = DESC_RATEMCS15;
1247 for (i = 0; i < 4; ++i)
1248 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1249 *rate_num = 4;
1250 break;
1251 case 0xC3C:
1252 case 0xE3C:
1253 case 0x183C:
1254 case 0x1A3C:
1255 rate[0] = DESC_RATEVHT1SS_MCS0;
1256 rate[1] = DESC_RATEVHT1SS_MCS1;
1257 rate[2] = DESC_RATEVHT1SS_MCS2;
1258 rate[3] = DESC_RATEVHT1SS_MCS3;
1259 for (i = 0; i < 4; ++i)
1260 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1261 *rate_num = 4;
1262 break;
1263 case 0xC40:
1264 case 0xE40:
1265 case 0x1840:
1266 case 0x1A40:
1267 rate[0] = DESC_RATEVHT1SS_MCS4;
1268 rate[1] = DESC_RATEVHT1SS_MCS5;
1269 rate[2] = DESC_RATEVHT1SS_MCS6;
1270 rate[3] = DESC_RATEVHT1SS_MCS7;
1271 for (i = 0; i < 4; ++i)
1272 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1273 *rate_num = 4;
1274 break;
1275 case 0xC44:
1276 case 0xE44:
1277 case 0x1844:
1278 case 0x1A44:
1279 rate[0] = DESC_RATEVHT1SS_MCS8;
1280 rate[1] = DESC_RATEVHT1SS_MCS9;
1281 rate[2] = DESC_RATEVHT2SS_MCS0;
1282 rate[3] = DESC_RATEVHT2SS_MCS1;
1283 for (i = 0; i < 4; ++i)
1284 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1285 *rate_num = 4;
1286 break;
1287 case 0xC48:
1288 case 0xE48:
1289 case 0x1848:
1290 case 0x1A48:
1291 rate[0] = DESC_RATEVHT2SS_MCS2;
1292 rate[1] = DESC_RATEVHT2SS_MCS3;
1293 rate[2] = DESC_RATEVHT2SS_MCS4;
1294 rate[3] = DESC_RATEVHT2SS_MCS5;
1295 for (i = 0; i < 4; ++i)
1296 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1297 *rate_num = 4;
1298 break;
1299 case 0xC4C:
1300 case 0xE4C:
1301 case 0x184C:
1302 case 0x1A4C:
1303 rate[0] = DESC_RATEVHT2SS_MCS6;
1304 rate[1] = DESC_RATEVHT2SS_MCS7;
1305 rate[2] = DESC_RATEVHT2SS_MCS8;
1306 rate[3] = DESC_RATEVHT2SS_MCS9;
1307 for (i = 0; i < 4; ++i)
1308 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1309 *rate_num = 4;
1310 break;
1311 case 0xCD8:
1312 case 0xED8:
1313 case 0x18D8:
1314 case 0x1AD8:
1315 rate[0] = DESC_RATEMCS16;
1316 rate[1] = DESC_RATEMCS17;
1317 rate[2] = DESC_RATEMCS18;
1318 rate[3] = DESC_RATEMCS19;
1319 for (i = 0; i < 4; ++i)
1320 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1321 *rate_num = 4;
1322 break;
1323 case 0xCDC:
1324 case 0xEDC:
1325 case 0x18DC:
1326 case 0x1ADC:
1327 rate[0] = DESC_RATEMCS20;
1328 rate[1] = DESC_RATEMCS21;
1329 rate[2] = DESC_RATEMCS22;
1330 rate[3] = DESC_RATEMCS23;
1331 for (i = 0; i < 4; ++i)
1332 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1333 *rate_num = 4;
1334 break;
1335 case 0xCE0:
1336 case 0xEE0:
1337 case 0x18E0:
1338 case 0x1AE0:
1339 rate[0] = DESC_RATEVHT3SS_MCS0;
1340 rate[1] = DESC_RATEVHT3SS_MCS1;
1341 rate[2] = DESC_RATEVHT3SS_MCS2;
1342 rate[3] = DESC_RATEVHT3SS_MCS3;
1343 for (i = 0; i < 4; ++i)
1344 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1345 *rate_num = 4;
1346 break;
1347 case 0xCE4:
1348 case 0xEE4:
1349 case 0x18E4:
1350 case 0x1AE4:
1351 rate[0] = DESC_RATEVHT3SS_MCS4;
1352 rate[1] = DESC_RATEVHT3SS_MCS5;
1353 rate[2] = DESC_RATEVHT3SS_MCS6;
1354 rate[3] = DESC_RATEVHT3SS_MCS7;
1355 for (i = 0; i < 4; ++i)
1356 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1357 *rate_num = 4;
1358 break;
1359 case 0xCE8:
1360 case 0xEE8:
1361 case 0x18E8:
1362 case 0x1AE8:
1363 rate[0] = DESC_RATEVHT3SS_MCS8;
1364 rate[1] = DESC_RATEVHT3SS_MCS9;
1365 for (i = 0; i < 2; ++i)
1366 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1367 *rate_num = 2;
1368 break;
1369 default:
1370 rtw_warn(rtwdev, "invalid tx power index addr 0x%08x\n", addr);
1371 break;
1372 }
1373 }
1374
rtw_phy_store_tx_power_by_rate(struct rtw_dev * rtwdev,u32 band,u32 rfpath,u32 txnum,u32 regaddr,u32 bitmask,u32 data)1375 static void rtw_phy_store_tx_power_by_rate(struct rtw_dev *rtwdev,
1376 u32 band, u32 rfpath, u32 txnum,
1377 u32 regaddr, u32 bitmask, u32 data)
1378 {
1379 struct rtw_hal *hal = &rtwdev->hal;
1380 u8 rate_num = 0;
1381 u8 rate;
1382 u8 rates[RTW_RF_PATH_MAX] = {0};
1383 s8 offset;
1384 s8 pwr_by_rate[RTW_RF_PATH_MAX] = {0};
1385 int i;
1386
1387 rtw_phy_get_rate_values_of_txpwr_by_rate(rtwdev, regaddr, bitmask, data,
1388 rates, pwr_by_rate, &rate_num);
1389
1390 if (WARN_ON(rfpath >= RTW_RF_PATH_MAX ||
1391 (band != PHY_BAND_2G && band != PHY_BAND_5G) ||
1392 rate_num > RTW_RF_PATH_MAX))
1393 return;
1394
1395 for (i = 0; i < rate_num; i++) {
1396 offset = pwr_by_rate[i];
1397 rate = rates[i];
1398 if (band == PHY_BAND_2G)
1399 hal->tx_pwr_by_rate_offset_2g[rfpath][rate] = offset;
1400 else if (band == PHY_BAND_5G)
1401 hal->tx_pwr_by_rate_offset_5g[rfpath][rate] = offset;
1402 else
1403 continue;
1404 }
1405 }
1406
rtw_parse_tbl_bb_pg(struct rtw_dev * rtwdev,const struct rtw_table * tbl)1407 void rtw_parse_tbl_bb_pg(struct rtw_dev *rtwdev, const struct rtw_table *tbl)
1408 {
1409 const struct rtw_phy_pg_cfg_pair *p = tbl->data;
1410 const struct rtw_phy_pg_cfg_pair *end = p + tbl->size;
1411
1412 for (; p < end; p++) {
1413 if (p->addr == 0xfe || p->addr == 0xffe) {
1414 msleep(50);
1415 continue;
1416 }
1417 rtw_phy_store_tx_power_by_rate(rtwdev, p->band, p->rf_path,
1418 p->tx_num, p->addr, p->bitmask,
1419 p->data);
1420 }
1421 }
1422 EXPORT_SYMBOL(rtw_parse_tbl_bb_pg);
1423
1424 static const u8 rtw_channel_idx_5g[RTW_MAX_CHANNEL_NUM_5G] = {
1425 36, 38, 40, 42, 44, 46, 48, /* Band 1 */
1426 52, 54, 56, 58, 60, 62, 64, /* Band 2 */
1427 100, 102, 104, 106, 108, 110, 112, /* Band 3 */
1428 116, 118, 120, 122, 124, 126, 128, /* Band 3 */
1429 132, 134, 136, 138, 140, 142, 144, /* Band 3 */
1430 149, 151, 153, 155, 157, 159, 161, /* Band 4 */
1431 165, 167, 169, 171, 173, 175, 177}; /* Band 4 */
1432
rtw_channel_to_idx(u8 band,u8 channel)1433 static int rtw_channel_to_idx(u8 band, u8 channel)
1434 {
1435 int ch_idx;
1436 u8 n_channel;
1437
1438 if (band == PHY_BAND_2G) {
1439 ch_idx = channel - 1;
1440 n_channel = RTW_MAX_CHANNEL_NUM_2G;
1441 } else if (band == PHY_BAND_5G) {
1442 n_channel = RTW_MAX_CHANNEL_NUM_5G;
1443 for (ch_idx = 0; ch_idx < n_channel; ch_idx++)
1444 if (rtw_channel_idx_5g[ch_idx] == channel)
1445 break;
1446 } else {
1447 return -1;
1448 }
1449
1450 if (ch_idx >= n_channel)
1451 return -1;
1452
1453 return ch_idx;
1454 }
1455
rtw_phy_set_tx_power_limit(struct rtw_dev * rtwdev,u8 regd,u8 band,u8 bw,u8 rs,u8 ch,s8 pwr_limit)1456 static void rtw_phy_set_tx_power_limit(struct rtw_dev *rtwdev, u8 regd, u8 band,
1457 u8 bw, u8 rs, u8 ch, s8 pwr_limit)
1458 {
1459 struct rtw_hal *hal = &rtwdev->hal;
1460 u8 max_power_index = rtwdev->chip->max_power_index;
1461 s8 ww;
1462 int ch_idx;
1463
1464 pwr_limit = clamp_t(s8, pwr_limit,
1465 -max_power_index, max_power_index);
1466 ch_idx = rtw_channel_to_idx(band, ch);
1467
1468 if (regd >= RTW_REGD_MAX || bw >= RTW_CHANNEL_WIDTH_MAX ||
1469 rs >= RTW_RATE_SECTION_MAX || ch_idx < 0) {
1470 WARN(1,
1471 "wrong txpwr_lmt regd=%u, band=%u bw=%u, rs=%u, ch_idx=%u, pwr_limit=%d\n",
1472 regd, band, bw, rs, ch_idx, pwr_limit);
1473 return;
1474 }
1475
1476 if (band == PHY_BAND_2G) {
1477 hal->tx_pwr_limit_2g[regd][bw][rs][ch_idx] = pwr_limit;
1478 ww = hal->tx_pwr_limit_2g[RTW_REGD_WW][bw][rs][ch_idx];
1479 ww = min_t(s8, ww, pwr_limit);
1480 hal->tx_pwr_limit_2g[RTW_REGD_WW][bw][rs][ch_idx] = ww;
1481 } else if (band == PHY_BAND_5G) {
1482 hal->tx_pwr_limit_5g[regd][bw][rs][ch_idx] = pwr_limit;
1483 ww = hal->tx_pwr_limit_5g[RTW_REGD_WW][bw][rs][ch_idx];
1484 ww = min_t(s8, ww, pwr_limit);
1485 hal->tx_pwr_limit_5g[RTW_REGD_WW][bw][rs][ch_idx] = ww;
1486 }
1487 }
1488
1489 /* cross-reference 5G power limits if values are not assigned */
1490 static void
rtw_xref_5g_txpwr_lmt(struct rtw_dev * rtwdev,u8 regd,u8 bw,u8 ch_idx,u8 rs_ht,u8 rs_vht)1491 rtw_xref_5g_txpwr_lmt(struct rtw_dev *rtwdev, u8 regd,
1492 u8 bw, u8 ch_idx, u8 rs_ht, u8 rs_vht)
1493 {
1494 struct rtw_hal *hal = &rtwdev->hal;
1495 u8 max_power_index = rtwdev->chip->max_power_index;
1496 s8 lmt_ht = hal->tx_pwr_limit_5g[regd][bw][rs_ht][ch_idx];
1497 s8 lmt_vht = hal->tx_pwr_limit_5g[regd][bw][rs_vht][ch_idx];
1498
1499 if (lmt_ht == lmt_vht)
1500 return;
1501
1502 if (lmt_ht == max_power_index)
1503 hal->tx_pwr_limit_5g[regd][bw][rs_ht][ch_idx] = lmt_vht;
1504
1505 else if (lmt_vht == max_power_index)
1506 hal->tx_pwr_limit_5g[regd][bw][rs_vht][ch_idx] = lmt_ht;
1507 }
1508
1509 /* cross-reference power limits for ht and vht */
1510 static void
rtw_xref_txpwr_lmt_by_rs(struct rtw_dev * rtwdev,u8 regd,u8 bw,u8 ch_idx)1511 rtw_xref_txpwr_lmt_by_rs(struct rtw_dev *rtwdev, u8 regd, u8 bw, u8 ch_idx)
1512 {
1513 u8 rs_idx, rs_ht, rs_vht;
1514 u8 rs_cmp[2][2] = {{RTW_RATE_SECTION_HT_1S, RTW_RATE_SECTION_VHT_1S},
1515 {RTW_RATE_SECTION_HT_2S, RTW_RATE_SECTION_VHT_2S} };
1516
1517 for (rs_idx = 0; rs_idx < 2; rs_idx++) {
1518 rs_ht = rs_cmp[rs_idx][0];
1519 rs_vht = rs_cmp[rs_idx][1];
1520
1521 rtw_xref_5g_txpwr_lmt(rtwdev, regd, bw, ch_idx, rs_ht, rs_vht);
1522 }
1523 }
1524
1525 /* cross-reference power limits for 5G channels */
1526 static void
rtw_xref_5g_txpwr_lmt_by_ch(struct rtw_dev * rtwdev,u8 regd,u8 bw)1527 rtw_xref_5g_txpwr_lmt_by_ch(struct rtw_dev *rtwdev, u8 regd, u8 bw)
1528 {
1529 u8 ch_idx;
1530
1531 for (ch_idx = 0; ch_idx < RTW_MAX_CHANNEL_NUM_5G; ch_idx++)
1532 rtw_xref_txpwr_lmt_by_rs(rtwdev, regd, bw, ch_idx);
1533 }
1534
1535 /* cross-reference power limits for 20/40M bandwidth */
1536 static void
rtw_xref_txpwr_lmt_by_bw(struct rtw_dev * rtwdev,u8 regd)1537 rtw_xref_txpwr_lmt_by_bw(struct rtw_dev *rtwdev, u8 regd)
1538 {
1539 u8 bw;
1540
1541 for (bw = RTW_CHANNEL_WIDTH_20; bw <= RTW_CHANNEL_WIDTH_40; bw++)
1542 rtw_xref_5g_txpwr_lmt_by_ch(rtwdev, regd, bw);
1543 }
1544
1545 /* cross-reference power limits */
rtw_xref_txpwr_lmt(struct rtw_dev * rtwdev)1546 static void rtw_xref_txpwr_lmt(struct rtw_dev *rtwdev)
1547 {
1548 u8 regd;
1549
1550 for (regd = 0; regd < RTW_REGD_MAX; regd++)
1551 rtw_xref_txpwr_lmt_by_bw(rtwdev, regd);
1552 }
1553
rtw_parse_tbl_txpwr_lmt(struct rtw_dev * rtwdev,const struct rtw_table * tbl)1554 void rtw_parse_tbl_txpwr_lmt(struct rtw_dev *rtwdev,
1555 const struct rtw_table *tbl)
1556 {
1557 const struct rtw_txpwr_lmt_cfg_pair *p = tbl->data;
1558 const struct rtw_txpwr_lmt_cfg_pair *end = p + tbl->size;
1559
1560 for (; p < end; p++) {
1561 rtw_phy_set_tx_power_limit(rtwdev, p->regd, p->band,
1562 p->bw, p->rs, p->ch, p->txpwr_lmt);
1563 }
1564
1565 rtw_xref_txpwr_lmt(rtwdev);
1566 }
1567 EXPORT_SYMBOL(rtw_parse_tbl_txpwr_lmt);
1568
rtw_phy_cfg_mac(struct rtw_dev * rtwdev,const struct rtw_table * tbl,u32 addr,u32 data)1569 void rtw_phy_cfg_mac(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
1570 u32 addr, u32 data)
1571 {
1572 rtw_write8(rtwdev, addr, data);
1573 }
1574 EXPORT_SYMBOL(rtw_phy_cfg_mac);
1575
rtw_phy_cfg_agc(struct rtw_dev * rtwdev,const struct rtw_table * tbl,u32 addr,u32 data)1576 void rtw_phy_cfg_agc(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
1577 u32 addr, u32 data)
1578 {
1579 rtw_write32(rtwdev, addr, data);
1580 }
1581 EXPORT_SYMBOL(rtw_phy_cfg_agc);
1582
rtw_phy_cfg_bb(struct rtw_dev * rtwdev,const struct rtw_table * tbl,u32 addr,u32 data)1583 void rtw_phy_cfg_bb(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
1584 u32 addr, u32 data)
1585 {
1586 if (addr == 0xfe)
1587 msleep(50);
1588 else if (addr == 0xfd)
1589 mdelay(5);
1590 else if (addr == 0xfc)
1591 mdelay(1);
1592 else if (addr == 0xfb)
1593 usleep_range(50, 60);
1594 else if (addr == 0xfa)
1595 udelay(5);
1596 else if (addr == 0xf9)
1597 udelay(1);
1598 else
1599 rtw_write32(rtwdev, addr, data);
1600 }
1601 EXPORT_SYMBOL(rtw_phy_cfg_bb);
1602
rtw_phy_cfg_rf(struct rtw_dev * rtwdev,const struct rtw_table * tbl,u32 addr,u32 data)1603 void rtw_phy_cfg_rf(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
1604 u32 addr, u32 data)
1605 {
1606 if (addr == 0xffe) {
1607 msleep(50);
1608 } else if (addr == 0xfe) {
1609 usleep_range(100, 110);
1610 } else {
1611 rtw_write_rf(rtwdev, tbl->rf_path, addr, RFREG_MASK, data);
1612 udelay(1);
1613 }
1614 }
1615 EXPORT_SYMBOL(rtw_phy_cfg_rf);
1616
rtw_load_rfk_table(struct rtw_dev * rtwdev)1617 static void rtw_load_rfk_table(struct rtw_dev *rtwdev)
1618 {
1619 struct rtw_chip_info *chip = rtwdev->chip;
1620 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
1621
1622 if (!chip->rfk_init_tbl)
1623 return;
1624
1625 rtw_write32_mask(rtwdev, 0x1e24, BIT(17), 0x1);
1626 rtw_write32_mask(rtwdev, 0x1cd0, BIT(28), 0x1);
1627 rtw_write32_mask(rtwdev, 0x1cd0, BIT(29), 0x1);
1628 rtw_write32_mask(rtwdev, 0x1cd0, BIT(30), 0x1);
1629 rtw_write32_mask(rtwdev, 0x1cd0, BIT(31), 0x0);
1630
1631 rtw_load_table(rtwdev, chip->rfk_init_tbl);
1632
1633 dpk_info->is_dpk_pwr_on = true;
1634 }
1635
rtw_phy_load_tables(struct rtw_dev * rtwdev)1636 void rtw_phy_load_tables(struct rtw_dev *rtwdev)
1637 {
1638 struct rtw_chip_info *chip = rtwdev->chip;
1639 u8 rf_path;
1640
1641 rtw_load_table(rtwdev, chip->mac_tbl);
1642 rtw_load_table(rtwdev, chip->bb_tbl);
1643 rtw_load_table(rtwdev, chip->agc_tbl);
1644 rtw_load_rfk_table(rtwdev);
1645
1646 for (rf_path = 0; rf_path < rtwdev->hal.rf_path_num; rf_path++) {
1647 const struct rtw_table *tbl;
1648
1649 tbl = chip->rf_tbl[rf_path];
1650 rtw_load_table(rtwdev, tbl);
1651 }
1652 }
1653 EXPORT_SYMBOL(rtw_phy_load_tables);
1654
rtw_get_channel_group(u8 channel,u8 rate)1655 static u8 rtw_get_channel_group(u8 channel, u8 rate)
1656 {
1657 switch (channel) {
1658 default:
1659 WARN_ON(1);
1660 fallthrough;
1661 case 1:
1662 case 2:
1663 case 36:
1664 case 38:
1665 case 40:
1666 case 42:
1667 return 0;
1668 case 3:
1669 case 4:
1670 case 5:
1671 case 44:
1672 case 46:
1673 case 48:
1674 case 50:
1675 return 1;
1676 case 6:
1677 case 7:
1678 case 8:
1679 case 52:
1680 case 54:
1681 case 56:
1682 case 58:
1683 return 2;
1684 case 9:
1685 case 10:
1686 case 11:
1687 case 60:
1688 case 62:
1689 case 64:
1690 return 3;
1691 case 12:
1692 case 13:
1693 case 100:
1694 case 102:
1695 case 104:
1696 case 106:
1697 return 4;
1698 case 14:
1699 return rate <= DESC_RATE11M ? 5 : 4;
1700 case 108:
1701 case 110:
1702 case 112:
1703 case 114:
1704 return 5;
1705 case 116:
1706 case 118:
1707 case 120:
1708 case 122:
1709 return 6;
1710 case 124:
1711 case 126:
1712 case 128:
1713 case 130:
1714 return 7;
1715 case 132:
1716 case 134:
1717 case 136:
1718 case 138:
1719 return 8;
1720 case 140:
1721 case 142:
1722 case 144:
1723 return 9;
1724 case 149:
1725 case 151:
1726 case 153:
1727 case 155:
1728 return 10;
1729 case 157:
1730 case 159:
1731 case 161:
1732 return 11;
1733 case 165:
1734 case 167:
1735 case 169:
1736 case 171:
1737 return 12;
1738 case 173:
1739 case 175:
1740 case 177:
1741 return 13;
1742 }
1743 }
1744
rtw_phy_get_dis_dpd_by_rate_diff(struct rtw_dev * rtwdev,u16 rate)1745 static s8 rtw_phy_get_dis_dpd_by_rate_diff(struct rtw_dev *rtwdev, u16 rate)
1746 {
1747 struct rtw_chip_info *chip = rtwdev->chip;
1748 s8 dpd_diff = 0;
1749
1750 if (!chip->en_dis_dpd)
1751 return 0;
1752
1753 #define RTW_DPD_RATE_CHECK(_rate) \
1754 case DESC_RATE ## _rate: \
1755 if (DIS_DPD_RATE ## _rate & chip->dpd_ratemask) \
1756 dpd_diff = -6 * chip->txgi_factor; \
1757 break
1758
1759 switch (rate) {
1760 RTW_DPD_RATE_CHECK(6M);
1761 RTW_DPD_RATE_CHECK(9M);
1762 RTW_DPD_RATE_CHECK(MCS0);
1763 RTW_DPD_RATE_CHECK(MCS1);
1764 RTW_DPD_RATE_CHECK(MCS8);
1765 RTW_DPD_RATE_CHECK(MCS9);
1766 RTW_DPD_RATE_CHECK(VHT1SS_MCS0);
1767 RTW_DPD_RATE_CHECK(VHT1SS_MCS1);
1768 RTW_DPD_RATE_CHECK(VHT2SS_MCS0);
1769 RTW_DPD_RATE_CHECK(VHT2SS_MCS1);
1770 }
1771 #undef RTW_DPD_RATE_CHECK
1772
1773 return dpd_diff;
1774 }
1775
rtw_phy_get_2g_tx_power_index(struct rtw_dev * rtwdev,struct rtw_2g_txpwr_idx * pwr_idx_2g,enum rtw_bandwidth bandwidth,u8 rate,u8 group)1776 static u8 rtw_phy_get_2g_tx_power_index(struct rtw_dev *rtwdev,
1777 struct rtw_2g_txpwr_idx *pwr_idx_2g,
1778 enum rtw_bandwidth bandwidth,
1779 u8 rate, u8 group)
1780 {
1781 struct rtw_chip_info *chip = rtwdev->chip;
1782 u8 tx_power;
1783 bool mcs_rate;
1784 bool above_2ss;
1785 u8 factor = chip->txgi_factor;
1786
1787 if (rate <= DESC_RATE11M)
1788 tx_power = pwr_idx_2g->cck_base[group];
1789 else
1790 tx_power = pwr_idx_2g->bw40_base[group];
1791
1792 if (rate >= DESC_RATE6M && rate <= DESC_RATE54M)
1793 tx_power += pwr_idx_2g->ht_1s_diff.ofdm * factor;
1794
1795 mcs_rate = (rate >= DESC_RATEMCS0 && rate <= DESC_RATEMCS15) ||
1796 (rate >= DESC_RATEVHT1SS_MCS0 &&
1797 rate <= DESC_RATEVHT2SS_MCS9);
1798 above_2ss = (rate >= DESC_RATEMCS8 && rate <= DESC_RATEMCS15) ||
1799 (rate >= DESC_RATEVHT2SS_MCS0);
1800
1801 if (!mcs_rate)
1802 return tx_power;
1803
1804 switch (bandwidth) {
1805 default:
1806 WARN_ON(1);
1807 fallthrough;
1808 case RTW_CHANNEL_WIDTH_20:
1809 tx_power += pwr_idx_2g->ht_1s_diff.bw20 * factor;
1810 if (above_2ss)
1811 tx_power += pwr_idx_2g->ht_2s_diff.bw20 * factor;
1812 break;
1813 case RTW_CHANNEL_WIDTH_40:
1814 /* bw40 is the base power */
1815 if (above_2ss)
1816 tx_power += pwr_idx_2g->ht_2s_diff.bw40 * factor;
1817 break;
1818 }
1819
1820 return tx_power;
1821 }
1822
rtw_phy_get_5g_tx_power_index(struct rtw_dev * rtwdev,struct rtw_5g_txpwr_idx * pwr_idx_5g,enum rtw_bandwidth bandwidth,u8 rate,u8 group)1823 static u8 rtw_phy_get_5g_tx_power_index(struct rtw_dev *rtwdev,
1824 struct rtw_5g_txpwr_idx *pwr_idx_5g,
1825 enum rtw_bandwidth bandwidth,
1826 u8 rate, u8 group)
1827 {
1828 struct rtw_chip_info *chip = rtwdev->chip;
1829 u8 tx_power;
1830 u8 upper, lower;
1831 bool mcs_rate;
1832 bool above_2ss;
1833 u8 factor = chip->txgi_factor;
1834
1835 tx_power = pwr_idx_5g->bw40_base[group];
1836
1837 mcs_rate = (rate >= DESC_RATEMCS0 && rate <= DESC_RATEMCS15) ||
1838 (rate >= DESC_RATEVHT1SS_MCS0 &&
1839 rate <= DESC_RATEVHT2SS_MCS9);
1840 above_2ss = (rate >= DESC_RATEMCS8 && rate <= DESC_RATEMCS15) ||
1841 (rate >= DESC_RATEVHT2SS_MCS0);
1842
1843 if (!mcs_rate) {
1844 tx_power += pwr_idx_5g->ht_1s_diff.ofdm * factor;
1845 return tx_power;
1846 }
1847
1848 switch (bandwidth) {
1849 default:
1850 WARN_ON(1);
1851 fallthrough;
1852 case RTW_CHANNEL_WIDTH_20:
1853 tx_power += pwr_idx_5g->ht_1s_diff.bw20 * factor;
1854 if (above_2ss)
1855 tx_power += pwr_idx_5g->ht_2s_diff.bw20 * factor;
1856 break;
1857 case RTW_CHANNEL_WIDTH_40:
1858 /* bw40 is the base power */
1859 if (above_2ss)
1860 tx_power += pwr_idx_5g->ht_2s_diff.bw40 * factor;
1861 break;
1862 case RTW_CHANNEL_WIDTH_80:
1863 /* the base idx of bw80 is the average of bw40+/bw40- */
1864 lower = pwr_idx_5g->bw40_base[group];
1865 upper = pwr_idx_5g->bw40_base[group + 1];
1866
1867 tx_power = (lower + upper) / 2;
1868 tx_power += pwr_idx_5g->vht_1s_diff.bw80 * factor;
1869 if (above_2ss)
1870 tx_power += pwr_idx_5g->vht_2s_diff.bw80 * factor;
1871 break;
1872 }
1873
1874 return tx_power;
1875 }
1876
rtw_phy_get_tx_power_limit(struct rtw_dev * rtwdev,u8 band,enum rtw_bandwidth bw,u8 rf_path,u8 rate,u8 channel,u8 regd)1877 static s8 rtw_phy_get_tx_power_limit(struct rtw_dev *rtwdev, u8 band,
1878 enum rtw_bandwidth bw, u8 rf_path,
1879 u8 rate, u8 channel, u8 regd)
1880 {
1881 struct rtw_hal *hal = &rtwdev->hal;
1882 u8 *cch_by_bw = hal->cch_by_bw;
1883 s8 power_limit = (s8)rtwdev->chip->max_power_index;
1884 u8 rs;
1885 int ch_idx;
1886 u8 cur_bw, cur_ch;
1887 s8 cur_lmt;
1888
1889 if (regd > RTW_REGD_WW)
1890 return power_limit;
1891
1892 if (rate >= DESC_RATE1M && rate <= DESC_RATE11M)
1893 rs = RTW_RATE_SECTION_CCK;
1894 else if (rate >= DESC_RATE6M && rate <= DESC_RATE54M)
1895 rs = RTW_RATE_SECTION_OFDM;
1896 else if (rate >= DESC_RATEMCS0 && rate <= DESC_RATEMCS7)
1897 rs = RTW_RATE_SECTION_HT_1S;
1898 else if (rate >= DESC_RATEMCS8 && rate <= DESC_RATEMCS15)
1899 rs = RTW_RATE_SECTION_HT_2S;
1900 else if (rate >= DESC_RATEVHT1SS_MCS0 && rate <= DESC_RATEVHT1SS_MCS9)
1901 rs = RTW_RATE_SECTION_VHT_1S;
1902 else if (rate >= DESC_RATEVHT2SS_MCS0 && rate <= DESC_RATEVHT2SS_MCS9)
1903 rs = RTW_RATE_SECTION_VHT_2S;
1904 else
1905 goto err;
1906
1907 /* only 20M BW with cck and ofdm */
1908 if (rs == RTW_RATE_SECTION_CCK || rs == RTW_RATE_SECTION_OFDM)
1909 bw = RTW_CHANNEL_WIDTH_20;
1910
1911 /* only 20/40M BW with ht */
1912 if (rs == RTW_RATE_SECTION_HT_1S || rs == RTW_RATE_SECTION_HT_2S)
1913 bw = min_t(u8, bw, RTW_CHANNEL_WIDTH_40);
1914
1915 /* select min power limit among [20M BW ~ current BW] */
1916 for (cur_bw = RTW_CHANNEL_WIDTH_20; cur_bw <= bw; cur_bw++) {
1917 cur_ch = cch_by_bw[cur_bw];
1918
1919 ch_idx = rtw_channel_to_idx(band, cur_ch);
1920 if (ch_idx < 0)
1921 goto err;
1922
1923 cur_lmt = cur_ch <= RTW_MAX_CHANNEL_NUM_2G ?
1924 hal->tx_pwr_limit_2g[regd][cur_bw][rs][ch_idx] :
1925 hal->tx_pwr_limit_5g[regd][cur_bw][rs][ch_idx];
1926
1927 power_limit = min_t(s8, cur_lmt, power_limit);
1928 }
1929
1930 return power_limit;
1931
1932 err:
1933 WARN(1, "invalid arguments, band=%d, bw=%d, path=%d, rate=%d, ch=%d\n",
1934 band, bw, rf_path, rate, channel);
1935 return (s8)rtwdev->chip->max_power_index;
1936 }
1937
rtw_get_tx_power_params(struct rtw_dev * rtwdev,u8 path,u8 rate,u8 bw,u8 ch,u8 regd,struct rtw_power_params * pwr_param)1938 void rtw_get_tx_power_params(struct rtw_dev *rtwdev, u8 path, u8 rate, u8 bw,
1939 u8 ch, u8 regd, struct rtw_power_params *pwr_param)
1940 {
1941 struct rtw_hal *hal = &rtwdev->hal;
1942 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1943 struct rtw_txpwr_idx *pwr_idx;
1944 u8 group, band;
1945 u8 *base = &pwr_param->pwr_base;
1946 s8 *offset = &pwr_param->pwr_offset;
1947 s8 *limit = &pwr_param->pwr_limit;
1948 s8 *remnant = &pwr_param->pwr_remnant;
1949
1950 pwr_idx = &rtwdev->efuse.txpwr_idx_table[path];
1951 group = rtw_get_channel_group(ch, rate);
1952
1953 /* base power index for 2.4G/5G */
1954 if (IS_CH_2G_BAND(ch)) {
1955 band = PHY_BAND_2G;
1956 *base = rtw_phy_get_2g_tx_power_index(rtwdev,
1957 &pwr_idx->pwr_idx_2g,
1958 bw, rate, group);
1959 *offset = hal->tx_pwr_by_rate_offset_2g[path][rate];
1960 } else {
1961 band = PHY_BAND_5G;
1962 *base = rtw_phy_get_5g_tx_power_index(rtwdev,
1963 &pwr_idx->pwr_idx_5g,
1964 bw, rate, group);
1965 *offset = hal->tx_pwr_by_rate_offset_5g[path][rate];
1966 }
1967
1968 *limit = rtw_phy_get_tx_power_limit(rtwdev, band, bw, path,
1969 rate, ch, regd);
1970 *remnant = (rate <= DESC_RATE11M ? dm_info->txagc_remnant_cck :
1971 dm_info->txagc_remnant_ofdm);
1972 }
1973
1974 u8
rtw_phy_get_tx_power_index(struct rtw_dev * rtwdev,u8 rf_path,u8 rate,enum rtw_bandwidth bandwidth,u8 channel,u8 regd)1975 rtw_phy_get_tx_power_index(struct rtw_dev *rtwdev, u8 rf_path, u8 rate,
1976 enum rtw_bandwidth bandwidth, u8 channel, u8 regd)
1977 {
1978 struct rtw_power_params pwr_param = {0};
1979 u8 tx_power;
1980 s8 offset;
1981
1982 rtw_get_tx_power_params(rtwdev, rf_path, rate, bandwidth,
1983 channel, regd, &pwr_param);
1984
1985 tx_power = pwr_param.pwr_base;
1986 offset = min_t(s8, pwr_param.pwr_offset, pwr_param.pwr_limit);
1987
1988 if (rtwdev->chip->en_dis_dpd)
1989 offset += rtw_phy_get_dis_dpd_by_rate_diff(rtwdev, rate);
1990
1991 tx_power += offset + pwr_param.pwr_remnant;
1992
1993 if (tx_power > rtwdev->chip->max_power_index)
1994 tx_power = rtwdev->chip->max_power_index;
1995
1996 return tx_power;
1997 }
1998 EXPORT_SYMBOL(rtw_phy_get_tx_power_index);
1999
rtw_phy_set_tx_power_index_by_rs(struct rtw_dev * rtwdev,u8 ch,u8 path,u8 rs)2000 static void rtw_phy_set_tx_power_index_by_rs(struct rtw_dev *rtwdev,
2001 u8 ch, u8 path, u8 rs)
2002 {
2003 struct rtw_hal *hal = &rtwdev->hal;
2004 u8 regd = rtwdev->regd.txpwr_regd;
2005 u8 *rates;
2006 u8 size;
2007 u8 rate;
2008 u8 pwr_idx;
2009 u8 bw;
2010 int i;
2011
2012 if (rs >= RTW_RATE_SECTION_MAX)
2013 return;
2014
2015 rates = rtw_rate_section[rs];
2016 size = rtw_rate_size[rs];
2017 bw = hal->current_band_width;
2018 for (i = 0; i < size; i++) {
2019 rate = rates[i];
2020 pwr_idx = rtw_phy_get_tx_power_index(rtwdev, path, rate,
2021 bw, ch, regd);
2022 hal->tx_pwr_tbl[path][rate] = pwr_idx;
2023 }
2024 }
2025
2026 /* set tx power level by path for each rates, note that the order of the rates
2027 * are *very* important, bacause 8822B/8821C combines every four bytes of tx
2028 * power index into a four-byte power index register, and calls set_tx_agc to
2029 * write these values into hardware
2030 */
rtw_phy_set_tx_power_level_by_path(struct rtw_dev * rtwdev,u8 ch,u8 path)2031 static void rtw_phy_set_tx_power_level_by_path(struct rtw_dev *rtwdev,
2032 u8 ch, u8 path)
2033 {
2034 struct rtw_hal *hal = &rtwdev->hal;
2035 u8 rs;
2036
2037 /* do not need cck rates if we are not in 2.4G */
2038 if (hal->current_band_type == RTW_BAND_2G)
2039 rs = RTW_RATE_SECTION_CCK;
2040 else
2041 rs = RTW_RATE_SECTION_OFDM;
2042
2043 for (; rs < RTW_RATE_SECTION_MAX; rs++)
2044 rtw_phy_set_tx_power_index_by_rs(rtwdev, ch, path, rs);
2045 }
2046
rtw_phy_set_tx_power_level(struct rtw_dev * rtwdev,u8 channel)2047 void rtw_phy_set_tx_power_level(struct rtw_dev *rtwdev, u8 channel)
2048 {
2049 struct rtw_chip_info *chip = rtwdev->chip;
2050 struct rtw_hal *hal = &rtwdev->hal;
2051 u8 path;
2052
2053 mutex_lock(&hal->tx_power_mutex);
2054
2055 for (path = 0; path < hal->rf_path_num; path++)
2056 rtw_phy_set_tx_power_level_by_path(rtwdev, channel, path);
2057
2058 chip->ops->set_tx_power_index(rtwdev);
2059 mutex_unlock(&hal->tx_power_mutex);
2060 }
2061 EXPORT_SYMBOL(rtw_phy_set_tx_power_level);
2062
2063 static void
rtw_phy_tx_power_by_rate_config_by_path(struct rtw_hal * hal,u8 path,u8 rs,u8 size,u8 * rates)2064 rtw_phy_tx_power_by_rate_config_by_path(struct rtw_hal *hal, u8 path,
2065 u8 rs, u8 size, u8 *rates)
2066 {
2067 u8 rate;
2068 u8 base_idx, rate_idx;
2069 s8 base_2g, base_5g;
2070
2071 if (rs >= RTW_RATE_SECTION_VHT_1S)
2072 base_idx = rates[size - 3];
2073 else
2074 base_idx = rates[size - 1];
2075 base_2g = hal->tx_pwr_by_rate_offset_2g[path][base_idx];
2076 base_5g = hal->tx_pwr_by_rate_offset_5g[path][base_idx];
2077 hal->tx_pwr_by_rate_base_2g[path][rs] = base_2g;
2078 hal->tx_pwr_by_rate_base_5g[path][rs] = base_5g;
2079 for (rate = 0; rate < size; rate++) {
2080 rate_idx = rates[rate];
2081 hal->tx_pwr_by_rate_offset_2g[path][rate_idx] -= base_2g;
2082 hal->tx_pwr_by_rate_offset_5g[path][rate_idx] -= base_5g;
2083 }
2084 }
2085
rtw_phy_tx_power_by_rate_config(struct rtw_hal * hal)2086 void rtw_phy_tx_power_by_rate_config(struct rtw_hal *hal)
2087 {
2088 u8 path;
2089
2090 for (path = 0; path < RTW_RF_PATH_MAX; path++) {
2091 rtw_phy_tx_power_by_rate_config_by_path(hal, path,
2092 RTW_RATE_SECTION_CCK,
2093 rtw_cck_size, rtw_cck_rates);
2094 rtw_phy_tx_power_by_rate_config_by_path(hal, path,
2095 RTW_RATE_SECTION_OFDM,
2096 rtw_ofdm_size, rtw_ofdm_rates);
2097 rtw_phy_tx_power_by_rate_config_by_path(hal, path,
2098 RTW_RATE_SECTION_HT_1S,
2099 rtw_ht_1s_size, rtw_ht_1s_rates);
2100 rtw_phy_tx_power_by_rate_config_by_path(hal, path,
2101 RTW_RATE_SECTION_HT_2S,
2102 rtw_ht_2s_size, rtw_ht_2s_rates);
2103 rtw_phy_tx_power_by_rate_config_by_path(hal, path,
2104 RTW_RATE_SECTION_VHT_1S,
2105 rtw_vht_1s_size, rtw_vht_1s_rates);
2106 rtw_phy_tx_power_by_rate_config_by_path(hal, path,
2107 RTW_RATE_SECTION_VHT_2S,
2108 rtw_vht_2s_size, rtw_vht_2s_rates);
2109 }
2110 }
2111
2112 static void
__rtw_phy_tx_power_limit_config(struct rtw_hal * hal,u8 regd,u8 bw,u8 rs)2113 __rtw_phy_tx_power_limit_config(struct rtw_hal *hal, u8 regd, u8 bw, u8 rs)
2114 {
2115 s8 base;
2116 u8 ch;
2117
2118 for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_2G; ch++) {
2119 base = hal->tx_pwr_by_rate_base_2g[0][rs];
2120 hal->tx_pwr_limit_2g[regd][bw][rs][ch] -= base;
2121 }
2122
2123 for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_5G; ch++) {
2124 base = hal->tx_pwr_by_rate_base_5g[0][rs];
2125 hal->tx_pwr_limit_5g[regd][bw][rs][ch] -= base;
2126 }
2127 }
2128
rtw_phy_tx_power_limit_config(struct rtw_hal * hal)2129 void rtw_phy_tx_power_limit_config(struct rtw_hal *hal)
2130 {
2131 u8 regd, bw, rs;
2132
2133 /* default at channel 1 */
2134 hal->cch_by_bw[RTW_CHANNEL_WIDTH_20] = 1;
2135
2136 for (regd = 0; regd < RTW_REGD_MAX; regd++)
2137 for (bw = 0; bw < RTW_CHANNEL_WIDTH_MAX; bw++)
2138 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++)
2139 __rtw_phy_tx_power_limit_config(hal, regd, bw, rs);
2140 }
2141
rtw_phy_init_tx_power_limit(struct rtw_dev * rtwdev,u8 regd,u8 bw,u8 rs)2142 static void rtw_phy_init_tx_power_limit(struct rtw_dev *rtwdev,
2143 u8 regd, u8 bw, u8 rs)
2144 {
2145 struct rtw_hal *hal = &rtwdev->hal;
2146 s8 max_power_index = (s8)rtwdev->chip->max_power_index;
2147 u8 ch;
2148
2149 /* 2.4G channels */
2150 for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_2G; ch++)
2151 hal->tx_pwr_limit_2g[regd][bw][rs][ch] = max_power_index;
2152
2153 /* 5G channels */
2154 for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_5G; ch++)
2155 hal->tx_pwr_limit_5g[regd][bw][rs][ch] = max_power_index;
2156 }
2157
rtw_phy_init_tx_power(struct rtw_dev * rtwdev)2158 void rtw_phy_init_tx_power(struct rtw_dev *rtwdev)
2159 {
2160 struct rtw_hal *hal = &rtwdev->hal;
2161 u8 regd, path, rate, rs, bw;
2162
2163 /* init tx power by rate offset */
2164 for (path = 0; path < RTW_RF_PATH_MAX; path++) {
2165 for (rate = 0; rate < DESC_RATE_MAX; rate++) {
2166 hal->tx_pwr_by_rate_offset_2g[path][rate] = 0;
2167 hal->tx_pwr_by_rate_offset_5g[path][rate] = 0;
2168 }
2169 }
2170
2171 /* init tx power limit */
2172 for (regd = 0; regd < RTW_REGD_MAX; regd++)
2173 for (bw = 0; bw < RTW_CHANNEL_WIDTH_MAX; bw++)
2174 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++)
2175 rtw_phy_init_tx_power_limit(rtwdev, regd, bw,
2176 rs);
2177 }
2178
rtw_phy_config_swing_table(struct rtw_dev * rtwdev,struct rtw_swing_table * swing_table)2179 void rtw_phy_config_swing_table(struct rtw_dev *rtwdev,
2180 struct rtw_swing_table *swing_table)
2181 {
2182 const struct rtw_pwr_track_tbl *tbl = rtwdev->chip->pwr_track_tbl;
2183 u8 channel = rtwdev->hal.current_channel;
2184
2185 if (IS_CH_2G_BAND(channel)) {
2186 if (rtwdev->dm_info.tx_rate <= DESC_RATE11M) {
2187 swing_table->p[RF_PATH_A] = tbl->pwrtrk_2g_ccka_p;
2188 swing_table->n[RF_PATH_A] = tbl->pwrtrk_2g_ccka_n;
2189 swing_table->p[RF_PATH_B] = tbl->pwrtrk_2g_cckb_p;
2190 swing_table->n[RF_PATH_B] = tbl->pwrtrk_2g_cckb_n;
2191 } else {
2192 swing_table->p[RF_PATH_A] = tbl->pwrtrk_2ga_p;
2193 swing_table->n[RF_PATH_A] = tbl->pwrtrk_2ga_n;
2194 swing_table->p[RF_PATH_B] = tbl->pwrtrk_2gb_p;
2195 swing_table->n[RF_PATH_B] = tbl->pwrtrk_2gb_n;
2196 }
2197 } else if (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel)) {
2198 swing_table->p[RF_PATH_A] = tbl->pwrtrk_5ga_p[RTW_PWR_TRK_5G_1];
2199 swing_table->n[RF_PATH_A] = tbl->pwrtrk_5ga_n[RTW_PWR_TRK_5G_1];
2200 swing_table->p[RF_PATH_B] = tbl->pwrtrk_5gb_p[RTW_PWR_TRK_5G_1];
2201 swing_table->n[RF_PATH_B] = tbl->pwrtrk_5gb_n[RTW_PWR_TRK_5G_1];
2202 } else if (IS_CH_5G_BAND_3(channel)) {
2203 swing_table->p[RF_PATH_A] = tbl->pwrtrk_5ga_p[RTW_PWR_TRK_5G_2];
2204 swing_table->n[RF_PATH_A] = tbl->pwrtrk_5ga_n[RTW_PWR_TRK_5G_2];
2205 swing_table->p[RF_PATH_B] = tbl->pwrtrk_5gb_p[RTW_PWR_TRK_5G_2];
2206 swing_table->n[RF_PATH_B] = tbl->pwrtrk_5gb_n[RTW_PWR_TRK_5G_2];
2207 } else if (IS_CH_5G_BAND_4(channel)) {
2208 swing_table->p[RF_PATH_A] = tbl->pwrtrk_5ga_p[RTW_PWR_TRK_5G_3];
2209 swing_table->n[RF_PATH_A] = tbl->pwrtrk_5ga_n[RTW_PWR_TRK_5G_3];
2210 swing_table->p[RF_PATH_B] = tbl->pwrtrk_5gb_p[RTW_PWR_TRK_5G_3];
2211 swing_table->n[RF_PATH_B] = tbl->pwrtrk_5gb_n[RTW_PWR_TRK_5G_3];
2212 } else {
2213 swing_table->p[RF_PATH_A] = tbl->pwrtrk_2ga_p;
2214 swing_table->n[RF_PATH_A] = tbl->pwrtrk_2ga_n;
2215 swing_table->p[RF_PATH_B] = tbl->pwrtrk_2gb_p;
2216 swing_table->n[RF_PATH_B] = tbl->pwrtrk_2gb_n;
2217 }
2218 }
2219 EXPORT_SYMBOL(rtw_phy_config_swing_table);
2220
rtw_phy_pwrtrack_avg(struct rtw_dev * rtwdev,u8 thermal,u8 path)2221 void rtw_phy_pwrtrack_avg(struct rtw_dev *rtwdev, u8 thermal, u8 path)
2222 {
2223 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
2224
2225 ewma_thermal_add(&dm_info->avg_thermal[path], thermal);
2226 dm_info->thermal_avg[path] =
2227 ewma_thermal_read(&dm_info->avg_thermal[path]);
2228 }
2229 EXPORT_SYMBOL(rtw_phy_pwrtrack_avg);
2230
rtw_phy_pwrtrack_thermal_changed(struct rtw_dev * rtwdev,u8 thermal,u8 path)2231 bool rtw_phy_pwrtrack_thermal_changed(struct rtw_dev *rtwdev, u8 thermal,
2232 u8 path)
2233 {
2234 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
2235 u8 avg = ewma_thermal_read(&dm_info->avg_thermal[path]);
2236
2237 if (avg == thermal)
2238 return false;
2239
2240 return true;
2241 }
2242 EXPORT_SYMBOL(rtw_phy_pwrtrack_thermal_changed);
2243
rtw_phy_pwrtrack_get_delta(struct rtw_dev * rtwdev,u8 path)2244 u8 rtw_phy_pwrtrack_get_delta(struct rtw_dev *rtwdev, u8 path)
2245 {
2246 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
2247 u8 therm_avg, therm_efuse, therm_delta;
2248
2249 therm_avg = dm_info->thermal_avg[path];
2250 therm_efuse = rtwdev->efuse.thermal_meter[path];
2251 therm_delta = abs(therm_avg - therm_efuse);
2252
2253 return min_t(u8, therm_delta, RTW_PWR_TRK_TBL_SZ - 1);
2254 }
2255 EXPORT_SYMBOL(rtw_phy_pwrtrack_get_delta);
2256
rtw_phy_pwrtrack_get_pwridx(struct rtw_dev * rtwdev,struct rtw_swing_table * swing_table,u8 tbl_path,u8 therm_path,u8 delta)2257 s8 rtw_phy_pwrtrack_get_pwridx(struct rtw_dev *rtwdev,
2258 struct rtw_swing_table *swing_table,
2259 u8 tbl_path, u8 therm_path, u8 delta)
2260 {
2261 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
2262 const u8 *delta_swing_table_idx_pos;
2263 const u8 *delta_swing_table_idx_neg;
2264
2265 if (delta >= RTW_PWR_TRK_TBL_SZ) {
2266 rtw_warn(rtwdev, "power track table overflow\n");
2267 return 0;
2268 }
2269
2270 if (!swing_table) {
2271 rtw_warn(rtwdev, "swing table not configured\n");
2272 return 0;
2273 }
2274
2275 delta_swing_table_idx_pos = swing_table->p[tbl_path];
2276 delta_swing_table_idx_neg = swing_table->n[tbl_path];
2277
2278 if (!delta_swing_table_idx_pos || !delta_swing_table_idx_neg) {
2279 rtw_warn(rtwdev, "invalid swing table index\n");
2280 return 0;
2281 }
2282
2283 if (dm_info->thermal_avg[therm_path] >
2284 rtwdev->efuse.thermal_meter[therm_path])
2285 return delta_swing_table_idx_pos[delta];
2286 else
2287 return -delta_swing_table_idx_neg[delta];
2288 }
2289 EXPORT_SYMBOL(rtw_phy_pwrtrack_get_pwridx);
2290
rtw_phy_pwrtrack_need_lck(struct rtw_dev * rtwdev)2291 bool rtw_phy_pwrtrack_need_lck(struct rtw_dev *rtwdev)
2292 {
2293 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
2294 u8 delta_lck;
2295
2296 delta_lck = abs(dm_info->thermal_avg[0] - dm_info->thermal_meter_lck);
2297 if (delta_lck >= rtwdev->chip->lck_threshold) {
2298 dm_info->thermal_meter_lck = dm_info->thermal_avg[0];
2299 return true;
2300 }
2301 return false;
2302 }
2303 EXPORT_SYMBOL(rtw_phy_pwrtrack_need_lck);
2304
rtw_phy_pwrtrack_need_iqk(struct rtw_dev * rtwdev)2305 bool rtw_phy_pwrtrack_need_iqk(struct rtw_dev *rtwdev)
2306 {
2307 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
2308 u8 delta_iqk;
2309
2310 delta_iqk = abs(dm_info->thermal_avg[0] - dm_info->thermal_meter_k);
2311 if (delta_iqk >= rtwdev->chip->iqk_threshold) {
2312 dm_info->thermal_meter_k = dm_info->thermal_avg[0];
2313 return true;
2314 }
2315 return false;
2316 }
2317 EXPORT_SYMBOL(rtw_phy_pwrtrack_need_iqk);
2318