1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * NinjaSCSI-32Bi Cardbus, NinjaSCSI-32UDE PCI/CardBus SCSI driver
4 * Copyright (C) 2001, 2002, 2003
5 * YOKOTA Hiroshi <yokota@netlab.is.tsukuba.ac.jp>
6 * GOTO Masanori <gotom@debian.or.jp>, <gotom@debian.org>
7 *
8 * Revision History:
9 * 1.0: Initial Release.
10 * 1.1: Add /proc SDTR status.
11 * Remove obsolete error handler nsp32_reset.
12 * Some clean up.
13 * 1.2: PowerPC (big endian) support.
14 */
15
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/kernel.h>
19 #include <linux/string.h>
20 #include <linux/timer.h>
21 #include <linux/ioport.h>
22 #include <linux/major.h>
23 #include <linux/blkdev.h>
24 #include <linux/interrupt.h>
25 #include <linux/pci.h>
26 #include <linux/delay.h>
27 #include <linux/ctype.h>
28 #include <linux/dma-mapping.h>
29
30 #include <asm/dma.h>
31 #include <asm/io.h>
32
33 #include <scsi/scsi.h>
34 #include <scsi/scsi_cmnd.h>
35 #include <scsi/scsi_device.h>
36 #include <scsi/scsi_host.h>
37 #include <scsi/scsi_ioctl.h>
38
39 #include "nsp32.h"
40
41
42 /***********************************************************************
43 * Module parameters
44 */
45 static int trans_mode = 0; /* default: BIOS */
46 module_param (trans_mode, int, 0);
47 MODULE_PARM_DESC(trans_mode, "transfer mode (0: BIOS(default) 1: Async 2: Ultra20M");
48 #define ASYNC_MODE 1
49 #define ULTRA20M_MODE 2
50
51 static bool auto_param = 0; /* default: ON */
52 module_param (auto_param, bool, 0);
53 MODULE_PARM_DESC(auto_param, "AutoParameter mode (0: ON(default) 1: OFF)");
54
55 static bool disc_priv = 1; /* default: OFF */
56 module_param (disc_priv, bool, 0);
57 MODULE_PARM_DESC(disc_priv, "disconnection privilege mode (0: ON 1: OFF(default))");
58
59 MODULE_AUTHOR("YOKOTA Hiroshi <yokota@netlab.is.tsukuba.ac.jp>, GOTO Masanori <gotom@debian.or.jp>");
60 MODULE_DESCRIPTION("Workbit NinjaSCSI-32Bi/UDE CardBus/PCI SCSI host bus adapter module");
61 MODULE_LICENSE("GPL");
62
63 static const char *nsp32_release_version = "1.2";
64
65
66 /****************************************************************************
67 * Supported hardware
68 */
69 static struct pci_device_id nsp32_pci_table[] = {
70 {
71 .vendor = PCI_VENDOR_ID_IODATA,
72 .device = PCI_DEVICE_ID_NINJASCSI_32BI_CBSC_II,
73 .subvendor = PCI_ANY_ID,
74 .subdevice = PCI_ANY_ID,
75 .driver_data = MODEL_IODATA,
76 },
77 {
78 .vendor = PCI_VENDOR_ID_WORKBIT,
79 .device = PCI_DEVICE_ID_NINJASCSI_32BI_KME,
80 .subvendor = PCI_ANY_ID,
81 .subdevice = PCI_ANY_ID,
82 .driver_data = MODEL_KME,
83 },
84 {
85 .vendor = PCI_VENDOR_ID_WORKBIT,
86 .device = PCI_DEVICE_ID_NINJASCSI_32BI_WBT,
87 .subvendor = PCI_ANY_ID,
88 .subdevice = PCI_ANY_ID,
89 .driver_data = MODEL_WORKBIT,
90 },
91 {
92 .vendor = PCI_VENDOR_ID_WORKBIT,
93 .device = PCI_DEVICE_ID_WORKBIT_STANDARD,
94 .subvendor = PCI_ANY_ID,
95 .subdevice = PCI_ANY_ID,
96 .driver_data = MODEL_PCI_WORKBIT,
97 },
98 {
99 .vendor = PCI_VENDOR_ID_WORKBIT,
100 .device = PCI_DEVICE_ID_NINJASCSI_32BI_LOGITEC,
101 .subvendor = PCI_ANY_ID,
102 .subdevice = PCI_ANY_ID,
103 .driver_data = MODEL_LOGITEC,
104 },
105 {
106 .vendor = PCI_VENDOR_ID_WORKBIT,
107 .device = PCI_DEVICE_ID_NINJASCSI_32BIB_LOGITEC,
108 .subvendor = PCI_ANY_ID,
109 .subdevice = PCI_ANY_ID,
110 .driver_data = MODEL_PCI_LOGITEC,
111 },
112 {
113 .vendor = PCI_VENDOR_ID_WORKBIT,
114 .device = PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO,
115 .subvendor = PCI_ANY_ID,
116 .subdevice = PCI_ANY_ID,
117 .driver_data = MODEL_PCI_MELCO,
118 },
119 {
120 .vendor = PCI_VENDOR_ID_WORKBIT,
121 .device = PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO_II,
122 .subvendor = PCI_ANY_ID,
123 .subdevice = PCI_ANY_ID,
124 .driver_data = MODEL_PCI_MELCO,
125 },
126 {0,0,},
127 };
128 MODULE_DEVICE_TABLE(pci, nsp32_pci_table);
129
130 static nsp32_hw_data nsp32_data_base; /* probe <-> detect glue */
131
132
133 /*
134 * Period/AckWidth speed conversion table
135 *
136 * Note: This period/ackwidth speed table must be in descending order.
137 */
138 static nsp32_sync_table nsp32_sync_table_40M[] = {
139 /* {PNo, AW, SP, EP, SREQ smpl} Speed(MB/s) Period AckWidth */
140 {0x1, 0, 0x0c, 0x0c, SMPL_40M}, /* 20.0 : 50ns, 25ns */
141 {0x2, 0, 0x0d, 0x18, SMPL_40M}, /* 13.3 : 75ns, 25ns */
142 {0x3, 1, 0x19, 0x19, SMPL_40M}, /* 10.0 : 100ns, 50ns */
143 {0x4, 1, 0x1a, 0x1f, SMPL_20M}, /* 8.0 : 125ns, 50ns */
144 {0x5, 2, 0x20, 0x25, SMPL_20M}, /* 6.7 : 150ns, 75ns */
145 {0x6, 2, 0x26, 0x31, SMPL_20M}, /* 5.7 : 175ns, 75ns */
146 {0x7, 3, 0x32, 0x32, SMPL_20M}, /* 5.0 : 200ns, 100ns */
147 {0x8, 3, 0x33, 0x38, SMPL_10M}, /* 4.4 : 225ns, 100ns */
148 {0x9, 3, 0x39, 0x3e, SMPL_10M}, /* 4.0 : 250ns, 100ns */
149 };
150
151 static nsp32_sync_table nsp32_sync_table_20M[] = {
152 {0x1, 0, 0x19, 0x19, SMPL_40M}, /* 10.0 : 100ns, 50ns */
153 {0x2, 0, 0x1a, 0x25, SMPL_20M}, /* 6.7 : 150ns, 50ns */
154 {0x3, 1, 0x26, 0x32, SMPL_20M}, /* 5.0 : 200ns, 100ns */
155 {0x4, 1, 0x33, 0x3e, SMPL_10M}, /* 4.0 : 250ns, 100ns */
156 {0x5, 2, 0x3f, 0x4b, SMPL_10M}, /* 3.3 : 300ns, 150ns */
157 {0x6, 2, 0x4c, 0x57, SMPL_10M}, /* 2.8 : 350ns, 150ns */
158 {0x7, 3, 0x58, 0x64, SMPL_10M}, /* 2.5 : 400ns, 200ns */
159 {0x8, 3, 0x65, 0x70, SMPL_10M}, /* 2.2 : 450ns, 200ns */
160 {0x9, 3, 0x71, 0x7d, SMPL_10M}, /* 2.0 : 500ns, 200ns */
161 };
162
163 static nsp32_sync_table nsp32_sync_table_pci[] = {
164 {0x1, 0, 0x0c, 0x0f, SMPL_40M}, /* 16.6 : 60ns, 30ns */
165 {0x2, 0, 0x10, 0x16, SMPL_40M}, /* 11.1 : 90ns, 30ns */
166 {0x3, 1, 0x17, 0x1e, SMPL_20M}, /* 8.3 : 120ns, 60ns */
167 {0x4, 1, 0x1f, 0x25, SMPL_20M}, /* 6.7 : 150ns, 60ns */
168 {0x5, 2, 0x26, 0x2d, SMPL_20M}, /* 5.6 : 180ns, 90ns */
169 {0x6, 2, 0x2e, 0x34, SMPL_10M}, /* 4.8 : 210ns, 90ns */
170 {0x7, 3, 0x35, 0x3c, SMPL_10M}, /* 4.2 : 240ns, 120ns */
171 {0x8, 3, 0x3d, 0x43, SMPL_10M}, /* 3.7 : 270ns, 120ns */
172 {0x9, 3, 0x44, 0x4b, SMPL_10M}, /* 3.3 : 300ns, 120ns */
173 };
174
175 /*
176 * function declaration
177 */
178 /* module entry point */
179 static int nsp32_probe (struct pci_dev *, const struct pci_device_id *);
180 static void nsp32_remove(struct pci_dev *);
181 static int __init init_nsp32 (void);
182 static void __exit exit_nsp32 (void);
183
184 /* struct struct scsi_host_template */
185 static int nsp32_show_info (struct seq_file *, struct Scsi_Host *);
186
187 static int nsp32_detect (struct pci_dev *pdev);
188 static int nsp32_queuecommand(struct Scsi_Host *, struct scsi_cmnd *);
189 static const char *nsp32_info (struct Scsi_Host *);
190 static int nsp32_release (struct Scsi_Host *);
191
192 /* SCSI error handler */
193 static int nsp32_eh_abort (struct scsi_cmnd *);
194 static int nsp32_eh_host_reset(struct scsi_cmnd *);
195
196 /* generate SCSI message */
197 static void nsp32_build_identify(struct scsi_cmnd *);
198 static void nsp32_build_nop (struct scsi_cmnd *);
199 static void nsp32_build_reject (struct scsi_cmnd *);
200 static void nsp32_build_sdtr (struct scsi_cmnd *, unsigned char, unsigned char);
201
202 /* SCSI message handler */
203 static int nsp32_busfree_occur(struct scsi_cmnd *, unsigned short);
204 static void nsp32_msgout_occur (struct scsi_cmnd *);
205 static void nsp32_msgin_occur (struct scsi_cmnd *, unsigned long, unsigned short);
206
207 static int nsp32_setup_sg_table (struct scsi_cmnd *);
208 static int nsp32_selection_autopara(struct scsi_cmnd *);
209 static int nsp32_selection_autoscsi(struct scsi_cmnd *);
210 static void nsp32_scsi_done (struct scsi_cmnd *);
211 static int nsp32_arbitration (struct scsi_cmnd *, unsigned int);
212 static int nsp32_reselection (struct scsi_cmnd *, unsigned char);
213 static void nsp32_adjust_busfree (struct scsi_cmnd *, unsigned int);
214 static void nsp32_restart_autoscsi (struct scsi_cmnd *, unsigned short);
215
216 /* SCSI SDTR */
217 static void nsp32_analyze_sdtr (struct scsi_cmnd *);
218 static int nsp32_search_period_entry(nsp32_hw_data *, nsp32_target *, unsigned char);
219 static void nsp32_set_async (nsp32_hw_data *, nsp32_target *);
220 static void nsp32_set_max_sync (nsp32_hw_data *, nsp32_target *, unsigned char *, unsigned char *);
221 static void nsp32_set_sync_entry (nsp32_hw_data *, nsp32_target *, int, unsigned char);
222
223 /* SCSI bus status handler */
224 static void nsp32_wait_req (nsp32_hw_data *, int);
225 static void nsp32_wait_sack (nsp32_hw_data *, int);
226 static void nsp32_sack_assert (nsp32_hw_data *);
227 static void nsp32_sack_negate (nsp32_hw_data *);
228 static void nsp32_do_bus_reset(nsp32_hw_data *);
229
230 /* hardware interrupt handler */
231 static irqreturn_t do_nsp32_isr(int, void *);
232
233 /* initialize hardware */
234 static int nsp32hw_init(nsp32_hw_data *);
235
236 /* EEPROM handler */
237 static int nsp32_getprom_param (nsp32_hw_data *);
238 static int nsp32_getprom_at24 (nsp32_hw_data *);
239 static int nsp32_getprom_c16 (nsp32_hw_data *);
240 static void nsp32_prom_start (nsp32_hw_data *);
241 static void nsp32_prom_stop (nsp32_hw_data *);
242 static int nsp32_prom_read (nsp32_hw_data *, int);
243 static int nsp32_prom_read_bit (nsp32_hw_data *);
244 static void nsp32_prom_write_bit(nsp32_hw_data *, int);
245 static void nsp32_prom_set (nsp32_hw_data *, int, int);
246 static int nsp32_prom_get (nsp32_hw_data *, int);
247
248 /* debug/warning/info message */
249 static void nsp32_message (const char *, int, char *, char *, ...);
250 #ifdef NSP32_DEBUG
251 static void nsp32_dmessage(const char *, int, int, char *, ...);
252 #endif
253
254 /*
255 * max_sectors is currently limited up to 128.
256 */
257 static struct scsi_host_template nsp32_template = {
258 .proc_name = "nsp32",
259 .name = "Workbit NinjaSCSI-32Bi/UDE",
260 .show_info = nsp32_show_info,
261 .info = nsp32_info,
262 .queuecommand = nsp32_queuecommand,
263 .can_queue = 1,
264 .sg_tablesize = NSP32_SG_SIZE,
265 .max_sectors = 128,
266 .this_id = NSP32_HOST_SCSIID,
267 .dma_boundary = PAGE_SIZE - 1,
268 .eh_abort_handler = nsp32_eh_abort,
269 .eh_host_reset_handler = nsp32_eh_host_reset,
270 /* .highmem_io = 1, */
271 };
272
273 #include "nsp32_io.h"
274
275 /***********************************************************************
276 * debug, error print
277 */
278 #ifndef NSP32_DEBUG
279 # define NSP32_DEBUG_MASK 0x000000
280 # define nsp32_msg(type, args...) nsp32_message ("", 0, (type), args)
281 # define nsp32_dbg(mask, args...) /* */
282 #else
283 # define NSP32_DEBUG_MASK 0xffffff
284 # define nsp32_msg(type, args...) \
285 nsp32_message (__func__, __LINE__, (type), args)
286 # define nsp32_dbg(mask, args...) \
287 nsp32_dmessage(__func__, __LINE__, (mask), args)
288 #endif
289
290 #define NSP32_DEBUG_QUEUECOMMAND BIT(0)
291 #define NSP32_DEBUG_REGISTER BIT(1)
292 #define NSP32_DEBUG_AUTOSCSI BIT(2)
293 #define NSP32_DEBUG_INTR BIT(3)
294 #define NSP32_DEBUG_SGLIST BIT(4)
295 #define NSP32_DEBUG_BUSFREE BIT(5)
296 #define NSP32_DEBUG_CDB_CONTENTS BIT(6)
297 #define NSP32_DEBUG_RESELECTION BIT(7)
298 #define NSP32_DEBUG_MSGINOCCUR BIT(8)
299 #define NSP32_DEBUG_EEPROM BIT(9)
300 #define NSP32_DEBUG_MSGOUTOCCUR BIT(10)
301 #define NSP32_DEBUG_BUSRESET BIT(11)
302 #define NSP32_DEBUG_RESTART BIT(12)
303 #define NSP32_DEBUG_SYNC BIT(13)
304 #define NSP32_DEBUG_WAIT BIT(14)
305 #define NSP32_DEBUG_TARGETFLAG BIT(15)
306 #define NSP32_DEBUG_PROC BIT(16)
307 #define NSP32_DEBUG_INIT BIT(17)
308 #define NSP32_SPECIAL_PRINT_REGISTER BIT(20)
309
310 #define NSP32_DEBUG_BUF_LEN 100
311
312 __printf(4, 5)
nsp32_message(const char * func,int line,char * type,char * fmt,...)313 static void nsp32_message(const char *func, int line, char *type, char *fmt, ...)
314 {
315 va_list args;
316 char buf[NSP32_DEBUG_BUF_LEN];
317
318 va_start(args, fmt);
319 vsnprintf(buf, sizeof(buf), fmt, args);
320 va_end(args);
321
322 #ifndef NSP32_DEBUG
323 printk("%snsp32: %s\n", type, buf);
324 #else
325 printk("%snsp32: %s (%d): %s\n", type, func, line, buf);
326 #endif
327 }
328
329 #ifdef NSP32_DEBUG
nsp32_dmessage(const char * func,int line,int mask,char * fmt,...)330 static void nsp32_dmessage(const char *func, int line, int mask, char *fmt, ...)
331 {
332 va_list args;
333 char buf[NSP32_DEBUG_BUF_LEN];
334
335 va_start(args, fmt);
336 vsnprintf(buf, sizeof(buf), fmt, args);
337 va_end(args);
338
339 if (mask & NSP32_DEBUG_MASK) {
340 printk("nsp32-debug: 0x%x %s (%d): %s\n", mask, func, line, buf);
341 }
342 }
343 #endif
344
345 #ifdef NSP32_DEBUG
346 # include "nsp32_debug.c"
347 #else
348 # define show_command(arg) /* */
349 # define show_busphase(arg) /* */
350 # define show_autophase(arg) /* */
351 #endif
352
353 /*
354 * IDENTIFY Message
355 */
nsp32_build_identify(struct scsi_cmnd * SCpnt)356 static void nsp32_build_identify(struct scsi_cmnd *SCpnt)
357 {
358 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
359 int pos = data->msgout_len;
360 int mode = FALSE;
361
362 /* XXX: Auto DiscPriv detection is progressing... */
363 if (disc_priv == 0) {
364 /* mode = TRUE; */
365 }
366
367 data->msgoutbuf[pos] = IDENTIFY(mode, SCpnt->device->lun); pos++;
368
369 data->msgout_len = pos;
370 }
371
372 /*
373 * SDTR Message Routine
374 */
nsp32_build_sdtr(struct scsi_cmnd * SCpnt,unsigned char period,unsigned char offset)375 static void nsp32_build_sdtr(struct scsi_cmnd *SCpnt,
376 unsigned char period,
377 unsigned char offset)
378 {
379 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
380 int pos = data->msgout_len;
381
382 data->msgoutbuf[pos] = EXTENDED_MESSAGE; pos++;
383 data->msgoutbuf[pos] = EXTENDED_SDTR_LEN; pos++;
384 data->msgoutbuf[pos] = EXTENDED_SDTR; pos++;
385 data->msgoutbuf[pos] = period; pos++;
386 data->msgoutbuf[pos] = offset; pos++;
387
388 data->msgout_len = pos;
389 }
390
391 /*
392 * No Operation Message
393 */
nsp32_build_nop(struct scsi_cmnd * SCpnt)394 static void nsp32_build_nop(struct scsi_cmnd *SCpnt)
395 {
396 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
397 int pos = data->msgout_len;
398
399 if (pos != 0) {
400 nsp32_msg(KERN_WARNING,
401 "Some messages are already contained!");
402 return;
403 }
404
405 data->msgoutbuf[pos] = NOP; pos++;
406 data->msgout_len = pos;
407 }
408
409 /*
410 * Reject Message
411 */
nsp32_build_reject(struct scsi_cmnd * SCpnt)412 static void nsp32_build_reject(struct scsi_cmnd *SCpnt)
413 {
414 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
415 int pos = data->msgout_len;
416
417 data->msgoutbuf[pos] = MESSAGE_REJECT; pos++;
418 data->msgout_len = pos;
419 }
420
421 /*
422 * timer
423 */
424 #if 0
425 static void nsp32_start_timer(struct scsi_cmnd *SCpnt, int time)
426 {
427 unsigned int base = SCpnt->host->io_port;
428
429 nsp32_dbg(NSP32_DEBUG_INTR, "timer=%d", time);
430
431 if (time & (~TIMER_CNT_MASK)) {
432 nsp32_dbg(NSP32_DEBUG_INTR, "timer set overflow");
433 }
434
435 nsp32_write2(base, TIMER_SET, time & TIMER_CNT_MASK);
436 }
437 #endif
438
439
440 /*
441 * set SCSI command and other parameter to asic, and start selection phase
442 */
nsp32_selection_autopara(struct scsi_cmnd * SCpnt)443 static int nsp32_selection_autopara(struct scsi_cmnd *SCpnt)
444 {
445 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
446 unsigned int base = SCpnt->device->host->io_port;
447 unsigned int host_id = SCpnt->device->host->this_id;
448 unsigned char target = scmd_id(SCpnt);
449 nsp32_autoparam *param = data->autoparam;
450 unsigned char phase;
451 int i, ret;
452 unsigned int msgout;
453 u16_le s;
454
455 nsp32_dbg(NSP32_DEBUG_AUTOSCSI, "in");
456
457 /*
458 * check bus free
459 */
460 phase = nsp32_read1(base, SCSI_BUS_MONITOR);
461 if (phase != BUSMON_BUS_FREE) {
462 nsp32_msg(KERN_WARNING, "bus busy");
463 show_busphase(phase & BUSMON_PHASE_MASK);
464 SCpnt->result = DID_BUS_BUSY << 16;
465 return FALSE;
466 }
467
468 /*
469 * message out
470 *
471 * Note: If the range of msgout_len is 1 - 3, fill scsi_msgout.
472 * over 3 messages needs another routine.
473 */
474 if (data->msgout_len == 0) {
475 nsp32_msg(KERN_ERR, "SCSI MsgOut without any message!");
476 SCpnt->result = DID_ERROR << 16;
477 return FALSE;
478 } else if (data->msgout_len > 0 && data->msgout_len <= 3) {
479 msgout = 0;
480 for (i = 0; i < data->msgout_len; i++) {
481 /*
482 * the sending order of the message is:
483 * MCNT 3: MSG#0 -> MSG#1 -> MSG#2
484 * MCNT 2: MSG#1 -> MSG#2
485 * MCNT 1: MSG#2
486 */
487 msgout >>= 8;
488 msgout |= ((unsigned int)(data->msgoutbuf[i]) << 24);
489 }
490 msgout |= MV_VALID; /* MV valid */
491 msgout |= (unsigned int)data->msgout_len; /* len */
492 } else {
493 /* data->msgout_len > 3 */
494 msgout = 0;
495 }
496
497 // nsp_dbg(NSP32_DEBUG_AUTOSCSI, "sel time out=0x%x\n", nsp32_read2(base, SEL_TIME_OUT));
498 // nsp32_write2(base, SEL_TIME_OUT, SEL_TIMEOUT_TIME);
499
500 /*
501 * setup asic parameter
502 */
503 memset(param, 0, sizeof(nsp32_autoparam));
504
505 /* cdb */
506 for (i = 0; i < SCpnt->cmd_len; i++) {
507 param->cdb[4 * i] = SCpnt->cmnd[i];
508 }
509
510 /* outgoing messages */
511 param->msgout = cpu_to_le32(msgout);
512
513 /* syncreg, ackwidth, target id, SREQ sampling rate */
514 param->syncreg = data->cur_target->syncreg;
515 param->ackwidth = data->cur_target->ackwidth;
516 param->target_id = BIT(host_id) | BIT(target);
517 param->sample_reg = data->cur_target->sample_reg;
518
519 // nsp32_dbg(NSP32_DEBUG_AUTOSCSI, "sample rate=0x%x\n", data->cur_target->sample_reg);
520
521 /* command control */
522 param->command_control = cpu_to_le16(CLEAR_CDB_FIFO_POINTER |
523 AUTOSCSI_START |
524 AUTO_MSGIN_00_OR_04 |
525 AUTO_MSGIN_02 |
526 AUTO_ATN );
527
528
529 /* transfer control */
530 s = 0;
531 switch (data->trans_method) {
532 case NSP32_TRANSFER_BUSMASTER:
533 s |= BM_START;
534 break;
535 case NSP32_TRANSFER_MMIO:
536 s |= CB_MMIO_MODE;
537 break;
538 case NSP32_TRANSFER_PIO:
539 s |= CB_IO_MODE;
540 break;
541 default:
542 nsp32_msg(KERN_ERR, "unknown trans_method");
543 break;
544 }
545 /*
546 * OR-ed BLIEND_MODE, FIFO intr is decreased, instead of PCI bus waits.
547 * For bus master transfer, it's taken off.
548 */
549 s |= (TRANSFER_GO | ALL_COUNTER_CLR);
550 param->transfer_control = cpu_to_le16(s);
551
552 /* sg table addr */
553 param->sgt_pointer = cpu_to_le32(data->cur_lunt->sglun_paddr);
554
555 /*
556 * transfer parameter to ASIC
557 */
558 nsp32_write4(base, SGT_ADR, data->auto_paddr);
559 nsp32_write2(base, COMMAND_CONTROL, CLEAR_CDB_FIFO_POINTER |
560 AUTO_PARAMETER );
561
562 /*
563 * Check arbitration
564 */
565 ret = nsp32_arbitration(SCpnt, base);
566
567 return ret;
568 }
569
570
571 /*
572 * Selection with AUTO SCSI (without AUTO PARAMETER)
573 */
nsp32_selection_autoscsi(struct scsi_cmnd * SCpnt)574 static int nsp32_selection_autoscsi(struct scsi_cmnd *SCpnt)
575 {
576 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
577 unsigned int base = SCpnt->device->host->io_port;
578 unsigned int host_id = SCpnt->device->host->this_id;
579 unsigned char target = scmd_id(SCpnt);
580 unsigned char phase;
581 int status;
582 unsigned short command = 0;
583 unsigned int msgout = 0;
584 int i;
585
586 nsp32_dbg(NSP32_DEBUG_AUTOSCSI, "in");
587
588 /*
589 * IRQ disable
590 */
591 nsp32_write2(base, IRQ_CONTROL, IRQ_CONTROL_ALL_IRQ_MASK);
592
593 /*
594 * check bus line
595 */
596 phase = nsp32_read1(base, SCSI_BUS_MONITOR);
597 if ((phase & BUSMON_BSY) || (phase & BUSMON_SEL)) {
598 nsp32_msg(KERN_WARNING, "bus busy");
599 SCpnt->result = DID_BUS_BUSY << 16;
600 status = 1;
601 goto out;
602 }
603
604 /*
605 * clear execph
606 */
607 nsp32_read2(base, SCSI_EXECUTE_PHASE);
608
609 /*
610 * clear FIFO counter to set CDBs
611 */
612 nsp32_write2(base, COMMAND_CONTROL, CLEAR_CDB_FIFO_POINTER);
613
614 /*
615 * set CDB0 - CDB15
616 */
617 for (i = 0; i < SCpnt->cmd_len; i++) {
618 nsp32_write1(base, COMMAND_DATA, SCpnt->cmnd[i]);
619 }
620 nsp32_dbg(NSP32_DEBUG_CDB_CONTENTS, "CDB[0]=[0x%x]", SCpnt->cmnd[0]);
621
622 /*
623 * set SCSIOUT LATCH(initiator)/TARGET(target) (OR-ed) ID
624 */
625 nsp32_write1(base, SCSI_OUT_LATCH_TARGET_ID, BIT(host_id) | BIT(target));
626
627 /*
628 * set SCSI MSGOUT REG
629 *
630 * Note: If the range of msgout_len is 1 - 3, fill scsi_msgout.
631 * over 3 messages needs another routine.
632 */
633 if (data->msgout_len == 0) {
634 nsp32_msg(KERN_ERR, "SCSI MsgOut without any message!");
635 SCpnt->result = DID_ERROR << 16;
636 status = 1;
637 goto out;
638 } else if (data->msgout_len > 0 && data->msgout_len <= 3) {
639 msgout = 0;
640 for (i = 0; i < data->msgout_len; i++) {
641 /*
642 * the sending order of the message is:
643 * MCNT 3: MSG#0 -> MSG#1 -> MSG#2
644 * MCNT 2: MSG#1 -> MSG#2
645 * MCNT 1: MSG#2
646 */
647 msgout >>= 8;
648 msgout |= ((unsigned int)(data->msgoutbuf[i]) << 24);
649 }
650 msgout |= MV_VALID; /* MV valid */
651 msgout |= (unsigned int)data->msgout_len; /* len */
652 nsp32_write4(base, SCSI_MSG_OUT, msgout);
653 } else {
654 /* data->msgout_len > 3 */
655 nsp32_write4(base, SCSI_MSG_OUT, 0);
656 }
657
658 /*
659 * set selection timeout(= 250ms)
660 */
661 nsp32_write2(base, SEL_TIME_OUT, SEL_TIMEOUT_TIME);
662
663 /*
664 * set SREQ hazard killer sampling rate
665 *
666 * TODO: sample_rate (BASE+0F) is 0 when internal clock = 40MHz.
667 * check other internal clock!
668 */
669 nsp32_write1(base, SREQ_SMPL_RATE, data->cur_target->sample_reg);
670
671 /*
672 * clear Arbit
673 */
674 nsp32_write1(base, SET_ARBIT, ARBIT_CLEAR);
675
676 /*
677 * set SYNCREG
678 * Don't set BM_START_ADR before setting this register.
679 */
680 nsp32_write1(base, SYNC_REG, data->cur_target->syncreg);
681
682 /*
683 * set ACKWIDTH
684 */
685 nsp32_write1(base, ACK_WIDTH, data->cur_target->ackwidth);
686
687 nsp32_dbg(NSP32_DEBUG_AUTOSCSI,
688 "syncreg=0x%x, ackwidth=0x%x, sgtpaddr=0x%x, id=0x%x",
689 nsp32_read1(base, SYNC_REG), nsp32_read1(base, ACK_WIDTH),
690 nsp32_read4(base, SGT_ADR), nsp32_read1(base, SCSI_OUT_LATCH_TARGET_ID));
691 nsp32_dbg(NSP32_DEBUG_AUTOSCSI, "msgout_len=%d, msgout=0x%x",
692 data->msgout_len, msgout);
693
694 /*
695 * set SGT ADDR (physical address)
696 */
697 nsp32_write4(base, SGT_ADR, data->cur_lunt->sglun_paddr);
698
699 /*
700 * set TRANSFER CONTROL REG
701 */
702 command = 0;
703 command |= (TRANSFER_GO | ALL_COUNTER_CLR);
704 if (data->trans_method & NSP32_TRANSFER_BUSMASTER) {
705 if (scsi_bufflen(SCpnt) > 0) {
706 command |= BM_START;
707 }
708 } else if (data->trans_method & NSP32_TRANSFER_MMIO) {
709 command |= CB_MMIO_MODE;
710 } else if (data->trans_method & NSP32_TRANSFER_PIO) {
711 command |= CB_IO_MODE;
712 }
713 nsp32_write2(base, TRANSFER_CONTROL, command);
714
715 /*
716 * start AUTO SCSI, kick off arbitration
717 */
718 command = (CLEAR_CDB_FIFO_POINTER |
719 AUTOSCSI_START |
720 AUTO_MSGIN_00_OR_04 |
721 AUTO_MSGIN_02 |
722 AUTO_ATN );
723 nsp32_write2(base, COMMAND_CONTROL, command);
724
725 /*
726 * Check arbitration
727 */
728 status = nsp32_arbitration(SCpnt, base);
729
730 out:
731 /*
732 * IRQ enable
733 */
734 nsp32_write2(base, IRQ_CONTROL, 0);
735
736 return status;
737 }
738
739
740 /*
741 * Arbitration Status Check
742 *
743 * Note: Arbitration counter is waited during ARBIT_GO is not lifting.
744 * Using udelay(1) consumes CPU time and system time, but
745 * arbitration delay time is defined minimal 2.4us in SCSI
746 * specification, thus udelay works as coarse grained wait timer.
747 */
nsp32_arbitration(struct scsi_cmnd * SCpnt,unsigned int base)748 static int nsp32_arbitration(struct scsi_cmnd *SCpnt, unsigned int base)
749 {
750 unsigned char arbit;
751 int status = TRUE;
752 int time = 0;
753
754 do {
755 arbit = nsp32_read1(base, ARBIT_STATUS);
756 time++;
757 } while ((arbit & (ARBIT_WIN | ARBIT_FAIL)) == 0 &&
758 (time <= ARBIT_TIMEOUT_TIME));
759
760 nsp32_dbg(NSP32_DEBUG_AUTOSCSI,
761 "arbit: 0x%x, delay time: %d", arbit, time);
762
763 if (arbit & ARBIT_WIN) {
764 /* Arbitration succeeded */
765 SCpnt->result = DID_OK << 16;
766 nsp32_index_write1(base, EXT_PORT, LED_ON); /* PCI LED on */
767 } else if (arbit & ARBIT_FAIL) {
768 /* Arbitration failed */
769 SCpnt->result = DID_BUS_BUSY << 16;
770 status = FALSE;
771 } else {
772 /*
773 * unknown error or ARBIT_GO timeout,
774 * something lock up! guess no connection.
775 */
776 nsp32_dbg(NSP32_DEBUG_AUTOSCSI, "arbit timeout");
777 SCpnt->result = DID_NO_CONNECT << 16;
778 status = FALSE;
779 }
780
781 /*
782 * clear Arbit
783 */
784 nsp32_write1(base, SET_ARBIT, ARBIT_CLEAR);
785
786 return status;
787 }
788
789
790 /*
791 * reselection
792 *
793 * Note: This reselection routine is called from msgin_occur,
794 * reselection target id&lun must be already set.
795 * SCSI-2 says IDENTIFY implies RESTORE_POINTER operation.
796 */
nsp32_reselection(struct scsi_cmnd * SCpnt,unsigned char newlun)797 static int nsp32_reselection(struct scsi_cmnd *SCpnt, unsigned char newlun)
798 {
799 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
800 unsigned int host_id = SCpnt->device->host->this_id;
801 unsigned int base = SCpnt->device->host->io_port;
802 unsigned char tmpid, newid;
803
804 nsp32_dbg(NSP32_DEBUG_RESELECTION, "enter");
805
806 /*
807 * calculate reselected SCSI ID
808 */
809 tmpid = nsp32_read1(base, RESELECT_ID);
810 tmpid &= (~BIT(host_id));
811 newid = 0;
812 while (tmpid) {
813 if (tmpid & 1) {
814 break;
815 }
816 tmpid >>= 1;
817 newid++;
818 }
819
820 /*
821 * If reselected New ID:LUN is not existed
822 * or current nexus is not existed, unexpected
823 * reselection is occurred. Send reject message.
824 */
825 if (newid >= ARRAY_SIZE(data->lunt) || newlun >= ARRAY_SIZE(data->lunt[0])) {
826 nsp32_msg(KERN_WARNING, "unknown id/lun");
827 return FALSE;
828 } else if(data->lunt[newid][newlun].SCpnt == NULL) {
829 nsp32_msg(KERN_WARNING, "no SCSI command is processing");
830 return FALSE;
831 }
832
833 data->cur_id = newid;
834 data->cur_lun = newlun;
835 data->cur_target = &(data->target[newid]);
836 data->cur_lunt = &(data->lunt[newid][newlun]);
837
838 /* reset SACK/SavedACK counter (or ALL clear?) */
839 nsp32_write4(base, CLR_COUNTER, CLRCOUNTER_ALLMASK);
840
841 return TRUE;
842 }
843
844
845 /*
846 * nsp32_setup_sg_table - build scatter gather list for transfer data
847 * with bus master.
848 *
849 * Note: NinjaSCSI-32Bi/UDE bus master can not transfer over 64KB at a time.
850 */
nsp32_setup_sg_table(struct scsi_cmnd * SCpnt)851 static int nsp32_setup_sg_table(struct scsi_cmnd *SCpnt)
852 {
853 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
854 struct scatterlist *sg;
855 nsp32_sgtable *sgt = data->cur_lunt->sglun->sgt;
856 int num, i;
857 u32_le l;
858
859 if (sgt == NULL) {
860 nsp32_dbg(NSP32_DEBUG_SGLIST, "SGT == null");
861 return FALSE;
862 }
863
864 num = scsi_dma_map(SCpnt);
865 if (!num)
866 return TRUE;
867 else if (num < 0)
868 return FALSE;
869 else {
870 scsi_for_each_sg(SCpnt, sg, num, i) {
871 /*
872 * Build nsp32_sglist, substitute sg dma addresses.
873 */
874 sgt[i].addr = cpu_to_le32(sg_dma_address(sg));
875 sgt[i].len = cpu_to_le32(sg_dma_len(sg));
876
877 if (le32_to_cpu(sgt[i].len) > 0x10000) {
878 nsp32_msg(KERN_ERR,
879 "can't transfer over 64KB at a time, size=0x%x", le32_to_cpu(sgt[i].len));
880 return FALSE;
881 }
882 nsp32_dbg(NSP32_DEBUG_SGLIST,
883 "num 0x%x : addr 0x%lx len 0x%lx",
884 i,
885 le32_to_cpu(sgt[i].addr),
886 le32_to_cpu(sgt[i].len ));
887 }
888
889 /* set end mark */
890 l = le32_to_cpu(sgt[num-1].len);
891 sgt[num-1].len = cpu_to_le32(l | SGTEND);
892 }
893
894 return TRUE;
895 }
896
nsp32_queuecommand_lck(struct scsi_cmnd * SCpnt,void (* done)(struct scsi_cmnd *))897 static int nsp32_queuecommand_lck(struct scsi_cmnd *SCpnt, void (*done)(struct scsi_cmnd *))
898 {
899 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
900 nsp32_target *target;
901 nsp32_lunt *cur_lunt;
902 int ret;
903
904 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND,
905 "enter. target: 0x%x LUN: 0x%llx cmnd: 0x%x cmndlen: 0x%x "
906 "use_sg: 0x%x reqbuf: 0x%lx reqlen: 0x%x",
907 SCpnt->device->id, SCpnt->device->lun, SCpnt->cmnd[0], SCpnt->cmd_len,
908 scsi_sg_count(SCpnt), scsi_sglist(SCpnt), scsi_bufflen(SCpnt));
909
910 if (data->CurrentSC != NULL) {
911 nsp32_msg(KERN_ERR, "Currentsc != NULL. Cancel this command request");
912 data->CurrentSC = NULL;
913 SCpnt->result = DID_NO_CONNECT << 16;
914 done(SCpnt);
915 return 0;
916 }
917
918 /* check target ID is not same as this initiator ID */
919 if (scmd_id(SCpnt) == SCpnt->device->host->this_id) {
920 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND, "target==host???");
921 SCpnt->result = DID_BAD_TARGET << 16;
922 done(SCpnt);
923 return 0;
924 }
925
926 /* check target LUN is allowable value */
927 if (SCpnt->device->lun >= MAX_LUN) {
928 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND, "no more lun");
929 SCpnt->result = DID_BAD_TARGET << 16;
930 done(SCpnt);
931 return 0;
932 }
933
934 show_command(SCpnt);
935
936 SCpnt->scsi_done = done;
937 data->CurrentSC = SCpnt;
938 SCpnt->SCp.Status = SAM_STAT_CHECK_CONDITION;
939 SCpnt->SCp.Message = 0;
940 scsi_set_resid(SCpnt, scsi_bufflen(SCpnt));
941
942 SCpnt->SCp.ptr = (char *)scsi_sglist(SCpnt);
943 SCpnt->SCp.this_residual = scsi_bufflen(SCpnt);
944 SCpnt->SCp.buffer = NULL;
945 SCpnt->SCp.buffers_residual = 0;
946
947 /* initialize data */
948 data->msgout_len = 0;
949 data->msgin_len = 0;
950 cur_lunt = &(data->lunt[SCpnt->device->id][SCpnt->device->lun]);
951 cur_lunt->SCpnt = SCpnt;
952 cur_lunt->save_datp = 0;
953 cur_lunt->msgin03 = FALSE;
954 data->cur_lunt = cur_lunt;
955 data->cur_id = SCpnt->device->id;
956 data->cur_lun = SCpnt->device->lun;
957
958 ret = nsp32_setup_sg_table(SCpnt);
959 if (ret == FALSE) {
960 nsp32_msg(KERN_ERR, "SGT fail");
961 SCpnt->result = DID_ERROR << 16;
962 nsp32_scsi_done(SCpnt);
963 return 0;
964 }
965
966 /* Build IDENTIFY */
967 nsp32_build_identify(SCpnt);
968
969 /*
970 * If target is the first time to transfer after the reset
971 * (target don't have SDTR_DONE and SDTR_INITIATOR), sync
972 * message SDTR is needed to do synchronous transfer.
973 */
974 target = &data->target[scmd_id(SCpnt)];
975 data->cur_target = target;
976
977 if (!(target->sync_flag & (SDTR_DONE | SDTR_INITIATOR | SDTR_TARGET))) {
978 unsigned char period, offset;
979
980 if (trans_mode != ASYNC_MODE) {
981 nsp32_set_max_sync(data, target, &period, &offset);
982 nsp32_build_sdtr(SCpnt, period, offset);
983 target->sync_flag |= SDTR_INITIATOR;
984 } else {
985 nsp32_set_async(data, target);
986 target->sync_flag |= SDTR_DONE;
987 }
988
989 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND,
990 "SDTR: entry: %d start_period: 0x%x offset: 0x%x\n",
991 target->limit_entry, period, offset);
992 } else if (target->sync_flag & SDTR_INITIATOR) {
993 /*
994 * It was negotiating SDTR with target, sending from the
995 * initiator, but there are no chance to remove this flag.
996 * Set async because we don't get proper negotiation.
997 */
998 nsp32_set_async(data, target);
999 target->sync_flag &= ~SDTR_INITIATOR;
1000 target->sync_flag |= SDTR_DONE;
1001
1002 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND,
1003 "SDTR_INITIATOR: fall back to async");
1004 } else if (target->sync_flag & SDTR_TARGET) {
1005 /*
1006 * It was negotiating SDTR with target, sending from target,
1007 * but there are no chance to remove this flag. Set async
1008 * because we don't get proper negotiation.
1009 */
1010 nsp32_set_async(data, target);
1011 target->sync_flag &= ~SDTR_TARGET;
1012 target->sync_flag |= SDTR_DONE;
1013
1014 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND,
1015 "Unknown SDTR from target is reached, fall back to async.");
1016 }
1017
1018 nsp32_dbg(NSP32_DEBUG_TARGETFLAG,
1019 "target: %d sync_flag: 0x%x syncreg: 0x%x ackwidth: 0x%x",
1020 SCpnt->device->id, target->sync_flag, target->syncreg,
1021 target->ackwidth);
1022
1023 /* Selection */
1024 if (auto_param == 0) {
1025 ret = nsp32_selection_autopara(SCpnt);
1026 } else {
1027 ret = nsp32_selection_autoscsi(SCpnt);
1028 }
1029
1030 if (ret != TRUE) {
1031 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND, "selection fail");
1032 nsp32_scsi_done(SCpnt);
1033 }
1034
1035 return 0;
1036 }
1037
DEF_SCSI_QCMD(nsp32_queuecommand)1038 static DEF_SCSI_QCMD(nsp32_queuecommand)
1039
1040 /* initialize asic */
1041 static int nsp32hw_init(nsp32_hw_data *data)
1042 {
1043 unsigned int base = data->BaseAddress;
1044 unsigned short irq_stat;
1045 unsigned long lc_reg;
1046 unsigned char power;
1047
1048 lc_reg = nsp32_index_read4(base, CFG_LATE_CACHE);
1049 if ((lc_reg & 0xff00) == 0) {
1050 lc_reg |= (0x20 << 8);
1051 nsp32_index_write2(base, CFG_LATE_CACHE, lc_reg & 0xffff);
1052 }
1053
1054 nsp32_write2(base, IRQ_CONTROL, IRQ_CONTROL_ALL_IRQ_MASK);
1055 nsp32_write2(base, TRANSFER_CONTROL, 0);
1056 nsp32_write4(base, BM_CNT, 0);
1057 nsp32_write2(base, SCSI_EXECUTE_PHASE, 0);
1058
1059 do {
1060 irq_stat = nsp32_read2(base, IRQ_STATUS);
1061 nsp32_dbg(NSP32_DEBUG_INIT, "irq_stat 0x%x", irq_stat);
1062 } while (irq_stat & IRQSTATUS_ANY_IRQ);
1063
1064 /*
1065 * Fill FIFO_FULL_SHLD, FIFO_EMPTY_SHLD. Below parameter is
1066 * designated by specification.
1067 */
1068 if ((data->trans_method & NSP32_TRANSFER_PIO) ||
1069 (data->trans_method & NSP32_TRANSFER_MMIO)) {
1070 nsp32_index_write1(base, FIFO_FULL_SHLD_COUNT, 0x40);
1071 nsp32_index_write1(base, FIFO_EMPTY_SHLD_COUNT, 0x40);
1072 } else if (data->trans_method & NSP32_TRANSFER_BUSMASTER) {
1073 nsp32_index_write1(base, FIFO_FULL_SHLD_COUNT, 0x10);
1074 nsp32_index_write1(base, FIFO_EMPTY_SHLD_COUNT, 0x60);
1075 } else {
1076 nsp32_dbg(NSP32_DEBUG_INIT, "unknown transfer mode");
1077 }
1078
1079 nsp32_dbg(NSP32_DEBUG_INIT, "full 0x%x emp 0x%x",
1080 nsp32_index_read1(base, FIFO_FULL_SHLD_COUNT),
1081 nsp32_index_read1(base, FIFO_EMPTY_SHLD_COUNT));
1082
1083 nsp32_index_write1(base, CLOCK_DIV, data->clock);
1084 nsp32_index_write1(base, BM_CYCLE, MEMRD_CMD1 | SGT_AUTO_PARA_MEMED_CMD);
1085 nsp32_write1(base, PARITY_CONTROL, 0); /* parity check is disable */
1086
1087 /*
1088 * initialize MISC_WRRD register
1089 *
1090 * Note: Designated parameters is obeyed as following:
1091 * MISC_SCSI_DIRECTION_DETECTOR_SELECT: It must be set.
1092 * MISC_MASTER_TERMINATION_SELECT: It must be set.
1093 * MISC_BMREQ_NEGATE_TIMING_SEL: It should be set.
1094 * MISC_AUTOSEL_TIMING_SEL: It should be set.
1095 * MISC_BMSTOP_CHANGE2_NONDATA_PHASE: It should be set.
1096 * MISC_DELAYED_BMSTART: It's selected for safety.
1097 *
1098 * Note: If MISC_BMSTOP_CHANGE2_NONDATA_PHASE is set, then
1099 * we have to set TRANSFERCONTROL_BM_START as 0 and set
1100 * appropriate value before restarting bus master transfer.
1101 */
1102 nsp32_index_write2(base, MISC_WR,
1103 (SCSI_DIRECTION_DETECTOR_SELECT |
1104 DELAYED_BMSTART |
1105 MASTER_TERMINATION_SELECT |
1106 BMREQ_NEGATE_TIMING_SEL |
1107 AUTOSEL_TIMING_SEL |
1108 BMSTOP_CHANGE2_NONDATA_PHASE));
1109
1110 nsp32_index_write1(base, TERM_PWR_CONTROL, 0);
1111 power = nsp32_index_read1(base, TERM_PWR_CONTROL);
1112 if (!(power & SENSE)) {
1113 nsp32_msg(KERN_INFO, "term power on");
1114 nsp32_index_write1(base, TERM_PWR_CONTROL, BPWR);
1115 }
1116
1117 nsp32_write2(base, TIMER_SET, TIMER_STOP);
1118 nsp32_write2(base, TIMER_SET, TIMER_STOP); /* Required 2 times */
1119
1120 nsp32_write1(base, SYNC_REG, 0);
1121 nsp32_write1(base, ACK_WIDTH, 0);
1122 nsp32_write2(base, SEL_TIME_OUT, SEL_TIMEOUT_TIME);
1123
1124 /*
1125 * enable to select designated IRQ (except for
1126 * IRQSELECT_SERR, IRQSELECT_PERR, IRQSELECT_BMCNTERR)
1127 */
1128 nsp32_index_write2(base, IRQ_SELECT, IRQSELECT_TIMER_IRQ |
1129 IRQSELECT_SCSIRESET_IRQ |
1130 IRQSELECT_FIFO_SHLD_IRQ |
1131 IRQSELECT_RESELECT_IRQ |
1132 IRQSELECT_PHASE_CHANGE_IRQ |
1133 IRQSELECT_AUTO_SCSI_SEQ_IRQ |
1134 // IRQSELECT_BMCNTERR_IRQ |
1135 IRQSELECT_TARGET_ABORT_IRQ |
1136 IRQSELECT_MASTER_ABORT_IRQ );
1137 nsp32_write2(base, IRQ_CONTROL, 0);
1138
1139 /* PCI LED off */
1140 nsp32_index_write1(base, EXT_PORT_DDR, LED_OFF);
1141 nsp32_index_write1(base, EXT_PORT, LED_OFF);
1142
1143 return TRUE;
1144 }
1145
1146
1147 /* interrupt routine */
do_nsp32_isr(int irq,void * dev_id)1148 static irqreturn_t do_nsp32_isr(int irq, void *dev_id)
1149 {
1150 nsp32_hw_data *data = dev_id;
1151 unsigned int base = data->BaseAddress;
1152 struct scsi_cmnd *SCpnt = data->CurrentSC;
1153 unsigned short auto_stat, irq_stat, trans_stat;
1154 unsigned char busmon, busphase;
1155 unsigned long flags;
1156 int ret;
1157 int handled = 0;
1158 struct Scsi_Host *host = data->Host;
1159
1160 spin_lock_irqsave(host->host_lock, flags);
1161
1162 /*
1163 * IRQ check, then enable IRQ mask
1164 */
1165 irq_stat = nsp32_read2(base, IRQ_STATUS);
1166 nsp32_dbg(NSP32_DEBUG_INTR,
1167 "enter IRQ: %d, IRQstatus: 0x%x", irq, irq_stat);
1168 /* is this interrupt comes from Ninja asic? */
1169 if ((irq_stat & IRQSTATUS_ANY_IRQ) == 0) {
1170 nsp32_dbg(NSP32_DEBUG_INTR, "shared interrupt: irq other 0x%x", irq_stat);
1171 goto out2;
1172 }
1173 handled = 1;
1174 nsp32_write2(base, IRQ_CONTROL, IRQ_CONTROL_ALL_IRQ_MASK);
1175
1176 busmon = nsp32_read1(base, SCSI_BUS_MONITOR);
1177 busphase = busmon & BUSMON_PHASE_MASK;
1178
1179 trans_stat = nsp32_read2(base, TRANSFER_STATUS);
1180 if ((irq_stat == 0xffff) && (trans_stat == 0xffff)) {
1181 nsp32_msg(KERN_INFO, "card disconnect");
1182 if (data->CurrentSC != NULL) {
1183 nsp32_msg(KERN_INFO, "clean up current SCSI command");
1184 SCpnt->result = DID_BAD_TARGET << 16;
1185 nsp32_scsi_done(SCpnt);
1186 }
1187 goto out;
1188 }
1189
1190 /* Timer IRQ */
1191 if (irq_stat & IRQSTATUS_TIMER_IRQ) {
1192 nsp32_dbg(NSP32_DEBUG_INTR, "timer stop");
1193 nsp32_write2(base, TIMER_SET, TIMER_STOP);
1194 goto out;
1195 }
1196
1197 /* SCSI reset */
1198 if (irq_stat & IRQSTATUS_SCSIRESET_IRQ) {
1199 nsp32_msg(KERN_INFO, "detected someone do bus reset");
1200 nsp32_do_bus_reset(data);
1201 if (SCpnt != NULL) {
1202 SCpnt->result = DID_RESET << 16;
1203 nsp32_scsi_done(SCpnt);
1204 }
1205 goto out;
1206 }
1207
1208 if (SCpnt == NULL) {
1209 nsp32_msg(KERN_WARNING, "SCpnt==NULL this can't be happened");
1210 nsp32_msg(KERN_WARNING, "irq_stat=0x%x trans_stat=0x%x", irq_stat, trans_stat);
1211 goto out;
1212 }
1213
1214 /*
1215 * AutoSCSI Interrupt.
1216 * Note: This interrupt is occurred when AutoSCSI is finished. Then
1217 * check SCSIEXECUTEPHASE, and do appropriate action. Each phases are
1218 * recorded when AutoSCSI sequencer has been processed.
1219 */
1220 if(irq_stat & IRQSTATUS_AUTOSCSI_IRQ) {
1221 /* getting SCSI executed phase */
1222 auto_stat = nsp32_read2(base, SCSI_EXECUTE_PHASE);
1223 nsp32_write2(base, SCSI_EXECUTE_PHASE, 0);
1224
1225 /* Selection Timeout, go busfree phase. */
1226 if (auto_stat & SELECTION_TIMEOUT) {
1227 nsp32_dbg(NSP32_DEBUG_INTR,
1228 "selection timeout occurred");
1229
1230 SCpnt->result = DID_TIME_OUT << 16;
1231 nsp32_scsi_done(SCpnt);
1232 goto out;
1233 }
1234
1235 if (auto_stat & MSGOUT_PHASE) {
1236 /*
1237 * MsgOut phase was processed.
1238 * If MSG_IN_OCCUER is not set, then MsgOut phase is
1239 * completed. Thus, msgout_len must reset. Otherwise,
1240 * nothing to do here. If MSG_OUT_OCCUER is occurred,
1241 * then we will encounter the condition and check.
1242 */
1243 if (!(auto_stat & MSG_IN_OCCUER) &&
1244 (data->msgout_len <= 3)) {
1245 /*
1246 * !MSG_IN_OCCUER && msgout_len <=3
1247 * ---> AutoSCSI with MSGOUTreg is processed.
1248 */
1249 data->msgout_len = 0;
1250 }
1251
1252 nsp32_dbg(NSP32_DEBUG_INTR, "MsgOut phase processed");
1253 }
1254
1255 if ((auto_stat & DATA_IN_PHASE) &&
1256 (scsi_get_resid(SCpnt) > 0) &&
1257 ((nsp32_read2(base, FIFO_REST_CNT) & FIFO_REST_MASK) != 0)) {
1258 printk( "auto+fifo\n");
1259 //nsp32_pio_read(SCpnt);
1260 }
1261
1262 if (auto_stat & (DATA_IN_PHASE | DATA_OUT_PHASE)) {
1263 /* DATA_IN_PHASE/DATA_OUT_PHASE was processed. */
1264 nsp32_dbg(NSP32_DEBUG_INTR,
1265 "Data in/out phase processed");
1266
1267 /* read BMCNT, SGT pointer addr */
1268 nsp32_dbg(NSP32_DEBUG_INTR, "BMCNT=0x%lx",
1269 nsp32_read4(base, BM_CNT));
1270 nsp32_dbg(NSP32_DEBUG_INTR, "addr=0x%lx",
1271 nsp32_read4(base, SGT_ADR));
1272 nsp32_dbg(NSP32_DEBUG_INTR, "SACK=0x%lx",
1273 nsp32_read4(base, SACK_CNT));
1274 nsp32_dbg(NSP32_DEBUG_INTR, "SSACK=0x%lx",
1275 nsp32_read4(base, SAVED_SACK_CNT));
1276
1277 scsi_set_resid(SCpnt, 0); /* all data transferred! */
1278 }
1279
1280 /*
1281 * MsgIn Occur
1282 */
1283 if (auto_stat & MSG_IN_OCCUER) {
1284 nsp32_msgin_occur(SCpnt, irq_stat, auto_stat);
1285 }
1286
1287 /*
1288 * MsgOut Occur
1289 */
1290 if (auto_stat & MSG_OUT_OCCUER) {
1291 nsp32_msgout_occur(SCpnt);
1292 }
1293
1294 /*
1295 * Bus Free Occur
1296 */
1297 if (auto_stat & BUS_FREE_OCCUER) {
1298 ret = nsp32_busfree_occur(SCpnt, auto_stat);
1299 if (ret == TRUE) {
1300 goto out;
1301 }
1302 }
1303
1304 if (auto_stat & STATUS_PHASE) {
1305 /*
1306 * Read CSB and substitute CSB for SCpnt->result
1307 * to save status phase stutas byte.
1308 * scsi error handler checks host_byte (DID_*:
1309 * low level driver to indicate status), then checks
1310 * status_byte (SCSI status byte).
1311 */
1312 SCpnt->result = (int)nsp32_read1(base, SCSI_CSB_IN);
1313 }
1314
1315 if (auto_stat & ILLEGAL_PHASE) {
1316 /* Illegal phase is detected. SACK is not back. */
1317 nsp32_msg(KERN_WARNING,
1318 "AUTO SCSI ILLEGAL PHASE OCCUR!!!!");
1319
1320 /* TODO: currently we don't have any action... bus reset? */
1321
1322 /*
1323 * To send back SACK, assert, wait, and negate.
1324 */
1325 nsp32_sack_assert(data);
1326 nsp32_wait_req(data, NEGATE);
1327 nsp32_sack_negate(data);
1328
1329 }
1330
1331 if (auto_stat & COMMAND_PHASE) {
1332 /* nothing to do */
1333 nsp32_dbg(NSP32_DEBUG_INTR, "Command phase processed");
1334 }
1335
1336 if (auto_stat & AUTOSCSI_BUSY) {
1337 /* AutoSCSI is running */
1338 }
1339
1340 show_autophase(auto_stat);
1341 }
1342
1343 /* FIFO_SHLD_IRQ */
1344 if (irq_stat & IRQSTATUS_FIFO_SHLD_IRQ) {
1345 nsp32_dbg(NSP32_DEBUG_INTR, "FIFO IRQ");
1346
1347 switch(busphase) {
1348 case BUSPHASE_DATA_OUT:
1349 nsp32_dbg(NSP32_DEBUG_INTR, "fifo/write");
1350
1351 //nsp32_pio_write(SCpnt);
1352
1353 break;
1354
1355 case BUSPHASE_DATA_IN:
1356 nsp32_dbg(NSP32_DEBUG_INTR, "fifo/read");
1357
1358 //nsp32_pio_read(SCpnt);
1359
1360 break;
1361
1362 case BUSPHASE_STATUS:
1363 nsp32_dbg(NSP32_DEBUG_INTR, "fifo/status");
1364
1365 SCpnt->SCp.Status = nsp32_read1(base, SCSI_CSB_IN);
1366
1367 break;
1368 default:
1369 nsp32_dbg(NSP32_DEBUG_INTR, "fifo/other phase");
1370 nsp32_dbg(NSP32_DEBUG_INTR, "irq_stat=0x%x trans_stat=0x%x", irq_stat, trans_stat);
1371 show_busphase(busphase);
1372 break;
1373 }
1374
1375 goto out;
1376 }
1377
1378 /* Phase Change IRQ */
1379 if (irq_stat & IRQSTATUS_PHASE_CHANGE_IRQ) {
1380 nsp32_dbg(NSP32_DEBUG_INTR, "phase change IRQ");
1381
1382 switch(busphase) {
1383 case BUSPHASE_MESSAGE_IN:
1384 nsp32_dbg(NSP32_DEBUG_INTR, "phase chg/msg in");
1385 nsp32_msgin_occur(SCpnt, irq_stat, 0);
1386 break;
1387 default:
1388 nsp32_msg(KERN_WARNING, "phase chg/other phase?");
1389 nsp32_msg(KERN_WARNING, "irq_stat=0x%x trans_stat=0x%x\n",
1390 irq_stat, trans_stat);
1391 show_busphase(busphase);
1392 break;
1393 }
1394 goto out;
1395 }
1396
1397 /* PCI_IRQ */
1398 if (irq_stat & IRQSTATUS_PCI_IRQ) {
1399 nsp32_dbg(NSP32_DEBUG_INTR, "PCI IRQ occurred");
1400 /* Do nothing */
1401 }
1402
1403 /* BMCNTERR_IRQ */
1404 if (irq_stat & IRQSTATUS_BMCNTERR_IRQ) {
1405 nsp32_msg(KERN_ERR, "Received unexpected BMCNTERR IRQ! ");
1406 /*
1407 * TODO: To be implemented improving bus master
1408 * transfer reliability when BMCNTERR is occurred in
1409 * AutoSCSI phase described in specification.
1410 */
1411 }
1412
1413 #if 0
1414 nsp32_dbg(NSP32_DEBUG_INTR,
1415 "irq_stat=0x%x trans_stat=0x%x", irq_stat, trans_stat);
1416 show_busphase(busphase);
1417 #endif
1418
1419 out:
1420 /* disable IRQ mask */
1421 nsp32_write2(base, IRQ_CONTROL, 0);
1422
1423 out2:
1424 spin_unlock_irqrestore(host->host_lock, flags);
1425
1426 nsp32_dbg(NSP32_DEBUG_INTR, "exit");
1427
1428 return IRQ_RETVAL(handled);
1429 }
1430
1431
nsp32_show_info(struct seq_file * m,struct Scsi_Host * host)1432 static int nsp32_show_info(struct seq_file *m, struct Scsi_Host *host)
1433 {
1434 unsigned long flags;
1435 nsp32_hw_data *data;
1436 int hostno;
1437 unsigned int base;
1438 unsigned char mode_reg;
1439 int id, speed;
1440 long model;
1441
1442 hostno = host->host_no;
1443 data = (nsp32_hw_data *)host->hostdata;
1444 base = host->io_port;
1445
1446 seq_puts(m, "NinjaSCSI-32 status\n\n");
1447 seq_printf(m, "Driver version: %s, $Revision: 1.33 $\n", nsp32_release_version);
1448 seq_printf(m, "SCSI host No.: %d\n", hostno);
1449 seq_printf(m, "IRQ: %d\n", host->irq);
1450 seq_printf(m, "IO: 0x%lx-0x%lx\n", host->io_port, host->io_port + host->n_io_port - 1);
1451 seq_printf(m, "MMIO(virtual address): 0x%lx-0x%lx\n", host->base, host->base + data->MmioLength - 1);
1452 seq_printf(m, "sg_tablesize: %d\n", host->sg_tablesize);
1453 seq_printf(m, "Chip revision: 0x%x\n", (nsp32_read2(base, INDEX_REG) >> 8) & 0xff);
1454
1455 mode_reg = nsp32_index_read1(base, CHIP_MODE);
1456 model = data->pci_devid->driver_data;
1457
1458 #ifdef CONFIG_PM
1459 seq_printf(m, "Power Management: %s\n", (mode_reg & OPTF) ? "yes" : "no");
1460 #endif
1461 seq_printf(m, "OEM: %ld, %s\n", (mode_reg & (OEM0|OEM1)), nsp32_model[model]);
1462
1463 spin_lock_irqsave(&(data->Lock), flags);
1464 seq_printf(m, "CurrentSC: 0x%p\n\n", data->CurrentSC);
1465 spin_unlock_irqrestore(&(data->Lock), flags);
1466
1467
1468 seq_puts(m, "SDTR status\n");
1469 for (id = 0; id < ARRAY_SIZE(data->target); id++) {
1470
1471 seq_printf(m, "id %d: ", id);
1472
1473 if (id == host->this_id) {
1474 seq_puts(m, "----- NinjaSCSI-32 host adapter\n");
1475 continue;
1476 }
1477
1478 if (data->target[id].sync_flag == SDTR_DONE) {
1479 if (data->target[id].period == 0 &&
1480 data->target[id].offset == ASYNC_OFFSET ) {
1481 seq_puts(m, "async");
1482 } else {
1483 seq_puts(m, " sync");
1484 }
1485 } else {
1486 seq_puts(m, " none");
1487 }
1488
1489 if (data->target[id].period != 0) {
1490
1491 speed = 1000000 / (data->target[id].period * 4);
1492
1493 seq_printf(m, " transfer %d.%dMB/s, offset %d",
1494 speed / 1000,
1495 speed % 1000,
1496 data->target[id].offset
1497 );
1498 }
1499 seq_putc(m, '\n');
1500 }
1501 return 0;
1502 }
1503
1504
1505
1506 /*
1507 * Reset parameters and call scsi_done for data->cur_lunt.
1508 * Be careful setting SCpnt->result = DID_* before calling this function.
1509 */
nsp32_scsi_done(struct scsi_cmnd * SCpnt)1510 static void nsp32_scsi_done(struct scsi_cmnd *SCpnt)
1511 {
1512 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
1513 unsigned int base = SCpnt->device->host->io_port;
1514
1515 scsi_dma_unmap(SCpnt);
1516
1517 /*
1518 * clear TRANSFERCONTROL_BM_START
1519 */
1520 nsp32_write2(base, TRANSFER_CONTROL, 0);
1521 nsp32_write4(base, BM_CNT, 0);
1522
1523 /*
1524 * call scsi_done
1525 */
1526 (*SCpnt->scsi_done)(SCpnt);
1527
1528 /*
1529 * reset parameters
1530 */
1531 data->cur_lunt->SCpnt = NULL;
1532 data->cur_lunt = NULL;
1533 data->cur_target = NULL;
1534 data->CurrentSC = NULL;
1535 }
1536
1537
1538 /*
1539 * Bus Free Occur
1540 *
1541 * Current Phase is BUSFREE. AutoSCSI is automatically execute BUSFREE phase
1542 * with ACK reply when below condition is matched:
1543 * MsgIn 00: Command Complete.
1544 * MsgIn 02: Save Data Pointer.
1545 * MsgIn 04: Disconnect.
1546 * In other case, unexpected BUSFREE is detected.
1547 */
nsp32_busfree_occur(struct scsi_cmnd * SCpnt,unsigned short execph)1548 static int nsp32_busfree_occur(struct scsi_cmnd *SCpnt, unsigned short execph)
1549 {
1550 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
1551 unsigned int base = SCpnt->device->host->io_port;
1552
1553 nsp32_dbg(NSP32_DEBUG_BUSFREE, "enter execph=0x%x", execph);
1554 show_autophase(execph);
1555
1556 nsp32_write4(base, BM_CNT, 0);
1557 nsp32_write2(base, TRANSFER_CONTROL, 0);
1558
1559 /*
1560 * MsgIn 02: Save Data Pointer
1561 *
1562 * VALID:
1563 * Save Data Pointer is received. Adjust pointer.
1564 *
1565 * NO-VALID:
1566 * SCSI-3 says if Save Data Pointer is not received, then we restart
1567 * processing and we can't adjust any SCSI data pointer in next data
1568 * phase.
1569 */
1570 if (execph & MSGIN_02_VALID) {
1571 nsp32_dbg(NSP32_DEBUG_BUSFREE, "MsgIn02_Valid");
1572
1573 /*
1574 * Check sack_cnt/saved_sack_cnt, then adjust sg table if
1575 * needed.
1576 */
1577 if (!(execph & MSGIN_00_VALID) &&
1578 ((execph & DATA_IN_PHASE) || (execph & DATA_OUT_PHASE))) {
1579 unsigned int sacklen, s_sacklen;
1580
1581 /*
1582 * Read SACK count and SAVEDSACK count, then compare.
1583 */
1584 sacklen = nsp32_read4(base, SACK_CNT );
1585 s_sacklen = nsp32_read4(base, SAVED_SACK_CNT);
1586
1587 /*
1588 * If SAVEDSACKCNT == 0, it means SavedDataPointer is
1589 * come after data transferring.
1590 */
1591 if (s_sacklen > 0) {
1592 /*
1593 * Comparing between sack and savedsack to
1594 * check the condition of AutoMsgIn03.
1595 *
1596 * If they are same, set msgin03 == TRUE,
1597 * COMMANDCONTROL_AUTO_MSGIN_03 is enabled at
1598 * reselection. On the other hand, if they
1599 * aren't same, set msgin03 == FALSE, and
1600 * COMMANDCONTROL_AUTO_MSGIN_03 is disabled at
1601 * reselection.
1602 */
1603 if (sacklen != s_sacklen) {
1604 data->cur_lunt->msgin03 = FALSE;
1605 } else {
1606 data->cur_lunt->msgin03 = TRUE;
1607 }
1608
1609 nsp32_adjust_busfree(SCpnt, s_sacklen);
1610 }
1611 }
1612
1613 /* This value has not substitude with valid value yet... */
1614 //data->cur_lunt->save_datp = data->cur_datp;
1615 } else {
1616 /*
1617 * no processing.
1618 */
1619 }
1620
1621 if (execph & MSGIN_03_VALID) {
1622 /* MsgIn03 was valid to be processed. No need processing. */
1623 }
1624
1625 /*
1626 * target SDTR check
1627 */
1628 if (data->cur_target->sync_flag & SDTR_INITIATOR) {
1629 /*
1630 * SDTR negotiation pulled by the initiator has not
1631 * finished yet. Fall back to ASYNC mode.
1632 */
1633 nsp32_set_async(data, data->cur_target);
1634 data->cur_target->sync_flag &= ~SDTR_INITIATOR;
1635 data->cur_target->sync_flag |= SDTR_DONE;
1636 } else if (data->cur_target->sync_flag & SDTR_TARGET) {
1637 /*
1638 * SDTR negotiation pulled by the target has been
1639 * negotiating.
1640 */
1641 if (execph & (MSGIN_00_VALID | MSGIN_04_VALID)) {
1642 /*
1643 * If valid message is received, then
1644 * negotiation is succeeded.
1645 */
1646 } else {
1647 /*
1648 * On the contrary, if unexpected bus free is
1649 * occurred, then negotiation is failed. Fall
1650 * back to ASYNC mode.
1651 */
1652 nsp32_set_async(data, data->cur_target);
1653 }
1654 data->cur_target->sync_flag &= ~SDTR_TARGET;
1655 data->cur_target->sync_flag |= SDTR_DONE;
1656 }
1657
1658 /*
1659 * It is always ensured by SCSI standard that initiator
1660 * switches into Bus Free Phase after
1661 * receiving message 00 (Command Complete), 04 (Disconnect).
1662 * It's the reason that processing here is valid.
1663 */
1664 if (execph & MSGIN_00_VALID) {
1665 /* MsgIn 00: Command Complete */
1666 nsp32_dbg(NSP32_DEBUG_BUSFREE, "command complete");
1667
1668 SCpnt->SCp.Status = nsp32_read1(base, SCSI_CSB_IN);
1669 SCpnt->SCp.Message = 0;
1670 nsp32_dbg(NSP32_DEBUG_BUSFREE,
1671 "normal end stat=0x%x resid=0x%x\n",
1672 SCpnt->SCp.Status, scsi_get_resid(SCpnt));
1673 SCpnt->result = (DID_OK << 16) |
1674 (SCpnt->SCp.Message << 8) |
1675 (SCpnt->SCp.Status << 0);
1676 nsp32_scsi_done(SCpnt);
1677 /* All operation is done */
1678 return TRUE;
1679 } else if (execph & MSGIN_04_VALID) {
1680 /* MsgIn 04: Disconnect */
1681 SCpnt->SCp.Status = nsp32_read1(base, SCSI_CSB_IN);
1682 SCpnt->SCp.Message = 4;
1683
1684 nsp32_dbg(NSP32_DEBUG_BUSFREE, "disconnect");
1685 return TRUE;
1686 } else {
1687 /* Unexpected bus free */
1688 nsp32_msg(KERN_WARNING, "unexpected bus free occurred");
1689
1690 /* DID_ERROR? */
1691 //SCpnt->result = (DID_OK << 16) | (SCpnt->SCp.Message << 8) | (SCpnt->SCp.Status << 0);
1692 SCpnt->result = DID_ERROR << 16;
1693 nsp32_scsi_done(SCpnt);
1694 return TRUE;
1695 }
1696 return FALSE;
1697 }
1698
1699
1700 /*
1701 * nsp32_adjust_busfree - adjusting SG table
1702 *
1703 * Note: This driver adjust the SG table using SCSI ACK
1704 * counter instead of BMCNT counter!
1705 */
nsp32_adjust_busfree(struct scsi_cmnd * SCpnt,unsigned int s_sacklen)1706 static void nsp32_adjust_busfree(struct scsi_cmnd *SCpnt, unsigned int s_sacklen)
1707 {
1708 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
1709 int old_entry = data->cur_entry;
1710 int new_entry;
1711 int sg_num = data->cur_lunt->sg_num;
1712 nsp32_sgtable *sgt = data->cur_lunt->sglun->sgt;
1713 unsigned int restlen, sentlen;
1714 u32_le len, addr;
1715
1716 nsp32_dbg(NSP32_DEBUG_SGLIST, "old resid=0x%x", scsi_get_resid(SCpnt));
1717
1718 /* adjust saved SACK count with 4 byte start address boundary */
1719 s_sacklen -= le32_to_cpu(sgt[old_entry].addr) & 3;
1720
1721 /*
1722 * calculate new_entry from sack count and each sgt[].len
1723 * calculate the byte which is intent to send
1724 */
1725 sentlen = 0;
1726 for (new_entry = old_entry; new_entry < sg_num; new_entry++) {
1727 sentlen += (le32_to_cpu(sgt[new_entry].len) & ~SGTEND);
1728 if (sentlen > s_sacklen) {
1729 break;
1730 }
1731 }
1732
1733 /* all sgt is processed */
1734 if (new_entry == sg_num) {
1735 goto last;
1736 }
1737
1738 if (sentlen == s_sacklen) {
1739 /* XXX: confirm it's ok or not */
1740 /* In this case, it's ok because we are at
1741 the head element of the sg. restlen is correctly calculated. */
1742 }
1743
1744 /* calculate the rest length for transferring */
1745 restlen = sentlen - s_sacklen;
1746
1747 /* update adjusting current SG table entry */
1748 len = le32_to_cpu(sgt[new_entry].len);
1749 addr = le32_to_cpu(sgt[new_entry].addr);
1750 addr += (len - restlen);
1751 sgt[new_entry].addr = cpu_to_le32(addr);
1752 sgt[new_entry].len = cpu_to_le32(restlen);
1753
1754 /* set cur_entry with new_entry */
1755 data->cur_entry = new_entry;
1756
1757 return;
1758
1759 last:
1760 if (scsi_get_resid(SCpnt) < sentlen) {
1761 nsp32_msg(KERN_ERR, "resid underflow");
1762 }
1763
1764 scsi_set_resid(SCpnt, scsi_get_resid(SCpnt) - sentlen);
1765 nsp32_dbg(NSP32_DEBUG_SGLIST, "new resid=0x%x", scsi_get_resid(SCpnt));
1766
1767 /* update hostdata and lun */
1768
1769 return;
1770 }
1771
1772
1773 /*
1774 * It's called MsgOut phase occur.
1775 * NinjaSCSI-32Bi/UDE automatically processes up to 3 messages in
1776 * message out phase. It, however, has more than 3 messages,
1777 * HBA creates the interrupt and we have to process by hand.
1778 */
nsp32_msgout_occur(struct scsi_cmnd * SCpnt)1779 static void nsp32_msgout_occur(struct scsi_cmnd *SCpnt)
1780 {
1781 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
1782 unsigned int base = SCpnt->device->host->io_port;
1783 int i;
1784
1785 nsp32_dbg(NSP32_DEBUG_MSGOUTOCCUR,
1786 "enter: msgout_len: 0x%x", data->msgout_len);
1787
1788 /*
1789 * If MsgOut phase is occurred without having any
1790 * message, then No_Operation is sent (SCSI-2).
1791 */
1792 if (data->msgout_len == 0) {
1793 nsp32_build_nop(SCpnt);
1794 }
1795
1796 /*
1797 * send messages
1798 */
1799 for (i = 0; i < data->msgout_len; i++) {
1800 nsp32_dbg(NSP32_DEBUG_MSGOUTOCCUR,
1801 "%d : 0x%x", i, data->msgoutbuf[i]);
1802
1803 /*
1804 * Check REQ is asserted.
1805 */
1806 nsp32_wait_req(data, ASSERT);
1807
1808 if (i == (data->msgout_len - 1)) {
1809 /*
1810 * If the last message, set the AutoSCSI restart
1811 * before send back the ack message. AutoSCSI
1812 * restart automatically negate ATN signal.
1813 */
1814 //command = (AUTO_MSGIN_00_OR_04 | AUTO_MSGIN_02);
1815 //nsp32_restart_autoscsi(SCpnt, command);
1816 nsp32_write2(base, COMMAND_CONTROL,
1817 (CLEAR_CDB_FIFO_POINTER |
1818 AUTO_COMMAND_PHASE |
1819 AUTOSCSI_RESTART |
1820 AUTO_MSGIN_00_OR_04 |
1821 AUTO_MSGIN_02 ));
1822 }
1823 /*
1824 * Write data with SACK, then wait sack is
1825 * automatically negated.
1826 */
1827 nsp32_write1(base, SCSI_DATA_WITH_ACK, data->msgoutbuf[i]);
1828 nsp32_wait_sack(data, NEGATE);
1829
1830 nsp32_dbg(NSP32_DEBUG_MSGOUTOCCUR, "bus: 0x%x\n",
1831 nsp32_read1(base, SCSI_BUS_MONITOR));
1832 }
1833
1834 data->msgout_len = 0;
1835
1836 nsp32_dbg(NSP32_DEBUG_MSGOUTOCCUR, "exit");
1837 }
1838
1839 /*
1840 * Restart AutoSCSI
1841 *
1842 * Note: Restarting AutoSCSI needs set:
1843 * SYNC_REG, ACK_WIDTH, SGT_ADR, TRANSFER_CONTROL
1844 */
nsp32_restart_autoscsi(struct scsi_cmnd * SCpnt,unsigned short command)1845 static void nsp32_restart_autoscsi(struct scsi_cmnd *SCpnt, unsigned short command)
1846 {
1847 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
1848 unsigned int base = data->BaseAddress;
1849 unsigned short transfer = 0;
1850
1851 nsp32_dbg(NSP32_DEBUG_RESTART, "enter");
1852
1853 if (data->cur_target == NULL || data->cur_lunt == NULL) {
1854 nsp32_msg(KERN_ERR, "Target or Lun is invalid");
1855 }
1856
1857 /*
1858 * set SYNC_REG
1859 * Don't set BM_START_ADR before setting this register.
1860 */
1861 nsp32_write1(base, SYNC_REG, data->cur_target->syncreg);
1862
1863 /*
1864 * set ACKWIDTH
1865 */
1866 nsp32_write1(base, ACK_WIDTH, data->cur_target->ackwidth);
1867
1868 /*
1869 * set SREQ hazard killer sampling rate
1870 */
1871 nsp32_write1(base, SREQ_SMPL_RATE, data->cur_target->sample_reg);
1872
1873 /*
1874 * set SGT ADDR (physical address)
1875 */
1876 nsp32_write4(base, SGT_ADR, data->cur_lunt->sglun_paddr);
1877
1878 /*
1879 * set TRANSFER CONTROL REG
1880 */
1881 transfer = 0;
1882 transfer |= (TRANSFER_GO | ALL_COUNTER_CLR);
1883 if (data->trans_method & NSP32_TRANSFER_BUSMASTER) {
1884 if (scsi_bufflen(SCpnt) > 0) {
1885 transfer |= BM_START;
1886 }
1887 } else if (data->trans_method & NSP32_TRANSFER_MMIO) {
1888 transfer |= CB_MMIO_MODE;
1889 } else if (data->trans_method & NSP32_TRANSFER_PIO) {
1890 transfer |= CB_IO_MODE;
1891 }
1892 nsp32_write2(base, TRANSFER_CONTROL, transfer);
1893
1894 /*
1895 * restart AutoSCSI
1896 *
1897 * TODO: COMMANDCONTROL_AUTO_COMMAND_PHASE is needed ?
1898 */
1899 command |= (CLEAR_CDB_FIFO_POINTER |
1900 AUTO_COMMAND_PHASE |
1901 AUTOSCSI_RESTART );
1902 nsp32_write2(base, COMMAND_CONTROL, command);
1903
1904 nsp32_dbg(NSP32_DEBUG_RESTART, "exit");
1905 }
1906
1907
1908 /*
1909 * cannot run automatically message in occur
1910 */
nsp32_msgin_occur(struct scsi_cmnd * SCpnt,unsigned long irq_status,unsigned short execph)1911 static void nsp32_msgin_occur(struct scsi_cmnd *SCpnt,
1912 unsigned long irq_status,
1913 unsigned short execph)
1914 {
1915 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
1916 unsigned int base = SCpnt->device->host->io_port;
1917 unsigned char msg;
1918 unsigned char msgtype;
1919 unsigned char newlun;
1920 unsigned short command = 0;
1921 int msgclear = TRUE;
1922 long new_sgtp;
1923 int ret;
1924
1925 /*
1926 * read first message
1927 * Use SCSIDATA_W_ACK instead of SCSIDATAIN, because the procedure
1928 * of Message-In have to be processed before sending back SCSI ACK.
1929 */
1930 msg = nsp32_read1(base, SCSI_DATA_IN);
1931 data->msginbuf[(unsigned char)data->msgin_len] = msg;
1932 msgtype = data->msginbuf[0];
1933 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR,
1934 "enter: msglen: 0x%x msgin: 0x%x msgtype: 0x%x",
1935 data->msgin_len, msg, msgtype);
1936
1937 /*
1938 * TODO: We need checking whether bus phase is message in?
1939 */
1940
1941 /*
1942 * assert SCSI ACK
1943 */
1944 nsp32_sack_assert(data);
1945
1946 /*
1947 * processing IDENTIFY
1948 */
1949 if (msgtype & 0x80) {
1950 if (!(irq_status & IRQSTATUS_RESELECT_OCCUER)) {
1951 /* Invalid (non reselect) phase */
1952 goto reject;
1953 }
1954
1955 newlun = msgtype & 0x1f; /* TODO: SPI-3 compliant? */
1956 ret = nsp32_reselection(SCpnt, newlun);
1957 if (ret == TRUE) {
1958 goto restart;
1959 } else {
1960 goto reject;
1961 }
1962 }
1963
1964 /*
1965 * processing messages except for IDENTIFY
1966 *
1967 * TODO: Messages are all SCSI-2 terminology. SCSI-3 compliance is TODO.
1968 */
1969 switch (msgtype) {
1970 /*
1971 * 1-byte message
1972 */
1973 case COMMAND_COMPLETE:
1974 case DISCONNECT:
1975 /*
1976 * These messages should not be occurred.
1977 * They should be processed on AutoSCSI sequencer.
1978 */
1979 nsp32_msg(KERN_WARNING,
1980 "unexpected message of AutoSCSI MsgIn: 0x%x", msg);
1981 break;
1982
1983 case RESTORE_POINTERS:
1984 /*
1985 * AutoMsgIn03 is disabled, and HBA gets this message.
1986 */
1987
1988 if ((execph & DATA_IN_PHASE) || (execph & DATA_OUT_PHASE)) {
1989 unsigned int s_sacklen;
1990
1991 s_sacklen = nsp32_read4(base, SAVED_SACK_CNT);
1992 if ((execph & MSGIN_02_VALID) && (s_sacklen > 0)) {
1993 nsp32_adjust_busfree(SCpnt, s_sacklen);
1994 } else {
1995 /* No need to rewrite SGT */
1996 }
1997 }
1998 data->cur_lunt->msgin03 = FALSE;
1999
2000 /* Update with the new value */
2001
2002 /* reset SACK/SavedACK counter (or ALL clear?) */
2003 nsp32_write4(base, CLR_COUNTER, CLRCOUNTER_ALLMASK);
2004
2005 /*
2006 * set new sg pointer
2007 */
2008 new_sgtp = data->cur_lunt->sglun_paddr +
2009 (data->cur_lunt->cur_entry * sizeof(nsp32_sgtable));
2010 nsp32_write4(base, SGT_ADR, new_sgtp);
2011
2012 break;
2013
2014 case SAVE_POINTERS:
2015 /*
2016 * These messages should not be occurred.
2017 * They should be processed on AutoSCSI sequencer.
2018 */
2019 nsp32_msg (KERN_WARNING,
2020 "unexpected message of AutoSCSI MsgIn: SAVE_POINTERS");
2021
2022 break;
2023
2024 case MESSAGE_REJECT:
2025 /* If previous message_out is sending SDTR, and get
2026 message_reject from target, SDTR negotiation is failed */
2027 if (data->cur_target->sync_flag &
2028 (SDTR_INITIATOR | SDTR_TARGET)) {
2029 /*
2030 * Current target is negotiating SDTR, but it's
2031 * failed. Fall back to async transfer mode, and set
2032 * SDTR_DONE.
2033 */
2034 nsp32_set_async(data, data->cur_target);
2035 data->cur_target->sync_flag &= ~SDTR_INITIATOR;
2036 data->cur_target->sync_flag |= SDTR_DONE;
2037
2038 }
2039 break;
2040
2041 case LINKED_CMD_COMPLETE:
2042 case LINKED_FLG_CMD_COMPLETE:
2043 /* queue tag is not supported currently */
2044 nsp32_msg (KERN_WARNING,
2045 "unsupported message: 0x%x", msgtype);
2046 break;
2047
2048 case INITIATE_RECOVERY:
2049 /* staring ECA (Extended Contingent Allegiance) state. */
2050 /* This message is declined in SPI2 or later. */
2051
2052 goto reject;
2053
2054 /*
2055 * 2-byte message
2056 */
2057 case SIMPLE_QUEUE_TAG:
2058 case 0x23:
2059 /*
2060 * 0x23: Ignore_Wide_Residue is not declared in scsi.h.
2061 * No support is needed.
2062 */
2063 if (data->msgin_len >= 1) {
2064 goto reject;
2065 }
2066
2067 /* current position is 1-byte of 2 byte */
2068 msgclear = FALSE;
2069
2070 break;
2071
2072 /*
2073 * extended message
2074 */
2075 case EXTENDED_MESSAGE:
2076 if (data->msgin_len < 1) {
2077 /*
2078 * Current position does not reach 2-byte
2079 * (2-byte is extended message length).
2080 */
2081 msgclear = FALSE;
2082 break;
2083 }
2084
2085 if ((data->msginbuf[1] + 1) > data->msgin_len) {
2086 /*
2087 * Current extended message has msginbuf[1] + 2
2088 * (msgin_len starts counting from 0, so buf[1] + 1).
2089 * If current message position is not finished,
2090 * continue receiving message.
2091 */
2092 msgclear = FALSE;
2093 break;
2094 }
2095
2096 /*
2097 * Reach here means regular length of each type of
2098 * extended messages.
2099 */
2100 switch (data->msginbuf[2]) {
2101 case EXTENDED_MODIFY_DATA_POINTER:
2102 /* TODO */
2103 goto reject; /* not implemented yet */
2104 break;
2105
2106 case EXTENDED_SDTR:
2107 /*
2108 * Exchange this message between initiator and target.
2109 */
2110 if (data->msgin_len != EXTENDED_SDTR_LEN + 1) {
2111 /*
2112 * received inappropriate message.
2113 */
2114 goto reject;
2115 break;
2116 }
2117
2118 nsp32_analyze_sdtr(SCpnt);
2119
2120 break;
2121
2122 case EXTENDED_EXTENDED_IDENTIFY:
2123 /* SCSI-I only, not supported. */
2124 goto reject; /* not implemented yet */
2125
2126 break;
2127
2128 case EXTENDED_WDTR:
2129 goto reject; /* not implemented yet */
2130
2131 break;
2132
2133 default:
2134 goto reject;
2135 }
2136 break;
2137
2138 default:
2139 goto reject;
2140 }
2141
2142 restart:
2143 if (msgclear == TRUE) {
2144 data->msgin_len = 0;
2145
2146 /*
2147 * If restarting AutoSCSI, but there are some message to out
2148 * (msgout_len > 0), set AutoATN, and set SCSIMSGOUT as 0
2149 * (MV_VALID = 0). When commandcontrol is written with
2150 * AutoSCSI restart, at the same time MsgOutOccur should be
2151 * happened (however, such situation is really possible...?).
2152 */
2153 if (data->msgout_len > 0) {
2154 nsp32_write4(base, SCSI_MSG_OUT, 0);
2155 command |= AUTO_ATN;
2156 }
2157
2158 /*
2159 * restart AutoSCSI
2160 * If it's failed, COMMANDCONTROL_AUTO_COMMAND_PHASE is needed.
2161 */
2162 command |= (AUTO_MSGIN_00_OR_04 | AUTO_MSGIN_02);
2163
2164 /*
2165 * If current msgin03 is TRUE, then flag on.
2166 */
2167 if (data->cur_lunt->msgin03 == TRUE) {
2168 command |= AUTO_MSGIN_03;
2169 }
2170 data->cur_lunt->msgin03 = FALSE;
2171 } else {
2172 data->msgin_len++;
2173 }
2174
2175 /*
2176 * restart AutoSCSI
2177 */
2178 nsp32_restart_autoscsi(SCpnt, command);
2179
2180 /*
2181 * wait SCSI REQ negate for REQ-ACK handshake
2182 */
2183 nsp32_wait_req(data, NEGATE);
2184
2185 /*
2186 * negate SCSI ACK
2187 */
2188 nsp32_sack_negate(data);
2189
2190 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "exit");
2191
2192 return;
2193
2194 reject:
2195 nsp32_msg(KERN_WARNING,
2196 "invalid or unsupported MessageIn, rejected. "
2197 "current msg: 0x%x (len: 0x%x), processing msg: 0x%x",
2198 msg, data->msgin_len, msgtype);
2199 nsp32_build_reject(SCpnt);
2200 data->msgin_len = 0;
2201
2202 goto restart;
2203 }
2204
2205 /*
2206 *
2207 */
nsp32_analyze_sdtr(struct scsi_cmnd * SCpnt)2208 static void nsp32_analyze_sdtr(struct scsi_cmnd *SCpnt)
2209 {
2210 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
2211 nsp32_target *target = data->cur_target;
2212 unsigned char get_period = data->msginbuf[3];
2213 unsigned char get_offset = data->msginbuf[4];
2214 int entry;
2215
2216 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "enter");
2217
2218 /*
2219 * If this inititor sent the SDTR message, then target responds SDTR,
2220 * initiator SYNCREG, ACKWIDTH from SDTR parameter.
2221 * Messages are not appropriate, then send back reject message.
2222 * If initiator did not send the SDTR, but target sends SDTR,
2223 * initiator calculator the appropriate parameter and send back SDTR.
2224 */
2225 if (target->sync_flag & SDTR_INITIATOR) {
2226 /*
2227 * Initiator sent SDTR, the target responds and
2228 * send back negotiation SDTR.
2229 */
2230 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "target responds SDTR");
2231
2232 target->sync_flag &= ~SDTR_INITIATOR;
2233 target->sync_flag |= SDTR_DONE;
2234
2235 /*
2236 * offset:
2237 */
2238 if (get_offset > SYNC_OFFSET) {
2239 /*
2240 * Negotiation is failed, the target send back
2241 * unexpected offset value.
2242 */
2243 goto reject;
2244 }
2245
2246 if (get_offset == ASYNC_OFFSET) {
2247 /*
2248 * Negotiation is succeeded, the target want
2249 * to fall back into asynchronous transfer mode.
2250 */
2251 goto async;
2252 }
2253
2254 /*
2255 * period:
2256 * Check whether sync period is too short. If too short,
2257 * fall back to async mode. If it's ok, then investigate
2258 * the received sync period. If sync period is acceptable
2259 * between sync table start_period and end_period, then
2260 * set this I_T nexus as sent offset and period.
2261 * If it's not acceptable, send back reject and fall back
2262 * to async mode.
2263 */
2264 if (get_period < data->synct[0].period_num) {
2265 /*
2266 * Negotiation is failed, the target send back
2267 * unexpected period value.
2268 */
2269 goto reject;
2270 }
2271
2272 entry = nsp32_search_period_entry(data, target, get_period);
2273
2274 if (entry < 0) {
2275 /*
2276 * Target want to use long period which is not
2277 * acceptable NinjaSCSI-32Bi/UDE.
2278 */
2279 goto reject;
2280 }
2281
2282 /*
2283 * Set new sync table and offset in this I_T nexus.
2284 */
2285 nsp32_set_sync_entry(data, target, entry, get_offset);
2286 } else {
2287 /* Target send SDTR to initiator. */
2288 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "target send SDTR");
2289
2290 target->sync_flag |= SDTR_INITIATOR;
2291
2292 /* offset: */
2293 if (get_offset > SYNC_OFFSET) {
2294 /* send back as SYNC_OFFSET */
2295 get_offset = SYNC_OFFSET;
2296 }
2297
2298 /* period: */
2299 if (get_period < data->synct[0].period_num) {
2300 get_period = data->synct[0].period_num;
2301 }
2302
2303 entry = nsp32_search_period_entry(data, target, get_period);
2304
2305 if (get_offset == ASYNC_OFFSET || entry < 0) {
2306 nsp32_set_async(data, target);
2307 nsp32_build_sdtr(SCpnt, 0, ASYNC_OFFSET);
2308 } else {
2309 nsp32_set_sync_entry(data, target, entry, get_offset);
2310 nsp32_build_sdtr(SCpnt, get_period, get_offset);
2311 }
2312 }
2313
2314 target->period = get_period;
2315 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "exit");
2316 return;
2317
2318 reject:
2319 /*
2320 * If the current message is unacceptable, send back to the target
2321 * with reject message.
2322 */
2323 nsp32_build_reject(SCpnt);
2324
2325 async:
2326 nsp32_set_async(data, target); /* set as ASYNC transfer mode */
2327
2328 target->period = 0;
2329 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "exit: set async");
2330 return;
2331 }
2332
2333
2334 /*
2335 * Search config entry number matched in sync_table from given
2336 * target and speed period value. If failed to search, return negative value.
2337 */
nsp32_search_period_entry(nsp32_hw_data * data,nsp32_target * target,unsigned char period)2338 static int nsp32_search_period_entry(nsp32_hw_data *data,
2339 nsp32_target *target,
2340 unsigned char period)
2341 {
2342 int i;
2343
2344 if (target->limit_entry >= data->syncnum) {
2345 nsp32_msg(KERN_ERR, "limit_entry exceeds syncnum!");
2346 target->limit_entry = 0;
2347 }
2348
2349 for (i = target->limit_entry; i < data->syncnum; i++) {
2350 if (period >= data->synct[i].start_period &&
2351 period <= data->synct[i].end_period) {
2352 break;
2353 }
2354 }
2355
2356 /*
2357 * Check given period value is over the sync_table value.
2358 * If so, return max value.
2359 */
2360 if (i == data->syncnum) {
2361 i = -1;
2362 }
2363
2364 return i;
2365 }
2366
2367
2368 /*
2369 * target <-> initiator use ASYNC transfer
2370 */
nsp32_set_async(nsp32_hw_data * data,nsp32_target * target)2371 static void nsp32_set_async(nsp32_hw_data *data, nsp32_target *target)
2372 {
2373 unsigned char period = data->synct[target->limit_entry].period_num;
2374
2375 target->offset = ASYNC_OFFSET;
2376 target->period = 0;
2377 target->syncreg = TO_SYNCREG(period, ASYNC_OFFSET);
2378 target->ackwidth = 0;
2379 target->sample_reg = 0;
2380
2381 nsp32_dbg(NSP32_DEBUG_SYNC, "set async");
2382 }
2383
2384
2385 /*
2386 * target <-> initiator use maximum SYNC transfer
2387 */
nsp32_set_max_sync(nsp32_hw_data * data,nsp32_target * target,unsigned char * period,unsigned char * offset)2388 static void nsp32_set_max_sync(nsp32_hw_data *data,
2389 nsp32_target *target,
2390 unsigned char *period,
2391 unsigned char *offset)
2392 {
2393 unsigned char period_num, ackwidth;
2394
2395 period_num = data->synct[target->limit_entry].period_num;
2396 *period = data->synct[target->limit_entry].start_period;
2397 ackwidth = data->synct[target->limit_entry].ackwidth;
2398 *offset = SYNC_OFFSET;
2399
2400 target->syncreg = TO_SYNCREG(period_num, *offset);
2401 target->ackwidth = ackwidth;
2402 target->offset = *offset;
2403 target->sample_reg = 0; /* disable SREQ sampling */
2404 }
2405
2406
2407 /*
2408 * target <-> initiator use entry number speed
2409 */
nsp32_set_sync_entry(nsp32_hw_data * data,nsp32_target * target,int entry,unsigned char offset)2410 static void nsp32_set_sync_entry(nsp32_hw_data *data,
2411 nsp32_target *target,
2412 int entry,
2413 unsigned char offset)
2414 {
2415 unsigned char period, ackwidth, sample_rate;
2416
2417 period = data->synct[entry].period_num;
2418 ackwidth = data->synct[entry].ackwidth;
2419 sample_rate = data->synct[entry].sample_rate;
2420
2421 target->syncreg = TO_SYNCREG(period, offset);
2422 target->ackwidth = ackwidth;
2423 target->offset = offset;
2424 target->sample_reg = sample_rate | SAMPLING_ENABLE;
2425
2426 nsp32_dbg(NSP32_DEBUG_SYNC, "set sync");
2427 }
2428
2429
2430 /*
2431 * It waits until SCSI REQ becomes assertion or negation state.
2432 *
2433 * Note: If nsp32_msgin_occur is called, we asserts SCSI ACK. Then
2434 * connected target responds SCSI REQ negation. We have to wait
2435 * SCSI REQ becomes negation in order to negate SCSI ACK signal for
2436 * REQ-ACK handshake.
2437 */
nsp32_wait_req(nsp32_hw_data * data,int state)2438 static void nsp32_wait_req(nsp32_hw_data *data, int state)
2439 {
2440 unsigned int base = data->BaseAddress;
2441 int wait_time = 0;
2442 unsigned char bus, req_bit;
2443
2444 if (!((state == ASSERT) || (state == NEGATE))) {
2445 nsp32_msg(KERN_ERR, "unknown state designation");
2446 }
2447 /* REQ is BIT(5) */
2448 req_bit = (state == ASSERT ? BUSMON_REQ : 0);
2449
2450 do {
2451 bus = nsp32_read1(base, SCSI_BUS_MONITOR);
2452 if ((bus & BUSMON_REQ) == req_bit) {
2453 nsp32_dbg(NSP32_DEBUG_WAIT,
2454 "wait_time: %d", wait_time);
2455 return;
2456 }
2457 udelay(1);
2458 wait_time++;
2459 } while (wait_time < REQSACK_TIMEOUT_TIME);
2460
2461 nsp32_msg(KERN_WARNING, "wait REQ timeout, req_bit: 0x%x", req_bit);
2462 }
2463
2464 /*
2465 * It waits until SCSI SACK becomes assertion or negation state.
2466 */
nsp32_wait_sack(nsp32_hw_data * data,int state)2467 static void nsp32_wait_sack(nsp32_hw_data *data, int state)
2468 {
2469 unsigned int base = data->BaseAddress;
2470 int wait_time = 0;
2471 unsigned char bus, ack_bit;
2472
2473 if (!((state == ASSERT) || (state == NEGATE))) {
2474 nsp32_msg(KERN_ERR, "unknown state designation");
2475 }
2476 /* ACK is BIT(4) */
2477 ack_bit = (state == ASSERT ? BUSMON_ACK : 0);
2478
2479 do {
2480 bus = nsp32_read1(base, SCSI_BUS_MONITOR);
2481 if ((bus & BUSMON_ACK) == ack_bit) {
2482 nsp32_dbg(NSP32_DEBUG_WAIT,
2483 "wait_time: %d", wait_time);
2484 return;
2485 }
2486 udelay(1);
2487 wait_time++;
2488 } while (wait_time < REQSACK_TIMEOUT_TIME);
2489
2490 nsp32_msg(KERN_WARNING, "wait SACK timeout, ack_bit: 0x%x", ack_bit);
2491 }
2492
2493 /*
2494 * assert SCSI ACK
2495 *
2496 * Note: SCSI ACK assertion needs with ACKENB=1, AUTODIRECTION=1.
2497 */
nsp32_sack_assert(nsp32_hw_data * data)2498 static void nsp32_sack_assert(nsp32_hw_data *data)
2499 {
2500 unsigned int base = data->BaseAddress;
2501 unsigned char busctrl;
2502
2503 busctrl = nsp32_read1(base, SCSI_BUS_CONTROL);
2504 busctrl |= (BUSCTL_ACK | AUTODIRECTION | ACKENB);
2505 nsp32_write1(base, SCSI_BUS_CONTROL, busctrl);
2506 }
2507
2508 /*
2509 * negate SCSI ACK
2510 */
nsp32_sack_negate(nsp32_hw_data * data)2511 static void nsp32_sack_negate(nsp32_hw_data *data)
2512 {
2513 unsigned int base = data->BaseAddress;
2514 unsigned char busctrl;
2515
2516 busctrl = nsp32_read1(base, SCSI_BUS_CONTROL);
2517 busctrl &= ~BUSCTL_ACK;
2518 nsp32_write1(base, SCSI_BUS_CONTROL, busctrl);
2519 }
2520
2521
2522
2523 /*
2524 * Note: n_io_port is defined as 0x7f because I/O register port is
2525 * assigned as:
2526 * 0x800-0x8ff: memory mapped I/O port
2527 * 0x900-0xbff: (map same 0x800-0x8ff I/O port image repeatedly)
2528 * 0xc00-0xfff: CardBus status registers
2529 */
nsp32_detect(struct pci_dev * pdev)2530 static int nsp32_detect(struct pci_dev *pdev)
2531 {
2532 struct Scsi_Host *host; /* registered host structure */
2533 struct resource *res;
2534 nsp32_hw_data *data;
2535 int ret;
2536 int i, j;
2537
2538 nsp32_dbg(NSP32_DEBUG_REGISTER, "enter");
2539
2540 /*
2541 * register this HBA as SCSI device
2542 */
2543 host = scsi_host_alloc(&nsp32_template, sizeof(nsp32_hw_data));
2544 if (host == NULL) {
2545 nsp32_msg (KERN_ERR, "failed to scsi register");
2546 goto err;
2547 }
2548
2549 /*
2550 * set nsp32_hw_data
2551 */
2552 data = (nsp32_hw_data *)host->hostdata;
2553
2554 memcpy(data, &nsp32_data_base, sizeof(nsp32_hw_data));
2555
2556 host->irq = data->IrqNumber;
2557 host->io_port = data->BaseAddress;
2558 host->unique_id = data->BaseAddress;
2559 host->n_io_port = data->NumAddress;
2560 host->base = (unsigned long)data->MmioAddress;
2561
2562 data->Host = host;
2563 spin_lock_init(&(data->Lock));
2564
2565 data->cur_lunt = NULL;
2566 data->cur_target = NULL;
2567
2568 /*
2569 * Bus master transfer mode is supported currently.
2570 */
2571 data->trans_method = NSP32_TRANSFER_BUSMASTER;
2572
2573 /*
2574 * Set clock div, CLOCK_4 (HBA has own external clock, and
2575 * dividing * 100ns/4).
2576 * Currently CLOCK_4 has only tested, not for CLOCK_2/PCICLK yet.
2577 */
2578 data->clock = CLOCK_4;
2579
2580 /*
2581 * Select appropriate nsp32_sync_table and set I_CLOCKDIV.
2582 */
2583 switch (data->clock) {
2584 case CLOCK_4:
2585 /* If data->clock is CLOCK_4, then select 40M sync table. */
2586 data->synct = nsp32_sync_table_40M;
2587 data->syncnum = ARRAY_SIZE(nsp32_sync_table_40M);
2588 break;
2589 case CLOCK_2:
2590 /* If data->clock is CLOCK_2, then select 20M sync table. */
2591 data->synct = nsp32_sync_table_20M;
2592 data->syncnum = ARRAY_SIZE(nsp32_sync_table_20M);
2593 break;
2594 case PCICLK:
2595 /* If data->clock is PCICLK, then select pci sync table. */
2596 data->synct = nsp32_sync_table_pci;
2597 data->syncnum = ARRAY_SIZE(nsp32_sync_table_pci);
2598 break;
2599 default:
2600 nsp32_msg(KERN_WARNING,
2601 "Invalid clock div is selected, set CLOCK_4.");
2602 /* Use default value CLOCK_4 */
2603 data->clock = CLOCK_4;
2604 data->synct = nsp32_sync_table_40M;
2605 data->syncnum = ARRAY_SIZE(nsp32_sync_table_40M);
2606 }
2607
2608 /*
2609 * setup nsp32_lunt
2610 */
2611
2612 /*
2613 * setup DMA
2614 */
2615 if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
2616 nsp32_msg (KERN_ERR, "failed to set PCI DMA mask");
2617 goto scsi_unregister;
2618 }
2619
2620 /*
2621 * allocate autoparam DMA resource.
2622 */
2623 data->autoparam = dma_alloc_coherent(&pdev->dev,
2624 sizeof(nsp32_autoparam), &(data->auto_paddr),
2625 GFP_KERNEL);
2626 if (data->autoparam == NULL) {
2627 nsp32_msg(KERN_ERR, "failed to allocate DMA memory");
2628 goto scsi_unregister;
2629 }
2630
2631 /*
2632 * allocate scatter-gather DMA resource.
2633 */
2634 data->sg_list = dma_alloc_coherent(&pdev->dev, NSP32_SG_TABLE_SIZE,
2635 &data->sg_paddr, GFP_KERNEL);
2636 if (data->sg_list == NULL) {
2637 nsp32_msg(KERN_ERR, "failed to allocate DMA memory");
2638 goto free_autoparam;
2639 }
2640
2641 for (i = 0; i < ARRAY_SIZE(data->lunt); i++) {
2642 for (j = 0; j < ARRAY_SIZE(data->lunt[0]); j++) {
2643 int offset = i * ARRAY_SIZE(data->lunt[0]) + j;
2644 nsp32_lunt tmp = {
2645 .SCpnt = NULL,
2646 .save_datp = 0,
2647 .msgin03 = FALSE,
2648 .sg_num = 0,
2649 .cur_entry = 0,
2650 .sglun = &(data->sg_list[offset]),
2651 .sglun_paddr = data->sg_paddr + (offset * sizeof(nsp32_sglun)),
2652 };
2653
2654 data->lunt[i][j] = tmp;
2655 }
2656 }
2657
2658 /*
2659 * setup target
2660 */
2661 for (i = 0; i < ARRAY_SIZE(data->target); i++) {
2662 nsp32_target *target = &(data->target[i]);
2663
2664 target->limit_entry = 0;
2665 target->sync_flag = 0;
2666 nsp32_set_async(data, target);
2667 }
2668
2669 /*
2670 * EEPROM check
2671 */
2672 ret = nsp32_getprom_param(data);
2673 if (ret == FALSE) {
2674 data->resettime = 3; /* default 3 */
2675 }
2676
2677 /*
2678 * setup HBA
2679 */
2680 nsp32hw_init(data);
2681
2682 snprintf(data->info_str, sizeof(data->info_str),
2683 "NinjaSCSI-32Bi/UDE: irq %d, io 0x%lx+0x%x",
2684 host->irq, host->io_port, host->n_io_port);
2685
2686 /*
2687 * SCSI bus reset
2688 *
2689 * Note: It's important to reset SCSI bus in initialization phase.
2690 * NinjaSCSI-32Bi/UDE HBA EEPROM seems to exchange SDTR when
2691 * system is coming up, so SCSI devices connected to HBA is set as
2692 * un-asynchronous mode. It brings the merit that this HBA is
2693 * ready to start synchronous transfer without any preparation,
2694 * but we are difficult to control transfer speed. In addition,
2695 * it prevents device transfer speed from effecting EEPROM start-up
2696 * SDTR. NinjaSCSI-32Bi/UDE has the feature if EEPROM is set as
2697 * Auto Mode, then FAST-10M is selected when SCSI devices are
2698 * connected same or more than 4 devices. It should be avoided
2699 * depending on this specification. Thus, resetting the SCSI bus
2700 * restores all connected SCSI devices to asynchronous mode, then
2701 * this driver set SDTR safely later, and we can control all SCSI
2702 * device transfer mode.
2703 */
2704 nsp32_do_bus_reset(data);
2705
2706 ret = request_irq(host->irq, do_nsp32_isr, IRQF_SHARED, "nsp32", data);
2707 if (ret < 0) {
2708 nsp32_msg(KERN_ERR, "Unable to allocate IRQ for NinjaSCSI32 "
2709 "SCSI PCI controller. Interrupt: %d", host->irq);
2710 goto free_sg_list;
2711 }
2712
2713 /*
2714 * PCI IO register
2715 */
2716 res = request_region(host->io_port, host->n_io_port, "nsp32");
2717 if (res == NULL) {
2718 nsp32_msg(KERN_ERR,
2719 "I/O region 0x%x+0x%x is already used",
2720 data->BaseAddress, data->NumAddress);
2721 goto free_irq;
2722 }
2723
2724 ret = scsi_add_host(host, &pdev->dev);
2725 if (ret) {
2726 nsp32_msg(KERN_ERR, "failed to add scsi host");
2727 goto free_region;
2728 }
2729 scsi_scan_host(host);
2730 pci_set_drvdata(pdev, host);
2731 return 0;
2732
2733 free_region:
2734 release_region(host->io_port, host->n_io_port);
2735
2736 free_irq:
2737 free_irq(host->irq, data);
2738
2739 free_sg_list:
2740 dma_free_coherent(&pdev->dev, NSP32_SG_TABLE_SIZE,
2741 data->sg_list, data->sg_paddr);
2742
2743 free_autoparam:
2744 dma_free_coherent(&pdev->dev, sizeof(nsp32_autoparam),
2745 data->autoparam, data->auto_paddr);
2746
2747 scsi_unregister:
2748 scsi_host_put(host);
2749
2750 err:
2751 return 1;
2752 }
2753
nsp32_release(struct Scsi_Host * host)2754 static int nsp32_release(struct Scsi_Host *host)
2755 {
2756 nsp32_hw_data *data = (nsp32_hw_data *)host->hostdata;
2757
2758 if (data->autoparam) {
2759 dma_free_coherent(&data->Pci->dev, sizeof(nsp32_autoparam),
2760 data->autoparam, data->auto_paddr);
2761 }
2762
2763 if (data->sg_list) {
2764 dma_free_coherent(&data->Pci->dev, NSP32_SG_TABLE_SIZE,
2765 data->sg_list, data->sg_paddr);
2766 }
2767
2768 if (host->irq) {
2769 free_irq(host->irq, data);
2770 }
2771
2772 if (host->io_port && host->n_io_port) {
2773 release_region(host->io_port, host->n_io_port);
2774 }
2775
2776 if (data->MmioAddress) {
2777 iounmap(data->MmioAddress);
2778 }
2779
2780 return 0;
2781 }
2782
nsp32_info(struct Scsi_Host * shpnt)2783 static const char *nsp32_info(struct Scsi_Host *shpnt)
2784 {
2785 nsp32_hw_data *data = (nsp32_hw_data *)shpnt->hostdata;
2786
2787 return data->info_str;
2788 }
2789
2790
2791 /****************************************************************************
2792 * error handler
2793 */
nsp32_eh_abort(struct scsi_cmnd * SCpnt)2794 static int nsp32_eh_abort(struct scsi_cmnd *SCpnt)
2795 {
2796 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
2797 unsigned int base = SCpnt->device->host->io_port;
2798
2799 nsp32_msg(KERN_WARNING, "abort");
2800
2801 if (data->cur_lunt->SCpnt == NULL) {
2802 nsp32_dbg(NSP32_DEBUG_BUSRESET, "abort failed");
2803 return FAILED;
2804 }
2805
2806 if (data->cur_target->sync_flag & (SDTR_INITIATOR | SDTR_TARGET)) {
2807 /* reset SDTR negotiation */
2808 data->cur_target->sync_flag = 0;
2809 nsp32_set_async(data, data->cur_target);
2810 }
2811
2812 nsp32_write2(base, TRANSFER_CONTROL, 0);
2813 nsp32_write2(base, BM_CNT, 0);
2814
2815 SCpnt->result = DID_ABORT << 16;
2816 nsp32_scsi_done(SCpnt);
2817
2818 nsp32_dbg(NSP32_DEBUG_BUSRESET, "abort success");
2819 return SUCCESS;
2820 }
2821
nsp32_do_bus_reset(nsp32_hw_data * data)2822 static void nsp32_do_bus_reset(nsp32_hw_data *data)
2823 {
2824 unsigned int base = data->BaseAddress;
2825 int i;
2826 unsigned short __maybe_unused intrdat;
2827
2828 nsp32_dbg(NSP32_DEBUG_BUSRESET, "in");
2829
2830 /*
2831 * stop all transfer
2832 * clear TRANSFERCONTROL_BM_START
2833 * clear counter
2834 */
2835 nsp32_write2(base, TRANSFER_CONTROL, 0);
2836 nsp32_write4(base, BM_CNT, 0);
2837 nsp32_write4(base, CLR_COUNTER, CLRCOUNTER_ALLMASK);
2838
2839 /*
2840 * fall back to asynchronous transfer mode
2841 * initialize SDTR negotiation flag
2842 */
2843 for (i = 0; i < ARRAY_SIZE(data->target); i++) {
2844 nsp32_target *target = &data->target[i];
2845
2846 target->sync_flag = 0;
2847 nsp32_set_async(data, target);
2848 }
2849
2850 /*
2851 * reset SCSI bus
2852 */
2853 nsp32_write1(base, SCSI_BUS_CONTROL, BUSCTL_RST);
2854 mdelay(RESET_HOLD_TIME / 1000);
2855 nsp32_write1(base, SCSI_BUS_CONTROL, 0);
2856 for(i = 0; i < 5; i++) {
2857 intrdat = nsp32_read2(base, IRQ_STATUS); /* dummy read */
2858 nsp32_dbg(NSP32_DEBUG_BUSRESET, "irq:1: 0x%x", intrdat);
2859 }
2860
2861 data->CurrentSC = NULL;
2862 }
2863
nsp32_eh_host_reset(struct scsi_cmnd * SCpnt)2864 static int nsp32_eh_host_reset(struct scsi_cmnd *SCpnt)
2865 {
2866 struct Scsi_Host *host = SCpnt->device->host;
2867 unsigned int base = SCpnt->device->host->io_port;
2868 nsp32_hw_data *data = (nsp32_hw_data *)host->hostdata;
2869
2870 nsp32_msg(KERN_INFO, "Host Reset");
2871 nsp32_dbg(NSP32_DEBUG_BUSRESET, "SCpnt=0x%x", SCpnt);
2872
2873 spin_lock_irq(SCpnt->device->host->host_lock);
2874
2875 nsp32hw_init(data);
2876 nsp32_write2(base, IRQ_CONTROL, IRQ_CONTROL_ALL_IRQ_MASK);
2877 nsp32_do_bus_reset(data);
2878 nsp32_write2(base, IRQ_CONTROL, 0);
2879
2880 spin_unlock_irq(SCpnt->device->host->host_lock);
2881 return SUCCESS; /* Host reset is succeeded at any time. */
2882 }
2883
2884
2885 /**************************************************************************
2886 * EEPROM handler
2887 */
2888
2889 /*
2890 * getting EEPROM parameter
2891 */
nsp32_getprom_param(nsp32_hw_data * data)2892 static int nsp32_getprom_param(nsp32_hw_data *data)
2893 {
2894 int vendor = data->pci_devid->vendor;
2895 int device = data->pci_devid->device;
2896 int ret, i;
2897 int __maybe_unused val;
2898
2899 /*
2900 * EEPROM checking.
2901 */
2902 ret = nsp32_prom_read(data, 0x7e);
2903 if (ret != 0x55) {
2904 nsp32_msg(KERN_INFO, "No EEPROM detected: 0x%x", ret);
2905 return FALSE;
2906 }
2907 ret = nsp32_prom_read(data, 0x7f);
2908 if (ret != 0xaa) {
2909 nsp32_msg(KERN_INFO, "Invalid number: 0x%x", ret);
2910 return FALSE;
2911 }
2912
2913 /*
2914 * check EEPROM type
2915 */
2916 if (vendor == PCI_VENDOR_ID_WORKBIT &&
2917 device == PCI_DEVICE_ID_WORKBIT_STANDARD) {
2918 ret = nsp32_getprom_c16(data);
2919 } else if (vendor == PCI_VENDOR_ID_WORKBIT &&
2920 device == PCI_DEVICE_ID_NINJASCSI_32BIB_LOGITEC) {
2921 ret = nsp32_getprom_at24(data);
2922 } else if (vendor == PCI_VENDOR_ID_WORKBIT &&
2923 device == PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO ) {
2924 ret = nsp32_getprom_at24(data);
2925 } else {
2926 nsp32_msg(KERN_WARNING, "Unknown EEPROM");
2927 ret = FALSE;
2928 }
2929
2930 /* for debug : SPROM data full checking */
2931 for (i = 0; i <= 0x1f; i++) {
2932 val = nsp32_prom_read(data, i);
2933 nsp32_dbg(NSP32_DEBUG_EEPROM,
2934 "rom address 0x%x : 0x%x", i, val);
2935 }
2936
2937 return ret;
2938 }
2939
2940
2941 /*
2942 * AT24C01A (Logitec: LHA-600S), AT24C02 (Melco Buffalo: IFC-USLP) data map:
2943 *
2944 * ROMADDR
2945 * 0x00 - 0x06 : Device Synchronous Transfer Period (SCSI ID 0 - 6)
2946 * Value 0x0: ASYNC, 0x0c: Ultra-20M, 0x19: Fast-10M
2947 * 0x07 : HBA Synchronous Transfer Period
2948 * Value 0: AutoSync, 1: Manual Setting
2949 * 0x08 - 0x0f : Not Used? (0x0)
2950 * 0x10 : Bus Termination
2951 * Value 0: Auto[ON], 1: ON, 2: OFF
2952 * 0x11 : Not Used? (0)
2953 * 0x12 : Bus Reset Delay Time (0x03)
2954 * 0x13 : Bootable CD Support
2955 * Value 0: Disable, 1: Enable
2956 * 0x14 : Device Scan
2957 * Bit 7 6 5 4 3 2 1 0
2958 * | <----------------->
2959 * | SCSI ID: Value 0: Skip, 1: YES
2960 * |-> Value 0: ALL scan, Value 1: Manual
2961 * 0x15 - 0x1b : Not Used? (0)
2962 * 0x1c : Constant? (0x01) (clock div?)
2963 * 0x1d - 0x7c : Not Used (0xff)
2964 * 0x7d : Not Used? (0xff)
2965 * 0x7e : Constant (0x55), Validity signature
2966 * 0x7f : Constant (0xaa), Validity signature
2967 */
nsp32_getprom_at24(nsp32_hw_data * data)2968 static int nsp32_getprom_at24(nsp32_hw_data *data)
2969 {
2970 int ret, i;
2971 int auto_sync;
2972 nsp32_target *target;
2973 int entry;
2974
2975 /*
2976 * Reset time which is designated by EEPROM.
2977 *
2978 * TODO: Not used yet.
2979 */
2980 data->resettime = nsp32_prom_read(data, 0x12);
2981
2982 /*
2983 * HBA Synchronous Transfer Period
2984 *
2985 * Note: auto_sync = 0: auto, 1: manual. Ninja SCSI HBA spec says
2986 * that if auto_sync is 0 (auto), and connected SCSI devices are
2987 * same or lower than 3, then transfer speed is set as ULTRA-20M.
2988 * On the contrary if connected SCSI devices are same or higher
2989 * than 4, then transfer speed is set as FAST-10M.
2990 *
2991 * I break this rule. The number of connected SCSI devices are
2992 * only ignored. If auto_sync is 0 (auto), then transfer speed is
2993 * forced as ULTRA-20M.
2994 */
2995 ret = nsp32_prom_read(data, 0x07);
2996 switch (ret) {
2997 case 0:
2998 auto_sync = TRUE;
2999 break;
3000 case 1:
3001 auto_sync = FALSE;
3002 break;
3003 default:
3004 nsp32_msg(KERN_WARNING,
3005 "Unsupported Auto Sync mode. Fall back to manual mode.");
3006 auto_sync = TRUE;
3007 }
3008
3009 if (trans_mode == ULTRA20M_MODE) {
3010 auto_sync = TRUE;
3011 }
3012
3013 /*
3014 * each device Synchronous Transfer Period
3015 */
3016 for (i = 0; i < NSP32_HOST_SCSIID; i++) {
3017 target = &data->target[i];
3018 if (auto_sync == TRUE) {
3019 target->limit_entry = 0; /* set as ULTRA20M */
3020 } else {
3021 ret = nsp32_prom_read(data, i);
3022 entry = nsp32_search_period_entry(data, target, ret);
3023 if (entry < 0) {
3024 /* search failed... set maximum speed */
3025 entry = 0;
3026 }
3027 target->limit_entry = entry;
3028 }
3029 }
3030
3031 return TRUE;
3032 }
3033
3034
3035 /*
3036 * C16 110 (I-O Data: SC-NBD) data map:
3037 *
3038 * ROMADDR
3039 * 0x00 - 0x06 : Device Synchronous Transfer Period (SCSI ID 0 - 6)
3040 * Value 0x0: 20MB/S, 0x1: 10MB/S, 0x2: 5MB/S, 0x3: ASYNC
3041 * 0x07 : 0 (HBA Synchronous Transfer Period: Auto Sync)
3042 * 0x08 - 0x0f : Not Used? (0x0)
3043 * 0x10 : Transfer Mode
3044 * Value 0: PIO, 1: Busmater
3045 * 0x11 : Bus Reset Delay Time (0x00-0x20)
3046 * 0x12 : Bus Termination
3047 * Value 0: Disable, 1: Enable
3048 * 0x13 - 0x19 : Disconnection
3049 * Value 0: Disable, 1: Enable
3050 * 0x1a - 0x7c : Not Used? (0)
3051 * 0x7d : Not Used? (0xf8)
3052 * 0x7e : Constant (0x55), Validity signature
3053 * 0x7f : Constant (0xaa), Validity signature
3054 */
nsp32_getprom_c16(nsp32_hw_data * data)3055 static int nsp32_getprom_c16(nsp32_hw_data *data)
3056 {
3057 int ret, i;
3058 nsp32_target *target;
3059 int entry, val;
3060
3061 /*
3062 * Reset time which is designated by EEPROM.
3063 *
3064 * TODO: Not used yet.
3065 */
3066 data->resettime = nsp32_prom_read(data, 0x11);
3067
3068 /*
3069 * each device Synchronous Transfer Period
3070 */
3071 for (i = 0; i < NSP32_HOST_SCSIID; i++) {
3072 target = &data->target[i];
3073 ret = nsp32_prom_read(data, i);
3074 switch (ret) {
3075 case 0: /* 20MB/s */
3076 val = 0x0c;
3077 break;
3078 case 1: /* 10MB/s */
3079 val = 0x19;
3080 break;
3081 case 2: /* 5MB/s */
3082 val = 0x32;
3083 break;
3084 case 3: /* ASYNC */
3085 val = 0x00;
3086 break;
3087 default: /* default 20MB/s */
3088 val = 0x0c;
3089 break;
3090 }
3091 entry = nsp32_search_period_entry(data, target, val);
3092 if (entry < 0 || trans_mode == ULTRA20M_MODE) {
3093 /* search failed... set maximum speed */
3094 entry = 0;
3095 }
3096 target->limit_entry = entry;
3097 }
3098
3099 return TRUE;
3100 }
3101
3102
3103 /*
3104 * Atmel AT24C01A (drived in 5V) serial EEPROM routines
3105 */
nsp32_prom_read(nsp32_hw_data * data,int romaddr)3106 static int nsp32_prom_read(nsp32_hw_data *data, int romaddr)
3107 {
3108 int i, val;
3109
3110 /* start condition */
3111 nsp32_prom_start(data);
3112
3113 /* device address */
3114 nsp32_prom_write_bit(data, 1); /* 1 */
3115 nsp32_prom_write_bit(data, 0); /* 0 */
3116 nsp32_prom_write_bit(data, 1); /* 1 */
3117 nsp32_prom_write_bit(data, 0); /* 0 */
3118 nsp32_prom_write_bit(data, 0); /* A2: 0 (GND) */
3119 nsp32_prom_write_bit(data, 0); /* A1: 0 (GND) */
3120 nsp32_prom_write_bit(data, 0); /* A0: 0 (GND) */
3121
3122 /* R/W: W for dummy write */
3123 nsp32_prom_write_bit(data, 0);
3124
3125 /* ack */
3126 nsp32_prom_write_bit(data, 0);
3127
3128 /* word address */
3129 for (i = 7; i >= 0; i--) {
3130 nsp32_prom_write_bit(data, ((romaddr >> i) & 1));
3131 }
3132
3133 /* ack */
3134 nsp32_prom_write_bit(data, 0);
3135
3136 /* start condition */
3137 nsp32_prom_start(data);
3138
3139 /* device address */
3140 nsp32_prom_write_bit(data, 1); /* 1 */
3141 nsp32_prom_write_bit(data, 0); /* 0 */
3142 nsp32_prom_write_bit(data, 1); /* 1 */
3143 nsp32_prom_write_bit(data, 0); /* 0 */
3144 nsp32_prom_write_bit(data, 0); /* A2: 0 (GND) */
3145 nsp32_prom_write_bit(data, 0); /* A1: 0 (GND) */
3146 nsp32_prom_write_bit(data, 0); /* A0: 0 (GND) */
3147
3148 /* R/W: R */
3149 nsp32_prom_write_bit(data, 1);
3150
3151 /* ack */
3152 nsp32_prom_write_bit(data, 0);
3153
3154 /* data... */
3155 val = 0;
3156 for (i = 7; i >= 0; i--) {
3157 val += (nsp32_prom_read_bit(data) << i);
3158 }
3159
3160 /* no ack */
3161 nsp32_prom_write_bit(data, 1);
3162
3163 /* stop condition */
3164 nsp32_prom_stop(data);
3165
3166 return val;
3167 }
3168
nsp32_prom_set(nsp32_hw_data * data,int bit,int val)3169 static void nsp32_prom_set(nsp32_hw_data *data, int bit, int val)
3170 {
3171 int base = data->BaseAddress;
3172 int tmp;
3173
3174 tmp = nsp32_index_read1(base, SERIAL_ROM_CTL);
3175
3176 if (val == 0) {
3177 tmp &= ~bit;
3178 } else {
3179 tmp |= bit;
3180 }
3181
3182 nsp32_index_write1(base, SERIAL_ROM_CTL, tmp);
3183
3184 udelay(10);
3185 }
3186
nsp32_prom_get(nsp32_hw_data * data,int bit)3187 static int nsp32_prom_get(nsp32_hw_data *data, int bit)
3188 {
3189 int base = data->BaseAddress;
3190 int tmp, ret;
3191
3192 if (bit != SDA) {
3193 nsp32_msg(KERN_ERR, "return value is not appropriate");
3194 return 0;
3195 }
3196
3197
3198 tmp = nsp32_index_read1(base, SERIAL_ROM_CTL) & bit;
3199
3200 if (tmp == 0) {
3201 ret = 0;
3202 } else {
3203 ret = 1;
3204 }
3205
3206 udelay(10);
3207
3208 return ret;
3209 }
3210
nsp32_prom_start(nsp32_hw_data * data)3211 static void nsp32_prom_start (nsp32_hw_data *data)
3212 {
3213 /* start condition */
3214 nsp32_prom_set(data, SCL, 1);
3215 nsp32_prom_set(data, SDA, 1);
3216 nsp32_prom_set(data, ENA, 1); /* output mode */
3217 nsp32_prom_set(data, SDA, 0); /* keeping SCL=1 and transiting
3218 * SDA 1->0 is start condition */
3219 nsp32_prom_set(data, SCL, 0);
3220 }
3221
nsp32_prom_stop(nsp32_hw_data * data)3222 static void nsp32_prom_stop (nsp32_hw_data *data)
3223 {
3224 /* stop condition */
3225 nsp32_prom_set(data, SCL, 1);
3226 nsp32_prom_set(data, SDA, 0);
3227 nsp32_prom_set(data, ENA, 1); /* output mode */
3228 nsp32_prom_set(data, SDA, 1);
3229 nsp32_prom_set(data, SCL, 0);
3230 }
3231
nsp32_prom_write_bit(nsp32_hw_data * data,int val)3232 static void nsp32_prom_write_bit(nsp32_hw_data *data, int val)
3233 {
3234 /* write */
3235 nsp32_prom_set(data, SDA, val);
3236 nsp32_prom_set(data, SCL, 1 );
3237 nsp32_prom_set(data, SCL, 0 );
3238 }
3239
nsp32_prom_read_bit(nsp32_hw_data * data)3240 static int nsp32_prom_read_bit(nsp32_hw_data *data)
3241 {
3242 int val;
3243
3244 /* read */
3245 nsp32_prom_set(data, ENA, 0); /* input mode */
3246 nsp32_prom_set(data, SCL, 1);
3247
3248 val = nsp32_prom_get(data, SDA);
3249
3250 nsp32_prom_set(data, SCL, 0);
3251 nsp32_prom_set(data, ENA, 1); /* output mode */
3252
3253 return val;
3254 }
3255
3256
3257 /**************************************************************************
3258 * Power Management
3259 */
3260 #ifdef CONFIG_PM
3261
3262 /* Device suspended */
nsp32_suspend(struct pci_dev * pdev,pm_message_t state)3263 static int nsp32_suspend(struct pci_dev *pdev, pm_message_t state)
3264 {
3265 struct Scsi_Host *host = pci_get_drvdata(pdev);
3266
3267 nsp32_msg(KERN_INFO, "pci-suspend: pdev=0x%p, state.event=%x, slot=%s, host=0x%p",
3268 pdev, state.event, pci_name(pdev), host);
3269
3270 pci_save_state (pdev);
3271 pci_disable_device (pdev);
3272 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3273
3274 return 0;
3275 }
3276
3277 /* Device woken up */
nsp32_resume(struct pci_dev * pdev)3278 static int nsp32_resume(struct pci_dev *pdev)
3279 {
3280 struct Scsi_Host *host = pci_get_drvdata(pdev);
3281 nsp32_hw_data *data = (nsp32_hw_data *)host->hostdata;
3282 unsigned short reg;
3283
3284 nsp32_msg(KERN_INFO, "pci-resume: pdev=0x%p, slot=%s, host=0x%p", pdev, pci_name(pdev), host);
3285
3286 pci_set_power_state(pdev, PCI_D0);
3287 pci_enable_wake (pdev, PCI_D0, 0);
3288 pci_restore_state (pdev);
3289
3290 reg = nsp32_read2(data->BaseAddress, INDEX_REG);
3291
3292 nsp32_msg(KERN_INFO, "io=0x%x reg=0x%x", data->BaseAddress, reg);
3293
3294 if (reg == 0xffff) {
3295 nsp32_msg(KERN_INFO, "missing device. abort resume.");
3296 return 0;
3297 }
3298
3299 nsp32hw_init (data);
3300 nsp32_do_bus_reset(data);
3301
3302 nsp32_msg(KERN_INFO, "resume success");
3303
3304 return 0;
3305 }
3306
3307 #endif
3308
3309 /************************************************************************
3310 * PCI/Cardbus probe/remove routine
3311 */
nsp32_probe(struct pci_dev * pdev,const struct pci_device_id * id)3312 static int nsp32_probe(struct pci_dev *pdev, const struct pci_device_id *id)
3313 {
3314 int ret;
3315 nsp32_hw_data *data = &nsp32_data_base;
3316
3317 nsp32_dbg(NSP32_DEBUG_REGISTER, "enter");
3318
3319 ret = pci_enable_device(pdev);
3320 if (ret) {
3321 nsp32_msg(KERN_ERR, "failed to enable pci device");
3322 return ret;
3323 }
3324
3325 data->Pci = pdev;
3326 data->pci_devid = id;
3327 data->IrqNumber = pdev->irq;
3328 data->BaseAddress = pci_resource_start(pdev, 0);
3329 data->NumAddress = pci_resource_len (pdev, 0);
3330 data->MmioAddress = pci_ioremap_bar(pdev, 1);
3331 data->MmioLength = pci_resource_len (pdev, 1);
3332
3333 pci_set_master(pdev);
3334
3335 ret = nsp32_detect(pdev);
3336
3337 nsp32_msg(KERN_INFO, "irq: %i mmio: %p+0x%lx slot: %s model: %s",
3338 pdev->irq,
3339 data->MmioAddress, data->MmioLength,
3340 pci_name(pdev),
3341 nsp32_model[id->driver_data]);
3342
3343 nsp32_dbg(NSP32_DEBUG_REGISTER, "exit %d", ret);
3344
3345 return ret;
3346 }
3347
nsp32_remove(struct pci_dev * pdev)3348 static void nsp32_remove(struct pci_dev *pdev)
3349 {
3350 struct Scsi_Host *host = pci_get_drvdata(pdev);
3351
3352 nsp32_dbg(NSP32_DEBUG_REGISTER, "enter");
3353
3354 scsi_remove_host(host);
3355
3356 nsp32_release(host);
3357
3358 scsi_host_put(host);
3359 }
3360
3361 static struct pci_driver nsp32_driver = {
3362 .name = "nsp32",
3363 .id_table = nsp32_pci_table,
3364 .probe = nsp32_probe,
3365 .remove = nsp32_remove,
3366 #ifdef CONFIG_PM
3367 .suspend = nsp32_suspend,
3368 .resume = nsp32_resume,
3369 #endif
3370 };
3371
3372 /*********************************************************************
3373 * Moule entry point
3374 */
init_nsp32(void)3375 static int __init init_nsp32(void) {
3376 nsp32_msg(KERN_INFO, "loading...");
3377 return pci_register_driver(&nsp32_driver);
3378 }
3379
exit_nsp32(void)3380 static void __exit exit_nsp32(void) {
3381 nsp32_msg(KERN_INFO, "unloading...");
3382 pci_unregister_driver(&nsp32_driver);
3383 }
3384
3385 module_init(init_nsp32);
3386 module_exit(exit_nsp32);
3387
3388 /* end */
3389