1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * intel TCO Watchdog Driver
4 *
5 * (c) Copyright 2006-2011 Wim Van Sebroeck <wim@iguana.be>.
6 *
7 * Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
8 * provide warranty for any of this software. This material is
9 * provided "AS-IS" and at no charge.
10 *
11 * The TCO watchdog is implemented in the following I/O controller hubs:
12 * (See the intel documentation on http://developer.intel.com.)
13 * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
14 * document number 290687-002, 298242-027: 82801BA (ICH2)
15 * document number 290733-003, 290739-013: 82801CA (ICH3-S)
16 * document number 290716-001, 290718-007: 82801CAM (ICH3-M)
17 * document number 290744-001, 290745-025: 82801DB (ICH4)
18 * document number 252337-001, 252663-008: 82801DBM (ICH4-M)
19 * document number 273599-001, 273645-002: 82801E (C-ICH)
20 * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
21 * document number 300641-004, 300884-013: 6300ESB
22 * document number 301473-002, 301474-026: 82801F (ICH6)
23 * document number 313082-001, 313075-006: 631xESB, 632xESB
24 * document number 307013-003, 307014-024: 82801G (ICH7)
25 * document number 322896-001, 322897-001: NM10
26 * document number 313056-003, 313057-017: 82801H (ICH8)
27 * document number 316972-004, 316973-012: 82801I (ICH9)
28 * document number 319973-002, 319974-002: 82801J (ICH10)
29 * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
30 * document number 320066-003, 320257-008: EP80597 (IICH)
31 * document number 324645-001, 324646-001: Cougar Point (CPT)
32 * document number TBD : Patsburg (PBG)
33 * document number TBD : DH89xxCC
34 * document number TBD : Panther Point
35 * document number TBD : Lynx Point
36 * document number TBD : Lynx Point-LP
37 */
38
39 /*
40 * Includes, defines, variables, module parameters, ...
41 */
42
43 /* Module and version information */
44 #define DRV_NAME "iTCO_wdt"
45 #define DRV_VERSION "1.11"
46
47 /* Includes */
48 #include <linux/acpi.h> /* For ACPI support */
49 #include <linux/bits.h> /* For BIT() */
50 #include <linux/module.h> /* For module specific items */
51 #include <linux/moduleparam.h> /* For new moduleparam's */
52 #include <linux/types.h> /* For standard types (like size_t) */
53 #include <linux/errno.h> /* For the -ENODEV/... values */
54 #include <linux/kernel.h> /* For printk/panic/... */
55 #include <linux/watchdog.h> /* For the watchdog specific items */
56 #include <linux/init.h> /* For __init/__exit/... */
57 #include <linux/fs.h> /* For file operations */
58 #include <linux/platform_device.h> /* For platform_driver framework */
59 #include <linux/pci.h> /* For pci functions */
60 #include <linux/ioport.h> /* For io-port access */
61 #include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */
62 #include <linux/uaccess.h> /* For copy_to_user/put_user/... */
63 #include <linux/io.h> /* For inb/outb/... */
64 #include <linux/platform_data/itco_wdt.h>
65 #include <linux/mfd/intel_pmc_bxt.h>
66
67 #include "iTCO_vendor.h"
68
69 /* Address definitions for the TCO */
70 /* TCO base address */
71 #define TCOBASE(p) ((p)->tco_res->start)
72 /* SMI Control and Enable Register */
73 #define SMI_EN(p) ((p)->smi_res->start)
74
75 #define TCO_RLD(p) (TCOBASE(p) + 0x00) /* TCO Timer Reload/Curr. Value */
76 #define TCOv1_TMR(p) (TCOBASE(p) + 0x01) /* TCOv1 Timer Initial Value*/
77 #define TCO_DAT_IN(p) (TCOBASE(p) + 0x02) /* TCO Data In Register */
78 #define TCO_DAT_OUT(p) (TCOBASE(p) + 0x03) /* TCO Data Out Register */
79 #define TCO1_STS(p) (TCOBASE(p) + 0x04) /* TCO1 Status Register */
80 #define TCO2_STS(p) (TCOBASE(p) + 0x06) /* TCO2 Status Register */
81 #define TCO1_CNT(p) (TCOBASE(p) + 0x08) /* TCO1 Control Register */
82 #define TCO2_CNT(p) (TCOBASE(p) + 0x0a) /* TCO2 Control Register */
83 #define TCOv2_TMR(p) (TCOBASE(p) + 0x12) /* TCOv2 Timer Initial Value*/
84
85 /* internal variables */
86 struct iTCO_wdt_private {
87 struct watchdog_device wddev;
88
89 /* TCO version/generation */
90 unsigned int iTCO_version;
91 struct resource *tco_res;
92 struct resource *smi_res;
93 /*
94 * NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2),
95 * or memory-mapped PMC register bit 4 (TCO version 3).
96 */
97 struct resource *gcs_pmc_res;
98 unsigned long __iomem *gcs_pmc;
99 /* the lock for io operations */
100 spinlock_t io_lock;
101 /* the PCI-device */
102 struct pci_dev *pci_dev;
103 /* whether or not the watchdog has been suspended */
104 bool suspended;
105 /* no reboot API private data */
106 void *no_reboot_priv;
107 /* no reboot update function pointer */
108 int (*update_no_reboot_bit)(void *p, bool set);
109 };
110
111 /* module parameters */
112 #define WATCHDOG_TIMEOUT 30 /* 30 sec default heartbeat */
113 static int heartbeat = WATCHDOG_TIMEOUT; /* in seconds */
114 module_param(heartbeat, int, 0);
115 MODULE_PARM_DESC(heartbeat, "Watchdog timeout in seconds. "
116 "5..76 (TCO v1) or 3..614 (TCO v2), default="
117 __MODULE_STRING(WATCHDOG_TIMEOUT) ")");
118
119 static bool nowayout = WATCHDOG_NOWAYOUT;
120 module_param(nowayout, bool, 0);
121 MODULE_PARM_DESC(nowayout,
122 "Watchdog cannot be stopped once started (default="
123 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
124
125 static int turn_SMI_watchdog_clear_off = 1;
126 module_param(turn_SMI_watchdog_clear_off, int, 0);
127 MODULE_PARM_DESC(turn_SMI_watchdog_clear_off,
128 "Turn off SMI clearing watchdog (depends on TCO-version)(default=1)");
129
130 /*
131 * Some TCO specific functions
132 */
133
134 /*
135 * The iTCO v1 and v2's internal timer is stored as ticks which decrement
136 * every 0.6 seconds. v3's internal timer is stored as seconds (some
137 * datasheets incorrectly state 0.6 seconds).
138 */
seconds_to_ticks(struct iTCO_wdt_private * p,int secs)139 static inline unsigned int seconds_to_ticks(struct iTCO_wdt_private *p,
140 int secs)
141 {
142 return p->iTCO_version == 3 ? secs : (secs * 10) / 6;
143 }
144
ticks_to_seconds(struct iTCO_wdt_private * p,int ticks)145 static inline unsigned int ticks_to_seconds(struct iTCO_wdt_private *p,
146 int ticks)
147 {
148 return p->iTCO_version == 3 ? ticks : (ticks * 6) / 10;
149 }
150
no_reboot_bit(struct iTCO_wdt_private * p)151 static inline u32 no_reboot_bit(struct iTCO_wdt_private *p)
152 {
153 u32 enable_bit;
154
155 switch (p->iTCO_version) {
156 case 5:
157 case 3:
158 enable_bit = 0x00000010;
159 break;
160 case 2:
161 enable_bit = 0x00000020;
162 break;
163 case 4:
164 case 1:
165 default:
166 enable_bit = 0x00000002;
167 break;
168 }
169
170 return enable_bit;
171 }
172
update_no_reboot_bit_def(void * priv,bool set)173 static int update_no_reboot_bit_def(void *priv, bool set)
174 {
175 return 0;
176 }
177
update_no_reboot_bit_pci(void * priv,bool set)178 static int update_no_reboot_bit_pci(void *priv, bool set)
179 {
180 struct iTCO_wdt_private *p = priv;
181 u32 val32 = 0, newval32 = 0;
182
183 pci_read_config_dword(p->pci_dev, 0xd4, &val32);
184 if (set)
185 val32 |= no_reboot_bit(p);
186 else
187 val32 &= ~no_reboot_bit(p);
188 pci_write_config_dword(p->pci_dev, 0xd4, val32);
189 pci_read_config_dword(p->pci_dev, 0xd4, &newval32);
190
191 /* make sure the update is successful */
192 if (val32 != newval32)
193 return -EIO;
194
195 return 0;
196 }
197
update_no_reboot_bit_mem(void * priv,bool set)198 static int update_no_reboot_bit_mem(void *priv, bool set)
199 {
200 struct iTCO_wdt_private *p = priv;
201 u32 val32 = 0, newval32 = 0;
202
203 val32 = readl(p->gcs_pmc);
204 if (set)
205 val32 |= no_reboot_bit(p);
206 else
207 val32 &= ~no_reboot_bit(p);
208 writel(val32, p->gcs_pmc);
209 newval32 = readl(p->gcs_pmc);
210
211 /* make sure the update is successful */
212 if (val32 != newval32)
213 return -EIO;
214
215 return 0;
216 }
217
update_no_reboot_bit_cnt(void * priv,bool set)218 static int update_no_reboot_bit_cnt(void *priv, bool set)
219 {
220 struct iTCO_wdt_private *p = priv;
221 u16 val, newval;
222
223 val = inw(TCO1_CNT(p));
224 if (set)
225 val |= BIT(0);
226 else
227 val &= ~BIT(0);
228 outw(val, TCO1_CNT(p));
229 newval = inw(TCO1_CNT(p));
230
231 /* make sure the update is successful */
232 return val != newval ? -EIO : 0;
233 }
234
update_no_reboot_bit_pmc(void * priv,bool set)235 static int update_no_reboot_bit_pmc(void *priv, bool set)
236 {
237 struct intel_pmc_dev *pmc = priv;
238 u32 bits = PMC_CFG_NO_REBOOT_EN;
239 u32 value = set ? bits : 0;
240
241 return intel_pmc_gcr_update(pmc, PMC_GCR_PMC_CFG_REG, bits, value);
242 }
243
iTCO_wdt_no_reboot_bit_setup(struct iTCO_wdt_private * p,struct platform_device * pdev,struct itco_wdt_platform_data * pdata)244 static void iTCO_wdt_no_reboot_bit_setup(struct iTCO_wdt_private *p,
245 struct platform_device *pdev,
246 struct itco_wdt_platform_data *pdata)
247 {
248 if (pdata->no_reboot_use_pmc) {
249 struct intel_pmc_dev *pmc = dev_get_drvdata(pdev->dev.parent);
250
251 p->update_no_reboot_bit = update_no_reboot_bit_pmc;
252 p->no_reboot_priv = pmc;
253 return;
254 }
255
256 if (p->iTCO_version >= 6)
257 p->update_no_reboot_bit = update_no_reboot_bit_cnt;
258 else if (p->iTCO_version >= 2)
259 p->update_no_reboot_bit = update_no_reboot_bit_mem;
260 else if (p->iTCO_version == 1)
261 p->update_no_reboot_bit = update_no_reboot_bit_pci;
262 else
263 p->update_no_reboot_bit = update_no_reboot_bit_def;
264
265 p->no_reboot_priv = p;
266 }
267
iTCO_wdt_start(struct watchdog_device * wd_dev)268 static int iTCO_wdt_start(struct watchdog_device *wd_dev)
269 {
270 struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
271 unsigned int val;
272
273 spin_lock(&p->io_lock);
274
275 iTCO_vendor_pre_start(p->smi_res, wd_dev->timeout);
276
277 /* disable chipset's NO_REBOOT bit */
278 if (p->update_no_reboot_bit(p->no_reboot_priv, false)) {
279 spin_unlock(&p->io_lock);
280 dev_err(wd_dev->parent, "failed to reset NO_REBOOT flag, reboot disabled by hardware/BIOS\n");
281 return -EIO;
282 }
283
284 /* Force the timer to its reload value by writing to the TCO_RLD
285 register */
286 if (p->iTCO_version >= 2)
287 outw(0x01, TCO_RLD(p));
288 else if (p->iTCO_version == 1)
289 outb(0x01, TCO_RLD(p));
290
291 /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */
292 val = inw(TCO1_CNT(p));
293 val &= 0xf7ff;
294 outw(val, TCO1_CNT(p));
295 val = inw(TCO1_CNT(p));
296 spin_unlock(&p->io_lock);
297
298 if (val & 0x0800)
299 return -1;
300 return 0;
301 }
302
iTCO_wdt_stop(struct watchdog_device * wd_dev)303 static int iTCO_wdt_stop(struct watchdog_device *wd_dev)
304 {
305 struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
306 unsigned int val;
307
308 spin_lock(&p->io_lock);
309
310 iTCO_vendor_pre_stop(p->smi_res);
311
312 /* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */
313 val = inw(TCO1_CNT(p));
314 val |= 0x0800;
315 outw(val, TCO1_CNT(p));
316 val = inw(TCO1_CNT(p));
317
318 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
319 p->update_no_reboot_bit(p->no_reboot_priv, true);
320
321 spin_unlock(&p->io_lock);
322
323 if ((val & 0x0800) == 0)
324 return -1;
325 return 0;
326 }
327
iTCO_wdt_ping(struct watchdog_device * wd_dev)328 static int iTCO_wdt_ping(struct watchdog_device *wd_dev)
329 {
330 struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
331
332 spin_lock(&p->io_lock);
333
334 /* Reload the timer by writing to the TCO Timer Counter register */
335 if (p->iTCO_version >= 2) {
336 outw(0x01, TCO_RLD(p));
337 } else if (p->iTCO_version == 1) {
338 /* Reset the timeout status bit so that the timer
339 * needs to count down twice again before rebooting */
340 outw(0x0008, TCO1_STS(p)); /* write 1 to clear bit */
341
342 outb(0x01, TCO_RLD(p));
343 }
344
345 spin_unlock(&p->io_lock);
346 return 0;
347 }
348
iTCO_wdt_set_timeout(struct watchdog_device * wd_dev,unsigned int t)349 static int iTCO_wdt_set_timeout(struct watchdog_device *wd_dev, unsigned int t)
350 {
351 struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
352 unsigned int val16;
353 unsigned char val8;
354 unsigned int tmrval;
355
356 tmrval = seconds_to_ticks(p, t);
357
358 /* For TCO v1 the timer counts down twice before rebooting */
359 if (p->iTCO_version == 1)
360 tmrval /= 2;
361
362 /* from the specs: */
363 /* "Values of 0h-3h are ignored and should not be attempted" */
364 if (tmrval < 0x04)
365 return -EINVAL;
366 if ((p->iTCO_version >= 2 && tmrval > 0x3ff) ||
367 (p->iTCO_version == 1 && tmrval > 0x03f))
368 return -EINVAL;
369
370 /* Write new heartbeat to watchdog */
371 if (p->iTCO_version >= 2) {
372 spin_lock(&p->io_lock);
373 val16 = inw(TCOv2_TMR(p));
374 val16 &= 0xfc00;
375 val16 |= tmrval;
376 outw(val16, TCOv2_TMR(p));
377 val16 = inw(TCOv2_TMR(p));
378 spin_unlock(&p->io_lock);
379
380 if ((val16 & 0x3ff) != tmrval)
381 return -EINVAL;
382 } else if (p->iTCO_version == 1) {
383 spin_lock(&p->io_lock);
384 val8 = inb(TCOv1_TMR(p));
385 val8 &= 0xc0;
386 val8 |= (tmrval & 0xff);
387 outb(val8, TCOv1_TMR(p));
388 val8 = inb(TCOv1_TMR(p));
389 spin_unlock(&p->io_lock);
390
391 if ((val8 & 0x3f) != tmrval)
392 return -EINVAL;
393 }
394
395 wd_dev->timeout = t;
396 return 0;
397 }
398
iTCO_wdt_get_timeleft(struct watchdog_device * wd_dev)399 static unsigned int iTCO_wdt_get_timeleft(struct watchdog_device *wd_dev)
400 {
401 struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
402 unsigned int val16;
403 unsigned char val8;
404 unsigned int time_left = 0;
405
406 /* read the TCO Timer */
407 if (p->iTCO_version >= 2) {
408 spin_lock(&p->io_lock);
409 val16 = inw(TCO_RLD(p));
410 val16 &= 0x3ff;
411 spin_unlock(&p->io_lock);
412
413 time_left = ticks_to_seconds(p, val16);
414 } else if (p->iTCO_version == 1) {
415 spin_lock(&p->io_lock);
416 val8 = inb(TCO_RLD(p));
417 val8 &= 0x3f;
418 if (!(inw(TCO1_STS(p)) & 0x0008))
419 val8 += (inb(TCOv1_TMR(p)) & 0x3f);
420 spin_unlock(&p->io_lock);
421
422 time_left = ticks_to_seconds(p, val8);
423 }
424 return time_left;
425 }
426
427 /*
428 * Kernel Interfaces
429 */
430
431 static const struct watchdog_info ident = {
432 .options = WDIOF_SETTIMEOUT |
433 WDIOF_KEEPALIVEPING |
434 WDIOF_MAGICCLOSE,
435 .firmware_version = 0,
436 .identity = DRV_NAME,
437 };
438
439 static const struct watchdog_ops iTCO_wdt_ops = {
440 .owner = THIS_MODULE,
441 .start = iTCO_wdt_start,
442 .stop = iTCO_wdt_stop,
443 .ping = iTCO_wdt_ping,
444 .set_timeout = iTCO_wdt_set_timeout,
445 .get_timeleft = iTCO_wdt_get_timeleft,
446 };
447
448 /*
449 * Init & exit routines
450 */
451
iTCO_wdt_probe(struct platform_device * pdev)452 static int iTCO_wdt_probe(struct platform_device *pdev)
453 {
454 struct device *dev = &pdev->dev;
455 struct itco_wdt_platform_data *pdata = dev_get_platdata(dev);
456 struct iTCO_wdt_private *p;
457 unsigned long val32;
458 int ret;
459
460 if (!pdata)
461 return -ENODEV;
462
463 p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
464 if (!p)
465 return -ENOMEM;
466
467 spin_lock_init(&p->io_lock);
468
469 p->tco_res = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_IO_TCO);
470 if (!p->tco_res)
471 return -ENODEV;
472
473 p->iTCO_version = pdata->version;
474 p->pci_dev = to_pci_dev(dev->parent);
475
476 p->smi_res = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_IO_SMI);
477 if (p->smi_res) {
478 /* The TCO logic uses the TCO_EN bit in the SMI_EN register */
479 if (!devm_request_region(dev, p->smi_res->start,
480 resource_size(p->smi_res),
481 pdev->name)) {
482 pr_err("I/O address 0x%04llx already in use, device disabled\n",
483 (u64)SMI_EN(p));
484 return -EBUSY;
485 }
486 } else if (iTCO_vendorsupport ||
487 turn_SMI_watchdog_clear_off >= p->iTCO_version) {
488 pr_err("SMI I/O resource is missing\n");
489 return -ENODEV;
490 }
491
492 iTCO_wdt_no_reboot_bit_setup(p, pdev, pdata);
493
494 /*
495 * Get the Memory-Mapped GCS or PMC register, we need it for the
496 * NO_REBOOT flag (TCO v2 and v3).
497 */
498 if (p->iTCO_version >= 2 && p->iTCO_version < 6 &&
499 !pdata->no_reboot_use_pmc) {
500 p->gcs_pmc_res = platform_get_resource(pdev,
501 IORESOURCE_MEM,
502 ICH_RES_MEM_GCS_PMC);
503 p->gcs_pmc = devm_ioremap_resource(dev, p->gcs_pmc_res);
504 if (IS_ERR(p->gcs_pmc))
505 return PTR_ERR(p->gcs_pmc);
506 }
507
508 /* Check chipset's NO_REBOOT bit */
509 if (p->update_no_reboot_bit(p->no_reboot_priv, false) &&
510 iTCO_vendor_check_noreboot_on()) {
511 dev_info(dev, "unable to reset NO_REBOOT flag, device disabled by hardware/BIOS\n");
512 return -ENODEV; /* Cannot reset NO_REBOOT bit */
513 }
514
515 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
516 p->update_no_reboot_bit(p->no_reboot_priv, true);
517
518 if (turn_SMI_watchdog_clear_off >= p->iTCO_version) {
519 /*
520 * Bit 13: TCO_EN -> 0
521 * Disables TCO logic generating an SMI#
522 */
523 val32 = inl(SMI_EN(p));
524 val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */
525 outl(val32, SMI_EN(p));
526 }
527
528 if (!devm_request_region(dev, p->tco_res->start,
529 resource_size(p->tco_res),
530 pdev->name)) {
531 dev_err(dev, "I/O address 0x%04llx already in use, device disabled\n",
532 (u64)TCOBASE(p));
533 return -EBUSY;
534 }
535
536 dev_info(dev, "Found a %s TCO device (Version=%d, TCOBASE=0x%04llx)\n",
537 pdata->name, pdata->version, (u64)TCOBASE(p));
538
539 /* Clear out the (probably old) status */
540 switch (p->iTCO_version) {
541 case 6:
542 case 5:
543 case 4:
544 outw(0x0008, TCO1_STS(p)); /* Clear the Time Out Status bit */
545 outw(0x0002, TCO2_STS(p)); /* Clear SECOND_TO_STS bit */
546 break;
547 case 3:
548 outl(0x20008, TCO1_STS(p));
549 break;
550 case 2:
551 case 1:
552 default:
553 outw(0x0008, TCO1_STS(p)); /* Clear the Time Out Status bit */
554 outw(0x0002, TCO2_STS(p)); /* Clear SECOND_TO_STS bit */
555 outw(0x0004, TCO2_STS(p)); /* Clear BOOT_STS bit */
556 break;
557 }
558
559 p->wddev.info = &ident,
560 p->wddev.ops = &iTCO_wdt_ops,
561 p->wddev.bootstatus = 0;
562 p->wddev.timeout = WATCHDOG_TIMEOUT;
563 watchdog_set_nowayout(&p->wddev, nowayout);
564 p->wddev.parent = dev;
565
566 watchdog_set_drvdata(&p->wddev, p);
567 platform_set_drvdata(pdev, p);
568
569 /* Make sure the watchdog is not running */
570 iTCO_wdt_stop(&p->wddev);
571
572 /* Check that the heartbeat value is within it's range;
573 if not reset to the default */
574 if (iTCO_wdt_set_timeout(&p->wddev, heartbeat)) {
575 iTCO_wdt_set_timeout(&p->wddev, WATCHDOG_TIMEOUT);
576 dev_info(dev, "timeout value out of range, using %d\n",
577 WATCHDOG_TIMEOUT);
578 }
579
580 watchdog_stop_on_reboot(&p->wddev);
581 watchdog_stop_on_unregister(&p->wddev);
582 ret = devm_watchdog_register_device(dev, &p->wddev);
583 if (ret != 0) {
584 dev_err(dev, "cannot register watchdog device (err=%d)\n", ret);
585 return ret;
586 }
587
588 dev_info(dev, "initialized. heartbeat=%d sec (nowayout=%d)\n",
589 heartbeat, nowayout);
590
591 return 0;
592 }
593
594 #ifdef CONFIG_PM_SLEEP
595 /*
596 * Suspend-to-idle requires this, because it stops the ticks and timekeeping, so
597 * the watchdog cannot be pinged while in that state. In ACPI sleep states the
598 * watchdog is stopped by the platform firmware.
599 */
600
601 #ifdef CONFIG_ACPI
need_suspend(void)602 static inline bool need_suspend(void)
603 {
604 return acpi_target_system_state() == ACPI_STATE_S0;
605 }
606 #else
need_suspend(void)607 static inline bool need_suspend(void) { return true; }
608 #endif
609
iTCO_wdt_suspend_noirq(struct device * dev)610 static int iTCO_wdt_suspend_noirq(struct device *dev)
611 {
612 struct iTCO_wdt_private *p = dev_get_drvdata(dev);
613 int ret = 0;
614
615 p->suspended = false;
616 if (watchdog_active(&p->wddev) && need_suspend()) {
617 ret = iTCO_wdt_stop(&p->wddev);
618 if (!ret)
619 p->suspended = true;
620 }
621 return ret;
622 }
623
iTCO_wdt_resume_noirq(struct device * dev)624 static int iTCO_wdt_resume_noirq(struct device *dev)
625 {
626 struct iTCO_wdt_private *p = dev_get_drvdata(dev);
627
628 if (p->suspended)
629 iTCO_wdt_start(&p->wddev);
630
631 return 0;
632 }
633
634 static const struct dev_pm_ops iTCO_wdt_pm = {
635 .suspend_noirq = iTCO_wdt_suspend_noirq,
636 .resume_noirq = iTCO_wdt_resume_noirq,
637 };
638
639 #define ITCO_WDT_PM_OPS (&iTCO_wdt_pm)
640 #else
641 #define ITCO_WDT_PM_OPS NULL
642 #endif /* CONFIG_PM_SLEEP */
643
644 static struct platform_driver iTCO_wdt_driver = {
645 .probe = iTCO_wdt_probe,
646 .driver = {
647 .name = DRV_NAME,
648 .pm = ITCO_WDT_PM_OPS,
649 },
650 };
651
652 module_platform_driver(iTCO_wdt_driver);
653
654 MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>");
655 MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver");
656 MODULE_VERSION(DRV_VERSION);
657 MODULE_LICENSE("GPL");
658 MODULE_ALIAS("platform:" DRV_NAME);
659