1// cmd/9l/optab.c, cmd/9l/asmout.c from Vita Nuova. 2// 3// Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 4// Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net) 5// Portions Copyright © 1997-1999 Vita Nuova Limited 6// Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com) 7// Portions Copyright © 2004,2006 Bruce Ellis 8// Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net) 9// Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others 10// Portions Copyright © 2009 The Go Authors. All rights reserved. 11// 12// Permission is hereby granted, free of charge, to any person obtaining a copy 13// of this software and associated documentation files (the "Software"), to deal 14// in the Software without restriction, including without limitation the rights 15// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16// copies of the Software, and to permit persons to whom the Software is 17// furnished to do so, subject to the following conditions: 18// 19// The above copyright notice and this permission notice shall be included in 20// all copies or substantial portions of the Software. 21// 22// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 25// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28// THE SOFTWARE. 29 30package ppc64 31 32import ( 33 "cmd/internal/obj" 34 "cmd/internal/objabi" 35 "encoding/binary" 36 "fmt" 37 "log" 38 "sort" 39) 40 41// ctxt9 holds state while assembling a single function. 42// Each function gets a fresh ctxt9. 43// This allows for multiple functions to be safely concurrently assembled. 44type ctxt9 struct { 45 ctxt *obj.Link 46 newprog obj.ProgAlloc 47 cursym *obj.LSym 48 autosize int32 49 instoffset int64 50 pc int64 51} 52 53// Instruction layout. 54 55const ( 56 funcAlign = 16 57) 58 59const ( 60 r0iszero = 1 61) 62 63type Optab struct { 64 as obj.As // Opcode 65 a1 uint8 66 a2 uint8 67 a3 uint8 68 a4 uint8 69 type_ int8 // cases in asmout below. E.g., 44 = st r,(ra+rb); 45 = ld (ra+rb), r 70 size int8 71 param int16 72} 73 74var optab = []Optab{ 75 {obj.ATEXT, C_LEXT, C_NONE, C_NONE, C_TEXTSIZE, 0, 0, 0}, 76 {obj.ATEXT, C_LEXT, C_NONE, C_LCON, C_TEXTSIZE, 0, 0, 0}, 77 {obj.ATEXT, C_ADDR, C_NONE, C_NONE, C_TEXTSIZE, 0, 0, 0}, 78 {obj.ATEXT, C_ADDR, C_NONE, C_LCON, C_TEXTSIZE, 0, 0, 0}, 79 /* move register */ 80 {AMOVD, C_REG, C_NONE, C_NONE, C_REG, 1, 4, 0}, 81 {AMOVB, C_REG, C_NONE, C_NONE, C_REG, 12, 4, 0}, 82 {AMOVBZ, C_REG, C_NONE, C_NONE, C_REG, 13, 4, 0}, 83 {AMOVW, C_REG, C_NONE, C_NONE, C_REG, 12, 4, 0}, 84 {AMOVWZ, C_REG, C_NONE, C_NONE, C_REG, 13, 4, 0}, 85 {AADD, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0}, 86 {AADD, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0}, 87 {AADD, C_ADDCON, C_REG, C_NONE, C_REG, 4, 4, 0}, 88 {AADD, C_ADDCON, C_NONE, C_NONE, C_REG, 4, 4, 0}, 89 {AADD, C_UCON, C_REG, C_NONE, C_REG, 20, 4, 0}, 90 {AADD, C_UCON, C_NONE, C_NONE, C_REG, 20, 4, 0}, 91 {AADD, C_LCON, C_REG, C_NONE, C_REG, 22, 12, 0}, 92 {AADD, C_LCON, C_NONE, C_NONE, C_REG, 22, 12, 0}, 93 {AADDC, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0}, 94 {AADDC, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0}, 95 {AADDC, C_ADDCON, C_REG, C_NONE, C_REG, 4, 4, 0}, 96 {AADDC, C_ADDCON, C_NONE, C_NONE, C_REG, 4, 4, 0}, 97 {AADDC, C_LCON, C_REG, C_NONE, C_REG, 22, 12, 0}, 98 {AADDC, C_LCON, C_NONE, C_NONE, C_REG, 22, 12, 0}, 99 {AAND, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, /* logical, no literal */ 100 {AAND, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 101 {AANDCC, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, 102 {AANDCC, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 103 {AANDCC, C_ANDCON, C_NONE, C_NONE, C_REG, 58, 4, 0}, 104 {AANDCC, C_ANDCON, C_REG, C_NONE, C_REG, 58, 4, 0}, 105 {AANDCC, C_UCON, C_NONE, C_NONE, C_REG, 59, 4, 0}, 106 {AANDCC, C_UCON, C_REG, C_NONE, C_REG, 59, 4, 0}, 107 {AANDCC, C_LCON, C_NONE, C_NONE, C_REG, 23, 12, 0}, 108 {AANDCC, C_LCON, C_REG, C_NONE, C_REG, 23, 12, 0}, 109 {AMULLW, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0}, 110 {AMULLW, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0}, 111 {AMULLW, C_ADDCON, C_REG, C_NONE, C_REG, 4, 4, 0}, 112 {AMULLW, C_ADDCON, C_NONE, C_NONE, C_REG, 4, 4, 0}, 113 {AMULLW, C_ANDCON, C_REG, C_NONE, C_REG, 4, 4, 0}, 114 {AMULLW, C_ANDCON, C_NONE, C_NONE, C_REG, 4, 4, 0}, 115 {AMULLW, C_LCON, C_REG, C_NONE, C_REG, 22, 12, 0}, 116 {AMULLW, C_LCON, C_NONE, C_NONE, C_REG, 22, 12, 0}, 117 {ASUBC, C_REG, C_REG, C_NONE, C_REG, 10, 4, 0}, 118 {ASUBC, C_REG, C_NONE, C_NONE, C_REG, 10, 4, 0}, 119 {ASUBC, C_REG, C_NONE, C_ADDCON, C_REG, 27, 4, 0}, 120 {ASUBC, C_REG, C_NONE, C_LCON, C_REG, 28, 12, 0}, 121 {AOR, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, /* logical, literal not cc (or/xor) */ 122 {AOR, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 123 {AOR, C_ANDCON, C_NONE, C_NONE, C_REG, 58, 4, 0}, 124 {AOR, C_ANDCON, C_REG, C_NONE, C_REG, 58, 4, 0}, 125 {AOR, C_UCON, C_NONE, C_NONE, C_REG, 59, 4, 0}, 126 {AOR, C_UCON, C_REG, C_NONE, C_REG, 59, 4, 0}, 127 {AOR, C_LCON, C_NONE, C_NONE, C_REG, 23, 12, 0}, 128 {AOR, C_LCON, C_REG, C_NONE, C_REG, 23, 12, 0}, 129 {ADIVW, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0}, /* op r1[,r2],r3 */ 130 {ADIVW, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0}, 131 {ASUB, C_REG, C_REG, C_NONE, C_REG, 10, 4, 0}, /* op r2[,r1],r3 */ 132 {ASUB, C_REG, C_NONE, C_NONE, C_REG, 10, 4, 0}, 133 {ASLW, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 134 {ASLW, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, 135 {ASLD, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 136 {ASLD, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, 137 {ASLD, C_SCON, C_REG, C_NONE, C_REG, 25, 4, 0}, 138 {ASLD, C_SCON, C_NONE, C_NONE, C_REG, 25, 4, 0}, 139 {ASLW, C_SCON, C_REG, C_NONE, C_REG, 57, 4, 0}, 140 {ASLW, C_SCON, C_NONE, C_NONE, C_REG, 57, 4, 0}, 141 {ASRAW, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 142 {ASRAW, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, 143 {ASRAW, C_SCON, C_REG, C_NONE, C_REG, 56, 4, 0}, 144 {ASRAW, C_SCON, C_NONE, C_NONE, C_REG, 56, 4, 0}, 145 {ASRAD, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 146 {ASRAD, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, 147 {ASRAD, C_SCON, C_REG, C_NONE, C_REG, 56, 4, 0}, 148 {ASRAD, C_SCON, C_NONE, C_NONE, C_REG, 56, 4, 0}, 149 {ARLWMI, C_SCON, C_REG, C_LCON, C_REG, 62, 4, 0}, 150 {ARLWMI, C_REG, C_REG, C_LCON, C_REG, 63, 4, 0}, 151 {ARLDMI, C_SCON, C_REG, C_LCON, C_REG, 30, 4, 0}, 152 {ARLDC, C_SCON, C_REG, C_LCON, C_REG, 29, 4, 0}, 153 {ARLDCL, C_SCON, C_REG, C_LCON, C_REG, 29, 4, 0}, 154 {ARLDCL, C_REG, C_REG, C_LCON, C_REG, 14, 4, 0}, 155 {ARLDICL, C_REG, C_REG, C_LCON, C_REG, 14, 4, 0}, 156 {ARLDICL, C_SCON, C_REG, C_LCON, C_REG, 14, 4, 0}, 157 {ARLDCL, C_REG, C_NONE, C_LCON, C_REG, 14, 4, 0}, 158 {AFADD, C_FREG, C_NONE, C_NONE, C_FREG, 2, 4, 0}, 159 {AFADD, C_FREG, C_FREG, C_NONE, C_FREG, 2, 4, 0}, 160 {AFABS, C_FREG, C_NONE, C_NONE, C_FREG, 33, 4, 0}, 161 {AFABS, C_NONE, C_NONE, C_NONE, C_FREG, 33, 4, 0}, 162 {AFMOVD, C_FREG, C_NONE, C_NONE, C_FREG, 33, 4, 0}, 163 {AFMADD, C_FREG, C_FREG, C_FREG, C_FREG, 34, 4, 0}, 164 {AFMUL, C_FREG, C_NONE, C_NONE, C_FREG, 32, 4, 0}, 165 {AFMUL, C_FREG, C_FREG, C_NONE, C_FREG, 32, 4, 0}, 166 167 /* store, short offset */ 168 {AMOVD, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 169 {AMOVW, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 170 {AMOVWZ, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 171 {AMOVBZ, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 172 {AMOVBZU, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 173 {AMOVB, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 174 {AMOVBU, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 175 {AMOVD, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 176 {AMOVW, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 177 {AMOVWZ, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 178 {AMOVBZ, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 179 {AMOVB, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 180 {AMOVD, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 181 {AMOVW, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 182 {AMOVWZ, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 183 {AMOVBZ, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 184 {AMOVB, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 185 {AMOVD, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 186 {AMOVW, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 187 {AMOVWZ, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 188 {AMOVBZ, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 189 {AMOVBZU, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 190 {AMOVB, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 191 {AMOVBU, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 192 193 /* load, short offset */ 194 {AMOVD, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO}, 195 {AMOVW, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO}, 196 {AMOVWZ, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO}, 197 {AMOVBZ, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO}, 198 {AMOVBZU, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO}, 199 {AMOVB, C_ZOREG, C_REG, C_NONE, C_REG, 9, 8, REGZERO}, 200 {AMOVBU, C_ZOREG, C_REG, C_NONE, C_REG, 9, 8, REGZERO}, 201 {AMOVD, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB}, 202 {AMOVW, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB}, 203 {AMOVWZ, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB}, 204 {AMOVBZ, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB}, 205 {AMOVB, C_SEXT, C_NONE, C_NONE, C_REG, 9, 8, REGSB}, 206 {AMOVD, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP}, 207 {AMOVW, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP}, 208 {AMOVWZ, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP}, 209 {AMOVBZ, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP}, 210 {AMOVB, C_SAUTO, C_NONE, C_NONE, C_REG, 9, 8, REGSP}, 211 {AMOVD, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO}, 212 {AMOVW, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO}, 213 {AMOVWZ, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO}, 214 {AMOVBZ, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO}, 215 {AMOVBZU, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO}, 216 {AMOVB, C_SOREG, C_NONE, C_NONE, C_REG, 9, 8, REGZERO}, 217 {AMOVBU, C_SOREG, C_NONE, C_NONE, C_REG, 9, 8, REGZERO}, 218 219 /* store, long offset */ 220 {AMOVD, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 221 {AMOVW, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 222 {AMOVWZ, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 223 {AMOVBZ, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 224 {AMOVB, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 225 {AMOVD, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 226 {AMOVW, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 227 {AMOVWZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 228 {AMOVBZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 229 {AMOVB, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 230 {AMOVD, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 231 {AMOVW, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 232 {AMOVWZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 233 {AMOVBZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 234 {AMOVB, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 235 {AMOVD, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 236 {AMOVW, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 237 {AMOVWZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 238 {AMOVBZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 239 {AMOVB, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 240 241 /* load, long offset */ 242 {AMOVD, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB}, 243 {AMOVW, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB}, 244 {AMOVWZ, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB}, 245 {AMOVBZ, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB}, 246 {AMOVB, C_LEXT, C_NONE, C_NONE, C_REG, 37, 12, REGSB}, 247 {AMOVD, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP}, 248 {AMOVW, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP}, 249 {AMOVWZ, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP}, 250 {AMOVBZ, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP}, 251 {AMOVB, C_LAUTO, C_NONE, C_NONE, C_REG, 37, 12, REGSP}, 252 {AMOVD, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO}, 253 {AMOVW, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO}, 254 {AMOVWZ, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO}, 255 {AMOVBZ, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO}, 256 {AMOVB, C_LOREG, C_NONE, C_NONE, C_REG, 37, 12, REGZERO}, 257 {AMOVD, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0}, 258 {AMOVW, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0}, 259 {AMOVWZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0}, 260 {AMOVBZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0}, 261 {AMOVB, C_ADDR, C_NONE, C_NONE, C_REG, 76, 12, 0}, 262 263 {AMOVD, C_TLS_LE, C_NONE, C_NONE, C_REG, 79, 4, 0}, 264 {AMOVD, C_TLS_IE, C_NONE, C_NONE, C_REG, 80, 8, 0}, 265 266 {AMOVD, C_GOTADDR, C_NONE, C_NONE, C_REG, 81, 8, 0}, 267 268 /* load constant */ 269 {AMOVD, C_SECON, C_NONE, C_NONE, C_REG, 3, 4, REGSB}, 270 {AMOVD, C_SACON, C_NONE, C_NONE, C_REG, 3, 4, REGSP}, 271 {AMOVD, C_LECON, C_NONE, C_NONE, C_REG, 26, 8, REGSB}, 272 {AMOVD, C_LACON, C_NONE, C_NONE, C_REG, 26, 8, REGSP}, 273 {AMOVD, C_ADDCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 274 {AMOVW, C_SECON, C_NONE, C_NONE, C_REG, 3, 4, REGSB}, /* TO DO: check */ 275 {AMOVW, C_SACON, C_NONE, C_NONE, C_REG, 3, 4, REGSP}, 276 {AMOVW, C_LECON, C_NONE, C_NONE, C_REG, 26, 8, REGSB}, 277 {AMOVW, C_LACON, C_NONE, C_NONE, C_REG, 26, 8, REGSP}, 278 {AMOVW, C_ADDCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 279 {AMOVWZ, C_SECON, C_NONE, C_NONE, C_REG, 3, 4, REGSB}, /* TO DO: check */ 280 {AMOVWZ, C_SACON, C_NONE, C_NONE, C_REG, 3, 4, REGSP}, 281 {AMOVWZ, C_LECON, C_NONE, C_NONE, C_REG, 26, 8, REGSB}, 282 {AMOVWZ, C_LACON, C_NONE, C_NONE, C_REG, 26, 8, REGSP}, 283 {AMOVWZ, C_ADDCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 284 285 /* load unsigned/long constants (TO DO: check) */ 286 {AMOVD, C_UCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 287 {AMOVD, C_LCON, C_NONE, C_NONE, C_REG, 19, 8, 0}, 288 {AMOVW, C_UCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 289 {AMOVW, C_LCON, C_NONE, C_NONE, C_REG, 19, 8, 0}, 290 {AMOVWZ, C_UCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 291 {AMOVWZ, C_LCON, C_NONE, C_NONE, C_REG, 19, 8, 0}, 292 {AMOVHBR, C_ZOREG, C_REG, C_NONE, C_REG, 45, 4, 0}, 293 {AMOVHBR, C_ZOREG, C_NONE, C_NONE, C_REG, 45, 4, 0}, 294 {AMOVHBR, C_REG, C_REG, C_NONE, C_ZOREG, 44, 4, 0}, 295 {AMOVHBR, C_REG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0}, 296 {ASYSCALL, C_NONE, C_NONE, C_NONE, C_NONE, 5, 4, 0}, 297 {ASYSCALL, C_REG, C_NONE, C_NONE, C_NONE, 77, 12, 0}, 298 {ASYSCALL, C_SCON, C_NONE, C_NONE, C_NONE, 77, 12, 0}, 299 {ABEQ, C_NONE, C_NONE, C_NONE, C_SBRA, 16, 4, 0}, 300 {ABEQ, C_CREG, C_NONE, C_NONE, C_SBRA, 16, 4, 0}, 301 {ABR, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 4, 0}, 302 {ABR, C_NONE, C_NONE, C_NONE, C_LBRAPIC, 11, 8, 0}, 303 {ABC, C_SCON, C_REG, C_NONE, C_SBRA, 16, 4, 0}, 304 {ABC, C_SCON, C_REG, C_NONE, C_LBRA, 17, 4, 0}, 305 {ABR, C_NONE, C_NONE, C_NONE, C_LR, 18, 4, 0}, 306 {ABR, C_NONE, C_NONE, C_NONE, C_CTR, 18, 4, 0}, 307 {ABR, C_REG, C_NONE, C_NONE, C_CTR, 18, 4, 0}, 308 {ABR, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 8, 0}, 309 {ABC, C_NONE, C_REG, C_NONE, C_LR, 18, 4, 0}, 310 {ABC, C_NONE, C_REG, C_NONE, C_CTR, 18, 4, 0}, 311 {ABC, C_SCON, C_REG, C_NONE, C_LR, 18, 4, 0}, 312 {ABC, C_SCON, C_REG, C_NONE, C_CTR, 18, 4, 0}, 313 {ABC, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 8, 0}, 314 {AFMOVD, C_SEXT, C_NONE, C_NONE, C_FREG, 8, 4, REGSB}, 315 {AFMOVD, C_SAUTO, C_NONE, C_NONE, C_FREG, 8, 4, REGSP}, 316 {AFMOVD, C_SOREG, C_NONE, C_NONE, C_FREG, 8, 4, REGZERO}, 317 {AFMOVD, C_LEXT, C_NONE, C_NONE, C_FREG, 36, 8, REGSB}, 318 {AFMOVD, C_LAUTO, C_NONE, C_NONE, C_FREG, 36, 8, REGSP}, 319 {AFMOVD, C_LOREG, C_NONE, C_NONE, C_FREG, 36, 8, REGZERO}, 320 {AFMOVD, C_ADDR, C_NONE, C_NONE, C_FREG, 75, 8, 0}, 321 {AFMOVD, C_FREG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 322 {AFMOVD, C_FREG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 323 {AFMOVD, C_FREG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 324 {AFMOVD, C_FREG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 325 {AFMOVD, C_FREG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 326 {AFMOVD, C_FREG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 327 {AFMOVD, C_FREG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 328 {AFMOVSX, C_ZOREG, C_REG, C_NONE, C_FREG, 45, 4, 0}, 329 {AFMOVSX, C_ZOREG, C_NONE, C_NONE, C_FREG, 45, 4, 0}, 330 {AFMOVSX, C_FREG, C_REG, C_NONE, C_ZOREG, 44, 4, 0}, 331 {AFMOVSX, C_FREG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0}, 332 {AFMOVSZ, C_ZOREG, C_REG, C_NONE, C_FREG, 45, 4, 0}, 333 {AFMOVSZ, C_ZOREG, C_NONE, C_NONE, C_FREG, 45, 4, 0}, 334 {ASYNC, C_NONE, C_NONE, C_NONE, C_NONE, 46, 4, 0}, 335 {AWORD, C_LCON, C_NONE, C_NONE, C_NONE, 40, 4, 0}, 336 {ADWORD, C_LCON, C_NONE, C_NONE, C_NONE, 31, 8, 0}, 337 {ADWORD, C_DCON, C_NONE, C_NONE, C_NONE, 31, 8, 0}, 338 {AADDME, C_REG, C_NONE, C_NONE, C_REG, 47, 4, 0}, 339 {AEXTSB, C_REG, C_NONE, C_NONE, C_REG, 48, 4, 0}, 340 {AEXTSB, C_NONE, C_NONE, C_NONE, C_REG, 48, 4, 0}, 341 {AISEL, C_LCON, C_REG, C_REG, C_REG, 84, 4, 0}, 342 {AISEL, C_ZCON, C_REG, C_REG, C_REG, 84, 4, 0}, 343 {ANEG, C_REG, C_NONE, C_NONE, C_REG, 47, 4, 0}, 344 {ANEG, C_NONE, C_NONE, C_NONE, C_REG, 47, 4, 0}, 345 {AREM, C_REG, C_NONE, C_NONE, C_REG, 50, 12, 0}, 346 {AREM, C_REG, C_REG, C_NONE, C_REG, 50, 12, 0}, 347 {AREMU, C_REG, C_NONE, C_NONE, C_REG, 50, 16, 0}, 348 {AREMU, C_REG, C_REG, C_NONE, C_REG, 50, 16, 0}, 349 {AREMD, C_REG, C_NONE, C_NONE, C_REG, 51, 12, 0}, 350 {AREMD, C_REG, C_REG, C_NONE, C_REG, 51, 12, 0}, 351 {AREMDU, C_REG, C_NONE, C_NONE, C_REG, 51, 12, 0}, 352 {AREMDU, C_REG, C_REG, C_NONE, C_REG, 51, 12, 0}, 353 {AMTFSB0, C_SCON, C_NONE, C_NONE, C_NONE, 52, 4, 0}, 354 {AMOVFL, C_FPSCR, C_NONE, C_NONE, C_FREG, 53, 4, 0}, 355 {AMOVFL, C_FREG, C_NONE, C_NONE, C_FPSCR, 64, 4, 0}, 356 {AMOVFL, C_FREG, C_NONE, C_LCON, C_FPSCR, 64, 4, 0}, 357 {AMOVFL, C_LCON, C_NONE, C_NONE, C_FPSCR, 65, 4, 0}, 358 {AMOVD, C_MSR, C_NONE, C_NONE, C_REG, 54, 4, 0}, /* mfmsr */ 359 {AMOVD, C_REG, C_NONE, C_NONE, C_MSR, 54, 4, 0}, /* mtmsrd */ 360 {AMOVWZ, C_REG, C_NONE, C_NONE, C_MSR, 54, 4, 0}, /* mtmsr */ 361 362 /* Other ISA 2.05+ instructions */ 363 {APOPCNTD, C_REG, C_NONE, C_NONE, C_REG, 93, 4, 0}, /* population count, x-form */ 364 {ACMPB, C_REG, C_REG, C_NONE, C_REG, 92, 4, 0}, /* compare byte, x-form */ 365 {AFTDIV, C_FREG, C_FREG, C_NONE, C_SCON, 92, 4, 0}, /* floating test for sw divide, x-form */ 366 {AFTSQRT, C_FREG, C_NONE, C_NONE, C_SCON, 93, 4, 0}, /* floating test for sw square root, x-form */ 367 368 /* Vector instructions */ 369 370 /* Vector load */ 371 {ALV, C_SOREG, C_NONE, C_NONE, C_VREG, 45, 4, 0}, /* vector load, x-form */ 372 373 /* Vector store */ 374 {ASTV, C_VREG, C_NONE, C_NONE, C_SOREG, 44, 4, 0}, /* vector store, x-form */ 375 376 /* Vector logical */ 377 {AVAND, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector and, vx-form */ 378 {AVOR, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector or, vx-form */ 379 380 /* Vector add */ 381 {AVADDUM, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add unsigned modulo, vx-form */ 382 {AVADDCU, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add & write carry unsigned, vx-form */ 383 {AVADDUS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add unsigned saturate, vx-form */ 384 {AVADDSS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add signed saturate, vx-form */ 385 {AVADDE, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector add extended, va-form */ 386 387 /* Vector subtract */ 388 {AVSUBUM, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract unsigned modulo, vx-form */ 389 {AVSUBCU, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract & write carry unsigned, vx-form */ 390 {AVSUBUS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract unsigned saturate, vx-form */ 391 {AVSUBSS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract signed saturate, vx-form */ 392 {AVSUBE, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector subtract extended, va-form */ 393 394 /* Vector multiply */ 395 {AVPMSUM, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector polynomial multiply & sum, vx-form */ 396 397 /* Vector rotate */ 398 {AVR, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector rotate, vx-form */ 399 400 /* Vector shift */ 401 {AVS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector shift, vx-form */ 402 {AVSA, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector shift algebraic, vx-form */ 403 {AVSOI, C_ANDCON, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector shift by octet immediate, va-form */ 404 405 /* Vector count */ 406 {AVCLZ, C_VREG, C_NONE, C_NONE, C_VREG, 85, 4, 0}, /* vector count leading zeros, vx-form */ 407 {AVPOPCNT, C_VREG, C_NONE, C_NONE, C_VREG, 85, 4, 0}, /* vector population count, vx-form */ 408 409 /* Vector compare */ 410 {AVCMPEQ, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector compare equal, vc-form */ 411 {AVCMPGT, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector compare greater than, vc-form */ 412 413 /* Vector permute */ 414 {AVPERM, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector permute, va-form */ 415 416 /* Vector select */ 417 {AVSEL, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector select, va-form */ 418 419 /* Vector splat */ 420 {AVSPLT, C_SCON, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector splat, vx-form */ 421 {AVSPLT, C_ADDCON, C_VREG, C_NONE, C_VREG, 82, 4, 0}, 422 {AVSPLTI, C_SCON, C_NONE, C_NONE, C_VREG, 82, 4, 0}, /* vector splat immediate, vx-form */ 423 {AVSPLTI, C_ADDCON, C_NONE, C_NONE, C_VREG, 82, 4, 0}, 424 425 /* Vector AES */ 426 {AVCIPH, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector AES cipher, vx-form */ 427 {AVNCIPH, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector AES inverse cipher, vx-form */ 428 {AVSBOX, C_VREG, C_NONE, C_NONE, C_VREG, 82, 4, 0}, /* vector AES subbytes, vx-form */ 429 430 /* Vector SHA */ 431 {AVSHASIGMA, C_ANDCON, C_VREG, C_ANDCON, C_VREG, 82, 4, 0}, /* vector SHA sigma, vx-form */ 432 433 /* VSX vector load */ 434 {ALXV, C_SOREG, C_NONE, C_NONE, C_VSREG, 87, 4, 0}, /* vsx vector load, xx1-form */ 435 436 /* VSX vector store */ 437 {ASTXV, C_VSREG, C_NONE, C_NONE, C_SOREG, 86, 4, 0}, /* vsx vector store, xx1-form */ 438 439 /* VSX scalar load */ 440 {ALXS, C_SOREG, C_NONE, C_NONE, C_VSREG, 87, 4, 0}, /* vsx scalar load, xx1-form */ 441 442 /* VSX scalar store */ 443 {ASTXS, C_VSREG, C_NONE, C_NONE, C_SOREG, 86, 4, 0}, /* vsx scalar store, xx1-form */ 444 445 /* VSX scalar as integer load */ 446 {ALXSI, C_SOREG, C_NONE, C_NONE, C_VSREG, 87, 4, 0}, /* vsx scalar as integer load, xx1-form */ 447 448 /* VSX scalar store as integer */ 449 {ASTXSI, C_VSREG, C_NONE, C_NONE, C_SOREG, 86, 4, 0}, /* vsx scalar as integer store, xx1-form */ 450 451 /* VSX move from VSR */ 452 {AMFVSR, C_VSREG, C_NONE, C_NONE, C_REG, 88, 4, 0}, /* vsx move from vsr, xx1-form */ 453 {AMFVSR, C_FREG, C_NONE, C_NONE, C_REG, 88, 4, 0}, 454 {AMFVSR, C_VREG, C_NONE, C_NONE, C_REG, 88, 4, 0}, 455 456 /* VSX move to VSR */ 457 {AMTVSR, C_REG, C_NONE, C_NONE, C_VSREG, 88, 4, 0}, /* vsx move to vsr, xx1-form */ 458 {AMTVSR, C_REG, C_NONE, C_NONE, C_FREG, 88, 4, 0}, 459 {AMTVSR, C_REG, C_NONE, C_NONE, C_VREG, 88, 4, 0}, 460 461 /* VSX logical */ 462 {AXXLAND, C_VSREG, C_VSREG, C_NONE, C_VSREG, 90, 4, 0}, /* vsx and, xx3-form */ 463 {AXXLOR, C_VSREG, C_VSREG, C_NONE, C_VSREG, 90, 4, 0}, /* vsx or, xx3-form */ 464 465 /* VSX select */ 466 {AXXSEL, C_VSREG, C_VSREG, C_VSREG, C_VSREG, 91, 4, 0}, /* vsx select, xx4-form */ 467 468 /* VSX merge */ 469 {AXXMRG, C_VSREG, C_VSREG, C_NONE, C_VSREG, 90, 4, 0}, /* vsx merge, xx3-form */ 470 471 /* VSX splat */ 472 {AXXSPLT, C_VSREG, C_NONE, C_SCON, C_VSREG, 89, 4, 0}, /* vsx splat, xx2-form */ 473 474 /* VSX permute */ 475 {AXXPERM, C_VSREG, C_VSREG, C_SCON, C_VSREG, 90, 4, 0}, /* vsx permute, xx3-form */ 476 477 /* VSX shift */ 478 {AXXSI, C_VSREG, C_VSREG, C_SCON, C_VSREG, 90, 4, 0}, /* vsx shift immediate, xx3-form */ 479 480 /* VSX scalar FP-FP conversion */ 481 {AXSCV, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx scalar fp-fp conversion, xx2-form */ 482 483 /* VSX vector FP-FP conversion */ 484 {AXVCV, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx vector fp-fp conversion, xx2-form */ 485 486 /* VSX scalar FP-integer conversion */ 487 {AXSCVX, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx scalar fp-integer conversion, xx2-form */ 488 489 /* VSX scalar integer-FP conversion */ 490 {AXSCVXP, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx scalar integer-fp conversion, xx2-form */ 491 492 /* VSX vector FP-integer conversion */ 493 {AXVCVX, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx vector fp-integer conversion, xx2-form */ 494 495 /* VSX vector integer-FP conversion */ 496 {AXVCVXP, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx vector integer-fp conversion, xx2-form */ 497 498 /* 64-bit special registers */ 499 {AMOVD, C_REG, C_NONE, C_NONE, C_SPR, 66, 4, 0}, 500 {AMOVD, C_REG, C_NONE, C_NONE, C_LR, 66, 4, 0}, 501 {AMOVD, C_REG, C_NONE, C_NONE, C_CTR, 66, 4, 0}, 502 {AMOVD, C_REG, C_NONE, C_NONE, C_XER, 66, 4, 0}, 503 {AMOVD, C_SPR, C_NONE, C_NONE, C_REG, 66, 4, 0}, 504 {AMOVD, C_LR, C_NONE, C_NONE, C_REG, 66, 4, 0}, 505 {AMOVD, C_CTR, C_NONE, C_NONE, C_REG, 66, 4, 0}, 506 {AMOVD, C_XER, C_NONE, C_NONE, C_REG, 66, 4, 0}, 507 508 /* 32-bit special registers (gloss over sign-extension or not?) */ 509 {AMOVW, C_REG, C_NONE, C_NONE, C_SPR, 66, 4, 0}, 510 {AMOVW, C_REG, C_NONE, C_NONE, C_CTR, 66, 4, 0}, 511 {AMOVW, C_REG, C_NONE, C_NONE, C_XER, 66, 4, 0}, 512 {AMOVW, C_SPR, C_NONE, C_NONE, C_REG, 66, 4, 0}, 513 {AMOVW, C_XER, C_NONE, C_NONE, C_REG, 66, 4, 0}, 514 {AMOVWZ, C_REG, C_NONE, C_NONE, C_SPR, 66, 4, 0}, 515 {AMOVWZ, C_REG, C_NONE, C_NONE, C_CTR, 66, 4, 0}, 516 {AMOVWZ, C_REG, C_NONE, C_NONE, C_XER, 66, 4, 0}, 517 {AMOVWZ, C_SPR, C_NONE, C_NONE, C_REG, 66, 4, 0}, 518 {AMOVWZ, C_XER, C_NONE, C_NONE, C_REG, 66, 4, 0}, 519 {AMOVFL, C_FPSCR, C_NONE, C_NONE, C_CREG, 73, 4, 0}, 520 {AMOVFL, C_CREG, C_NONE, C_NONE, C_CREG, 67, 4, 0}, 521 {AMOVW, C_CREG, C_NONE, C_NONE, C_REG, 68, 4, 0}, 522 {AMOVWZ, C_CREG, C_NONE, C_NONE, C_REG, 68, 4, 0}, 523 {AMOVFL, C_REG, C_NONE, C_NONE, C_LCON, 69, 4, 0}, 524 {AMOVFL, C_REG, C_NONE, C_NONE, C_CREG, 69, 4, 0}, 525 {AMOVW, C_REG, C_NONE, C_NONE, C_CREG, 69, 4, 0}, 526 {AMOVWZ, C_REG, C_NONE, C_NONE, C_CREG, 69, 4, 0}, 527 {ACMP, C_REG, C_NONE, C_NONE, C_REG, 70, 4, 0}, 528 {ACMP, C_REG, C_REG, C_NONE, C_REG, 70, 4, 0}, 529 {ACMP, C_REG, C_NONE, C_NONE, C_ADDCON, 71, 4, 0}, 530 {ACMP, C_REG, C_REG, C_NONE, C_ADDCON, 71, 4, 0}, 531 {ACMPU, C_REG, C_NONE, C_NONE, C_REG, 70, 4, 0}, 532 {ACMPU, C_REG, C_REG, C_NONE, C_REG, 70, 4, 0}, 533 {ACMPU, C_REG, C_NONE, C_NONE, C_ANDCON, 71, 4, 0}, 534 {ACMPU, C_REG, C_REG, C_NONE, C_ANDCON, 71, 4, 0}, 535 {AFCMPO, C_FREG, C_NONE, C_NONE, C_FREG, 70, 4, 0}, 536 {AFCMPO, C_FREG, C_REG, C_NONE, C_FREG, 70, 4, 0}, 537 {ATW, C_LCON, C_REG, C_NONE, C_REG, 60, 4, 0}, 538 {ATW, C_LCON, C_REG, C_NONE, C_ADDCON, 61, 4, 0}, 539 {ADCBF, C_ZOREG, C_NONE, C_NONE, C_NONE, 43, 4, 0}, 540 {ADCBF, C_ZOREG, C_REG, C_NONE, C_NONE, 43, 4, 0}, 541 {AECOWX, C_REG, C_REG, C_NONE, C_ZOREG, 44, 4, 0}, 542 {AECIWX, C_ZOREG, C_REG, C_NONE, C_REG, 45, 4, 0}, 543 {AECOWX, C_REG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0}, 544 {AECIWX, C_ZOREG, C_NONE, C_NONE, C_REG, 45, 4, 0}, 545 {AEIEIO, C_NONE, C_NONE, C_NONE, C_NONE, 46, 4, 0}, 546 {ATLBIE, C_REG, C_NONE, C_NONE, C_NONE, 49, 4, 0}, 547 {ATLBIE, C_SCON, C_NONE, C_NONE, C_REG, 49, 4, 0}, 548 {ASLBMFEE, C_REG, C_NONE, C_NONE, C_REG, 55, 4, 0}, 549 {ASLBMTE, C_REG, C_NONE, C_NONE, C_REG, 55, 4, 0}, 550 {ASTSW, C_REG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0}, 551 {ASTSW, C_REG, C_NONE, C_LCON, C_ZOREG, 41, 4, 0}, 552 {ALSW, C_ZOREG, C_NONE, C_NONE, C_REG, 45, 4, 0}, 553 {ALSW, C_ZOREG, C_NONE, C_LCON, C_REG, 42, 4, 0}, 554 {obj.AUNDEF, C_NONE, C_NONE, C_NONE, C_NONE, 78, 4, 0}, 555 {obj.APCDATA, C_LCON, C_NONE, C_NONE, C_LCON, 0, 0, 0}, 556 {obj.AFUNCDATA, C_SCON, C_NONE, C_NONE, C_ADDR, 0, 0, 0}, 557 {obj.ANOP, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0}, 558 {obj.ADUFFZERO, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 4, 0}, // same as ABR/ABL 559 {obj.ADUFFCOPY, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 4, 0}, // same as ABR/ABL 560 561 {obj.AXXX, C_NONE, C_NONE, C_NONE, C_NONE, 0, 4, 0}, 562} 563 564var oprange [ALAST & obj.AMask][]Optab 565 566var xcmp [C_NCLASS][C_NCLASS]bool 567 568func span9(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { 569 p := cursym.Func.Text 570 if p == nil || p.Link == nil { // handle external functions and ELF section symbols 571 return 572 } 573 574 if oprange[AANDN&obj.AMask] == nil { 575 ctxt.Diag("ppc64 ops not initialized, call ppc64.buildop first") 576 } 577 578 c := ctxt9{ctxt: ctxt, newprog: newprog, cursym: cursym, autosize: int32(p.To.Offset)} 579 580 pc := int64(0) 581 p.Pc = pc 582 583 var m int 584 var o *Optab 585 for p = p.Link; p != nil; p = p.Link { 586 p.Pc = pc 587 o = c.oplook(p) 588 m = int(o.size) 589 if m == 0 { 590 if p.As != obj.ANOP && p.As != obj.AFUNCDATA && p.As != obj.APCDATA { 591 c.ctxt.Diag("zero-width instruction\n%v", p) 592 } 593 continue 594 } 595 596 pc += int64(m) 597 } 598 599 c.cursym.Size = pc 600 601 /* 602 * if any procedure is large enough to 603 * generate a large SBRA branch, then 604 * generate extra passes putting branches 605 * around jmps to fix. this is rare. 606 */ 607 bflag := 1 608 609 var otxt int64 610 var q *obj.Prog 611 for bflag != 0 { 612 bflag = 0 613 pc = 0 614 for p = c.cursym.Func.Text.Link; p != nil; p = p.Link { 615 p.Pc = pc 616 o = c.oplook(p) 617 618 // very large conditional branches 619 if (o.type_ == 16 || o.type_ == 17) && p.Pcond != nil { 620 otxt = p.Pcond.Pc - pc 621 if otxt < -(1<<15)+10 || otxt >= (1<<15)-10 { 622 q = c.newprog() 623 q.Link = p.Link 624 p.Link = q 625 q.As = ABR 626 q.To.Type = obj.TYPE_BRANCH 627 q.Pcond = p.Pcond 628 p.Pcond = q 629 q = c.newprog() 630 q.Link = p.Link 631 p.Link = q 632 q.As = ABR 633 q.To.Type = obj.TYPE_BRANCH 634 q.Pcond = q.Link.Link 635 636 //addnop(p->link); 637 //addnop(p); 638 bflag = 1 639 } 640 } 641 642 m = int(o.size) 643 if m == 0 { 644 if p.As != obj.ANOP && p.As != obj.AFUNCDATA && p.As != obj.APCDATA { 645 c.ctxt.Diag("zero-width instruction\n%v", p) 646 } 647 continue 648 } 649 650 pc += int64(m) 651 } 652 653 c.cursym.Size = pc 654 } 655 656 pc += -pc & (funcAlign - 1) 657 c.cursym.Size = pc 658 659 /* 660 * lay out the code, emitting code and data relocations. 661 */ 662 663 c.cursym.Grow(c.cursym.Size) 664 665 bp := c.cursym.P 666 var i int32 667 var out [6]uint32 668 for p := c.cursym.Func.Text.Link; p != nil; p = p.Link { 669 c.pc = p.Pc 670 o = c.oplook(p) 671 if int(o.size) > 4*len(out) { 672 log.Fatalf("out array in span9 is too small, need at least %d for %v", o.size/4, p) 673 } 674 c.asmout(p, o, out[:]) 675 for i = 0; i < int32(o.size/4); i++ { 676 c.ctxt.Arch.ByteOrder.PutUint32(bp, out[i]) 677 bp = bp[4:] 678 } 679 } 680} 681 682func isint32(v int64) bool { 683 return int64(int32(v)) == v 684} 685 686func isuint32(v uint64) bool { 687 return uint64(uint32(v)) == v 688} 689 690func (c *ctxt9) aclass(a *obj.Addr) int { 691 switch a.Type { 692 case obj.TYPE_NONE: 693 return C_NONE 694 695 case obj.TYPE_REG: 696 if REG_R0 <= a.Reg && a.Reg <= REG_R31 { 697 return C_REG 698 } 699 if REG_F0 <= a.Reg && a.Reg <= REG_F31 { 700 return C_FREG 701 } 702 if REG_V0 <= a.Reg && a.Reg <= REG_V31 { 703 return C_VREG 704 } 705 if REG_VS0 <= a.Reg && a.Reg <= REG_VS63 { 706 return C_VSREG 707 } 708 if REG_CR0 <= a.Reg && a.Reg <= REG_CR7 || a.Reg == REG_CR { 709 return C_CREG 710 } 711 if REG_SPR0 <= a.Reg && a.Reg <= REG_SPR0+1023 { 712 switch a.Reg { 713 case REG_LR: 714 return C_LR 715 716 case REG_XER: 717 return C_XER 718 719 case REG_CTR: 720 return C_CTR 721 } 722 723 return C_SPR 724 } 725 726 if REG_DCR0 <= a.Reg && a.Reg <= REG_DCR0+1023 { 727 return C_SPR 728 } 729 if a.Reg == REG_FPSCR { 730 return C_FPSCR 731 } 732 if a.Reg == REG_MSR { 733 return C_MSR 734 } 735 return C_GOK 736 737 case obj.TYPE_MEM: 738 switch a.Name { 739 case obj.NAME_EXTERN, 740 obj.NAME_STATIC: 741 if a.Sym == nil { 742 break 743 } 744 c.instoffset = a.Offset 745 if a.Sym != nil { // use relocation 746 if a.Sym.Type == objabi.STLSBSS { 747 if c.ctxt.Flag_shared { 748 return C_TLS_IE 749 } else { 750 return C_TLS_LE 751 } 752 } 753 return C_ADDR 754 } 755 return C_LEXT 756 757 case obj.NAME_GOTREF: 758 return C_GOTADDR 759 760 case obj.NAME_AUTO: 761 if a.Reg == REGSP { 762 // unset base register for better printing, since 763 // a.Offset is still relative to pseudo-SP. 764 a.Reg = obj.REG_NONE 765 } 766 c.instoffset = int64(c.autosize) + a.Offset 767 if c.instoffset >= -BIG && c.instoffset < BIG { 768 return C_SAUTO 769 } 770 return C_LAUTO 771 772 case obj.NAME_PARAM: 773 if a.Reg == REGSP { 774 // unset base register for better printing, since 775 // a.Offset is still relative to pseudo-FP. 776 a.Reg = obj.REG_NONE 777 } 778 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.FixedFrameSize() 779 if c.instoffset >= -BIG && c.instoffset < BIG { 780 return C_SAUTO 781 } 782 return C_LAUTO 783 784 case obj.NAME_NONE: 785 c.instoffset = a.Offset 786 if c.instoffset == 0 { 787 return C_ZOREG 788 } 789 if c.instoffset >= -BIG && c.instoffset < BIG { 790 return C_SOREG 791 } 792 return C_LOREG 793 } 794 795 return C_GOK 796 797 case obj.TYPE_TEXTSIZE: 798 return C_TEXTSIZE 799 800 case obj.TYPE_CONST, 801 obj.TYPE_ADDR: 802 switch a.Name { 803 case obj.NAME_NONE: 804 c.instoffset = a.Offset 805 if a.Reg != 0 { 806 if -BIG <= c.instoffset && c.instoffset <= BIG { 807 return C_SACON 808 } 809 if isint32(c.instoffset) { 810 return C_LACON 811 } 812 return C_DACON 813 } 814 815 goto consize 816 817 case obj.NAME_EXTERN, 818 obj.NAME_STATIC: 819 s := a.Sym 820 if s == nil { 821 break 822 } 823 824 c.instoffset = a.Offset 825 826 /* not sure why this barfs */ 827 return C_LCON 828 829 case obj.NAME_AUTO: 830 if a.Reg == REGSP { 831 // unset base register for better printing, since 832 // a.Offset is still relative to pseudo-SP. 833 a.Reg = obj.REG_NONE 834 } 835 c.instoffset = int64(c.autosize) + a.Offset 836 if c.instoffset >= -BIG && c.instoffset < BIG { 837 return C_SACON 838 } 839 return C_LACON 840 841 case obj.NAME_PARAM: 842 if a.Reg == REGSP { 843 // unset base register for better printing, since 844 // a.Offset is still relative to pseudo-FP. 845 a.Reg = obj.REG_NONE 846 } 847 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.FixedFrameSize() 848 if c.instoffset >= -BIG && c.instoffset < BIG { 849 return C_SACON 850 } 851 return C_LACON 852 } 853 854 return C_GOK 855 856 consize: 857 if c.instoffset >= 0 { 858 if c.instoffset == 0 { 859 return C_ZCON 860 } 861 if c.instoffset <= 0x7fff { 862 return C_SCON 863 } 864 if c.instoffset <= 0xffff { 865 return C_ANDCON 866 } 867 if c.instoffset&0xffff == 0 && isuint32(uint64(c.instoffset)) { /* && (instoffset & (1<<31)) == 0) */ 868 return C_UCON 869 } 870 if isint32(c.instoffset) || isuint32(uint64(c.instoffset)) { 871 return C_LCON 872 } 873 return C_DCON 874 } 875 876 if c.instoffset >= -0x8000 { 877 return C_ADDCON 878 } 879 if c.instoffset&0xffff == 0 && isint32(c.instoffset) { 880 return C_UCON 881 } 882 if isint32(c.instoffset) { 883 return C_LCON 884 } 885 return C_DCON 886 887 case obj.TYPE_BRANCH: 888 if a.Sym != nil && c.ctxt.Flag_dynlink { 889 return C_LBRAPIC 890 } 891 return C_SBRA 892 } 893 894 return C_GOK 895} 896 897func prasm(p *obj.Prog) { 898 fmt.Printf("%v\n", p) 899} 900 901func (c *ctxt9) oplook(p *obj.Prog) *Optab { 902 a1 := int(p.Optab) 903 if a1 != 0 { 904 return &optab[a1-1] 905 } 906 a1 = int(p.From.Class) 907 if a1 == 0 { 908 a1 = c.aclass(&p.From) + 1 909 p.From.Class = int8(a1) 910 } 911 912 a1-- 913 a3 := C_NONE + 1 914 if p.From3 != nil { 915 a3 = int(p.From3.Class) 916 if a3 == 0 { 917 a3 = c.aclass(p.From3) + 1 918 p.From3.Class = int8(a3) 919 } 920 } 921 922 a3-- 923 a4 := int(p.To.Class) 924 if a4 == 0 { 925 a4 = c.aclass(&p.To) + 1 926 p.To.Class = int8(a4) 927 } 928 929 a4-- 930 a2 := C_NONE 931 if p.Reg != 0 { 932 if REG_R0 <= p.Reg && p.Reg <= REG_R31 { 933 a2 = C_REG 934 } else if REG_V0 <= p.Reg && p.Reg <= REG_V31 { 935 a2 = C_VREG 936 } else if REG_VS0 <= p.Reg && p.Reg <= REG_VS63 { 937 a2 = C_VSREG 938 } else if REG_F0 <= p.Reg && p.Reg <= REG_F31 { 939 a2 = C_FREG 940 } 941 } 942 943 //print("oplook %v %d %d %d %d\n", p, a1, a2, a3, a4); 944 ops := oprange[p.As&obj.AMask] 945 c1 := &xcmp[a1] 946 c3 := &xcmp[a3] 947 c4 := &xcmp[a4] 948 for i := range ops { 949 op := &ops[i] 950 if int(op.a2) == a2 && c1[op.a1] && c3[op.a3] && c4[op.a4] { 951 p.Optab = uint16(cap(optab) - cap(ops) + i + 1) 952 return op 953 } 954 } 955 956 c.ctxt.Diag("illegal combination %v %v %v %v %v", p.As, DRconv(a1), DRconv(a2), DRconv(a3), DRconv(a4)) 957 prasm(p) 958 if ops == nil { 959 ops = optab 960 } 961 return &ops[0] 962} 963 964func cmp(a int, b int) bool { 965 if a == b { 966 return true 967 } 968 switch a { 969 case C_LCON: 970 if b == C_ZCON || b == C_SCON || b == C_UCON || b == C_ADDCON || b == C_ANDCON { 971 return true 972 } 973 974 case C_ADDCON: 975 if b == C_ZCON || b == C_SCON { 976 return true 977 } 978 979 case C_ANDCON: 980 if b == C_ZCON || b == C_SCON { 981 return true 982 } 983 984 case C_SPR: 985 if b == C_LR || b == C_XER || b == C_CTR { 986 return true 987 } 988 989 case C_UCON: 990 if b == C_ZCON { 991 return true 992 } 993 994 case C_SCON: 995 if b == C_ZCON { 996 return true 997 } 998 999 case C_LACON: 1000 if b == C_SACON { 1001 return true 1002 } 1003 1004 case C_LBRA: 1005 if b == C_SBRA { 1006 return true 1007 } 1008 1009 case C_LEXT: 1010 if b == C_SEXT { 1011 return true 1012 } 1013 1014 case C_LAUTO: 1015 if b == C_SAUTO { 1016 return true 1017 } 1018 1019 case C_REG: 1020 if b == C_ZCON { 1021 return r0iszero != 0 /*TypeKind(100016)*/ 1022 } 1023 1024 case C_LOREG: 1025 if b == C_ZOREG || b == C_SOREG { 1026 return true 1027 } 1028 1029 case C_SOREG: 1030 if b == C_ZOREG { 1031 return true 1032 } 1033 1034 case C_ANY: 1035 return true 1036 } 1037 1038 return false 1039} 1040 1041type ocmp []Optab 1042 1043func (x ocmp) Len() int { 1044 return len(x) 1045} 1046 1047func (x ocmp) Swap(i, j int) { 1048 x[i], x[j] = x[j], x[i] 1049} 1050 1051func (x ocmp) Less(i, j int) bool { 1052 p1 := &x[i] 1053 p2 := &x[j] 1054 n := int(p1.as) - int(p2.as) 1055 if n != 0 { 1056 return n < 0 1057 } 1058 n = int(p1.a1) - int(p2.a1) 1059 if n != 0 { 1060 return n < 0 1061 } 1062 n = int(p1.a2) - int(p2.a2) 1063 if n != 0 { 1064 return n < 0 1065 } 1066 n = int(p1.a3) - int(p2.a3) 1067 if n != 0 { 1068 return n < 0 1069 } 1070 n = int(p1.a4) - int(p2.a4) 1071 if n != 0 { 1072 return n < 0 1073 } 1074 return false 1075} 1076func opset(a, b0 obj.As) { 1077 oprange[a&obj.AMask] = oprange[b0] 1078} 1079 1080func buildop(ctxt *obj.Link) { 1081 if oprange[AANDN&obj.AMask] != nil { 1082 // Already initialized; stop now. 1083 // This happens in the cmd/asm tests, 1084 // each of which re-initializes the arch. 1085 return 1086 } 1087 1088 var n int 1089 1090 for i := 0; i < C_NCLASS; i++ { 1091 for n = 0; n < C_NCLASS; n++ { 1092 if cmp(n, i) { 1093 xcmp[i][n] = true 1094 } 1095 } 1096 } 1097 for n = 0; optab[n].as != obj.AXXX; n++ { 1098 } 1099 sort.Sort(ocmp(optab[:n])) 1100 for i := 0; i < n; i++ { 1101 r := optab[i].as 1102 r0 := r & obj.AMask 1103 start := i 1104 for optab[i].as == r { 1105 i++ 1106 } 1107 oprange[r0] = optab[start:i] 1108 i-- 1109 1110 switch r { 1111 default: 1112 ctxt.Diag("unknown op in build: %v", r) 1113 log.Fatalf("instruction missing from switch in asm9.go:buildop: %v", r) 1114 1115 case ADCBF: /* unary indexed: op (b+a); op (b) */ 1116 opset(ADCBI, r0) 1117 1118 opset(ADCBST, r0) 1119 opset(ADCBT, r0) 1120 opset(ADCBTST, r0) 1121 opset(ADCBZ, r0) 1122 opset(AICBI, r0) 1123 1124 case AECOWX: /* indexed store: op s,(b+a); op s,(b) */ 1125 opset(ASTWCCC, r0) 1126 opset(ASTBCCC, r0) 1127 1128 opset(ASTDCCC, r0) 1129 1130 case AREM: /* macro */ 1131 opset(AREMCC, r0) 1132 1133 opset(AREMV, r0) 1134 opset(AREMVCC, r0) 1135 1136 case AREMU: 1137 opset(AREMU, r0) 1138 opset(AREMUCC, r0) 1139 opset(AREMUV, r0) 1140 opset(AREMUVCC, r0) 1141 1142 case AREMD: 1143 opset(AREMDCC, r0) 1144 opset(AREMDV, r0) 1145 opset(AREMDVCC, r0) 1146 1147 case AREMDU: 1148 opset(AREMDU, r0) 1149 opset(AREMDUCC, r0) 1150 opset(AREMDUV, r0) 1151 opset(AREMDUVCC, r0) 1152 1153 case ADIVW: /* op Rb[,Ra],Rd */ 1154 opset(AMULHW, r0) 1155 1156 opset(AMULHWCC, r0) 1157 opset(AMULHWU, r0) 1158 opset(AMULHWUCC, r0) 1159 opset(AMULLWCC, r0) 1160 opset(AMULLWVCC, r0) 1161 opset(AMULLWV, r0) 1162 opset(ADIVWCC, r0) 1163 opset(ADIVWV, r0) 1164 opset(ADIVWVCC, r0) 1165 opset(ADIVWU, r0) 1166 opset(ADIVWUCC, r0) 1167 opset(ADIVWUV, r0) 1168 opset(ADIVWUVCC, r0) 1169 opset(AADDCC, r0) 1170 opset(AADDCV, r0) 1171 opset(AADDCVCC, r0) 1172 opset(AADDV, r0) 1173 opset(AADDVCC, r0) 1174 opset(AADDE, r0) 1175 opset(AADDECC, r0) 1176 opset(AADDEV, r0) 1177 opset(AADDEVCC, r0) 1178 opset(ACRAND, r0) 1179 opset(ACRANDN, r0) 1180 opset(ACREQV, r0) 1181 opset(ACRNAND, r0) 1182 opset(ACRNOR, r0) 1183 opset(ACROR, r0) 1184 opset(ACRORN, r0) 1185 opset(ACRXOR, r0) 1186 opset(AMULHD, r0) 1187 opset(AMULHDCC, r0) 1188 opset(AMULHDU, r0) 1189 opset(AMULHDUCC, r0) 1190 opset(AMULLD, r0) 1191 opset(AMULLDCC, r0) 1192 opset(AMULLDVCC, r0) 1193 opset(AMULLDV, r0) 1194 opset(ADIVD, r0) 1195 opset(ADIVDCC, r0) 1196 opset(ADIVDE, r0) 1197 opset(ADIVDEU, r0) 1198 opset(ADIVDECC, r0) 1199 opset(ADIVDEUCC, r0) 1200 opset(ADIVDVCC, r0) 1201 opset(ADIVDV, r0) 1202 opset(ADIVDU, r0) 1203 opset(ADIVDUCC, r0) 1204 opset(ADIVDUVCC, r0) 1205 opset(ADIVDUCC, r0) 1206 1207 case APOPCNTD: 1208 opset(APOPCNTW, r0) 1209 opset(APOPCNTB, r0) 1210 1211 case AMOVBZ: /* lbz, stz, rlwm(r/r), lhz, lha, stz, and x variants */ 1212 opset(AMOVH, r0) 1213 1214 opset(AMOVHZ, r0) 1215 1216 case AMOVBZU: /* lbz[x]u, stb[x]u, lhz[x]u, lha[x]u, sth[u]x, ld[x]u, std[u]x */ 1217 opset(AMOVHU, r0) 1218 1219 opset(AMOVHZU, r0) 1220 opset(AMOVWU, r0) 1221 opset(AMOVWZU, r0) 1222 opset(AMOVDU, r0) 1223 opset(AMOVMW, r0) 1224 1225 case ALV: /* lvebx, lvehx, lvewx, lvx, lvxl, lvsl, lvsr */ 1226 opset(ALVEBX, r0) 1227 opset(ALVEHX, r0) 1228 opset(ALVEWX, r0) 1229 opset(ALVX, r0) 1230 opset(ALVXL, r0) 1231 opset(ALVSL, r0) 1232 opset(ALVSR, r0) 1233 1234 case ASTV: /* stvebx, stvehx, stvewx, stvx, stvxl */ 1235 opset(ASTVEBX, r0) 1236 opset(ASTVEHX, r0) 1237 opset(ASTVEWX, r0) 1238 opset(ASTVX, r0) 1239 opset(ASTVXL, r0) 1240 1241 case AVAND: /* vand, vandc, vnand */ 1242 opset(AVAND, r0) 1243 opset(AVANDC, r0) 1244 opset(AVNAND, r0) 1245 1246 case AVOR: /* vor, vorc, vxor, vnor, veqv */ 1247 opset(AVOR, r0) 1248 opset(AVORC, r0) 1249 opset(AVXOR, r0) 1250 opset(AVNOR, r0) 1251 opset(AVEQV, r0) 1252 1253 case AVADDUM: /* vaddubm, vadduhm, vadduwm, vaddudm, vadduqm */ 1254 opset(AVADDUBM, r0) 1255 opset(AVADDUHM, r0) 1256 opset(AVADDUWM, r0) 1257 opset(AVADDUDM, r0) 1258 opset(AVADDUQM, r0) 1259 1260 case AVADDCU: /* vaddcuq, vaddcuw */ 1261 opset(AVADDCUQ, r0) 1262 opset(AVADDCUW, r0) 1263 1264 case AVADDUS: /* vaddubs, vadduhs, vadduws */ 1265 opset(AVADDUBS, r0) 1266 opset(AVADDUHS, r0) 1267 opset(AVADDUWS, r0) 1268 1269 case AVADDSS: /* vaddsbs, vaddshs, vaddsws */ 1270 opset(AVADDSBS, r0) 1271 opset(AVADDSHS, r0) 1272 opset(AVADDSWS, r0) 1273 1274 case AVADDE: /* vaddeuqm, vaddecuq */ 1275 opset(AVADDEUQM, r0) 1276 opset(AVADDECUQ, r0) 1277 1278 case AVSUBUM: /* vsububm, vsubuhm, vsubuwm, vsubudm, vsubuqm */ 1279 opset(AVSUBUBM, r0) 1280 opset(AVSUBUHM, r0) 1281 opset(AVSUBUWM, r0) 1282 opset(AVSUBUDM, r0) 1283 opset(AVSUBUQM, r0) 1284 1285 case AVSUBCU: /* vsubcuq, vsubcuw */ 1286 opset(AVSUBCUQ, r0) 1287 opset(AVSUBCUW, r0) 1288 1289 case AVSUBUS: /* vsububs, vsubuhs, vsubuws */ 1290 opset(AVSUBUBS, r0) 1291 opset(AVSUBUHS, r0) 1292 opset(AVSUBUWS, r0) 1293 1294 case AVSUBSS: /* vsubsbs, vsubshs, vsubsws */ 1295 opset(AVSUBSBS, r0) 1296 opset(AVSUBSHS, r0) 1297 opset(AVSUBSWS, r0) 1298 1299 case AVSUBE: /* vsubeuqm, vsubecuq */ 1300 opset(AVSUBEUQM, r0) 1301 opset(AVSUBECUQ, r0) 1302 1303 case AVPMSUM: /* vpmsumb, vpmsumh, vpmsumw, vpmsumd */ 1304 opset(AVPMSUMB, r0) 1305 opset(AVPMSUMH, r0) 1306 opset(AVPMSUMW, r0) 1307 opset(AVPMSUMD, r0) 1308 1309 case AVR: /* vrlb, vrlh, vrlw, vrld */ 1310 opset(AVRLB, r0) 1311 opset(AVRLH, r0) 1312 opset(AVRLW, r0) 1313 opset(AVRLD, r0) 1314 1315 case AVS: /* vs[l,r], vs[l,r]o, vs[l,r]b, vs[l,r]h, vs[l,r]w, vs[l,r]d */ 1316 opset(AVSLB, r0) 1317 opset(AVSLH, r0) 1318 opset(AVSLW, r0) 1319 opset(AVSL, r0) 1320 opset(AVSLO, r0) 1321 opset(AVSRB, r0) 1322 opset(AVSRH, r0) 1323 opset(AVSRW, r0) 1324 opset(AVSR, r0) 1325 opset(AVSRO, r0) 1326 opset(AVSLD, r0) 1327 opset(AVSRD, r0) 1328 1329 case AVSA: /* vsrab, vsrah, vsraw, vsrad */ 1330 opset(AVSRAB, r0) 1331 opset(AVSRAH, r0) 1332 opset(AVSRAW, r0) 1333 opset(AVSRAD, r0) 1334 1335 case AVSOI: /* vsldoi */ 1336 opset(AVSLDOI, r0) 1337 1338 case AVCLZ: /* vclzb, vclzh, vclzw, vclzd */ 1339 opset(AVCLZB, r0) 1340 opset(AVCLZH, r0) 1341 opset(AVCLZW, r0) 1342 opset(AVCLZD, r0) 1343 1344 case AVPOPCNT: /* vpopcntb, vpopcnth, vpopcntw, vpopcntd */ 1345 opset(AVPOPCNTB, r0) 1346 opset(AVPOPCNTH, r0) 1347 opset(AVPOPCNTW, r0) 1348 opset(AVPOPCNTD, r0) 1349 1350 case AVCMPEQ: /* vcmpequb[.], vcmpequh[.], vcmpequw[.], vcmpequd[.] */ 1351 opset(AVCMPEQUB, r0) 1352 opset(AVCMPEQUBCC, r0) 1353 opset(AVCMPEQUH, r0) 1354 opset(AVCMPEQUHCC, r0) 1355 opset(AVCMPEQUW, r0) 1356 opset(AVCMPEQUWCC, r0) 1357 opset(AVCMPEQUD, r0) 1358 opset(AVCMPEQUDCC, r0) 1359 1360 case AVCMPGT: /* vcmpgt[u,s]b[.], vcmpgt[u,s]h[.], vcmpgt[u,s]w[.], vcmpgt[u,s]d[.] */ 1361 opset(AVCMPGTUB, r0) 1362 opset(AVCMPGTUBCC, r0) 1363 opset(AVCMPGTUH, r0) 1364 opset(AVCMPGTUHCC, r0) 1365 opset(AVCMPGTUW, r0) 1366 opset(AVCMPGTUWCC, r0) 1367 opset(AVCMPGTUD, r0) 1368 opset(AVCMPGTUDCC, r0) 1369 opset(AVCMPGTSB, r0) 1370 opset(AVCMPGTSBCC, r0) 1371 opset(AVCMPGTSH, r0) 1372 opset(AVCMPGTSHCC, r0) 1373 opset(AVCMPGTSW, r0) 1374 opset(AVCMPGTSWCC, r0) 1375 opset(AVCMPGTSD, r0) 1376 opset(AVCMPGTSDCC, r0) 1377 1378 case AVPERM: /* vperm */ 1379 opset(AVPERM, r0) 1380 1381 case AVSEL: /* vsel */ 1382 opset(AVSEL, r0) 1383 1384 case AVSPLT: /* vspltb, vsplth, vspltw */ 1385 opset(AVSPLTB, r0) 1386 opset(AVSPLTH, r0) 1387 opset(AVSPLTW, r0) 1388 1389 case AVSPLTI: /* vspltisb, vspltish, vspltisw */ 1390 opset(AVSPLTISB, r0) 1391 opset(AVSPLTISH, r0) 1392 opset(AVSPLTISW, r0) 1393 1394 case AVCIPH: /* vcipher, vcipherlast */ 1395 opset(AVCIPHER, r0) 1396 opset(AVCIPHERLAST, r0) 1397 1398 case AVNCIPH: /* vncipher, vncipherlast */ 1399 opset(AVNCIPHER, r0) 1400 opset(AVNCIPHERLAST, r0) 1401 1402 case AVSBOX: /* vsbox */ 1403 opset(AVSBOX, r0) 1404 1405 case AVSHASIGMA: /* vshasigmaw, vshasigmad */ 1406 opset(AVSHASIGMAW, r0) 1407 opset(AVSHASIGMAD, r0) 1408 1409 case ALXV: /* lxvd2x, lxvdsx, lxvw4x */ 1410 opset(ALXVD2X, r0) 1411 opset(ALXVDSX, r0) 1412 opset(ALXVW4X, r0) 1413 1414 case ASTXV: /* stxvd2x, stxvdsx, stxvw4x */ 1415 opset(ASTXVD2X, r0) 1416 opset(ASTXVW4X, r0) 1417 1418 case ALXS: /* lxsdx */ 1419 opset(ALXSDX, r0) 1420 1421 case ASTXS: /* stxsdx */ 1422 opset(ASTXSDX, r0) 1423 1424 case ALXSI: /* lxsiwax, lxsiwzx */ 1425 opset(ALXSIWAX, r0) 1426 opset(ALXSIWZX, r0) 1427 1428 case ASTXSI: /* stxsiwx */ 1429 opset(ASTXSIWX, r0) 1430 1431 case AMFVSR: /* mfvsrd, mfvsrwz (and extended mnemonics) */ 1432 opset(AMFVSRD, r0) 1433 opset(AMFFPRD, r0) 1434 opset(AMFVRD, r0) 1435 opset(AMFVSRWZ, r0) 1436 1437 case AMTVSR: /* mtvsrd, mtvsrwa, mtvsrwz (and extended mnemonics) */ 1438 opset(AMTVSRD, r0) 1439 opset(AMTFPRD, r0) 1440 opset(AMTVRD, r0) 1441 opset(AMTVSRWA, r0) 1442 opset(AMTVSRWZ, r0) 1443 1444 case AXXLAND: /* xxland, xxlandc, xxleqv, xxlnand */ 1445 opset(AXXLANDQ, r0) 1446 opset(AXXLANDC, r0) 1447 opset(AXXLEQV, r0) 1448 opset(AXXLNAND, r0) 1449 1450 case AXXLOR: /* xxlorc, xxlnor, xxlor, xxlxor */ 1451 opset(AXXLORC, r0) 1452 opset(AXXLNOR, r0) 1453 opset(AXXLORQ, r0) 1454 opset(AXXLXOR, r0) 1455 1456 case AXXSEL: /* xxsel */ 1457 opset(AXXSEL, r0) 1458 1459 case AXXMRG: /* xxmrghw, xxmrglw */ 1460 opset(AXXMRGHW, r0) 1461 opset(AXXMRGLW, r0) 1462 1463 case AXXSPLT: /* xxspltw */ 1464 opset(AXXSPLTW, r0) 1465 1466 case AXXPERM: /* xxpermdi */ 1467 opset(AXXPERMDI, r0) 1468 1469 case AXXSI: /* xxsldwi */ 1470 opset(AXXSLDWI, r0) 1471 1472 case AXSCV: /* xscvdpsp, xscvspdp, xscvdpspn, xscvspdpn */ 1473 opset(AXSCVDPSP, r0) 1474 opset(AXSCVSPDP, r0) 1475 opset(AXSCVDPSPN, r0) 1476 opset(AXSCVSPDPN, r0) 1477 1478 case AXVCV: /* xvcvdpsp, xvcvspdp */ 1479 opset(AXVCVDPSP, r0) 1480 opset(AXVCVSPDP, r0) 1481 1482 case AXSCVX: /* xscvdpsxds, xscvdpsxws, xscvdpuxds, xscvdpuxws */ 1483 opset(AXSCVDPSXDS, r0) 1484 opset(AXSCVDPSXWS, r0) 1485 opset(AXSCVDPUXDS, r0) 1486 opset(AXSCVDPUXWS, r0) 1487 1488 case AXSCVXP: /* xscvsxddp, xscvuxddp, xscvsxdsp, xscvuxdsp */ 1489 opset(AXSCVSXDDP, r0) 1490 opset(AXSCVUXDDP, r0) 1491 opset(AXSCVSXDSP, r0) 1492 opset(AXSCVUXDSP, r0) 1493 1494 case AXVCVX: /* xvcvdpsxds, xvcvdpsxws, xvcvdpuxds, xvcvdpuxws, xvcvspsxds, xvcvspsxws, xvcvspuxds, xvcvspuxws */ 1495 opset(AXVCVDPSXDS, r0) 1496 opset(AXVCVDPSXWS, r0) 1497 opset(AXVCVDPUXDS, r0) 1498 opset(AXVCVDPUXWS, r0) 1499 opset(AXVCVSPSXDS, r0) 1500 opset(AXVCVSPSXWS, r0) 1501 opset(AXVCVSPUXDS, r0) 1502 opset(AXVCVSPUXWS, r0) 1503 1504 case AXVCVXP: /* xvcvsxddp, xvcvsxwdp, xvcvuxddp, xvcvuxwdp, xvcvsxdsp, xvcvsxwsp, xvcvuxdsp, xvcvuxwsp */ 1505 opset(AXVCVSXDDP, r0) 1506 opset(AXVCVSXWDP, r0) 1507 opset(AXVCVUXDDP, r0) 1508 opset(AXVCVUXWDP, r0) 1509 opset(AXVCVSXDSP, r0) 1510 opset(AXVCVSXWSP, r0) 1511 opset(AXVCVUXDSP, r0) 1512 opset(AXVCVUXWSP, r0) 1513 1514 case AAND: /* logical op Rb,Rs,Ra; no literal */ 1515 opset(AANDN, r0) 1516 1517 opset(AANDNCC, r0) 1518 opset(AEQV, r0) 1519 opset(AEQVCC, r0) 1520 opset(ANAND, r0) 1521 opset(ANANDCC, r0) 1522 opset(ANOR, r0) 1523 opset(ANORCC, r0) 1524 opset(AORCC, r0) 1525 opset(AORN, r0) 1526 opset(AORNCC, r0) 1527 opset(AXORCC, r0) 1528 1529 case AADDME: /* op Ra, Rd */ 1530 opset(AADDMECC, r0) 1531 1532 opset(AADDMEV, r0) 1533 opset(AADDMEVCC, r0) 1534 opset(AADDZE, r0) 1535 opset(AADDZECC, r0) 1536 opset(AADDZEV, r0) 1537 opset(AADDZEVCC, r0) 1538 opset(ASUBME, r0) 1539 opset(ASUBMECC, r0) 1540 opset(ASUBMEV, r0) 1541 opset(ASUBMEVCC, r0) 1542 opset(ASUBZE, r0) 1543 opset(ASUBZECC, r0) 1544 opset(ASUBZEV, r0) 1545 opset(ASUBZEVCC, r0) 1546 1547 case AADDC: 1548 opset(AADDCCC, r0) 1549 1550 case ABEQ: 1551 opset(ABGE, r0) 1552 opset(ABGT, r0) 1553 opset(ABLE, r0) 1554 opset(ABLT, r0) 1555 opset(ABNE, r0) 1556 opset(ABVC, r0) 1557 opset(ABVS, r0) 1558 1559 case ABR: 1560 opset(ABL, r0) 1561 1562 case ABC: 1563 opset(ABCL, r0) 1564 1565 case AEXTSB: /* op Rs, Ra */ 1566 opset(AEXTSBCC, r0) 1567 1568 opset(AEXTSH, r0) 1569 opset(AEXTSHCC, r0) 1570 opset(ACNTLZW, r0) 1571 opset(ACNTLZWCC, r0) 1572 opset(ACNTLZD, r0) 1573 opset(AEXTSW, r0) 1574 opset(AEXTSWCC, r0) 1575 opset(ACNTLZDCC, r0) 1576 1577 case AFABS: /* fop [s,]d */ 1578 opset(AFABSCC, r0) 1579 1580 opset(AFNABS, r0) 1581 opset(AFNABSCC, r0) 1582 opset(AFNEG, r0) 1583 opset(AFNEGCC, r0) 1584 opset(AFRSP, r0) 1585 opset(AFRSPCC, r0) 1586 opset(AFCTIW, r0) 1587 opset(AFCTIWCC, r0) 1588 opset(AFCTIWZ, r0) 1589 opset(AFCTIWZCC, r0) 1590 opset(AFCTID, r0) 1591 opset(AFCTIDCC, r0) 1592 opset(AFCTIDZ, r0) 1593 opset(AFCTIDZCC, r0) 1594 opset(AFCFID, r0) 1595 opset(AFCFIDCC, r0) 1596 opset(AFCFIDU, r0) 1597 opset(AFCFIDUCC, r0) 1598 opset(AFRES, r0) 1599 opset(AFRESCC, r0) 1600 opset(AFRIM, r0) 1601 opset(AFRIMCC, r0) 1602 opset(AFRIP, r0) 1603 opset(AFRIPCC, r0) 1604 opset(AFRIZ, r0) 1605 opset(AFRIZCC, r0) 1606 opset(AFRSQRTE, r0) 1607 opset(AFRSQRTECC, r0) 1608 opset(AFSQRT, r0) 1609 opset(AFSQRTCC, r0) 1610 opset(AFSQRTS, r0) 1611 opset(AFSQRTSCC, r0) 1612 1613 case AFADD: 1614 opset(AFADDS, r0) 1615 opset(AFADDCC, r0) 1616 opset(AFADDSCC, r0) 1617 opset(AFDIV, r0) 1618 opset(AFDIVS, r0) 1619 opset(AFDIVCC, r0) 1620 opset(AFDIVSCC, r0) 1621 opset(AFSUB, r0) 1622 opset(AFSUBS, r0) 1623 opset(AFSUBCC, r0) 1624 opset(AFSUBSCC, r0) 1625 1626 case AFMADD: 1627 opset(AFMADDCC, r0) 1628 opset(AFMADDS, r0) 1629 opset(AFMADDSCC, r0) 1630 opset(AFMSUB, r0) 1631 opset(AFMSUBCC, r0) 1632 opset(AFMSUBS, r0) 1633 opset(AFMSUBSCC, r0) 1634 opset(AFNMADD, r0) 1635 opset(AFNMADDCC, r0) 1636 opset(AFNMADDS, r0) 1637 opset(AFNMADDSCC, r0) 1638 opset(AFNMSUB, r0) 1639 opset(AFNMSUBCC, r0) 1640 opset(AFNMSUBS, r0) 1641 opset(AFNMSUBSCC, r0) 1642 opset(AFSEL, r0) 1643 opset(AFSELCC, r0) 1644 1645 case AFMUL: 1646 opset(AFMULS, r0) 1647 opset(AFMULCC, r0) 1648 opset(AFMULSCC, r0) 1649 1650 case AFCMPO: 1651 opset(AFCMPU, r0) 1652 1653 case AISEL: 1654 opset(AISEL, r0) 1655 1656 case AMTFSB0: 1657 opset(AMTFSB0CC, r0) 1658 opset(AMTFSB1, r0) 1659 opset(AMTFSB1CC, r0) 1660 1661 case ANEG: /* op [Ra,] Rd */ 1662 opset(ANEGCC, r0) 1663 1664 opset(ANEGV, r0) 1665 opset(ANEGVCC, r0) 1666 1667 case AOR: /* or/xor Rb,Rs,Ra; ori/xori $uimm,Rs,Ra; oris/xoris $uimm,Rs,Ra */ 1668 opset(AXOR, r0) 1669 1670 case ASLW: 1671 opset(ASLWCC, r0) 1672 opset(ASRW, r0) 1673 opset(ASRWCC, r0) 1674 opset(AROTLW, r0) 1675 1676 case ASLD: 1677 opset(ASLDCC, r0) 1678 opset(ASRD, r0) 1679 opset(ASRDCC, r0) 1680 opset(AROTL, r0) 1681 1682 case ASRAW: /* sraw Rb,Rs,Ra; srawi sh,Rs,Ra */ 1683 opset(ASRAWCC, r0) 1684 1685 case ASRAD: /* sraw Rb,Rs,Ra; srawi sh,Rs,Ra */ 1686 opset(ASRADCC, r0) 1687 1688 case ASUB: /* SUB Ra,Rb,Rd => subf Rd,ra,rb */ 1689 opset(ASUB, r0) 1690 1691 opset(ASUBCC, r0) 1692 opset(ASUBV, r0) 1693 opset(ASUBVCC, r0) 1694 opset(ASUBCCC, r0) 1695 opset(ASUBCV, r0) 1696 opset(ASUBCVCC, r0) 1697 opset(ASUBE, r0) 1698 opset(ASUBECC, r0) 1699 opset(ASUBEV, r0) 1700 opset(ASUBEVCC, r0) 1701 1702 case ASYNC: 1703 opset(AISYNC, r0) 1704 opset(ALWSYNC, r0) 1705 opset(APTESYNC, r0) 1706 opset(ATLBSYNC, r0) 1707 1708 case ARLWMI: 1709 opset(ARLWMICC, r0) 1710 opset(ARLWNM, r0) 1711 opset(ARLWNMCC, r0) 1712 1713 case ARLDMI: 1714 opset(ARLDMICC, r0) 1715 opset(ARLDIMI, r0) 1716 opset(ARLDIMICC, r0) 1717 1718 case ARLDC: 1719 opset(ARLDCCC, r0) 1720 1721 case ARLDCL: 1722 opset(ARLDCR, r0) 1723 opset(ARLDCLCC, r0) 1724 opset(ARLDCRCC, r0) 1725 1726 case ARLDICL: 1727 opset(ARLDICLCC, r0) 1728 opset(ARLDICR, r0) 1729 opset(ARLDICRCC, r0) 1730 1731 case AFMOVD: 1732 opset(AFMOVDCC, r0) 1733 opset(AFMOVDU, r0) 1734 opset(AFMOVS, r0) 1735 opset(AFMOVSU, r0) 1736 1737 case AECIWX: 1738 opset(ALBAR, r0) 1739 opset(ALWAR, r0) 1740 opset(ALDAR, r0) 1741 1742 case ASYSCALL: /* just the op; flow of control */ 1743 opset(ARFI, r0) 1744 1745 opset(ARFCI, r0) 1746 opset(ARFID, r0) 1747 opset(AHRFID, r0) 1748 1749 case AMOVHBR: 1750 opset(AMOVWBR, r0) 1751 opset(AMOVDBR, r0) 1752 1753 case ASLBMFEE: 1754 opset(ASLBMFEV, r0) 1755 1756 case ATW: 1757 opset(ATD, r0) 1758 1759 case ATLBIE: 1760 opset(ASLBIE, r0) 1761 opset(ATLBIEL, r0) 1762 1763 case AEIEIO: 1764 opset(ASLBIA, r0) 1765 1766 case ACMP: 1767 opset(ACMPW, r0) 1768 1769 case ACMPU: 1770 opset(ACMPWU, r0) 1771 1772 case ACMPB: 1773 opset(ACMPB, r0) 1774 1775 case AFTDIV: 1776 opset(AFTDIV, r0) 1777 1778 case AFTSQRT: 1779 opset(AFTSQRT, r0) 1780 1781 case AADD, 1782 AANDCC, /* and. Rb,Rs,Ra; andi. $uimm,Rs,Ra; andis. $uimm,Rs,Ra */ 1783 AFMOVSX, 1784 AFMOVSZ, 1785 ALSW, 1786 AMOVW, 1787 /* load/store/move word with sign extension; special 32-bit move; move 32-bit literals */ 1788 AMOVWZ, /* load/store/move word with zero extension; move 32-bit literals */ 1789 AMOVD, /* load/store/move 64-bit values, including 32-bit literals with/without sign-extension */ 1790 AMOVB, /* macro: move byte with sign extension */ 1791 AMOVBU, /* macro: move byte with sign extension & update */ 1792 AMOVFL, 1793 AMULLW, 1794 /* op $s[,r2],r3; op r1[,r2],r3; no cc/v */ 1795 ASUBC, /* op r1,$s,r3; op r1[,r2],r3 */ 1796 ASTSW, 1797 ASLBMTE, 1798 AWORD, 1799 ADWORD, 1800 obj.ANOP, 1801 obj.ATEXT, 1802 obj.AUNDEF, 1803 obj.AFUNCDATA, 1804 obj.APCDATA, 1805 obj.ADUFFZERO, 1806 obj.ADUFFCOPY: 1807 break 1808 } 1809 } 1810} 1811 1812func OPVXX1(o uint32, xo uint32, oe uint32) uint32 { 1813 return o<<26 | xo<<1 | oe<<11 1814} 1815 1816func OPVXX2(o uint32, xo uint32, oe uint32) uint32 { 1817 return o<<26 | xo<<2 | oe<<11 1818} 1819 1820func OPVXX3(o uint32, xo uint32, oe uint32) uint32 { 1821 return o<<26 | xo<<3 | oe<<11 1822} 1823 1824func OPVXX4(o uint32, xo uint32, oe uint32) uint32 { 1825 return o<<26 | xo<<4 | oe<<11 1826} 1827 1828func OPVX(o uint32, xo uint32, oe uint32, rc uint32) uint32 { 1829 return o<<26 | xo | oe<<11 | rc&1 1830} 1831 1832func OPVC(o uint32, xo uint32, oe uint32, rc uint32) uint32 { 1833 return o<<26 | xo | oe<<11 | (rc&1)<<10 1834} 1835 1836func OPVCC(o uint32, xo uint32, oe uint32, rc uint32) uint32 { 1837 return o<<26 | xo<<1 | oe<<10 | rc&1 1838} 1839 1840func OPCC(o uint32, xo uint32, rc uint32) uint32 { 1841 return OPVCC(o, xo, 0, rc) 1842} 1843 1844func OP(o uint32, xo uint32) uint32 { 1845 return OPVCC(o, xo, 0, 0) 1846} 1847 1848/* the order is dest, a/s, b/imm for both arithmetic and logical operations */ 1849func AOP_RRR(op uint32, d uint32, a uint32, b uint32) uint32 { 1850 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 1851} 1852 1853/* VX-form 2-register operands, r/none/r */ 1854func AOP_RR(op uint32, d uint32, a uint32) uint32 { 1855 return op | (d&31)<<21 | (a&31)<<11 1856} 1857 1858/* VA-form 4-register operands */ 1859func AOP_RRRR(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 { 1860 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (c&31)<<6 1861} 1862 1863func AOP_IRR(op uint32, d uint32, a uint32, simm uint32) uint32 { 1864 return op | (d&31)<<21 | (a&31)<<16 | simm&0xFFFF 1865} 1866 1867/* VX-form 2-register + UIM operands */ 1868func AOP_VIRR(op uint32, d uint32, a uint32, simm uint32) uint32 { 1869 return op | (d&31)<<21 | (simm&0xFFFF)<<16 | (a&31)<<11 1870} 1871 1872/* VX-form 2-register + ST + SIX operands */ 1873func AOP_IIRR(op uint32, d uint32, a uint32, sbit uint32, simm uint32) uint32 { 1874 return op | (d&31)<<21 | (a&31)<<16 | (sbit&1)<<15 | (simm&0xF)<<11 1875} 1876 1877/* VA-form 3-register + SHB operands */ 1878func AOP_IRRR(op uint32, d uint32, a uint32, b uint32, simm uint32) uint32 { 1879 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (simm&0xF)<<6 1880} 1881 1882/* VX-form 1-register + SIM operands */ 1883func AOP_IR(op uint32, d uint32, simm uint32) uint32 { 1884 return op | (d&31)<<21 | (simm&31)<<16 1885} 1886 1887/* XX1-form 3-register operands, 1 VSR operand */ 1888func AOP_XX1(op uint32, d uint32, a uint32, b uint32) uint32 { 1889 /* For the XX-form encodings, we need the VSX register number to be exactly */ 1890 /* between 0-63, so we can properly set the rightmost bits. */ 1891 r := d - REG_VS0 1892 return op | (r&31)<<21 | (a&31)<<16 | (b&31)<<11 | (r&32)>>5 1893} 1894 1895/* XX2-form 3-register operands, 2 VSR operands */ 1896func AOP_XX2(op uint32, d uint32, a uint32, b uint32) uint32 { 1897 xt := d - REG_VS0 1898 xb := b - REG_VS0 1899 return op | (xt&31)<<21 | (a&3)<<16 | (xb&31)<<11 | (xb&32)>>4 | (xt&32)>>5 1900} 1901 1902/* XX3-form 3 VSR operands */ 1903func AOP_XX3(op uint32, d uint32, a uint32, b uint32) uint32 { 1904 xt := d - REG_VS0 1905 xa := a - REG_VS0 1906 xb := b - REG_VS0 1907 return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5 1908} 1909 1910/* XX3-form 3 VSR operands + immediate */ 1911func AOP_XX3I(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 { 1912 xt := d - REG_VS0 1913 xa := a - REG_VS0 1914 xb := b - REG_VS0 1915 return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (c&3)<<8 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5 1916} 1917 1918/* XX4-form, 4 VSR operands */ 1919func AOP_XX4(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 { 1920 xt := d - REG_VS0 1921 xa := a - REG_VS0 1922 xb := b - REG_VS0 1923 xc := c - REG_VS0 1924 return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (xc&31)<<6 | (xc&32)>>2 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5 1925} 1926 1927func LOP_RRR(op uint32, a uint32, s uint32, b uint32) uint32 { 1928 return op | (s&31)<<21 | (a&31)<<16 | (b&31)<<11 1929} 1930 1931func LOP_IRR(op uint32, a uint32, s uint32, uimm uint32) uint32 { 1932 return op | (s&31)<<21 | (a&31)<<16 | uimm&0xFFFF 1933} 1934 1935func OP_BR(op uint32, li uint32, aa uint32) uint32 { 1936 return op | li&0x03FFFFFC | aa<<1 1937} 1938 1939func OP_BC(op uint32, bo uint32, bi uint32, bd uint32, aa uint32) uint32 { 1940 return op | (bo&0x1F)<<21 | (bi&0x1F)<<16 | bd&0xFFFC | aa<<1 1941} 1942 1943func OP_BCR(op uint32, bo uint32, bi uint32) uint32 { 1944 return op | (bo&0x1F)<<21 | (bi&0x1F)<<16 1945} 1946 1947func OP_RLW(op uint32, a uint32, s uint32, sh uint32, mb uint32, me uint32) uint32 { 1948 return op | (s&31)<<21 | (a&31)<<16 | (sh&31)<<11 | (mb&31)<<6 | (me&31)<<1 1949} 1950 1951func AOP_RLDIC(op uint32, a uint32, s uint32, sh uint32, m uint32) uint32 { 1952 return op | (s&31)<<21 | (a&31)<<16 | (sh&31)<<11 | ((sh&32)>>5)<<1 | (m&31)<<6 | ((m&32)>>5)<<5 1953} 1954 1955func AOP_ISEL(op uint32, t uint32, a uint32, b uint32, bc uint32) uint32 { 1956 return op | (t&31)<<21 | (a&31)<<16 | (b&31)<<11 | (bc&0x1F)<<6 1957} 1958 1959const ( 1960 /* each rhs is OPVCC(_, _, _, _) */ 1961 OP_ADD = 31<<26 | 266<<1 | 0<<10 | 0 1962 OP_ADDI = 14<<26 | 0<<1 | 0<<10 | 0 1963 OP_ADDIS = 15<<26 | 0<<1 | 0<<10 | 0 1964 OP_ANDI = 28<<26 | 0<<1 | 0<<10 | 0 1965 OP_EXTSB = 31<<26 | 954<<1 | 0<<10 | 0 1966 OP_EXTSH = 31<<26 | 922<<1 | 0<<10 | 0 1967 OP_EXTSW = 31<<26 | 986<<1 | 0<<10 | 0 1968 OP_ISEL = 31<<26 | 15<<1 | 0<<10 | 0 1969 OP_MCRF = 19<<26 | 0<<1 | 0<<10 | 0 1970 OP_MCRFS = 63<<26 | 64<<1 | 0<<10 | 0 1971 OP_MCRXR = 31<<26 | 512<<1 | 0<<10 | 0 1972 OP_MFCR = 31<<26 | 19<<1 | 0<<10 | 0 1973 OP_MFFS = 63<<26 | 583<<1 | 0<<10 | 0 1974 OP_MFMSR = 31<<26 | 83<<1 | 0<<10 | 0 1975 OP_MFSPR = 31<<26 | 339<<1 | 0<<10 | 0 1976 OP_MFSR = 31<<26 | 595<<1 | 0<<10 | 0 1977 OP_MFSRIN = 31<<26 | 659<<1 | 0<<10 | 0 1978 OP_MTCRF = 31<<26 | 144<<1 | 0<<10 | 0 1979 OP_MTFSF = 63<<26 | 711<<1 | 0<<10 | 0 1980 OP_MTFSFI = 63<<26 | 134<<1 | 0<<10 | 0 1981 OP_MTMSR = 31<<26 | 146<<1 | 0<<10 | 0 1982 OP_MTMSRD = 31<<26 | 178<<1 | 0<<10 | 0 1983 OP_MTSPR = 31<<26 | 467<<1 | 0<<10 | 0 1984 OP_MTSR = 31<<26 | 210<<1 | 0<<10 | 0 1985 OP_MTSRIN = 31<<26 | 242<<1 | 0<<10 | 0 1986 OP_MULLW = 31<<26 | 235<<1 | 0<<10 | 0 1987 OP_MULLD = 31<<26 | 233<<1 | 0<<10 | 0 1988 OP_OR = 31<<26 | 444<<1 | 0<<10 | 0 1989 OP_ORI = 24<<26 | 0<<1 | 0<<10 | 0 1990 OP_ORIS = 25<<26 | 0<<1 | 0<<10 | 0 1991 OP_RLWINM = 21<<26 | 0<<1 | 0<<10 | 0 1992 OP_RLWNM = 23<<26 | 0<<1 | 0<<10 | 0 1993 OP_SUBF = 31<<26 | 40<<1 | 0<<10 | 0 1994 OP_RLDIC = 30<<26 | 4<<1 | 0<<10 | 0 1995 OP_RLDICR = 30<<26 | 2<<1 | 0<<10 | 0 1996 OP_RLDICL = 30<<26 | 0<<1 | 0<<10 | 0 1997 OP_RLDCL = 30<<26 | 8<<1 | 0<<10 | 0 1998) 1999 2000func oclass(a *obj.Addr) int { 2001 return int(a.Class) - 1 2002} 2003 2004const ( 2005 D_FORM = iota 2006 DS_FORM 2007) 2008 2009// This function determines when a non-indexed load or store is D or 2010// DS form for use in finding the size of the offset field in the instruction. 2011// The size is needed when setting the offset value in the instruction 2012// and when generating relocation for that field. 2013// DS form instructions include: ld, ldu, lwa, std, stdu. All other 2014// loads and stores with an offset field are D form. This function should 2015// only be called with the same opcodes as are handled by opstore and opload. 2016func (c *ctxt9) opform(insn uint32) int { 2017 switch insn { 2018 default: 2019 c.ctxt.Diag("bad insn in loadform: %x", insn) 2020 case OPVCC(58, 0, 0, 0), // ld 2021 OPVCC(58, 0, 0, 1), // ldu 2022 OPVCC(58, 0, 0, 0) | 1<<1, // lwa 2023 OPVCC(62, 0, 0, 0), // std 2024 OPVCC(62, 0, 0, 1): //stdu 2025 return DS_FORM 2026 case OP_ADDI, // add 2027 OPVCC(32, 0, 0, 0), // lwz 2028 OPVCC(33, 0, 0, 0), // lwzu 2029 OPVCC(34, 0, 0, 0), // lbz 2030 OPVCC(35, 0, 0, 0), // lbzu 2031 OPVCC(40, 0, 0, 0), // lhz 2032 OPVCC(41, 0, 0, 0), // lhzu 2033 OPVCC(42, 0, 0, 0), // lha 2034 OPVCC(43, 0, 0, 0), // lhau 2035 OPVCC(46, 0, 0, 0), // lmw 2036 OPVCC(48, 0, 0, 0), // lfs 2037 OPVCC(49, 0, 0, 0), // lfsu 2038 OPVCC(50, 0, 0, 0), // lfd 2039 OPVCC(51, 0, 0, 0), // lfdu 2040 OPVCC(36, 0, 0, 0), // stw 2041 OPVCC(37, 0, 0, 0), // stwu 2042 OPVCC(38, 0, 0, 0), // stb 2043 OPVCC(39, 0, 0, 0), // stbu 2044 OPVCC(44, 0, 0, 0), // sth 2045 OPVCC(45, 0, 0, 0), // sthu 2046 OPVCC(47, 0, 0, 0), // stmw 2047 OPVCC(52, 0, 0, 0), // stfs 2048 OPVCC(53, 0, 0, 0), // stfsu 2049 OPVCC(54, 0, 0, 0), // stfd 2050 OPVCC(55, 0, 0, 0): // stfdu 2051 return D_FORM 2052 } 2053 return 0 2054} 2055 2056// Encode instructions and create relocation for accessing s+d according to the 2057// instruction op with source or destination (as appropriate) register reg. 2058func (c *ctxt9) symbolAccess(s *obj.LSym, d int64, reg int16, op uint32) (o1, o2 uint32) { 2059 var base uint32 2060 form := c.opform(op) 2061 if c.ctxt.Flag_shared { 2062 base = REG_R2 2063 } else { 2064 base = REG_R0 2065 } 2066 o1 = AOP_IRR(OP_ADDIS, REGTMP, base, 0) 2067 o2 = AOP_IRR(op, uint32(reg), REGTMP, 0) 2068 rel := obj.Addrel(c.cursym) 2069 rel.Off = int32(c.pc) 2070 rel.Siz = 8 2071 rel.Sym = s 2072 rel.Add = d 2073 if c.ctxt.Flag_shared { 2074 switch form { 2075 case D_FORM: 2076 rel.Type = objabi.R_ADDRPOWER_TOCREL 2077 case DS_FORM: 2078 rel.Type = objabi.R_ADDRPOWER_TOCREL_DS 2079 } 2080 2081 } else { 2082 switch form { 2083 case D_FORM: 2084 rel.Type = objabi.R_ADDRPOWER 2085 case DS_FORM: 2086 rel.Type = objabi.R_ADDRPOWER_DS 2087 } 2088 } 2089 return 2090} 2091 2092/* 2093 * 32-bit masks 2094 */ 2095func getmask(m []byte, v uint32) bool { 2096 m[1] = 0 2097 m[0] = m[1] 2098 if v != ^uint32(0) && v&(1<<31) != 0 && v&1 != 0 { /* MB > ME */ 2099 if getmask(m, ^v) { 2100 i := int(m[0]) 2101 m[0] = m[1] + 1 2102 m[1] = byte(i - 1) 2103 return true 2104 } 2105 2106 return false 2107 } 2108 2109 for i := 0; i < 32; i++ { 2110 if v&(1<<uint(31-i)) != 0 { 2111 m[0] = byte(i) 2112 for { 2113 m[1] = byte(i) 2114 i++ 2115 if i >= 32 || v&(1<<uint(31-i)) == 0 { 2116 break 2117 } 2118 } 2119 2120 for ; i < 32; i++ { 2121 if v&(1<<uint(31-i)) != 0 { 2122 return false 2123 } 2124 } 2125 return true 2126 } 2127 } 2128 2129 return false 2130} 2131 2132func (c *ctxt9) maskgen(p *obj.Prog, m []byte, v uint32) { 2133 if !getmask(m, v) { 2134 c.ctxt.Diag("cannot generate mask #%x\n%v", v, p) 2135 } 2136} 2137 2138/* 2139 * 64-bit masks (rldic etc) 2140 */ 2141func getmask64(m []byte, v uint64) bool { 2142 m[1] = 0 2143 m[0] = m[1] 2144 for i := 0; i < 64; i++ { 2145 if v&(uint64(1)<<uint(63-i)) != 0 { 2146 m[0] = byte(i) 2147 for { 2148 m[1] = byte(i) 2149 i++ 2150 if i >= 64 || v&(uint64(1)<<uint(63-i)) == 0 { 2151 break 2152 } 2153 } 2154 2155 for ; i < 64; i++ { 2156 if v&(uint64(1)<<uint(63-i)) != 0 { 2157 return false 2158 } 2159 } 2160 return true 2161 } 2162 } 2163 2164 return false 2165} 2166 2167func (c *ctxt9) maskgen64(p *obj.Prog, m []byte, v uint64) { 2168 if !getmask64(m, v) { 2169 c.ctxt.Diag("cannot generate mask #%x\n%v", v, p) 2170 } 2171} 2172 2173func loadu32(r int, d int64) uint32 { 2174 v := int32(d >> 16) 2175 if isuint32(uint64(d)) { 2176 return LOP_IRR(OP_ORIS, uint32(r), REGZERO, uint32(v)) 2177 } 2178 return AOP_IRR(OP_ADDIS, uint32(r), REGZERO, uint32(v)) 2179} 2180 2181func high16adjusted(d int32) uint16 { 2182 if d&0x8000 != 0 { 2183 return uint16((d >> 16) + 1) 2184 } 2185 return uint16(d >> 16) 2186} 2187 2188func (c *ctxt9) asmout(p *obj.Prog, o *Optab, out []uint32) { 2189 o1 := uint32(0) 2190 o2 := uint32(0) 2191 o3 := uint32(0) 2192 o4 := uint32(0) 2193 o5 := uint32(0) 2194 2195 //print("%v => case %d\n", p, o->type); 2196 switch o.type_ { 2197 default: 2198 c.ctxt.Diag("unknown type %d", o.type_) 2199 prasm(p) 2200 2201 case 0: /* pseudo ops */ 2202 break 2203 2204 case 1: /* mov r1,r2 ==> OR Rs,Rs,Ra */ 2205 if p.To.Reg == REGZERO && p.From.Type == obj.TYPE_CONST { 2206 v := c.regoff(&p.From) 2207 if r0iszero != 0 /*TypeKind(100016)*/ && v != 0 { 2208 //nerrors--; 2209 c.ctxt.Diag("literal operation on R0\n%v", p) 2210 } 2211 2212 o1 = LOP_IRR(OP_ADDI, REGZERO, REGZERO, uint32(v)) 2213 break 2214 } 2215 2216 o1 = LOP_RRR(OP_OR, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.From.Reg)) 2217 2218 case 2: /* int/cr/fp op Rb,[Ra],Rd */ 2219 r := int(p.Reg) 2220 2221 if r == 0 { 2222 r = int(p.To.Reg) 2223 } 2224 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg)) 2225 2226 case 3: /* mov $soreg/addcon/ucon, r ==> addis/addi $i,reg',r */ 2227 d := c.vregoff(&p.From) 2228 2229 v := int32(d) 2230 r := int(p.From.Reg) 2231 if r == 0 { 2232 r = int(o.param) 2233 } 2234 if r0iszero != 0 /*TypeKind(100016)*/ && p.To.Reg == 0 && (r != 0 || v != 0) { 2235 c.ctxt.Diag("literal operation on R0\n%v", p) 2236 } 2237 a := OP_ADDI 2238 if o.a1 == C_UCON { 2239 if d&0xffff != 0 { 2240 log.Fatalf("invalid handling of %v", p) 2241 } 2242 v >>= 16 2243 if r == REGZERO && isuint32(uint64(d)) { 2244 o1 = LOP_IRR(OP_ORIS, uint32(p.To.Reg), REGZERO, uint32(v)) 2245 break 2246 } 2247 2248 a = OP_ADDIS 2249 } else { 2250 if int64(int16(d)) != d { 2251 log.Fatalf("invalid handling of %v", p) 2252 } 2253 } 2254 2255 o1 = AOP_IRR(uint32(a), uint32(p.To.Reg), uint32(r), uint32(v)) 2256 2257 case 4: /* add/mul $scon,[r1],r2 */ 2258 v := c.regoff(&p.From) 2259 2260 r := int(p.Reg) 2261 if r == 0 { 2262 r = int(p.To.Reg) 2263 } 2264 if r0iszero != 0 /*TypeKind(100016)*/ && p.To.Reg == 0 { 2265 c.ctxt.Diag("literal operation on R0\n%v", p) 2266 } 2267 if int32(int16(v)) != v { 2268 log.Fatalf("mishandled instruction %v", p) 2269 } 2270 o1 = AOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v)) 2271 2272 case 5: /* syscall */ 2273 o1 = c.oprrr(p.As) 2274 2275 case 6: /* logical op Rb,[Rs,]Ra; no literal */ 2276 r := int(p.Reg) 2277 2278 if r == 0 { 2279 r = int(p.To.Reg) 2280 } 2281 // AROTL and AROTLW are extended mnemonics, which map to RLDCL and RLWNM. 2282 switch p.As { 2283 case AROTL: 2284 o1 = AOP_RLDIC(OP_RLDCL, uint32(p.To.Reg), uint32(r), uint32(p.From.Reg), uint32(0)) 2285 case AROTLW: 2286 o1 = OP_RLW(OP_RLWNM, uint32(p.To.Reg), uint32(r), uint32(p.From.Reg), 0, 31) 2287 default: 2288 o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg)) 2289 } 2290 2291 case 7: /* mov r, soreg ==> stw o(r) */ 2292 r := int(p.To.Reg) 2293 2294 if r == 0 { 2295 r = int(o.param) 2296 } 2297 v := c.regoff(&p.To) 2298 if p.To.Type == obj.TYPE_MEM && p.To.Index != 0 { 2299 if v != 0 { 2300 c.ctxt.Diag("illegal indexed instruction\n%v", p) 2301 } 2302 if c.ctxt.Flag_shared && r == REG_R13 { 2303 rel := obj.Addrel(c.cursym) 2304 rel.Off = int32(c.pc) 2305 rel.Siz = 4 2306 // This (and the matching part in the load case 2307 // below) are the only places in the ppc64 toolchain 2308 // that knows the name of the tls variable. Possibly 2309 // we could add some assembly syntax so that the name 2310 // of the variable does not have to be assumed. 2311 rel.Sym = c.ctxt.Lookup("runtime.tls_g") 2312 rel.Type = objabi.R_POWER_TLS 2313 } 2314 o1 = AOP_RRR(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(r)) 2315 } else { 2316 if int32(int16(v)) != v { 2317 log.Fatalf("mishandled instruction %v", p) 2318 } 2319 // Offsets in DS form stores must be a multiple of 4 2320 inst := c.opstore(p.As) 2321 if c.opform(inst) == DS_FORM && v&0x3 != 0 { 2322 log.Fatalf("invalid offset for DS form load/store %v", p) 2323 } 2324 o1 = AOP_IRR(inst, uint32(p.From.Reg), uint32(r), uint32(v)) 2325 } 2326 2327 case 8: /* mov soreg, r ==> lbz/lhz/lwz o(r) */ 2328 r := int(p.From.Reg) 2329 2330 if r == 0 { 2331 r = int(o.param) 2332 } 2333 v := c.regoff(&p.From) 2334 if p.From.Type == obj.TYPE_MEM && p.From.Index != 0 { 2335 if v != 0 { 2336 c.ctxt.Diag("illegal indexed instruction\n%v", p) 2337 } 2338 if c.ctxt.Flag_shared && r == REG_R13 { 2339 rel := obj.Addrel(c.cursym) 2340 rel.Off = int32(c.pc) 2341 rel.Siz = 4 2342 rel.Sym = c.ctxt.Lookup("runtime.tls_g") 2343 rel.Type = objabi.R_POWER_TLS 2344 } 2345 o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(r)) 2346 } else { 2347 if int32(int16(v)) != v { 2348 log.Fatalf("mishandled instruction %v", p) 2349 } 2350 // Offsets in DS form loads must be a multiple of 4 2351 inst := c.opload(p.As) 2352 if c.opform(inst) == DS_FORM && v&0x3 != 0 { 2353 log.Fatalf("invalid offset for DS form load/store %v", p) 2354 } 2355 o1 = AOP_IRR(inst, uint32(p.To.Reg), uint32(r), uint32(v)) 2356 } 2357 2358 case 9: /* movb soreg, r ==> lbz o(r),r2; extsb r2,r2 */ 2359 r := int(p.From.Reg) 2360 2361 if r == 0 { 2362 r = int(o.param) 2363 } 2364 v := c.regoff(&p.From) 2365 if p.From.Type == obj.TYPE_MEM && p.From.Index != 0 { 2366 if v != 0 { 2367 c.ctxt.Diag("illegal indexed instruction\n%v", p) 2368 } 2369 o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(r)) 2370 } else { 2371 o1 = AOP_IRR(c.opload(p.As), uint32(p.To.Reg), uint32(r), uint32(v)) 2372 } 2373 o2 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0) 2374 2375 case 10: /* sub Ra,[Rb],Rd => subf Rd,Ra,Rb */ 2376 r := int(p.Reg) 2377 2378 if r == 0 { 2379 r = int(p.To.Reg) 2380 } 2381 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(r)) 2382 2383 case 11: /* br/bl lbra */ 2384 v := int32(0) 2385 2386 if p.Pcond != nil { 2387 v = int32(p.Pcond.Pc - p.Pc) 2388 if v&03 != 0 { 2389 c.ctxt.Diag("odd branch target address\n%v", p) 2390 v &^= 03 2391 } 2392 2393 if v < -(1<<25) || v >= 1<<24 { 2394 c.ctxt.Diag("branch too far\n%v", p) 2395 } 2396 } 2397 2398 o1 = OP_BR(c.opirr(p.As), uint32(v), 0) 2399 if p.To.Sym != nil { 2400 rel := obj.Addrel(c.cursym) 2401 rel.Off = int32(c.pc) 2402 rel.Siz = 4 2403 rel.Sym = p.To.Sym 2404 v += int32(p.To.Offset) 2405 if v&03 != 0 { 2406 c.ctxt.Diag("odd branch target address\n%v", p) 2407 v &^= 03 2408 } 2409 2410 rel.Add = int64(v) 2411 rel.Type = objabi.R_CALLPOWER 2412 } 2413 o2 = 0x60000000 // nop, sometimes overwritten by ld r2, 24(r1) when dynamic linking 2414 2415 case 12: /* movb r,r (extsb); movw r,r (extsw) */ 2416 if p.To.Reg == REGZERO && p.From.Type == obj.TYPE_CONST { 2417 v := c.regoff(&p.From) 2418 if r0iszero != 0 /*TypeKind(100016)*/ && v != 0 { 2419 c.ctxt.Diag("literal operation on R0\n%v", p) 2420 } 2421 2422 o1 = LOP_IRR(OP_ADDI, REGZERO, REGZERO, uint32(v)) 2423 break 2424 } 2425 2426 if p.As == AMOVW { 2427 o1 = LOP_RRR(OP_EXTSW, uint32(p.To.Reg), uint32(p.From.Reg), 0) 2428 } else { 2429 o1 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.From.Reg), 0) 2430 } 2431 2432 case 13: /* mov[bhw]z r,r; uses rlwinm not andi. to avoid changing CC */ 2433 if p.As == AMOVBZ { 2434 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(p.From.Reg), 0, 24, 31) 2435 } else if p.As == AMOVH { 2436 o1 = LOP_RRR(OP_EXTSH, uint32(p.To.Reg), uint32(p.From.Reg), 0) 2437 } else if p.As == AMOVHZ { 2438 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(p.From.Reg), 0, 16, 31) 2439 } else if p.As == AMOVWZ { 2440 o1 = OP_RLW(OP_RLDIC, uint32(p.To.Reg), uint32(p.From.Reg), 0, 0, 0) | 1<<5 /* MB=32 */ 2441 } else { 2442 c.ctxt.Diag("internal: bad mov[bhw]z\n%v", p) 2443 } 2444 2445 case 14: /* rldc[lr] Rb,Rs,$mask,Ra -- left, right give different masks */ 2446 r := int(p.Reg) 2447 2448 if r == 0 { 2449 r = int(p.To.Reg) 2450 } 2451 d := c.vregoff(p.From3) 2452 var a int 2453 switch p.As { 2454 2455 // These opcodes expect a mask operand that has to be converted into the 2456 // appropriate operand. The way these were defined, not all valid masks are possible. 2457 // Left here for compatibility in case they were used or generated. 2458 case ARLDCL, ARLDCLCC: 2459 var mask [2]uint8 2460 c.maskgen64(p, mask[:], uint64(d)) 2461 2462 a = int(mask[0]) /* MB */ 2463 if mask[1] != 63 { 2464 c.ctxt.Diag("invalid mask for rotate: %x (end != bit 63)\n%v", uint64(d), p) 2465 } 2466 o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg)) 2467 o1 |= (uint32(a) & 31) << 6 2468 if a&0x20 != 0 { 2469 o1 |= 1 << 5 /* mb[5] is top bit */ 2470 } 2471 2472 case ARLDCR, ARLDCRCC: 2473 var mask [2]uint8 2474 c.maskgen64(p, mask[:], uint64(d)) 2475 2476 a = int(mask[1]) /* ME */ 2477 if mask[0] != 0 { 2478 c.ctxt.Diag("invalid mask for rotate: %x (start != 0)\n%v", uint64(d), p) 2479 } 2480 o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg)) 2481 o1 |= (uint32(a) & 31) << 6 2482 if a&0x20 != 0 { 2483 o1 |= 1 << 5 /* mb[5] is top bit */ 2484 } 2485 2486 // These opcodes use a shift count like the ppc64 asm, no mask conversion done 2487 case ARLDICR, ARLDICRCC: 2488 me := int(d) 2489 sh := c.regoff(&p.From) 2490 o1 = AOP_RLDIC(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(sh), uint32(me)) 2491 2492 case ARLDICL, ARLDICLCC: 2493 mb := int(d) 2494 sh := c.regoff(&p.From) 2495 o1 = AOP_RLDIC(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(sh), uint32(mb)) 2496 2497 default: 2498 c.ctxt.Diag("unexpected op in rldc case\n%v", p) 2499 a = 0 2500 } 2501 2502 case 17, /* bc bo,bi,lbra (same for now) */ 2503 16: /* bc bo,bi,sbra */ 2504 a := 0 2505 2506 r := int(p.Reg) 2507 2508 if p.From.Type == obj.TYPE_CONST { 2509 a = int(c.regoff(&p.From)) 2510 } else if p.From.Type == obj.TYPE_REG { 2511 if r != 0 { 2512 c.ctxt.Diag("unexpected register setting for branch with CR: %d\n", r) 2513 } 2514 // BI values for the CR 2515 switch p.From.Reg { 2516 case REG_CR0: 2517 r = BI_CR0 2518 case REG_CR1: 2519 r = BI_CR1 2520 case REG_CR2: 2521 r = BI_CR2 2522 case REG_CR3: 2523 r = BI_CR3 2524 case REG_CR4: 2525 r = BI_CR4 2526 case REG_CR5: 2527 r = BI_CR5 2528 case REG_CR6: 2529 r = BI_CR6 2530 case REG_CR7: 2531 r = BI_CR7 2532 default: 2533 c.ctxt.Diag("unrecognized register: expecting CR\n") 2534 } 2535 } 2536 v := int32(0) 2537 if p.Pcond != nil { 2538 v = int32(p.Pcond.Pc - p.Pc) 2539 } 2540 if v&03 != 0 { 2541 c.ctxt.Diag("odd branch target address\n%v", p) 2542 v &^= 03 2543 } 2544 2545 if v < -(1<<16) || v >= 1<<15 { 2546 c.ctxt.Diag("branch too far\n%v", p) 2547 } 2548 o1 = OP_BC(c.opirr(p.As), uint32(a), uint32(r), uint32(v), 0) 2549 2550 case 15: /* br/bl (r) => mov r,lr; br/bl (lr) */ 2551 var v int32 2552 if p.As == ABC || p.As == ABCL { 2553 v = c.regoff(&p.To) & 31 2554 } else { 2555 v = 20 /* unconditional */ 2556 } 2557 o1 = AOP_RRR(OP_MTSPR, uint32(p.To.Reg), 0, 0) | (REG_LR&0x1f)<<16 | ((REG_LR>>5)&0x1f)<<11 2558 o2 = OPVCC(19, 16, 0, 0) 2559 if p.As == ABL || p.As == ABCL { 2560 o2 |= 1 2561 } 2562 o2 = OP_BCR(o2, uint32(v), uint32(p.To.Index)) 2563 2564 case 18: /* br/bl (lr/ctr); bc/bcl bo,bi,(lr/ctr) */ 2565 var v int32 2566 if p.As == ABC || p.As == ABCL { 2567 v = c.regoff(&p.From) & 31 2568 } else { 2569 v = 20 /* unconditional */ 2570 } 2571 r := int(p.Reg) 2572 if r == 0 { 2573 r = 0 2574 } 2575 switch oclass(&p.To) { 2576 case C_CTR: 2577 o1 = OPVCC(19, 528, 0, 0) 2578 2579 case C_LR: 2580 o1 = OPVCC(19, 16, 0, 0) 2581 2582 default: 2583 c.ctxt.Diag("bad optab entry (18): %d\n%v", p.To.Class, p) 2584 v = 0 2585 } 2586 2587 if p.As == ABL || p.As == ABCL { 2588 o1 |= 1 2589 } 2590 o1 = OP_BCR(o1, uint32(v), uint32(r)) 2591 2592 case 19: /* mov $lcon,r ==> cau+or */ 2593 d := c.vregoff(&p.From) 2594 2595 if p.From.Sym == nil { 2596 o1 = loadu32(int(p.To.Reg), d) 2597 o2 = LOP_IRR(OP_ORI, uint32(p.To.Reg), uint32(p.To.Reg), uint32(int32(d))) 2598 } else { 2599 o1, o2 = c.symbolAccess(p.From.Sym, d, p.To.Reg, OP_ADDI) 2600 } 2601 2602 //if(dlm) reloc(&p->from, p->pc, 0); 2603 2604 case 20: /* add $ucon,,r */ 2605 v := c.regoff(&p.From) 2606 2607 r := int(p.Reg) 2608 if r == 0 { 2609 r = int(p.To.Reg) 2610 } 2611 if p.As == AADD && (r0iszero == 0 /*TypeKind(100016)*/ && p.Reg == 0 || r0iszero != 0 /*TypeKind(100016)*/ && p.To.Reg == 0) { 2612 c.ctxt.Diag("literal operation on R0\n%v", p) 2613 } 2614 o1 = AOP_IRR(c.opirr(-p.As), uint32(p.To.Reg), uint32(r), uint32(v)>>16) 2615 2616 case 22: /* add $lcon,r1,r2 ==> cau+or+add */ /* could do add/sub more efficiently */ 2617 if p.To.Reg == REGTMP || p.Reg == REGTMP { 2618 c.ctxt.Diag("can't synthesize large constant\n%v", p) 2619 } 2620 d := c.vregoff(&p.From) 2621 o1 = loadu32(REGTMP, d) 2622 o2 = LOP_IRR(OP_ORI, REGTMP, REGTMP, uint32(int32(d))) 2623 r := int(p.Reg) 2624 if r == 0 { 2625 r = int(p.To.Reg) 2626 } 2627 o3 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r)) 2628 if p.From.Sym != nil { 2629 c.ctxt.Diag("%v is not supported", p) 2630 } 2631 2632 //if(dlm) reloc(&p->from, p->pc, 0); 2633 2634 case 23: /* and $lcon,r1,r2 ==> cau+or+and */ /* masks could be done using rlnm etc. */ 2635 if p.To.Reg == REGTMP || p.Reg == REGTMP { 2636 c.ctxt.Diag("can't synthesize large constant\n%v", p) 2637 } 2638 d := c.vregoff(&p.From) 2639 o1 = loadu32(REGTMP, d) 2640 o2 = LOP_IRR(OP_ORI, REGTMP, REGTMP, uint32(int32(d))) 2641 r := int(p.Reg) 2642 if r == 0 { 2643 r = int(p.To.Reg) 2644 } 2645 o3 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r)) 2646 if p.From.Sym != nil { 2647 c.ctxt.Diag("%v is not supported", p) 2648 } 2649 2650 //if(dlm) reloc(&p->from, p->pc, 0); 2651 2652 /*24*/ 2653 case 25: 2654 /* sld[.] $sh,rS,rA -> rldicr[.] $sh,rS,mask(0,63-sh),rA; srd[.] -> rldicl */ 2655 v := c.regoff(&p.From) 2656 2657 if v < 0 { 2658 v = 0 2659 } else if v > 63 { 2660 v = 63 2661 } 2662 r := int(p.Reg) 2663 if r == 0 { 2664 r = int(p.To.Reg) 2665 } 2666 var a int 2667 op := uint32(0) 2668 switch p.As { 2669 case ASLD, ASLDCC: 2670 a = int(63 - v) 2671 op = OP_RLDICR 2672 2673 case ASRD, ASRDCC: 2674 a = int(v) 2675 v = 64 - v 2676 op = OP_RLDICL 2677 case AROTL: 2678 a = int(0) 2679 op = OP_RLDICL 2680 default: 2681 c.ctxt.Diag("unexpected op in sldi case\n%v", p) 2682 a = 0 2683 o1 = 0 2684 } 2685 2686 o1 = AOP_RLDIC(op, uint32(p.To.Reg), uint32(r), uint32(v), uint32(a)) 2687 if p.As == ASLDCC || p.As == ASRDCC { 2688 o1 |= 1 // Set the condition code bit 2689 } 2690 2691 case 26: /* mov $lsext/auto/oreg,,r2 ==> addis+addi */ 2692 if p.To.Reg == REGTMP { 2693 c.ctxt.Diag("can't synthesize large constant\n%v", p) 2694 } 2695 v := c.regoff(&p.From) 2696 r := int(p.From.Reg) 2697 if r == 0 { 2698 r = int(o.param) 2699 } 2700 o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v))) 2701 o2 = AOP_IRR(OP_ADDI, uint32(p.To.Reg), REGTMP, uint32(v)) 2702 2703 case 27: /* subc ra,$simm,rd => subfic rd,ra,$simm */ 2704 v := c.regoff(p.From3) 2705 2706 r := int(p.From.Reg) 2707 o1 = AOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v)) 2708 2709 case 28: /* subc r1,$lcon,r2 ==> cau+or+subfc */ 2710 if p.To.Reg == REGTMP || p.From.Reg == REGTMP { 2711 c.ctxt.Diag("can't synthesize large constant\n%v", p) 2712 } 2713 v := c.regoff(p.From3) 2714 o1 = AOP_IRR(OP_ADDIS, REGTMP, REGZERO, uint32(v)>>16) 2715 o2 = LOP_IRR(OP_ORI, REGTMP, REGTMP, uint32(v)) 2716 o3 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), REGTMP) 2717 if p.From.Sym != nil { 2718 c.ctxt.Diag("%v is not supported", p) 2719 } 2720 2721 //if(dlm) reloc(&p->from3, p->pc, 0); 2722 2723 case 29: /* rldic[lr]? $sh,s,$mask,a -- left, right, plain give different masks */ 2724 v := c.regoff(&p.From) 2725 2726 d := c.vregoff(p.From3) 2727 var mask [2]uint8 2728 c.maskgen64(p, mask[:], uint64(d)) 2729 var a int 2730 switch p.As { 2731 case ARLDC, ARLDCCC: 2732 a = int(mask[0]) /* MB */ 2733 if int32(mask[1]) != (63 - v) { 2734 c.ctxt.Diag("invalid mask for shift: %x (shift %d)\n%v", uint64(d), v, p) 2735 } 2736 2737 case ARLDCL, ARLDCLCC: 2738 a = int(mask[0]) /* MB */ 2739 if mask[1] != 63 { 2740 c.ctxt.Diag("invalid mask for shift: %x (shift %d)\n%v", uint64(d), v, p) 2741 } 2742 2743 case ARLDCR, ARLDCRCC: 2744 a = int(mask[1]) /* ME */ 2745 if mask[0] != 0 { 2746 c.ctxt.Diag("invalid mask for shift: %x (shift %d)\n%v", uint64(d), v, p) 2747 } 2748 2749 default: 2750 c.ctxt.Diag("unexpected op in rldic case\n%v", p) 2751 a = 0 2752 } 2753 2754 o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), (uint32(v) & 0x1F)) 2755 o1 |= (uint32(a) & 31) << 6 2756 if v&0x20 != 0 { 2757 o1 |= 1 << 1 2758 } 2759 if a&0x20 != 0 { 2760 o1 |= 1 << 5 /* mb[5] is top bit */ 2761 } 2762 2763 case 30: /* rldimi $sh,s,$mask,a */ 2764 v := c.regoff(&p.From) 2765 2766 d := c.vregoff(p.From3) 2767 2768 // Original opcodes had mask operands which had to be converted to a shift count as expected by 2769 // the ppc64 asm. 2770 switch p.As { 2771 case ARLDMI, ARLDMICC: 2772 var mask [2]uint8 2773 c.maskgen64(p, mask[:], uint64(d)) 2774 if int32(mask[1]) != (63 - v) { 2775 c.ctxt.Diag("invalid mask for shift: %x (shift %d)\n%v", uint64(d), v, p) 2776 } 2777 o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), (uint32(v) & 0x1F)) 2778 o1 |= (uint32(mask[0]) & 31) << 6 2779 if v&0x20 != 0 { 2780 o1 |= 1 << 1 2781 } 2782 if mask[0]&0x20 != 0 { 2783 o1 |= 1 << 5 /* mb[5] is top bit */ 2784 } 2785 2786 // Opcodes with shift count operands. 2787 case ARLDIMI, ARLDIMICC: 2788 o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), (uint32(v) & 0x1F)) 2789 o1 |= (uint32(d) & 31) << 6 2790 if d&0x20 != 0 { 2791 o1 |= 1 << 5 2792 } 2793 if v&0x20 != 0 { 2794 o1 |= 1 << 1 2795 } 2796 } 2797 2798 case 31: /* dword */ 2799 d := c.vregoff(&p.From) 2800 2801 if c.ctxt.Arch.ByteOrder == binary.BigEndian { 2802 o1 = uint32(d >> 32) 2803 o2 = uint32(d) 2804 } else { 2805 o1 = uint32(d) 2806 o2 = uint32(d >> 32) 2807 } 2808 2809 if p.From.Sym != nil { 2810 rel := obj.Addrel(c.cursym) 2811 rel.Off = int32(c.pc) 2812 rel.Siz = 8 2813 rel.Sym = p.From.Sym 2814 rel.Add = p.From.Offset 2815 rel.Type = objabi.R_ADDR 2816 o2 = 0 2817 o1 = o2 2818 } 2819 2820 case 32: /* fmul frc,fra,frd */ 2821 r := int(p.Reg) 2822 2823 if r == 0 { 2824 r = int(p.To.Reg) 2825 } 2826 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0) | (uint32(p.From.Reg)&31)<<6 2827 2828 case 33: /* fabs [frb,]frd; fmr. frb,frd */ 2829 r := int(p.From.Reg) 2830 2831 if oclass(&p.From) == C_NONE { 2832 r = int(p.To.Reg) 2833 } 2834 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), 0, uint32(r)) 2835 2836 case 34: /* FMADDx fra,frb,frc,frt (t=a*c±b) */ 2837 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) | (uint32(p.From3.Reg)&31)<<6 2838 2839 case 35: /* mov r,lext/lauto/loreg ==> cau $(v>>16),sb,r'; store o(r') */ 2840 v := c.regoff(&p.To) 2841 2842 r := int(p.To.Reg) 2843 if r == 0 { 2844 r = int(o.param) 2845 } 2846 // Offsets in DS form stores must be a multiple of 4 2847 inst := c.opstore(p.As) 2848 if c.opform(inst) == DS_FORM && v&0x3 != 0 { 2849 log.Fatalf("invalid offset for DS form load/store %v", p) 2850 } 2851 o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v))) 2852 o2 = AOP_IRR(inst, uint32(p.From.Reg), REGTMP, uint32(v)) 2853 2854 case 36: /* mov bz/h/hz lext/lauto/lreg,r ==> lbz/lha/lhz etc */ 2855 v := c.regoff(&p.From) 2856 2857 r := int(p.From.Reg) 2858 if r == 0 { 2859 r = int(o.param) 2860 } 2861 o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v))) 2862 o2 = AOP_IRR(c.opload(p.As), uint32(p.To.Reg), REGTMP, uint32(v)) 2863 2864 case 37: /* movb lext/lauto/lreg,r ==> lbz o(reg),r; extsb r */ 2865 v := c.regoff(&p.From) 2866 2867 r := int(p.From.Reg) 2868 if r == 0 { 2869 r = int(o.param) 2870 } 2871 o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v))) 2872 o2 = AOP_IRR(c.opload(p.As), uint32(p.To.Reg), REGTMP, uint32(v)) 2873 o3 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0) 2874 2875 case 40: /* word */ 2876 o1 = uint32(c.regoff(&p.From)) 2877 2878 case 41: /* stswi */ 2879 o1 = AOP_RRR(c.opirr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), 0) | (uint32(c.regoff(p.From3))&0x7F)<<11 2880 2881 case 42: /* lswi */ 2882 o1 = AOP_RRR(c.opirr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), 0) | (uint32(c.regoff(p.From3))&0x7F)<<11 2883 2884 case 43: /* unary indexed source: dcbf (b); dcbf (a+b) */ 2885 o1 = AOP_RRR(c.oprrr(p.As), 0, uint32(p.From.Index), uint32(p.From.Reg)) 2886 2887 case 44: /* indexed store */ 2888 o1 = AOP_RRR(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(p.To.Reg)) 2889 2890 case 45: /* indexed load */ 2891 o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg)) 2892 2893 case 46: /* plain op */ 2894 o1 = c.oprrr(p.As) 2895 2896 case 47: /* op Ra, Rd; also op [Ra,] Rd */ 2897 r := int(p.From.Reg) 2898 2899 if r == 0 { 2900 r = int(p.To.Reg) 2901 } 2902 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0) 2903 2904 case 48: /* op Rs, Ra */ 2905 r := int(p.From.Reg) 2906 2907 if r == 0 { 2908 r = int(p.To.Reg) 2909 } 2910 o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0) 2911 2912 case 49: /* op Rb; op $n, Rb */ 2913 if p.From.Type != obj.TYPE_REG { /* tlbie $L, rB */ 2914 v := c.regoff(&p.From) & 1 2915 o1 = AOP_RRR(c.oprrr(p.As), 0, 0, uint32(p.To.Reg)) | uint32(v)<<21 2916 } else { 2917 o1 = AOP_RRR(c.oprrr(p.As), 0, 0, uint32(p.From.Reg)) 2918 } 2919 2920 case 50: /* rem[u] r1[,r2],r3 */ 2921 r := int(p.Reg) 2922 2923 if r == 0 { 2924 r = int(p.To.Reg) 2925 } 2926 v := c.oprrr(p.As) 2927 t := v & (1<<10 | 1) /* OE|Rc */ 2928 o1 = AOP_RRR(v&^t, REGTMP, uint32(r), uint32(p.From.Reg)) 2929 o2 = AOP_RRR(OP_MULLW, REGTMP, REGTMP, uint32(p.From.Reg)) 2930 o3 = AOP_RRR(OP_SUBF|t, uint32(p.To.Reg), REGTMP, uint32(r)) 2931 if p.As == AREMU { 2932 o4 = o3 2933 2934 /* Clear top 32 bits */ 2935 o3 = OP_RLW(OP_RLDIC, REGTMP, REGTMP, 0, 0, 0) | 1<<5 2936 } 2937 2938 case 51: /* remd[u] r1[,r2],r3 */ 2939 r := int(p.Reg) 2940 2941 if r == 0 { 2942 r = int(p.To.Reg) 2943 } 2944 v := c.oprrr(p.As) 2945 t := v & (1<<10 | 1) /* OE|Rc */ 2946 o1 = AOP_RRR(v&^t, REGTMP, uint32(r), uint32(p.From.Reg)) 2947 o2 = AOP_RRR(OP_MULLD, REGTMP, REGTMP, uint32(p.From.Reg)) 2948 o3 = AOP_RRR(OP_SUBF|t, uint32(p.To.Reg), REGTMP, uint32(r)) 2949 2950 case 52: /* mtfsbNx cr(n) */ 2951 v := c.regoff(&p.From) & 31 2952 2953 o1 = AOP_RRR(c.oprrr(p.As), uint32(v), 0, 0) 2954 2955 case 53: /* mffsX ,fr1 */ 2956 o1 = AOP_RRR(OP_MFFS, uint32(p.To.Reg), 0, 0) 2957 2958 case 54: /* mov msr,r1; mov r1, msr*/ 2959 if oclass(&p.From) == C_REG { 2960 if p.As == AMOVD { 2961 o1 = AOP_RRR(OP_MTMSRD, uint32(p.From.Reg), 0, 0) 2962 } else { 2963 o1 = AOP_RRR(OP_MTMSR, uint32(p.From.Reg), 0, 0) 2964 } 2965 } else { 2966 o1 = AOP_RRR(OP_MFMSR, uint32(p.To.Reg), 0, 0) 2967 } 2968 2969 case 55: /* op Rb, Rd */ 2970 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), 0, uint32(p.From.Reg)) 2971 2972 case 56: /* sra $sh,[s,]a; srd $sh,[s,]a */ 2973 v := c.regoff(&p.From) 2974 2975 r := int(p.Reg) 2976 if r == 0 { 2977 r = int(p.To.Reg) 2978 } 2979 o1 = AOP_RRR(c.opirr(p.As), uint32(r), uint32(p.To.Reg), uint32(v)&31) 2980 if (p.As == ASRAD || p.As == ASRADCC) && (v&0x20 != 0) { 2981 o1 |= 1 << 1 /* mb[5] */ 2982 } 2983 2984 case 57: /* slw $sh,[s,]a -> rlwinm ... */ 2985 v := c.regoff(&p.From) 2986 2987 r := int(p.Reg) 2988 if r == 0 { 2989 r = int(p.To.Reg) 2990 } 2991 2992 /* 2993 * Let user (gs) shoot himself in the foot. 2994 * qc has already complained. 2995 * 2996 if(v < 0 || v > 31) 2997 ctxt->diag("illegal shift %ld\n%v", v, p); 2998 */ 2999 if v < 0 { 3000 v = 0 3001 } else if v > 32 { 3002 v = 32 3003 } 3004 var mask [2]uint8 3005 switch p.As { 3006 case AROTLW: 3007 mask[0], mask[1] = 0, 31 3008 case ASRW, ASRWCC: 3009 mask[0], mask[1] = uint8(v), 31 3010 v = 32 - v 3011 default: 3012 mask[0], mask[1] = 0, uint8(31-v) 3013 } 3014 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(r), uint32(v), uint32(mask[0]), uint32(mask[1])) 3015 if p.As == ASLWCC || p.As == ASRWCC { 3016 o1 |= 1 // set the condition code 3017 } 3018 3019 case 58: /* logical $andcon,[s],a */ 3020 v := c.regoff(&p.From) 3021 3022 r := int(p.Reg) 3023 if r == 0 { 3024 r = int(p.To.Reg) 3025 } 3026 o1 = LOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v)) 3027 3028 case 59: /* or/and $ucon,,r */ 3029 v := c.regoff(&p.From) 3030 3031 r := int(p.Reg) 3032 if r == 0 { 3033 r = int(p.To.Reg) 3034 } 3035 o1 = LOP_IRR(c.opirr(-p.As), uint32(p.To.Reg), uint32(r), uint32(v)>>16) /* oris, xoris, andis */ 3036 3037 case 60: /* tw to,a,b */ 3038 r := int(c.regoff(&p.From) & 31) 3039 3040 o1 = AOP_RRR(c.oprrr(p.As), uint32(r), uint32(p.Reg), uint32(p.To.Reg)) 3041 3042 case 61: /* tw to,a,$simm */ 3043 r := int(c.regoff(&p.From) & 31) 3044 3045 v := c.regoff(&p.To) 3046 o1 = AOP_IRR(c.opirr(p.As), uint32(r), uint32(p.Reg), uint32(v)) 3047 3048 case 62: /* rlwmi $sh,s,$mask,a */ 3049 v := c.regoff(&p.From) 3050 3051 var mask [2]uint8 3052 c.maskgen(p, mask[:], uint32(c.regoff(p.From3))) 3053 o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), uint32(v)) 3054 o1 |= (uint32(mask[0])&31)<<6 | (uint32(mask[1])&31)<<1 3055 3056 case 63: /* rlwmi b,s,$mask,a */ 3057 var mask [2]uint8 3058 c.maskgen(p, mask[:], uint32(c.regoff(p.From3))) 3059 3060 o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), uint32(p.From.Reg)) 3061 o1 |= (uint32(mask[0])&31)<<6 | (uint32(mask[1])&31)<<1 3062 3063 case 64: /* mtfsf fr[, $m] {,fpcsr} */ 3064 var v int32 3065 if p.From3Type() != obj.TYPE_NONE { 3066 v = c.regoff(p.From3) & 255 3067 } else { 3068 v = 255 3069 } 3070 o1 = OP_MTFSF | uint32(v)<<17 | uint32(p.From.Reg)<<11 3071 3072 case 65: /* MOVFL $imm,FPSCR(n) => mtfsfi crfd,imm */ 3073 if p.To.Reg == 0 { 3074 c.ctxt.Diag("must specify FPSCR(n)\n%v", p) 3075 } 3076 o1 = OP_MTFSFI | (uint32(p.To.Reg)&15)<<23 | (uint32(c.regoff(&p.From))&31)<<12 3077 3078 case 66: /* mov spr,r1; mov r1,spr, also dcr */ 3079 var r int 3080 var v int32 3081 if REG_R0 <= p.From.Reg && p.From.Reg <= REG_R31 { 3082 r = int(p.From.Reg) 3083 v = int32(p.To.Reg) 3084 if REG_DCR0 <= v && v <= REG_DCR0+1023 { 3085 o1 = OPVCC(31, 451, 0, 0) /* mtdcr */ 3086 } else { 3087 o1 = OPVCC(31, 467, 0, 0) /* mtspr */ 3088 } 3089 } else { 3090 r = int(p.To.Reg) 3091 v = int32(p.From.Reg) 3092 if REG_DCR0 <= v && v <= REG_DCR0+1023 { 3093 o1 = OPVCC(31, 323, 0, 0) /* mfdcr */ 3094 } else { 3095 o1 = OPVCC(31, 339, 0, 0) /* mfspr */ 3096 } 3097 } 3098 3099 o1 = AOP_RRR(o1, uint32(r), 0, 0) | (uint32(v)&0x1f)<<16 | ((uint32(v)>>5)&0x1f)<<11 3100 3101 case 67: /* mcrf crfD,crfS */ 3102 if p.From.Type != obj.TYPE_REG || p.From.Reg < REG_CR0 || REG_CR7 < p.From.Reg || p.To.Type != obj.TYPE_REG || p.To.Reg < REG_CR0 || REG_CR7 < p.To.Reg { 3103 c.ctxt.Diag("illegal CR field number\n%v", p) 3104 } 3105 o1 = AOP_RRR(OP_MCRF, ((uint32(p.To.Reg) & 7) << 2), ((uint32(p.From.Reg) & 7) << 2), 0) 3106 3107 case 68: /* mfcr rD; mfocrf CRM,rD */ 3108 if p.From.Type == obj.TYPE_REG && REG_CR0 <= p.From.Reg && p.From.Reg <= REG_CR7 { 3109 v := int32(1 << uint(7-(p.To.Reg&7))) /* CR(n) */ 3110 o1 = AOP_RRR(OP_MFCR, uint32(p.To.Reg), 0, 0) | 1<<20 | uint32(v)<<12 /* new form, mfocrf */ 3111 } else { 3112 o1 = AOP_RRR(OP_MFCR, uint32(p.To.Reg), 0, 0) /* old form, whole register */ 3113 } 3114 3115 case 69: /* mtcrf CRM,rS */ 3116 var v int32 3117 if p.From3Type() != obj.TYPE_NONE { 3118 if p.To.Reg != 0 { 3119 c.ctxt.Diag("can't use both mask and CR(n)\n%v", p) 3120 } 3121 v = c.regoff(p.From3) & 0xff 3122 } else { 3123 if p.To.Reg == 0 { 3124 v = 0xff /* CR */ 3125 } else { 3126 v = 1 << uint(7-(p.To.Reg&7)) /* CR(n) */ 3127 } 3128 } 3129 3130 o1 = AOP_RRR(OP_MTCRF, uint32(p.From.Reg), 0, 0) | uint32(v)<<12 3131 3132 case 70: /* [f]cmp r,r,cr*/ 3133 var r int 3134 if p.Reg == 0 { 3135 r = 0 3136 } else { 3137 r = (int(p.Reg) & 7) << 2 3138 } 3139 o1 = AOP_RRR(c.oprrr(p.As), uint32(r), uint32(p.From.Reg), uint32(p.To.Reg)) 3140 3141 case 71: /* cmp[l] r,i,cr*/ 3142 var r int 3143 if p.Reg == 0 { 3144 r = 0 3145 } else { 3146 r = (int(p.Reg) & 7) << 2 3147 } 3148 o1 = AOP_RRR(c.opirr(p.As), uint32(r), uint32(p.From.Reg), 0) | uint32(c.regoff(&p.To))&0xffff 3149 3150 case 72: /* slbmte (Rb+Rs -> slb[Rb]) -> Rs, Rb */ 3151 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), 0, uint32(p.To.Reg)) 3152 3153 case 73: /* mcrfs crfD,crfS */ 3154 if p.From.Type != obj.TYPE_REG || p.From.Reg != REG_FPSCR || p.To.Type != obj.TYPE_REG || p.To.Reg < REG_CR0 || REG_CR7 < p.To.Reg { 3155 c.ctxt.Diag("illegal FPSCR/CR field number\n%v", p) 3156 } 3157 o1 = AOP_RRR(OP_MCRFS, ((uint32(p.To.Reg) & 7) << 2), ((0 & 7) << 2), 0) 3158 3159 case 77: /* syscall $scon, syscall Rx */ 3160 if p.From.Type == obj.TYPE_CONST { 3161 if p.From.Offset > BIG || p.From.Offset < -BIG { 3162 c.ctxt.Diag("illegal syscall, sysnum too large: %v", p) 3163 } 3164 o1 = AOP_IRR(OP_ADDI, REGZERO, REGZERO, uint32(p.From.Offset)) 3165 } else if p.From.Type == obj.TYPE_REG { 3166 o1 = LOP_RRR(OP_OR, REGZERO, uint32(p.From.Reg), uint32(p.From.Reg)) 3167 } else { 3168 c.ctxt.Diag("illegal syscall: %v", p) 3169 o1 = 0x7fe00008 // trap always 3170 } 3171 3172 o2 = c.oprrr(p.As) 3173 o3 = AOP_RRR(c.oprrr(AXOR), REGZERO, REGZERO, REGZERO) // XOR R0, R0 3174 3175 case 78: /* undef */ 3176 o1 = 0 /* "An instruction consisting entirely of binary 0s is guaranteed 3177 always to be an illegal instruction." */ 3178 3179 /* relocation operations */ 3180 case 74: 3181 v := c.vregoff(&p.To) 3182 // Offsets in DS form stores must be a multiple of 4 3183 inst := c.opstore(p.As) 3184 if c.opform(inst) == DS_FORM && v&0x3 != 0 { 3185 log.Fatalf("invalid offset for DS form load/store %v", p) 3186 } 3187 o1, o2 = c.symbolAccess(p.To.Sym, v, p.From.Reg, inst) 3188 3189 //if(dlm) reloc(&p->to, p->pc, 1); 3190 3191 case 75: 3192 v := c.vregoff(&p.From) 3193 // Offsets in DS form loads must be a multiple of 4 3194 inst := c.opload(p.As) 3195 if c.opform(inst) == DS_FORM && v&0x3 != 0 { 3196 log.Fatalf("invalid offset for DS form load/store %v", p) 3197 } 3198 o1, o2 = c.symbolAccess(p.From.Sym, v, p.To.Reg, inst) 3199 3200 //if(dlm) reloc(&p->from, p->pc, 1); 3201 3202 case 76: 3203 v := c.vregoff(&p.From) 3204 // Offsets in DS form loads must be a multiple of 4 3205 inst := c.opload(p.As) 3206 if c.opform(inst) == DS_FORM && v&0x3 != 0 { 3207 log.Fatalf("invalid offset for DS form load/store %v", p) 3208 } 3209 o1, o2 = c.symbolAccess(p.From.Sym, v, p.To.Reg, inst) 3210 o3 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0) 3211 3212 //if(dlm) reloc(&p->from, p->pc, 1); 3213 3214 case 79: 3215 if p.From.Offset != 0 { 3216 c.ctxt.Diag("invalid offset against tls var %v", p) 3217 } 3218 o1 = AOP_IRR(OP_ADDI, uint32(p.To.Reg), REGZERO, 0) 3219 rel := obj.Addrel(c.cursym) 3220 rel.Off = int32(c.pc) 3221 rel.Siz = 4 3222 rel.Sym = p.From.Sym 3223 rel.Type = objabi.R_POWER_TLS_LE 3224 3225 case 80: 3226 if p.From.Offset != 0 { 3227 c.ctxt.Diag("invalid offset against tls var %v", p) 3228 } 3229 o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), REG_R2, 0) 3230 o2 = AOP_IRR(c.opload(AMOVD), uint32(p.To.Reg), uint32(p.To.Reg), 0) 3231 rel := obj.Addrel(c.cursym) 3232 rel.Off = int32(c.pc) 3233 rel.Siz = 8 3234 rel.Sym = p.From.Sym 3235 rel.Type = objabi.R_POWER_TLS_IE 3236 3237 case 81: 3238 v := c.vregoff(&p.To) 3239 if v != 0 { 3240 c.ctxt.Diag("invalid offset against GOT slot %v", p) 3241 } 3242 3243 o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), REG_R2, 0) 3244 o2 = AOP_IRR(c.opload(AMOVD), uint32(p.To.Reg), uint32(p.To.Reg), 0) 3245 rel := obj.Addrel(c.cursym) 3246 rel.Off = int32(c.pc) 3247 rel.Siz = 8 3248 rel.Sym = p.From.Sym 3249 rel.Type = objabi.R_ADDRPOWER_GOT 3250 case 82: /* vector instructions, VX-form and VC-form */ 3251 if p.From.Type == obj.TYPE_REG { 3252 /* reg reg none OR reg reg reg */ 3253 /* 3-register operand order: VRA, VRB, VRT */ 3254 /* 2-register operand order: VRA, VRT */ 3255 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) 3256 } else if p.From3Type() == obj.TYPE_CONST { 3257 /* imm imm reg reg */ 3258 /* operand order: SIX, VRA, ST, VRT */ 3259 six := int(c.regoff(&p.From)) 3260 st := int(c.regoff(p.From3)) 3261 o1 = AOP_IIRR(c.opiirr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(st), uint32(six)) 3262 } else if p.From3Type() == obj.TYPE_NONE && p.Reg != 0 { 3263 /* imm reg reg */ 3264 /* operand order: UIM, VRB, VRT */ 3265 uim := int(c.regoff(&p.From)) 3266 o1 = AOP_VIRR(c.opirr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(uim)) 3267 } else { 3268 /* imm reg */ 3269 /* operand order: SIM, VRT */ 3270 sim := int(c.regoff(&p.From)) 3271 o1 = AOP_IR(c.opirr(p.As), uint32(p.To.Reg), uint32(sim)) 3272 } 3273 3274 case 83: /* vector instructions, VA-form */ 3275 if p.From.Type == obj.TYPE_REG { 3276 /* reg reg reg reg */ 3277 /* 4-register operand order: VRA, VRB, VRC, VRT */ 3278 o1 = AOP_RRRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(p.From3.Reg)) 3279 } else if p.From.Type == obj.TYPE_CONST { 3280 /* imm reg reg reg */ 3281 /* operand order: SHB, VRA, VRB, VRT */ 3282 shb := int(c.regoff(&p.From)) 3283 o1 = AOP_IRRR(c.opirrr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(p.From3.Reg), uint32(shb)) 3284 } 3285 3286 case 84: // ISEL BC,RA,RB,RT -> isel rt,ra,rb,bc 3287 bc := c.vregoff(&p.From) 3288 3289 // rt = To.Reg, ra = p.Reg, rb = p.From3.Reg 3290 o1 = AOP_ISEL(OP_ISEL, uint32(p.To.Reg), uint32(p.Reg), uint32(p.From3.Reg), uint32(bc)) 3291 3292 case 85: /* vector instructions, VX-form */ 3293 /* reg none reg */ 3294 /* 2-register operand order: VRB, VRT */ 3295 o1 = AOP_RR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg)) 3296 3297 case 86: /* VSX indexed store, XX1-form */ 3298 /* reg reg reg */ 3299 /* 3-register operand order: XT, (RB)(RA*1) */ 3300 o1 = AOP_XX1(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(p.To.Reg)) 3301 3302 case 87: /* VSX indexed load, XX1-form */ 3303 /* reg reg reg */ 3304 /* 3-register operand order: (RB)(RA*1), XT */ 3305 o1 = AOP_XX1(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg)) 3306 3307 case 88: /* VSX instructions, XX1-form */ 3308 /* reg reg none OR reg reg reg */ 3309 /* 3-register operand order: RA, RB, XT */ 3310 /* 2-register operand order: XS, RA or RA, XT */ 3311 xt := int32(p.To.Reg) 3312 xs := int32(p.From.Reg) 3313 /* We need to treat the special case of extended mnemonics that may have a FREG/VREG as an argument */ 3314 if REG_V0 <= xt && xt <= REG_V31 { 3315 /* Convert V0-V31 to VS32-VS63 */ 3316 xt = xt + 64 3317 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) 3318 } else if REG_F0 <= xt && xt <= REG_F31 { 3319 /* Convert F0-F31 to VS0-VS31 */ 3320 xt = xt + 64 3321 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) 3322 } else if REG_VS0 <= xt && xt <= REG_VS63 { 3323 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) 3324 } else if REG_V0 <= xs && xs <= REG_V31 { 3325 /* Likewise for XS */ 3326 xs = xs + 64 3327 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg)) 3328 } else if REG_F0 <= xs && xs <= REG_F31 { 3329 xs = xs + 64 3330 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg)) 3331 } else if REG_VS0 <= xs && xs <= REG_VS63 { 3332 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg)) 3333 } 3334 3335 case 89: /* VSX instructions, XX2-form */ 3336 /* reg none reg OR reg imm reg */ 3337 /* 2-register operand order: XB, XT or XB, UIM, XT*/ 3338 uim := int(c.regoff(p.From3)) 3339 o1 = AOP_XX2(c.oprrr(p.As), uint32(p.To.Reg), uint32(uim), uint32(p.From.Reg)) 3340 3341 case 90: /* VSX instructions, XX3-form */ 3342 if p.From3Type() == obj.TYPE_NONE { 3343 /* reg reg reg */ 3344 /* 3-register operand order: XA, XB, XT */ 3345 o1 = AOP_XX3(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) 3346 } else if p.From3Type() == obj.TYPE_CONST { 3347 /* reg reg reg imm */ 3348 /* operand order: XA, XB, DM, XT */ 3349 dm := int(c.regoff(p.From3)) 3350 o1 = AOP_XX3I(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(dm)) 3351 } 3352 3353 case 91: /* VSX instructions, XX4-form */ 3354 /* reg reg reg reg */ 3355 /* 3-register operand order: XA, XB, XC, XT */ 3356 o1 = AOP_XX4(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(p.From3.Reg)) 3357 3358 case 92: /* X-form instructions, 3-operands */ 3359 if p.To.Type == obj.TYPE_CONST { 3360 /* imm reg reg */ 3361 /* operand order: FRA, FRB, BF */ 3362 bf := int(c.regoff(&p.To)) << 2 3363 o1 = AOP_RRR(c.opirr(p.As), uint32(bf), uint32(p.From.Reg), uint32(p.Reg)) 3364 } else if p.To.Type == obj.TYPE_REG { 3365 /* reg reg reg */ 3366 /* operand order: RS, RB, RA */ 3367 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg)) 3368 } 3369 3370 case 93: /* X-form instructions, 2-operands */ 3371 if p.To.Type == obj.TYPE_CONST { 3372 /* imm reg */ 3373 /* operand order: FRB, BF */ 3374 bf := int(c.regoff(&p.To)) << 2 3375 o1 = AOP_RR(c.opirr(p.As), uint32(bf), uint32(p.From.Reg)) 3376 } else if p.Reg == 0 { 3377 /* popcnt* r,r, X-form */ 3378 /* operand order: RS, RA */ 3379 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg)) 3380 } 3381 3382 } 3383 3384 out[0] = o1 3385 out[1] = o2 3386 out[2] = o3 3387 out[3] = o4 3388 out[4] = o5 3389 return 3390} 3391 3392func (c *ctxt9) vregoff(a *obj.Addr) int64 { 3393 c.instoffset = 0 3394 if a != nil { 3395 c.aclass(a) 3396 } 3397 return c.instoffset 3398} 3399 3400func (c *ctxt9) regoff(a *obj.Addr) int32 { 3401 return int32(c.vregoff(a)) 3402} 3403 3404func (c *ctxt9) oprrr(a obj.As) uint32 { 3405 switch a { 3406 case AADD: 3407 return OPVCC(31, 266, 0, 0) 3408 case AADDCC: 3409 return OPVCC(31, 266, 0, 1) 3410 case AADDV: 3411 return OPVCC(31, 266, 1, 0) 3412 case AADDVCC: 3413 return OPVCC(31, 266, 1, 1) 3414 case AADDC: 3415 return OPVCC(31, 10, 0, 0) 3416 case AADDCCC: 3417 return OPVCC(31, 10, 0, 1) 3418 case AADDCV: 3419 return OPVCC(31, 10, 1, 0) 3420 case AADDCVCC: 3421 return OPVCC(31, 10, 1, 1) 3422 case AADDE: 3423 return OPVCC(31, 138, 0, 0) 3424 case AADDECC: 3425 return OPVCC(31, 138, 0, 1) 3426 case AADDEV: 3427 return OPVCC(31, 138, 1, 0) 3428 case AADDEVCC: 3429 return OPVCC(31, 138, 1, 1) 3430 case AADDME: 3431 return OPVCC(31, 234, 0, 0) 3432 case AADDMECC: 3433 return OPVCC(31, 234, 0, 1) 3434 case AADDMEV: 3435 return OPVCC(31, 234, 1, 0) 3436 case AADDMEVCC: 3437 return OPVCC(31, 234, 1, 1) 3438 case AADDZE: 3439 return OPVCC(31, 202, 0, 0) 3440 case AADDZECC: 3441 return OPVCC(31, 202, 0, 1) 3442 case AADDZEV: 3443 return OPVCC(31, 202, 1, 0) 3444 case AADDZEVCC: 3445 return OPVCC(31, 202, 1, 1) 3446 3447 case AAND: 3448 return OPVCC(31, 28, 0, 0) 3449 case AANDCC: 3450 return OPVCC(31, 28, 0, 1) 3451 case AANDN: 3452 return OPVCC(31, 60, 0, 0) 3453 case AANDNCC: 3454 return OPVCC(31, 60, 0, 1) 3455 3456 case ACMP: 3457 return OPVCC(31, 0, 0, 0) | 1<<21 /* L=1 */ 3458 case ACMPU: 3459 return OPVCC(31, 32, 0, 0) | 1<<21 3460 case ACMPW: 3461 return OPVCC(31, 0, 0, 0) /* L=0 */ 3462 case ACMPWU: 3463 return OPVCC(31, 32, 0, 0) 3464 case ACMPB: 3465 return OPVCC(31, 508, 0, 0) /* cmpb - v2.05 */ 3466 3467 case ACNTLZW: 3468 return OPVCC(31, 26, 0, 0) 3469 case ACNTLZWCC: 3470 return OPVCC(31, 26, 0, 1) 3471 case ACNTLZD: 3472 return OPVCC(31, 58, 0, 0) 3473 case ACNTLZDCC: 3474 return OPVCC(31, 58, 0, 1) 3475 3476 case ACRAND: 3477 return OPVCC(19, 257, 0, 0) 3478 case ACRANDN: 3479 return OPVCC(19, 129, 0, 0) 3480 case ACREQV: 3481 return OPVCC(19, 289, 0, 0) 3482 case ACRNAND: 3483 return OPVCC(19, 225, 0, 0) 3484 case ACRNOR: 3485 return OPVCC(19, 33, 0, 0) 3486 case ACROR: 3487 return OPVCC(19, 449, 0, 0) 3488 case ACRORN: 3489 return OPVCC(19, 417, 0, 0) 3490 case ACRXOR: 3491 return OPVCC(19, 193, 0, 0) 3492 3493 case ADCBF: 3494 return OPVCC(31, 86, 0, 0) 3495 case ADCBI: 3496 return OPVCC(31, 470, 0, 0) 3497 case ADCBST: 3498 return OPVCC(31, 54, 0, 0) 3499 case ADCBT: 3500 return OPVCC(31, 278, 0, 0) 3501 case ADCBTST: 3502 return OPVCC(31, 246, 0, 0) 3503 case ADCBZ: 3504 return OPVCC(31, 1014, 0, 0) 3505 3506 case AREM, ADIVW: 3507 return OPVCC(31, 491, 0, 0) 3508 3509 case AREMCC, ADIVWCC: 3510 return OPVCC(31, 491, 0, 1) 3511 3512 case AREMV, ADIVWV: 3513 return OPVCC(31, 491, 1, 0) 3514 3515 case AREMVCC, ADIVWVCC: 3516 return OPVCC(31, 491, 1, 1) 3517 3518 case AREMU, ADIVWU: 3519 return OPVCC(31, 459, 0, 0) 3520 3521 case AREMUCC, ADIVWUCC: 3522 return OPVCC(31, 459, 0, 1) 3523 3524 case AREMUV, ADIVWUV: 3525 return OPVCC(31, 459, 1, 0) 3526 3527 case AREMUVCC, ADIVWUVCC: 3528 return OPVCC(31, 459, 1, 1) 3529 3530 case AREMD, ADIVD: 3531 return OPVCC(31, 489, 0, 0) 3532 3533 case AREMDCC, ADIVDCC: 3534 return OPVCC(31, 489, 0, 1) 3535 3536 case ADIVDE: 3537 return OPVCC(31, 425, 0, 0) 3538 3539 case ADIVDECC: 3540 return OPVCC(31, 425, 0, 1) 3541 3542 case ADIVDEU: 3543 return OPVCC(31, 393, 0, 0) 3544 3545 case ADIVDEUCC: 3546 return OPVCC(31, 393, 0, 1) 3547 3548 case AREMDV, ADIVDV: 3549 return OPVCC(31, 489, 1, 0) 3550 3551 case AREMDVCC, ADIVDVCC: 3552 return OPVCC(31, 489, 1, 1) 3553 3554 case AREMDU, ADIVDU: 3555 return OPVCC(31, 457, 0, 0) 3556 3557 case AREMDUCC, ADIVDUCC: 3558 return OPVCC(31, 457, 0, 1) 3559 3560 case AREMDUV, ADIVDUV: 3561 return OPVCC(31, 457, 1, 0) 3562 3563 case AREMDUVCC, ADIVDUVCC: 3564 return OPVCC(31, 457, 1, 1) 3565 3566 case AEIEIO: 3567 return OPVCC(31, 854, 0, 0) 3568 3569 case AEQV: 3570 return OPVCC(31, 284, 0, 0) 3571 case AEQVCC: 3572 return OPVCC(31, 284, 0, 1) 3573 3574 case AEXTSB: 3575 return OPVCC(31, 954, 0, 0) 3576 case AEXTSBCC: 3577 return OPVCC(31, 954, 0, 1) 3578 case AEXTSH: 3579 return OPVCC(31, 922, 0, 0) 3580 case AEXTSHCC: 3581 return OPVCC(31, 922, 0, 1) 3582 case AEXTSW: 3583 return OPVCC(31, 986, 0, 0) 3584 case AEXTSWCC: 3585 return OPVCC(31, 986, 0, 1) 3586 3587 case AFABS: 3588 return OPVCC(63, 264, 0, 0) 3589 case AFABSCC: 3590 return OPVCC(63, 264, 0, 1) 3591 case AFADD: 3592 return OPVCC(63, 21, 0, 0) 3593 case AFADDCC: 3594 return OPVCC(63, 21, 0, 1) 3595 case AFADDS: 3596 return OPVCC(59, 21, 0, 0) 3597 case AFADDSCC: 3598 return OPVCC(59, 21, 0, 1) 3599 case AFCMPO: 3600 return OPVCC(63, 32, 0, 0) 3601 case AFCMPU: 3602 return OPVCC(63, 0, 0, 0) 3603 case AFCFID: 3604 return OPVCC(63, 846, 0, 0) 3605 case AFCFIDCC: 3606 return OPVCC(63, 846, 0, 1) 3607 case AFCFIDU: 3608 return OPVCC(63, 974, 0, 0) 3609 case AFCFIDUCC: 3610 return OPVCC(63, 974, 0, 1) 3611 case AFCTIW: 3612 return OPVCC(63, 14, 0, 0) 3613 case AFCTIWCC: 3614 return OPVCC(63, 14, 0, 1) 3615 case AFCTIWZ: 3616 return OPVCC(63, 15, 0, 0) 3617 case AFCTIWZCC: 3618 return OPVCC(63, 15, 0, 1) 3619 case AFCTID: 3620 return OPVCC(63, 814, 0, 0) 3621 case AFCTIDCC: 3622 return OPVCC(63, 814, 0, 1) 3623 case AFCTIDZ: 3624 return OPVCC(63, 815, 0, 0) 3625 case AFCTIDZCC: 3626 return OPVCC(63, 815, 0, 1) 3627 case AFDIV: 3628 return OPVCC(63, 18, 0, 0) 3629 case AFDIVCC: 3630 return OPVCC(63, 18, 0, 1) 3631 case AFDIVS: 3632 return OPVCC(59, 18, 0, 0) 3633 case AFDIVSCC: 3634 return OPVCC(59, 18, 0, 1) 3635 case AFMADD: 3636 return OPVCC(63, 29, 0, 0) 3637 case AFMADDCC: 3638 return OPVCC(63, 29, 0, 1) 3639 case AFMADDS: 3640 return OPVCC(59, 29, 0, 0) 3641 case AFMADDSCC: 3642 return OPVCC(59, 29, 0, 1) 3643 3644 case AFMOVS, AFMOVD: 3645 return OPVCC(63, 72, 0, 0) /* load */ 3646 case AFMOVDCC: 3647 return OPVCC(63, 72, 0, 1) 3648 case AFMSUB: 3649 return OPVCC(63, 28, 0, 0) 3650 case AFMSUBCC: 3651 return OPVCC(63, 28, 0, 1) 3652 case AFMSUBS: 3653 return OPVCC(59, 28, 0, 0) 3654 case AFMSUBSCC: 3655 return OPVCC(59, 28, 0, 1) 3656 case AFMUL: 3657 return OPVCC(63, 25, 0, 0) 3658 case AFMULCC: 3659 return OPVCC(63, 25, 0, 1) 3660 case AFMULS: 3661 return OPVCC(59, 25, 0, 0) 3662 case AFMULSCC: 3663 return OPVCC(59, 25, 0, 1) 3664 case AFNABS: 3665 return OPVCC(63, 136, 0, 0) 3666 case AFNABSCC: 3667 return OPVCC(63, 136, 0, 1) 3668 case AFNEG: 3669 return OPVCC(63, 40, 0, 0) 3670 case AFNEGCC: 3671 return OPVCC(63, 40, 0, 1) 3672 case AFNMADD: 3673 return OPVCC(63, 31, 0, 0) 3674 case AFNMADDCC: 3675 return OPVCC(63, 31, 0, 1) 3676 case AFNMADDS: 3677 return OPVCC(59, 31, 0, 0) 3678 case AFNMADDSCC: 3679 return OPVCC(59, 31, 0, 1) 3680 case AFNMSUB: 3681 return OPVCC(63, 30, 0, 0) 3682 case AFNMSUBCC: 3683 return OPVCC(63, 30, 0, 1) 3684 case AFNMSUBS: 3685 return OPVCC(59, 30, 0, 0) 3686 case AFNMSUBSCC: 3687 return OPVCC(59, 30, 0, 1) 3688 case AFRES: 3689 return OPVCC(59, 24, 0, 0) 3690 case AFRESCC: 3691 return OPVCC(59, 24, 0, 1) 3692 case AFRIM: 3693 return OPVCC(63, 488, 0, 0) 3694 case AFRIMCC: 3695 return OPVCC(63, 488, 0, 1) 3696 case AFRIP: 3697 return OPVCC(63, 456, 0, 0) 3698 case AFRIPCC: 3699 return OPVCC(63, 456, 0, 1) 3700 case AFRIZ: 3701 return OPVCC(63, 424, 0, 0) 3702 case AFRIZCC: 3703 return OPVCC(63, 424, 0, 1) 3704 case AFRSP: 3705 return OPVCC(63, 12, 0, 0) 3706 case AFRSPCC: 3707 return OPVCC(63, 12, 0, 1) 3708 case AFRSQRTE: 3709 return OPVCC(63, 26, 0, 0) 3710 case AFRSQRTECC: 3711 return OPVCC(63, 26, 0, 1) 3712 case AFSEL: 3713 return OPVCC(63, 23, 0, 0) 3714 case AFSELCC: 3715 return OPVCC(63, 23, 0, 1) 3716 case AFSQRT: 3717 return OPVCC(63, 22, 0, 0) 3718 case AFSQRTCC: 3719 return OPVCC(63, 22, 0, 1) 3720 case AFSQRTS: 3721 return OPVCC(59, 22, 0, 0) 3722 case AFSQRTSCC: 3723 return OPVCC(59, 22, 0, 1) 3724 case AFSUB: 3725 return OPVCC(63, 20, 0, 0) 3726 case AFSUBCC: 3727 return OPVCC(63, 20, 0, 1) 3728 case AFSUBS: 3729 return OPVCC(59, 20, 0, 0) 3730 case AFSUBSCC: 3731 return OPVCC(59, 20, 0, 1) 3732 3733 case AICBI: 3734 return OPVCC(31, 982, 0, 0) 3735 case AISYNC: 3736 return OPVCC(19, 150, 0, 0) 3737 3738 case AMTFSB0: 3739 return OPVCC(63, 70, 0, 0) 3740 case AMTFSB0CC: 3741 return OPVCC(63, 70, 0, 1) 3742 case AMTFSB1: 3743 return OPVCC(63, 38, 0, 0) 3744 case AMTFSB1CC: 3745 return OPVCC(63, 38, 0, 1) 3746 3747 case AMULHW: 3748 return OPVCC(31, 75, 0, 0) 3749 case AMULHWCC: 3750 return OPVCC(31, 75, 0, 1) 3751 case AMULHWU: 3752 return OPVCC(31, 11, 0, 0) 3753 case AMULHWUCC: 3754 return OPVCC(31, 11, 0, 1) 3755 case AMULLW: 3756 return OPVCC(31, 235, 0, 0) 3757 case AMULLWCC: 3758 return OPVCC(31, 235, 0, 1) 3759 case AMULLWV: 3760 return OPVCC(31, 235, 1, 0) 3761 case AMULLWVCC: 3762 return OPVCC(31, 235, 1, 1) 3763 3764 case AMULHD: 3765 return OPVCC(31, 73, 0, 0) 3766 case AMULHDCC: 3767 return OPVCC(31, 73, 0, 1) 3768 case AMULHDU: 3769 return OPVCC(31, 9, 0, 0) 3770 case AMULHDUCC: 3771 return OPVCC(31, 9, 0, 1) 3772 case AMULLD: 3773 return OPVCC(31, 233, 0, 0) 3774 case AMULLDCC: 3775 return OPVCC(31, 233, 0, 1) 3776 case AMULLDV: 3777 return OPVCC(31, 233, 1, 0) 3778 case AMULLDVCC: 3779 return OPVCC(31, 233, 1, 1) 3780 3781 case ANAND: 3782 return OPVCC(31, 476, 0, 0) 3783 case ANANDCC: 3784 return OPVCC(31, 476, 0, 1) 3785 case ANEG: 3786 return OPVCC(31, 104, 0, 0) 3787 case ANEGCC: 3788 return OPVCC(31, 104, 0, 1) 3789 case ANEGV: 3790 return OPVCC(31, 104, 1, 0) 3791 case ANEGVCC: 3792 return OPVCC(31, 104, 1, 1) 3793 case ANOR: 3794 return OPVCC(31, 124, 0, 0) 3795 case ANORCC: 3796 return OPVCC(31, 124, 0, 1) 3797 case AOR: 3798 return OPVCC(31, 444, 0, 0) 3799 case AORCC: 3800 return OPVCC(31, 444, 0, 1) 3801 case AORN: 3802 return OPVCC(31, 412, 0, 0) 3803 case AORNCC: 3804 return OPVCC(31, 412, 0, 1) 3805 3806 case APOPCNTD: 3807 return OPVCC(31, 506, 0, 0) /* popcntd - v2.06 */ 3808 case APOPCNTW: 3809 return OPVCC(31, 378, 0, 0) /* popcntw - v2.06 */ 3810 case APOPCNTB: 3811 return OPVCC(31, 122, 0, 0) /* popcntb - v2.02 */ 3812 3813 case ARFI: 3814 return OPVCC(19, 50, 0, 0) 3815 case ARFCI: 3816 return OPVCC(19, 51, 0, 0) 3817 case ARFID: 3818 return OPVCC(19, 18, 0, 0) 3819 case AHRFID: 3820 return OPVCC(19, 274, 0, 0) 3821 3822 case ARLWMI: 3823 return OPVCC(20, 0, 0, 0) 3824 case ARLWMICC: 3825 return OPVCC(20, 0, 0, 1) 3826 case ARLWNM: 3827 return OPVCC(23, 0, 0, 0) 3828 case ARLWNMCC: 3829 return OPVCC(23, 0, 0, 1) 3830 3831 case ARLDCL: 3832 return OPVCC(30, 8, 0, 0) 3833 case ARLDCR: 3834 return OPVCC(30, 9, 0, 0) 3835 3836 case ARLDICL: 3837 return OPVCC(30, 0, 0, 0) 3838 case ARLDICLCC: 3839 return OPVCC(30, 0, 0, 1) 3840 case ARLDICR: 3841 return OPVCC(30, 0, 0, 0) | 2<<1 // rldicr 3842 case ARLDICRCC: 3843 return OPVCC(30, 0, 0, 1) | 2<<1 // rldicr. 3844 3845 case ASYSCALL: 3846 return OPVCC(17, 1, 0, 0) 3847 3848 case ASLW: 3849 return OPVCC(31, 24, 0, 0) 3850 case ASLWCC: 3851 return OPVCC(31, 24, 0, 1) 3852 case ASLD: 3853 return OPVCC(31, 27, 0, 0) 3854 case ASLDCC: 3855 return OPVCC(31, 27, 0, 1) 3856 3857 case ASRAW: 3858 return OPVCC(31, 792, 0, 0) 3859 case ASRAWCC: 3860 return OPVCC(31, 792, 0, 1) 3861 case ASRAD: 3862 return OPVCC(31, 794, 0, 0) 3863 case ASRADCC: 3864 return OPVCC(31, 794, 0, 1) 3865 3866 case ASRW: 3867 return OPVCC(31, 536, 0, 0) 3868 case ASRWCC: 3869 return OPVCC(31, 536, 0, 1) 3870 case ASRD: 3871 return OPVCC(31, 539, 0, 0) 3872 case ASRDCC: 3873 return OPVCC(31, 539, 0, 1) 3874 3875 case ASUB: 3876 return OPVCC(31, 40, 0, 0) 3877 case ASUBCC: 3878 return OPVCC(31, 40, 0, 1) 3879 case ASUBV: 3880 return OPVCC(31, 40, 1, 0) 3881 case ASUBVCC: 3882 return OPVCC(31, 40, 1, 1) 3883 case ASUBC: 3884 return OPVCC(31, 8, 0, 0) 3885 case ASUBCCC: 3886 return OPVCC(31, 8, 0, 1) 3887 case ASUBCV: 3888 return OPVCC(31, 8, 1, 0) 3889 case ASUBCVCC: 3890 return OPVCC(31, 8, 1, 1) 3891 case ASUBE: 3892 return OPVCC(31, 136, 0, 0) 3893 case ASUBECC: 3894 return OPVCC(31, 136, 0, 1) 3895 case ASUBEV: 3896 return OPVCC(31, 136, 1, 0) 3897 case ASUBEVCC: 3898 return OPVCC(31, 136, 1, 1) 3899 case ASUBME: 3900 return OPVCC(31, 232, 0, 0) 3901 case ASUBMECC: 3902 return OPVCC(31, 232, 0, 1) 3903 case ASUBMEV: 3904 return OPVCC(31, 232, 1, 0) 3905 case ASUBMEVCC: 3906 return OPVCC(31, 232, 1, 1) 3907 case ASUBZE: 3908 return OPVCC(31, 200, 0, 0) 3909 case ASUBZECC: 3910 return OPVCC(31, 200, 0, 1) 3911 case ASUBZEV: 3912 return OPVCC(31, 200, 1, 0) 3913 case ASUBZEVCC: 3914 return OPVCC(31, 200, 1, 1) 3915 3916 case ASYNC: 3917 return OPVCC(31, 598, 0, 0) 3918 case ALWSYNC: 3919 return OPVCC(31, 598, 0, 0) | 1<<21 3920 3921 case APTESYNC: 3922 return OPVCC(31, 598, 0, 0) | 2<<21 3923 3924 case ATLBIE: 3925 return OPVCC(31, 306, 0, 0) 3926 case ATLBIEL: 3927 return OPVCC(31, 274, 0, 0) 3928 case ATLBSYNC: 3929 return OPVCC(31, 566, 0, 0) 3930 case ASLBIA: 3931 return OPVCC(31, 498, 0, 0) 3932 case ASLBIE: 3933 return OPVCC(31, 434, 0, 0) 3934 case ASLBMFEE: 3935 return OPVCC(31, 915, 0, 0) 3936 case ASLBMFEV: 3937 return OPVCC(31, 851, 0, 0) 3938 case ASLBMTE: 3939 return OPVCC(31, 402, 0, 0) 3940 3941 case ATW: 3942 return OPVCC(31, 4, 0, 0) 3943 case ATD: 3944 return OPVCC(31, 68, 0, 0) 3945 3946 /* Vector (VMX/Altivec) instructions */ 3947 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */ 3948 /* are enabled starting at POWER6 (ISA 2.05). */ 3949 case AVAND: 3950 return OPVX(4, 1028, 0, 0) /* vand - v2.03 */ 3951 case AVANDC: 3952 return OPVX(4, 1092, 0, 0) /* vandc - v2.03 */ 3953 case AVNAND: 3954 return OPVX(4, 1412, 0, 0) /* vnand - v2.07 */ 3955 3956 case AVOR: 3957 return OPVX(4, 1156, 0, 0) /* vor - v2.03 */ 3958 case AVORC: 3959 return OPVX(4, 1348, 0, 0) /* vorc - v2.07 */ 3960 case AVNOR: 3961 return OPVX(4, 1284, 0, 0) /* vnor - v2.03 */ 3962 case AVXOR: 3963 return OPVX(4, 1220, 0, 0) /* vxor - v2.03 */ 3964 case AVEQV: 3965 return OPVX(4, 1668, 0, 0) /* veqv - v2.07 */ 3966 3967 case AVADDUBM: 3968 return OPVX(4, 0, 0, 0) /* vaddubm - v2.03 */ 3969 case AVADDUHM: 3970 return OPVX(4, 64, 0, 0) /* vadduhm - v2.03 */ 3971 case AVADDUWM: 3972 return OPVX(4, 128, 0, 0) /* vadduwm - v2.03 */ 3973 case AVADDUDM: 3974 return OPVX(4, 192, 0, 0) /* vaddudm - v2.07 */ 3975 case AVADDUQM: 3976 return OPVX(4, 256, 0, 0) /* vadduqm - v2.07 */ 3977 3978 case AVADDCUQ: 3979 return OPVX(4, 320, 0, 0) /* vaddcuq - v2.07 */ 3980 case AVADDCUW: 3981 return OPVX(4, 384, 0, 0) /* vaddcuw - v2.03 */ 3982 3983 case AVADDUBS: 3984 return OPVX(4, 512, 0, 0) /* vaddubs - v2.03 */ 3985 case AVADDUHS: 3986 return OPVX(4, 576, 0, 0) /* vadduhs - v2.03 */ 3987 case AVADDUWS: 3988 return OPVX(4, 640, 0, 0) /* vadduws - v2.03 */ 3989 3990 case AVADDSBS: 3991 return OPVX(4, 768, 0, 0) /* vaddsbs - v2.03 */ 3992 case AVADDSHS: 3993 return OPVX(4, 832, 0, 0) /* vaddshs - v2.03 */ 3994 case AVADDSWS: 3995 return OPVX(4, 896, 0, 0) /* vaddsws - v2.03 */ 3996 3997 case AVADDEUQM: 3998 return OPVX(4, 60, 0, 0) /* vaddeuqm - v2.07 */ 3999 case AVADDECUQ: 4000 return OPVX(4, 61, 0, 0) /* vaddecuq - v2.07 */ 4001 4002 case AVPMSUMB: 4003 return OPVX(4, 1032, 0, 0) /* vpmsumb - v2.07 */ 4004 case AVPMSUMH: 4005 return OPVX(4, 1096, 0, 0) /* vpmsumh - v2.07 */ 4006 case AVPMSUMW: 4007 return OPVX(4, 1160, 0, 0) /* vpmsumw - v2.07 */ 4008 case AVPMSUMD: 4009 return OPVX(4, 1224, 0, 0) /* vpmsumd - v2.07 */ 4010 4011 case AVSUBUBM: 4012 return OPVX(4, 1024, 0, 0) /* vsububm - v2.03 */ 4013 case AVSUBUHM: 4014 return OPVX(4, 1088, 0, 0) /* vsubuhm - v2.03 */ 4015 case AVSUBUWM: 4016 return OPVX(4, 1152, 0, 0) /* vsubuwm - v2.03 */ 4017 case AVSUBUDM: 4018 return OPVX(4, 1216, 0, 0) /* vsubudm - v2.07 */ 4019 case AVSUBUQM: 4020 return OPVX(4, 1280, 0, 0) /* vsubuqm - v2.07 */ 4021 4022 case AVSUBCUQ: 4023 return OPVX(4, 1344, 0, 0) /* vsubcuq - v2.07 */ 4024 case AVSUBCUW: 4025 return OPVX(4, 1408, 0, 0) /* vsubcuw - v2.03 */ 4026 4027 case AVSUBUBS: 4028 return OPVX(4, 1536, 0, 0) /* vsububs - v2.03 */ 4029 case AVSUBUHS: 4030 return OPVX(4, 1600, 0, 0) /* vsubuhs - v2.03 */ 4031 case AVSUBUWS: 4032 return OPVX(4, 1664, 0, 0) /* vsubuws - v2.03 */ 4033 4034 case AVSUBSBS: 4035 return OPVX(4, 1792, 0, 0) /* vsubsbs - v2.03 */ 4036 case AVSUBSHS: 4037 return OPVX(4, 1856, 0, 0) /* vsubshs - v2.03 */ 4038 case AVSUBSWS: 4039 return OPVX(4, 1920, 0, 0) /* vsubsws - v2.03 */ 4040 4041 case AVSUBEUQM: 4042 return OPVX(4, 62, 0, 0) /* vsubeuqm - v2.07 */ 4043 case AVSUBECUQ: 4044 return OPVX(4, 63, 0, 0) /* vsubecuq - v2.07 */ 4045 4046 case AVRLB: 4047 return OPVX(4, 4, 0, 0) /* vrlb - v2.03 */ 4048 case AVRLH: 4049 return OPVX(4, 68, 0, 0) /* vrlh - v2.03 */ 4050 case AVRLW: 4051 return OPVX(4, 132, 0, 0) /* vrlw - v2.03 */ 4052 case AVRLD: 4053 return OPVX(4, 196, 0, 0) /* vrld - v2.07 */ 4054 4055 case AVSLB: 4056 return OPVX(4, 260, 0, 0) /* vslh - v2.03 */ 4057 case AVSLH: 4058 return OPVX(4, 324, 0, 0) /* vslh - v2.03 */ 4059 case AVSLW: 4060 return OPVX(4, 388, 0, 0) /* vslw - v2.03 */ 4061 case AVSL: 4062 return OPVX(4, 452, 0, 0) /* vsl - v2.03 */ 4063 case AVSLO: 4064 return OPVX(4, 1036, 0, 0) /* vsl - v2.03 */ 4065 case AVSRB: 4066 return OPVX(4, 516, 0, 0) /* vsrb - v2.03 */ 4067 case AVSRH: 4068 return OPVX(4, 580, 0, 0) /* vsrh - v2.03 */ 4069 case AVSRW: 4070 return OPVX(4, 644, 0, 0) /* vsrw - v2.03 */ 4071 case AVSR: 4072 return OPVX(4, 708, 0, 0) /* vsr - v2.03 */ 4073 case AVSRO: 4074 return OPVX(4, 1100, 0, 0) /* vsro - v2.03 */ 4075 case AVSLD: 4076 return OPVX(4, 1476, 0, 0) /* vsld - v2.07 */ 4077 case AVSRD: 4078 return OPVX(4, 1732, 0, 0) /* vsrd - v2.07 */ 4079 4080 case AVSRAB: 4081 return OPVX(4, 772, 0, 0) /* vsrab - v2.03 */ 4082 case AVSRAH: 4083 return OPVX(4, 836, 0, 0) /* vsrah - v2.03 */ 4084 case AVSRAW: 4085 return OPVX(4, 900, 0, 0) /* vsraw - v2.03 */ 4086 case AVSRAD: 4087 return OPVX(4, 964, 0, 0) /* vsrad - v2.07 */ 4088 4089 case AVCLZB: 4090 return OPVX(4, 1794, 0, 0) /* vclzb - v2.07 */ 4091 case AVCLZH: 4092 return OPVX(4, 1858, 0, 0) /* vclzh - v2.07 */ 4093 case AVCLZW: 4094 return OPVX(4, 1922, 0, 0) /* vclzw - v2.07 */ 4095 case AVCLZD: 4096 return OPVX(4, 1986, 0, 0) /* vclzd - v2.07 */ 4097 4098 case AVPOPCNTB: 4099 return OPVX(4, 1795, 0, 0) /* vpopcntb - v2.07 */ 4100 case AVPOPCNTH: 4101 return OPVX(4, 1859, 0, 0) /* vpopcnth - v2.07 */ 4102 case AVPOPCNTW: 4103 return OPVX(4, 1923, 0, 0) /* vpopcntw - v2.07 */ 4104 case AVPOPCNTD: 4105 return OPVX(4, 1987, 0, 0) /* vpopcntd - v2.07 */ 4106 4107 case AVCMPEQUB: 4108 return OPVC(4, 6, 0, 0) /* vcmpequb - v2.03 */ 4109 case AVCMPEQUBCC: 4110 return OPVC(4, 6, 0, 1) /* vcmpequb. - v2.03 */ 4111 case AVCMPEQUH: 4112 return OPVC(4, 70, 0, 0) /* vcmpequh - v2.03 */ 4113 case AVCMPEQUHCC: 4114 return OPVC(4, 70, 0, 1) /* vcmpequh. - v2.03 */ 4115 case AVCMPEQUW: 4116 return OPVC(4, 134, 0, 0) /* vcmpequw - v2.03 */ 4117 case AVCMPEQUWCC: 4118 return OPVC(4, 134, 0, 1) /* vcmpequw. - v2.03 */ 4119 case AVCMPEQUD: 4120 return OPVC(4, 199, 0, 0) /* vcmpequd - v2.07 */ 4121 case AVCMPEQUDCC: 4122 return OPVC(4, 199, 0, 1) /* vcmpequd. - v2.07 */ 4123 4124 case AVCMPGTUB: 4125 return OPVC(4, 518, 0, 0) /* vcmpgtub - v2.03 */ 4126 case AVCMPGTUBCC: 4127 return OPVC(4, 518, 0, 1) /* vcmpgtub. - v2.03 */ 4128 case AVCMPGTUH: 4129 return OPVC(4, 582, 0, 0) /* vcmpgtuh - v2.03 */ 4130 case AVCMPGTUHCC: 4131 return OPVC(4, 582, 0, 1) /* vcmpgtuh. - v2.03 */ 4132 case AVCMPGTUW: 4133 return OPVC(4, 646, 0, 0) /* vcmpgtuw - v2.03 */ 4134 case AVCMPGTUWCC: 4135 return OPVC(4, 646, 0, 1) /* vcmpgtuw. - v2.03 */ 4136 case AVCMPGTUD: 4137 return OPVC(4, 711, 0, 0) /* vcmpgtud - v2.07 */ 4138 case AVCMPGTUDCC: 4139 return OPVC(4, 711, 0, 1) /* vcmpgtud. v2.07 */ 4140 case AVCMPGTSB: 4141 return OPVC(4, 774, 0, 0) /* vcmpgtsb - v2.03 */ 4142 case AVCMPGTSBCC: 4143 return OPVC(4, 774, 0, 1) /* vcmpgtsb. - v2.03 */ 4144 case AVCMPGTSH: 4145 return OPVC(4, 838, 0, 0) /* vcmpgtsh - v2.03 */ 4146 case AVCMPGTSHCC: 4147 return OPVC(4, 838, 0, 1) /* vcmpgtsh. - v2.03 */ 4148 case AVCMPGTSW: 4149 return OPVC(4, 902, 0, 0) /* vcmpgtsw - v2.03 */ 4150 case AVCMPGTSWCC: 4151 return OPVC(4, 902, 0, 1) /* vcmpgtsw. - v2.03 */ 4152 case AVCMPGTSD: 4153 return OPVC(4, 967, 0, 0) /* vcmpgtsd - v2.07 */ 4154 case AVCMPGTSDCC: 4155 return OPVC(4, 967, 0, 1) /* vcmpgtsd. - v2.07 */ 4156 4157 case AVPERM: 4158 return OPVX(4, 43, 0, 0) /* vperm - v2.03 */ 4159 4160 case AVSEL: 4161 return OPVX(4, 42, 0, 0) /* vsel - v2.03 */ 4162 4163 case AVCIPHER: 4164 return OPVX(4, 1288, 0, 0) /* vcipher - v2.07 */ 4165 case AVCIPHERLAST: 4166 return OPVX(4, 1289, 0, 0) /* vcipherlast - v2.07 */ 4167 case AVNCIPHER: 4168 return OPVX(4, 1352, 0, 0) /* vncipher - v2.07 */ 4169 case AVNCIPHERLAST: 4170 return OPVX(4, 1353, 0, 0) /* vncipherlast - v2.07 */ 4171 case AVSBOX: 4172 return OPVX(4, 1480, 0, 0) /* vsbox - v2.07 */ 4173 /* End of vector instructions */ 4174 4175 /* Vector scalar (VSX) instructions */ 4176 /* ISA 2.06 enables these for POWER7. */ 4177 case AMFVSRD, AMFVRD, AMFFPRD: 4178 return OPVXX1(31, 51, 0) /* mfvsrd - v2.07 */ 4179 case AMFVSRWZ: 4180 return OPVXX1(31, 115, 0) /* mfvsrwz - v2.07 */ 4181 4182 case AMTVSRD, AMTFPRD, AMTVRD: 4183 return OPVXX1(31, 179, 0) /* mtvsrd - v2.07 */ 4184 case AMTVSRWA: 4185 return OPVXX1(31, 211, 0) /* mtvsrwa - v2.07 */ 4186 case AMTVSRWZ: 4187 return OPVXX1(31, 243, 0) /* mtvsrwz - v2.07 */ 4188 4189 case AXXLANDQ: 4190 return OPVXX3(60, 130, 0) /* xxland - v2.06 */ 4191 case AXXLANDC: 4192 return OPVXX3(60, 138, 0) /* xxlandc - v2.06 */ 4193 case AXXLEQV: 4194 return OPVXX3(60, 186, 0) /* xxleqv - v2.07 */ 4195 case AXXLNAND: 4196 return OPVXX3(60, 178, 0) /* xxlnand - v2.07 */ 4197 4198 case AXXLORC: 4199 return OPVXX3(60, 170, 0) /* xxlorc - v2.07 */ 4200 case AXXLNOR: 4201 return OPVXX3(60, 162, 0) /* xxlnor - v2.06 */ 4202 case AXXLORQ: 4203 return OPVXX3(60, 146, 0) /* xxlor - v2.06 */ 4204 case AXXLXOR: 4205 return OPVXX3(60, 154, 0) /* xxlxor - v2.06 */ 4206 4207 case AXXSEL: 4208 return OPVXX4(60, 3, 0) /* xxsel - v2.06 */ 4209 4210 case AXXMRGHW: 4211 return OPVXX3(60, 18, 0) /* xxmrghw - v2.06 */ 4212 case AXXMRGLW: 4213 return OPVXX3(60, 50, 0) /* xxmrglw - v2.06 */ 4214 4215 case AXXSPLTW: 4216 return OPVXX2(60, 164, 0) /* xxspltw - v2.06 */ 4217 4218 case AXXPERMDI: 4219 return OPVXX3(60, 10, 0) /* xxpermdi - v2.06 */ 4220 4221 case AXXSLDWI: 4222 return OPVXX3(60, 2, 0) /* xxsldwi - v2.06 */ 4223 4224 case AXSCVDPSP: 4225 return OPVXX2(60, 265, 0) /* xscvdpsp - v2.06 */ 4226 case AXSCVSPDP: 4227 return OPVXX2(60, 329, 0) /* xscvspdp - v2.06 */ 4228 case AXSCVDPSPN: 4229 return OPVXX2(60, 267, 0) /* xscvdpspn - v2.07 */ 4230 case AXSCVSPDPN: 4231 return OPVXX2(60, 331, 0) /* xscvspdpn - v2.07 */ 4232 4233 case AXVCVDPSP: 4234 return OPVXX2(60, 393, 0) /* xvcvdpsp - v2.06 */ 4235 case AXVCVSPDP: 4236 return OPVXX2(60, 457, 0) /* xvcvspdp - v2.06 */ 4237 4238 case AXSCVDPSXDS: 4239 return OPVXX2(60, 344, 0) /* xscvdpsxds - v2.06 */ 4240 case AXSCVDPSXWS: 4241 return OPVXX2(60, 88, 0) /* xscvdpsxws - v2.06 */ 4242 case AXSCVDPUXDS: 4243 return OPVXX2(60, 328, 0) /* xscvdpuxds - v2.06 */ 4244 case AXSCVDPUXWS: 4245 return OPVXX2(60, 72, 0) /* xscvdpuxws - v2.06 */ 4246 4247 case AXSCVSXDDP: 4248 return OPVXX2(60, 376, 0) /* xscvsxddp - v2.06 */ 4249 case AXSCVUXDDP: 4250 return OPVXX2(60, 360, 0) /* xscvuxddp - v2.06 */ 4251 case AXSCVSXDSP: 4252 return OPVXX2(60, 312, 0) /* xscvsxdsp - v2.06 */ 4253 case AXSCVUXDSP: 4254 return OPVXX2(60, 296, 0) /* xscvuxdsp - v2.06 */ 4255 4256 case AXVCVDPSXDS: 4257 return OPVXX2(60, 472, 0) /* xvcvdpsxds - v2.06 */ 4258 case AXVCVDPSXWS: 4259 return OPVXX2(60, 216, 0) /* xvcvdpsxws - v2.06 */ 4260 case AXVCVDPUXDS: 4261 return OPVXX2(60, 456, 0) /* xvcvdpuxds - v2.06 */ 4262 case AXVCVDPUXWS: 4263 return OPVXX2(60, 200, 0) /* xvcvdpuxws - v2.06 */ 4264 case AXVCVSPSXDS: 4265 return OPVXX2(60, 408, 0) /* xvcvspsxds - v2.07 */ 4266 case AXVCVSPSXWS: 4267 return OPVXX2(60, 152, 0) /* xvcvspsxws - v2.07 */ 4268 case AXVCVSPUXDS: 4269 return OPVXX2(60, 392, 0) /* xvcvspuxds - v2.07 */ 4270 case AXVCVSPUXWS: 4271 return OPVXX2(60, 136, 0) /* xvcvspuxws - v2.07 */ 4272 4273 case AXVCVSXDDP: 4274 return OPVXX2(60, 504, 0) /* xvcvsxddp - v2.06 */ 4275 case AXVCVSXWDP: 4276 return OPVXX2(60, 248, 0) /* xvcvsxwdp - v2.06 */ 4277 case AXVCVUXDDP: 4278 return OPVXX2(60, 488, 0) /* xvcvuxddp - v2.06 */ 4279 case AXVCVUXWDP: 4280 return OPVXX2(60, 232, 0) /* xvcvuxwdp - v2.06 */ 4281 case AXVCVSXDSP: 4282 return OPVXX2(60, 440, 0) /* xvcvsxdsp - v2.06 */ 4283 case AXVCVSXWSP: 4284 return OPVXX2(60, 184, 0) /* xvcvsxwsp - v2.06 */ 4285 case AXVCVUXDSP: 4286 return OPVXX2(60, 424, 0) /* xvcvuxdsp - v2.06 */ 4287 case AXVCVUXWSP: 4288 return OPVXX2(60, 168, 0) /* xvcvuxwsp - v2.06 */ 4289 /* End of VSX instructions */ 4290 4291 case AXOR: 4292 return OPVCC(31, 316, 0, 0) 4293 case AXORCC: 4294 return OPVCC(31, 316, 0, 1) 4295 } 4296 4297 c.ctxt.Diag("bad r/r, r/r/r or r/r/r/r opcode %v", a) 4298 return 0 4299} 4300 4301func (c *ctxt9) opirrr(a obj.As) uint32 { 4302 switch a { 4303 /* Vector (VMX/Altivec) instructions */ 4304 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */ 4305 /* are enabled starting at POWER6 (ISA 2.05). */ 4306 case AVSLDOI: 4307 return OPVX(4, 44, 0, 0) /* vsldoi - v2.03 */ 4308 } 4309 4310 c.ctxt.Diag("bad i/r/r/r opcode %v", a) 4311 return 0 4312} 4313 4314func (c *ctxt9) opiirr(a obj.As) uint32 { 4315 switch a { 4316 /* Vector (VMX/Altivec) instructions */ 4317 /* ISA 2.07 enables these for POWER8 and beyond. */ 4318 case AVSHASIGMAW: 4319 return OPVX(4, 1666, 0, 0) /* vshasigmaw - v2.07 */ 4320 case AVSHASIGMAD: 4321 return OPVX(4, 1730, 0, 0) /* vshasigmad - v2.07 */ 4322 } 4323 4324 c.ctxt.Diag("bad i/i/r/r opcode %v", a) 4325 return 0 4326} 4327 4328func (c *ctxt9) opirr(a obj.As) uint32 { 4329 switch a { 4330 case AADD: 4331 return OPVCC(14, 0, 0, 0) 4332 case AADDC: 4333 return OPVCC(12, 0, 0, 0) 4334 case AADDCCC: 4335 return OPVCC(13, 0, 0, 0) 4336 case -AADD: 4337 return OPVCC(15, 0, 0, 0) /* ADDIS/CAU */ 4338 4339 case AANDCC: 4340 return OPVCC(28, 0, 0, 0) 4341 case -AANDCC: 4342 return OPVCC(29, 0, 0, 0) /* ANDIS./ANDIU. */ 4343 4344 case ABR: 4345 return OPVCC(18, 0, 0, 0) 4346 case ABL: 4347 return OPVCC(18, 0, 0, 0) | 1 4348 case obj.ADUFFZERO: 4349 return OPVCC(18, 0, 0, 0) | 1 4350 case obj.ADUFFCOPY: 4351 return OPVCC(18, 0, 0, 0) | 1 4352 case ABC: 4353 return OPVCC(16, 0, 0, 0) 4354 case ABCL: 4355 return OPVCC(16, 0, 0, 0) | 1 4356 4357 case ABEQ: 4358 return AOP_RRR(16<<26, 12, 2, 0) 4359 case ABGE: 4360 return AOP_RRR(16<<26, 4, 0, 0) 4361 case ABGT: 4362 return AOP_RRR(16<<26, 12, 1, 0) 4363 case ABLE: 4364 return AOP_RRR(16<<26, 4, 1, 0) 4365 case ABLT: 4366 return AOP_RRR(16<<26, 12, 0, 0) 4367 case ABNE: 4368 return AOP_RRR(16<<26, 4, 2, 0) 4369 case ABVC: 4370 return AOP_RRR(16<<26, 4, 3, 0) // apparently unordered-clear 4371 case ABVS: 4372 return AOP_RRR(16<<26, 12, 3, 0) // apparently unordered-set 4373 4374 case ACMP: 4375 return OPVCC(11, 0, 0, 0) | 1<<21 /* L=1 */ 4376 case ACMPU: 4377 return OPVCC(10, 0, 0, 0) | 1<<21 4378 case ACMPW: 4379 return OPVCC(11, 0, 0, 0) /* L=0 */ 4380 case ACMPWU: 4381 return OPVCC(10, 0, 0, 0) 4382 case ALSW: 4383 return OPVCC(31, 597, 0, 0) 4384 4385 case AMULLW: 4386 return OPVCC(7, 0, 0, 0) 4387 4388 case AOR: 4389 return OPVCC(24, 0, 0, 0) 4390 case -AOR: 4391 return OPVCC(25, 0, 0, 0) /* ORIS/ORIU */ 4392 4393 case ARLWMI: 4394 return OPVCC(20, 0, 0, 0) /* rlwimi */ 4395 case ARLWMICC: 4396 return OPVCC(20, 0, 0, 1) 4397 case ARLDMI: 4398 return OPVCC(30, 0, 0, 0) | 3<<2 /* rldimi */ 4399 case ARLDMICC: 4400 return OPVCC(30, 0, 0, 1) | 3<<2 4401 case ARLDIMI: 4402 return OPVCC(30, 0, 0, 0) | 3<<2 /* rldimi */ 4403 case ARLDIMICC: 4404 return OPVCC(30, 0, 0, 1) | 3<<2 4405 case ARLWNM: 4406 return OPVCC(21, 0, 0, 0) /* rlwinm */ 4407 case ARLWNMCC: 4408 return OPVCC(21, 0, 0, 1) 4409 4410 case ARLDCL: 4411 return OPVCC(30, 0, 0, 0) /* rldicl */ 4412 case ARLDCLCC: 4413 return OPVCC(30, 0, 0, 1) 4414 case ARLDCR: 4415 return OPVCC(30, 1, 0, 0) /* rldicr */ 4416 case ARLDCRCC: 4417 return OPVCC(30, 1, 0, 1) 4418 case ARLDC: 4419 return OPVCC(30, 0, 0, 0) | 2<<2 4420 case ARLDCCC: 4421 return OPVCC(30, 0, 0, 1) | 2<<2 4422 4423 case ASRAW: 4424 return OPVCC(31, 824, 0, 0) 4425 case ASRAWCC: 4426 return OPVCC(31, 824, 0, 1) 4427 case ASRAD: 4428 return OPVCC(31, (413 << 1), 0, 0) 4429 case ASRADCC: 4430 return OPVCC(31, (413 << 1), 0, 1) 4431 4432 case ASTSW: 4433 return OPVCC(31, 725, 0, 0) 4434 4435 case ASUBC: 4436 return OPVCC(8, 0, 0, 0) 4437 4438 case ATW: 4439 return OPVCC(3, 0, 0, 0) 4440 case ATD: 4441 return OPVCC(2, 0, 0, 0) 4442 4443 /* Vector (VMX/Altivec) instructions */ 4444 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */ 4445 /* are enabled starting at POWER6 (ISA 2.05). */ 4446 case AVSPLTB: 4447 return OPVX(4, 524, 0, 0) /* vspltb - v2.03 */ 4448 case AVSPLTH: 4449 return OPVX(4, 588, 0, 0) /* vsplth - v2.03 */ 4450 case AVSPLTW: 4451 return OPVX(4, 652, 0, 0) /* vspltw - v2.03 */ 4452 4453 case AVSPLTISB: 4454 return OPVX(4, 780, 0, 0) /* vspltisb - v2.03 */ 4455 case AVSPLTISH: 4456 return OPVX(4, 844, 0, 0) /* vspltish - v2.03 */ 4457 case AVSPLTISW: 4458 return OPVX(4, 908, 0, 0) /* vspltisw - v2.03 */ 4459 /* End of vector instructions */ 4460 4461 case AFTDIV: 4462 return OPVCC(63, 128, 0, 0) /* ftdiv - v2.06 */ 4463 case AFTSQRT: 4464 return OPVCC(63, 160, 0, 0) /* ftsqrt - v2.06 */ 4465 4466 case AXOR: 4467 return OPVCC(26, 0, 0, 0) /* XORIL */ 4468 case -AXOR: 4469 return OPVCC(27, 0, 0, 0) /* XORIU */ 4470 } 4471 4472 c.ctxt.Diag("bad opcode i/r or i/r/r %v", a) 4473 return 0 4474} 4475 4476/* 4477 * load o(a),d 4478 */ 4479func (c *ctxt9) opload(a obj.As) uint32 { 4480 switch a { 4481 case AMOVD: 4482 return OPVCC(58, 0, 0, 0) /* ld */ 4483 case AMOVDU: 4484 return OPVCC(58, 0, 0, 1) /* ldu */ 4485 case AMOVWZ: 4486 return OPVCC(32, 0, 0, 0) /* lwz */ 4487 case AMOVWZU: 4488 return OPVCC(33, 0, 0, 0) /* lwzu */ 4489 case AMOVW: 4490 return OPVCC(58, 0, 0, 0) | 1<<1 /* lwa */ 4491 4492 /* no AMOVWU */ 4493 case AMOVB, AMOVBZ: 4494 return OPVCC(34, 0, 0, 0) 4495 /* load */ 4496 4497 case AMOVBU, AMOVBZU: 4498 return OPVCC(35, 0, 0, 0) 4499 case AFMOVD: 4500 return OPVCC(50, 0, 0, 0) 4501 case AFMOVDU: 4502 return OPVCC(51, 0, 0, 0) 4503 case AFMOVS: 4504 return OPVCC(48, 0, 0, 0) 4505 case AFMOVSU: 4506 return OPVCC(49, 0, 0, 0) 4507 case AMOVH: 4508 return OPVCC(42, 0, 0, 0) 4509 case AMOVHU: 4510 return OPVCC(43, 0, 0, 0) 4511 case AMOVHZ: 4512 return OPVCC(40, 0, 0, 0) 4513 case AMOVHZU: 4514 return OPVCC(41, 0, 0, 0) 4515 case AMOVMW: 4516 return OPVCC(46, 0, 0, 0) /* lmw */ 4517 } 4518 4519 c.ctxt.Diag("bad load opcode %v", a) 4520 return 0 4521} 4522 4523/* 4524 * indexed load a(b),d 4525 */ 4526func (c *ctxt9) oploadx(a obj.As) uint32 { 4527 switch a { 4528 case AMOVWZ: 4529 return OPVCC(31, 23, 0, 0) /* lwzx */ 4530 case AMOVWZU: 4531 return OPVCC(31, 55, 0, 0) /* lwzux */ 4532 case AMOVW: 4533 return OPVCC(31, 341, 0, 0) /* lwax */ 4534 case AMOVWU: 4535 return OPVCC(31, 373, 0, 0) /* lwaux */ 4536 4537 case AMOVB, AMOVBZ: 4538 return OPVCC(31, 87, 0, 0) /* lbzx */ 4539 4540 case AMOVBU, AMOVBZU: 4541 return OPVCC(31, 119, 0, 0) /* lbzux */ 4542 case AFMOVD: 4543 return OPVCC(31, 599, 0, 0) /* lfdx */ 4544 case AFMOVDU: 4545 return OPVCC(31, 631, 0, 0) /* lfdux */ 4546 case AFMOVS: 4547 return OPVCC(31, 535, 0, 0) /* lfsx */ 4548 case AFMOVSU: 4549 return OPVCC(31, 567, 0, 0) /* lfsux */ 4550 case AFMOVSX: 4551 return OPVCC(31, 855, 0, 0) /* lfiwax - power6, isa 2.05 */ 4552 case AFMOVSZ: 4553 return OPVCC(31, 887, 0, 0) /* lfiwzx - power7, isa 2.06 */ 4554 case AMOVH: 4555 return OPVCC(31, 343, 0, 0) /* lhax */ 4556 case AMOVHU: 4557 return OPVCC(31, 375, 0, 0) /* lhaux */ 4558 case AMOVHBR: 4559 return OPVCC(31, 790, 0, 0) /* lhbrx */ 4560 case AMOVWBR: 4561 return OPVCC(31, 534, 0, 0) /* lwbrx */ 4562 case AMOVDBR: 4563 return OPVCC(31, 532, 0, 0) /* ldbrx */ 4564 case AMOVHZ: 4565 return OPVCC(31, 279, 0, 0) /* lhzx */ 4566 case AMOVHZU: 4567 return OPVCC(31, 311, 0, 0) /* lhzux */ 4568 case AECIWX: 4569 return OPVCC(31, 310, 0, 0) /* eciwx */ 4570 case ALBAR: 4571 return OPVCC(31, 52, 0, 0) /* lbarx */ 4572 case ALWAR: 4573 return OPVCC(31, 20, 0, 0) /* lwarx */ 4574 case ALDAR: 4575 return OPVCC(31, 84, 0, 0) 4576 case ALSW: 4577 return OPVCC(31, 533, 0, 0) /* lswx */ 4578 case AMOVD: 4579 return OPVCC(31, 21, 0, 0) /* ldx */ 4580 case AMOVDU: 4581 return OPVCC(31, 53, 0, 0) /* ldux */ 4582 4583 /* Vector (VMX/Altivec) instructions */ 4584 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */ 4585 /* are enabled starting at POWER6 (ISA 2.05). */ 4586 case ALVEBX: 4587 return OPVCC(31, 7, 0, 0) /* lvebx - v2.03 */ 4588 case ALVEHX: 4589 return OPVCC(31, 39, 0, 0) /* lvehx - v2.03 */ 4590 case ALVEWX: 4591 return OPVCC(31, 71, 0, 0) /* lvewx - v2.03 */ 4592 case ALVX: 4593 return OPVCC(31, 103, 0, 0) /* lvx - v2.03 */ 4594 case ALVXL: 4595 return OPVCC(31, 359, 0, 0) /* lvxl - v2.03 */ 4596 case ALVSL: 4597 return OPVCC(31, 6, 0, 0) /* lvsl - v2.03 */ 4598 case ALVSR: 4599 return OPVCC(31, 38, 0, 0) /* lvsr - v2.03 */ 4600 /* End of vector instructions */ 4601 4602 /* Vector scalar (VSX) instructions */ 4603 /* ISA 2.06 enables these for POWER7. */ 4604 case ALXVD2X: 4605 return OPVXX1(31, 844, 0) /* lxvd2x - v2.06 */ 4606 case ALXVDSX: 4607 return OPVXX1(31, 332, 0) /* lxvdsx - v2.06 */ 4608 case ALXVW4X: 4609 return OPVXX1(31, 780, 0) /* lxvw4x - v2.06 */ 4610 4611 case ALXSDX: 4612 return OPVXX1(31, 588, 0) /* lxsdx - v2.06 */ 4613 4614 case ALXSIWAX: 4615 return OPVXX1(31, 76, 0) /* lxsiwax - v2.07 */ 4616 case ALXSIWZX: 4617 return OPVXX1(31, 12, 0) /* lxsiwzx - v2.07 */ 4618 /* End of vector scalar instructions */ 4619 4620 } 4621 4622 c.ctxt.Diag("bad loadx opcode %v", a) 4623 return 0 4624} 4625 4626/* 4627 * store s,o(d) 4628 */ 4629func (c *ctxt9) opstore(a obj.As) uint32 { 4630 switch a { 4631 case AMOVB, AMOVBZ: 4632 return OPVCC(38, 0, 0, 0) /* stb */ 4633 4634 case AMOVBU, AMOVBZU: 4635 return OPVCC(39, 0, 0, 0) /* stbu */ 4636 case AFMOVD: 4637 return OPVCC(54, 0, 0, 0) /* stfd */ 4638 case AFMOVDU: 4639 return OPVCC(55, 0, 0, 0) /* stfdu */ 4640 case AFMOVS: 4641 return OPVCC(52, 0, 0, 0) /* stfs */ 4642 case AFMOVSU: 4643 return OPVCC(53, 0, 0, 0) /* stfsu */ 4644 4645 case AMOVHZ, AMOVH: 4646 return OPVCC(44, 0, 0, 0) /* sth */ 4647 4648 case AMOVHZU, AMOVHU: 4649 return OPVCC(45, 0, 0, 0) /* sthu */ 4650 case AMOVMW: 4651 return OPVCC(47, 0, 0, 0) /* stmw */ 4652 case ASTSW: 4653 return OPVCC(31, 725, 0, 0) /* stswi */ 4654 4655 case AMOVWZ, AMOVW: 4656 return OPVCC(36, 0, 0, 0) /* stw */ 4657 4658 case AMOVWZU, AMOVWU: 4659 return OPVCC(37, 0, 0, 0) /* stwu */ 4660 case AMOVD: 4661 return OPVCC(62, 0, 0, 0) /* std */ 4662 case AMOVDU: 4663 return OPVCC(62, 0, 0, 1) /* stdu */ 4664 } 4665 4666 c.ctxt.Diag("unknown store opcode %v", a) 4667 return 0 4668} 4669 4670/* 4671 * indexed store s,a(b) 4672 */ 4673func (c *ctxt9) opstorex(a obj.As) uint32 { 4674 switch a { 4675 case AMOVB, AMOVBZ: 4676 return OPVCC(31, 215, 0, 0) /* stbx */ 4677 4678 case AMOVBU, AMOVBZU: 4679 return OPVCC(31, 247, 0, 0) /* stbux */ 4680 case AFMOVD: 4681 return OPVCC(31, 727, 0, 0) /* stfdx */ 4682 case AFMOVDU: 4683 return OPVCC(31, 759, 0, 0) /* stfdux */ 4684 case AFMOVS: 4685 return OPVCC(31, 663, 0, 0) /* stfsx */ 4686 case AFMOVSU: 4687 return OPVCC(31, 695, 0, 0) /* stfsux */ 4688 case AFMOVSX: 4689 return OPVCC(31, 983, 0, 0) /* stfiwx */ 4690 4691 case AMOVHZ, AMOVH: 4692 return OPVCC(31, 407, 0, 0) /* sthx */ 4693 case AMOVHBR: 4694 return OPVCC(31, 918, 0, 0) /* sthbrx */ 4695 4696 case AMOVHZU, AMOVHU: 4697 return OPVCC(31, 439, 0, 0) /* sthux */ 4698 4699 case AMOVWZ, AMOVW: 4700 return OPVCC(31, 151, 0, 0) /* stwx */ 4701 4702 case AMOVWZU, AMOVWU: 4703 return OPVCC(31, 183, 0, 0) /* stwux */ 4704 case ASTSW: 4705 return OPVCC(31, 661, 0, 0) /* stswx */ 4706 case AMOVWBR: 4707 return OPVCC(31, 662, 0, 0) /* stwbrx */ 4708 case ASTBCCC: 4709 return OPVCC(31, 694, 0, 1) /* stbcx. */ 4710 case ASTWCCC: 4711 return OPVCC(31, 150, 0, 1) /* stwcx. */ 4712 case ASTDCCC: 4713 return OPVCC(31, 214, 0, 1) /* stwdx. */ 4714 case AECOWX: 4715 return OPVCC(31, 438, 0, 0) /* ecowx */ 4716 case AMOVD: 4717 return OPVCC(31, 149, 0, 0) /* stdx */ 4718 case AMOVDU: 4719 return OPVCC(31, 181, 0, 0) /* stdux */ 4720 4721 /* Vector (VMX/Altivec) instructions */ 4722 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */ 4723 /* are enabled starting at POWER6 (ISA 2.05). */ 4724 case ASTVEBX: 4725 return OPVCC(31, 135, 0, 0) /* stvebx - v2.03 */ 4726 case ASTVEHX: 4727 return OPVCC(31, 167, 0, 0) /* stvehx - v2.03 */ 4728 case ASTVEWX: 4729 return OPVCC(31, 199, 0, 0) /* stvewx - v2.03 */ 4730 case ASTVX: 4731 return OPVCC(31, 231, 0, 0) /* stvx - v2.03 */ 4732 case ASTVXL: 4733 return OPVCC(31, 487, 0, 0) /* stvxl - v2.03 */ 4734 /* End of vector instructions */ 4735 4736 /* Vector scalar (VSX) instructions */ 4737 /* ISA 2.06 enables these for POWER7. */ 4738 case ASTXVD2X: 4739 return OPVXX1(31, 972, 0) /* stxvd2x - v2.06 */ 4740 case ASTXVW4X: 4741 return OPVXX1(31, 908, 0) /* stxvw4x - v2.06 */ 4742 4743 case ASTXSDX: 4744 return OPVXX1(31, 716, 0) /* stxsdx - v2.06 */ 4745 4746 case ASTXSIWX: 4747 return OPVXX1(31, 140, 0) /* stxsiwx - v2.07 */ 4748 /* End of vector scalar instructions */ 4749 4750 } 4751 4752 c.ctxt.Diag("unknown storex opcode %v", a) 4753 return 0 4754} 4755