1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #define DEBUG_TYPE "isel"
15 #include "SDNodeDbgValue.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/ConstantFolding.h"
21 #include "llvm/Constants.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/Function.h"
25 #include "llvm/GlobalVariable.h"
26 #include "llvm/InlineAsm.h"
27 #include "llvm/Instructions.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/IntrinsicInst.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/Module.h"
32 #include "llvm/CodeGen/Analysis.h"
33 #include "llvm/CodeGen/FastISel.h"
34 #include "llvm/CodeGen/FunctionLoweringInfo.h"
35 #include "llvm/CodeGen/GCStrategy.h"
36 #include "llvm/CodeGen/GCMetadata.h"
37 #include "llvm/CodeGen/MachineFunction.h"
38 #include "llvm/CodeGen/MachineFrameInfo.h"
39 #include "llvm/CodeGen/MachineInstrBuilder.h"
40 #include "llvm/CodeGen/MachineJumpTableInfo.h"
41 #include "llvm/CodeGen/MachineModuleInfo.h"
42 #include "llvm/CodeGen/MachineRegisterInfo.h"
43 #include "llvm/CodeGen/PseudoSourceValue.h"
44 #include "llvm/CodeGen/SelectionDAG.h"
45 #include "llvm/Analysis/DebugInfo.h"
46 #include "llvm/Target/TargetRegisterInfo.h"
47 #include "llvm/Target/TargetData.h"
48 #include "llvm/Target/TargetFrameInfo.h"
49 #include "llvm/Target/TargetInstrInfo.h"
50 #include "llvm/Target/TargetIntrinsicInfo.h"
51 #include "llvm/Target/TargetLowering.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "llvm/Support/Compiler.h"
54 #include "llvm/Support/CommandLine.h"
55 #include "llvm/Support/Debug.h"
56 #include "llvm/Support/ErrorHandling.h"
57 #include "llvm/Support/MathExtras.h"
58 #include "llvm/Support/raw_ostream.h"
59 #include <algorithm>
60 using namespace llvm;
61
62 /// LimitFloatPrecision - Generate low-precision inline sequences for
63 /// some float libcalls (6, 8 or 12 bits).
64 static unsigned LimitFloatPrecision;
65
66 static cl::opt<unsigned, true>
67 LimitFPPrecision("limit-float-precision",
68 cl::desc("Generate low-precision inline sequences "
69 "for some float libcalls"),
70 cl::location(LimitFloatPrecision),
71 cl::init(0));
72
73 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
74 const SDValue *Parts, unsigned NumParts,
75 EVT PartVT, EVT ValueVT);
76
77 /// getCopyFromParts - Create a value that contains the specified legal parts
78 /// combined into the value they represent. If the parts combine to a type
79 /// larger then ValueVT then AssertOp can be used to specify whether the extra
80 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
81 /// (ISD::AssertSext).
getCopyFromParts(SelectionDAG & DAG,DebugLoc DL,const SDValue * Parts,unsigned NumParts,EVT PartVT,EVT ValueVT,ISD::NodeType AssertOp=ISD::DELETED_NODE)82 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL,
83 const SDValue *Parts,
84 unsigned NumParts, EVT PartVT, EVT ValueVT,
85 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
86 if (ValueVT.isVector())
87 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT);
88
89 assert(NumParts > 0 && "No parts to assemble!");
90 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
91 SDValue Val = Parts[0];
92
93 if (NumParts > 1) {
94 // Assemble the value from multiple parts.
95 if (ValueVT.isInteger()) {
96 unsigned PartBits = PartVT.getSizeInBits();
97 unsigned ValueBits = ValueVT.getSizeInBits();
98
99 // Assemble the power of 2 part.
100 unsigned RoundParts = NumParts & (NumParts - 1) ?
101 1 << Log2_32(NumParts) : NumParts;
102 unsigned RoundBits = PartBits * RoundParts;
103 EVT RoundVT = RoundBits == ValueBits ?
104 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
105 SDValue Lo, Hi;
106
107 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
108
109 if (RoundParts > 2) {
110 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
111 PartVT, HalfVT);
112 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
113 RoundParts / 2, PartVT, HalfVT);
114 } else {
115 Lo = DAG.getNode(ISD::BIT_CONVERT, DL, HalfVT, Parts[0]);
116 Hi = DAG.getNode(ISD::BIT_CONVERT, DL, HalfVT, Parts[1]);
117 }
118
119 if (TLI.isBigEndian())
120 std::swap(Lo, Hi);
121
122 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
123
124 if (RoundParts < NumParts) {
125 // Assemble the trailing non-power-of-2 part.
126 unsigned OddParts = NumParts - RoundParts;
127 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
128 Hi = getCopyFromParts(DAG, DL,
129 Parts + RoundParts, OddParts, PartVT, OddVT);
130
131 // Combine the round and odd parts.
132 Lo = Val;
133 if (TLI.isBigEndian())
134 std::swap(Lo, Hi);
135 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
136 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
137 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
138 DAG.getConstant(Lo.getValueType().getSizeInBits(),
139 TLI.getPointerTy()));
140 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
141 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
142 }
143 } else if (PartVT.isFloatingPoint()) {
144 // FP split into multiple FP parts (for ppcf128)
145 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) &&
146 "Unexpected split");
147 SDValue Lo, Hi;
148 Lo = DAG.getNode(ISD::BIT_CONVERT, DL, EVT(MVT::f64), Parts[0]);
149 Hi = DAG.getNode(ISD::BIT_CONVERT, DL, EVT(MVT::f64), Parts[1]);
150 if (TLI.isBigEndian())
151 std::swap(Lo, Hi);
152 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
153 } else {
154 // FP split into integer parts (soft fp)
155 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
156 !PartVT.isVector() && "Unexpected split");
157 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
158 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT);
159 }
160 }
161
162 // There is now one part, held in Val. Correct it to match ValueVT.
163 PartVT = Val.getValueType();
164
165 if (PartVT == ValueVT)
166 return Val;
167
168 if (PartVT.isInteger() && ValueVT.isInteger()) {
169 if (ValueVT.bitsLT(PartVT)) {
170 // For a truncate, see if we have any information to
171 // indicate whether the truncated bits will always be
172 // zero or sign-extension.
173 if (AssertOp != ISD::DELETED_NODE)
174 Val = DAG.getNode(AssertOp, DL, PartVT, Val,
175 DAG.getValueType(ValueVT));
176 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
177 }
178 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
179 }
180
181 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
182 // FP_ROUND's are always exact here.
183 if (ValueVT.bitsLT(Val.getValueType()))
184 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
185 DAG.getIntPtrConstant(1));
186
187 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
188 }
189
190 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
191 return DAG.getNode(ISD::BIT_CONVERT, DL, ValueVT, Val);
192
193 llvm_unreachable("Unknown mismatch!");
194 return SDValue();
195 }
196
197 /// getCopyFromParts - Create a value that contains the specified legal parts
198 /// combined into the value they represent. If the parts combine to a type
199 /// larger then ValueVT then AssertOp can be used to specify whether the extra
200 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
201 /// (ISD::AssertSext).
getCopyFromPartsVector(SelectionDAG & DAG,DebugLoc DL,const SDValue * Parts,unsigned NumParts,EVT PartVT,EVT ValueVT)202 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
203 const SDValue *Parts, unsigned NumParts,
204 EVT PartVT, EVT ValueVT) {
205 assert(ValueVT.isVector() && "Not a vector value");
206 assert(NumParts > 0 && "No parts to assemble!");
207 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
208 SDValue Val = Parts[0];
209
210 // Handle a multi-element vector.
211 if (NumParts > 1) {
212 EVT IntermediateVT, RegisterVT;
213 unsigned NumIntermediates;
214 unsigned NumRegs =
215 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
216 NumIntermediates, RegisterVT);
217 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
218 NumParts = NumRegs; // Silence a compiler warning.
219 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
220 assert(RegisterVT == Parts[0].getValueType() &&
221 "Part type doesn't match part!");
222
223 // Assemble the parts into intermediate operands.
224 SmallVector<SDValue, 8> Ops(NumIntermediates);
225 if (NumIntermediates == NumParts) {
226 // If the register was not expanded, truncate or copy the value,
227 // as appropriate.
228 for (unsigned i = 0; i != NumParts; ++i)
229 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
230 PartVT, IntermediateVT);
231 } else if (NumParts > 0) {
232 // If the intermediate type was expanded, build the intermediate
233 // operands from the parts.
234 assert(NumParts % NumIntermediates == 0 &&
235 "Must expand into a divisible number of parts!");
236 unsigned Factor = NumParts / NumIntermediates;
237 for (unsigned i = 0; i != NumIntermediates; ++i)
238 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
239 PartVT, IntermediateVT);
240 }
241
242 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
243 // intermediate operands.
244 Val = DAG.getNode(IntermediateVT.isVector() ?
245 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL,
246 ValueVT, &Ops[0], NumIntermediates);
247 }
248
249 // There is now one part, held in Val. Correct it to match ValueVT.
250 PartVT = Val.getValueType();
251
252 if (PartVT == ValueVT)
253 return Val;
254
255 if (PartVT.isVector()) {
256 // If the element type of the source/dest vectors are the same, but the
257 // parts vector has more elements than the value vector, then we have a
258 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
259 // elements we want.
260 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) {
261 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
262 "Cannot narrow, it would be a lossy transformation");
263 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
264 DAG.getIntPtrConstant(0));
265 }
266
267 // Vector/Vector bitcast.
268 return DAG.getNode(ISD::BIT_CONVERT, DL, ValueVT, Val);
269 }
270
271 assert(ValueVT.getVectorElementType() == PartVT &&
272 ValueVT.getVectorNumElements() == 1 &&
273 "Only trivial scalar-to-vector conversions should get here!");
274 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
275 }
276
277
278
279
280 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl,
281 SDValue Val, SDValue *Parts, unsigned NumParts,
282 EVT PartVT);
283
284 /// getCopyToParts - Create a series of nodes that contain the specified value
285 /// split into legal parts. If the parts contain more bits than Val, then, for
286 /// integers, ExtendKind can be used to specify how to generate the extra bits.
getCopyToParts(SelectionDAG & DAG,DebugLoc DL,SDValue Val,SDValue * Parts,unsigned NumParts,EVT PartVT,ISD::NodeType ExtendKind=ISD::ANY_EXTEND)287 static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL,
288 SDValue Val, SDValue *Parts, unsigned NumParts,
289 EVT PartVT,
290 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
291 EVT ValueVT = Val.getValueType();
292
293 // Handle the vector case separately.
294 if (ValueVT.isVector())
295 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT);
296
297 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
298 unsigned PartBits = PartVT.getSizeInBits();
299 unsigned OrigNumParts = NumParts;
300 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
301
302 if (NumParts == 0)
303 return;
304
305 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
306 if (PartVT == ValueVT) {
307 assert(NumParts == 1 && "No-op copy with multiple parts!");
308 Parts[0] = Val;
309 return;
310 }
311
312 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
313 // If the parts cover more bits than the value has, promote the value.
314 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
315 assert(NumParts == 1 && "Do not know what to promote to!");
316 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
317 } else {
318 assert(PartVT.isInteger() && ValueVT.isInteger() &&
319 "Unknown mismatch!");
320 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
321 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
322 }
323 } else if (PartBits == ValueVT.getSizeInBits()) {
324 // Different types of the same size.
325 assert(NumParts == 1 && PartVT != ValueVT);
326 Val = DAG.getNode(ISD::BIT_CONVERT, DL, PartVT, Val);
327 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
328 // If the parts cover less bits than value has, truncate the value.
329 assert(PartVT.isInteger() && ValueVT.isInteger() &&
330 "Unknown mismatch!");
331 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
332 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
333 }
334
335 // The value may have changed - recompute ValueVT.
336 ValueVT = Val.getValueType();
337 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
338 "Failed to tile the value with PartVT!");
339
340 if (NumParts == 1) {
341 assert(PartVT == ValueVT && "Type conversion failed!");
342 Parts[0] = Val;
343 return;
344 }
345
346 // Expand the value into multiple parts.
347 if (NumParts & (NumParts - 1)) {
348 // The number of parts is not a power of 2. Split off and copy the tail.
349 assert(PartVT.isInteger() && ValueVT.isInteger() &&
350 "Do not know what to expand to!");
351 unsigned RoundParts = 1 << Log2_32(NumParts);
352 unsigned RoundBits = RoundParts * PartBits;
353 unsigned OddParts = NumParts - RoundParts;
354 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
355 DAG.getIntPtrConstant(RoundBits));
356 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT);
357
358 if (TLI.isBigEndian())
359 // The odd parts were reversed by getCopyToParts - unreverse them.
360 std::reverse(Parts + RoundParts, Parts + NumParts);
361
362 NumParts = RoundParts;
363 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
364 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
365 }
366
367 // The number of parts is a power of 2. Repeatedly bisect the value using
368 // EXTRACT_ELEMENT.
369 Parts[0] = DAG.getNode(ISD::BIT_CONVERT, DL,
370 EVT::getIntegerVT(*DAG.getContext(),
371 ValueVT.getSizeInBits()),
372 Val);
373
374 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
375 for (unsigned i = 0; i < NumParts; i += StepSize) {
376 unsigned ThisBits = StepSize * PartBits / 2;
377 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
378 SDValue &Part0 = Parts[i];
379 SDValue &Part1 = Parts[i+StepSize/2];
380
381 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
382 ThisVT, Part0, DAG.getIntPtrConstant(1));
383 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
384 ThisVT, Part0, DAG.getIntPtrConstant(0));
385
386 if (ThisBits == PartBits && ThisVT != PartVT) {
387 Part0 = DAG.getNode(ISD::BIT_CONVERT, DL, PartVT, Part0);
388 Part1 = DAG.getNode(ISD::BIT_CONVERT, DL, PartVT, Part1);
389 }
390 }
391 }
392
393 if (TLI.isBigEndian())
394 std::reverse(Parts, Parts + OrigNumParts);
395 }
396
397
398 /// getCopyToPartsVector - Create a series of nodes that contain the specified
399 /// value split into legal parts.
getCopyToPartsVector(SelectionDAG & DAG,DebugLoc DL,SDValue Val,SDValue * Parts,unsigned NumParts,EVT PartVT)400 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL,
401 SDValue Val, SDValue *Parts, unsigned NumParts,
402 EVT PartVT) {
403 EVT ValueVT = Val.getValueType();
404 assert(ValueVT.isVector() && "Not a vector");
405 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
406
407 if (NumParts == 1) {
408 if (PartVT == ValueVT) {
409 // Nothing to do.
410 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
411 // Bitconvert vector->vector case.
412 Val = DAG.getNode(ISD::BIT_CONVERT, DL, PartVT, Val);
413 } else if (PartVT.isVector() &&
414 PartVT.getVectorElementType() == ValueVT.getVectorElementType()&&
415 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
416 EVT ElementVT = PartVT.getVectorElementType();
417 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
418 // undef elements.
419 SmallVector<SDValue, 16> Ops;
420 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
421 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
422 ElementVT, Val, DAG.getIntPtrConstant(i)));
423
424 for (unsigned i = ValueVT.getVectorNumElements(),
425 e = PartVT.getVectorNumElements(); i != e; ++i)
426 Ops.push_back(DAG.getUNDEF(ElementVT));
427
428 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size());
429
430 // FIXME: Use CONCAT for 2x -> 4x.
431
432 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
433 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
434 } else {
435 // Vector -> scalar conversion.
436 assert(ValueVT.getVectorElementType() == PartVT &&
437 ValueVT.getVectorNumElements() == 1 &&
438 "Only trivial vector-to-scalar conversions should get here!");
439 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
440 PartVT, Val, DAG.getIntPtrConstant(0));
441 }
442
443 Parts[0] = Val;
444 return;
445 }
446
447 // Handle a multi-element vector.
448 EVT IntermediateVT, RegisterVT;
449 unsigned NumIntermediates;
450 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
451 IntermediateVT,
452 NumIntermediates, RegisterVT);
453 unsigned NumElements = ValueVT.getVectorNumElements();
454
455 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
456 NumParts = NumRegs; // Silence a compiler warning.
457 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
458
459 // Split the vector into intermediate operands.
460 SmallVector<SDValue, 8> Ops(NumIntermediates);
461 for (unsigned i = 0; i != NumIntermediates; ++i) {
462 if (IntermediateVT.isVector())
463 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
464 IntermediateVT, Val,
465 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates)));
466 else
467 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
468 IntermediateVT, Val, DAG.getIntPtrConstant(i));
469 }
470
471 // Split the intermediate operands into legal parts.
472 if (NumParts == NumIntermediates) {
473 // If the register was not expanded, promote or copy the value,
474 // as appropriate.
475 for (unsigned i = 0; i != NumParts; ++i)
476 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT);
477 } else if (NumParts > 0) {
478 // If the intermediate type was expanded, split each the value into
479 // legal parts.
480 assert(NumParts % NumIntermediates == 0 &&
481 "Must expand into a divisible number of parts!");
482 unsigned Factor = NumParts / NumIntermediates;
483 for (unsigned i = 0; i != NumIntermediates; ++i)
484 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT);
485 }
486 }
487
488
489
490
491 namespace {
492 /// RegsForValue - This struct represents the registers (physical or virtual)
493 /// that a particular set of values is assigned, and the type information
494 /// about the value. The most common situation is to represent one value at a
495 /// time, but struct or array values are handled element-wise as multiple
496 /// values. The splitting of aggregates is performed recursively, so that we
497 /// never have aggregate-typed registers. The values at this point do not
498 /// necessarily have legal types, so each value may require one or more
499 /// registers of some legal type.
500 ///
501 struct RegsForValue {
502 /// ValueVTs - The value types of the values, which may not be legal, and
503 /// may need be promoted or synthesized from one or more registers.
504 ///
505 SmallVector<EVT, 4> ValueVTs;
506
507 /// RegVTs - The value types of the registers. This is the same size as
508 /// ValueVTs and it records, for each value, what the type of the assigned
509 /// register or registers are. (Individual values are never synthesized
510 /// from more than one type of register.)
511 ///
512 /// With virtual registers, the contents of RegVTs is redundant with TLI's
513 /// getRegisterType member function, however when with physical registers
514 /// it is necessary to have a separate record of the types.
515 ///
516 SmallVector<EVT, 4> RegVTs;
517
518 /// Regs - This list holds the registers assigned to the values.
519 /// Each legal or promoted value requires one register, and each
520 /// expanded value requires multiple registers.
521 ///
522 SmallVector<unsigned, 4> Regs;
523
RegsForValue__anoncb58423a0111::RegsForValue524 RegsForValue() {}
525
RegsForValue__anoncb58423a0111::RegsForValue526 RegsForValue(const SmallVector<unsigned, 4> ®s,
527 EVT regvt, EVT valuevt)
528 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
529
RegsForValue__anoncb58423a0111::RegsForValue530 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
531 unsigned Reg, const Type *Ty) {
532 ComputeValueVTs(tli, Ty, ValueVTs);
533
534 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
535 EVT ValueVT = ValueVTs[Value];
536 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
537 EVT RegisterVT = tli.getRegisterType(Context, ValueVT);
538 for (unsigned i = 0; i != NumRegs; ++i)
539 Regs.push_back(Reg + i);
540 RegVTs.push_back(RegisterVT);
541 Reg += NumRegs;
542 }
543 }
544
545 /// areValueTypesLegal - Return true if types of all the values are legal.
areValueTypesLegal__anoncb58423a0111::RegsForValue546 bool areValueTypesLegal(const TargetLowering &TLI) {
547 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
548 EVT RegisterVT = RegVTs[Value];
549 if (!TLI.isTypeLegal(RegisterVT))
550 return false;
551 }
552 return true;
553 }
554
555 /// append - Add the specified values to this one.
append__anoncb58423a0111::RegsForValue556 void append(const RegsForValue &RHS) {
557 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
558 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
559 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
560 }
561
562 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
563 /// this value and returns the result as a ValueVTs value. This uses
564 /// Chain/Flag as the input and updates them for the output Chain/Flag.
565 /// If the Flag pointer is NULL, no flag is used.
566 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
567 DebugLoc dl,
568 SDValue &Chain, SDValue *Flag) const;
569
570 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
571 /// specified value into the registers specified by this object. This uses
572 /// Chain/Flag as the input and updates them for the output Chain/Flag.
573 /// If the Flag pointer is NULL, no flag is used.
574 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
575 SDValue &Chain, SDValue *Flag) const;
576
577 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
578 /// operand list. This adds the code marker, matching input operand index
579 /// (if applicable), and includes the number of values added into it.
580 void AddInlineAsmOperands(unsigned Kind,
581 bool HasMatching, unsigned MatchingIdx,
582 SelectionDAG &DAG,
583 std::vector<SDValue> &Ops) const;
584 };
585 }
586
587 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
588 /// this value and returns the result as a ValueVT value. This uses
589 /// Chain/Flag as the input and updates them for the output Chain/Flag.
590 /// If the Flag pointer is NULL, no flag is used.
getCopyFromRegs(SelectionDAG & DAG,FunctionLoweringInfo & FuncInfo,DebugLoc dl,SDValue & Chain,SDValue * Flag) const591 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
592 FunctionLoweringInfo &FuncInfo,
593 DebugLoc dl,
594 SDValue &Chain, SDValue *Flag) const {
595 // A Value with type {} or [0 x %t] needs no registers.
596 if (ValueVTs.empty())
597 return SDValue();
598
599 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
600
601 // Assemble the legal parts into the final values.
602 SmallVector<SDValue, 4> Values(ValueVTs.size());
603 SmallVector<SDValue, 8> Parts;
604 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
605 // Copy the legal parts from the registers.
606 EVT ValueVT = ValueVTs[Value];
607 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
608 EVT RegisterVT = RegVTs[Value];
609
610 Parts.resize(NumRegs);
611 for (unsigned i = 0; i != NumRegs; ++i) {
612 SDValue P;
613 if (Flag == 0) {
614 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
615 } else {
616 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
617 *Flag = P.getValue(2);
618 }
619
620 Chain = P.getValue(1);
621
622 // If the source register was virtual and if we know something about it,
623 // add an assert node.
624 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
625 RegisterVT.isInteger() && !RegisterVT.isVector()) {
626 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
627 if (FuncInfo.LiveOutRegInfo.size() > SlotNo) {
628 const FunctionLoweringInfo::LiveOutInfo &LOI =
629 FuncInfo.LiveOutRegInfo[SlotNo];
630
631 unsigned RegSize = RegisterVT.getSizeInBits();
632 unsigned NumSignBits = LOI.NumSignBits;
633 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
634
635 // FIXME: We capture more information than the dag can represent. For
636 // now, just use the tightest assertzext/assertsext possible.
637 bool isSExt = true;
638 EVT FromVT(MVT::Other);
639 if (NumSignBits == RegSize)
640 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
641 else if (NumZeroBits >= RegSize-1)
642 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
643 else if (NumSignBits > RegSize-8)
644 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
645 else if (NumZeroBits >= RegSize-8)
646 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
647 else if (NumSignBits > RegSize-16)
648 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
649 else if (NumZeroBits >= RegSize-16)
650 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
651 else if (NumSignBits > RegSize-32)
652 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
653 else if (NumZeroBits >= RegSize-32)
654 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
655
656 if (FromVT != MVT::Other)
657 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
658 RegisterVT, P, DAG.getValueType(FromVT));
659 }
660 }
661
662 Parts[i] = P;
663 }
664
665 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
666 NumRegs, RegisterVT, ValueVT);
667 Part += NumRegs;
668 Parts.clear();
669 }
670
671 return DAG.getNode(ISD::MERGE_VALUES, dl,
672 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
673 &Values[0], ValueVTs.size());
674 }
675
676 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
677 /// specified value into the registers specified by this object. This uses
678 /// Chain/Flag as the input and updates them for the output Chain/Flag.
679 /// If the Flag pointer is NULL, no flag is used.
getCopyToRegs(SDValue Val,SelectionDAG & DAG,DebugLoc dl,SDValue & Chain,SDValue * Flag) const680 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
681 SDValue &Chain, SDValue *Flag) const {
682 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
683
684 // Get the list of the values's legal parts.
685 unsigned NumRegs = Regs.size();
686 SmallVector<SDValue, 8> Parts(NumRegs);
687 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
688 EVT ValueVT = ValueVTs[Value];
689 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
690 EVT RegisterVT = RegVTs[Value];
691
692 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
693 &Parts[Part], NumParts, RegisterVT);
694 Part += NumParts;
695 }
696
697 // Copy the parts into the registers.
698 SmallVector<SDValue, 8> Chains(NumRegs);
699 for (unsigned i = 0; i != NumRegs; ++i) {
700 SDValue Part;
701 if (Flag == 0) {
702 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
703 } else {
704 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
705 *Flag = Part.getValue(1);
706 }
707
708 Chains[i] = Part.getValue(0);
709 }
710
711 if (NumRegs == 1 || Flag)
712 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
713 // flagged to it. That is the CopyToReg nodes and the user are considered
714 // a single scheduling unit. If we create a TokenFactor and return it as
715 // chain, then the TokenFactor is both a predecessor (operand) of the
716 // user as well as a successor (the TF operands are flagged to the user).
717 // c1, f1 = CopyToReg
718 // c2, f2 = CopyToReg
719 // c3 = TokenFactor c1, c2
720 // ...
721 // = op c3, ..., f2
722 Chain = Chains[NumRegs-1];
723 else
724 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
725 }
726
727 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
728 /// operand list. This adds the code marker and includes the number of
729 /// values added into it.
AddInlineAsmOperands(unsigned Code,bool HasMatching,unsigned MatchingIdx,SelectionDAG & DAG,std::vector<SDValue> & Ops) const730 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
731 unsigned MatchingIdx,
732 SelectionDAG &DAG,
733 std::vector<SDValue> &Ops) const {
734 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
735
736 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
737 if (HasMatching)
738 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
739 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
740 Ops.push_back(Res);
741
742 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
743 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
744 EVT RegisterVT = RegVTs[Value];
745 for (unsigned i = 0; i != NumRegs; ++i) {
746 assert(Reg < Regs.size() && "Mismatch in # registers expected");
747 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
748 }
749 }
750 }
751
init(GCFunctionInfo * gfi,AliasAnalysis & aa)752 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
753 AA = &aa;
754 GFI = gfi;
755 TD = DAG.getTarget().getTargetData();
756 }
757
758 /// clear - Clear out the current SelectionDAG and the associated
759 /// state and prepare this SelectionDAGBuilder object to be used
760 /// for a new block. This doesn't clear out information about
761 /// additional blocks that are needed to complete switch lowering
762 /// or PHI node updating; that information is cleared out as it is
763 /// consumed.
clear()764 void SelectionDAGBuilder::clear() {
765 NodeMap.clear();
766 UnusedArgNodeMap.clear();
767 PendingLoads.clear();
768 PendingExports.clear();
769 DanglingDebugInfoMap.clear();
770 CurDebugLoc = DebugLoc();
771 HasTailCall = false;
772 }
773
774 /// getRoot - Return the current virtual root of the Selection DAG,
775 /// flushing any PendingLoad items. This must be done before emitting
776 /// a store or any other node that may need to be ordered after any
777 /// prior load instructions.
778 ///
getRoot()779 SDValue SelectionDAGBuilder::getRoot() {
780 if (PendingLoads.empty())
781 return DAG.getRoot();
782
783 if (PendingLoads.size() == 1) {
784 SDValue Root = PendingLoads[0];
785 DAG.setRoot(Root);
786 PendingLoads.clear();
787 return Root;
788 }
789
790 // Otherwise, we have to make a token factor node.
791 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
792 &PendingLoads[0], PendingLoads.size());
793 PendingLoads.clear();
794 DAG.setRoot(Root);
795 return Root;
796 }
797
798 /// getControlRoot - Similar to getRoot, but instead of flushing all the
799 /// PendingLoad items, flush all the PendingExports items. It is necessary
800 /// to do this before emitting a terminator instruction.
801 ///
getControlRoot()802 SDValue SelectionDAGBuilder::getControlRoot() {
803 SDValue Root = DAG.getRoot();
804
805 if (PendingExports.empty())
806 return Root;
807
808 // Turn all of the CopyToReg chains into one factored node.
809 if (Root.getOpcode() != ISD::EntryToken) {
810 unsigned i = 0, e = PendingExports.size();
811 for (; i != e; ++i) {
812 assert(PendingExports[i].getNode()->getNumOperands() > 1);
813 if (PendingExports[i].getNode()->getOperand(0) == Root)
814 break; // Don't add the root if we already indirectly depend on it.
815 }
816
817 if (i == e)
818 PendingExports.push_back(Root);
819 }
820
821 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
822 &PendingExports[0],
823 PendingExports.size());
824 PendingExports.clear();
825 DAG.setRoot(Root);
826 return Root;
827 }
828
AssignOrderingToNode(const SDNode * Node)829 void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) {
830 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering.
831 DAG.AssignOrdering(Node, SDNodeOrder);
832
833 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I)
834 AssignOrderingToNode(Node->getOperand(I).getNode());
835 }
836
visit(const Instruction & I)837 void SelectionDAGBuilder::visit(const Instruction &I) {
838 // Set up outgoing PHI node register values before emitting the terminator.
839 if (isa<TerminatorInst>(&I))
840 HandlePHINodesInSuccessorBlocks(I.getParent());
841
842 CurDebugLoc = I.getDebugLoc();
843
844 visit(I.getOpcode(), I);
845
846 if (!isa<TerminatorInst>(&I) && !HasTailCall)
847 CopyToExportRegsIfNeeded(&I);
848
849 CurDebugLoc = DebugLoc();
850 }
851
visitPHI(const PHINode &)852 void SelectionDAGBuilder::visitPHI(const PHINode &) {
853 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
854 }
855
visit(unsigned Opcode,const User & I)856 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
857 // Note: this doesn't use InstVisitor, because it has to work with
858 // ConstantExpr's in addition to instructions.
859 switch (Opcode) {
860 default: llvm_unreachable("Unknown instruction type encountered!");
861 // Build the switch statement using the Instruction.def file.
862 #define HANDLE_INST(NUM, OPCODE, CLASS) \
863 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break;
864 #include "llvm/Instruction.def"
865 }
866
867 // Assign the ordering to the freshly created DAG nodes.
868 if (NodeMap.count(&I)) {
869 ++SDNodeOrder;
870 AssignOrderingToNode(getValue(&I).getNode());
871 }
872 }
873
874 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
875 // generate the debug data structures now that we've seen its definition.
resolveDanglingDebugInfo(const Value * V,SDValue Val)876 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
877 SDValue Val) {
878 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
879 if (DDI.getDI()) {
880 const DbgValueInst *DI = DDI.getDI();
881 DebugLoc dl = DDI.getdl();
882 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
883 MDNode *Variable = DI->getVariable();
884 uint64_t Offset = DI->getOffset();
885 SDDbgValue *SDV;
886 if (Val.getNode()) {
887 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) {
888 SDV = DAG.getDbgValue(Variable, Val.getNode(),
889 Val.getResNo(), Offset, dl, DbgSDNodeOrder);
890 DAG.AddDbgValue(SDV, Val.getNode(), false);
891 }
892 } else {
893 SDV = DAG.getDbgValue(Variable, UndefValue::get(V->getType()),
894 Offset, dl, SDNodeOrder);
895 DAG.AddDbgValue(SDV, 0, false);
896 }
897 DanglingDebugInfoMap[V] = DanglingDebugInfo();
898 }
899 }
900
901 // getValue - Return an SDValue for the given Value.
getValue(const Value * V)902 SDValue SelectionDAGBuilder::getValue(const Value *V) {
903 // If we already have an SDValue for this value, use it. It's important
904 // to do this first, so that we don't create a CopyFromReg if we already
905 // have a regular SDValue.
906 SDValue &N = NodeMap[V];
907 if (N.getNode()) return N;
908
909 // If there's a virtual register allocated and initialized for this
910 // value, use it.
911 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
912 if (It != FuncInfo.ValueMap.end()) {
913 unsigned InReg = It->second;
914 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType());
915 SDValue Chain = DAG.getEntryNode();
916 return N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain,NULL);
917 }
918
919 // Otherwise create a new SDValue and remember it.
920 SDValue Val = getValueImpl(V);
921 NodeMap[V] = Val;
922 resolveDanglingDebugInfo(V, Val);
923 return Val;
924 }
925
926 /// getNonRegisterValue - Return an SDValue for the given Value, but
927 /// don't look in FuncInfo.ValueMap for a virtual register.
getNonRegisterValue(const Value * V)928 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
929 // If we already have an SDValue for this value, use it.
930 SDValue &N = NodeMap[V];
931 if (N.getNode()) return N;
932
933 // Otherwise create a new SDValue and remember it.
934 SDValue Val = getValueImpl(V);
935 NodeMap[V] = Val;
936 resolveDanglingDebugInfo(V, Val);
937 return Val;
938 }
939
940 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
941 /// Create an SDValue for the given value.
getValueImpl(const Value * V)942 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
943 if (const Constant *C = dyn_cast<Constant>(V)) {
944 EVT VT = TLI.getValueType(V->getType(), true);
945
946 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
947 return DAG.getConstant(*CI, VT);
948
949 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
950 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT);
951
952 if (isa<ConstantPointerNull>(C))
953 return DAG.getConstant(0, TLI.getPointerTy());
954
955 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
956 return DAG.getConstantFP(*CFP, VT);
957
958 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
959 return DAG.getUNDEF(VT);
960
961 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
962 visit(CE->getOpcode(), *CE);
963 SDValue N1 = NodeMap[V];
964 assert(N1.getNode() && "visit didn't populate the NodeMap!");
965 return N1;
966 }
967
968 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
969 SmallVector<SDValue, 4> Constants;
970 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
971 OI != OE; ++OI) {
972 SDNode *Val = getValue(*OI).getNode();
973 // If the operand is an empty aggregate, there are no values.
974 if (!Val) continue;
975 // Add each leaf value from the operand to the Constants list
976 // to form a flattened list of all the values.
977 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
978 Constants.push_back(SDValue(Val, i));
979 }
980
981 return DAG.getMergeValues(&Constants[0], Constants.size(),
982 getCurDebugLoc());
983 }
984
985 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
986 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
987 "Unknown struct or array constant!");
988
989 SmallVector<EVT, 4> ValueVTs;
990 ComputeValueVTs(TLI, C->getType(), ValueVTs);
991 unsigned NumElts = ValueVTs.size();
992 if (NumElts == 0)
993 return SDValue(); // empty struct
994 SmallVector<SDValue, 4> Constants(NumElts);
995 for (unsigned i = 0; i != NumElts; ++i) {
996 EVT EltVT = ValueVTs[i];
997 if (isa<UndefValue>(C))
998 Constants[i] = DAG.getUNDEF(EltVT);
999 else if (EltVT.isFloatingPoint())
1000 Constants[i] = DAG.getConstantFP(0, EltVT);
1001 else
1002 Constants[i] = DAG.getConstant(0, EltVT);
1003 }
1004
1005 return DAG.getMergeValues(&Constants[0], NumElts,
1006 getCurDebugLoc());
1007 }
1008
1009 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1010 return DAG.getBlockAddress(BA, VT);
1011
1012 const VectorType *VecTy = cast<VectorType>(V->getType());
1013 unsigned NumElements = VecTy->getNumElements();
1014
1015 // Now that we know the number and type of the elements, get that number of
1016 // elements into the Ops array based on what kind of constant it is.
1017 SmallVector<SDValue, 16> Ops;
1018 if (const ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
1019 for (unsigned i = 0; i != NumElements; ++i)
1020 Ops.push_back(getValue(CP->getOperand(i)));
1021 } else {
1022 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1023 EVT EltVT = TLI.getValueType(VecTy->getElementType());
1024
1025 SDValue Op;
1026 if (EltVT.isFloatingPoint())
1027 Op = DAG.getConstantFP(0, EltVT);
1028 else
1029 Op = DAG.getConstant(0, EltVT);
1030 Ops.assign(NumElements, Op);
1031 }
1032
1033 // Create a BUILD_VECTOR node.
1034 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
1035 VT, &Ops[0], Ops.size());
1036 }
1037
1038 // If this is a static alloca, generate it as the frameindex instead of
1039 // computation.
1040 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1041 DenseMap<const AllocaInst*, int>::iterator SI =
1042 FuncInfo.StaticAllocaMap.find(AI);
1043 if (SI != FuncInfo.StaticAllocaMap.end())
1044 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1045 }
1046
1047 // If this is an instruction which fast-isel has deferred, select it now.
1048 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1049 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1050 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
1051 SDValue Chain = DAG.getEntryNode();
1052 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL);
1053 }
1054
1055 llvm_unreachable("Can't get register for value!");
1056 return SDValue();
1057 }
1058
visitRet(const ReturnInst & I)1059 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1060 SDValue Chain = getControlRoot();
1061 SmallVector<ISD::OutputArg, 8> Outs;
1062 SmallVector<SDValue, 8> OutVals;
1063
1064 if (!FuncInfo.CanLowerReturn) {
1065 unsigned DemoteReg = FuncInfo.DemoteRegister;
1066 const Function *F = I.getParent()->getParent();
1067
1068 // Emit a store of the return value through the virtual register.
1069 // Leave Outs empty so that LowerReturn won't try to load return
1070 // registers the usual way.
1071 SmallVector<EVT, 1> PtrValueVTs;
1072 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
1073 PtrValueVTs);
1074
1075 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1076 SDValue RetOp = getValue(I.getOperand(0));
1077
1078 SmallVector<EVT, 4> ValueVTs;
1079 SmallVector<uint64_t, 4> Offsets;
1080 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1081 unsigned NumValues = ValueVTs.size();
1082
1083 SmallVector<SDValue, 4> Chains(NumValues);
1084 for (unsigned i = 0; i != NumValues; ++i) {
1085 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(),
1086 RetPtr.getValueType(), RetPtr,
1087 DAG.getIntPtrConstant(Offsets[i]));
1088 Chains[i] =
1089 DAG.getStore(Chain, getCurDebugLoc(),
1090 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1091 Add, NULL, Offsets[i], false, false, 0);
1092 }
1093
1094 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
1095 MVT::Other, &Chains[0], NumValues);
1096 } else if (I.getNumOperands() != 0) {
1097 SmallVector<EVT, 4> ValueVTs;
1098 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
1099 unsigned NumValues = ValueVTs.size();
1100 if (NumValues) {
1101 SDValue RetOp = getValue(I.getOperand(0));
1102 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1103 EVT VT = ValueVTs[j];
1104
1105 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1106
1107 const Function *F = I.getParent()->getParent();
1108 if (F->paramHasAttr(0, Attribute::SExt))
1109 ExtendKind = ISD::SIGN_EXTEND;
1110 else if (F->paramHasAttr(0, Attribute::ZExt))
1111 ExtendKind = ISD::ZERO_EXTEND;
1112
1113 // FIXME: C calling convention requires the return type to be promoted
1114 // to at least 32-bit. But this is not necessary for non-C calling
1115 // conventions. The frontend should mark functions whose return values
1116 // require promoting with signext or zeroext attributes.
1117 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1118 EVT MinVT = TLI.getRegisterType(*DAG.getContext(), MVT::i32);
1119 if (VT.bitsLT(MinVT))
1120 VT = MinVT;
1121 }
1122
1123 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT);
1124 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT);
1125 SmallVector<SDValue, 4> Parts(NumParts);
1126 getCopyToParts(DAG, getCurDebugLoc(),
1127 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1128 &Parts[0], NumParts, PartVT, ExtendKind);
1129
1130 // 'inreg' on function refers to return value
1131 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1132 if (F->paramHasAttr(0, Attribute::InReg))
1133 Flags.setInReg();
1134
1135 // Propagate extension type if any
1136 if (F->paramHasAttr(0, Attribute::SExt))
1137 Flags.setSExt();
1138 else if (F->paramHasAttr(0, Attribute::ZExt))
1139 Flags.setZExt();
1140
1141 for (unsigned i = 0; i < NumParts; ++i) {
1142 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1143 /*isfixed=*/true));
1144 OutVals.push_back(Parts[i]);
1145 }
1146 }
1147 }
1148 }
1149
1150 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1151 CallingConv::ID CallConv =
1152 DAG.getMachineFunction().getFunction()->getCallingConv();
1153 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg,
1154 Outs, OutVals, getCurDebugLoc(), DAG);
1155
1156 // Verify that the target's LowerReturn behaved as expected.
1157 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1158 "LowerReturn didn't return a valid chain!");
1159
1160 // Update the DAG with the new chain value resulting from return lowering.
1161 DAG.setRoot(Chain);
1162 }
1163
1164 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1165 /// created for it, emit nodes to copy the value into the virtual
1166 /// registers.
CopyToExportRegsIfNeeded(const Value * V)1167 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1168 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1169 if (VMI != FuncInfo.ValueMap.end()) {
1170 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1171 CopyValueToVirtualRegister(V, VMI->second);
1172 }
1173 }
1174
1175 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1176 /// the current basic block, add it to ValueMap now so that we'll get a
1177 /// CopyTo/FromReg.
ExportFromCurrentBlock(const Value * V)1178 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1179 // No need to export constants.
1180 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1181
1182 // Already exported?
1183 if (FuncInfo.isExportedInst(V)) return;
1184
1185 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1186 CopyValueToVirtualRegister(V, Reg);
1187 }
1188
isExportableFromCurrentBlock(const Value * V,const BasicBlock * FromBB)1189 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1190 const BasicBlock *FromBB) {
1191 // The operands of the setcc have to be in this block. We don't know
1192 // how to export them from some other block.
1193 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1194 // Can export from current BB.
1195 if (VI->getParent() == FromBB)
1196 return true;
1197
1198 // Is already exported, noop.
1199 return FuncInfo.isExportedInst(V);
1200 }
1201
1202 // If this is an argument, we can export it if the BB is the entry block or
1203 // if it is already exported.
1204 if (isa<Argument>(V)) {
1205 if (FromBB == &FromBB->getParent()->getEntryBlock())
1206 return true;
1207
1208 // Otherwise, can only export this if it is already exported.
1209 return FuncInfo.isExportedInst(V);
1210 }
1211
1212 // Otherwise, constants can always be exported.
1213 return true;
1214 }
1215
InBlock(const Value * V,const BasicBlock * BB)1216 static bool InBlock(const Value *V, const BasicBlock *BB) {
1217 if (const Instruction *I = dyn_cast<Instruction>(V))
1218 return I->getParent() == BB;
1219 return true;
1220 }
1221
1222 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1223 /// This function emits a branch and is used at the leaves of an OR or an
1224 /// AND operator tree.
1225 ///
1226 void
EmitBranchForMergedCondition(const Value * Cond,MachineBasicBlock * TBB,MachineBasicBlock * FBB,MachineBasicBlock * CurBB,MachineBasicBlock * SwitchBB)1227 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1228 MachineBasicBlock *TBB,
1229 MachineBasicBlock *FBB,
1230 MachineBasicBlock *CurBB,
1231 MachineBasicBlock *SwitchBB) {
1232 const BasicBlock *BB = CurBB->getBasicBlock();
1233
1234 // If the leaf of the tree is a comparison, merge the condition into
1235 // the caseblock.
1236 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1237 // The operands of the cmp have to be in this block. We don't know
1238 // how to export them from some other block. If this is the first block
1239 // of the sequence, no exporting is needed.
1240 if (CurBB == SwitchBB ||
1241 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1242 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1243 ISD::CondCode Condition;
1244 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1245 Condition = getICmpCondCode(IC->getPredicate());
1246 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1247 Condition = getFCmpCondCode(FC->getPredicate());
1248 } else {
1249 Condition = ISD::SETEQ; // silence warning.
1250 llvm_unreachable("Unknown compare instruction");
1251 }
1252
1253 CaseBlock CB(Condition, BOp->getOperand(0),
1254 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1255 SwitchCases.push_back(CB);
1256 return;
1257 }
1258 }
1259
1260 // Create a CaseBlock record representing this branch.
1261 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1262 NULL, TBB, FBB, CurBB);
1263 SwitchCases.push_back(CB);
1264 }
1265
1266 /// FindMergedConditions - If Cond is an expression like
FindMergedConditions(const Value * Cond,MachineBasicBlock * TBB,MachineBasicBlock * FBB,MachineBasicBlock * CurBB,MachineBasicBlock * SwitchBB,unsigned Opc)1267 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1268 MachineBasicBlock *TBB,
1269 MachineBasicBlock *FBB,
1270 MachineBasicBlock *CurBB,
1271 MachineBasicBlock *SwitchBB,
1272 unsigned Opc) {
1273 // If this node is not part of the or/and tree, emit it as a branch.
1274 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1275 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1276 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1277 BOp->getParent() != CurBB->getBasicBlock() ||
1278 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1279 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1280 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB);
1281 return;
1282 }
1283
1284 // Create TmpBB after CurBB.
1285 MachineFunction::iterator BBI = CurBB;
1286 MachineFunction &MF = DAG.getMachineFunction();
1287 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1288 CurBB->getParent()->insert(++BBI, TmpBB);
1289
1290 if (Opc == Instruction::Or) {
1291 // Codegen X | Y as:
1292 // jmp_if_X TBB
1293 // jmp TmpBB
1294 // TmpBB:
1295 // jmp_if_Y TBB
1296 // jmp FBB
1297 //
1298
1299 // Emit the LHS condition.
1300 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc);
1301
1302 // Emit the RHS condition into TmpBB.
1303 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1304 } else {
1305 assert(Opc == Instruction::And && "Unknown merge op!");
1306 // Codegen X & Y as:
1307 // jmp_if_X TmpBB
1308 // jmp FBB
1309 // TmpBB:
1310 // jmp_if_Y TBB
1311 // jmp FBB
1312 //
1313 // This requires creation of TmpBB after CurBB.
1314
1315 // Emit the LHS condition.
1316 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc);
1317
1318 // Emit the RHS condition into TmpBB.
1319 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1320 }
1321 }
1322
1323 /// If the set of cases should be emitted as a series of branches, return true.
1324 /// If we should emit this as a bunch of and/or'd together conditions, return
1325 /// false.
1326 bool
ShouldEmitAsBranches(const std::vector<CaseBlock> & Cases)1327 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1328 if (Cases.size() != 2) return true;
1329
1330 // If this is two comparisons of the same values or'd or and'd together, they
1331 // will get folded into a single comparison, so don't emit two blocks.
1332 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1333 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1334 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1335 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1336 return false;
1337 }
1338
1339 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1340 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1341 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1342 Cases[0].CC == Cases[1].CC &&
1343 isa<Constant>(Cases[0].CmpRHS) &&
1344 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1345 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1346 return false;
1347 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1348 return false;
1349 }
1350
1351 return true;
1352 }
1353
visitBr(const BranchInst & I)1354 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1355 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1356
1357 // Update machine-CFG edges.
1358 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1359
1360 // Figure out which block is immediately after the current one.
1361 MachineBasicBlock *NextBlock = 0;
1362 MachineFunction::iterator BBI = BrMBB;
1363 if (++BBI != FuncInfo.MF->end())
1364 NextBlock = BBI;
1365
1366 if (I.isUnconditional()) {
1367 // Update machine-CFG edges.
1368 BrMBB->addSuccessor(Succ0MBB);
1369
1370 // If this is not a fall-through branch, emit the branch.
1371 if (Succ0MBB != NextBlock)
1372 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1373 MVT::Other, getControlRoot(),
1374 DAG.getBasicBlock(Succ0MBB)));
1375
1376 return;
1377 }
1378
1379 // If this condition is one of the special cases we handle, do special stuff
1380 // now.
1381 const Value *CondVal = I.getCondition();
1382 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1383
1384 // If this is a series of conditions that are or'd or and'd together, emit
1385 // this as a sequence of branches instead of setcc's with and/or operations.
1386 // For example, instead of something like:
1387 // cmp A, B
1388 // C = seteq
1389 // cmp D, E
1390 // F = setle
1391 // or C, F
1392 // jnz foo
1393 // Emit:
1394 // cmp A, B
1395 // je foo
1396 // cmp D, E
1397 // jle foo
1398 //
1399 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1400 if (BOp->hasOneUse() &&
1401 (BOp->getOpcode() == Instruction::And ||
1402 BOp->getOpcode() == Instruction::Or)) {
1403 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1404 BOp->getOpcode());
1405 // If the compares in later blocks need to use values not currently
1406 // exported from this block, export them now. This block should always
1407 // be the first entry.
1408 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1409
1410 // Allow some cases to be rejected.
1411 if (ShouldEmitAsBranches(SwitchCases)) {
1412 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1413 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1414 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1415 }
1416
1417 // Emit the branch for this block.
1418 visitSwitchCase(SwitchCases[0], BrMBB);
1419 SwitchCases.erase(SwitchCases.begin());
1420 return;
1421 }
1422
1423 // Okay, we decided not to do this, remove any inserted MBB's and clear
1424 // SwitchCases.
1425 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1426 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1427
1428 SwitchCases.clear();
1429 }
1430 }
1431
1432 // Create a CaseBlock record representing this branch.
1433 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1434 NULL, Succ0MBB, Succ1MBB, BrMBB);
1435
1436 // Use visitSwitchCase to actually insert the fast branch sequence for this
1437 // cond branch.
1438 visitSwitchCase(CB, BrMBB);
1439 }
1440
1441 /// visitSwitchCase - Emits the necessary code to represent a single node in
1442 /// the binary search tree resulting from lowering a switch instruction.
visitSwitchCase(CaseBlock & CB,MachineBasicBlock * SwitchBB)1443 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1444 MachineBasicBlock *SwitchBB) {
1445 SDValue Cond;
1446 SDValue CondLHS = getValue(CB.CmpLHS);
1447 DebugLoc dl = getCurDebugLoc();
1448
1449 // Build the setcc now.
1450 if (CB.CmpMHS == NULL) {
1451 // Fold "(X == true)" to X and "(X == false)" to !X to
1452 // handle common cases produced by branch lowering.
1453 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1454 CB.CC == ISD::SETEQ)
1455 Cond = CondLHS;
1456 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1457 CB.CC == ISD::SETEQ) {
1458 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1459 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1460 } else
1461 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1462 } else {
1463 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1464
1465 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1466 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1467
1468 SDValue CmpOp = getValue(CB.CmpMHS);
1469 EVT VT = CmpOp.getValueType();
1470
1471 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1472 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1473 ISD::SETLE);
1474 } else {
1475 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1476 VT, CmpOp, DAG.getConstant(Low, VT));
1477 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1478 DAG.getConstant(High-Low, VT), ISD::SETULE);
1479 }
1480 }
1481
1482 // Update successor info
1483 SwitchBB->addSuccessor(CB.TrueBB);
1484 SwitchBB->addSuccessor(CB.FalseBB);
1485
1486 // Set NextBlock to be the MBB immediately after the current one, if any.
1487 // This is used to avoid emitting unnecessary branches to the next block.
1488 MachineBasicBlock *NextBlock = 0;
1489 MachineFunction::iterator BBI = SwitchBB;
1490 if (++BBI != FuncInfo.MF->end())
1491 NextBlock = BBI;
1492
1493 // If the lhs block is the next block, invert the condition so that we can
1494 // fall through to the lhs instead of the rhs block.
1495 if (CB.TrueBB == NextBlock) {
1496 std::swap(CB.TrueBB, CB.FalseBB);
1497 SDValue True = DAG.getConstant(1, Cond.getValueType());
1498 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1499 }
1500
1501 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1502 MVT::Other, getControlRoot(), Cond,
1503 DAG.getBasicBlock(CB.TrueBB));
1504
1505 // Insert the false branch.
1506 if (CB.FalseBB != NextBlock)
1507 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1508 DAG.getBasicBlock(CB.FalseBB));
1509
1510 DAG.setRoot(BrCond);
1511 }
1512
1513 /// visitJumpTable - Emit JumpTable node in the current MBB
visitJumpTable(JumpTable & JT)1514 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1515 // Emit the code for the jump table
1516 assert(JT.Reg != -1U && "Should lower JT Header first!");
1517 EVT PTy = TLI.getPointerTy();
1518 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1519 JT.Reg, PTy);
1520 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1521 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1522 MVT::Other, Index.getValue(1),
1523 Table, Index);
1524 DAG.setRoot(BrJumpTable);
1525 }
1526
1527 /// visitJumpTableHeader - This function emits necessary code to produce index
1528 /// in the JumpTable from switch case.
visitJumpTableHeader(JumpTable & JT,JumpTableHeader & JTH,MachineBasicBlock * SwitchBB)1529 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1530 JumpTableHeader &JTH,
1531 MachineBasicBlock *SwitchBB) {
1532 // Subtract the lowest switch case value from the value being switched on and
1533 // conditional branch to default mbb if the result is greater than the
1534 // difference between smallest and largest cases.
1535 SDValue SwitchOp = getValue(JTH.SValue);
1536 EVT VT = SwitchOp.getValueType();
1537 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1538 DAG.getConstant(JTH.First, VT));
1539
1540 // The SDNode we just created, which holds the value being switched on minus
1541 // the smallest case value, needs to be copied to a virtual register so it
1542 // can be used as an index into the jump table in a subsequent basic block.
1543 // This value may be smaller or larger than the target's pointer type, and
1544 // therefore require extension or truncating.
1545 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy());
1546
1547 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
1548 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1549 JumpTableReg, SwitchOp);
1550 JT.Reg = JumpTableReg;
1551
1552 // Emit the range check for the jump table, and branch to the default block
1553 // for the switch statement if the value being switched on exceeds the largest
1554 // case in the switch.
1555 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1556 TLI.getSetCCResultType(Sub.getValueType()), Sub,
1557 DAG.getConstant(JTH.Last-JTH.First,VT),
1558 ISD::SETUGT);
1559
1560 // Set NextBlock to be the MBB immediately after the current one, if any.
1561 // This is used to avoid emitting unnecessary branches to the next block.
1562 MachineBasicBlock *NextBlock = 0;
1563 MachineFunction::iterator BBI = SwitchBB;
1564
1565 if (++BBI != FuncInfo.MF->end())
1566 NextBlock = BBI;
1567
1568 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1569 MVT::Other, CopyTo, CMP,
1570 DAG.getBasicBlock(JT.Default));
1571
1572 if (JT.MBB != NextBlock)
1573 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1574 DAG.getBasicBlock(JT.MBB));
1575
1576 DAG.setRoot(BrCond);
1577 }
1578
1579 /// visitBitTestHeader - This function emits necessary code to produce value
1580 /// suitable for "bit tests"
visitBitTestHeader(BitTestBlock & B,MachineBasicBlock * SwitchBB)1581 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1582 MachineBasicBlock *SwitchBB) {
1583 // Subtract the minimum value
1584 SDValue SwitchOp = getValue(B.SValue);
1585 EVT VT = SwitchOp.getValueType();
1586 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1587 DAG.getConstant(B.First, VT));
1588
1589 // Check range
1590 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1591 TLI.getSetCCResultType(Sub.getValueType()),
1592 Sub, DAG.getConstant(B.Range, VT),
1593 ISD::SETUGT);
1594
1595 SDValue ShiftOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(),
1596 TLI.getPointerTy());
1597
1598 B.Reg = FuncInfo.CreateReg(TLI.getPointerTy());
1599 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1600 B.Reg, ShiftOp);
1601
1602 // Set NextBlock to be the MBB immediately after the current one, if any.
1603 // This is used to avoid emitting unnecessary branches to the next block.
1604 MachineBasicBlock *NextBlock = 0;
1605 MachineFunction::iterator BBI = SwitchBB;
1606 if (++BBI != FuncInfo.MF->end())
1607 NextBlock = BBI;
1608
1609 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1610
1611 SwitchBB->addSuccessor(B.Default);
1612 SwitchBB->addSuccessor(MBB);
1613
1614 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1615 MVT::Other, CopyTo, RangeCmp,
1616 DAG.getBasicBlock(B.Default));
1617
1618 if (MBB != NextBlock)
1619 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1620 DAG.getBasicBlock(MBB));
1621
1622 DAG.setRoot(BrRange);
1623 }
1624
1625 /// visitBitTestCase - this function produces one "bit test"
visitBitTestCase(MachineBasicBlock * NextMBB,unsigned Reg,BitTestCase & B,MachineBasicBlock * SwitchBB)1626 void SelectionDAGBuilder::visitBitTestCase(MachineBasicBlock* NextMBB,
1627 unsigned Reg,
1628 BitTestCase &B,
1629 MachineBasicBlock *SwitchBB) {
1630 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), Reg,
1631 TLI.getPointerTy());
1632 SDValue Cmp;
1633 if (CountPopulation_64(B.Mask) == 1) {
1634 // Testing for a single bit; just compare the shift count with what it
1635 // would need to be to shift a 1 bit in that position.
1636 Cmp = DAG.getSetCC(getCurDebugLoc(),
1637 TLI.getSetCCResultType(ShiftOp.getValueType()),
1638 ShiftOp,
1639 DAG.getConstant(CountTrailingZeros_64(B.Mask),
1640 TLI.getPointerTy()),
1641 ISD::SETEQ);
1642 } else {
1643 // Make desired shift
1644 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(),
1645 TLI.getPointerTy(),
1646 DAG.getConstant(1, TLI.getPointerTy()),
1647 ShiftOp);
1648
1649 // Emit bit tests and jumps
1650 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1651 TLI.getPointerTy(), SwitchVal,
1652 DAG.getConstant(B.Mask, TLI.getPointerTy()));
1653 Cmp = DAG.getSetCC(getCurDebugLoc(),
1654 TLI.getSetCCResultType(AndOp.getValueType()),
1655 AndOp, DAG.getConstant(0, TLI.getPointerTy()),
1656 ISD::SETNE);
1657 }
1658
1659 SwitchBB->addSuccessor(B.TargetBB);
1660 SwitchBB->addSuccessor(NextMBB);
1661
1662 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1663 MVT::Other, getControlRoot(),
1664 Cmp, DAG.getBasicBlock(B.TargetBB));
1665
1666 // Set NextBlock to be the MBB immediately after the current one, if any.
1667 // This is used to avoid emitting unnecessary branches to the next block.
1668 MachineBasicBlock *NextBlock = 0;
1669 MachineFunction::iterator BBI = SwitchBB;
1670 if (++BBI != FuncInfo.MF->end())
1671 NextBlock = BBI;
1672
1673 if (NextMBB != NextBlock)
1674 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1675 DAG.getBasicBlock(NextMBB));
1676
1677 DAG.setRoot(BrAnd);
1678 }
1679
visitInvoke(const InvokeInst & I)1680 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1681 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1682
1683 // Retrieve successors.
1684 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1685 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1686
1687 const Value *Callee(I.getCalledValue());
1688 if (isa<InlineAsm>(Callee))
1689 visitInlineAsm(&I);
1690 else
1691 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1692
1693 // If the value of the invoke is used outside of its defining block, make it
1694 // available as a virtual register.
1695 CopyToExportRegsIfNeeded(&I);
1696
1697 // Update successor info
1698 InvokeMBB->addSuccessor(Return);
1699 InvokeMBB->addSuccessor(LandingPad);
1700
1701 // Drop into normal successor.
1702 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1703 MVT::Other, getControlRoot(),
1704 DAG.getBasicBlock(Return)));
1705 }
1706
visitUnwind(const UnwindInst & I)1707 void SelectionDAGBuilder::visitUnwind(const UnwindInst &I) {
1708 }
1709
1710 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1711 /// small case ranges).
handleSmallSwitchRange(CaseRec & CR,CaseRecVector & WorkList,const Value * SV,MachineBasicBlock * Default,MachineBasicBlock * SwitchBB)1712 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
1713 CaseRecVector& WorkList,
1714 const Value* SV,
1715 MachineBasicBlock *Default,
1716 MachineBasicBlock *SwitchBB) {
1717 Case& BackCase = *(CR.Range.second-1);
1718
1719 // Size is the number of Cases represented by this range.
1720 size_t Size = CR.Range.second - CR.Range.first;
1721 if (Size > 3)
1722 return false;
1723
1724 // Get the MachineFunction which holds the current MBB. This is used when
1725 // inserting any additional MBBs necessary to represent the switch.
1726 MachineFunction *CurMF = FuncInfo.MF;
1727
1728 // Figure out which block is immediately after the current one.
1729 MachineBasicBlock *NextBlock = 0;
1730 MachineFunction::iterator BBI = CR.CaseBB;
1731
1732 if (++BBI != FuncInfo.MF->end())
1733 NextBlock = BBI;
1734
1735 // TODO: If any two of the cases has the same destination, and if one value
1736 // is the same as the other, but has one bit unset that the other has set,
1737 // use bit manipulation to do two compares at once. For example:
1738 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1739
1740 // Rearrange the case blocks so that the last one falls through if possible.
1741 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1742 // The last case block won't fall through into 'NextBlock' if we emit the
1743 // branches in this order. See if rearranging a case value would help.
1744 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1745 if (I->BB == NextBlock) {
1746 std::swap(*I, BackCase);
1747 break;
1748 }
1749 }
1750 }
1751
1752 // Create a CaseBlock record representing a conditional branch to
1753 // the Case's target mbb if the value being switched on SV is equal
1754 // to C.
1755 MachineBasicBlock *CurBlock = CR.CaseBB;
1756 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1757 MachineBasicBlock *FallThrough;
1758 if (I != E-1) {
1759 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1760 CurMF->insert(BBI, FallThrough);
1761
1762 // Put SV in a virtual register to make it available from the new blocks.
1763 ExportFromCurrentBlock(SV);
1764 } else {
1765 // If the last case doesn't match, go to the default block.
1766 FallThrough = Default;
1767 }
1768
1769 const Value *RHS, *LHS, *MHS;
1770 ISD::CondCode CC;
1771 if (I->High == I->Low) {
1772 // This is just small small case range :) containing exactly 1 case
1773 CC = ISD::SETEQ;
1774 LHS = SV; RHS = I->High; MHS = NULL;
1775 } else {
1776 CC = ISD::SETLE;
1777 LHS = I->Low; MHS = SV; RHS = I->High;
1778 }
1779 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock);
1780
1781 // If emitting the first comparison, just call visitSwitchCase to emit the
1782 // code into the current block. Otherwise, push the CaseBlock onto the
1783 // vector to be later processed by SDISel, and insert the node's MBB
1784 // before the next MBB.
1785 if (CurBlock == SwitchBB)
1786 visitSwitchCase(CB, SwitchBB);
1787 else
1788 SwitchCases.push_back(CB);
1789
1790 CurBlock = FallThrough;
1791 }
1792
1793 return true;
1794 }
1795
areJTsAllowed(const TargetLowering & TLI)1796 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1797 return !DisableJumpTables &&
1798 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
1799 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
1800 }
1801
ComputeRange(const APInt & First,const APInt & Last)1802 static APInt ComputeRange(const APInt &First, const APInt &Last) {
1803 APInt LastExt(Last), FirstExt(First);
1804 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
1805 LastExt.sext(BitWidth); FirstExt.sext(BitWidth);
1806 return (LastExt - FirstExt + 1ULL);
1807 }
1808
1809 /// handleJTSwitchCase - Emit jumptable for current switch case range
handleJTSwitchCase(CaseRec & CR,CaseRecVector & WorkList,const Value * SV,MachineBasicBlock * Default,MachineBasicBlock * SwitchBB)1810 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec& CR,
1811 CaseRecVector& WorkList,
1812 const Value* SV,
1813 MachineBasicBlock* Default,
1814 MachineBasicBlock *SwitchBB) {
1815 Case& FrontCase = *CR.Range.first;
1816 Case& BackCase = *(CR.Range.second-1);
1817
1818 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
1819 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
1820
1821 APInt TSize(First.getBitWidth(), 0);
1822 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1823 I!=E; ++I)
1824 TSize += I->size();
1825
1826 if (!areJTsAllowed(TLI) || TSize.ult(4))
1827 return false;
1828
1829 APInt Range = ComputeRange(First, Last);
1830 double Density = TSize.roundToDouble() / Range.roundToDouble();
1831 if (Density < 0.4)
1832 return false;
1833
1834 DEBUG(dbgs() << "Lowering jump table\n"
1835 << "First entry: " << First << ". Last entry: " << Last << '\n'
1836 << "Range: " << Range
1837 << "Size: " << TSize << ". Density: " << Density << "\n\n");
1838
1839 // Get the MachineFunction which holds the current MBB. This is used when
1840 // inserting any additional MBBs necessary to represent the switch.
1841 MachineFunction *CurMF = FuncInfo.MF;
1842
1843 // Figure out which block is immediately after the current one.
1844 MachineFunction::iterator BBI = CR.CaseBB;
1845 ++BBI;
1846
1847 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1848
1849 // Create a new basic block to hold the code for loading the address
1850 // of the jump table, and jumping to it. Update successor information;
1851 // we will either branch to the default case for the switch, or the jump
1852 // table.
1853 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1854 CurMF->insert(BBI, JumpTableBB);
1855 CR.CaseBB->addSuccessor(Default);
1856 CR.CaseBB->addSuccessor(JumpTableBB);
1857
1858 // Build a vector of destination BBs, corresponding to each target
1859 // of the jump table. If the value of the jump table slot corresponds to
1860 // a case statement, push the case's BB onto the vector, otherwise, push
1861 // the default BB.
1862 std::vector<MachineBasicBlock*> DestBBs;
1863 APInt TEI = First;
1864 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1865 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
1866 const APInt &High = cast<ConstantInt>(I->High)->getValue();
1867
1868 if (Low.sle(TEI) && TEI.sle(High)) {
1869 DestBBs.push_back(I->BB);
1870 if (TEI==High)
1871 ++I;
1872 } else {
1873 DestBBs.push_back(Default);
1874 }
1875 }
1876
1877 // Update successor info. Add one edge to each unique successor.
1878 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1879 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1880 E = DestBBs.end(); I != E; ++I) {
1881 if (!SuccsHandled[(*I)->getNumber()]) {
1882 SuccsHandled[(*I)->getNumber()] = true;
1883 JumpTableBB->addSuccessor(*I);
1884 }
1885 }
1886
1887 // Create a jump table index for this jump table.
1888 unsigned JTEncoding = TLI.getJumpTableEncoding();
1889 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
1890 ->createJumpTableIndex(DestBBs);
1891
1892 // Set the jump table information so that we can codegen it as a second
1893 // MachineBasicBlock
1894 JumpTable JT(-1U, JTI, JumpTableBB, Default);
1895 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
1896 if (CR.CaseBB == SwitchBB)
1897 visitJumpTableHeader(JT, JTH, SwitchBB);
1898
1899 JTCases.push_back(JumpTableBlock(JTH, JT));
1900
1901 return true;
1902 }
1903
1904 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1905 /// 2 subtrees.
handleBTSplitSwitchCase(CaseRec & CR,CaseRecVector & WorkList,const Value * SV,MachineBasicBlock * Default,MachineBasicBlock * SwitchBB)1906 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
1907 CaseRecVector& WorkList,
1908 const Value* SV,
1909 MachineBasicBlock *Default,
1910 MachineBasicBlock *SwitchBB) {
1911 // Get the MachineFunction which holds the current MBB. This is used when
1912 // inserting any additional MBBs necessary to represent the switch.
1913 MachineFunction *CurMF = FuncInfo.MF;
1914
1915 // Figure out which block is immediately after the current one.
1916 MachineFunction::iterator BBI = CR.CaseBB;
1917 ++BBI;
1918
1919 Case& FrontCase = *CR.Range.first;
1920 Case& BackCase = *(CR.Range.second-1);
1921 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1922
1923 // Size is the number of Cases represented by this range.
1924 unsigned Size = CR.Range.second - CR.Range.first;
1925
1926 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
1927 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
1928 double FMetric = 0;
1929 CaseItr Pivot = CR.Range.first + Size/2;
1930
1931 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1932 // (heuristically) allow us to emit JumpTable's later.
1933 APInt TSize(First.getBitWidth(), 0);
1934 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1935 I!=E; ++I)
1936 TSize += I->size();
1937
1938 APInt LSize = FrontCase.size();
1939 APInt RSize = TSize-LSize;
1940 DEBUG(dbgs() << "Selecting best pivot: \n"
1941 << "First: " << First << ", Last: " << Last <<'\n'
1942 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
1943 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1944 J!=E; ++I, ++J) {
1945 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
1946 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
1947 APInt Range = ComputeRange(LEnd, RBegin);
1948 assert((Range - 2ULL).isNonNegative() &&
1949 "Invalid case distance");
1950 double LDensity = (double)LSize.roundToDouble() /
1951 (LEnd - First + 1ULL).roundToDouble();
1952 double RDensity = (double)RSize.roundToDouble() /
1953 (Last - RBegin + 1ULL).roundToDouble();
1954 double Metric = Range.logBase2()*(LDensity+RDensity);
1955 // Should always split in some non-trivial place
1956 DEBUG(dbgs() <<"=>Step\n"
1957 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
1958 << "LDensity: " << LDensity
1959 << ", RDensity: " << RDensity << '\n'
1960 << "Metric: " << Metric << '\n');
1961 if (FMetric < Metric) {
1962 Pivot = J;
1963 FMetric = Metric;
1964 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
1965 }
1966
1967 LSize += J->size();
1968 RSize -= J->size();
1969 }
1970 if (areJTsAllowed(TLI)) {
1971 // If our case is dense we *really* should handle it earlier!
1972 assert((FMetric > 0) && "Should handle dense range earlier!");
1973 } else {
1974 Pivot = CR.Range.first + Size/2;
1975 }
1976
1977 CaseRange LHSR(CR.Range.first, Pivot);
1978 CaseRange RHSR(Pivot, CR.Range.second);
1979 Constant *C = Pivot->Low;
1980 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1981
1982 // We know that we branch to the LHS if the Value being switched on is
1983 // less than the Pivot value, C. We use this to optimize our binary
1984 // tree a bit, by recognizing that if SV is greater than or equal to the
1985 // LHS's Case Value, and that Case Value is exactly one less than the
1986 // Pivot's Value, then we can branch directly to the LHS's Target,
1987 // rather than creating a leaf node for it.
1988 if ((LHSR.second - LHSR.first) == 1 &&
1989 LHSR.first->High == CR.GE &&
1990 cast<ConstantInt>(C)->getValue() ==
1991 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
1992 TrueBB = LHSR.first->BB;
1993 } else {
1994 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1995 CurMF->insert(BBI, TrueBB);
1996 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1997
1998 // Put SV in a virtual register to make it available from the new blocks.
1999 ExportFromCurrentBlock(SV);
2000 }
2001
2002 // Similar to the optimization above, if the Value being switched on is
2003 // known to be less than the Constant CR.LT, and the current Case Value
2004 // is CR.LT - 1, then we can branch directly to the target block for
2005 // the current Case Value, rather than emitting a RHS leaf node for it.
2006 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2007 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
2008 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
2009 FalseBB = RHSR.first->BB;
2010 } else {
2011 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2012 CurMF->insert(BBI, FalseBB);
2013 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2014
2015 // Put SV in a virtual register to make it available from the new blocks.
2016 ExportFromCurrentBlock(SV);
2017 }
2018
2019 // Create a CaseBlock record representing a conditional branch to
2020 // the LHS node if the value being switched on SV is less than C.
2021 // Otherwise, branch to LHS.
2022 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
2023
2024 if (CR.CaseBB == SwitchBB)
2025 visitSwitchCase(CB, SwitchBB);
2026 else
2027 SwitchCases.push_back(CB);
2028
2029 return true;
2030 }
2031
2032 /// handleBitTestsSwitchCase - if current case range has few destination and
2033 /// range span less, than machine word bitwidth, encode case range into series
2034 /// of masks and emit bit tests with these masks.
handleBitTestsSwitchCase(CaseRec & CR,CaseRecVector & WorkList,const Value * SV,MachineBasicBlock * Default,MachineBasicBlock * SwitchBB)2035 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2036 CaseRecVector& WorkList,
2037 const Value* SV,
2038 MachineBasicBlock* Default,
2039 MachineBasicBlock *SwitchBB){
2040 EVT PTy = TLI.getPointerTy();
2041 unsigned IntPtrBits = PTy.getSizeInBits();
2042
2043 Case& FrontCase = *CR.Range.first;
2044 Case& BackCase = *(CR.Range.second-1);
2045
2046 // Get the MachineFunction which holds the current MBB. This is used when
2047 // inserting any additional MBBs necessary to represent the switch.
2048 MachineFunction *CurMF = FuncInfo.MF;
2049
2050 // If target does not have legal shift left, do not emit bit tests at all.
2051 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy()))
2052 return false;
2053
2054 size_t numCmps = 0;
2055 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2056 I!=E; ++I) {
2057 // Single case counts one, case range - two.
2058 numCmps += (I->Low == I->High ? 1 : 2);
2059 }
2060
2061 // Count unique destinations
2062 SmallSet<MachineBasicBlock*, 4> Dests;
2063 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2064 Dests.insert(I->BB);
2065 if (Dests.size() > 3)
2066 // Don't bother the code below, if there are too much unique destinations
2067 return false;
2068 }
2069 DEBUG(dbgs() << "Total number of unique destinations: "
2070 << Dests.size() << '\n'
2071 << "Total number of comparisons: " << numCmps << '\n');
2072
2073 // Compute span of values.
2074 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
2075 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
2076 APInt cmpRange = maxValue - minValue;
2077
2078 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2079 << "Low bound: " << minValue << '\n'
2080 << "High bound: " << maxValue << '\n');
2081
2082 if (cmpRange.uge(IntPtrBits) ||
2083 (!(Dests.size() == 1 && numCmps >= 3) &&
2084 !(Dests.size() == 2 && numCmps >= 5) &&
2085 !(Dests.size() >= 3 && numCmps >= 6)))
2086 return false;
2087
2088 DEBUG(dbgs() << "Emitting bit tests\n");
2089 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2090
2091 // Optimize the case where all the case values fit in a
2092 // word without having to subtract minValue. In this case,
2093 // we can optimize away the subtraction.
2094 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) {
2095 cmpRange = maxValue;
2096 } else {
2097 lowBound = minValue;
2098 }
2099
2100 CaseBitsVector CasesBits;
2101 unsigned i, count = 0;
2102
2103 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2104 MachineBasicBlock* Dest = I->BB;
2105 for (i = 0; i < count; ++i)
2106 if (Dest == CasesBits[i].BB)
2107 break;
2108
2109 if (i == count) {
2110 assert((count < 3) && "Too much destinations to test!");
2111 CasesBits.push_back(CaseBits(0, Dest, 0));
2112 count++;
2113 }
2114
2115 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2116 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2117
2118 uint64_t lo = (lowValue - lowBound).getZExtValue();
2119 uint64_t hi = (highValue - lowBound).getZExtValue();
2120
2121 for (uint64_t j = lo; j <= hi; j++) {
2122 CasesBits[i].Mask |= 1ULL << j;
2123 CasesBits[i].Bits++;
2124 }
2125
2126 }
2127 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2128
2129 BitTestInfo BTC;
2130
2131 // Figure out which block is immediately after the current one.
2132 MachineFunction::iterator BBI = CR.CaseBB;
2133 ++BBI;
2134
2135 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2136
2137 DEBUG(dbgs() << "Cases:\n");
2138 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2139 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2140 << ", Bits: " << CasesBits[i].Bits
2141 << ", BB: " << CasesBits[i].BB << '\n');
2142
2143 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2144 CurMF->insert(BBI, CaseBB);
2145 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2146 CaseBB,
2147 CasesBits[i].BB));
2148
2149 // Put SV in a virtual register to make it available from the new blocks.
2150 ExportFromCurrentBlock(SV);
2151 }
2152
2153 BitTestBlock BTB(lowBound, cmpRange, SV,
2154 -1U, (CR.CaseBB == SwitchBB),
2155 CR.CaseBB, Default, BTC);
2156
2157 if (CR.CaseBB == SwitchBB)
2158 visitBitTestHeader(BTB, SwitchBB);
2159
2160 BitTestCases.push_back(BTB);
2161
2162 return true;
2163 }
2164
2165 /// Clusterify - Transform simple list of Cases into list of CaseRange's
Clusterify(CaseVector & Cases,const SwitchInst & SI)2166 size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2167 const SwitchInst& SI) {
2168 size_t numCmps = 0;
2169
2170 // Start with "simple" cases
2171 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) {
2172 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2173 Cases.push_back(Case(SI.getSuccessorValue(i),
2174 SI.getSuccessorValue(i),
2175 SMBB));
2176 }
2177 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2178
2179 // Merge case into clusters
2180 if (Cases.size() >= 2)
2181 // Must recompute end() each iteration because it may be
2182 // invalidated by erase if we hold on to it
2183 for (CaseItr I = Cases.begin(), J = ++(Cases.begin()); J != Cases.end(); ) {
2184 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2185 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2186 MachineBasicBlock* nextBB = J->BB;
2187 MachineBasicBlock* currentBB = I->BB;
2188
2189 // If the two neighboring cases go to the same destination, merge them
2190 // into a single case.
2191 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2192 I->High = J->High;
2193 J = Cases.erase(J);
2194 } else {
2195 I = J++;
2196 }
2197 }
2198
2199 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2200 if (I->Low != I->High)
2201 // A range counts double, since it requires two compares.
2202 ++numCmps;
2203 }
2204
2205 return numCmps;
2206 }
2207
visitSwitch(const SwitchInst & SI)2208 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2209 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2210
2211 // Figure out which block is immediately after the current one.
2212 MachineBasicBlock *NextBlock = 0;
2213 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2214
2215 // If there is only the default destination, branch to it if it is not the
2216 // next basic block. Otherwise, just fall through.
2217 if (SI.getNumOperands() == 2) {
2218 // Update machine-CFG edges.
2219
2220 // If this is not a fall-through branch, emit the branch.
2221 SwitchMBB->addSuccessor(Default);
2222 if (Default != NextBlock)
2223 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
2224 MVT::Other, getControlRoot(),
2225 DAG.getBasicBlock(Default)));
2226
2227 return;
2228 }
2229
2230 // If there are any non-default case statements, create a vector of Cases
2231 // representing each one, and sort the vector so that we can efficiently
2232 // create a binary search tree from them.
2233 CaseVector Cases;
2234 size_t numCmps = Clusterify(Cases, SI);
2235 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2236 << ". Total compares: " << numCmps << '\n');
2237 numCmps = 0;
2238
2239 // Get the Value to be switched on and default basic blocks, which will be
2240 // inserted into CaseBlock records, representing basic blocks in the binary
2241 // search tree.
2242 const Value *SV = SI.getOperand(0);
2243
2244 // Push the initial CaseRec onto the worklist
2245 CaseRecVector WorkList;
2246 WorkList.push_back(CaseRec(SwitchMBB,0,0,
2247 CaseRange(Cases.begin(),Cases.end())));
2248
2249 while (!WorkList.empty()) {
2250 // Grab a record representing a case range to process off the worklist
2251 CaseRec CR = WorkList.back();
2252 WorkList.pop_back();
2253
2254 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2255 continue;
2256
2257 // If the range has few cases (two or less) emit a series of specific
2258 // tests.
2259 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2260 continue;
2261
2262 // If the switch has more than 5 blocks, and at least 40% dense, and the
2263 // target supports indirect branches, then emit a jump table rather than
2264 // lowering the switch to a binary tree of conditional branches.
2265 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2266 continue;
2267
2268 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2269 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2270 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB);
2271 }
2272 }
2273
visitIndirectBr(const IndirectBrInst & I)2274 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2275 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2276
2277 // Update machine-CFG edges with unique successors.
2278 SmallVector<BasicBlock*, 32> succs;
2279 succs.reserve(I.getNumSuccessors());
2280 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i)
2281 succs.push_back(I.getSuccessor(i));
2282 array_pod_sort(succs.begin(), succs.end());
2283 succs.erase(std::unique(succs.begin(), succs.end()), succs.end());
2284 for (unsigned i = 0, e = succs.size(); i != e; ++i)
2285 IndirectBrMBB->addSuccessor(FuncInfo.MBBMap[succs[i]]);
2286
2287 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(),
2288 MVT::Other, getControlRoot(),
2289 getValue(I.getAddress())));
2290 }
2291
visitFSub(const User & I)2292 void SelectionDAGBuilder::visitFSub(const User &I) {
2293 // -0.0 - X --> fneg
2294 const Type *Ty = I.getType();
2295 if (Ty->isVectorTy()) {
2296 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2297 const VectorType *DestTy = cast<VectorType>(I.getType());
2298 const Type *ElTy = DestTy->getElementType();
2299 unsigned VL = DestTy->getNumElements();
2300 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2301 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2302 if (CV == CNZ) {
2303 SDValue Op2 = getValue(I.getOperand(1));
2304 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2305 Op2.getValueType(), Op2));
2306 return;
2307 }
2308 }
2309 }
2310
2311 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2312 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2313 SDValue Op2 = getValue(I.getOperand(1));
2314 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2315 Op2.getValueType(), Op2));
2316 return;
2317 }
2318
2319 visitBinary(I, ISD::FSUB);
2320 }
2321
visitBinary(const User & I,unsigned OpCode)2322 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2323 SDValue Op1 = getValue(I.getOperand(0));
2324 SDValue Op2 = getValue(I.getOperand(1));
2325 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2326 Op1.getValueType(), Op1, Op2));
2327 }
2328
visitShift(const User & I,unsigned Opcode)2329 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2330 SDValue Op1 = getValue(I.getOperand(0));
2331 SDValue Op2 = getValue(I.getOperand(1));
2332 if (!I.getType()->isVectorTy() &&
2333 Op2.getValueType() != TLI.getShiftAmountTy()) {
2334 // If the operand is smaller than the shift count type, promote it.
2335 EVT PTy = TLI.getPointerTy();
2336 EVT STy = TLI.getShiftAmountTy();
2337 if (STy.bitsGT(Op2.getValueType()))
2338 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2339 TLI.getShiftAmountTy(), Op2);
2340 // If the operand is larger than the shift count type but the shift
2341 // count type has enough bits to represent any shift value, truncate
2342 // it now. This is a common case and it exposes the truncate to
2343 // optimization early.
2344 else if (STy.getSizeInBits() >=
2345 Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2346 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2347 TLI.getShiftAmountTy(), Op2);
2348 // Otherwise we'll need to temporarily settle for some other
2349 // convenient type; type legalization will make adjustments as
2350 // needed.
2351 else if (PTy.bitsLT(Op2.getValueType()))
2352 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2353 TLI.getPointerTy(), Op2);
2354 else if (PTy.bitsGT(Op2.getValueType()))
2355 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2356 TLI.getPointerTy(), Op2);
2357 }
2358
2359 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2360 Op1.getValueType(), Op1, Op2));
2361 }
2362
visitICmp(const User & I)2363 void SelectionDAGBuilder::visitICmp(const User &I) {
2364 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2365 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2366 predicate = IC->getPredicate();
2367 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2368 predicate = ICmpInst::Predicate(IC->getPredicate());
2369 SDValue Op1 = getValue(I.getOperand(0));
2370 SDValue Op2 = getValue(I.getOperand(1));
2371 ISD::CondCode Opcode = getICmpCondCode(predicate);
2372
2373 EVT DestVT = TLI.getValueType(I.getType());
2374 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode));
2375 }
2376
visitFCmp(const User & I)2377 void SelectionDAGBuilder::visitFCmp(const User &I) {
2378 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2379 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2380 predicate = FC->getPredicate();
2381 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2382 predicate = FCmpInst::Predicate(FC->getPredicate());
2383 SDValue Op1 = getValue(I.getOperand(0));
2384 SDValue Op2 = getValue(I.getOperand(1));
2385 ISD::CondCode Condition = getFCmpCondCode(predicate);
2386 EVT DestVT = TLI.getValueType(I.getType());
2387 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2388 }
2389
visitSelect(const User & I)2390 void SelectionDAGBuilder::visitSelect(const User &I) {
2391 SmallVector<EVT, 4> ValueVTs;
2392 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2393 unsigned NumValues = ValueVTs.size();
2394 if (NumValues == 0) return;
2395
2396 SmallVector<SDValue, 4> Values(NumValues);
2397 SDValue Cond = getValue(I.getOperand(0));
2398 SDValue TrueVal = getValue(I.getOperand(1));
2399 SDValue FalseVal = getValue(I.getOperand(2));
2400
2401 for (unsigned i = 0; i != NumValues; ++i)
2402 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
2403 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2404 Cond,
2405 SDValue(TrueVal.getNode(),
2406 TrueVal.getResNo() + i),
2407 SDValue(FalseVal.getNode(),
2408 FalseVal.getResNo() + i));
2409
2410 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2411 DAG.getVTList(&ValueVTs[0], NumValues),
2412 &Values[0], NumValues));
2413 }
2414
visitTrunc(const User & I)2415 void SelectionDAGBuilder::visitTrunc(const User &I) {
2416 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2417 SDValue N = getValue(I.getOperand(0));
2418 EVT DestVT = TLI.getValueType(I.getType());
2419 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2420 }
2421
visitZExt(const User & I)2422 void SelectionDAGBuilder::visitZExt(const User &I) {
2423 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2424 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2425 SDValue N = getValue(I.getOperand(0));
2426 EVT DestVT = TLI.getValueType(I.getType());
2427 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2428 }
2429
visitSExt(const User & I)2430 void SelectionDAGBuilder::visitSExt(const User &I) {
2431 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2432 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2433 SDValue N = getValue(I.getOperand(0));
2434 EVT DestVT = TLI.getValueType(I.getType());
2435 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2436 }
2437
visitFPTrunc(const User & I)2438 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2439 // FPTrunc is never a no-op cast, no need to check
2440 SDValue N = getValue(I.getOperand(0));
2441 EVT DestVT = TLI.getValueType(I.getType());
2442 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2443 DestVT, N, DAG.getIntPtrConstant(0)));
2444 }
2445
visitFPExt(const User & I)2446 void SelectionDAGBuilder::visitFPExt(const User &I){
2447 // FPTrunc is never a no-op cast, no need to check
2448 SDValue N = getValue(I.getOperand(0));
2449 EVT DestVT = TLI.getValueType(I.getType());
2450 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2451 }
2452
visitFPToUI(const User & I)2453 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2454 // FPToUI is never a no-op cast, no need to check
2455 SDValue N = getValue(I.getOperand(0));
2456 EVT DestVT = TLI.getValueType(I.getType());
2457 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2458 }
2459
visitFPToSI(const User & I)2460 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2461 // FPToSI is never a no-op cast, no need to check
2462 SDValue N = getValue(I.getOperand(0));
2463 EVT DestVT = TLI.getValueType(I.getType());
2464 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2465 }
2466
visitUIToFP(const User & I)2467 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2468 // UIToFP is never a no-op cast, no need to check
2469 SDValue N = getValue(I.getOperand(0));
2470 EVT DestVT = TLI.getValueType(I.getType());
2471 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2472 }
2473
visitSIToFP(const User & I)2474 void SelectionDAGBuilder::visitSIToFP(const User &I){
2475 // SIToFP is never a no-op cast, no need to check
2476 SDValue N = getValue(I.getOperand(0));
2477 EVT DestVT = TLI.getValueType(I.getType());
2478 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2479 }
2480
visitPtrToInt(const User & I)2481 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2482 // What to do depends on the size of the integer and the size of the pointer.
2483 // We can either truncate, zero extend, or no-op, accordingly.
2484 SDValue N = getValue(I.getOperand(0));
2485 EVT DestVT = TLI.getValueType(I.getType());
2486 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2487 }
2488
visitIntToPtr(const User & I)2489 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2490 // What to do depends on the size of the integer and the size of the pointer.
2491 // We can either truncate, zero extend, or no-op, accordingly.
2492 SDValue N = getValue(I.getOperand(0));
2493 EVT DestVT = TLI.getValueType(I.getType());
2494 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2495 }
2496
visitBitCast(const User & I)2497 void SelectionDAGBuilder::visitBitCast(const User &I) {
2498 SDValue N = getValue(I.getOperand(0));
2499 EVT DestVT = TLI.getValueType(I.getType());
2500
2501 // BitCast assures us that source and destination are the same size so this is
2502 // either a BIT_CONVERT or a no-op.
2503 if (DestVT != N.getValueType())
2504 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
2505 DestVT, N)); // convert types.
2506 else
2507 setValue(&I, N); // noop cast.
2508 }
2509
visitInsertElement(const User & I)2510 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2511 SDValue InVec = getValue(I.getOperand(0));
2512 SDValue InVal = getValue(I.getOperand(1));
2513 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2514 TLI.getPointerTy(),
2515 getValue(I.getOperand(2)));
2516 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2517 TLI.getValueType(I.getType()),
2518 InVec, InVal, InIdx));
2519 }
2520
visitExtractElement(const User & I)2521 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2522 SDValue InVec = getValue(I.getOperand(0));
2523 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2524 TLI.getPointerTy(),
2525 getValue(I.getOperand(1)));
2526 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2527 TLI.getValueType(I.getType()), InVec, InIdx));
2528 }
2529
2530 // Utility for visitShuffleVector - Returns true if the mask is mask starting
2531 // from SIndx and increasing to the element length (undefs are allowed).
SequentialMask(SmallVectorImpl<int> & Mask,unsigned SIndx)2532 static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) {
2533 unsigned MaskNumElts = Mask.size();
2534 for (unsigned i = 0; i != MaskNumElts; ++i)
2535 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx)))
2536 return false;
2537 return true;
2538 }
2539
visitShuffleVector(const User & I)2540 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2541 SmallVector<int, 8> Mask;
2542 SDValue Src1 = getValue(I.getOperand(0));
2543 SDValue Src2 = getValue(I.getOperand(1));
2544
2545 // Convert the ConstantVector mask operand into an array of ints, with -1
2546 // representing undef values.
2547 SmallVector<Constant*, 8> MaskElts;
2548 cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts);
2549 unsigned MaskNumElts = MaskElts.size();
2550 for (unsigned i = 0; i != MaskNumElts; ++i) {
2551 if (isa<UndefValue>(MaskElts[i]))
2552 Mask.push_back(-1);
2553 else
2554 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue());
2555 }
2556
2557 EVT VT = TLI.getValueType(I.getType());
2558 EVT SrcVT = Src1.getValueType();
2559 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2560
2561 if (SrcNumElts == MaskNumElts) {
2562 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2563 &Mask[0]));
2564 return;
2565 }
2566
2567 // Normalize the shuffle vector since mask and vector length don't match.
2568 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2569 // Mask is longer than the source vectors and is a multiple of the source
2570 // vectors. We can use concatenate vector to make the mask and vectors
2571 // lengths match.
2572 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) {
2573 // The shuffle is concatenating two vectors together.
2574 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2575 VT, Src1, Src2));
2576 return;
2577 }
2578
2579 // Pad both vectors with undefs to make them the same length as the mask.
2580 unsigned NumConcat = MaskNumElts / SrcNumElts;
2581 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2582 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2583 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2584
2585 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2586 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2587 MOps1[0] = Src1;
2588 MOps2[0] = Src2;
2589
2590 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2591 getCurDebugLoc(), VT,
2592 &MOps1[0], NumConcat);
2593 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2594 getCurDebugLoc(), VT,
2595 &MOps2[0], NumConcat);
2596
2597 // Readjust mask for new input vector length.
2598 SmallVector<int, 8> MappedOps;
2599 for (unsigned i = 0; i != MaskNumElts; ++i) {
2600 int Idx = Mask[i];
2601 if (Idx < (int)SrcNumElts)
2602 MappedOps.push_back(Idx);
2603 else
2604 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts);
2605 }
2606
2607 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2608 &MappedOps[0]));
2609 return;
2610 }
2611
2612 if (SrcNumElts > MaskNumElts) {
2613 // Analyze the access pattern of the vector to see if we can extract
2614 // two subvectors and do the shuffle. The analysis is done by calculating
2615 // the range of elements the mask access on both vectors.
2616 int MinRange[2] = { static_cast<int>(SrcNumElts+1),
2617 static_cast<int>(SrcNumElts+1)};
2618 int MaxRange[2] = {-1, -1};
2619
2620 for (unsigned i = 0; i != MaskNumElts; ++i) {
2621 int Idx = Mask[i];
2622 int Input = 0;
2623 if (Idx < 0)
2624 continue;
2625
2626 if (Idx >= (int)SrcNumElts) {
2627 Input = 1;
2628 Idx -= SrcNumElts;
2629 }
2630 if (Idx > MaxRange[Input])
2631 MaxRange[Input] = Idx;
2632 if (Idx < MinRange[Input])
2633 MinRange[Input] = Idx;
2634 }
2635
2636 // Check if the access is smaller than the vector size and can we find
2637 // a reasonable extract index.
2638 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not
2639 // Extract.
2640 int StartIdx[2]; // StartIdx to extract from
2641 for (int Input=0; Input < 2; ++Input) {
2642 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) {
2643 RangeUse[Input] = 0; // Unused
2644 StartIdx[Input] = 0;
2645 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) {
2646 // Fits within range but we should see if we can find a good
2647 // start index that is a multiple of the mask length.
2648 if (MaxRange[Input] < (int)MaskNumElts) {
2649 RangeUse[Input] = 1; // Extract from beginning of the vector
2650 StartIdx[Input] = 0;
2651 } else {
2652 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2653 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2654 StartIdx[Input] + MaskNumElts < SrcNumElts)
2655 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2656 }
2657 }
2658 }
2659
2660 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2661 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2662 return;
2663 }
2664 else if (RangeUse[0] < 2 && RangeUse[1] < 2) {
2665 // Extract appropriate subvector and generate a vector shuffle
2666 for (int Input=0; Input < 2; ++Input) {
2667 SDValue &Src = Input == 0 ? Src1 : Src2;
2668 if (RangeUse[Input] == 0)
2669 Src = DAG.getUNDEF(VT);
2670 else
2671 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
2672 Src, DAG.getIntPtrConstant(StartIdx[Input]));
2673 }
2674
2675 // Calculate new mask.
2676 SmallVector<int, 8> MappedOps;
2677 for (unsigned i = 0; i != MaskNumElts; ++i) {
2678 int Idx = Mask[i];
2679 if (Idx < 0)
2680 MappedOps.push_back(Idx);
2681 else if (Idx < (int)SrcNumElts)
2682 MappedOps.push_back(Idx - StartIdx[0]);
2683 else
2684 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts);
2685 }
2686
2687 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2688 &MappedOps[0]));
2689 return;
2690 }
2691 }
2692
2693 // We can't use either concat vectors or extract subvectors so fall back to
2694 // replacing the shuffle with extract and build vector.
2695 // to insert and build vector.
2696 EVT EltVT = VT.getVectorElementType();
2697 EVT PtrVT = TLI.getPointerTy();
2698 SmallVector<SDValue,8> Ops;
2699 for (unsigned i = 0; i != MaskNumElts; ++i) {
2700 if (Mask[i] < 0) {
2701 Ops.push_back(DAG.getUNDEF(EltVT));
2702 } else {
2703 int Idx = Mask[i];
2704 SDValue Res;
2705
2706 if (Idx < (int)SrcNumElts)
2707 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2708 EltVT, Src1, DAG.getConstant(Idx, PtrVT));
2709 else
2710 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2711 EltVT, Src2,
2712 DAG.getConstant(Idx - SrcNumElts, PtrVT));
2713
2714 Ops.push_back(Res);
2715 }
2716 }
2717
2718 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2719 VT, &Ops[0], Ops.size()));
2720 }
2721
visitInsertValue(const InsertValueInst & I)2722 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2723 const Value *Op0 = I.getOperand(0);
2724 const Value *Op1 = I.getOperand(1);
2725 const Type *AggTy = I.getType();
2726 const Type *ValTy = Op1->getType();
2727 bool IntoUndef = isa<UndefValue>(Op0);
2728 bool FromUndef = isa<UndefValue>(Op1);
2729
2730 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2731 I.idx_begin(), I.idx_end());
2732
2733 SmallVector<EVT, 4> AggValueVTs;
2734 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2735 SmallVector<EVT, 4> ValValueVTs;
2736 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2737
2738 unsigned NumAggValues = AggValueVTs.size();
2739 unsigned NumValValues = ValValueVTs.size();
2740 SmallVector<SDValue, 4> Values(NumAggValues);
2741
2742 SDValue Agg = getValue(Op0);
2743 SDValue Val = getValue(Op1);
2744 unsigned i = 0;
2745 // Copy the beginning value(s) from the original aggregate.
2746 for (; i != LinearIndex; ++i)
2747 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2748 SDValue(Agg.getNode(), Agg.getResNo() + i);
2749 // Copy values from the inserted value(s).
2750 for (; i != LinearIndex + NumValValues; ++i)
2751 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2752 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2753 // Copy remaining value(s) from the original aggregate.
2754 for (; i != NumAggValues; ++i)
2755 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2756 SDValue(Agg.getNode(), Agg.getResNo() + i);
2757
2758 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2759 DAG.getVTList(&AggValueVTs[0], NumAggValues),
2760 &Values[0], NumAggValues));
2761 }
2762
visitExtractValue(const ExtractValueInst & I)2763 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2764 const Value *Op0 = I.getOperand(0);
2765 const Type *AggTy = Op0->getType();
2766 const Type *ValTy = I.getType();
2767 bool OutOfUndef = isa<UndefValue>(Op0);
2768
2769 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2770 I.idx_begin(), I.idx_end());
2771
2772 SmallVector<EVT, 4> ValValueVTs;
2773 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2774
2775 unsigned NumValValues = ValValueVTs.size();
2776 SmallVector<SDValue, 4> Values(NumValValues);
2777
2778 SDValue Agg = getValue(Op0);
2779 // Copy out the selected value(s).
2780 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2781 Values[i - LinearIndex] =
2782 OutOfUndef ?
2783 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2784 SDValue(Agg.getNode(), Agg.getResNo() + i);
2785
2786 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2787 DAG.getVTList(&ValValueVTs[0], NumValValues),
2788 &Values[0], NumValValues));
2789 }
2790
visitGetElementPtr(const User & I)2791 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2792 SDValue N = getValue(I.getOperand(0));
2793 const Type *Ty = I.getOperand(0)->getType();
2794
2795 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2796 OI != E; ++OI) {
2797 const Value *Idx = *OI;
2798 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2799 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2800 if (Field) {
2801 // N = N + Offset
2802 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2803 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2804 DAG.getIntPtrConstant(Offset));
2805 }
2806
2807 Ty = StTy->getElementType(Field);
2808 } else {
2809 Ty = cast<SequentialType>(Ty)->getElementType();
2810
2811 // If this is a constant subscript, handle it quickly.
2812 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2813 if (CI->isZero()) continue;
2814 uint64_t Offs =
2815 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2816 SDValue OffsVal;
2817 EVT PTy = TLI.getPointerTy();
2818 unsigned PtrBits = PTy.getSizeInBits();
2819 if (PtrBits < 64)
2820 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2821 TLI.getPointerTy(),
2822 DAG.getConstant(Offs, MVT::i64));
2823 else
2824 OffsVal = DAG.getIntPtrConstant(Offs);
2825
2826 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2827 OffsVal);
2828 continue;
2829 }
2830
2831 // N = N + Idx * ElementSize;
2832 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(),
2833 TD->getTypeAllocSize(Ty));
2834 SDValue IdxN = getValue(Idx);
2835
2836 // If the index is smaller or larger than intptr_t, truncate or extend
2837 // it.
2838 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType());
2839
2840 // If this is a multiply by a power of two, turn it into a shl
2841 // immediately. This is a very common case.
2842 if (ElementSize != 1) {
2843 if (ElementSize.isPowerOf2()) {
2844 unsigned Amt = ElementSize.logBase2();
2845 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
2846 N.getValueType(), IdxN,
2847 DAG.getConstant(Amt, TLI.getPointerTy()));
2848 } else {
2849 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy());
2850 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
2851 N.getValueType(), IdxN, Scale);
2852 }
2853 }
2854
2855 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2856 N.getValueType(), N, IdxN);
2857 }
2858 }
2859
2860 setValue(&I, N);
2861 }
2862
visitAlloca(const AllocaInst & I)2863 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
2864 // If this is a fixed sized alloca in the entry block of the function,
2865 // allocate it statically on the stack.
2866 if (FuncInfo.StaticAllocaMap.count(&I))
2867 return; // getValue will auto-populate this.
2868
2869 const Type *Ty = I.getAllocatedType();
2870 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
2871 unsigned Align =
2872 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2873 I.getAlignment());
2874
2875 SDValue AllocSize = getValue(I.getArraySize());
2876
2877 EVT IntPtr = TLI.getPointerTy();
2878 if (AllocSize.getValueType() != IntPtr)
2879 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr);
2880
2881 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr,
2882 AllocSize,
2883 DAG.getConstant(TySize, IntPtr));
2884
2885 // Handle alignment. If the requested alignment is less than or equal to
2886 // the stack alignment, ignore it. If the size is greater than or equal to
2887 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2888 unsigned StackAlign = TM.getFrameInfo()->getStackAlignment();
2889 if (Align <= StackAlign)
2890 Align = 0;
2891
2892 // Round the size of the allocation up to the stack alignment size
2893 // by add SA-1 to the size.
2894 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2895 AllocSize.getValueType(), AllocSize,
2896 DAG.getIntPtrConstant(StackAlign-1));
2897
2898 // Mask out the low bits for alignment purposes.
2899 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
2900 AllocSize.getValueType(), AllocSize,
2901 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2902
2903 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2904 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
2905 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
2906 VTs, Ops, 3);
2907 setValue(&I, DSA);
2908 DAG.setRoot(DSA.getValue(1));
2909
2910 // Inform the Frame Information that we have just allocated a variable-sized
2911 // object.
2912 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1);
2913 }
2914
visitLoad(const LoadInst & I)2915 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
2916 const Value *SV = I.getOperand(0);
2917 SDValue Ptr = getValue(SV);
2918
2919 const Type *Ty = I.getType();
2920
2921 bool isVolatile = I.isVolatile();
2922 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
2923 unsigned Alignment = I.getAlignment();
2924
2925 SmallVector<EVT, 4> ValueVTs;
2926 SmallVector<uint64_t, 4> Offsets;
2927 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2928 unsigned NumValues = ValueVTs.size();
2929 if (NumValues == 0)
2930 return;
2931
2932 SDValue Root;
2933 bool ConstantMemory = false;
2934 if (I.isVolatile())
2935 // Serialize volatile loads with other side effects.
2936 Root = getRoot();
2937 else if (AA->pointsToConstantMemory(SV)) {
2938 // Do not serialize (non-volatile) loads of constant memory with anything.
2939 Root = DAG.getEntryNode();
2940 ConstantMemory = true;
2941 } else {
2942 // Do not serialize non-volatile loads against each other.
2943 Root = DAG.getRoot();
2944 }
2945
2946 SmallVector<SDValue, 4> Values(NumValues);
2947 SmallVector<SDValue, 4> Chains(NumValues);
2948 EVT PtrVT = Ptr.getValueType();
2949 for (unsigned i = 0; i != NumValues; ++i) {
2950 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2951 PtrVT, Ptr,
2952 DAG.getConstant(Offsets[i], PtrVT));
2953 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
2954 A, SV, Offsets[i], isVolatile,
2955 isNonTemporal, Alignment);
2956
2957 Values[i] = L;
2958 Chains[i] = L.getValue(1);
2959 }
2960
2961 if (!ConstantMemory) {
2962 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2963 MVT::Other, &Chains[0], NumValues);
2964 if (isVolatile)
2965 DAG.setRoot(Chain);
2966 else
2967 PendingLoads.push_back(Chain);
2968 }
2969
2970 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2971 DAG.getVTList(&ValueVTs[0], NumValues),
2972 &Values[0], NumValues));
2973 }
2974
visitStore(const StoreInst & I)2975 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
2976 const Value *SrcV = I.getOperand(0);
2977 const Value *PtrV = I.getOperand(1);
2978
2979 SmallVector<EVT, 4> ValueVTs;
2980 SmallVector<uint64_t, 4> Offsets;
2981 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
2982 unsigned NumValues = ValueVTs.size();
2983 if (NumValues == 0)
2984 return;
2985
2986 // Get the lowered operands. Note that we do this after
2987 // checking if NumResults is zero, because with zero results
2988 // the operands won't have values in the map.
2989 SDValue Src = getValue(SrcV);
2990 SDValue Ptr = getValue(PtrV);
2991
2992 SDValue Root = getRoot();
2993 SmallVector<SDValue, 4> Chains(NumValues);
2994 EVT PtrVT = Ptr.getValueType();
2995 bool isVolatile = I.isVolatile();
2996 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
2997 unsigned Alignment = I.getAlignment();
2998
2999 for (unsigned i = 0; i != NumValues; ++i) {
3000 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr,
3001 DAG.getConstant(Offsets[i], PtrVT));
3002 Chains[i] = DAG.getStore(Root, getCurDebugLoc(),
3003 SDValue(Src.getNode(), Src.getResNo() + i),
3004 Add, PtrV, Offsets[i], isVolatile,
3005 isNonTemporal, Alignment);
3006 }
3007
3008 DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3009 MVT::Other, &Chains[0], NumValues));
3010 }
3011
3012 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3013 /// node.
visitTargetIntrinsic(const CallInst & I,unsigned Intrinsic)3014 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3015 unsigned Intrinsic) {
3016 bool HasChain = !I.doesNotAccessMemory();
3017 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3018
3019 // Build the operand list.
3020 SmallVector<SDValue, 8> Ops;
3021 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3022 if (OnlyLoad) {
3023 // We don't need to serialize loads against other loads.
3024 Ops.push_back(DAG.getRoot());
3025 } else {
3026 Ops.push_back(getRoot());
3027 }
3028 }
3029
3030 // Info is set by getTgtMemInstrinsic
3031 TargetLowering::IntrinsicInfo Info;
3032 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3033
3034 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3035 if (!IsTgtIntrinsic)
3036 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
3037
3038 // Add all operands of the call to the operand list.
3039 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3040 SDValue Op = getValue(I.getArgOperand(i));
3041 assert(TLI.isTypeLegal(Op.getValueType()) &&
3042 "Intrinsic uses a non-legal type?");
3043 Ops.push_back(Op);
3044 }
3045
3046 SmallVector<EVT, 4> ValueVTs;
3047 ComputeValueVTs(TLI, I.getType(), ValueVTs);
3048 #ifndef NDEBUG
3049 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) {
3050 assert(TLI.isTypeLegal(ValueVTs[Val]) &&
3051 "Intrinsic uses a non-legal type?");
3052 }
3053 #endif // NDEBUG
3054
3055 if (HasChain)
3056 ValueVTs.push_back(MVT::Other);
3057
3058 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
3059
3060 // Create the node.
3061 SDValue Result;
3062 if (IsTgtIntrinsic) {
3063 // This is target intrinsic that touches memory
3064 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
3065 VTs, &Ops[0], Ops.size(),
3066 Info.memVT, Info.ptrVal, Info.offset,
3067 Info.align, Info.vol,
3068 Info.readMem, Info.writeMem);
3069 } else if (!HasChain) {
3070 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
3071 VTs, &Ops[0], Ops.size());
3072 } else if (!I.getType()->isVoidTy()) {
3073 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
3074 VTs, &Ops[0], Ops.size());
3075 } else {
3076 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
3077 VTs, &Ops[0], Ops.size());
3078 }
3079
3080 if (HasChain) {
3081 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3082 if (OnlyLoad)
3083 PendingLoads.push_back(Chain);
3084 else
3085 DAG.setRoot(Chain);
3086 }
3087
3088 if (!I.getType()->isVoidTy()) {
3089 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3090 EVT VT = TLI.getValueType(PTy);
3091 Result = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), VT, Result);
3092 }
3093
3094 setValue(&I, Result);
3095 }
3096 }
3097
3098 /// GetSignificand - Get the significand and build it into a floating-point
3099 /// number with exponent of 1:
3100 ///
3101 /// Op = (Op & 0x007fffff) | 0x3f800000;
3102 ///
3103 /// where Op is the hexidecimal representation of floating point value.
3104 static SDValue
GetSignificand(SelectionDAG & DAG,SDValue Op,DebugLoc dl)3105 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
3106 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3107 DAG.getConstant(0x007fffff, MVT::i32));
3108 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3109 DAG.getConstant(0x3f800000, MVT::i32));
3110 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2);
3111 }
3112
3113 /// GetExponent - Get the exponent:
3114 ///
3115 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3116 ///
3117 /// where Op is the hexidecimal representation of floating point value.
3118 static SDValue
GetExponent(SelectionDAG & DAG,SDValue Op,const TargetLowering & TLI,DebugLoc dl)3119 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3120 DebugLoc dl) {
3121 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3122 DAG.getConstant(0x7f800000, MVT::i32));
3123 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3124 DAG.getConstant(23, TLI.getPointerTy()));
3125 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3126 DAG.getConstant(127, MVT::i32));
3127 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3128 }
3129
3130 /// getF32Constant - Get 32-bit floating point constant.
3131 static SDValue
getF32Constant(SelectionDAG & DAG,unsigned Flt)3132 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3133 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
3134 }
3135
3136 /// Inlined utility function to implement binary input atomic intrinsics for
3137 /// visitIntrinsicCall: I is a call instruction
3138 /// Op is the associated NodeType for I
3139 const char *
implVisitBinaryAtomic(const CallInst & I,ISD::NodeType Op)3140 SelectionDAGBuilder::implVisitBinaryAtomic(const CallInst& I,
3141 ISD::NodeType Op) {
3142 SDValue Root = getRoot();
3143 SDValue L =
3144 DAG.getAtomic(Op, getCurDebugLoc(),
3145 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(),
3146 Root,
3147 getValue(I.getArgOperand(0)),
3148 getValue(I.getArgOperand(1)),
3149 I.getArgOperand(0));
3150 setValue(&I, L);
3151 DAG.setRoot(L.getValue(1));
3152 return 0;
3153 }
3154
3155 // implVisitAluOverflow - Lower arithmetic overflow intrinsics.
3156 const char *
implVisitAluOverflow(const CallInst & I,ISD::NodeType Op)3157 SelectionDAGBuilder::implVisitAluOverflow(const CallInst &I, ISD::NodeType Op) {
3158 SDValue Op1 = getValue(I.getArgOperand(0));
3159 SDValue Op2 = getValue(I.getArgOperand(1));
3160
3161 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
3162 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2));
3163 return 0;
3164 }
3165
3166 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
3167 /// limited-precision mode.
3168 void
visitExp(const CallInst & I)3169 SelectionDAGBuilder::visitExp(const CallInst &I) {
3170 SDValue result;
3171 DebugLoc dl = getCurDebugLoc();
3172
3173 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3174 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3175 SDValue Op = getValue(I.getArgOperand(0));
3176
3177 // Put the exponent in the right bit position for later addition to the
3178 // final result:
3179 //
3180 // #define LOG2OFe 1.4426950f
3181 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3182 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3183 getF32Constant(DAG, 0x3fb8aa3b));
3184 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3185
3186 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3187 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3188 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3189
3190 // IntegerPartOfX <<= 23;
3191 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3192 DAG.getConstant(23, TLI.getPointerTy()));
3193
3194 if (LimitFloatPrecision <= 6) {
3195 // For floating-point precision of 6:
3196 //
3197 // TwoToFractionalPartOfX =
3198 // 0.997535578f +
3199 // (0.735607626f + 0.252464424f * x) * x;
3200 //
3201 // error 0.0144103317, which is 6 bits
3202 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3203 getF32Constant(DAG, 0x3e814304));
3204 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3205 getF32Constant(DAG, 0x3f3c50c8));
3206 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3207 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3208 getF32Constant(DAG, 0x3f7f5e7e));
3209 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5);
3210
3211 // Add the exponent into the result in integer domain.
3212 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3213 TwoToFracPartOfX, IntegerPartOfX);
3214
3215 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6);
3216 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3217 // For floating-point precision of 12:
3218 //
3219 // TwoToFractionalPartOfX =
3220 // 0.999892986f +
3221 // (0.696457318f +
3222 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3223 //
3224 // 0.000107046256 error, which is 13 to 14 bits
3225 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3226 getF32Constant(DAG, 0x3da235e3));
3227 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3228 getF32Constant(DAG, 0x3e65b8f3));
3229 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3230 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3231 getF32Constant(DAG, 0x3f324b07));
3232 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3233 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3234 getF32Constant(DAG, 0x3f7ff8fd));
3235 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7);
3236
3237 // Add the exponent into the result in integer domain.
3238 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3239 TwoToFracPartOfX, IntegerPartOfX);
3240
3241 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8);
3242 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3243 // For floating-point precision of 18:
3244 //
3245 // TwoToFractionalPartOfX =
3246 // 0.999999982f +
3247 // (0.693148872f +
3248 // (0.240227044f +
3249 // (0.554906021e-1f +
3250 // (0.961591928e-2f +
3251 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3252 //
3253 // error 2.47208000*10^(-7), which is better than 18 bits
3254 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3255 getF32Constant(DAG, 0x3924b03e));
3256 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3257 getF32Constant(DAG, 0x3ab24b87));
3258 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3259 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3260 getF32Constant(DAG, 0x3c1d8c17));
3261 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3262 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3263 getF32Constant(DAG, 0x3d634a1d));
3264 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3265 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3266 getF32Constant(DAG, 0x3e75fe14));
3267 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3268 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3269 getF32Constant(DAG, 0x3f317234));
3270 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3271 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3272 getF32Constant(DAG, 0x3f800000));
3273 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,
3274 MVT::i32, t13);
3275
3276 // Add the exponent into the result in integer domain.
3277 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3278 TwoToFracPartOfX, IntegerPartOfX);
3279
3280 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14);
3281 }
3282 } else {
3283 // No special expansion.
3284 result = DAG.getNode(ISD::FEXP, dl,
3285 getValue(I.getArgOperand(0)).getValueType(),
3286 getValue(I.getArgOperand(0)));
3287 }
3288
3289 setValue(&I, result);
3290 }
3291
3292 /// visitLog - Lower a log intrinsic. Handles the special sequences for
3293 /// limited-precision mode.
3294 void
visitLog(const CallInst & I)3295 SelectionDAGBuilder::visitLog(const CallInst &I) {
3296 SDValue result;
3297 DebugLoc dl = getCurDebugLoc();
3298
3299 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3300 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3301 SDValue Op = getValue(I.getArgOperand(0));
3302 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3303
3304 // Scale the exponent by log(2) [0.69314718f].
3305 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3306 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3307 getF32Constant(DAG, 0x3f317218));
3308
3309 // Get the significand and build it into a floating-point number with
3310 // exponent of 1.
3311 SDValue X = GetSignificand(DAG, Op1, dl);
3312
3313 if (LimitFloatPrecision <= 6) {
3314 // For floating-point precision of 6:
3315 //
3316 // LogofMantissa =
3317 // -1.1609546f +
3318 // (1.4034025f - 0.23903021f * x) * x;
3319 //
3320 // error 0.0034276066, which is better than 8 bits
3321 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3322 getF32Constant(DAG, 0xbe74c456));
3323 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3324 getF32Constant(DAG, 0x3fb3a2b1));
3325 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3326 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3327 getF32Constant(DAG, 0x3f949a29));
3328
3329 result = DAG.getNode(ISD::FADD, dl,
3330 MVT::f32, LogOfExponent, LogOfMantissa);
3331 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3332 // For floating-point precision of 12:
3333 //
3334 // LogOfMantissa =
3335 // -1.7417939f +
3336 // (2.8212026f +
3337 // (-1.4699568f +
3338 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3339 //
3340 // error 0.000061011436, which is 14 bits
3341 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3342 getF32Constant(DAG, 0xbd67b6d6));
3343 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3344 getF32Constant(DAG, 0x3ee4f4b8));
3345 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3346 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3347 getF32Constant(DAG, 0x3fbc278b));
3348 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3349 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3350 getF32Constant(DAG, 0x40348e95));
3351 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3352 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3353 getF32Constant(DAG, 0x3fdef31a));
3354
3355 result = DAG.getNode(ISD::FADD, dl,
3356 MVT::f32, LogOfExponent, LogOfMantissa);
3357 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3358 // For floating-point precision of 18:
3359 //
3360 // LogOfMantissa =
3361 // -2.1072184f +
3362 // (4.2372794f +
3363 // (-3.7029485f +
3364 // (2.2781945f +
3365 // (-0.87823314f +
3366 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3367 //
3368 // error 0.0000023660568, which is better than 18 bits
3369 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3370 getF32Constant(DAG, 0xbc91e5ac));
3371 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3372 getF32Constant(DAG, 0x3e4350aa));
3373 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3374 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3375 getF32Constant(DAG, 0x3f60d3e3));
3376 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3377 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3378 getF32Constant(DAG, 0x4011cdf0));
3379 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3380 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3381 getF32Constant(DAG, 0x406cfd1c));
3382 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3383 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3384 getF32Constant(DAG, 0x408797cb));
3385 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3386 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3387 getF32Constant(DAG, 0x4006dcab));
3388
3389 result = DAG.getNode(ISD::FADD, dl,
3390 MVT::f32, LogOfExponent, LogOfMantissa);
3391 }
3392 } else {
3393 // No special expansion.
3394 result = DAG.getNode(ISD::FLOG, dl,
3395 getValue(I.getArgOperand(0)).getValueType(),
3396 getValue(I.getArgOperand(0)));
3397 }
3398
3399 setValue(&I, result);
3400 }
3401
3402 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3403 /// limited-precision mode.
3404 void
visitLog2(const CallInst & I)3405 SelectionDAGBuilder::visitLog2(const CallInst &I) {
3406 SDValue result;
3407 DebugLoc dl = getCurDebugLoc();
3408
3409 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3410 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3411 SDValue Op = getValue(I.getArgOperand(0));
3412 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3413
3414 // Get the exponent.
3415 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3416
3417 // Get the significand and build it into a floating-point number with
3418 // exponent of 1.
3419 SDValue X = GetSignificand(DAG, Op1, dl);
3420
3421 // Different possible minimax approximations of significand in
3422 // floating-point for various degrees of accuracy over [1,2].
3423 if (LimitFloatPrecision <= 6) {
3424 // For floating-point precision of 6:
3425 //
3426 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3427 //
3428 // error 0.0049451742, which is more than 7 bits
3429 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3430 getF32Constant(DAG, 0xbeb08fe0));
3431 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3432 getF32Constant(DAG, 0x40019463));
3433 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3434 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3435 getF32Constant(DAG, 0x3fd6633d));
3436
3437 result = DAG.getNode(ISD::FADD, dl,
3438 MVT::f32, LogOfExponent, Log2ofMantissa);
3439 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3440 // For floating-point precision of 12:
3441 //
3442 // Log2ofMantissa =
3443 // -2.51285454f +
3444 // (4.07009056f +
3445 // (-2.12067489f +
3446 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3447 //
3448 // error 0.0000876136000, which is better than 13 bits
3449 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3450 getF32Constant(DAG, 0xbda7262e));
3451 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3452 getF32Constant(DAG, 0x3f25280b));
3453 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3454 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3455 getF32Constant(DAG, 0x4007b923));
3456 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3457 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3458 getF32Constant(DAG, 0x40823e2f));
3459 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3460 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3461 getF32Constant(DAG, 0x4020d29c));
3462
3463 result = DAG.getNode(ISD::FADD, dl,
3464 MVT::f32, LogOfExponent, Log2ofMantissa);
3465 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3466 // For floating-point precision of 18:
3467 //
3468 // Log2ofMantissa =
3469 // -3.0400495f +
3470 // (6.1129976f +
3471 // (-5.3420409f +
3472 // (3.2865683f +
3473 // (-1.2669343f +
3474 // (0.27515199f -
3475 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3476 //
3477 // error 0.0000018516, which is better than 18 bits
3478 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3479 getF32Constant(DAG, 0xbcd2769e));
3480 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3481 getF32Constant(DAG, 0x3e8ce0b9));
3482 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3483 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3484 getF32Constant(DAG, 0x3fa22ae7));
3485 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3486 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3487 getF32Constant(DAG, 0x40525723));
3488 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3489 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3490 getF32Constant(DAG, 0x40aaf200));
3491 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3492 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3493 getF32Constant(DAG, 0x40c39dad));
3494 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3495 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3496 getF32Constant(DAG, 0x4042902c));
3497
3498 result = DAG.getNode(ISD::FADD, dl,
3499 MVT::f32, LogOfExponent, Log2ofMantissa);
3500 }
3501 } else {
3502 // No special expansion.
3503 result = DAG.getNode(ISD::FLOG2, dl,
3504 getValue(I.getArgOperand(0)).getValueType(),
3505 getValue(I.getArgOperand(0)));
3506 }
3507
3508 setValue(&I, result);
3509 }
3510
3511 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3512 /// limited-precision mode.
3513 void
visitLog10(const CallInst & I)3514 SelectionDAGBuilder::visitLog10(const CallInst &I) {
3515 SDValue result;
3516 DebugLoc dl = getCurDebugLoc();
3517
3518 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3519 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3520 SDValue Op = getValue(I.getArgOperand(0));
3521 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3522
3523 // Scale the exponent by log10(2) [0.30102999f].
3524 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3525 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3526 getF32Constant(DAG, 0x3e9a209a));
3527
3528 // Get the significand and build it into a floating-point number with
3529 // exponent of 1.
3530 SDValue X = GetSignificand(DAG, Op1, dl);
3531
3532 if (LimitFloatPrecision <= 6) {
3533 // For floating-point precision of 6:
3534 //
3535 // Log10ofMantissa =
3536 // -0.50419619f +
3537 // (0.60948995f - 0.10380950f * x) * x;
3538 //
3539 // error 0.0014886165, which is 6 bits
3540 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3541 getF32Constant(DAG, 0xbdd49a13));
3542 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3543 getF32Constant(DAG, 0x3f1c0789));
3544 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3545 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3546 getF32Constant(DAG, 0x3f011300));
3547
3548 result = DAG.getNode(ISD::FADD, dl,
3549 MVT::f32, LogOfExponent, Log10ofMantissa);
3550 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3551 // For floating-point precision of 12:
3552 //
3553 // Log10ofMantissa =
3554 // -0.64831180f +
3555 // (0.91751397f +
3556 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3557 //
3558 // error 0.00019228036, which is better than 12 bits
3559 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3560 getF32Constant(DAG, 0x3d431f31));
3561 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3562 getF32Constant(DAG, 0x3ea21fb2));
3563 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3564 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3565 getF32Constant(DAG, 0x3f6ae232));
3566 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3567 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3568 getF32Constant(DAG, 0x3f25f7c3));
3569
3570 result = DAG.getNode(ISD::FADD, dl,
3571 MVT::f32, LogOfExponent, Log10ofMantissa);
3572 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3573 // For floating-point precision of 18:
3574 //
3575 // Log10ofMantissa =
3576 // -0.84299375f +
3577 // (1.5327582f +
3578 // (-1.0688956f +
3579 // (0.49102474f +
3580 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3581 //
3582 // error 0.0000037995730, which is better than 18 bits
3583 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3584 getF32Constant(DAG, 0x3c5d51ce));
3585 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3586 getF32Constant(DAG, 0x3e00685a));
3587 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3588 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3589 getF32Constant(DAG, 0x3efb6798));
3590 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3591 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3592 getF32Constant(DAG, 0x3f88d192));
3593 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3594 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3595 getF32Constant(DAG, 0x3fc4316c));
3596 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3597 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3598 getF32Constant(DAG, 0x3f57ce70));
3599
3600 result = DAG.getNode(ISD::FADD, dl,
3601 MVT::f32, LogOfExponent, Log10ofMantissa);
3602 }
3603 } else {
3604 // No special expansion.
3605 result = DAG.getNode(ISD::FLOG10, dl,
3606 getValue(I.getArgOperand(0)).getValueType(),
3607 getValue(I.getArgOperand(0)));
3608 }
3609
3610 setValue(&I, result);
3611 }
3612
3613 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3614 /// limited-precision mode.
3615 void
visitExp2(const CallInst & I)3616 SelectionDAGBuilder::visitExp2(const CallInst &I) {
3617 SDValue result;
3618 DebugLoc dl = getCurDebugLoc();
3619
3620 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3621 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3622 SDValue Op = getValue(I.getArgOperand(0));
3623
3624 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
3625
3626 // FractionalPartOfX = x - (float)IntegerPartOfX;
3627 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3628 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
3629
3630 // IntegerPartOfX <<= 23;
3631 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3632 DAG.getConstant(23, TLI.getPointerTy()));
3633
3634 if (LimitFloatPrecision <= 6) {
3635 // For floating-point precision of 6:
3636 //
3637 // TwoToFractionalPartOfX =
3638 // 0.997535578f +
3639 // (0.735607626f + 0.252464424f * x) * x;
3640 //
3641 // error 0.0144103317, which is 6 bits
3642 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3643 getF32Constant(DAG, 0x3e814304));
3644 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3645 getF32Constant(DAG, 0x3f3c50c8));
3646 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3647 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3648 getF32Constant(DAG, 0x3f7f5e7e));
3649 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3650 SDValue TwoToFractionalPartOfX =
3651 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3652
3653 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3654 MVT::f32, TwoToFractionalPartOfX);
3655 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3656 // For floating-point precision of 12:
3657 //
3658 // TwoToFractionalPartOfX =
3659 // 0.999892986f +
3660 // (0.696457318f +
3661 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3662 //
3663 // error 0.000107046256, which is 13 to 14 bits
3664 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3665 getF32Constant(DAG, 0x3da235e3));
3666 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3667 getF32Constant(DAG, 0x3e65b8f3));
3668 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3669 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3670 getF32Constant(DAG, 0x3f324b07));
3671 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3672 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3673 getF32Constant(DAG, 0x3f7ff8fd));
3674 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3675 SDValue TwoToFractionalPartOfX =
3676 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3677
3678 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3679 MVT::f32, TwoToFractionalPartOfX);
3680 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3681 // For floating-point precision of 18:
3682 //
3683 // TwoToFractionalPartOfX =
3684 // 0.999999982f +
3685 // (0.693148872f +
3686 // (0.240227044f +
3687 // (0.554906021e-1f +
3688 // (0.961591928e-2f +
3689 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3690 // error 2.47208000*10^(-7), which is better than 18 bits
3691 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3692 getF32Constant(DAG, 0x3924b03e));
3693 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3694 getF32Constant(DAG, 0x3ab24b87));
3695 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3696 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3697 getF32Constant(DAG, 0x3c1d8c17));
3698 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3699 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3700 getF32Constant(DAG, 0x3d634a1d));
3701 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3702 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3703 getF32Constant(DAG, 0x3e75fe14));
3704 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3705 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3706 getF32Constant(DAG, 0x3f317234));
3707 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3708 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3709 getF32Constant(DAG, 0x3f800000));
3710 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3711 SDValue TwoToFractionalPartOfX =
3712 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3713
3714 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3715 MVT::f32, TwoToFractionalPartOfX);
3716 }
3717 } else {
3718 // No special expansion.
3719 result = DAG.getNode(ISD::FEXP2, dl,
3720 getValue(I.getArgOperand(0)).getValueType(),
3721 getValue(I.getArgOperand(0)));
3722 }
3723
3724 setValue(&I, result);
3725 }
3726
3727 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3728 /// limited-precision mode with x == 10.0f.
3729 void
visitPow(const CallInst & I)3730 SelectionDAGBuilder::visitPow(const CallInst &I) {
3731 SDValue result;
3732 const Value *Val = I.getArgOperand(0);
3733 DebugLoc dl = getCurDebugLoc();
3734 bool IsExp10 = false;
3735
3736 if (getValue(Val).getValueType() == MVT::f32 &&
3737 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 &&
3738 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3739 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
3740 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
3741 APFloat Ten(10.0f);
3742 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
3743 }
3744 }
3745 }
3746
3747 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3748 SDValue Op = getValue(I.getArgOperand(1));
3749
3750 // Put the exponent in the right bit position for later addition to the
3751 // final result:
3752 //
3753 // #define LOG2OF10 3.3219281f
3754 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
3755 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3756 getF32Constant(DAG, 0x40549a78));
3757 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3758
3759 // FractionalPartOfX = x - (float)IntegerPartOfX;
3760 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3761 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3762
3763 // IntegerPartOfX <<= 23;
3764 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3765 DAG.getConstant(23, TLI.getPointerTy()));
3766
3767 if (LimitFloatPrecision <= 6) {
3768 // For floating-point precision of 6:
3769 //
3770 // twoToFractionalPartOfX =
3771 // 0.997535578f +
3772 // (0.735607626f + 0.252464424f * x) * x;
3773 //
3774 // error 0.0144103317, which is 6 bits
3775 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3776 getF32Constant(DAG, 0x3e814304));
3777 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3778 getF32Constant(DAG, 0x3f3c50c8));
3779 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3780 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3781 getF32Constant(DAG, 0x3f7f5e7e));
3782 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3783 SDValue TwoToFractionalPartOfX =
3784 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3785
3786 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3787 MVT::f32, TwoToFractionalPartOfX);
3788 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3789 // For floating-point precision of 12:
3790 //
3791 // TwoToFractionalPartOfX =
3792 // 0.999892986f +
3793 // (0.696457318f +
3794 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3795 //
3796 // error 0.000107046256, which is 13 to 14 bits
3797 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3798 getF32Constant(DAG, 0x3da235e3));
3799 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3800 getF32Constant(DAG, 0x3e65b8f3));
3801 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3802 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3803 getF32Constant(DAG, 0x3f324b07));
3804 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3805 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3806 getF32Constant(DAG, 0x3f7ff8fd));
3807 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3808 SDValue TwoToFractionalPartOfX =
3809 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3810
3811 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3812 MVT::f32, TwoToFractionalPartOfX);
3813 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3814 // For floating-point precision of 18:
3815 //
3816 // TwoToFractionalPartOfX =
3817 // 0.999999982f +
3818 // (0.693148872f +
3819 // (0.240227044f +
3820 // (0.554906021e-1f +
3821 // (0.961591928e-2f +
3822 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3823 // error 2.47208000*10^(-7), which is better than 18 bits
3824 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3825 getF32Constant(DAG, 0x3924b03e));
3826 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3827 getF32Constant(DAG, 0x3ab24b87));
3828 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3829 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3830 getF32Constant(DAG, 0x3c1d8c17));
3831 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3832 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3833 getF32Constant(DAG, 0x3d634a1d));
3834 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3835 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3836 getF32Constant(DAG, 0x3e75fe14));
3837 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3838 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3839 getF32Constant(DAG, 0x3f317234));
3840 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3841 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3842 getF32Constant(DAG, 0x3f800000));
3843 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3844 SDValue TwoToFractionalPartOfX =
3845 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3846
3847 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3848 MVT::f32, TwoToFractionalPartOfX);
3849 }
3850 } else {
3851 // No special expansion.
3852 result = DAG.getNode(ISD::FPOW, dl,
3853 getValue(I.getArgOperand(0)).getValueType(),
3854 getValue(I.getArgOperand(0)),
3855 getValue(I.getArgOperand(1)));
3856 }
3857
3858 setValue(&I, result);
3859 }
3860
3861
3862 /// ExpandPowI - Expand a llvm.powi intrinsic.
ExpandPowI(DebugLoc DL,SDValue LHS,SDValue RHS,SelectionDAG & DAG)3863 static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS,
3864 SelectionDAG &DAG) {
3865 // If RHS is a constant, we can expand this out to a multiplication tree,
3866 // otherwise we end up lowering to a call to __powidf2 (for example). When
3867 // optimizing for size, we only want to do this if the expansion would produce
3868 // a small number of multiplies, otherwise we do the full expansion.
3869 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3870 // Get the exponent as a positive value.
3871 unsigned Val = RHSC->getSExtValue();
3872 if ((int)Val < 0) Val = -Val;
3873
3874 // powi(x, 0) -> 1.0
3875 if (Val == 0)
3876 return DAG.getConstantFP(1.0, LHS.getValueType());
3877
3878 const Function *F = DAG.getMachineFunction().getFunction();
3879 if (!F->hasFnAttr(Attribute::OptimizeForSize) ||
3880 // If optimizing for size, don't insert too many multiplies. This
3881 // inserts up to 5 multiplies.
3882 CountPopulation_32(Val)+Log2_32(Val) < 7) {
3883 // We use the simple binary decomposition method to generate the multiply
3884 // sequence. There are more optimal ways to do this (for example,
3885 // powi(x,15) generates one more multiply than it should), but this has
3886 // the benefit of being both really simple and much better than a libcall.
3887 SDValue Res; // Logically starts equal to 1.0
3888 SDValue CurSquare = LHS;
3889 while (Val) {
3890 if (Val & 1) {
3891 if (Res.getNode())
3892 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
3893 else
3894 Res = CurSquare; // 1.0*CurSquare.
3895 }
3896
3897 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
3898 CurSquare, CurSquare);
3899 Val >>= 1;
3900 }
3901
3902 // If the original was negative, invert the result, producing 1/(x*x*x).
3903 if (RHSC->getSExtValue() < 0)
3904 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
3905 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
3906 return Res;
3907 }
3908 }
3909
3910 // Otherwise, expand to a libcall.
3911 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
3912 }
3913
3914 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
3915 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
3916 /// At the end of instruction selection, they will be inserted to the entry BB.
3917 bool
EmitFuncArgumentDbgValue(const Value * V,MDNode * Variable,int64_t Offset,const SDValue & N)3918 SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable,
3919 int64_t Offset,
3920 const SDValue &N) {
3921 const Argument *Arg = dyn_cast<Argument>(V);
3922 if (!Arg)
3923 return false;
3924
3925 MachineFunction &MF = DAG.getMachineFunction();
3926 // Ignore inlined function arguments here.
3927 DIVariable DV(Variable);
3928 if (DV.isInlinedFnArgument(MF.getFunction()))
3929 return false;
3930
3931 MachineBasicBlock *MBB = FuncInfo.MBB;
3932 if (MBB != &MF.front())
3933 return false;
3934
3935 unsigned Reg = 0;
3936 if (Arg->hasByValAttr()) {
3937 // Byval arguments' frame index is recorded during argument lowering.
3938 // Use this info directly.
3939 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
3940 Reg = TRI->getFrameRegister(MF);
3941 Offset = FuncInfo.getByValArgumentFrameIndex(Arg);
3942 }
3943
3944 if (N.getNode() && N.getOpcode() == ISD::CopyFromReg) {
3945 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
3946 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
3947 MachineRegisterInfo &RegInfo = MF.getRegInfo();
3948 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
3949 if (PR)
3950 Reg = PR;
3951 }
3952 }
3953
3954 if (!Reg) {
3955 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
3956 if (VMI == FuncInfo.ValueMap.end())
3957 return false;
3958 Reg = VMI->second;
3959 }
3960
3961 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo();
3962 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(),
3963 TII->get(TargetOpcode::DBG_VALUE))
3964 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable);
3965 FuncInfo.ArgDbgValues.push_back(&*MIB);
3966 return true;
3967 }
3968
3969 // VisualStudio defines setjmp as _setjmp
3970 #if defined(_MSC_VER) && defined(setjmp)
3971 #define setjmp_undefined_for_visual_studio
3972 #undef setjmp
3973 #endif
3974
3975 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
3976 /// we want to emit this as a call to a named external function, return the name
3977 /// otherwise lower it and return null.
3978 const char *
visitIntrinsicCall(const CallInst & I,unsigned Intrinsic)3979 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
3980 DebugLoc dl = getCurDebugLoc();
3981 SDValue Res;
3982
3983 switch (Intrinsic) {
3984 default:
3985 // By default, turn this into a target intrinsic node.
3986 visitTargetIntrinsic(I, Intrinsic);
3987 return 0;
3988 case Intrinsic::vastart: visitVAStart(I); return 0;
3989 case Intrinsic::vaend: visitVAEnd(I); return 0;
3990 case Intrinsic::vacopy: visitVACopy(I); return 0;
3991 case Intrinsic::returnaddress:
3992 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
3993 getValue(I.getArgOperand(0))));
3994 return 0;
3995 case Intrinsic::frameaddress:
3996 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
3997 getValue(I.getArgOperand(0))));
3998 return 0;
3999 case Intrinsic::setjmp:
4000 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
4001 case Intrinsic::longjmp:
4002 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
4003 case Intrinsic::memcpy: {
4004 // Assert for address < 256 since we support only user defined address
4005 // spaces.
4006 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4007 < 256 &&
4008 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4009 < 256 &&
4010 "Unknown address space");
4011 SDValue Op1 = getValue(I.getArgOperand(0));
4012 SDValue Op2 = getValue(I.getArgOperand(1));
4013 SDValue Op3 = getValue(I.getArgOperand(2));
4014 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4015 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4016 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false,
4017 I.getArgOperand(0), 0, I.getArgOperand(1), 0));
4018 return 0;
4019 }
4020 case Intrinsic::memset: {
4021 // Assert for address < 256 since we support only user defined address
4022 // spaces.
4023 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4024 < 256 &&
4025 "Unknown address space");
4026 SDValue Op1 = getValue(I.getArgOperand(0));
4027 SDValue Op2 = getValue(I.getArgOperand(1));
4028 SDValue Op3 = getValue(I.getArgOperand(2));
4029 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4030 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4031 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4032 I.getArgOperand(0), 0));
4033 return 0;
4034 }
4035 case Intrinsic::memmove: {
4036 // Assert for address < 256 since we support only user defined address
4037 // spaces.
4038 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4039 < 256 &&
4040 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4041 < 256 &&
4042 "Unknown address space");
4043 SDValue Op1 = getValue(I.getArgOperand(0));
4044 SDValue Op2 = getValue(I.getArgOperand(1));
4045 SDValue Op3 = getValue(I.getArgOperand(2));
4046 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4047 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4048
4049 // If the source and destination are known to not be aliases, we can
4050 // lower memmove as memcpy.
4051 uint64_t Size = -1ULL;
4052 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
4053 Size = C->getZExtValue();
4054 if (AA->alias(I.getArgOperand(0), Size, I.getArgOperand(1), Size) ==
4055 AliasAnalysis::NoAlias) {
4056 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4057 false, I.getArgOperand(0), 0,
4058 I.getArgOperand(1), 0));
4059 return 0;
4060 }
4061
4062 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4063 I.getArgOperand(0), 0, I.getArgOperand(1), 0));
4064 return 0;
4065 }
4066 case Intrinsic::dbg_declare: {
4067 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4068 MDNode *Variable = DI.getVariable();
4069 const Value *Address = DI.getAddress();
4070 if (!Address || !DIVariable(DI.getVariable()).Verify())
4071 return 0;
4072
4073 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4074 // but do not always have a corresponding SDNode built. The SDNodeOrder
4075 // absolute, but not relative, values are different depending on whether
4076 // debug info exists.
4077 ++SDNodeOrder;
4078
4079 // Check if address has undef value.
4080 if (isa<UndefValue>(Address) ||
4081 (Address->use_empty() && !isa<Argument>(Address))) {
4082 SDDbgValue*SDV =
4083 DAG.getDbgValue(Variable, UndefValue::get(Address->getType()),
4084 0, dl, SDNodeOrder);
4085 DAG.AddDbgValue(SDV, 0, false);
4086 return 0;
4087 }
4088
4089 SDValue &N = NodeMap[Address];
4090 if (!N.getNode() && isa<Argument>(Address))
4091 // Check unused arguments map.
4092 N = UnusedArgNodeMap[Address];
4093 SDDbgValue *SDV;
4094 if (N.getNode()) {
4095 // Parameters are handled specially.
4096 bool isParameter =
4097 DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable;
4098 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4099 Address = BCI->getOperand(0);
4100 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4101
4102 if (isParameter && !AI) {
4103 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4104 if (FINode)
4105 // Byval parameter. We have a frame index at this point.
4106 SDV = DAG.getDbgValue(Variable, FINode->getIndex(),
4107 0, dl, SDNodeOrder);
4108 else
4109 // Can't do anything with other non-AI cases yet. This might be a
4110 // parameter of a callee function that got inlined, for example.
4111 return 0;
4112 } else if (AI)
4113 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(),
4114 0, dl, SDNodeOrder);
4115 else
4116 // Can't do anything with other non-AI cases yet.
4117 return 0;
4118 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4119 } else {
4120 // If Address is an arugment then try to emits its dbg value using
4121 // virtual register info from the FuncInfo.ValueMap. Otherwise add undef
4122 // to help track missing debug info.
4123 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) {
4124 SDV = DAG.getDbgValue(Variable, UndefValue::get(Address->getType()),
4125 0, dl, SDNodeOrder);
4126 DAG.AddDbgValue(SDV, 0, false);
4127 }
4128 }
4129 return 0;
4130 }
4131 case Intrinsic::dbg_value: {
4132 const DbgValueInst &DI = cast<DbgValueInst>(I);
4133 if (!DIVariable(DI.getVariable()).Verify())
4134 return 0;
4135
4136 MDNode *Variable = DI.getVariable();
4137 uint64_t Offset = DI.getOffset();
4138 const Value *V = DI.getValue();
4139 if (!V)
4140 return 0;
4141
4142 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4143 // but do not always have a corresponding SDNode built. The SDNodeOrder
4144 // absolute, but not relative, values are different depending on whether
4145 // debug info exists.
4146 ++SDNodeOrder;
4147 SDDbgValue *SDV;
4148 if (isa<ConstantInt>(V) || isa<ConstantFP>(V)) {
4149 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder);
4150 DAG.AddDbgValue(SDV, 0, false);
4151 } else {
4152 // Do not use getValue() in here; we don't want to generate code at
4153 // this point if it hasn't been done yet.
4154 SDValue N = NodeMap[V];
4155 if (!N.getNode() && isa<Argument>(V))
4156 // Check unused arguments map.
4157 N = UnusedArgNodeMap[V];
4158 if (N.getNode()) {
4159 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) {
4160 SDV = DAG.getDbgValue(Variable, N.getNode(),
4161 N.getResNo(), Offset, dl, SDNodeOrder);
4162 DAG.AddDbgValue(SDV, N.getNode(), false);
4163 }
4164 } else if (isa<PHINode>(V) && !V->use_empty() ) {
4165 // Do not call getValue(V) yet, as we don't want to generate code.
4166 // Remember it for later.
4167 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4168 DanglingDebugInfoMap[V] = DDI;
4169 } else {
4170 // We may expand this to cover more cases. One case where we have no
4171 // data available is an unreferenced parameter; we need this fallback.
4172 SDV = DAG.getDbgValue(Variable, UndefValue::get(V->getType()),
4173 Offset, dl, SDNodeOrder);
4174 DAG.AddDbgValue(SDV, 0, false);
4175 }
4176 }
4177
4178 // Build a debug info table entry.
4179 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4180 V = BCI->getOperand(0);
4181 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4182 // Don't handle byval struct arguments or VLAs, for example.
4183 if (!AI)
4184 return 0;
4185 DenseMap<const AllocaInst*, int>::iterator SI =
4186 FuncInfo.StaticAllocaMap.find(AI);
4187 if (SI == FuncInfo.StaticAllocaMap.end())
4188 return 0; // VLAs.
4189 int FI = SI->second;
4190
4191 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4192 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo())
4193 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc());
4194 return 0;
4195 }
4196 case Intrinsic::eh_exception: {
4197 // Insert the EXCEPTIONADDR instruction.
4198 assert(FuncInfo.MBB->isLandingPad() &&
4199 "Call to eh.exception not in landing pad!");
4200 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
4201 SDValue Ops[1];
4202 Ops[0] = DAG.getRoot();
4203 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
4204 setValue(&I, Op);
4205 DAG.setRoot(Op.getValue(1));
4206 return 0;
4207 }
4208
4209 case Intrinsic::eh_selector: {
4210 MachineBasicBlock *CallMBB = FuncInfo.MBB;
4211 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4212 if (CallMBB->isLandingPad())
4213 AddCatchInfo(I, &MMI, CallMBB);
4214 else {
4215 #ifndef NDEBUG
4216 FuncInfo.CatchInfoLost.insert(&I);
4217 #endif
4218 // FIXME: Mark exception selector register as live in. Hack for PR1508.
4219 unsigned Reg = TLI.getExceptionSelectorRegister();
4220 if (Reg) FuncInfo.MBB->addLiveIn(Reg);
4221 }
4222
4223 // Insert the EHSELECTION instruction.
4224 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
4225 SDValue Ops[2];
4226 Ops[0] = getValue(I.getArgOperand(0));
4227 Ops[1] = getRoot();
4228 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2);
4229 DAG.setRoot(Op.getValue(1));
4230 setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32));
4231 return 0;
4232 }
4233
4234 case Intrinsic::eh_typeid_for: {
4235 // Find the type id for the given typeinfo.
4236 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0));
4237 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4238 Res = DAG.getConstant(TypeID, MVT::i32);
4239 setValue(&I, Res);
4240 return 0;
4241 }
4242
4243 case Intrinsic::eh_return_i32:
4244 case Intrinsic::eh_return_i64:
4245 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4246 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
4247 MVT::Other,
4248 getControlRoot(),
4249 getValue(I.getArgOperand(0)),
4250 getValue(I.getArgOperand(1))));
4251 return 0;
4252 case Intrinsic::eh_unwind_init:
4253 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4254 return 0;
4255 case Intrinsic::eh_dwarf_cfa: {
4256 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl,
4257 TLI.getPointerTy());
4258 SDValue Offset = DAG.getNode(ISD::ADD, dl,
4259 TLI.getPointerTy(),
4260 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
4261 TLI.getPointerTy()),
4262 CfaArg);
4263 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl,
4264 TLI.getPointerTy(),
4265 DAG.getConstant(0, TLI.getPointerTy()));
4266 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
4267 FA, Offset));
4268 return 0;
4269 }
4270 case Intrinsic::eh_sjlj_callsite: {
4271 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4272 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4273 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4274 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4275
4276 MMI.setCurrentCallSite(CI->getZExtValue());
4277 return 0;
4278 }
4279 case Intrinsic::eh_sjlj_setjmp: {
4280 setValue(&I, DAG.getNode(ISD::EH_SJLJ_SETJMP, dl, MVT::i32, getRoot(),
4281 getValue(I.getArgOperand(0))));
4282 return 0;
4283 }
4284 case Intrinsic::eh_sjlj_longjmp: {
4285 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other,
4286 getRoot(),
4287 getValue(I.getArgOperand(0))));
4288 return 0;
4289 }
4290
4291 case Intrinsic::convertff:
4292 case Intrinsic::convertfsi:
4293 case Intrinsic::convertfui:
4294 case Intrinsic::convertsif:
4295 case Intrinsic::convertuif:
4296 case Intrinsic::convertss:
4297 case Intrinsic::convertsu:
4298 case Intrinsic::convertus:
4299 case Intrinsic::convertuu: {
4300 ISD::CvtCode Code = ISD::CVT_INVALID;
4301 switch (Intrinsic) {
4302 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4303 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4304 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4305 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4306 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4307 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4308 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4309 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4310 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4311 }
4312 EVT DestVT = TLI.getValueType(I.getType());
4313 const Value *Op1 = I.getArgOperand(0);
4314 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
4315 DAG.getValueType(DestVT),
4316 DAG.getValueType(getValue(Op1).getValueType()),
4317 getValue(I.getArgOperand(1)),
4318 getValue(I.getArgOperand(2)),
4319 Code);
4320 setValue(&I, Res);
4321 return 0;
4322 }
4323 case Intrinsic::sqrt:
4324 setValue(&I, DAG.getNode(ISD::FSQRT, dl,
4325 getValue(I.getArgOperand(0)).getValueType(),
4326 getValue(I.getArgOperand(0))));
4327 return 0;
4328 case Intrinsic::powi:
4329 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)),
4330 getValue(I.getArgOperand(1)), DAG));
4331 return 0;
4332 case Intrinsic::sin:
4333 setValue(&I, DAG.getNode(ISD::FSIN, dl,
4334 getValue(I.getArgOperand(0)).getValueType(),
4335 getValue(I.getArgOperand(0))));
4336 return 0;
4337 case Intrinsic::cos:
4338 setValue(&I, DAG.getNode(ISD::FCOS, dl,
4339 getValue(I.getArgOperand(0)).getValueType(),
4340 getValue(I.getArgOperand(0))));
4341 return 0;
4342 case Intrinsic::log:
4343 visitLog(I);
4344 return 0;
4345 case Intrinsic::log2:
4346 visitLog2(I);
4347 return 0;
4348 case Intrinsic::log10:
4349 visitLog10(I);
4350 return 0;
4351 case Intrinsic::exp:
4352 visitExp(I);
4353 return 0;
4354 case Intrinsic::exp2:
4355 visitExp2(I);
4356 return 0;
4357 case Intrinsic::pow:
4358 visitPow(I);
4359 return 0;
4360 case Intrinsic::convert_to_fp16:
4361 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl,
4362 MVT::i16, getValue(I.getArgOperand(0))));
4363 return 0;
4364 case Intrinsic::convert_from_fp16:
4365 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl,
4366 MVT::f32, getValue(I.getArgOperand(0))));
4367 return 0;
4368 case Intrinsic::pcmarker: {
4369 SDValue Tmp = getValue(I.getArgOperand(0));
4370 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
4371 return 0;
4372 }
4373 case Intrinsic::readcyclecounter: {
4374 SDValue Op = getRoot();
4375 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4376 DAG.getVTList(MVT::i64, MVT::Other),
4377 &Op, 1);
4378 setValue(&I, Res);
4379 DAG.setRoot(Res.getValue(1));
4380 return 0;
4381 }
4382 case Intrinsic::bswap:
4383 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4384 getValue(I.getArgOperand(0)).getValueType(),
4385 getValue(I.getArgOperand(0))));
4386 return 0;
4387 case Intrinsic::cttz: {
4388 SDValue Arg = getValue(I.getArgOperand(0));
4389 EVT Ty = Arg.getValueType();
4390 setValue(&I, DAG.getNode(ISD::CTTZ, dl, Ty, Arg));
4391 return 0;
4392 }
4393 case Intrinsic::ctlz: {
4394 SDValue Arg = getValue(I.getArgOperand(0));
4395 EVT Ty = Arg.getValueType();
4396 setValue(&I, DAG.getNode(ISD::CTLZ, dl, Ty, Arg));
4397 return 0;
4398 }
4399 case Intrinsic::ctpop: {
4400 SDValue Arg = getValue(I.getArgOperand(0));
4401 EVT Ty = Arg.getValueType();
4402 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg));
4403 return 0;
4404 }
4405 case Intrinsic::stacksave: {
4406 SDValue Op = getRoot();
4407 Res = DAG.getNode(ISD::STACKSAVE, dl,
4408 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
4409 setValue(&I, Res);
4410 DAG.setRoot(Res.getValue(1));
4411 return 0;
4412 }
4413 case Intrinsic::stackrestore: {
4414 Res = getValue(I.getArgOperand(0));
4415 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res));
4416 return 0;
4417 }
4418 case Intrinsic::stackprotector: {
4419 // Emit code into the DAG to store the stack guard onto the stack.
4420 MachineFunction &MF = DAG.getMachineFunction();
4421 MachineFrameInfo *MFI = MF.getFrameInfo();
4422 EVT PtrTy = TLI.getPointerTy();
4423
4424 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value.
4425 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4426
4427 int FI = FuncInfo.StaticAllocaMap[Slot];
4428 MFI->setStackProtectorIndex(FI);
4429
4430 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4431
4432 // Store the stack protector onto the stack.
4433 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
4434 PseudoSourceValue::getFixedStack(FI),
4435 0, true, false, 0);
4436 setValue(&I, Res);
4437 DAG.setRoot(Res);
4438 return 0;
4439 }
4440 case Intrinsic::objectsize: {
4441 // If we don't know by now, we're never going to know.
4442 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
4443
4444 assert(CI && "Non-constant type in __builtin_object_size?");
4445
4446 SDValue Arg = getValue(I.getCalledValue());
4447 EVT Ty = Arg.getValueType();
4448
4449 if (CI->isZero())
4450 Res = DAG.getConstant(-1ULL, Ty);
4451 else
4452 Res = DAG.getConstant(0, Ty);
4453
4454 setValue(&I, Res);
4455 return 0;
4456 }
4457 case Intrinsic::var_annotation:
4458 // Discard annotate attributes
4459 return 0;
4460
4461 case Intrinsic::init_trampoline: {
4462 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
4463
4464 SDValue Ops[6];
4465 Ops[0] = getRoot();
4466 Ops[1] = getValue(I.getArgOperand(0));
4467 Ops[2] = getValue(I.getArgOperand(1));
4468 Ops[3] = getValue(I.getArgOperand(2));
4469 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
4470 Ops[5] = DAG.getSrcValue(F);
4471
4472 Res = DAG.getNode(ISD::TRAMPOLINE, dl,
4473 DAG.getVTList(TLI.getPointerTy(), MVT::Other),
4474 Ops, 6);
4475
4476 setValue(&I, Res);
4477 DAG.setRoot(Res.getValue(1));
4478 return 0;
4479 }
4480 case Intrinsic::gcroot:
4481 if (GFI) {
4482 const Value *Alloca = I.getArgOperand(0);
4483 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
4484
4485 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4486 GFI->addStackRoot(FI->getIndex(), TypeMap);
4487 }
4488 return 0;
4489 case Intrinsic::gcread:
4490 case Intrinsic::gcwrite:
4491 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4492 return 0;
4493 case Intrinsic::flt_rounds:
4494 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
4495 return 0;
4496 case Intrinsic::trap:
4497 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
4498 return 0;
4499 case Intrinsic::uadd_with_overflow:
4500 return implVisitAluOverflow(I, ISD::UADDO);
4501 case Intrinsic::sadd_with_overflow:
4502 return implVisitAluOverflow(I, ISD::SADDO);
4503 case Intrinsic::usub_with_overflow:
4504 return implVisitAluOverflow(I, ISD::USUBO);
4505 case Intrinsic::ssub_with_overflow:
4506 return implVisitAluOverflow(I, ISD::SSUBO);
4507 case Intrinsic::umul_with_overflow:
4508 return implVisitAluOverflow(I, ISD::UMULO);
4509 case Intrinsic::smul_with_overflow:
4510 return implVisitAluOverflow(I, ISD::SMULO);
4511
4512 case Intrinsic::prefetch: {
4513 SDValue Ops[4];
4514 Ops[0] = getRoot();
4515 Ops[1] = getValue(I.getArgOperand(0));
4516 Ops[2] = getValue(I.getArgOperand(1));
4517 Ops[3] = getValue(I.getArgOperand(2));
4518 DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, MVT::Other, &Ops[0], 4));
4519 return 0;
4520 }
4521
4522 case Intrinsic::memory_barrier: {
4523 SDValue Ops[6];
4524 Ops[0] = getRoot();
4525 for (int x = 1; x < 6; ++x)
4526 Ops[x] = getValue(I.getArgOperand(x - 1));
4527
4528 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
4529 return 0;
4530 }
4531 case Intrinsic::atomic_cmp_swap: {
4532 SDValue Root = getRoot();
4533 SDValue L =
4534 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(),
4535 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(),
4536 Root,
4537 getValue(I.getArgOperand(0)),
4538 getValue(I.getArgOperand(1)),
4539 getValue(I.getArgOperand(2)),
4540 I.getArgOperand(0));
4541 setValue(&I, L);
4542 DAG.setRoot(L.getValue(1));
4543 return 0;
4544 }
4545 case Intrinsic::atomic_load_add:
4546 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
4547 case Intrinsic::atomic_load_sub:
4548 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
4549 case Intrinsic::atomic_load_or:
4550 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
4551 case Intrinsic::atomic_load_xor:
4552 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
4553 case Intrinsic::atomic_load_and:
4554 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
4555 case Intrinsic::atomic_load_nand:
4556 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
4557 case Intrinsic::atomic_load_max:
4558 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
4559 case Intrinsic::atomic_load_min:
4560 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
4561 case Intrinsic::atomic_load_umin:
4562 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
4563 case Intrinsic::atomic_load_umax:
4564 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
4565 case Intrinsic::atomic_swap:
4566 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
4567
4568 case Intrinsic::invariant_start:
4569 case Intrinsic::lifetime_start:
4570 // Discard region information.
4571 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
4572 return 0;
4573 case Intrinsic::invariant_end:
4574 case Intrinsic::lifetime_end:
4575 // Discard region information.
4576 return 0;
4577 }
4578 }
4579
LowerCallTo(ImmutableCallSite CS,SDValue Callee,bool isTailCall,MachineBasicBlock * LandingPad)4580 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
4581 bool isTailCall,
4582 MachineBasicBlock *LandingPad) {
4583 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
4584 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
4585 const Type *RetTy = FTy->getReturnType();
4586 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4587 MCSymbol *BeginLabel = 0;
4588
4589 TargetLowering::ArgListTy Args;
4590 TargetLowering::ArgListEntry Entry;
4591 Args.reserve(CS.arg_size());
4592
4593 // Check whether the function can return without sret-demotion.
4594 SmallVector<ISD::OutputArg, 4> Outs;
4595 SmallVector<uint64_t, 4> Offsets;
4596 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(),
4597 Outs, TLI, &Offsets);
4598
4599 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(),
4600 FTy->isVarArg(), Outs, FTy->getContext());
4601
4602 SDValue DemoteStackSlot;
4603
4604 if (!CanLowerReturn) {
4605 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(
4606 FTy->getReturnType());
4607 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(
4608 FTy->getReturnType());
4609 MachineFunction &MF = DAG.getMachineFunction();
4610 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
4611 const Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType());
4612
4613 DemoteStackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
4614 Entry.Node = DemoteStackSlot;
4615 Entry.Ty = StackSlotPtrType;
4616 Entry.isSExt = false;
4617 Entry.isZExt = false;
4618 Entry.isInReg = false;
4619 Entry.isSRet = true;
4620 Entry.isNest = false;
4621 Entry.isByVal = false;
4622 Entry.Alignment = Align;
4623 Args.push_back(Entry);
4624 RetTy = Type::getVoidTy(FTy->getContext());
4625 }
4626
4627 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
4628 i != e; ++i) {
4629 SDValue ArgNode = getValue(*i);
4630 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
4631
4632 unsigned attrInd = i - CS.arg_begin() + 1;
4633 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
4634 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
4635 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
4636 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
4637 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
4638 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
4639 Entry.Alignment = CS.getParamAlignment(attrInd);
4640 Args.push_back(Entry);
4641 }
4642
4643 if (LandingPad) {
4644 // Insert a label before the invoke call to mark the try range. This can be
4645 // used to detect deletion of the invoke via the MachineModuleInfo.
4646 BeginLabel = MMI.getContext().CreateTempSymbol();
4647
4648 // For SjLj, keep track of which landing pads go with which invokes
4649 // so as to maintain the ordering of pads in the LSDA.
4650 unsigned CallSiteIndex = MMI.getCurrentCallSite();
4651 if (CallSiteIndex) {
4652 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
4653 // Now that the call site is handled, stop tracking it.
4654 MMI.setCurrentCallSite(0);
4655 }
4656
4657 // Both PendingLoads and PendingExports must be flushed here;
4658 // this call might not return.
4659 (void)getRoot();
4660 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel));
4661 }
4662
4663 // Check if target-independent constraints permit a tail call here.
4664 // Target-dependent constraints are checked within TLI.LowerCallTo.
4665 if (isTailCall &&
4666 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI))
4667 isTailCall = false;
4668
4669 // If there's a possibility that fast-isel has already selected some amount
4670 // of the current basic block, don't emit a tail call.
4671 if (isTailCall && EnableFastISel)
4672 isTailCall = false;
4673
4674 std::pair<SDValue,SDValue> Result =
4675 TLI.LowerCallTo(getRoot(), RetTy,
4676 CS.paramHasAttr(0, Attribute::SExt),
4677 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
4678 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(),
4679 CS.getCallingConv(),
4680 isTailCall,
4681 !CS.getInstruction()->use_empty(),
4682 Callee, Args, DAG, getCurDebugLoc());
4683 assert((isTailCall || Result.second.getNode()) &&
4684 "Non-null chain expected with non-tail call!");
4685 assert((Result.second.getNode() || !Result.first.getNode()) &&
4686 "Null value expected with tail call!");
4687 if (Result.first.getNode()) {
4688 setValue(CS.getInstruction(), Result.first);
4689 } else if (!CanLowerReturn && Result.second.getNode()) {
4690 // The instruction result is the result of loading from the
4691 // hidden sret parameter.
4692 SmallVector<EVT, 1> PVTs;
4693 const Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType());
4694
4695 ComputeValueVTs(TLI, PtrRetTy, PVTs);
4696 assert(PVTs.size() == 1 && "Pointers should fit in one register");
4697 EVT PtrVT = PVTs[0];
4698 unsigned NumValues = Outs.size();
4699 SmallVector<SDValue, 4> Values(NumValues);
4700 SmallVector<SDValue, 4> Chains(NumValues);
4701
4702 for (unsigned i = 0; i < NumValues; ++i) {
4703 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT,
4704 DemoteStackSlot,
4705 DAG.getConstant(Offsets[i], PtrVT));
4706 SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second,
4707 Add, NULL, Offsets[i], false, false, 1);
4708 Values[i] = L;
4709 Chains[i] = L.getValue(1);
4710 }
4711
4712 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
4713 MVT::Other, &Chains[0], NumValues);
4714 PendingLoads.push_back(Chain);
4715
4716 // Collect the legal value parts into potentially illegal values
4717 // that correspond to the original function's return values.
4718 SmallVector<EVT, 4> RetTys;
4719 RetTy = FTy->getReturnType();
4720 ComputeValueVTs(TLI, RetTy, RetTys);
4721 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4722 SmallVector<SDValue, 4> ReturnValues;
4723 unsigned CurReg = 0;
4724 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
4725 EVT VT = RetTys[I];
4726 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT);
4727 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT);
4728
4729 SDValue ReturnValue =
4730 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs,
4731 RegisterVT, VT, AssertOp);
4732 ReturnValues.push_back(ReturnValue);
4733 CurReg += NumRegs;
4734 }
4735
4736 setValue(CS.getInstruction(),
4737 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
4738 DAG.getVTList(&RetTys[0], RetTys.size()),
4739 &ReturnValues[0], ReturnValues.size()));
4740
4741 }
4742
4743 // As a special case, a null chain means that a tail call has been emitted and
4744 // the DAG root is already updated.
4745 if (Result.second.getNode())
4746 DAG.setRoot(Result.second);
4747 else
4748 HasTailCall = true;
4749
4750 if (LandingPad) {
4751 // Insert a label at the end of the invoke call to mark the try range. This
4752 // can be used to detect deletion of the invoke via the MachineModuleInfo.
4753 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
4754 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel));
4755
4756 // Inform MachineModuleInfo of range.
4757 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
4758 }
4759 }
4760
4761 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
4762 /// value is equal or not-equal to zero.
IsOnlyUsedInZeroEqualityComparison(const Value * V)4763 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
4764 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end();
4765 UI != E; ++UI) {
4766 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI))
4767 if (IC->isEquality())
4768 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
4769 if (C->isNullValue())
4770 continue;
4771 // Unknown instruction.
4772 return false;
4773 }
4774 return true;
4775 }
4776
getMemCmpLoad(const Value * PtrVal,MVT LoadVT,const Type * LoadTy,SelectionDAGBuilder & Builder)4777 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
4778 const Type *LoadTy,
4779 SelectionDAGBuilder &Builder) {
4780
4781 // Check to see if this load can be trivially constant folded, e.g. if the
4782 // input is from a string literal.
4783 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
4784 // Cast pointer to the type we really want to load.
4785 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
4786 PointerType::getUnqual(LoadTy));
4787
4788 if (const Constant *LoadCst =
4789 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
4790 Builder.TD))
4791 return Builder.getValue(LoadCst);
4792 }
4793
4794 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
4795 // still constant memory, the input chain can be the entry node.
4796 SDValue Root;
4797 bool ConstantMemory = false;
4798
4799 // Do not serialize (non-volatile) loads of constant memory with anything.
4800 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
4801 Root = Builder.DAG.getEntryNode();
4802 ConstantMemory = true;
4803 } else {
4804 // Do not serialize non-volatile loads against each other.
4805 Root = Builder.DAG.getRoot();
4806 }
4807
4808 SDValue Ptr = Builder.getValue(PtrVal);
4809 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root,
4810 Ptr, PtrVal /*SrcValue*/, 0/*SVOffset*/,
4811 false /*volatile*/,
4812 false /*nontemporal*/, 1 /* align=1 */);
4813
4814 if (!ConstantMemory)
4815 Builder.PendingLoads.push_back(LoadVal.getValue(1));
4816 return LoadVal;
4817 }
4818
4819
4820 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
4821 /// If so, return true and lower it, otherwise return false and it will be
4822 /// lowered like a normal call.
visitMemCmpCall(const CallInst & I)4823 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
4824 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
4825 if (I.getNumArgOperands() != 3)
4826 return false;
4827
4828 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
4829 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
4830 !I.getArgOperand(2)->getType()->isIntegerTy() ||
4831 !I.getType()->isIntegerTy())
4832 return false;
4833
4834 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2));
4835
4836 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
4837 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
4838 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) {
4839 bool ActuallyDoIt = true;
4840 MVT LoadVT;
4841 const Type *LoadTy;
4842 switch (Size->getZExtValue()) {
4843 default:
4844 LoadVT = MVT::Other;
4845 LoadTy = 0;
4846 ActuallyDoIt = false;
4847 break;
4848 case 2:
4849 LoadVT = MVT::i16;
4850 LoadTy = Type::getInt16Ty(Size->getContext());
4851 break;
4852 case 4:
4853 LoadVT = MVT::i32;
4854 LoadTy = Type::getInt32Ty(Size->getContext());
4855 break;
4856 case 8:
4857 LoadVT = MVT::i64;
4858 LoadTy = Type::getInt64Ty(Size->getContext());
4859 break;
4860 /*
4861 case 16:
4862 LoadVT = MVT::v4i32;
4863 LoadTy = Type::getInt32Ty(Size->getContext());
4864 LoadTy = VectorType::get(LoadTy, 4);
4865 break;
4866 */
4867 }
4868
4869 // This turns into unaligned loads. We only do this if the target natively
4870 // supports the MVT we'll be loading or if it is small enough (<= 4) that
4871 // we'll only produce a small number of byte loads.
4872
4873 // Require that we can find a legal MVT, and only do this if the target
4874 // supports unaligned loads of that type. Expanding into byte loads would
4875 // bloat the code.
4876 if (ActuallyDoIt && Size->getZExtValue() > 4) {
4877 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
4878 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
4879 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT))
4880 ActuallyDoIt = false;
4881 }
4882
4883 if (ActuallyDoIt) {
4884 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
4885 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
4886
4887 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal,
4888 ISD::SETNE);
4889 EVT CallVT = TLI.getValueType(I.getType(), true);
4890 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT));
4891 return true;
4892 }
4893 }
4894
4895
4896 return false;
4897 }
4898
4899
visitCall(const CallInst & I)4900 void SelectionDAGBuilder::visitCall(const CallInst &I) {
4901 // Handle inline assembly differently.
4902 if (isa<InlineAsm>(I.getCalledValue())) {
4903 visitInlineAsm(&I);
4904 return;
4905 }
4906
4907 const char *RenameFn = 0;
4908 if (Function *F = I.getCalledFunction()) {
4909 if (F->isDeclaration()) {
4910 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
4911 if (unsigned IID = II->getIntrinsicID(F)) {
4912 RenameFn = visitIntrinsicCall(I, IID);
4913 if (!RenameFn)
4914 return;
4915 }
4916 }
4917 if (unsigned IID = F->getIntrinsicID()) {
4918 RenameFn = visitIntrinsicCall(I, IID);
4919 if (!RenameFn)
4920 return;
4921 }
4922 }
4923
4924 // Check for well-known libc/libm calls. If the function is internal, it
4925 // can't be a library call.
4926 if (!F->hasLocalLinkage() && F->hasName()) {
4927 StringRef Name = F->getName();
4928 if (Name == "copysign" || Name == "copysignf" || Name == "copysignl") {
4929 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
4930 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
4931 I.getType() == I.getArgOperand(0)->getType() &&
4932 I.getType() == I.getArgOperand(1)->getType()) {
4933 SDValue LHS = getValue(I.getArgOperand(0));
4934 SDValue RHS = getValue(I.getArgOperand(1));
4935 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
4936 LHS.getValueType(), LHS, RHS));
4937 return;
4938 }
4939 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") {
4940 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
4941 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
4942 I.getType() == I.getArgOperand(0)->getType()) {
4943 SDValue Tmp = getValue(I.getArgOperand(0));
4944 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
4945 Tmp.getValueType(), Tmp));
4946 return;
4947 }
4948 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") {
4949 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
4950 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
4951 I.getType() == I.getArgOperand(0)->getType() &&
4952 I.onlyReadsMemory()) {
4953 SDValue Tmp = getValue(I.getArgOperand(0));
4954 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
4955 Tmp.getValueType(), Tmp));
4956 return;
4957 }
4958 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") {
4959 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
4960 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
4961 I.getType() == I.getArgOperand(0)->getType() &&
4962 I.onlyReadsMemory()) {
4963 SDValue Tmp = getValue(I.getArgOperand(0));
4964 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
4965 Tmp.getValueType(), Tmp));
4966 return;
4967 }
4968 } else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") {
4969 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
4970 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
4971 I.getType() == I.getArgOperand(0)->getType() &&
4972 I.onlyReadsMemory()) {
4973 SDValue Tmp = getValue(I.getArgOperand(0));
4974 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(),
4975 Tmp.getValueType(), Tmp));
4976 return;
4977 }
4978 } else if (Name == "memcmp") {
4979 if (visitMemCmpCall(I))
4980 return;
4981 }
4982 }
4983 }
4984
4985 SDValue Callee;
4986 if (!RenameFn)
4987 Callee = getValue(I.getCalledValue());
4988 else
4989 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
4990
4991 // Check if we can potentially perform a tail call. More detailed checking is
4992 // be done within LowerCallTo, after more information about the call is known.
4993 LowerCallTo(&I, Callee, I.isTailCall());
4994 }
4995
4996 namespace llvm {
4997
4998 /// AsmOperandInfo - This contains information for each constraint that we are
4999 /// lowering.
5000 class LLVM_LIBRARY_VISIBILITY SDISelAsmOperandInfo :
5001 public TargetLowering::AsmOperandInfo {
5002 public:
5003 /// CallOperand - If this is the result output operand or a clobber
5004 /// this is null, otherwise it is the incoming operand to the CallInst.
5005 /// This gets modified as the asm is processed.
5006 SDValue CallOperand;
5007
5008 /// AssignedRegs - If this is a register or register class operand, this
5009 /// contains the set of register corresponding to the operand.
5010 RegsForValue AssignedRegs;
5011
SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo & info)5012 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
5013 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
5014 }
5015
5016 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
5017 /// busy in OutputRegs/InputRegs.
MarkAllocatedRegs(bool isOutReg,bool isInReg,std::set<unsigned> & OutputRegs,std::set<unsigned> & InputRegs,const TargetRegisterInfo & TRI) const5018 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
5019 std::set<unsigned> &OutputRegs,
5020 std::set<unsigned> &InputRegs,
5021 const TargetRegisterInfo &TRI) const {
5022 if (isOutReg) {
5023 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
5024 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
5025 }
5026 if (isInReg) {
5027 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
5028 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
5029 }
5030 }
5031
5032 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5033 /// corresponds to. If there is no Value* for this operand, it returns
5034 /// MVT::Other.
getCallOperandValEVT(LLVMContext & Context,const TargetLowering & TLI,const TargetData * TD) const5035 EVT getCallOperandValEVT(LLVMContext &Context,
5036 const TargetLowering &TLI,
5037 const TargetData *TD) const {
5038 if (CallOperandVal == 0) return MVT::Other;
5039
5040 if (isa<BasicBlock>(CallOperandVal))
5041 return TLI.getPointerTy();
5042
5043 const llvm::Type *OpTy = CallOperandVal->getType();
5044
5045 // If this is an indirect operand, the operand is a pointer to the
5046 // accessed type.
5047 if (isIndirect) {
5048 const llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5049 if (!PtrTy)
5050 report_fatal_error("Indirect operand for inline asm not a pointer!");
5051 OpTy = PtrTy->getElementType();
5052 }
5053
5054 // If OpTy is not a single value, it may be a struct/union that we
5055 // can tile with integers.
5056 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5057 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
5058 switch (BitSize) {
5059 default: break;
5060 case 1:
5061 case 8:
5062 case 16:
5063 case 32:
5064 case 64:
5065 case 128:
5066 OpTy = IntegerType::get(Context, BitSize);
5067 break;
5068 }
5069 }
5070
5071 return TLI.getValueType(OpTy, true);
5072 }
5073
5074 private:
5075 /// MarkRegAndAliases - Mark the specified register and all aliases in the
5076 /// specified set.
MarkRegAndAliases(unsigned Reg,std::set<unsigned> & Regs,const TargetRegisterInfo & TRI)5077 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
5078 const TargetRegisterInfo &TRI) {
5079 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
5080 Regs.insert(Reg);
5081 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
5082 for (; *Aliases; ++Aliases)
5083 Regs.insert(*Aliases);
5084 }
5085 };
5086
5087 } // end llvm namespace.
5088
5089 /// isAllocatableRegister - If the specified register is safe to allocate,
5090 /// i.e. it isn't a stack pointer or some other special register, return the
5091 /// register class for the register. Otherwise, return null.
5092 static const TargetRegisterClass *
isAllocatableRegister(unsigned Reg,MachineFunction & MF,const TargetLowering & TLI,const TargetRegisterInfo * TRI)5093 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
5094 const TargetLowering &TLI,
5095 const TargetRegisterInfo *TRI) {
5096 EVT FoundVT = MVT::Other;
5097 const TargetRegisterClass *FoundRC = 0;
5098 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
5099 E = TRI->regclass_end(); RCI != E; ++RCI) {
5100 EVT ThisVT = MVT::Other;
5101
5102 const TargetRegisterClass *RC = *RCI;
5103 // If none of the value types for this register class are valid, we
5104 // can't use it. For example, 64-bit reg classes on 32-bit targets.
5105 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
5106 I != E; ++I) {
5107 if (TLI.isTypeLegal(*I)) {
5108 // If we have already found this register in a different register class,
5109 // choose the one with the largest VT specified. For example, on
5110 // PowerPC, we favor f64 register classes over f32.
5111 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
5112 ThisVT = *I;
5113 break;
5114 }
5115 }
5116 }
5117
5118 if (ThisVT == MVT::Other) continue;
5119
5120 // NOTE: This isn't ideal. In particular, this might allocate the
5121 // frame pointer in functions that need it (due to them not being taken
5122 // out of allocation, because a variable sized allocation hasn't been seen
5123 // yet). This is a slight code pessimization, but should still work.
5124 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
5125 E = RC->allocation_order_end(MF); I != E; ++I)
5126 if (*I == Reg) {
5127 // We found a matching register class. Keep looking at others in case
5128 // we find one with larger registers that this physreg is also in.
5129 FoundRC = RC;
5130 FoundVT = ThisVT;
5131 break;
5132 }
5133 }
5134 return FoundRC;
5135 }
5136
5137 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5138 /// specified operand. We prefer to assign virtual registers, to allow the
5139 /// register allocator to handle the assignment process. However, if the asm
5140 /// uses features that we can't model on machineinstrs, we have SDISel do the
5141 /// allocation. This produces generally horrible, but correct, code.
5142 ///
5143 /// OpInfo describes the operand.
5144 /// Input and OutputRegs are the set of already allocated physical registers.
5145 ///
5146 void SelectionDAGBuilder::
GetRegistersForValue(SDISelAsmOperandInfo & OpInfo,std::set<unsigned> & OutputRegs,std::set<unsigned> & InputRegs)5147 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
5148 std::set<unsigned> &OutputRegs,
5149 std::set<unsigned> &InputRegs) {
5150 LLVMContext &Context = FuncInfo.Fn->getContext();
5151
5152 // Compute whether this value requires an input register, an output register,
5153 // or both.
5154 bool isOutReg = false;
5155 bool isInReg = false;
5156 switch (OpInfo.Type) {
5157 case InlineAsm::isOutput:
5158 isOutReg = true;
5159
5160 // If there is an input constraint that matches this, we need to reserve
5161 // the input register so no other inputs allocate to it.
5162 isInReg = OpInfo.hasMatchingInput();
5163 break;
5164 case InlineAsm::isInput:
5165 isInReg = true;
5166 isOutReg = false;
5167 break;
5168 case InlineAsm::isClobber:
5169 isOutReg = true;
5170 isInReg = true;
5171 break;
5172 }
5173
5174
5175 MachineFunction &MF = DAG.getMachineFunction();
5176 SmallVector<unsigned, 4> Regs;
5177
5178 // If this is a constraint for a single physreg, or a constraint for a
5179 // register class, find it.
5180 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
5181 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5182 OpInfo.ConstraintVT);
5183
5184 unsigned NumRegs = 1;
5185 if (OpInfo.ConstraintVT != MVT::Other) {
5186 // If this is a FP input in an integer register (or visa versa) insert a bit
5187 // cast of the input value. More generally, handle any case where the input
5188 // value disagrees with the register class we plan to stick this in.
5189 if (OpInfo.Type == InlineAsm::isInput &&
5190 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5191 // Try to convert to the first EVT that the reg class contains. If the
5192 // types are identical size, use a bitcast to convert (e.g. two differing
5193 // vector types).
5194 EVT RegVT = *PhysReg.second->vt_begin();
5195 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
5196 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5197 RegVT, OpInfo.CallOperand);
5198 OpInfo.ConstraintVT = RegVT;
5199 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5200 // If the input is a FP value and we want it in FP registers, do a
5201 // bitcast to the corresponding integer type. This turns an f64 value
5202 // into i64, which can be passed with two i32 values on a 32-bit
5203 // machine.
5204 RegVT = EVT::getIntegerVT(Context,
5205 OpInfo.ConstraintVT.getSizeInBits());
5206 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5207 RegVT, OpInfo.CallOperand);
5208 OpInfo.ConstraintVT = RegVT;
5209 }
5210 }
5211
5212 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5213 }
5214
5215 EVT RegVT;
5216 EVT ValueVT = OpInfo.ConstraintVT;
5217
5218 // If this is a constraint for a specific physical register, like {r17},
5219 // assign it now.
5220 if (unsigned AssignedReg = PhysReg.first) {
5221 const TargetRegisterClass *RC = PhysReg.second;
5222 if (OpInfo.ConstraintVT == MVT::Other)
5223 ValueVT = *RC->vt_begin();
5224
5225 // Get the actual register value type. This is important, because the user
5226 // may have asked for (e.g.) the AX register in i32 type. We need to
5227 // remember that AX is actually i16 to get the right extension.
5228 RegVT = *RC->vt_begin();
5229
5230 // This is a explicit reference to a physical register.
5231 Regs.push_back(AssignedReg);
5232
5233 // If this is an expanded reference, add the rest of the regs to Regs.
5234 if (NumRegs != 1) {
5235 TargetRegisterClass::iterator I = RC->begin();
5236 for (; *I != AssignedReg; ++I)
5237 assert(I != RC->end() && "Didn't find reg!");
5238
5239 // Already added the first reg.
5240 --NumRegs; ++I;
5241 for (; NumRegs; --NumRegs, ++I) {
5242 assert(I != RC->end() && "Ran out of registers to allocate!");
5243 Regs.push_back(*I);
5244 }
5245 }
5246
5247 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5248 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5249 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5250 return;
5251 }
5252
5253 // Otherwise, if this was a reference to an LLVM register class, create vregs
5254 // for this reference.
5255 if (const TargetRegisterClass *RC = PhysReg.second) {
5256 RegVT = *RC->vt_begin();
5257 if (OpInfo.ConstraintVT == MVT::Other)
5258 ValueVT = RegVT;
5259
5260 // Create the appropriate number of virtual registers.
5261 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5262 for (; NumRegs; --NumRegs)
5263 Regs.push_back(RegInfo.createVirtualRegister(RC));
5264
5265 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5266 return;
5267 }
5268
5269 // This is a reference to a register class that doesn't directly correspond
5270 // to an LLVM register class. Allocate NumRegs consecutive, available,
5271 // registers from the class.
5272 std::vector<unsigned> RegClassRegs
5273 = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
5274 OpInfo.ConstraintVT);
5275
5276 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5277 unsigned NumAllocated = 0;
5278 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
5279 unsigned Reg = RegClassRegs[i];
5280 // See if this register is available.
5281 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
5282 (isInReg && InputRegs.count(Reg))) { // Already used.
5283 // Make sure we find consecutive registers.
5284 NumAllocated = 0;
5285 continue;
5286 }
5287
5288 // Check to see if this register is allocatable (i.e. don't give out the
5289 // stack pointer).
5290 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI);
5291 if (!RC) { // Couldn't allocate this register.
5292 // Reset NumAllocated to make sure we return consecutive registers.
5293 NumAllocated = 0;
5294 continue;
5295 }
5296
5297 // Okay, this register is good, we can use it.
5298 ++NumAllocated;
5299
5300 // If we allocated enough consecutive registers, succeed.
5301 if (NumAllocated == NumRegs) {
5302 unsigned RegStart = (i-NumAllocated)+1;
5303 unsigned RegEnd = i+1;
5304 // Mark all of the allocated registers used.
5305 for (unsigned i = RegStart; i != RegEnd; ++i)
5306 Regs.push_back(RegClassRegs[i]);
5307
5308 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(),
5309 OpInfo.ConstraintVT);
5310 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5311 return;
5312 }
5313 }
5314
5315 // Otherwise, we couldn't allocate enough registers for this.
5316 }
5317
5318 /// visitInlineAsm - Handle a call to an InlineAsm object.
5319 ///
visitInlineAsm(ImmutableCallSite CS)5320 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5321 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5322
5323 /// ConstraintOperands - Information about all of the constraints.
5324 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
5325
5326 std::set<unsigned> OutputRegs, InputRegs;
5327
5328 // Do a prepass over the constraints, canonicalizing them, and building up the
5329 // ConstraintOperands list.
5330 std::vector<InlineAsm::ConstraintInfo>
5331 ConstraintInfos = IA->ParseConstraints();
5332
5333 bool hasMemory = hasInlineAsmMemConstraint(ConstraintInfos, TLI);
5334
5335 SDValue Chain, Flag;
5336
5337 // We won't need to flush pending loads if this asm doesn't touch
5338 // memory and is nonvolatile.
5339 if (hasMemory || IA->hasSideEffects())
5340 Chain = getRoot();
5341 else
5342 Chain = DAG.getRoot();
5343
5344 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5345 unsigned ResNo = 0; // ResNo - The result number of the next output.
5346 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5347 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
5348 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5349
5350 EVT OpVT = MVT::Other;
5351
5352 // Compute the value type for each operand.
5353 switch (OpInfo.Type) {
5354 case InlineAsm::isOutput:
5355 // Indirect outputs just consume an argument.
5356 if (OpInfo.isIndirect) {
5357 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5358 break;
5359 }
5360
5361 // The return value of the call is this value. As such, there is no
5362 // corresponding argument.
5363 assert(!CS.getType()->isVoidTy() &&
5364 "Bad inline asm!");
5365 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
5366 OpVT = TLI.getValueType(STy->getElementType(ResNo));
5367 } else {
5368 assert(ResNo == 0 && "Asm only has one result!");
5369 OpVT = TLI.getValueType(CS.getType());
5370 }
5371 ++ResNo;
5372 break;
5373 case InlineAsm::isInput:
5374 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5375 break;
5376 case InlineAsm::isClobber:
5377 // Nothing to do.
5378 break;
5379 }
5380
5381 // If this is an input or an indirect output, process the call argument.
5382 // BasicBlocks are labels, currently appearing only in asm's.
5383 if (OpInfo.CallOperandVal) {
5384 // Strip bitcasts, if any. This mostly comes up for functions.
5385 OpInfo.CallOperandVal = OpInfo.CallOperandVal->stripPointerCasts();
5386
5387 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5388 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5389 } else {
5390 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5391 }
5392
5393 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD);
5394 }
5395
5396 OpInfo.ConstraintVT = OpVT;
5397 }
5398
5399 // Second pass over the constraints: compute which constraint option to use
5400 // and assign registers to constraints that want a specific physreg.
5401 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5402 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5403
5404 // If this is an output operand with a matching input operand, look up the
5405 // matching input. If their types mismatch, e.g. one is an integer, the
5406 // other is floating point, or their sizes are different, flag it as an
5407 // error.
5408 if (OpInfo.hasMatchingInput()) {
5409 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5410
5411 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5412 if ((OpInfo.ConstraintVT.isInteger() !=
5413 Input.ConstraintVT.isInteger()) ||
5414 (OpInfo.ConstraintVT.getSizeInBits() !=
5415 Input.ConstraintVT.getSizeInBits())) {
5416 report_fatal_error("Unsupported asm: input constraint"
5417 " with a matching output constraint of"
5418 " incompatible type!");
5419 }
5420 Input.ConstraintVT = OpInfo.ConstraintVT;
5421 }
5422 }
5423
5424 // Compute the constraint code and ConstraintType to use.
5425 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
5426
5427 // If this is a memory input, and if the operand is not indirect, do what we
5428 // need to to provide an address for the memory input.
5429 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5430 !OpInfo.isIndirect) {
5431 assert(OpInfo.Type == InlineAsm::isInput &&
5432 "Can only indirectify direct input operands!");
5433
5434 // Memory operands really want the address of the value. If we don't have
5435 // an indirect input, put it in the constpool if we can, otherwise spill
5436 // it to a stack slot.
5437
5438 // If the operand is a float, integer, or vector constant, spill to a
5439 // constant pool entry to get its address.
5440 const Value *OpVal = OpInfo.CallOperandVal;
5441 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5442 isa<ConstantVector>(OpVal)) {
5443 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5444 TLI.getPointerTy());
5445 } else {
5446 // Otherwise, create a stack slot and emit a store to it before the
5447 // asm.
5448 const Type *Ty = OpVal->getType();
5449 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
5450 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
5451 MachineFunction &MF = DAG.getMachineFunction();
5452 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5453 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5454 Chain = DAG.getStore(Chain, getCurDebugLoc(),
5455 OpInfo.CallOperand, StackSlot, NULL, 0,
5456 false, false, 0);
5457 OpInfo.CallOperand = StackSlot;
5458 }
5459
5460 // There is no longer a Value* corresponding to this operand.
5461 OpInfo.CallOperandVal = 0;
5462
5463 // It is now an indirect operand.
5464 OpInfo.isIndirect = true;
5465 }
5466
5467 // If this constraint is for a specific register, allocate it before
5468 // anything else.
5469 if (OpInfo.ConstraintType == TargetLowering::C_Register)
5470 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5471 }
5472
5473 ConstraintInfos.clear();
5474
5475 // Second pass - Loop over all of the operands, assigning virtual or physregs
5476 // to register class operands.
5477 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5478 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5479
5480 // C_Register operands have already been allocated, Other/Memory don't need
5481 // to be.
5482 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
5483 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5484 }
5485
5486 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
5487 std::vector<SDValue> AsmNodeOperands;
5488 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
5489 AsmNodeOperands.push_back(
5490 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
5491 TLI.getPointerTy()));
5492
5493 // If we have a !srcloc metadata node associated with it, we want to attach
5494 // this to the ultimately generated inline asm machineinstr. To do this, we
5495 // pass in the third operand as this (potentially null) inline asm MDNode.
5496 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
5497 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
5498
5499 // Remember the AlignStack bit as operand 3.
5500 AsmNodeOperands.push_back(DAG.getTargetConstant(IA->isAlignStack() ? 1 : 0,
5501 MVT::i1));
5502
5503 // Loop over all of the inputs, copying the operand values into the
5504 // appropriate registers and processing the output regs.
5505 RegsForValue RetValRegs;
5506
5507 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
5508 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
5509
5510 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5511 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5512
5513 switch (OpInfo.Type) {
5514 case InlineAsm::isOutput: {
5515 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
5516 OpInfo.ConstraintType != TargetLowering::C_Register) {
5517 // Memory output, or 'other' output (e.g. 'X' constraint).
5518 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
5519
5520 // Add information to the INLINEASM node to know about this output.
5521 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
5522 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
5523 TLI.getPointerTy()));
5524 AsmNodeOperands.push_back(OpInfo.CallOperand);
5525 break;
5526 }
5527
5528 // Otherwise, this is a register or register class output.
5529
5530 // Copy the output from the appropriate register. Find a register that
5531 // we can use.
5532 if (OpInfo.AssignedRegs.Regs.empty())
5533 report_fatal_error("Couldn't allocate output reg for constraint '" +
5534 Twine(OpInfo.ConstraintCode) + "'!");
5535
5536 // If this is an indirect operand, store through the pointer after the
5537 // asm.
5538 if (OpInfo.isIndirect) {
5539 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
5540 OpInfo.CallOperandVal));
5541 } else {
5542 // This is the result value of the call.
5543 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5544 // Concatenate this output onto the outputs list.
5545 RetValRegs.append(OpInfo.AssignedRegs);
5546 }
5547
5548 // Add information to the INLINEASM node to know that this register is
5549 // set.
5550 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
5551 InlineAsm::Kind_RegDefEarlyClobber :
5552 InlineAsm::Kind_RegDef,
5553 false,
5554 0,
5555 DAG,
5556 AsmNodeOperands);
5557 break;
5558 }
5559 case InlineAsm::isInput: {
5560 SDValue InOperandVal = OpInfo.CallOperand;
5561
5562 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
5563 // If this is required to match an output register we have already set,
5564 // just use its register.
5565 unsigned OperandNo = OpInfo.getMatchedOperand();
5566
5567 // Scan until we find the definition we already emitted of this operand.
5568 // When we find it, create a RegsForValue operand.
5569 unsigned CurOp = InlineAsm::Op_FirstOperand;
5570 for (; OperandNo; --OperandNo) {
5571 // Advance to the next operand.
5572 unsigned OpFlag =
5573 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5574 assert((InlineAsm::isRegDefKind(OpFlag) ||
5575 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
5576 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
5577 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
5578 }
5579
5580 unsigned OpFlag =
5581 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5582 if (InlineAsm::isRegDefKind(OpFlag) ||
5583 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
5584 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
5585 if (OpInfo.isIndirect) {
5586 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
5587 LLVMContext &Ctx = *DAG.getContext();
5588 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
5589 " don't know how to handle tied "
5590 "indirect register inputs");
5591 }
5592
5593 RegsForValue MatchedRegs;
5594 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
5595 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
5596 MatchedRegs.RegVTs.push_back(RegVT);
5597 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
5598 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
5599 i != e; ++i)
5600 MatchedRegs.Regs.push_back
5601 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)));
5602
5603 // Use the produced MatchedRegs object to
5604 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5605 Chain, &Flag);
5606 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
5607 true, OpInfo.getMatchedOperand(),
5608 DAG, AsmNodeOperands);
5609 break;
5610 }
5611
5612 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
5613 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
5614 "Unexpected number of operands");
5615 // Add information to the INLINEASM node to know about this input.
5616 // See InlineAsm.h isUseOperandTiedToDef.
5617 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
5618 OpInfo.getMatchedOperand());
5619 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
5620 TLI.getPointerTy()));
5621 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
5622 break;
5623 }
5624
5625 // Treat indirect 'X' constraint as memory.
5626 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
5627 OpInfo.isIndirect)
5628 OpInfo.ConstraintType = TargetLowering::C_Memory;
5629
5630 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
5631 std::vector<SDValue> Ops;
5632 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
5633 Ops, DAG);
5634 if (Ops.empty())
5635 report_fatal_error("Invalid operand for inline asm constraint '" +
5636 Twine(OpInfo.ConstraintCode) + "'!");
5637
5638 // Add information to the INLINEASM node to know about this input.
5639 unsigned ResOpType =
5640 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
5641 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5642 TLI.getPointerTy()));
5643 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
5644 break;
5645 }
5646
5647 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
5648 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
5649 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
5650 "Memory operands expect pointer values");
5651
5652 // Add information to the INLINEASM node to know about this input.
5653 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
5654 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5655 TLI.getPointerTy()));
5656 AsmNodeOperands.push_back(InOperandVal);
5657 break;
5658 }
5659
5660 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
5661 OpInfo.ConstraintType == TargetLowering::C_Register) &&
5662 "Unknown constraint type!");
5663 assert(!OpInfo.isIndirect &&
5664 "Don't know how to handle indirect register inputs yet!");
5665
5666 // Copy the input into the appropriate registers.
5667 if (OpInfo.AssignedRegs.Regs.empty() ||
5668 !OpInfo.AssignedRegs.areValueTypesLegal(TLI))
5669 report_fatal_error("Couldn't allocate input reg for constraint '" +
5670 Twine(OpInfo.ConstraintCode) + "'!");
5671
5672 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5673 Chain, &Flag);
5674
5675 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
5676 DAG, AsmNodeOperands);
5677 break;
5678 }
5679 case InlineAsm::isClobber: {
5680 // Add the clobbered value to the operand list, so that the register
5681 // allocator is aware that the physreg got clobbered.
5682 if (!OpInfo.AssignedRegs.Regs.empty())
5683 OpInfo.AssignedRegs.AddInlineAsmOperands(
5684 InlineAsm::Kind_RegDefEarlyClobber,
5685 false, 0, DAG,
5686 AsmNodeOperands);
5687 break;
5688 }
5689 }
5690 }
5691
5692 // Finish up input operands. Set the input chain and add the flag last.
5693 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
5694 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
5695
5696 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
5697 DAG.getVTList(MVT::Other, MVT::Flag),
5698 &AsmNodeOperands[0], AsmNodeOperands.size());
5699 Flag = Chain.getValue(1);
5700
5701 // If this asm returns a register value, copy the result from that register
5702 // and set it as the value of the call.
5703 if (!RetValRegs.Regs.empty()) {
5704 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
5705 Chain, &Flag);
5706
5707 // FIXME: Why don't we do this for inline asms with MRVs?
5708 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
5709 EVT ResultType = TLI.getValueType(CS.getType());
5710
5711 // If any of the results of the inline asm is a vector, it may have the
5712 // wrong width/num elts. This can happen for register classes that can
5713 // contain multiple different value types. The preg or vreg allocated may
5714 // not have the same VT as was expected. Convert it to the right type
5715 // with bit_convert.
5716 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
5717 Val = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5718 ResultType, Val);
5719
5720 } else if (ResultType != Val.getValueType() &&
5721 ResultType.isInteger() && Val.getValueType().isInteger()) {
5722 // If a result value was tied to an input value, the computed result may
5723 // have a wider width than the expected result. Extract the relevant
5724 // portion.
5725 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
5726 }
5727
5728 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
5729 }
5730
5731 setValue(CS.getInstruction(), Val);
5732 // Don't need to use this as a chain in this case.
5733 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
5734 return;
5735 }
5736
5737 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
5738
5739 // Process indirect outputs, first output all of the flagged copies out of
5740 // physregs.
5741 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
5742 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
5743 const Value *Ptr = IndirectStoresToEmit[i].second;
5744 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
5745 Chain, &Flag);
5746 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
5747 }
5748
5749 // Emit the non-flagged stores from the physregs.
5750 SmallVector<SDValue, 8> OutChains;
5751 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
5752 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(),
5753 StoresToEmit[i].first,
5754 getValue(StoresToEmit[i].second),
5755 StoresToEmit[i].second, 0,
5756 false, false, 0);
5757 OutChains.push_back(Val);
5758 }
5759
5760 if (!OutChains.empty())
5761 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
5762 &OutChains[0], OutChains.size());
5763
5764 DAG.setRoot(Chain);
5765 }
5766
visitVAStart(const CallInst & I)5767 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
5768 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
5769 MVT::Other, getRoot(),
5770 getValue(I.getArgOperand(0)),
5771 DAG.getSrcValue(I.getArgOperand(0))));
5772 }
5773
visitVAArg(const VAArgInst & I)5774 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
5775 const TargetData &TD = *TLI.getTargetData();
5776 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
5777 getRoot(), getValue(I.getOperand(0)),
5778 DAG.getSrcValue(I.getOperand(0)),
5779 TD.getABITypeAlignment(I.getType()));
5780 setValue(&I, V);
5781 DAG.setRoot(V.getValue(1));
5782 }
5783
visitVAEnd(const CallInst & I)5784 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
5785 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
5786 MVT::Other, getRoot(),
5787 getValue(I.getArgOperand(0)),
5788 DAG.getSrcValue(I.getArgOperand(0))));
5789 }
5790
visitVACopy(const CallInst & I)5791 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
5792 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
5793 MVT::Other, getRoot(),
5794 getValue(I.getArgOperand(0)),
5795 getValue(I.getArgOperand(1)),
5796 DAG.getSrcValue(I.getArgOperand(0)),
5797 DAG.getSrcValue(I.getArgOperand(1))));
5798 }
5799
5800 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
5801 /// implementation, which just calls LowerCall.
5802 /// FIXME: When all targets are
5803 /// migrated to using LowerCall, this hook should be integrated into SDISel.
5804 std::pair<SDValue, SDValue>
LowerCallTo(SDValue Chain,const Type * RetTy,bool RetSExt,bool RetZExt,bool isVarArg,bool isInreg,unsigned NumFixedArgs,CallingConv::ID CallConv,bool isTailCall,bool isReturnValueUsed,SDValue Callee,ArgListTy & Args,SelectionDAG & DAG,DebugLoc dl) const5805 TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
5806 bool RetSExt, bool RetZExt, bool isVarArg,
5807 bool isInreg, unsigned NumFixedArgs,
5808 CallingConv::ID CallConv, bool isTailCall,
5809 bool isReturnValueUsed,
5810 SDValue Callee,
5811 ArgListTy &Args, SelectionDAG &DAG,
5812 DebugLoc dl) const {
5813 // Handle all of the outgoing arguments.
5814 SmallVector<ISD::OutputArg, 32> Outs;
5815 SmallVector<SDValue, 32> OutVals;
5816 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
5817 SmallVector<EVT, 4> ValueVTs;
5818 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
5819 for (unsigned Value = 0, NumValues = ValueVTs.size();
5820 Value != NumValues; ++Value) {
5821 EVT VT = ValueVTs[Value];
5822 const Type *ArgTy = VT.getTypeForEVT(RetTy->getContext());
5823 SDValue Op = SDValue(Args[i].Node.getNode(),
5824 Args[i].Node.getResNo() + Value);
5825 ISD::ArgFlagsTy Flags;
5826 unsigned OriginalAlignment =
5827 getTargetData()->getABITypeAlignment(ArgTy);
5828
5829 if (Args[i].isZExt)
5830 Flags.setZExt();
5831 if (Args[i].isSExt)
5832 Flags.setSExt();
5833 if (Args[i].isInReg)
5834 Flags.setInReg();
5835 if (Args[i].isSRet)
5836 Flags.setSRet();
5837 if (Args[i].isByVal) {
5838 Flags.setByVal();
5839 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
5840 const Type *ElementTy = Ty->getElementType();
5841 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
5842 unsigned FrameSize = getTargetData()->getTypeAllocSize(ElementTy);
5843 // For ByVal, alignment should come from FE. BE will guess if this
5844 // info is not there but there are cases it cannot get right.
5845 if (Args[i].Alignment)
5846 FrameAlign = Args[i].Alignment;
5847 Flags.setByValAlign(FrameAlign);
5848 Flags.setByValSize(FrameSize);
5849 }
5850 if (Args[i].isNest)
5851 Flags.setNest();
5852 Flags.setOrigAlign(OriginalAlignment);
5853
5854 EVT PartVT = getRegisterType(RetTy->getContext(), VT);
5855 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT);
5856 SmallVector<SDValue, 4> Parts(NumParts);
5857 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
5858
5859 if (Args[i].isSExt)
5860 ExtendKind = ISD::SIGN_EXTEND;
5861 else if (Args[i].isZExt)
5862 ExtendKind = ISD::ZERO_EXTEND;
5863
5864 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts,
5865 PartVT, ExtendKind);
5866
5867 for (unsigned j = 0; j != NumParts; ++j) {
5868 // if it isn't first piece, alignment must be 1
5869 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(),
5870 i < NumFixedArgs);
5871 if (NumParts > 1 && j == 0)
5872 MyFlags.Flags.setSplit();
5873 else if (j != 0)
5874 MyFlags.Flags.setOrigAlign(1);
5875
5876 Outs.push_back(MyFlags);
5877 OutVals.push_back(Parts[j]);
5878 }
5879 }
5880 }
5881
5882 // Handle the incoming return values from the call.
5883 SmallVector<ISD::InputArg, 32> Ins;
5884 SmallVector<EVT, 4> RetTys;
5885 ComputeValueVTs(*this, RetTy, RetTys);
5886 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5887 EVT VT = RetTys[I];
5888 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
5889 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
5890 for (unsigned i = 0; i != NumRegs; ++i) {
5891 ISD::InputArg MyFlags;
5892 MyFlags.VT = RegisterVT;
5893 MyFlags.Used = isReturnValueUsed;
5894 if (RetSExt)
5895 MyFlags.Flags.setSExt();
5896 if (RetZExt)
5897 MyFlags.Flags.setZExt();
5898 if (isInreg)
5899 MyFlags.Flags.setInReg();
5900 Ins.push_back(MyFlags);
5901 }
5902 }
5903
5904 SmallVector<SDValue, 4> InVals;
5905 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall,
5906 Outs, OutVals, Ins, dl, DAG, InVals);
5907
5908 // Verify that the target's LowerCall behaved as expected.
5909 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
5910 "LowerCall didn't return a valid chain!");
5911 assert((!isTailCall || InVals.empty()) &&
5912 "LowerCall emitted a return value for a tail call!");
5913 assert((isTailCall || InVals.size() == Ins.size()) &&
5914 "LowerCall didn't emit the correct number of values!");
5915
5916 // For a tail call, the return value is merely live-out and there aren't
5917 // any nodes in the DAG representing it. Return a special value to
5918 // indicate that a tail call has been emitted and no more Instructions
5919 // should be processed in the current block.
5920 if (isTailCall) {
5921 DAG.setRoot(Chain);
5922 return std::make_pair(SDValue(), SDValue());
5923 }
5924
5925 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
5926 assert(InVals[i].getNode() &&
5927 "LowerCall emitted a null value!");
5928 assert(Ins[i].VT == InVals[i].getValueType() &&
5929 "LowerCall emitted a value with the wrong type!");
5930 });
5931
5932 // Collect the legal value parts into potentially illegal values
5933 // that correspond to the original function's return values.
5934 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5935 if (RetSExt)
5936 AssertOp = ISD::AssertSext;
5937 else if (RetZExt)
5938 AssertOp = ISD::AssertZext;
5939 SmallVector<SDValue, 4> ReturnValues;
5940 unsigned CurReg = 0;
5941 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5942 EVT VT = RetTys[I];
5943 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
5944 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
5945
5946 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg],
5947 NumRegs, RegisterVT, VT,
5948 AssertOp));
5949 CurReg += NumRegs;
5950 }
5951
5952 // For a function returning void, there is no return value. We can't create
5953 // such a node, so we just return a null return value in that case. In
5954 // that case, nothing will actualy look at the value.
5955 if (ReturnValues.empty())
5956 return std::make_pair(SDValue(), Chain);
5957
5958 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
5959 DAG.getVTList(&RetTys[0], RetTys.size()),
5960 &ReturnValues[0], ReturnValues.size());
5961 return std::make_pair(Res, Chain);
5962 }
5963
LowerOperationWrapper(SDNode * N,SmallVectorImpl<SDValue> & Results,SelectionDAG & DAG) const5964 void TargetLowering::LowerOperationWrapper(SDNode *N,
5965 SmallVectorImpl<SDValue> &Results,
5966 SelectionDAG &DAG) const {
5967 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
5968 if (Res.getNode())
5969 Results.push_back(Res);
5970 }
5971
LowerOperation(SDValue Op,SelectionDAG & DAG) const5972 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
5973 llvm_unreachable("LowerOperation not implemented for this target!");
5974 return SDValue();
5975 }
5976
5977 void
CopyValueToVirtualRegister(const Value * V,unsigned Reg)5978 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
5979 SDValue Op = getNonRegisterValue(V);
5980 assert((Op.getOpcode() != ISD::CopyFromReg ||
5981 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
5982 "Copy from a reg to the same reg!");
5983 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
5984
5985 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
5986 SDValue Chain = DAG.getEntryNode();
5987 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
5988 PendingExports.push_back(Chain);
5989 }
5990
5991 #include "llvm/CodeGen/SelectionDAGISel.h"
5992
LowerArguments(const BasicBlock * LLVMBB)5993 void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) {
5994 // If this is the entry block, emit arguments.
5995 const Function &F = *LLVMBB->getParent();
5996 SelectionDAG &DAG = SDB->DAG;
5997 DebugLoc dl = SDB->getCurDebugLoc();
5998 const TargetData *TD = TLI.getTargetData();
5999 SmallVector<ISD::InputArg, 16> Ins;
6000
6001 // Check whether the function can return without sret-demotion.
6002 SmallVector<ISD::OutputArg, 4> Outs;
6003 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
6004 Outs, TLI);
6005
6006 if (!FuncInfo->CanLowerReturn) {
6007 // Put in an sret pointer parameter before all the other parameters.
6008 SmallVector<EVT, 1> ValueVTs;
6009 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6010
6011 // NOTE: Assuming that a pointer will never break down to more than one VT
6012 // or one register.
6013 ISD::ArgFlagsTy Flags;
6014 Flags.setSRet();
6015 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]);
6016 ISD::InputArg RetArg(Flags, RegisterVT, true);
6017 Ins.push_back(RetArg);
6018 }
6019
6020 // Set up the incoming argument description vector.
6021 unsigned Idx = 1;
6022 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
6023 I != E; ++I, ++Idx) {
6024 SmallVector<EVT, 4> ValueVTs;
6025 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6026 bool isArgValueUsed = !I->use_empty();
6027 for (unsigned Value = 0, NumValues = ValueVTs.size();
6028 Value != NumValues; ++Value) {
6029 EVT VT = ValueVTs[Value];
6030 const Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
6031 ISD::ArgFlagsTy Flags;
6032 unsigned OriginalAlignment =
6033 TD->getABITypeAlignment(ArgTy);
6034
6035 if (F.paramHasAttr(Idx, Attribute::ZExt))
6036 Flags.setZExt();
6037 if (F.paramHasAttr(Idx, Attribute::SExt))
6038 Flags.setSExt();
6039 if (F.paramHasAttr(Idx, Attribute::InReg))
6040 Flags.setInReg();
6041 if (F.paramHasAttr(Idx, Attribute::StructRet))
6042 Flags.setSRet();
6043 if (F.paramHasAttr(Idx, Attribute::ByVal)) {
6044 Flags.setByVal();
6045 const PointerType *Ty = cast<PointerType>(I->getType());
6046 const Type *ElementTy = Ty->getElementType();
6047 unsigned FrameAlign = TLI.getByValTypeAlignment(ElementTy);
6048 unsigned FrameSize = TD->getTypeAllocSize(ElementTy);
6049 // For ByVal, alignment should be passed from FE. BE will guess if
6050 // this info is not there but there are cases it cannot get right.
6051 if (F.getParamAlignment(Idx))
6052 FrameAlign = F.getParamAlignment(Idx);
6053 Flags.setByValAlign(FrameAlign);
6054 Flags.setByValSize(FrameSize);
6055 }
6056 if (F.paramHasAttr(Idx, Attribute::Nest))
6057 Flags.setNest();
6058 Flags.setOrigAlign(OriginalAlignment);
6059
6060 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6061 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6062 for (unsigned i = 0; i != NumRegs; ++i) {
6063 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed);
6064 if (NumRegs > 1 && i == 0)
6065 MyFlags.Flags.setSplit();
6066 // if it isn't first piece, alignment must be 1
6067 else if (i > 0)
6068 MyFlags.Flags.setOrigAlign(1);
6069 Ins.push_back(MyFlags);
6070 }
6071 }
6072 }
6073
6074 // Call the target to set up the argument values.
6075 SmallVector<SDValue, 8> InVals;
6076 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
6077 F.isVarArg(), Ins,
6078 dl, DAG, InVals);
6079
6080 // Verify that the target's LowerFormalArguments behaved as expected.
6081 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
6082 "LowerFormalArguments didn't return a valid chain!");
6083 assert(InVals.size() == Ins.size() &&
6084 "LowerFormalArguments didn't emit the correct number of values!");
6085 DEBUG({
6086 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6087 assert(InVals[i].getNode() &&
6088 "LowerFormalArguments emitted a null value!");
6089 assert(Ins[i].VT == InVals[i].getValueType() &&
6090 "LowerFormalArguments emitted a value with the wrong type!");
6091 }
6092 });
6093
6094 // Update the DAG with the new chain value resulting from argument lowering.
6095 DAG.setRoot(NewRoot);
6096
6097 // Set up the argument values.
6098 unsigned i = 0;
6099 Idx = 1;
6100 if (!FuncInfo->CanLowerReturn) {
6101 // Create a virtual register for the sret pointer, and put in a copy
6102 // from the sret argument into it.
6103 SmallVector<EVT, 1> ValueVTs;
6104 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6105 EVT VT = ValueVTs[0];
6106 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6107 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6108 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
6109 RegVT, VT, AssertOp);
6110
6111 MachineFunction& MF = SDB->DAG.getMachineFunction();
6112 MachineRegisterInfo& RegInfo = MF.getRegInfo();
6113 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT));
6114 FuncInfo->DemoteRegister = SRetReg;
6115 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(),
6116 SRetReg, ArgValue);
6117 DAG.setRoot(NewRoot);
6118
6119 // i indexes lowered arguments. Bump it past the hidden sret argument.
6120 // Idx indexes LLVM arguments. Don't touch it.
6121 ++i;
6122 }
6123
6124 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
6125 ++I, ++Idx) {
6126 SmallVector<SDValue, 4> ArgValues;
6127 SmallVector<EVT, 4> ValueVTs;
6128 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6129 unsigned NumValues = ValueVTs.size();
6130
6131 // If this argument is unused then remember its value. It is used to generate
6132 // debugging information.
6133 if (I->use_empty() && NumValues)
6134 SDB->setUnusedArgValue(I, InVals[i]);
6135
6136 for (unsigned Value = 0; Value != NumValues; ++Value) {
6137 EVT VT = ValueVTs[Value];
6138 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6139 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6140
6141 if (!I->use_empty()) {
6142 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6143 if (F.paramHasAttr(Idx, Attribute::SExt))
6144 AssertOp = ISD::AssertSext;
6145 else if (F.paramHasAttr(Idx, Attribute::ZExt))
6146 AssertOp = ISD::AssertZext;
6147
6148 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
6149 NumParts, PartVT, VT,
6150 AssertOp));
6151 }
6152
6153 i += NumParts;
6154 }
6155
6156 // Note down frame index for byval arguments.
6157 if (I->hasByValAttr() && !ArgValues.empty())
6158 if (FrameIndexSDNode *FI =
6159 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
6160 FuncInfo->setByValArgumentFrameIndex(I, FI->getIndex());
6161
6162 if (!I->use_empty()) {
6163 SDValue Res;
6164 if (!ArgValues.empty())
6165 Res = DAG.getMergeValues(&ArgValues[0], NumValues,
6166 SDB->getCurDebugLoc());
6167 SDB->setValue(I, Res);
6168
6169 // If this argument is live outside of the entry block, insert a copy from
6170 // whereever we got it to the vreg that other BB's will reference it as.
6171 SDB->CopyToExportRegsIfNeeded(I);
6172 }
6173 }
6174
6175 assert(i == InVals.size() && "Argument register count mismatch!");
6176
6177 // Finally, if the target has anything special to do, allow it to do so.
6178 // FIXME: this should insert code into the DAG!
6179 EmitFunctionEntryCode();
6180 }
6181
6182 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
6183 /// ensure constants are generated when needed. Remember the virtual registers
6184 /// that need to be added to the Machine PHI nodes as input. We cannot just
6185 /// directly add them, because expansion might result in multiple MBB's for one
6186 /// BB. As such, the start of the BB might correspond to a different MBB than
6187 /// the end.
6188 ///
6189 void
HandlePHINodesInSuccessorBlocks(const BasicBlock * LLVMBB)6190 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
6191 const TerminatorInst *TI = LLVMBB->getTerminator();
6192
6193 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
6194
6195 // Check successor nodes' PHI nodes that expect a constant to be available
6196 // from this block.
6197 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
6198 const BasicBlock *SuccBB = TI->getSuccessor(succ);
6199 if (!isa<PHINode>(SuccBB->begin())) continue;
6200 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
6201
6202 // If this terminator has multiple identical successors (common for
6203 // switches), only handle each succ once.
6204 if (!SuccsHandled.insert(SuccMBB)) continue;
6205
6206 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6207
6208 // At this point we know that there is a 1-1 correspondence between LLVM PHI
6209 // nodes and Machine PHI nodes, but the incoming operands have not been
6210 // emitted yet.
6211 for (BasicBlock::const_iterator I = SuccBB->begin();
6212 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
6213 // Ignore dead phi's.
6214 if (PN->use_empty()) continue;
6215
6216 unsigned Reg;
6217 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6218
6219 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
6220 unsigned &RegOut = ConstantsOut[C];
6221 if (RegOut == 0) {
6222 RegOut = FuncInfo.CreateRegs(C->getType());
6223 CopyValueToVirtualRegister(C, RegOut);
6224 }
6225 Reg = RegOut;
6226 } else {
6227 DenseMap<const Value *, unsigned>::iterator I =
6228 FuncInfo.ValueMap.find(PHIOp);
6229 if (I != FuncInfo.ValueMap.end())
6230 Reg = I->second;
6231 else {
6232 assert(isa<AllocaInst>(PHIOp) &&
6233 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
6234 "Didn't codegen value into a register!??");
6235 Reg = FuncInfo.CreateRegs(PHIOp->getType());
6236 CopyValueToVirtualRegister(PHIOp, Reg);
6237 }
6238 }
6239
6240 // Remember that this register needs to added to the machine PHI node as
6241 // the input for this MBB.
6242 SmallVector<EVT, 4> ValueVTs;
6243 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
6244 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
6245 EVT VT = ValueVTs[vti];
6246 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
6247 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
6248 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
6249 Reg += NumRegisters;
6250 }
6251 }
6252 }
6253 ConstantsOut.clear();
6254 }
6255