1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This header file implements the operating system Host concept.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "llvm/System/Host.h"
15 #include "llvm/Config/config.h"
16 #include <string.h>
17
18 // Include the platform-specific parts of this class.
19 #ifdef LLVM_ON_UNIX
20 #include "Unix/Host.inc"
21 #endif
22 #ifdef LLVM_ON_WIN32
23 #include "Win32/Host.inc"
24 #endif
25 #ifdef _MSC_VER
26 #include <intrin.h>
27 #endif
28
29 //===----------------------------------------------------------------------===//
30 //
31 // Implementations of the CPU detection routines
32 //
33 //===----------------------------------------------------------------------===//
34
35 using namespace llvm;
36
37 #if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
38 || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
39
40 /// GetX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
41 /// specified arguments. If we can't run cpuid on the host, return true.
GetX86CpuIDAndInfo(unsigned value,unsigned * rEAX,unsigned * rEBX,unsigned * rECX,unsigned * rEDX)42 static bool GetX86CpuIDAndInfo(unsigned value, unsigned *rEAX,
43 unsigned *rEBX, unsigned *rECX, unsigned *rEDX) {
44 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
45 #if defined(__GNUC__)
46 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
47 asm ("movq\t%%rbx, %%rsi\n\t"
48 "cpuid\n\t"
49 "xchgq\t%%rbx, %%rsi\n\t"
50 : "=a" (*rEAX),
51 "=S" (*rEBX),
52 "=c" (*rECX),
53 "=d" (*rEDX)
54 : "a" (value));
55 return false;
56 #elif defined(_MSC_VER)
57 int registers[4];
58 __cpuid(registers, value);
59 *rEAX = registers[0];
60 *rEBX = registers[1];
61 *rECX = registers[2];
62 *rEDX = registers[3];
63 return false;
64 #endif
65 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
66 #if defined(__GNUC__)
67 asm ("movl\t%%ebx, %%esi\n\t"
68 "cpuid\n\t"
69 "xchgl\t%%ebx, %%esi\n\t"
70 : "=a" (*rEAX),
71 "=S" (*rEBX),
72 "=c" (*rECX),
73 "=d" (*rEDX)
74 : "a" (value));
75 return false;
76 #elif defined(_MSC_VER)
77 __asm {
78 mov eax,value
79 cpuid
80 mov esi,rEAX
81 mov dword ptr [esi],eax
82 mov esi,rEBX
83 mov dword ptr [esi],ebx
84 mov esi,rECX
85 mov dword ptr [esi],ecx
86 mov esi,rEDX
87 mov dword ptr [esi],edx
88 }
89 return false;
90 #endif
91 #endif
92 return true;
93 }
94
DetectX86FamilyModel(unsigned EAX,unsigned & Family,unsigned & Model)95 static void DetectX86FamilyModel(unsigned EAX, unsigned &Family, unsigned &Model) {
96 Family = (EAX >> 8) & 0xf; // Bits 8 - 11
97 Model = (EAX >> 4) & 0xf; // Bits 4 - 7
98 if (Family == 6 || Family == 0xf) {
99 if (Family == 0xf)
100 // Examine extended family ID if family ID is F.
101 Family += (EAX >> 20) & 0xff; // Bits 20 - 27
102 // Examine extended model ID if family ID is 6 or F.
103 Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
104 }
105 }
106
getHostCPUName()107 std::string sys::getHostCPUName() {
108 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
109 if (GetX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX))
110 return "generic";
111 unsigned Family = 0;
112 unsigned Model = 0;
113 DetectX86FamilyModel(EAX, Family, Model);
114
115 GetX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
116 bool Em64T = (EDX >> 29) & 0x1;
117 bool HasSSE3 = (ECX & 0x1);
118
119 union {
120 unsigned u[3];
121 char c[12];
122 } text;
123
124 GetX86CpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1);
125 if (memcmp(text.c, "GenuineIntel", 12) == 0) {
126 switch (Family) {
127 case 3:
128 return "i386";
129 case 4:
130 switch (Model) {
131 case 0: // Intel486TM DX processors
132 case 1: // Intel486TM DX processors
133 case 2: // Intel486 SX processors
134 case 3: // Intel487TM processors, IntelDX2 OverDrive® processors,
135 // IntelDX2TM processors
136 case 4: // Intel486 SL processor
137 case 5: // IntelSX2TM processors
138 case 7: // Write-Back Enhanced IntelDX2 processors
139 case 8: // IntelDX4 OverDrive processors, IntelDX4TM processors
140 default: return "i486";
141 }
142 case 5:
143 switch (Model) {
144 case 1: // Pentium OverDrive processor for Pentium processor (60, 66),
145 // Pentium® processors (60, 66)
146 case 2: // Pentium OverDrive processor for Pentium processor (75, 90,
147 // 100, 120, 133), Pentium processors (75, 90, 100, 120, 133,
148 // 150, 166, 200)
149 case 3: // Pentium OverDrive processors for Intel486 processor-based
150 // systems
151 return "pentium";
152
153 case 4: // Pentium OverDrive processor with MMXTM technology for Pentium
154 // processor (75, 90, 100, 120, 133), Pentium processor with
155 // MMXTM technology (166, 200)
156 return "pentium-mmx";
157
158 default: return "pentium";
159 }
160 case 6:
161 switch (Model) {
162 case 1: // Pentium Pro processor
163 return "pentiumpro";
164
165 case 3: // Intel Pentium II OverDrive processor, Pentium II processor,
166 // model 03
167 case 5: // Pentium II processor, model 05, Pentium II Xeon processor,
168 // model 05, and Intel® Celeron® processor, model 05
169 case 6: // Celeron processor, model 06
170 return "pentium2";
171
172 case 7: // Pentium III processor, model 07, and Pentium III Xeon
173 // processor, model 07
174 case 8: // Pentium III processor, model 08, Pentium III Xeon processor,
175 // model 08, and Celeron processor, model 08
176 case 10: // Pentium III Xeon processor, model 0Ah
177 case 11: // Pentium III processor, model 0Bh
178 return "pentium3";
179
180 case 9: // Intel Pentium M processor, Intel Celeron M processor model 09.
181 case 13: // Intel Pentium M processor, Intel Celeron M processor, model
182 // 0Dh. All processors are manufactured using the 90 nm process.
183 return "pentium-m";
184
185 case 14: // Intel CoreTM Duo processor, Intel CoreTM Solo processor, model
186 // 0Eh. All processors are manufactured using the 65 nm process.
187 return "yonah";
188
189 case 15: // Intel CoreTM2 Duo processor, Intel CoreTM2 Duo mobile
190 // processor, Intel CoreTM2 Quad processor, Intel CoreTM2 Quad
191 // mobile processor, Intel CoreTM2 Extreme processor, Intel
192 // Pentium Dual-Core processor, Intel Xeon processor, model
193 // 0Fh. All processors are manufactured using the 65 nm process.
194 case 22: // Intel Celeron processor model 16h. All processors are
195 // manufactured using the 65 nm process
196 return "core2";
197
198 case 21: // Intel EP80579 Integrated Processor and Intel EP80579
199 // Integrated Processor with Intel QuickAssist Technology
200 return "i686"; // FIXME: ???
201
202 case 23: // Intel CoreTM2 Extreme processor, Intel Xeon processor, model
203 // 17h. All processors are manufactured using the 45 nm process.
204 //
205 // 45nm: Penryn , Wolfdale, Yorkfield (XE)
206 return "penryn";
207
208 case 26: // Intel Core i7 processor and Intel Xeon processor. All
209 // processors are manufactured using the 45 nm process.
210 case 29: // Intel Xeon processor MP. All processors are manufactured using
211 // the 45 nm process.
212 return "corei7";
213
214 case 28: // Intel Atom processor. All processors are manufactured using
215 // the 45 nm process
216 return "atom";
217
218 default: return "i686";
219 }
220 case 15: {
221 switch (Model) {
222 case 0: // Pentium 4 processor, Intel Xeon processor. All processors are
223 // model 00h and manufactured using the 0.18 micron process.
224 case 1: // Pentium 4 processor, Intel Xeon processor, Intel Xeon
225 // processor MP, and Intel Celeron processor. All processors are
226 // model 01h and manufactured using the 0.18 micron process.
227 case 2: // Pentium 4 processor, Mobile Intel Pentium 4 processor – M,
228 // Intel Xeon processor, Intel Xeon processor MP, Intel Celeron
229 // processor, and Mobile Intel Celeron processor. All processors
230 // are model 02h and manufactured using the 0.13 micron process.
231 return (Em64T) ? "x86-64" : "pentium4";
232
233 case 3: // Pentium 4 processor, Intel Xeon processor, Intel Celeron D
234 // processor. All processors are model 03h and manufactured using
235 // the 90 nm process.
236 case 4: // Pentium 4 processor, Pentium 4 processor Extreme Edition,
237 // Pentium D processor, Intel Xeon processor, Intel Xeon
238 // processor MP, Intel Celeron D processor. All processors are
239 // model 04h and manufactured using the 90 nm process.
240 case 6: // Pentium 4 processor, Pentium D processor, Pentium processor
241 // Extreme Edition, Intel Xeon processor, Intel Xeon processor
242 // MP, Intel Celeron D processor. All processors are model 06h
243 // and manufactured using the 65 nm process.
244 return (Em64T) ? "nocona" : "prescott";
245
246 default:
247 return (Em64T) ? "x86-64" : "pentium4";
248 }
249 }
250
251 default:
252 return "generic";
253 }
254 } else if (memcmp(text.c, "AuthenticAMD", 12) == 0) {
255 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There
256 // appears to be no way to generate the wide variety of AMD-specific targets
257 // from the information returned from CPUID.
258 switch (Family) {
259 case 4:
260 return "i486";
261 case 5:
262 switch (Model) {
263 case 6:
264 case 7: return "k6";
265 case 8: return "k6-2";
266 case 9:
267 case 13: return "k6-3";
268 default: return "pentium";
269 }
270 case 6:
271 switch (Model) {
272 case 4: return "athlon-tbird";
273 case 6:
274 case 7:
275 case 8: return "athlon-mp";
276 case 10: return "athlon-xp";
277 default: return "athlon";
278 }
279 case 15:
280 if (HasSSE3) {
281 return "k8-sse3";
282 } else {
283 switch (Model) {
284 case 1: return "opteron";
285 case 5: return "athlon-fx"; // also opteron
286 default: return "athlon64";
287 }
288 }
289 case 16:
290 return "amdfam10";
291 default:
292 return "generic";
293 }
294 }
295 return "generic";
296 }
297 #else
getHostCPUName()298 std::string sys::getHostCPUName() {
299 return "generic";
300 }
301 #endif
302
getHostCPUFeatures(StringMap<bool> & Features)303 bool sys::getHostCPUFeatures(StringMap<bool> &Features){
304 return false;
305 }
306