1`timescale 1ns / 1ps 2/* 3 * This software is Copyright (c) 2016 Denis Burykin 4 * [denis_burykin yahoo com], [denis-burykin2014 yandex ru] 5 * and it is hereby released to the general public under the following terms: 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted. 8 * 9 */ 10 11//********************************************************** 12// 13// Output FIFO (high-speed output). 14// 15//********************************************************** 16 17module output_fifo ( 18 input wr_clk, 19 input [15:0] din, 20 input wr_en, 21 output full, 22 23 input rd_clk, 24 output [15:0] dout, 25 input rd_en, 26 output empty, 27 input mode_limit, 28 input reg_output_limit, 29 output [15:0] output_limit, 30 output output_limit_not_done 31 ); 32 33 // 34 // output_limit_fifo (one is able to limit output) is unable for asynchronous operation. 35 // Because of that, a small asynchronous FIFO is prepend. 36 // 37 38 // fifo_16x64: 39 // IP Coregen -> FIFO Generator 40 // Independent Clocks - Distributed RAM 41 // First Word Fall Through 42 // width 16, depth 64 43 // Reset: off 44 // 45 wire [15:0] data_stage2; 46 fifo_16x64 fifo_output1( 47 .wr_clk(wr_clk), 48 .din(din), 49 .wr_en(wr_en), 50 .full(full), 51 52 .rd_clk(rd_clk), 53 .dout(data_stage2), 54 .rd_en(rd_en_stage2), 55 .empty(empty_stage2) 56 ); 57 assign rd_en_stage2 = ~empty_stage2 & ~full_stage2; 58 assign wr_en_stage2 = rd_en_stage2; 59 60 61 output_limit_fifo #( 62 .ADDR_MSB(`MSB(`OUTPUT_FIFO_SIZE) - 2) 63 //.ADDR_MSB(13) // 32 Kbytes 64 ) fifo_output0( 65 .rst(1'b0), 66 .CLK(rd_clk), 67 68 .din(data_stage2), 69 .wr_en(wr_en_stage2), 70 .full(full_stage2), 71 72 .dout(dout), 73 .rd_en(rd_en), 74 .empty(empty), 75 76 .mode_limit(mode_limit), 77 .reg_output_limit(reg_output_limit), 78 .output_limit(output_limit), 79 .output_limit_not_done(output_limit_not_done) 80 ); 81 82endmodule 83