1`timescale 1ns / 1ps
2/*
3 * This software is Copyright (c) 2016 Denis Burykin
4 * [denis_burykin yahoo com], [denis-burykin2014 yandex ru]
5 * and it is hereby released to the general public under the following terms:
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted.
8 *
9 */
10
11module startup_spartan6 (
12	input rst
13	);
14
15	STARTUP_SPARTAN6 STARTUP_SPARTAN6_inst (
16		.CFGCLK(),//CFGCLK),       // 1-bit output: Configuration logic main clock output.
17		.CFGMCLK(),//CFGMCLK),     // 1-bit output: Configuration internal oscillator clock output.
18		.EOS(),//EOS),             // 1-bit output: Active high output signal indicates the End Of Configuration.
19		.CLK(1'b0),             // 1-bit input: User startup-clock input
20		.GSR(rst),             // 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
21		.GTS(1'b0),             // 1-bit input: Global 3-state input (GTS cannot be used for the port name)
22		.KEYCLEARB(1'b0)  // 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
23	);
24
25
26endmodule
27