1# 2# This software is Copyright (c) 2016 Denis Burykin 3# [denis_burykin yahoo com], [denis-burykin2014 yandex ru] 4# and it is hereby released to the general public under the following terms: 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted. 7# 8# TIMESPEC's moved to clocks.ucf 9NET "IFCLK_IN" LOC = "K20" |IOSTANDARD = LVCMOS33 ; 10NET "FXCLK_IN" LOC = "L22" | IOSTANDARD = LVCMOS33 ; 11 12NET "CS_IN" LOC = "AB11" |IOSTANDARD = LVCMOS33 ; 13 14NET "PA0" LOC = "AA22" |IOSTANDARD = LVCMOS33 ; 15NET "PA1" LOC = "W17" |IOSTANDARD = LVCMOS33 ; 16NET "PA7" LOC = "AB17" |IOSTANDARD = LVCMOS33 ; 17 18NET "SLOE" LOC = "U15" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; # PA2 19NET "SLRD" LOC = "N22" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; 20NET "SLWR" LOC = "M22" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; 21NET "PKTEND" LOC = "AB5" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; # PA6 22NET "FIFOADR0" LOC = "AB21" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ; # PA4 23NET "FIFOADR1" LOC = "Y18" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ; # PA5 24NET "FLAGA" LOC = "F20" |IOSTANDARD = LVCMOS33 ; 25NET "FLAGB" LOC = "F19" |IOSTANDARD = LVCMOS33 ; 26NET "FLAGC" LOC = "F18" |IOSTANDARD = LVCMOS33 ; 27 28NET "FIFO_DATA<0>" LOC = "Y17" |IOSTANDARD = LVCMOS33 ; 29NET "FIFO_DATA<1>" LOC = "V13" |IOSTANDARD = LVCMOS33 ; 30NET "FIFO_DATA<2>" LOC = "W13" |IOSTANDARD = LVCMOS33 ; 31NET "FIFO_DATA<3>" LOC = "AA8" |IOSTANDARD = LVCMOS33 ; 32NET "FIFO_DATA<4>" LOC = "AB8" |IOSTANDARD = LVCMOS33 ; 33NET "FIFO_DATA<5>" LOC = "W6" |IOSTANDARD = LVCMOS33 ; 34NET "FIFO_DATA<6>" LOC = "Y6" |IOSTANDARD = LVCMOS33 ; 35NET "FIFO_DATA<7>" LOC = "Y9" |IOSTANDARD = LVCMOS33 ; 36NET "FIFO_DATA<8>" LOC = "V21" |IOSTANDARD = LVCMOS33 ; 37NET "FIFO_DATA<9>" LOC = "V22" |IOSTANDARD = LVCMOS33 ; 38NET "FIFO_DATA<10>" LOC = "U20" |IOSTANDARD = LVCMOS33 ; 39NET "FIFO_DATA<11>" LOC = "U22" |IOSTANDARD = LVCMOS33 ; 40NET "FIFO_DATA<12>" LOC = "R20" |IOSTANDARD = LVCMOS33 ; 41NET "FIFO_DATA<13>" LOC = "R22" |IOSTANDARD = LVCMOS33 ; 42NET "FIFO_DATA<14>" LOC = "P18" |IOSTANDARD = LVCMOS33 ; 43NET "FIFO_DATA<15>" LOC = "P19" |IOSTANDARD = LVCMOS33 ; 44 45 46NET "PC<0>" LOC="G20" |IOSTANDARD = LVCMOS33 |DRIVE = 12; 47NET "PC<1>" LOC="T20" |IOSTANDARD = LVCMOS33 |DRIVE = 12; 48NET "PC<2>" LOC="Y5" |IOSTANDARD = LVCMOS33 |DRIVE = 12; 49NET "PC<3>" LOC="AB9" |IOSTANDARD = LVCMOS33 |DRIVE = 12; 50NET "PC<4>" LOC="G19" |IOSTANDARD = LVCMOS33 |DRIVE = 12; 51NET "PC<5>" LOC="H20" |IOSTANDARD = LVCMOS33 |DRIVE = 12; 52NET "PC<6>" LOC="H19" |IOSTANDARD = LVCMOS33 |DRIVE = 12; 53NET "PC<7>" LOC="H18" |IOSTANDARD = LVCMOS33 |DRIVE = 12; 54 55NET "INT4" LOC = "C18" |IOSTANDARD = LVCMOS33 |DRIVE = 12; 56NET "INT5" LOC = "V17" |IOSTANDARD = LVCMOS33 |DRIVE = 12; 57# NET "SCL" LOC = "F22" | IOSTANDARD = LVCMOS33 ; 58# NET "SDA" LOC = "E22" | IOSTANDARD = LVCMOS33 ; 59NET "FPGA_ID<0>" LOC="T12" |IOSTANDARD = LVCMOS33 ; 60NET "FPGA_ID<1>" LOC="R13" |IOSTANDARD = LVCMOS33 ; 61NET "FPGA_ID<2>" LOC="T14" |IOSTANDARD = LVCMOS33 ; 62 63NET "FPGA_ID*" TIG; 64 65 66