1 /**************************************************************************//**
2 * @file core_cm0.h
3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
4 * @version V4.10
5 * @date 18. March 2015
6 *
7 * @note
8 *
9 ******************************************************************************/
10 /* Copyright (c) 2009 - 2015 ARM LIMITED
11
12 All rights reserved.
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 - Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 - Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 - Neither the name of ARM nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23 *
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ---------------------------------------------------------------------------*/
36
37
38 #if defined ( __ICCARM__ )
39 #pragma system_include /* treat file as system include file for MISRA check */
40 #endif
41
42 #ifndef __CORE_CM0_H_GENERIC
43 #define __CORE_CM0_H_GENERIC
44
45 #ifdef __cplusplus
46 extern "C" {
47 #endif
48
49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
50 CMSIS violates the following MISRA-C:2004 rules:
51
52 \li Required Rule 8.5, object/function definition in header file.<br>
53 Function definitions in header files are used to allow 'inlining'.
54
55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
56 Unions are used for effective representation of core registers.
57
58 \li Advisory Rule 19.7, Function-like macro defined.<br>
59 Function-like macros are used to allow more efficient code.
60 */
61
62
63 /*******************************************************************************
64 * CMSIS definitions
65 ******************************************************************************/
66 /** \ingroup Cortex_M0
67 @{
68 */
69
70 /* CMSIS CM0 definitions */
71 #define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
72 #define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
73 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
74 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
75
76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
77
78
79 #if defined ( __CC_ARM )
80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
82 #define __STATIC_INLINE static __inline
83
84 #elif defined ( __GNUC__ )
85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
87 #define __STATIC_INLINE static inline
88
89 #elif defined ( __ICCARM__ )
90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
92 #define __STATIC_INLINE static inline
93
94 #elif defined ( __TMS470__ )
95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
96 #define __STATIC_INLINE static inline
97
98 #elif defined ( __TASKING__ )
99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
101 #define __STATIC_INLINE static inline
102
103 #elif defined ( __CSMC__ )
104 #define __packed
105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
107 #define __STATIC_INLINE static inline
108
109 #endif
110
111 /** __FPU_USED indicates whether an FPU is used or not.
112 This core does not support an FPU at all
113 */
114 #define __FPU_USED 0
115
116 #if defined ( __CC_ARM )
117 #if defined __TARGET_FPU_VFP
118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
119 #endif
120
121 #elif defined ( __GNUC__ )
122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
124 #endif
125
126 #elif defined ( __ICCARM__ )
127 #if defined __ARMVFP__
128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
129 #endif
130
131 #elif defined ( __TMS470__ )
132 #if defined __TI__VFP_SUPPORT____
133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
134 #endif
135
136 #elif defined ( __TASKING__ )
137 #if defined __FPU_VFP__
138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
139 #endif
140
141 #elif defined ( __CSMC__ ) /* Cosmic */
142 #if ( __CSMC__ & 0x400) // FPU present for parser
143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
144 #endif
145 #endif
146
147 #include <stdint.h> /* standard types definitions */
148 #include <core_cmInstr.h> /* Core Instruction Access */
149 #include <core_cmFunc.h> /* Core Function Access */
150
151 #ifdef __cplusplus
152 }
153 #endif
154
155 #endif /* __CORE_CM0_H_GENERIC */
156
157 #ifndef __CMSIS_GENERIC
158
159 #ifndef __CORE_CM0_H_DEPENDANT
160 #define __CORE_CM0_H_DEPENDANT
161
162 #ifdef __cplusplus
163 extern "C" {
164 #endif
165
166 /* check device defines and use defaults */
167 #if defined __CHECK_DEVICE_DEFINES
168 #ifndef __CM0_REV
169 #define __CM0_REV 0x0000
170 #warning "__CM0_REV not defined in device header file; using default!"
171 #endif
172
173 #ifndef __NVIC_PRIO_BITS
174 #define __NVIC_PRIO_BITS 2
175 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
176 #endif
177
178 #ifndef __Vendor_SysTickConfig
179 #define __Vendor_SysTickConfig 0
180 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
181 #endif
182 #endif
183
184 /* IO definitions (access restrictions to peripheral registers) */
185 /**
186 \defgroup CMSIS_glob_defs CMSIS Global Defines
187
188 <strong>IO Type Qualifiers</strong> are used
189 \li to specify the access to peripheral variables.
190 \li for automatic generation of peripheral register debug information.
191 */
192 #ifdef __cplusplus
193 #define __I volatile /*!< Defines 'read only' permissions */
194 #else
195 #define __I volatile const /*!< Defines 'read only' permissions */
196 #endif
197 #define __O volatile /*!< Defines 'write only' permissions */
198 #define __IO volatile /*!< Defines 'read / write' permissions */
199
200 #ifdef __cplusplus
201 #define __IM volatile /*!< Defines 'read only' permissions */
202 #else
203 #define __IM volatile const /*!< Defines 'read only' permissions */
204 #endif
205 #define __OM volatile /*!< Defines 'write only' permissions */
206 #define __IOM volatile /*!< Defines 'read / write' permissions */
207
208 /*@} end of group Cortex_M0 */
209
210
211
212 /*******************************************************************************
213 * Register Abstraction
214 Core Register contain:
215 - Core Register
216 - Core NVIC Register
217 - Core SCB Register
218 - Core SysTick Register
219 ******************************************************************************/
220 /** \defgroup CMSIS_core_register Defines and Type Definitions
221 \brief Type definitions and defines for Cortex-M processor based devices.
222 */
223
224 /** \ingroup CMSIS_core_register
225 \defgroup CMSIS_CORE Status and Control Registers
226 \brief Core Register type definitions.
227 @{
228 */
229
230 /** \brief Union type to access the Application Program Status Register (APSR).
231 */
232 typedef union
233 {
234 struct
235 {
236 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
237 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
238 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
239 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
240 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
241 } b; /*!< Structure used for bit access */
242 uint32_t w; /*!< Type used for word access */
243 } APSR_Type;
244
245 /* APSR Register Definitions */
246 #define APSR_N_Pos 31 /*!< APSR: N Position */
247 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
248
249 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
250 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
251
252 #define APSR_C_Pos 29 /*!< APSR: C Position */
253 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
254
255 #define APSR_V_Pos 28 /*!< APSR: V Position */
256 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
257
258
259 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
260 */
261 typedef union
262 {
263 struct
264 {
265 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
266 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
267 } b; /*!< Structure used for bit access */
268 uint32_t w; /*!< Type used for word access */
269 } IPSR_Type;
270
271 /* IPSR Register Definitions */
272 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
273 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
274
275
276 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
277 */
278 typedef union
279 {
280 struct
281 {
282 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
283 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
284 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
285 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
286 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
287 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
288 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
289 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
290 } b; /*!< Structure used for bit access */
291 uint32_t w; /*!< Type used for word access */
292 } xPSR_Type;
293
294 /* xPSR Register Definitions */
295 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
296 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
297
298 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
299 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
300
301 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
302 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
303
304 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
305 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
306
307 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
308 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
309
310 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
311 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
312
313
314 /** \brief Union type to access the Control Registers (CONTROL).
315 */
316 typedef union
317 {
318 struct
319 {
320 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
321 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
322 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
323 } b; /*!< Structure used for bit access */
324 uint32_t w; /*!< Type used for word access */
325 } CONTROL_Type;
326
327 /* CONTROL Register Definitions */
328 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
329 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
330
331 /*@} end of group CMSIS_CORE */
332
333
334 /** \ingroup CMSIS_core_register
335 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
336 \brief Type definitions for the NVIC Registers
337 @{
338 */
339
340 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
341 */
342 typedef struct
343 {
344 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
345 uint32_t RESERVED0[31];
346 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
347 uint32_t RSERVED1[31];
348 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
349 uint32_t RESERVED2[31];
350 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
351 uint32_t RESERVED3[31];
352 uint32_t RESERVED4[64];
353 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
354 } NVIC_Type;
355
356 /*@} end of group CMSIS_NVIC */
357
358
359 /** \ingroup CMSIS_core_register
360 \defgroup CMSIS_SCB System Control Block (SCB)
361 \brief Type definitions for the System Control Block Registers
362 @{
363 */
364
365 /** \brief Structure type to access the System Control Block (SCB).
366 */
367 typedef struct
368 {
369 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
370 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
371 uint32_t RESERVED0;
372 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
373 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
374 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
375 uint32_t RESERVED1;
376 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
377 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
378 } SCB_Type;
379
380 /* SCB CPUID Register Definitions */
381 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
382 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
383
384 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
385 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
386
387 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
388 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
389
390 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
391 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
392
393 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
394 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
395
396 /* SCB Interrupt Control State Register Definitions */
397 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
398 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
399
400 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
401 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
402
403 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
404 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
405
406 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
407 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
408
409 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
410 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
411
412 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
413 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
414
415 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
416 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
417
418 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
419 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
420
421 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
422 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
423
424 /* SCB Application Interrupt and Reset Control Register Definitions */
425 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
426 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
427
428 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
429 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
430
431 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
432 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
433
434 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
435 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
436
437 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
438 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
439
440 /* SCB System Control Register Definitions */
441 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
442 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
443
444 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
445 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
446
447 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
448 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
449
450 /* SCB Configuration Control Register Definitions */
451 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
452 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
453
454 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
455 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
456
457 /* SCB System Handler Control and State Register Definitions */
458 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
459 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
460
461 /*@} end of group CMSIS_SCB */
462
463
464 /** \ingroup CMSIS_core_register
465 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
466 \brief Type definitions for the System Timer Registers.
467 @{
468 */
469
470 /** \brief Structure type to access the System Timer (SysTick).
471 */
472 typedef struct
473 {
474 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
475 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
476 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
477 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
478 } SysTick_Type;
479
480 /* SysTick Control / Status Register Definitions */
481 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
482 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
483
484 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
485 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
486
487 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
488 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
489
490 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
491 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
492
493 /* SysTick Reload Register Definitions */
494 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
495 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
496
497 /* SysTick Current Register Definitions */
498 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
499 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
500
501 /* SysTick Calibration Register Definitions */
502 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
503 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
504
505 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
506 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
507
508 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
509 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
510
511 /*@} end of group CMSIS_SysTick */
512
513
514 /** \ingroup CMSIS_core_register
515 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
516 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
517 are only accessible over DAP and not via processor. Therefore
518 they are not covered by the Cortex-M0 header file.
519 @{
520 */
521 /*@} end of group CMSIS_CoreDebug */
522
523
524 /** \ingroup CMSIS_core_register
525 \defgroup CMSIS_core_base Core Definitions
526 \brief Definitions for base addresses, unions, and structures.
527 @{
528 */
529
530 /* Memory mapping of Cortex-M0 Hardware */
531 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
532 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
533 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
534 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
535
536 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
537 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
538 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
539
540
541 /*@} */
542
543
544
545 /*******************************************************************************
546 * Hardware Abstraction Layer
547 Core Function Interface contains:
548 - Core NVIC Functions
549 - Core SysTick Functions
550 - Core Register Access Functions
551 ******************************************************************************/
552 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
553 */
554
555
556
557 /* ########################## NVIC functions #################################### */
558 /** \ingroup CMSIS_Core_FunctionInterface
559 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
560 \brief Functions that manage interrupts and exceptions via the NVIC.
561 @{
562 */
563
564 /* Interrupt Priorities are WORD accessible only under ARMv6M */
565 /* The following MACROS handle generation of the register offset and byte masks */
566 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
567 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
568 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
569
570
571 /** \brief Enable External Interrupt
572
573 The function enables a device-specific interrupt in the NVIC interrupt controller.
574
575 \param [in] IRQn External interrupt number. Value cannot be negative.
576 */
NVIC_EnableIRQ(IRQn_Type IRQn)577 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
578 {
579 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
580 }
581
582
583 /** \brief Disable External Interrupt
584
585 The function disables a device-specific interrupt in the NVIC interrupt controller.
586
587 \param [in] IRQn External interrupt number. Value cannot be negative.
588 */
NVIC_DisableIRQ(IRQn_Type IRQn)589 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
590 {
591 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
592 __DSB();
593 __ISB();
594 }
595
596
597 /** \brief Get Pending Interrupt
598
599 The function reads the pending register in the NVIC and returns the pending bit
600 for the specified interrupt.
601
602 \param [in] IRQn Interrupt number.
603
604 \return 0 Interrupt status is not pending.
605 \return 1 Interrupt status is pending.
606 */
NVIC_GetPendingIRQ(IRQn_Type IRQn)607 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
608 {
609 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
610 }
611
612
613 /** \brief Set Pending Interrupt
614
615 The function sets the pending bit of an external interrupt.
616
617 \param [in] IRQn Interrupt number. Value cannot be negative.
618 */
NVIC_SetPendingIRQ(IRQn_Type IRQn)619 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
620 {
621 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
622 }
623
624
625 /** \brief Clear Pending Interrupt
626
627 The function clears the pending bit of an external interrupt.
628
629 \param [in] IRQn External interrupt number. Value cannot be negative.
630 */
NVIC_ClearPendingIRQ(IRQn_Type IRQn)631 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
632 {
633 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
634 }
635
636
637 /** \brief Set Interrupt Priority
638
639 The function sets the priority of an interrupt.
640
641 \note The priority cannot be set for every core interrupt.
642
643 \param [in] IRQn Interrupt number.
644 \param [in] priority Priority to set.
645 */
NVIC_SetPriority(IRQn_Type IRQn,uint32_t priority)646 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
647 {
648 if((int32_t)(IRQn) < 0) {
649 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
650 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
651 }
652 else {
653 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
654 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
655 }
656 }
657
658
659 /** \brief Get Interrupt Priority
660
661 The function reads the priority of an interrupt. The interrupt
662 number can be positive to specify an external (device specific)
663 interrupt, or negative to specify an internal (core) interrupt.
664
665
666 \param [in] IRQn Interrupt number.
667 \return Interrupt Priority. Value is aligned automatically to the implemented
668 priority bits of the microcontroller.
669 */
NVIC_GetPriority(IRQn_Type IRQn)670 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
671 {
672
673 if((int32_t)(IRQn) < 0) {
674 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
675 }
676 else {
677 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
678 }
679 }
680
681
682 /** \brief System Reset
683
684 The function initiates a system reset request to reset the MCU.
685 */
NVIC_SystemReset(void)686 __STATIC_INLINE void NVIC_SystemReset(void)
687 {
688 __DSB(); /* Ensure all outstanding memory accesses included
689 buffered write are completed before reset */
690 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
691 SCB_AIRCR_SYSRESETREQ_Msk);
692 __DSB(); /* Ensure completion of memory access */
693 while(1) { __NOP(); } /* wait until reset */
694 }
695
696 /*@} end of CMSIS_Core_NVICFunctions */
697
698
699
700 /* ################################## SysTick function ############################################ */
701 /** \ingroup CMSIS_Core_FunctionInterface
702 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
703 \brief Functions that configure the System.
704 @{
705 */
706
707 #if (__Vendor_SysTickConfig == 0)
708
709 /** \brief System Tick Configuration
710
711 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
712 Counter is in free running mode to generate periodic interrupts.
713
714 \param [in] ticks Number of ticks between two interrupts.
715
716 \return 0 Function succeeded.
717 \return 1 Function failed.
718
719 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
720 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
721 must contain a vendor-specific implementation of this function.
722
723 */
SysTick_Config(uint32_t ticks)724 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
725 {
726 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
727
728 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
729 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
730 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
731 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
732 SysTick_CTRL_TICKINT_Msk |
733 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
734 return (0UL); /* Function successful */
735 }
736
737 #endif
738
739 /*@} end of CMSIS_Core_SysTickFunctions */
740
741
742
743
744 #ifdef __cplusplus
745 }
746 #endif
747
748 #endif /* __CORE_CM0_H_DEPENDANT */
749
750 #endif /* __CMSIS_GENERIC */
751