1 /**
2 ******************************************************************************
3 * @file stm32l1xx_ll_adc.h
4 * @author MCD Application Team
5 * @version V1.2.0
6 * @date 01-July-2016
7 * @brief Header file of ADC LL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32L1xx_LL_ADC_H
40 #define __STM32L1xx_LL_ADC_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32l1xx.h"
48
49 /** @addtogroup STM32L1xx_LL_Driver
50 * @{
51 */
52
53 #if defined (ADC1)
54
55 /** @defgroup ADC_LL ADC
56 * @{
57 */
58
59 /* Private types -------------------------------------------------------------*/
60 /* Private variables ---------------------------------------------------------*/
61
make_crc_table(void)62 /* Private constants ---------------------------------------------------------*/
63 /** @defgroup ADC_LL_Private_Constants ADC Private Constants
64 * @{
65 */
66
67 /* Internal mask for ADC group regular sequencer: */
68 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
69 /* - sequencer register offset */
70 /* - sequencer rank bits position into the selected register */
71
72 /* Internal register offset for ADC group regular sequencer configuration */
73 /* (offset placed into a spare area of literal definition) */
74 #define ADC_SQR1_REGOFFSET ((uint32_t)0x00000000U)
75 #define ADC_SQR2_REGOFFSET ((uint32_t)0x00000100U)
76 #define ADC_SQR3_REGOFFSET ((uint32_t)0x00000200U)
77 #define ADC_SQR4_REGOFFSET ((uint32_t)0x00000300U)
78 #define ADC_SQR5_REGOFFSET ((uint32_t)0x00000400U)
79
80 #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET | ADC_SQR5_REGOFFSET)
81 #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
82
83 /* Definition of ADC group regular sequencer bits information to be inserted */
84 /* into ADC group regular sequencer ranks literals definition. */
85 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR5_SQ1) */
86 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_SQR5_SQ2) */
87 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_SQR5_SQ3) */
88 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_SQR5_SQ4) */
89 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_SQR5_SQ5) */
90 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS ((uint32_t)25U) /* Value equivalent to POSITION_VAL(ADC_SQR5_SQ6) */
91 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ7) */
92 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ8) */
93 #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ9) */
94 #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ10) */
95 #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ11) */
96 #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS ((uint32_t)25U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ12) */
97 #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ13) */
98 #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ14) */
99 #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ15) */
100 #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ16) */
101 #define ADC_REG_RANK_17_SQRX_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ17) */
102 #define ADC_REG_RANK_18_SQRX_BITOFFSET_POS ((uint32_t)25U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ18) */
103 #define ADC_REG_RANK_19_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ29) */
104 #define ADC_REG_RANK_20_SQRX_BITOFFSET_POS ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ20) */
105 #define ADC_REG_RANK_21_SQRX_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ21) */
106 #define ADC_REG_RANK_22_SQRX_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ22) */
107 #define ADC_REG_RANK_23_SQRX_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ23) */
108 #define ADC_REG_RANK_24_SQRX_BITOFFSET_POS ((uint32_t)25U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ24) */
109 #define ADC_REG_RANK_25_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ25) */
110 #define ADC_REG_RANK_26_SQRX_BITOFFSET_POS ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ26) */
111 #define ADC_REG_RANK_27_SQRX_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ27) */
112 #if defined(ADC_SQR1_SQ28)
113 #define ADC_REG_RANK_28_SQRX_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ28) */
114 #endif
115
116
117
118 /* Internal mask for ADC group injected sequencer: */
119 /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
120 /* - data register offset */
121 /* - offset register offset */
122 /* - sequencer rank bits position into the selected register */
123
124 /* Internal register offset for ADC group injected data register */
125 /* (offset placed into a spare area of literal definition) */
126 #define ADC_JDR1_REGOFFSET ((uint32_t)0x00000000U)
127 #define ADC_JDR2_REGOFFSET ((uint32_t)0x00000100U)
128 #define ADC_JDR3_REGOFFSET ((uint32_t)0x00000200U)
129 #define ADC_JDR4_REGOFFSET ((uint32_t)0x00000300U)
130
131 /* Internal register offset for ADC group injected offset configuration */
132 /* (offset placed into a spare area of literal definition) */
133 #define ADC_JOFR1_REGOFFSET ((uint32_t)0x00000000U)
134 #define ADC_JOFR2_REGOFFSET ((uint32_t)0x00001000U)
135 #define ADC_JOFR3_REGOFFSET ((uint32_t)0x00002000U)
136 #define ADC_JOFR4_REGOFFSET ((uint32_t)0x00003000U)
137
138 #define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
139 #define ADC_INJ_JOFRX_REGOFFSET_MASK (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET)
140 #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
141
142 /* Definition of ADC group injected sequencer bits information to be inserted */
143 /* into ADC group injected sequencer ranks literals definition. */
144 #define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ1) */
145 #define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ2) */
146 #define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ3) */
147 #define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ4) */
148
149
150
151 /* Internal mask for ADC group regular trigger: */
152 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
153 /* - regular trigger source */
154 /* - regular trigger edge */
155 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
156
157 /* Mask containing trigger source masks for each of possible */
158 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
159 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
160 #define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTSEL) >> (4U * 0U)) | \
161 ((ADC_CR2_EXTSEL) >> (4U * 1U)) | \
162 ((ADC_CR2_EXTSEL) >> (4U * 2U)) | \
163 ((ADC_CR2_EXTSEL) >> (4U * 3U)) )
164
165 /* Mask containing trigger edge masks for each of possible */
166 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
167 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
168 #define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN) >> (4U * 0U)) | \
169 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 1U)) | \
170 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 2U)) | \
171 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 3U)) )
172
173 /* Definition of ADC group regular trigger bits information. */
174 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTSEL) */
175 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS ((uint32_t)28U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTEN) */
176
177
178
179 /* Internal mask for ADC group injected trigger: */
180 /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */
181 /* - injected trigger source */
182 /* - injected trigger edge */
183 #define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
184
185 /* Mask containing trigger source masks for each of possible */
186 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
187 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
188 #define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_JEXTSEL) >> (4U * 0U)) | \
189 ((ADC_CR2_JEXTSEL) >> (4U * 1U)) | \
190 ((ADC_CR2_JEXTSEL) >> (4U * 2U)) | \
191 ((ADC_CR2_JEXTSEL) >> (4U * 3U)) )
192
193 /* Mask containing trigger edge masks for each of possible */
194 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
195 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
196 #define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN) >> (4U * 0U)) | \
197 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 1U)) | \
198 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 2U)) | \
199 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 3U)) )
200
201 /* Definition of ADC group injected trigger bits information. */
202 #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS ((uint32_t)16U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTSEL) */
203 #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTEN) */
204
205
206
207
208
209
210 /* Internal mask for ADC channel: */
211 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
212 /* - channel identifier defined by number */
213 /* - channel differentiation between external channels (connected to */
214 /* GPIO pins) and internal channels (connected to internal paths) */
215 /* - channel sampling time defined by SMPRx register offset */
216 /* and SMPx bits positions into SMPRx register */
217 #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CR1_AWDCH)
218 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ((uint32_t) 0U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
219 #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
220 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
221 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 ((uint32_t)0x0000001FU) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
222
223 /* Channel differentiation between external and internal channels */
224 #define ADC_CHANNEL_ID_INTERNAL_CH ((uint32_t)0x80000000U) /* Marker of internal channel */
225 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH)
226
227 /* Internal register offset for ADC channel sampling time configuration */
228 /* (offset placed into a spare area of literal definition) */
229 #define ADC_SMPR1_REGOFFSET ((uint32_t)0x00000000U)
230 #define ADC_SMPR2_REGOFFSET ((uint32_t)0x02000000U)
231 #define ADC_SMPR3_REGOFFSET ((uint32_t)0x04000000U)
232 #if defined(ADC_SMPR0_SMP31)
233 #define ADC_SMPR0_REGOFFSET ((uint32_t)0x28000000U) /* SMPR0 register offset from SMPR1 is 20 registers. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */
234 #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET | ADC_SMPR3_REGOFFSET | ADC_SMPR0_REGOFFSET)
235 #else
236 #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET | ADC_SMPR3_REGOFFSET)
237 #endif /* ADC_SMPR0_SMP31 */
238
239 #define ADC_CHANNEL_SMPx_BITOFFSET_MASK ((uint32_t)0x01F00000U)
240 #define ADC_CHANNEL_SMPx_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
241
242 /* Definition of channels ID number information to be inserted into */
243 /* channels literals definition. */
244 #define ADC_CHANNEL_0_NUMBER ((uint32_t)0x00000000U)
245 #define ADC_CHANNEL_1_NUMBER ( ADC_CR1_AWDCH_0)
246 #define ADC_CHANNEL_2_NUMBER ( ADC_CR1_AWDCH_1 )
247 #define ADC_CHANNEL_3_NUMBER ( ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
248 #define ADC_CHANNEL_4_NUMBER ( ADC_CR1_AWDCH_2 )
249 #define ADC_CHANNEL_5_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)
250 #define ADC_CHANNEL_6_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )
251 #define ADC_CHANNEL_7_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
252 #define ADC_CHANNEL_8_NUMBER ( ADC_CR1_AWDCH_3 )
253 #define ADC_CHANNEL_9_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0)
254 #define ADC_CHANNEL_10_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 )
255 #define ADC_CHANNEL_11_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
256 #define ADC_CHANNEL_12_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 )
257 #define ADC_CHANNEL_13_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)
258 #define ADC_CHANNEL_14_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )
259 #define ADC_CHANNEL_15_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
260 #define ADC_CHANNEL_16_NUMBER (ADC_CR1_AWDCH_4 )
261 #define ADC_CHANNEL_17_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0)
262 #define ADC_CHANNEL_18_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1 )
263 #define ADC_CHANNEL_19_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
264 #define ADC_CHANNEL_20_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_2 )
265 #define ADC_CHANNEL_21_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)
266 #define ADC_CHANNEL_22_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )
267 #define ADC_CHANNEL_23_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
268 #define ADC_CHANNEL_24_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_3 )
269 #define ADC_CHANNEL_25_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0)
270 #define ADC_CHANNEL_26_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 )
271 #if defined(ADC_SMPR0_SMP31)
272 #define ADC_CHANNEL_27_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
273 #define ADC_CHANNEL_28_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 )
274 #define ADC_CHANNEL_29_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)
275 #define ADC_CHANNEL_30_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )
276 #define ADC_CHANNEL_31_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
277 #endif /* ADC_SMPR0_SMP31 */
278
279 /* Definition of channels sampling time information to be inserted into */
280 /* channels literals definition. */
281 #define ADC_CHANNEL_0_SMP (ADC_SMPR3_REGOFFSET | (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP0) */
282 #define ADC_CHANNEL_1_SMP (ADC_SMPR3_REGOFFSET | (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP1) */
283 #define ADC_CHANNEL_2_SMP (ADC_SMPR3_REGOFFSET | (((uint32_t) 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP2) */
284 #define ADC_CHANNEL_3_SMP (ADC_SMPR3_REGOFFSET | (((uint32_t) 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP3) */
285 #define ADC_CHANNEL_4_SMP (ADC_SMPR3_REGOFFSET | (((uint32_t)12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP4) */
286 #define ADC_CHANNEL_5_SMP (ADC_SMPR3_REGOFFSET | (((uint32_t)15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP5) */
287 #define ADC_CHANNEL_6_SMP (ADC_SMPR3_REGOFFSET | (((uint32_t)18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP6) */
288 #define ADC_CHANNEL_7_SMP (ADC_SMPR3_REGOFFSET | (((uint32_t)21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP7) */
289 #define ADC_CHANNEL_8_SMP (ADC_SMPR3_REGOFFSET | (((uint32_t)24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP8) */
290 #define ADC_CHANNEL_9_SMP (ADC_SMPR3_REGOFFSET | (((uint32_t)27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP9) */
291 #define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP10) */
292 #define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP11) */
293 #define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP12) */
294 #define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t) 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP13) */
295 #define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP14) */
296 #define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP15) */
297 #define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP16) */
298 #define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP17) */
299 #define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP18) */
300 #define ADC_CHANNEL_19_SMP (ADC_SMPR2_REGOFFSET | (((uint32_t)27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP19) */
301 #define ADC_CHANNEL_20_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP20) */
302 #define ADC_CHANNEL_21_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP21) */
303 #define ADC_CHANNEL_22_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP22) */
304 #define ADC_CHANNEL_23_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t) 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP23) */
305 #define ADC_CHANNEL_24_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP24) */
306 #define ADC_CHANNEL_25_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP25) */
307 #define ADC_CHANNEL_26_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP26) */
308 #if defined(ADC_SMPR0_SMP31)
309 #define ADC_CHANNEL_27_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP27) */
310 #define ADC_CHANNEL_28_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP28) */
311 #define ADC_CHANNEL_29_SMP (ADC_SMPR1_REGOFFSET | (((uint32_t)27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP19) */
312 #define ADC_CHANNEL_30_SMP (ADC_SMPR0_REGOFFSET | (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR0_SMP30) */
313 #define ADC_CHANNEL_31_SMP (ADC_SMPR0_REGOFFSET | (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR0_SMP31) */
314 #endif /* ADC_SMPR0_SMP31 */
315
316
317 /* Internal mask for ADC analog watchdog: */
318 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
319 /* (concatenation of multiple bits used in different analog watchdogs, */
320 /* (feature of several watchdogs not available on all STM32 families)). */
321 /* - analog watchdog 1: monitored channel defined by number, */
322 /* selection of ADC group (ADC groups regular and-or injected). */
323
324 /* Internal register offset for ADC analog watchdog channel configuration */
325 #define ADC_AWD_CR1_REGOFFSET ((uint32_t)0x00000000U)
326
327 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET)
328
329 #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CR1_AWDCH | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
330 #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK)
331
332 /* Internal register offset for ADC analog watchdog threshold configuration */
333 #define ADC_AWD_TR1_HIGH_REGOFFSET ((uint32_t)0x00000000U)
334 #define ADC_AWD_TR1_LOW_REGOFFSET ((uint32_t)0x00000001U)
335 #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET)
336
337
338 /* ADC registers bits positions */
339 #define ADC_CR1_RES_BITOFFSET_POS ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_CR1_RES) */
340 #define ADC_TR_HT_BITOFFSET_POS ((uint32_t)16U) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */
341
342
343 /* ADC internal channels related definitions */
344 /* Internal voltage reference VrefInt */
345 #define VREFINT_CAL_ADDR ((uint16_t*) ((uint32_t)0x1FF800F8U)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
346 #define VREFINT_CAL_VREF ((uint32_t) 3000U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
347 /* Temperature sensor */
348 #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) ((uint32_t)0x1FF800FAU)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
349 #define TEMPSENSOR_CAL2_ADDR ((uint16_t*) ((uint32_t)0x1FF800FEU)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
350 #define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
351 #define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
352 #define TEMPSENSOR_CAL_VREFANALOG ((uint32_t) 3000U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
353
354
355 /**
356 * @}
357 */
358
359
360 /* Private macros ------------------------------------------------------------*/
361 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
362 * @{
363 */
364
365 /**
366 * @brief Driver macro reserved for internal use: isolate bits with the
367 * selected mask and shift them to the register LSB
368 * (shift mask on register position bit 0).
369 * @param __BITS__ Bits in register 32 bits
370 * @param __MASK__ Mask in register 32 bits
371 * @retval Bits in register 32 bits
372 */
373 #define __ADC_MASK_SHIFT(__BITS__, __MASK__) \
374 (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
375
376 /**
377 * @brief Driver macro reserved for internal use: set a pointer to
378 * a register from a register basis from which an offset
379 * is applied.
380 * @param __REG__ Register basis from which the offset is applied.
381 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
382 * @retval Pointer to register address
383 */
384 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
385 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
386
387 /**
388 * @}
389 */
390
391
392 /* Exported types ------------------------------------------------------------*/
393 #if defined(USE_FULL_LL_DRIVER)
394 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
395 * @{
396 */
397
398 /**
399 * @brief Structure definition of some features of ADC common parameters
400 * and multimode
401 * (all ADC instances belonging to the same ADC common instance).
402 * @note The setting of these parameters by function @ref LL_ADC_CommonInit()
403 * is conditioned to ADC instances state (all ADC instances
404 * sharing the same ADC common instance):
405 * All ADC instances sharing the same ADC common instance must be
406 * disabled.
407 */
408 typedef struct
409 {
410 uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
411 This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
412 @note On this STM32 serie, HSI RC oscillator is the only clock source for ADC.
413 Therefore, HSI RC oscillator must be preliminarily enabled at RCC top level.
414 @note On this STM32 serie, some clock ratio constraints between ADC clock and APB clock
415 must be respected:
416 - In all cases: if APB clock frequency is too low compared ADC clock frequency, a delay between conversions must be inserted.
417 - If ADC group injected is used: ADC clock frequency should be lower than APB clock frequency /4 for resolution 12 or 10 bits, APB clock frequency /3 for resolution 8 bits, APB clock frequency /2 for resolution 6 bits.
418 Refer to reference manual.
419
420 This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */
421
422 } LL_ADC_CommonInitTypeDef;
423
424 /**
425 * @brief Structure definition of some features of ADC instance.
426 * @note These parameters have an impact on ADC scope: ADC instance.
427 * Affects both group regular and group injected (availability
428 * of ADC group injected depends on STM32 families).
429 * Refer to corresponding unitary functions into
430 * @ref ADC_LL_EF_Configuration_ADC_Instance .
431 * @note The setting of these parameters by function @ref LL_ADC_Init()
432 * is conditioned to ADC state:
433 * ADC instance must be disabled.
434 * This condition is applied to all ADC features, for efficiency
435 * and compatibility over all STM32 families. However, the different
436 * features can be set under different ADC state conditions
437 * (setting possible with ADC enabled without conversion on going,
438 * ADC enabled with conversion on going, ...)
439 * Each feature can be updated afterwards with a unitary function
440 * and potentially with ADC in a different state than disabled,
441 * refer to description of each function for setting
442 * conditioned to ADC state.
443 */
444 typedef struct
445 {
446 uint32_t Resolution; /*!< Set ADC resolution.
447 This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
448
449 This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
450
451 uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
452 This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
453
454 This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
455
456 uint32_t LowPowerMode; /*!< Set ADC low power mode.
457 This parameter can be a concatenation of a value of @ref ADC_LL_EC_LP_MODE_AUTOWAIT and a value of @ref ADC_LL_EC_LP_MODE_AUTOPOWEROFF
458
459 This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerModeAutoWait() and @ref LL_ADC_SetLowPowerModeAutoPowerOff(). */
460
461 uint32_t SequencersScanMode; /*!< Set ADC scan selection.
462 This parameter can be a value of @ref ADC_LL_EC_SCAN_SELECTION
463
464 This feature can be modified afterwards using unitary function @ref LL_ADC_SetSequencersScanMode(). */
465
466 } LL_ADC_InitTypeDef;
467
468 /**
469 * @brief Structure definition of some features of ADC group regular.
470 * @note These parameters have an impact on ADC scope: ADC group regular.
471 * Refer to corresponding unitary functions into
472 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
473 * (functions with prefix "REG").
474 * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
475 * is conditioned to ADC state:
476 * ADC instance must be disabled.
477 * This condition is applied to all ADC features, for efficiency
478 * and compatibility over all STM32 families. However, the different
479 * features can be set under different ADC state conditions
480 * (setting possible with ADC enabled without conversion on going,
481 * ADC enabled with conversion on going, ...)
482 * Each feature can be updated afterwards with a unitary function
483 * and potentially with ADC in a different state than disabled,
484 * refer to description of each function for setting
485 * conditioned to ADC state.
486 */
487 typedef struct
488 {
489 uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
490 This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
491 @note On this STM32 serie, setting of external trigger edge is performed
492 using function @ref LL_ADC_REG_StartConversionExtTrig().
493
494 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
495
496 uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
497 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
498 @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
499
500 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
501
502 uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
503 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
504 @note This parameter has an effect only if group regular sequencer is enabled
505 (scan length of 2 ranks or more).
506
507 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
508
509 uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
510 This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
511 Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
512
513 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
514
515 uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
516 This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
517
518 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
519
520 } LL_ADC_REG_InitTypeDef;
521
522 /**
523 * @brief Structure definition of some features of ADC group injected.
524 * @note These parameters have an impact on ADC scope: ADC group injected.
525 * Refer to corresponding unitary functions into
526 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
527 * (functions with prefix "INJ").
528 * @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
529 * is conditioned to ADC state:
530 * ADC instance must be disabled.
531 * This condition is applied to all ADC features, for efficiency
532 * and compatibility over all STM32 families. However, the different
533 * features can be set under different ADC state conditions
534 * (setting possible with ADC enabled without conversion on going,
535 * ADC enabled with conversion on going, ...)
536 * Each feature can be updated afterwards with a unitary function
537 * and potentially with ADC in a different state than disabled,
538 * refer to description of each function for setting
539 * conditioned to ADC state.
540 */
541 typedef struct
542 {
543 uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
544 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
545 @note On this STM32 serie, setting of external trigger edge is performed
546 using function @ref LL_ADC_INJ_StartConversionExtTrig().
547
548 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
549
550 uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
551 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
552 @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
553
554 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */
555
556 uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
557 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
558 @note This parameter has an effect only if group injected sequencer is enabled
559 (scan length of 2 ranks or more).
560
561 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */
562
563 uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
564 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
565 Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.
566
567 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
568
569 } LL_ADC_INJ_InitTypeDef;
570
571 /**
572 * @}
573 */
574 #endif /* USE_FULL_LL_DRIVER */
575
576 /* Exported constants --------------------------------------------------------*/
577 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
578 * @{
579 */
580
581 /** @defgroup ADC_LL_EC_FLAG ADC flags
582 * @brief Flags defines which can be used with LL_ADC_ReadReg function
583 * @{
584 */
585 #define LL_ADC_FLAG_ADRDY ADC_SR_ADONS /*!< ADC flag ADC instance ready */
586 #define LL_ADC_FLAG_STRT ADC_SR_STRT /*!< ADC flag ADC group regular conversion start */
587 #define LL_ADC_FLAG_EOCS ADC_SR_EOC /*!< ADC flag ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
588 #define LL_ADC_FLAG_OVR ADC_SR_OVR /*!< ADC flag ADC group regular overrun */
589 #define LL_ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC flag ADC group injected conversion start */
590 #define LL_ADC_FLAG_JEOS ADC_SR_JEOC /*!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
591 #define LL_ADC_FLAG_AWD1 ADC_SR_AWD /*!< ADC flag ADC analog watchdog 1 */
592 /**
593 * @}
594 */
595
596 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
597 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
598 * @{
599 */
600 #define LL_ADC_IT_EOCS ADC_CR1_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */
601 #define LL_ADC_IT_OVR ADC_CR1_OVRIE /*!< ADC interruption ADC group regular overrun */
602 #define LL_ADC_IT_JEOS ADC_CR1_JEOCIE /*!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
603 #define LL_ADC_IT_AWD1 ADC_CR1_AWDIE /*!< ADC interruption ADC analog watchdog 1 */
604 /**
605 * @}
606 */
607
608 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
609 * @{
610 */
611 /* List of ADC registers intended to be used (most commonly) with */
612 /* DMA transfer. */
613 /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
614 #define LL_ADC_DMA_REG_REGULAR_DATA ((uint32_t)0x00000000U) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
615 /**
616 * @}
617 */
618
619 /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
620 * @{
621 */
622 #define LL_ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000U) /*!< ADC asynchronous clock without prescaler */
623 #define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_ADCPRE_0) /*!< ADC asynchronous clock with prescaler division by 2 */
624 #define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_ADCPRE_1) /*!< ADC asynchronous clock with prescaler division by 4 */
625 /**
626 * @}
627 */
628
629 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
630 * @{
631 */
632 /* Note: Other measurement paths to internal channels may be available */
633 /* (connections to other peripherals). */
634 /* If they are not listed below, they do not require any specific */
635 /* path enable. In this case, Access to measurement path is done */
636 /* only by selecting the corresponding ADC internal channel. */
637 #define LL_ADC_PATH_INTERNAL_NONE ((uint32_t)0x00000000U)/*!< ADC measurement pathes all disabled */
638 #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_TSVREFE) /*!< ADC measurement path to internal channel VrefInt */
639 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSVREFE) /*!< ADC measurement path to internal channel temperature sensor */
640 /**
641 * @}
642 */
643
644 /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
645 * @{
646 */
647 #define LL_ADC_RESOLUTION_12B ((uint32_t)0x00000000U) /*!< ADC resolution 12 bits */
648 #define LL_ADC_RESOLUTION_10B ( ADC_CR1_RES_0) /*!< ADC resolution 10 bits */
649 #define LL_ADC_RESOLUTION_8B (ADC_CR1_RES_1 ) /*!< ADC resolution 8 bits */
650 #define LL_ADC_RESOLUTION_6B (ADC_CR1_RES_1 | ADC_CR1_RES_0) /*!< ADC resolution 6 bits */
651 /**
652 * @}
653 */
654
655 /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
656 * @{
657 */
658 #define LL_ADC_DATA_ALIGN_RIGHT ((uint32_t)0x00000000U)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
659 #define LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
660 /**
661 * @}
662 */
663
664 /** @defgroup ADC_LL_EC_LP_MODE_AUTOWAIT ADC instance - Low power mode auto wait (auto delay)
665 * @{
666 */
667 #define LL_ADC_LP_AUTOWAIT_NONE ((uint32_t)0x00000000U) /*!< ADC low power mode auto wait not activated */
668 #define LL_ADC_LP_AUTOWAIT ( ADC_CR2_DELS_0) /*!< ADC low power mode auto wait: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerModeAutoWait(). */
669 #define LL_ADC_LP_AUTOWAIT_7_APBCLOCKCYCLES ( ADC_CR2_DELS_1 ) /*!< ADC low power mode auto wait: Insert a delay between ADC conversions: 7 APB clock cycles */
670 #define LL_ADC_LP_AUTOWAIT_15_APBCLOCKCYCLES ( ADC_CR2_DELS_1 | ADC_CR2_DELS_0) /*!< ADC low power mode auto wait: Insert a delay between ADC conversions: 15 APB clock cycles */
671 #define LL_ADC_LP_AUTOWAIT_31_APBCLOCKCYCLES (ADC_CR2_DELS_2 ) /*!< ADC low power mode auto wait: Insert a delay between ADC conversions: 31 APB clock cycles */
672 #define LL_ADC_LP_AUTOWAIT_63_APBCLOCKCYCLES (ADC_CR2_DELS_2 | ADC_CR2_DELS_0) /*!< ADC low power mode auto wait: Insert a delay between ADC conversions: 63 APB clock cycles */
673 #define LL_ADC_LP_AUTOWAIT_127_APBCLOCKCYCLES (ADC_CR2_DELS_2 | ADC_CR2_DELS_1 ) /*!< ADC low power mode auto wait: Insert a delay between ADC conversions: 127 APB clock cycles */
674 #define LL_ADC_LP_AUTOWAIT_255_APBCLOCKCYCLES (ADC_CR2_DELS_2 | ADC_CR2_DELS_1 | ADC_CR2_DELS_0) /*!< ADC low power mode auto wait: Insert a delay between ADC conversions: 255 APB clock cycles */
675 /**
676 * @}
677 */
678
679 /** @defgroup ADC_LL_EC_LP_MODE_AUTOPOWEROFF ADC instance - Low power mode auto power-off
680 * @{
681 */
682 #define LL_ADC_LP_AUTOPOWEROFF_NONE ((uint32_t)0x00000000U) /*!< ADC low power mode auto power-off not activated */
683 #define LL_ADC_LP_AUTOPOWEROFF_IDLE_PHASE (ADC_CR1_PDI) /*!< ADC low power mode auto power-off: ADC power off when ADC is not converting (idle phase) */
684 #define LL_ADC_LP_AUTOPOWEROFF_AUTOWAIT_PHASE (ADC_CR1_PDD) /*!< ADC low power mode auto power-off: ADC power off when a delay is inserted between conversions (refer to function @ref LL_ADC_SetLowPowerModeAutoWait() ) */
685 #define LL_ADC_LP_AUTOPOWEROFF_IDLE_AUTOWAIT_PHASES (ADC_CR1_PDI | ADC_CR1_PDD) /*!< ADC low power mode auto power-off: ADC power off when ADC is not converting (idle phase) and when a delay is inserted between conversions (refer to function @ref LL_ADC_SetLowPowerModeAutoWait() ) */
686 /**
687 * @}
688 */
689
690 /** @defgroup ADC_LL_EC_SCAN_SELECTION ADC instance - Scan selection
691 * @{
692 */
693 #define LL_ADC_SEQ_SCAN_DISABLE ((uint32_t)0x00000000U) /*!< ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of both groups regular and injected sequencers (sequence length, ...) is discarded: equivalent to length of 1 rank.*/
694 #define LL_ADC_SEQ_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN) /*!< ADC conversions are performed in sequence conversions mode, according to configuration of both groups regular and injected sequencers (sequence length, ...). */
695 /**
696 * @}
697 */
698
699 #if defined(ADC_CR2_CFG)
700 /** @defgroup ADC_LL_EC_CHANNELS_BANK ADC instance - Channels bank
701 * @{
702 */
703 #define LL_ADC_CHANNELS_BANK_A ((uint32_t)0x00000000U) /*!< ADC channels bank A */
704 #define LL_ADC_CHANNELS_BANK_B ((uint32_t)ADC_CR2_CFG) /*!< ADC channels bank B, available in devices categories 3, 4, 5. */
705 /**
706 * @}
707 */
708 #endif
709
710 /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
711 * @{
712 */
713 #define LL_ADC_GROUP_REGULAR ((uint32_t)0x00000001U) /*!< ADC group regular (available on all STM32 devices) */
714 #define LL_ADC_GROUP_INJECTED ((uint32_t)0x00000002U) /*!< ADC group injected (not available on all STM32 devices)*/
715 #define LL_ADC_GROUP_REGULAR_INJECTED ((uint32_t)0x00000003U) /*!< ADC both groups regular and injected */
716 /**
717 * @}
718 */
719
720 /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
721 * @{
722 */
723 #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 . Channel different in bank A and bank B. */
724 #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 . Channel different in bank A and bank B. */
725 #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 . Channel different in bank A and bank B. */
726 #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 . Channel different in bank A and bank B. */
727 #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 . Direct (fast) channel. */
728 #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 . Direct (fast) channel. */
729 #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 . Channel different in bank A and bank B. */
730 #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 . Channel different in bank A and bank B. */
731 #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 . Channel different in bank A and bank B. */
732 #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 . Channel different in bank A and bank B. */
733 #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10. Channel different in bank A and bank B. */
734 #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11. Channel different in bank A and bank B. */
735 #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12. Channel different in bank A and bank B. */
736 #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13. Channel common to both bank A and bank B. */
737 #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14. Channel common to both bank A and bank B. */
738 #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15. Channel common to both bank A and bank B. */
739 #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16. Channel common to both bank A and bank B. */
740 #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17. Channel common to both bank A and bank B. */
741 #define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18. Channel common to both bank A and bank B. */
742 #define LL_ADC_CHANNEL_19 (ADC_CHANNEL_19_NUMBER | ADC_CHANNEL_19_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN19. Channel common to both bank A and bank B. */
743 #define LL_ADC_CHANNEL_20 (ADC_CHANNEL_20_NUMBER | ADC_CHANNEL_20_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN20. Channel common to both bank A and bank B. */
744 #define LL_ADC_CHANNEL_21 (ADC_CHANNEL_21_NUMBER | ADC_CHANNEL_21_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN21. Channel common to both bank A and bank B. */
745 #define LL_ADC_CHANNEL_22 (ADC_CHANNEL_22_NUMBER | ADC_CHANNEL_22_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN22. Direct (fast) channel. */
746 #define LL_ADC_CHANNEL_23 (ADC_CHANNEL_23_NUMBER | ADC_CHANNEL_23_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN23. Direct (fast) channel. */
747 #define LL_ADC_CHANNEL_24 (ADC_CHANNEL_24_NUMBER | ADC_CHANNEL_24_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN24. Direct (fast) channel. */
748 #define LL_ADC_CHANNEL_25 (ADC_CHANNEL_25_NUMBER | ADC_CHANNEL_25_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN25. Direct (fast) channel. */
749 #define LL_ADC_CHANNEL_26 (ADC_CHANNEL_26_NUMBER | ADC_CHANNEL_26_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN26. Direct (fast) channel. */
750 #if defined(ADC_SMPR0_SMP31)
751 #define LL_ADC_CHANNEL_27 (ADC_CHANNEL_27_NUMBER | ADC_CHANNEL_27_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN27. Channel common to both bank A and bank B. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */
752 #define LL_ADC_CHANNEL_28 (ADC_CHANNEL_28_NUMBER | ADC_CHANNEL_28_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN28. Channel common to both bank A and bank B. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */
753 #define LL_ADC_CHANNEL_29 (ADC_CHANNEL_29_NUMBER | ADC_CHANNEL_29_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN29. Channel common to both bank A and bank B. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */
754 #define LL_ADC_CHANNEL_30 (ADC_CHANNEL_30_NUMBER | ADC_CHANNEL_30_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN30. Channel common to both bank A and bank B. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */
755 #define LL_ADC_CHANNEL_31 (ADC_CHANNEL_31_NUMBER | ADC_CHANNEL_31_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN31. Channel common to both bank A and bank B. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */
756 #endif /* ADC_SMPR0_SMP31 */
757 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. Channel common to both bank A and bank B. */
758 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. Channel common to both bank A and bank B. */
759 #define LL_ADC_CHANNEL_VCOMP (LL_ADC_CHANNEL_26 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to comparator COMP1 positive input via ADC switch matrix. Channel common to both bank A and bank B. */
760 #if defined(OPAMP_CSR_OPA1PD) || defined (OPAMP_CSR_OPA2PD) || defined (OPAMP_CSR_OPA3PD)
761 #define LL_ADC_CHANNEL_VOPAMP1 (LL_ADC_CHANNEL_3 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP1 output via ADC switch matrix. Channel common to both bank A and bank B. */
762 #define LL_ADC_CHANNEL_VOPAMP2 (LL_ADC_CHANNEL_8 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP2 output via ADC switch matrix. Channel common to both bank A and bank B. */
763 #if defined(OPAMP_CSR_OPA3PD)
764 #define LL_ADC_CHANNEL_VOPAMP3 (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP3 output via ADC switch matrix. Channel common to both bank A and bank B. */
765 #endif /* OPAMP_CSR_OPA3PD */
766 #endif /* OPAMP_CSR_OPA1PD || OPAMP_CSR_OPA2PD || OPAMP_CSR_OPA3PD */
767 /**
768 * @}
769 */
770
771 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
772 * @{
773 */
774 #define LL_ADC_REG_TRIG_SOFTWARE ((uint32_t)0x00000000U) /*!< ADC group regular conversion trigger internal: SW start. */
775 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
776 #define LL_ADC_REG_TRIG_EXT_TIM2_CH3 (ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
777 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CR2_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
778 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
779 #define LL_ADC_REG_TRIG_EXT_TIM3_CH1 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
780 #define LL_ADC_REG_TRIG_EXT_TIM3_CH3 (ADC_CR2_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
781 #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
782 #define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
783 #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
784 #define LL_ADC_REG_TRIG_EXT_TIM9_CH2 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM9 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
785 #define LL_ADC_REG_TRIG_EXT_TIM9_TRGO (ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM9 TRGO. Trigger edge set to rising edge (default setting). */
786 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger external interrupt line 11. Trigger edge set to rising edge (default setting). */
787 /**
788 * @}
789 */
790
791 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
792 * @{
793 */
794 #define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CR2_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */
795 #define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CR2_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */
796 #define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CR2_EXTEN_1 | ADC_CR2_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
797 /**
798 * @}
799 */
800
801 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
802 * @{
803 */
804 #define LL_ADC_REG_CONV_SINGLE ((uint32_t)0x00000000U) /*!< ADC conversions are performed in single mode: one conversion per trigger */
805 #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CR2_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
806 /**
807 * @}
808 */
809
810 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
811 * @{
812 */
813 #define LL_ADC_REG_DMA_TRANSFER_NONE ((uint32_t)0x00000000U) /*!< ADC conversions are not transferred by DMA */
814 #define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CR2_DMA) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
815 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CR2_DDS | ADC_CR2_DMA) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
816 /**
817 * @}
818 */
819
820 /** @defgroup ADC_LL_EC_REG_FLAG_EOC_SELECTION ADC group regular - Flag EOC selection (unitary or sequence conversions)
821 * @{
822 */
823 #define LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV ((uint32_t)0x00000000U) /*!< ADC flag EOC (end of unitary conversion) selected */
824 #define LL_ADC_REG_FLAG_EOC_UNITARY_CONV ((uint32_t)ADC_CR2_EOCS) /*!< ADC flag EOS (end of sequence conversions) selected */
825 /**
826 * @}
827 */
828
829 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
830 * @{
831 */
832 #define LL_ADC_REG_SEQ_SCAN_DISABLE ((uint32_t)0x00000000U) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
833 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
834 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
835 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
836 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
837 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
838 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
839 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
840 #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
841 #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
842 #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
843 #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
844 #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
845 #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
846 #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
847 #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
848 /**
849 * @}
850 */
851
852 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
853 * @{
854 */
855 #define LL_ADC_REG_SEQ_DISCONT_DISABLE ((uint32_t)0x00000000U) /*!< ADC group regular sequencer discontinuous mode disable */
856 #define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
857 #define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
858 #define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
859 #define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
860 #define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
861 #define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
862 #define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
863 #define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
864 /**
865 * @}
866 */
867
868 /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
869 * @{
870 */
871 #define LL_ADC_REG_RANK_1 (ADC_SQR5_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */
872 #define LL_ADC_REG_RANK_2 (ADC_SQR5_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */
873 #define LL_ADC_REG_RANK_3 (ADC_SQR5_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */
874 #define LL_ADC_REG_RANK_4 (ADC_SQR5_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */
875 #define LL_ADC_REG_RANK_5 (ADC_SQR5_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */
876 #define LL_ADC_REG_RANK_6 (ADC_SQR5_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */
877 #define LL_ADC_REG_RANK_7 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */
878 #define LL_ADC_REG_RANK_8 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */
879 #define LL_ADC_REG_RANK_9 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */
880 #define LL_ADC_REG_RANK_10 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */
881 #define LL_ADC_REG_RANK_11 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */
882 #define LL_ADC_REG_RANK_12 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */
883 #define LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */
884 #define LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
885 #define LL_ADC_REG_RANK_15 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
886 #define LL_ADC_REG_RANK_16 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
887 #define LL_ADC_REG_RANK_17 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_17_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 17 */
888 #define LL_ADC_REG_RANK_18 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_18_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 18 */
889 #define LL_ADC_REG_RANK_19 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_19_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 19 */
890 #define LL_ADC_REG_RANK_20 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_20_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 20 */
891 #define LL_ADC_REG_RANK_21 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_21_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 21 */
892 #define LL_ADC_REG_RANK_22 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_22_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 22 */
893 #define LL_ADC_REG_RANK_23 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_23_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 23 */
894 #define LL_ADC_REG_RANK_24 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_24_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 24 */
895 #define LL_ADC_REG_RANK_25 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_25_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 25 */
896 #define LL_ADC_REG_RANK_26 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_26_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 26 */
897 #define LL_ADC_REG_RANK_27 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_27_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 27 */
898 #if defined(ADC_SQR1_SQ28)
899 #define LL_ADC_REG_RANK_28 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_28_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 28 */
900 #endif
901 /**
902 * @}
903 */
904
905 /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
906 * @{
907 */
908 #define LL_ADC_INJ_TRIG_SOFTWARE ((uint32_t)0x00000000U) /*!< ADC group injected conversion trigger internal: SW start. */
909 #define LL_ADC_INJ_TRIG_EXT_TIM9_CH1 (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM9 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
910 #define LL_ADC_INJ_TRIG_EXT_TIM9_TRGO (ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM9 TRGO. Trigger edge set to rising edge (default setting). */
911 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
912 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
913 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_CR2_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
914 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
915 #define LL_ADC_INJ_TRIG_EXT_TIM4_CH1 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
916 #define LL_ADC_INJ_TRIG_EXT_TIM4_CH2 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
917 #define LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (ADC_CR2_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
918 #define LL_ADC_INJ_TRIG_EXT_TIM10_CH1 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM10 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
919 #define LL_ADC_INJ_TRIG_EXT_TIM7_TRGO (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM7 TRGO. Trigger edge set to rising edge (default setting). */
920 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger external interrupt line 15. Trigger edge set to rising edge (default setting). */
921 /**
922 * @}
923 */
924
925 /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
926 * @{
927 */
928 #define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_CR2_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */
929 #define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_CR2_JEXTEN_1 ) /*!< ADC group injected conversion trigger polarity set to falling edge */
930 #define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_CR2_JEXTEN_1 | ADC_CR2_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */
931 /**
932 * @}
933 */
934
935 /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
936 * @{
937 */
938 #define LL_ADC_INJ_TRIG_INDEPENDENT ((uint32_t)0x00000000U)/*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
939 #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CR1_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
940 /**
941 * @}
942 */
943
944
945 /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
946 * @{
947 */
948 #define LL_ADC_INJ_SEQ_SCAN_DISABLE ((uint32_t)0x00000000U) /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
949 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
950 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
951 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
952 /**
953 * @}
954 */
955
956 /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
957 * @{
958 */
959 #define LL_ADC_INJ_SEQ_DISCONT_DISABLE ((uint32_t)0x00000000U)/*!< ADC group injected sequencer discontinuous mode disable */
960 #define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CR1_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
961 /**
962 * @}
963 */
964
965 /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
966 * @{
967 */
968 #define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 */
969 #define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 2 */
970 #define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 3 */
971 #define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 4 */
972 /**
973 * @}
974 */
975
976 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
977 * @{
978 */
979 #define LL_ADC_SAMPLINGTIME_4CYCLES ((uint32_t)0x00000000U) /*!< Sampling time 4 ADC clock cycles */
980 #define LL_ADC_SAMPLINGTIME_9CYCLES (ADC_SMPR3_SMP0_0) /*!< Sampling time 9 ADC clock cycles */
981 #define LL_ADC_SAMPLINGTIME_16CYCLES (ADC_SMPR3_SMP0_1) /*!< Sampling time 16 ADC clock cycles */
982 #define LL_ADC_SAMPLINGTIME_24CYCLES (ADC_SMPR3_SMP0_1 | ADC_SMPR3_SMP0_0) /*!< Sampling time 24 ADC clock cycles */
983 #define LL_ADC_SAMPLINGTIME_48CYCLES (ADC_SMPR3_SMP0_2) /*!< Sampling time 48 ADC clock cycles */
984 #define LL_ADC_SAMPLINGTIME_96CYCLES (ADC_SMPR3_SMP0_2 | ADC_SMPR3_SMP0_0) /*!< Sampling time 96 ADC clock cycles */
985 #define LL_ADC_SAMPLINGTIME_192CYCLES (ADC_SMPR3_SMP0_2 | ADC_SMPR3_SMP0_1) /*!< Sampling time 192 ADC clock cycles */
986 #define LL_ADC_SAMPLINGTIME_384CYCLES (ADC_SMPR3_SMP0_2 | ADC_SMPR3_SMP0_1 | ADC_SMPR3_SMP0_0) /*!< Sampling time 384 ADC clock cycles */
987 /**
988 * @}
989 */
990
991 #if defined(COMP_CSR_FCH3)
992 /** @defgroup ADC_LL_EC_CHANNEL_ROUTING_LIST Channel - Routing channels list
993 * @{
994 */
995 #define LL_ADC_CHANNEL_3_ROUTING (COMP_CSR_FCH3) /*!< ADC channel 3 routing. Used as ADC direct channel (fast channel) if OPAMP1 is in power down mode. */
996 #define LL_ADC_CHANNEL_8_ROUTING (COMP_CSR_FCH8) /*!< ADC channel 8 routing. Used as ADC direct channel (fast channel) if OPAMP2 is in power down mode. */
997 #define LL_ADC_CHANNEL_13_ROUTING (COMP_CSR_RCH13) /*!< ADC channel 13 routing. Used as ADC re-routed channel if OPAMP3 is in power down mode. Otherwise, channel 13 is connected to OPAMP3 output and routed through switches COMP1_SW1 and VCOMP to ADC switch matrix. (Note: OPAMP3 is available on STM32L1 Cat.4 only). */
998 /**
999 * @}
1000 */
1001
1002 /** @defgroup ADC_LL_EC_CHANNEL_ROUTING_SELECTION Channel - Routing selection
1003 * @{
1004 */
1005 #define LL_ADC_CHANNEL_ROUTING_DEFAULT ((uint32_t)0x00000000U) /*!< ADC channel routing default: slow channel */
1006 #define LL_ADC_CHANNEL_ROUTING_DIRECT ((uint32_t)0x00000001U) /*!< ADC channel routing direct: fast channel. */
1007 /**
1008 * @}
1009 */
1010 #endif
1011
1012 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
1013 * @{
1014 */
1015 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
1016 /**
1017 * @}
1018 */
1019
1020 /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
1021 * @{
1022 */
1023 #define LL_ADC_AWD_DISABLE ((uint32_t)0x00000000U) /*!< ADC analog watchdog monitoring disabled */
1024 #define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
1025 #define LL_ADC_AWD_ALL_CHANNELS_INJ ( ADC_CR1_JAWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
1026 #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ ( ADC_CR1_JAWDEN | ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
1027 #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
1028 #define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */
1029 #define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */
1030 #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
1031 #define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */
1032 #define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */
1033 #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
1034 #define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */
1035 #define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */
1036 #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
1037 #define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */
1038 #define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */
1039 #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
1040 #define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */
1041 #define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */
1042 #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
1043 #define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */
1044 #define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */
1045 #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
1046 #define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */
1047 #define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */
1048 #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
1049 #define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */
1050 #define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */
1051 #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
1052 #define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */
1053 #define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */
1054 #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
1055 #define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */
1056 #define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */
1057 #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
1058 #define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */
1059 #define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */
1060 #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
1061 #define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */
1062 #define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */
1063 #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
1064 #define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */
1065 #define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */
1066 #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
1067 #define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */
1068 #define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */
1069 #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
1070 #define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */
1071 #define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */
1072 #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
1073 #define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */
1074 #define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */
1075 #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
1076 #define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */
1077 #define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */
1078 #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
1079 #define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */
1080 #define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */
1081 #define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
1082 #define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */
1083 #define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */
1084 #define LL_ADC_AWD_CHANNEL_19_REG ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group regular only */
1085 #define LL_ADC_AWD_CHANNEL_19_INJ ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group injected only */
1086 #define LL_ADC_AWD_CHANNEL_19_REG_INJ ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by either group regular or injected */
1087 #define LL_ADC_AWD_CHANNEL_20_REG ((LL_ADC_CHANNEL_20 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN20, converted by group regular only */
1088 #define LL_ADC_AWD_CHANNEL_20_INJ ((LL_ADC_CHANNEL_20 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN20, converted by group injected only */
1089 #define LL_ADC_AWD_CHANNEL_20_REG_INJ ((LL_ADC_CHANNEL_20 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN20, converted by either group regular or injected */
1090 #define LL_ADC_AWD_CHANNEL_21_REG ((LL_ADC_CHANNEL_21 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN21, converted by group regular only */
1091 #define LL_ADC_AWD_CHANNEL_21_INJ ((LL_ADC_CHANNEL_21 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN21, converted by group injected only */
1092 #define LL_ADC_AWD_CHANNEL_21_REG_INJ ((LL_ADC_CHANNEL_21 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN21, converted by either group regular or injected */
1093 #define LL_ADC_AWD_CHANNEL_22_REG ((LL_ADC_CHANNEL_22 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN22, converted by group regular only */
1094 #define LL_ADC_AWD_CHANNEL_22_INJ ((LL_ADC_CHANNEL_22 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN22, converted by group injected only */
1095 #define LL_ADC_AWD_CHANNEL_22_REG_INJ ((LL_ADC_CHANNEL_22 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN22, converted by either group regular or injected */
1096 #define LL_ADC_AWD_CHANNEL_23_REG ((LL_ADC_CHANNEL_23 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN23, converted by group regular only */
1097 #define LL_ADC_AWD_CHANNEL_23_INJ ((LL_ADC_CHANNEL_23 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN23, converted by group injected only */
1098 #define LL_ADC_AWD_CHANNEL_23_REG_INJ ((LL_ADC_CHANNEL_23 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN23, converted by either group regular or injected */
1099 #define LL_ADC_AWD_CHANNEL_24_REG ((LL_ADC_CHANNEL_24 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN24, converted by group regular only */
1100 #define LL_ADC_AWD_CHANNEL_24_INJ ((LL_ADC_CHANNEL_24 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN24, converted by group injected only */
1101 #define LL_ADC_AWD_CHANNEL_24_REG_INJ ((LL_ADC_CHANNEL_24 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN24, converted by either group regular or injected */
1102 #define LL_ADC_AWD_CHANNEL_25_REG ((LL_ADC_CHANNEL_25 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN25, converted by group regular only */
1103 #define LL_ADC_AWD_CHANNEL_25_INJ ((LL_ADC_CHANNEL_25 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN25, converted by group injected only */
1104 #define LL_ADC_AWD_CHANNEL_25_REG_INJ ((LL_ADC_CHANNEL_25 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN25, converted by either group regular or injected */
1105 #define LL_ADC_AWD_CHANNEL_26_REG ((LL_ADC_CHANNEL_26 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN26, converted by group regular only */
1106 #define LL_ADC_AWD_CHANNEL_26_INJ ((LL_ADC_CHANNEL_26 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN26, converted by group injected only */
1107 #define LL_ADC_AWD_CHANNEL_26_REG_INJ ((LL_ADC_CHANNEL_26 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN26, converted by either group regular or injected */
1108 #if defined(ADC_SMPR0_SMP31)
1109 #define LL_ADC_AWD_CHANNEL_27_REG ((LL_ADC_CHANNEL_27 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN27, converted by group regular only. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */
1110 #define LL_ADC_AWD_CHANNEL_27_INJ ((LL_ADC_CHANNEL_27 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN27, converted by group injected only. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */
1111 #define LL_ADC_AWD_CHANNEL_27_REG_INJ ((LL_ADC_CHANNEL_27 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN27, converted by either group regular or injected. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */
1112 #define LL_ADC_AWD_CHANNEL_28_REG ((LL_ADC_CHANNEL_28 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN28, converted by group regular only. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */
1113 #define LL_ADC_AWD_CHANNEL_28_INJ ((LL_ADC_CHANNEL_28 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN28, converted by group injected only. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */
1114 #define LL_ADC_AWD_CHANNEL_28_REG_INJ ((LL_ADC_CHANNEL_28 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN28, converted by either group regular or injected. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */
1115 #define LL_ADC_AWD_CHANNEL_29_REG ((LL_ADC_CHANNEL_29 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN29, converted by group regular only. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */
1116 #define LL_ADC_AWD_CHANNEL_29_INJ ((LL_ADC_CHANNEL_29 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN29, converted by group injected only. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */
1117 #define LL_ADC_AWD_CHANNEL_29_REG_INJ ((LL_ADC_CHANNEL_29 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN29, converted by either group regular or injected. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */
1118 #define LL_ADC_AWD_CHANNEL_30_REG ((LL_ADC_CHANNEL_30 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN30, converted by group regular only. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */
1119 #define LL_ADC_AWD_CHANNEL_30_INJ ((LL_ADC_CHANNEL_30 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN30, converted by group injected only. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */
1120 #define LL_ADC_AWD_CHANNEL_30_REG_INJ ((LL_ADC_CHANNEL_30 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN30, converted by either group regular or injected. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */
1121 #define LL_ADC_AWD_CHANNEL_31_REG ((LL_ADC_CHANNEL_31 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN31, converted by group regular only. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */
1122 #define LL_ADC_AWD_CHANNEL_31_INJ ((LL_ADC_CHANNEL_31 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN31, converted by group injected only. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */
1123 #define LL_ADC_AWD_CHANNEL_31_REG_INJ ((LL_ADC_CHANNEL_31 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN31, converted by either group regular or injected. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */
1124 #endif /* ADC_SMPR0_SMP31 */
1125 #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only. Channel common to both bank A and bank B. */
1126 #define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only. Channel common to both bank A and bank B. */
1127 #define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected. Channel common to both bank A and bank B. */
1128 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only. Channel common to both bank A and bank B. */
1129 #define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only. Channel common to both bank A and bank B. */
1130 #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected. Channel common to both bank A and bank B. */
1131 #define LL_ADC_AWD_CH_VCOMP_REG ((LL_ADC_CHANNEL_VCOMP & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to comparator COMP1 positive input via ADC switch matrix. Channel common to both bank A and bank B. */
1132 #define LL_ADC_AWD_CH_VCOMP_INJ ((LL_ADC_CHANNEL_VCOMP & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to comparator COMP1 positive input via ADC switch matrix. Channel common to both bank A and bank B. */
1133 #define LL_ADC_AWD_CH_VCOMP_REG_INJ ((LL_ADC_CHANNEL_VCOMP & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to comparator COMP1 positive input via ADC switch matrix. Channel common to both bank A and bank B. */
1134 #if defined(OPAMP_CSR_OPA1PD) || defined (OPAMP_CSR_OPA2PD) || defined (OPAMP_CSR_OPA3PD)
1135 #define LL_ADC_AWD_CH_VOPAMP1_REG ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP1 output via ADC switch matrix. Channel common to both bank A and bank B. */
1136 #define LL_ADC_AWD_CH_VOPAMP1_INJ ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP1 output via ADC switch matrix. Channel common to both bank A and bank B. */
1137 #define LL_ADC_AWD_CH_VOPAMP1_REG_INJ ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP1 output via ADC switch matrix. Channel common to both bank A and bank B. */
1138 #define LL_ADC_AWD_CH_VOPAMP2_REG ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP2 output via ADC switch matrix. Channel common to both bank A and bank B. */
1139 #define LL_ADC_AWD_CH_VOPAMP2_INJ ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP2 output via ADC switch matrix. Channel common to both bank A and bank B. */
1140 #define LL_ADC_AWD_CH_VOPAMP2_REG_INJ ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP2 output via ADC switch matrix. Channel common to both bank A and bank B. */
1141 #if defined(OPAMP_CSR_OPA3PD)
1142 #define LL_ADC_AWD_CH_VOPAMP3_REG ((LL_ADC_CHANNEL_VOPAMP3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output via ADC switch matrix. Channel common to both bank A and bank B. */
1143 #define LL_ADC_AWD_CH_VOPAMP3_INJ ((LL_ADC_CHANNEL_VOPAMP3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output via ADC switch matrix. Channel common to both bank A and bank B. */
1144 #define LL_ADC_AWD_CH_VOPAMP3_REG_INJ ((LL_ADC_CHANNEL_VOPAMP3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output via ADC switch matrix. Channel common to both bank A and bank B. */
1145 #endif /* OPAMP_CSR_OPA3PD */
1146 #endif /* OPAMP_CSR_OPA1PD || OPAMP_CSR_OPA2PD || OPAMP_CSR_OPA3PD */
1147 /**
1148 * @}
1149 */
1150
1151 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
1152 * @{
1153 */
1154 #define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD_TR1_HIGH_REGOFFSET) /*!< ADC analog watchdog threshold high */
1155 #define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD_TR1_LOW_REGOFFSET) /*!< ADC analog watchdog threshold low */
1156 /**
1157 * @}
1158 */
1159
1160
1161 /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
1162 * @note Only ADC IP HW delays are defined in ADC LL driver driver,
1163 * not timeout values.
1164 * For details on delays values, refer to descriptions in source code
1165 * above each literal definition.
1166 * @{
1167 */
1168
1169 /* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
1170 /* not timeout values. */
1171 /* Timeout values for ADC operations are dependent to device clock */
1172 /* configuration (system clock versus ADC clock), */
1173 /* and therefore must be defined in user application. */
1174 /* Indications for estimation of ADC timeout delays, for this */
1175 /* STM32 serie: */
1176 /* - ADC enable time: maximum delay is 3.5us */
1177 /* (refer to device datasheet, parameter "tSTAB") */
1178 /* - ADC conversion time: duration depending on ADC clock and ADC */
1179 /* configuration. */
1180 /* (refer to device reference manual, section "Timing") */
1181
1182 /* Delay for internal voltage reference stabilization time. */
1183 /* Delay set to maximum value (refer to device datasheet, */
1184 /* parameter "TADC_BUF"). */
1185 /* Unit: us */
1186 #define LL_ADC_DELAY_VREFINT_STAB_US ((uint32_t) 10U) /*!< Delay for internal voltage reference stabilization time */
1187
1188 /* Delay for temperature sensor stabilization time. */
1189 /* Literal set to maximum value (refer to device datasheet, */
1190 /* parameter "tSTART"). */
1191 /* Unit: us */
1192 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US ((uint32_t) 10U) /*!< Delay for internal voltage reference stabilization time */
1193
1194 /**
1195 * @}
1196 */
1197
1198 /**
1199 * @}
1200 */
1201
1202
1203 /* Exported macro ------------------------------------------------------------*/
1204 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
1205 * @{
1206 */
1207
1208 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
1209 * @{
1210 */
1211
1212 /**
1213 * @brief Write a value in ADC register
1214 * @param __INSTANCE__ ADC Instance
1215 * @param __REG__ Register to be written
1216 * @param __VALUE__ Value to be written in the register
1217 * @retval None
1218 */
1219 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
1220
1221 /**
1222 * @brief Read a value in ADC register
1223 * @param __INSTANCE__ ADC Instance
1224 * @param __REG__ Register to be read
1225 * @retval Register value
1226 */
1227 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1228 /**
1229 * @}
1230 */
1231
1232 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
1233 * @{
1234 */
1235
1236 /**
1237 * @brief Helper macro to get ADC channel number in decimal format
1238 * from literals LL_ADC_CHANNEL_x.
1239 * @note Example:
1240 * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
1241 * will return decimal number "4".
1242 * @note The input can be a value from functions where a channel
1243 * number is returned, either defined with number
1244 * or with bitfield (only one bit must be set).
1245 * @param __CHANNEL__ This parameter can be one of the following values:
1246 * @arg @ref LL_ADC_CHANNEL_0 (2)
1247 * @arg @ref LL_ADC_CHANNEL_1 (2)
1248 * @arg @ref LL_ADC_CHANNEL_2 (2)
1249 * @arg @ref LL_ADC_CHANNEL_3 (2)
1250 * @arg @ref LL_ADC_CHANNEL_4 (1)
1251 * @arg @ref LL_ADC_CHANNEL_5 (1)
1252 * @arg @ref LL_ADC_CHANNEL_6 (2)
1253 * @arg @ref LL_ADC_CHANNEL_7 (2)
1254 * @arg @ref LL_ADC_CHANNEL_8 (2)
1255 * @arg @ref LL_ADC_CHANNEL_9 (2)
1256 * @arg @ref LL_ADC_CHANNEL_10 (2)
1257 * @arg @ref LL_ADC_CHANNEL_11 (2)
1258 * @arg @ref LL_ADC_CHANNEL_12 (2)
1259 * @arg @ref LL_ADC_CHANNEL_13 (3)
1260 * @arg @ref LL_ADC_CHANNEL_14 (3)
1261 * @arg @ref LL_ADC_CHANNEL_15 (3)
1262 * @arg @ref LL_ADC_CHANNEL_16 (3)
1263 * @arg @ref LL_ADC_CHANNEL_17 (3)
1264 * @arg @ref LL_ADC_CHANNEL_18 (3)
1265 * @arg @ref LL_ADC_CHANNEL_19 (3)
1266 * @arg @ref LL_ADC_CHANNEL_20 (3)
1267 * @arg @ref LL_ADC_CHANNEL_21 (3)
1268 * @arg @ref LL_ADC_CHANNEL_22 (1)
1269 * @arg @ref LL_ADC_CHANNEL_23 (1)
1270 * @arg @ref LL_ADC_CHANNEL_24 (1)
1271 * @arg @ref LL_ADC_CHANNEL_25 (1)
1272 * @arg @ref LL_ADC_CHANNEL_26 (3)
1273 * @arg @ref LL_ADC_CHANNEL_27 (3)(4)
1274 * @arg @ref LL_ADC_CHANNEL_28 (3)(4)
1275 * @arg @ref LL_ADC_CHANNEL_29 (3)(4)
1276 * @arg @ref LL_ADC_CHANNEL_30 (3)(4)
1277 * @arg @ref LL_ADC_CHANNEL_31 (3)(4)
1278 * @arg @ref LL_ADC_CHANNEL_VREFINT (3)
1279 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)
1280 * @arg @ref LL_ADC_CHANNEL_VCOMP (3)
1281 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (3)(5)
1282 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (3)(5)
1283 * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)(5)
1284 *
1285 * (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n
1286 * (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n
1287 * (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n
1288 * (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n
1289 * (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5
1290 * @retval Value between Min_Data=0 and Max_Data=18
1291 */
1292 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
1293 (((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
1294
1295 /**
1296 * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
1297 * from number in decimal format.
1298 * @note Example:
1299 * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
1300 * will return a data equivalent to "LL_ADC_CHANNEL_4".
1301 * @param __DECIMAL_NB__: Value between Min_Data=0 and Max_Data=18
1302 * @retval Returned value can be one of the following values:
1303 * @arg @ref LL_ADC_CHANNEL_0 (2)
1304 * @arg @ref LL_ADC_CHANNEL_1 (2)
1305 * @arg @ref LL_ADC_CHANNEL_2 (2)
1306 * @arg @ref LL_ADC_CHANNEL_3 (2)
1307 * @arg @ref LL_ADC_CHANNEL_4 (1)
1308 * @arg @ref LL_ADC_CHANNEL_5 (1)
1309 * @arg @ref LL_ADC_CHANNEL_6 (2)
1310 * @arg @ref LL_ADC_CHANNEL_7 (2)
1311 * @arg @ref LL_ADC_CHANNEL_8 (2)
1312 * @arg @ref LL_ADC_CHANNEL_9 (2)
1313 * @arg @ref LL_ADC_CHANNEL_10 (2)
1314 * @arg @ref LL_ADC_CHANNEL_11 (2)
1315 * @arg @ref LL_ADC_CHANNEL_12 (2)
1316 * @arg @ref LL_ADC_CHANNEL_13 (3)
1317 * @arg @ref LL_ADC_CHANNEL_14 (3)
1318 * @arg @ref LL_ADC_CHANNEL_15 (3)
1319 * @arg @ref LL_ADC_CHANNEL_16 (3)
1320 * @arg @ref LL_ADC_CHANNEL_17 (3)
1321 * @arg @ref LL_ADC_CHANNEL_18 (3)
1322 * @arg @ref LL_ADC_CHANNEL_19 (3)
1323 * @arg @ref LL_ADC_CHANNEL_20 (3)
1324 * @arg @ref LL_ADC_CHANNEL_21 (3)
1325 * @arg @ref LL_ADC_CHANNEL_22 (1)
1326 * @arg @ref LL_ADC_CHANNEL_23 (1)
1327 * @arg @ref LL_ADC_CHANNEL_24 (1)
1328 * @arg @ref LL_ADC_CHANNEL_25 (1)
1329 * @arg @ref LL_ADC_CHANNEL_26 (3)
1330 * @arg @ref LL_ADC_CHANNEL_27 (3)(4)
1331 * @arg @ref LL_ADC_CHANNEL_28 (3)(4)
1332 * @arg @ref LL_ADC_CHANNEL_29 (3)(4)
1333 * @arg @ref LL_ADC_CHANNEL_30 (3)(4)
1334 * @arg @ref LL_ADC_CHANNEL_31 (3)(4)
1335 * @arg @ref LL_ADC_CHANNEL_VREFINT (3)(6)
1336 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)(6)
1337 * @arg @ref LL_ADC_CHANNEL_VCOMP (3)(6)
1338 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (3)(5)
1339 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (3)(5)
1340 * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)(5)
1341 *
1342 * (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n
1343 * (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n
1344 * (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n
1345 * (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n
1346 * (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5.\n
1347 * (6) For ADC channel read back from ADC register,
1348 * comparison with internal channel parameter to be done
1349 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1350 */
1351 #if defined(ADC_SMPR0_SMP31)
1352 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
1353 (((__DECIMAL_NB__) <= 9U) \
1354 ? ( \
1355 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1356 (ADC_SMPR3_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1357 ) \
1358 : \
1359 (((__DECIMAL_NB__) <= 19U) \
1360 ? ( \
1361 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1362 (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) -10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1363 ) \
1364 : \
1365 (((__DECIMAL_NB__) <= 28U) \
1366 ? ( \
1367 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1368 (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) -20U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1369 ) \
1370 : \
1371 ( \
1372 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1373 (ADC_SMPR0_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 30U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1374 ) \
1375 ) \
1376 ) \
1377 )
1378 #else
1379 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
1380 (((__DECIMAL_NB__) <= 9U) \
1381 ? ( \
1382 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1383 (ADC_SMPR3_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1384 ) \
1385 : \
1386 (((__DECIMAL_NB__) <= 19U) \
1387 ? ( \
1388 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1389 (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) -10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1390 ) \
1391 : \
1392 ( \
1393 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1394 (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) -20U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1395 ) \
1396 ) \
1397 )
1398 #endif /* ADC_SMPR0_SMP31 */
1399
1400 /**
1401 * @brief Helper macro to determine whether the selected channel
1402 * corresponds to literal definitions of driver.
1403 * @note The different literal definitions of ADC channels are:
1404 * - ADC internal channel:
1405 * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
1406 * - ADC external channel (channel connected to a GPIO pin):
1407 * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
1408 * @note The channel parameter must be a value defined from literal
1409 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1410 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1411 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
1412 * must not be a value from functions where a channel number is
1413 * returned from ADC registers,
1414 * because internal and external channels share the same channel
1415 * number in ADC registers. The differentiation is made only with
1416 * parameters definitions of driver.
1417 * @param __CHANNEL__ This parameter can be one of the following values:
1418 * @arg @ref LL_ADC_CHANNEL_0 (2)
1419 * @arg @ref LL_ADC_CHANNEL_1 (2)
1420 * @arg @ref LL_ADC_CHANNEL_2 (2)
1421 * @arg @ref LL_ADC_CHANNEL_3 (2)
1422 * @arg @ref LL_ADC_CHANNEL_4 (1)
1423 * @arg @ref LL_ADC_CHANNEL_5 (1)
1424 * @arg @ref LL_ADC_CHANNEL_6 (2)
1425 * @arg @ref LL_ADC_CHANNEL_7 (2)
1426 * @arg @ref LL_ADC_CHANNEL_8 (2)
1427 * @arg @ref LL_ADC_CHANNEL_9 (2)
1428 * @arg @ref LL_ADC_CHANNEL_10 (2)
1429 * @arg @ref LL_ADC_CHANNEL_11 (2)
1430 * @arg @ref LL_ADC_CHANNEL_12 (2)
1431 * @arg @ref LL_ADC_CHANNEL_13 (3)
1432 * @arg @ref LL_ADC_CHANNEL_14 (3)
1433 * @arg @ref LL_ADC_CHANNEL_15 (3)
1434 * @arg @ref LL_ADC_CHANNEL_16 (3)
1435 * @arg @ref LL_ADC_CHANNEL_17 (3)
1436 * @arg @ref LL_ADC_CHANNEL_18 (3)
1437 * @arg @ref LL_ADC_CHANNEL_19 (3)
1438 * @arg @ref LL_ADC_CHANNEL_20 (3)
1439 * @arg @ref LL_ADC_CHANNEL_21 (3)
1440 * @arg @ref LL_ADC_CHANNEL_22 (1)
1441 * @arg @ref LL_ADC_CHANNEL_23 (1)
1442 * @arg @ref LL_ADC_CHANNEL_24 (1)
1443 * @arg @ref LL_ADC_CHANNEL_25 (1)
1444 * @arg @ref LL_ADC_CHANNEL_26 (3)
1445 * @arg @ref LL_ADC_CHANNEL_27 (3)(4)
1446 * @arg @ref LL_ADC_CHANNEL_28 (3)(4)
1447 * @arg @ref LL_ADC_CHANNEL_29 (3)(4)
1448 * @arg @ref LL_ADC_CHANNEL_30 (3)(4)
1449 * @arg @ref LL_ADC_CHANNEL_31 (3)(4)
1450 * @arg @ref LL_ADC_CHANNEL_VREFINT (3)
1451 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)
1452 * @arg @ref LL_ADC_CHANNEL_VCOMP (3)
1453 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (3)(5)
1454 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (3)(5)
1455 * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)(5)
1456 *
1457 * (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n
1458 * (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n
1459 * (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n
1460 * (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n
1461 * (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5
1462 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
1463 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
1464 */
1465 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
1466 (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)
1467
1468 /**
1469 * @brief Helper macro to convert a channel defined from parameter
1470 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1471 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1472 * to its equivalent parameter definition of a ADC external channel
1473 * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
1474 * @note The channel parameter can be, additionally to a value
1475 * defined from parameter definition of a ADC internal channel
1476 * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
1477 * a value defined from parameter definition of
1478 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1479 * or a value from functions where a channel number is returned
1480 * from ADC registers.
1481 * @param __CHANNEL__ This parameter can be one of the following values:
1482 * @arg @ref LL_ADC_CHANNEL_0 (2)
1483 * @arg @ref LL_ADC_CHANNEL_1 (2)
1484 * @arg @ref LL_ADC_CHANNEL_2 (2)
1485 * @arg @ref LL_ADC_CHANNEL_3 (2)
1486 * @arg @ref LL_ADC_CHANNEL_4 (1)
1487 * @arg @ref LL_ADC_CHANNEL_5 (1)
1488 * @arg @ref LL_ADC_CHANNEL_6 (2)
1489 * @arg @ref LL_ADC_CHANNEL_7 (2)
1490 * @arg @ref LL_ADC_CHANNEL_8 (2)
1491 * @arg @ref LL_ADC_CHANNEL_9 (2)
1492 * @arg @ref LL_ADC_CHANNEL_10 (2)
1493 * @arg @ref LL_ADC_CHANNEL_11 (2)
1494 * @arg @ref LL_ADC_CHANNEL_12 (2)
1495 * @arg @ref LL_ADC_CHANNEL_13 (3)
1496 * @arg @ref LL_ADC_CHANNEL_14 (3)
1497 * @arg @ref LL_ADC_CHANNEL_15 (3)
1498 * @arg @ref LL_ADC_CHANNEL_16 (3)
1499 * @arg @ref LL_ADC_CHANNEL_17 (3)
1500 * @arg @ref LL_ADC_CHANNEL_18 (3)
1501 * @arg @ref LL_ADC_CHANNEL_19 (3)
1502 * @arg @ref LL_ADC_CHANNEL_20 (3)
1503 * @arg @ref LL_ADC_CHANNEL_21 (3)
1504 * @arg @ref LL_ADC_CHANNEL_22 (1)
1505 * @arg @ref LL_ADC_CHANNEL_23 (1)
1506 * @arg @ref LL_ADC_CHANNEL_24 (1)
1507 * @arg @ref LL_ADC_CHANNEL_25 (1)
1508 * @arg @ref LL_ADC_CHANNEL_26 (3)
1509 * @arg @ref LL_ADC_CHANNEL_27 (3)(4)
1510 * @arg @ref LL_ADC_CHANNEL_28 (3)(4)
1511 * @arg @ref LL_ADC_CHANNEL_29 (3)(4)
1512 * @arg @ref LL_ADC_CHANNEL_30 (3)(4)
1513 * @arg @ref LL_ADC_CHANNEL_31 (3)(4)
1514 * @arg @ref LL_ADC_CHANNEL_VREFINT (3)
1515 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)
1516 * @arg @ref LL_ADC_CHANNEL_VCOMP (3)
1517 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (3)(5)
1518 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (3)(5)
1519 * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)(5)
1520 *
1521 * (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n
1522 * (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n
1523 * (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n
1524 * (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n
1525 * (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5
1526 * @retval Returned value can be one of the following values:
1527 * @arg @ref LL_ADC_CHANNEL_0
1528 * @arg @ref LL_ADC_CHANNEL_1
1529 * @arg @ref LL_ADC_CHANNEL_2
1530 * @arg @ref LL_ADC_CHANNEL_3
1531 * @arg @ref LL_ADC_CHANNEL_4
1532 * @arg @ref LL_ADC_CHANNEL_5
1533 * @arg @ref LL_ADC_CHANNEL_6
1534 * @arg @ref LL_ADC_CHANNEL_7
1535 * @arg @ref LL_ADC_CHANNEL_8
1536 * @arg @ref LL_ADC_CHANNEL_9
1537 * @arg @ref LL_ADC_CHANNEL_10
1538 * @arg @ref LL_ADC_CHANNEL_11
1539 * @arg @ref LL_ADC_CHANNEL_12
1540 * @arg @ref LL_ADC_CHANNEL_13
1541 * @arg @ref LL_ADC_CHANNEL_14
1542 * @arg @ref LL_ADC_CHANNEL_15
1543 * @arg @ref LL_ADC_CHANNEL_16
1544 * @arg @ref LL_ADC_CHANNEL_17
1545 * @arg @ref LL_ADC_CHANNEL_18
1546 */
1547 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
1548 ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
1549
1550 /**
1551 * @brief Helper macro to determine whether the internal channel
1552 * selected is available on the ADC instance selected.
1553 * @note The channel parameter must be a value defined from parameter
1554 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1555 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1556 * must not be a value defined from parameter definition of
1557 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1558 * or a value from functions where a channel number is
1559 * returned from ADC registers,
1560 * because internal and external channels share the same channel
1561 * number in ADC registers. The differentiation is made only with
1562 * parameters definitions of driver.
1563 * @param __ADC_INSTANCE__ ADC instance
1564 * @param __CHANNEL__ This parameter can be one of the following values:
1565 * @arg @ref LL_ADC_CHANNEL_VREFINT (3)
1566 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)
1567 * @arg @ref LL_ADC_CHANNEL_VCOMP (3)
1568 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (3)(5)
1569 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (3)(5)
1570 * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)(5)
1571 *
1572 * (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n
1573 * (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n
1574 * (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n
1575 * (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n
1576 * (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5
1577 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
1578 * Value "1" if the internal channel selected is available on the ADC instance selected.
1579 */
1580 #if defined (OPAMP_CSR_OPA3PD)
1581 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1582 ( \
1583 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1584 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1585 ((__CHANNEL__) == LL_ADC_CHANNEL_VCOMP) || \
1586 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) || \
1587 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) || \
1588 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3) \
1589 )
1590 #elif defined(OPAMP_CSR_OPA1PD) || defined (OPAMP_CSR_OPA2PD)
1591 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1592 ( \
1593 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1594 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1595 ((__CHANNEL__) == LL_ADC_CHANNEL_VCOMP) || \
1596 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) || \
1597 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) \
1598 )
1599 #else
1600 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1601 ( \
1602 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1603 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1604 ((__CHANNEL__) == LL_ADC_CHANNEL_VCOMP) \
1605 )
1606 #endif
1607
1608 /**
1609 * @brief Helper macro to define ADC analog watchdog parameter:
1610 * define a single channel to monitor with analog watchdog
1611 * from sequencer channel and groups definition.
1612 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
1613 * Example:
1614 * LL_ADC_SetAnalogWDMonitChannels(
1615 * ADC1, LL_ADC_AWD1,
1616 * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
1617 * @param __CHANNEL__ This parameter can be one of the following values:
1618 * @arg @ref LL_ADC_CHANNEL_0 (2)
1619 * @arg @ref LL_ADC_CHANNEL_1 (2)
1620 * @arg @ref LL_ADC_CHANNEL_2 (2)
1621 * @arg @ref LL_ADC_CHANNEL_3 (2)
1622 * @arg @ref LL_ADC_CHANNEL_4 (1)
1623 * @arg @ref LL_ADC_CHANNEL_5 (1)
1624 * @arg @ref LL_ADC_CHANNEL_6 (2)
1625 * @arg @ref LL_ADC_CHANNEL_7 (2)
1626 * @arg @ref LL_ADC_CHANNEL_8 (2)
1627 * @arg @ref LL_ADC_CHANNEL_9 (2)
1628 * @arg @ref LL_ADC_CHANNEL_10 (2)
1629 * @arg @ref LL_ADC_CHANNEL_11 (2)
1630 * @arg @ref LL_ADC_CHANNEL_12 (2)
1631 * @arg @ref LL_ADC_CHANNEL_13 (3)
1632 * @arg @ref LL_ADC_CHANNEL_14 (3)
1633 * @arg @ref LL_ADC_CHANNEL_15 (3)
1634 * @arg @ref LL_ADC_CHANNEL_16 (3)
1635 * @arg @ref LL_ADC_CHANNEL_17 (3)
1636 * @arg @ref LL_ADC_CHANNEL_18 (3)
1637 * @arg @ref LL_ADC_CHANNEL_19 (3)
1638 * @arg @ref LL_ADC_CHANNEL_20 (3)
1639 * @arg @ref LL_ADC_CHANNEL_21 (3)
1640 * @arg @ref LL_ADC_CHANNEL_22 (1)
1641 * @arg @ref LL_ADC_CHANNEL_23 (1)
1642 * @arg @ref LL_ADC_CHANNEL_24 (1)
1643 * @arg @ref LL_ADC_CHANNEL_25 (1)
1644 * @arg @ref LL_ADC_CHANNEL_26 (3)
1645 * @arg @ref LL_ADC_CHANNEL_27 (3)(4)
1646 * @arg @ref LL_ADC_CHANNEL_28 (3)(4)
1647 * @arg @ref LL_ADC_CHANNEL_29 (3)(4)
1648 * @arg @ref LL_ADC_CHANNEL_30 (3)(4)
1649 * @arg @ref LL_ADC_CHANNEL_31 (3)(4)
1650 * @arg @ref LL_ADC_CHANNEL_VREFINT (3)(6)
1651 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)(6)
1652 * @arg @ref LL_ADC_CHANNEL_VCOMP (3)(6)
1653 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (3)(5)
1654 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (3)(5)
1655 * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)(5)
1656 *
1657 * (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n
1658 * (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n
1659 * (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n
1660 * (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n
1661 * (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5.\n
1662 * (6) For ADC channel read back from ADC register,
1663 * comparison with internal channel parameter to be done
1664 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1665 * @param __GROUP__ This parameter can be one of the following values:
1666 * @arg @ref LL_ADC_GROUP_REGULAR
1667 * @arg @ref LL_ADC_GROUP_INJECTED
1668 * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
1669 * @retval Returned value can be one of the following values:
1670 * @arg @ref LL_ADC_AWD_DISABLE
1671 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
1672 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
1673 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
1674 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (2)
1675 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (2)
1676 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ (2)
1677 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (2)
1678 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (2)
1679 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ (2)
1680 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (2)
1681 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (2)
1682 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ (2)
1683 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (2)
1684 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (2)
1685 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ (2)
1686 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (1)
1687 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (1)
1688 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ (1)
1689 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (1)
1690 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (1)
1691 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ (1)
1692 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (2)
1693 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (2)
1694 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ (2)
1695 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (2)
1696 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (2)
1697 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ (2)
1698 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (2)
1699 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (2)
1700 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ (2)
1701 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (2)
1702 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (2)
1703 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ (2)
1704 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (2)
1705 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (2)
1706 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ (2)
1707 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (2)
1708 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (2)
1709 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ (2)
1710 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (2)
1711 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (2)
1712 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ (2)
1713 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (3)
1714 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (3)
1715 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ (3)
1716 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (3)
1717 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (3)
1718 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ (3)
1719 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (3)
1720 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (3)
1721 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ (3)
1722 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (3)
1723 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (3)
1724 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ (3)
1725 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (3)
1726 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (3)
1727 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ (3)
1728 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (3)
1729 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (3)
1730 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ (3)
1731 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG (3)
1732 * @arg @ref LL_ADC_AWD_CHANNEL_19_INJ (3)
1733 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ (3)
1734 * @arg @ref LL_ADC_AWD_CHANNEL_20_REG (3)
1735 * @arg @ref LL_ADC_AWD_CHANNEL_20_INJ (3)
1736 * @arg @ref LL_ADC_AWD_CHANNEL_20_REG_INJ (3)
1737 * @arg @ref LL_ADC_AWD_CHANNEL_21_REG (3)
1738 * @arg @ref LL_ADC_AWD_CHANNEL_21_INJ (3)
1739 * @arg @ref LL_ADC_AWD_CHANNEL_21_REG_INJ (3)
1740 * @arg @ref LL_ADC_AWD_CHANNEL_22_REG (1)
1741 * @arg @ref LL_ADC_AWD_CHANNEL_22_INJ (1)
1742 * @arg @ref LL_ADC_AWD_CHANNEL_22_REG_INJ (1)
1743 * @arg @ref LL_ADC_AWD_CHANNEL_23_REG (1)
1744 * @arg @ref LL_ADC_AWD_CHANNEL_23_INJ (1)
1745 * @arg @ref LL_ADC_AWD_CHANNEL_23_REG_INJ (1)
1746 * @arg @ref LL_ADC_AWD_CHANNEL_24_REG (1)
1747 * @arg @ref LL_ADC_AWD_CHANNEL_24_INJ (1)
1748 * @arg @ref LL_ADC_AWD_CHANNEL_24_REG_INJ (1)
1749 * @arg @ref LL_ADC_AWD_CHANNEL_25_REG (1)
1750 * @arg @ref LL_ADC_AWD_CHANNEL_25_INJ (1)
1751 * @arg @ref LL_ADC_AWD_CHANNEL_25_REG_INJ (1)
1752 * @arg @ref LL_ADC_AWD_CHANNEL_26_REG (3)
1753 * @arg @ref LL_ADC_AWD_CHANNEL_26_INJ (3)
1754 * @arg @ref LL_ADC_AWD_CHANNEL_26_REG_INJ (3)
1755 * @arg @ref LL_ADC_AWD_CHANNEL_27_REG (3)(4)
1756 * @arg @ref LL_ADC_AWD_CHANNEL_27_INJ (3)(4)
1757 * @arg @ref LL_ADC_AWD_CHANNEL_27_REG_INJ (3)(4)
1758 * @arg @ref LL_ADC_AWD_CHANNEL_28_REG (3)(4)
1759 * @arg @ref LL_ADC_AWD_CHANNEL_28_INJ (3)(4)
1760 * @arg @ref LL_ADC_AWD_CHANNEL_28_REG_INJ (3)(4)
1761 * @arg @ref LL_ADC_AWD_CHANNEL_29_REG (3)(4)
1762 * @arg @ref LL_ADC_AWD_CHANNEL_29_INJ (3)(4)
1763 * @arg @ref LL_ADC_AWD_CHANNEL_29_REG_INJ (3)(4)
1764 * @arg @ref LL_ADC_AWD_CHANNEL_30_REG (3)(4)
1765 * @arg @ref LL_ADC_AWD_CHANNEL_30_INJ (3)(4)
1766 * @arg @ref LL_ADC_AWD_CHANNEL_30_REG_INJ (3)(4)
1767 * @arg @ref LL_ADC_AWD_CHANNEL_31_REG (3)(4)
1768 * @arg @ref LL_ADC_AWD_CHANNEL_31_INJ (3)(4)
1769 * @arg @ref LL_ADC_AWD_CHANNEL_31_REG_INJ (3)(4)
1770 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (3)
1771 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (3)
1772 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (3)
1773 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (3)
1774 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (3)
1775 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (3)
1776 * @arg @ref LL_ADC_AWD_CH_VCOMP_REG (3)
1777 * @arg @ref LL_ADC_AWD_CH_VCOMP_INJ (3)
1778 * @arg @ref LL_ADC_AWD_CH_VCOMP_REG_INJ (3)
1779 * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG (3)(5)
1780 * @arg @ref LL_ADC_AWD_CH_VOPAMP1_INJ (3)(5)
1781 * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG_INJ (3)(5)
1782 * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG (3)(5)
1783 * @arg @ref LL_ADC_AWD_CH_VOPAMP2_INJ (3)(5)
1784 * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG_INJ (3)(5)
1785 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_REG (3)(5)
1786 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_INJ (3)(5)
1787 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_REG_INJ (3)(5)
1788 *
1789 * (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n
1790 * (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n
1791 * (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n
1792 * (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n
1793 * (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5
1794 */
1795 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
1796 (((__GROUP__) == LL_ADC_GROUP_REGULAR) \
1797 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \
1798 : \
1799 ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
1800 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) \
1801 : \
1802 (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \
1803 )
1804
1805 /**
1806 * @brief Helper macro to set the value of ADC analog watchdog threshold high
1807 * or low in function of ADC resolution, when ADC resolution is
1808 * different of 12 bits.
1809 * @note To be used with function @ref LL_ADC_SetAnalogWDThresholds().
1810 * Example, with a ADC resolution of 8 bits, to set the value of
1811 * analog watchdog threshold high (on 8 bits):
1812 * LL_ADC_SetAnalogWDThresholds
1813 * (< ADCx param >,
1814 * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
1815 * );
1816 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1817 * @arg @ref LL_ADC_RESOLUTION_12B
1818 * @arg @ref LL_ADC_RESOLUTION_10B
1819 * @arg @ref LL_ADC_RESOLUTION_8B
1820 * @arg @ref LL_ADC_RESOLUTION_6B
1821 * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
1822 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1823 */
1824 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
1825 ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U )))
1826
1827 /**
1828 * @brief Helper macro to get the value of ADC analog watchdog threshold high
1829 * or low in function of ADC resolution, when ADC resolution is
1830 * different of 12 bits.
1831 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
1832 * Example, with a ADC resolution of 8 bits, to get the value of
1833 * analog watchdog threshold high (on 8 bits):
1834 * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
1835 * (LL_ADC_RESOLUTION_8B,
1836 * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
1837 * );
1838 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1839 * @arg @ref LL_ADC_RESOLUTION_12B
1840 * @arg @ref LL_ADC_RESOLUTION_10B
1841 * @arg @ref LL_ADC_RESOLUTION_8B
1842 * @arg @ref LL_ADC_RESOLUTION_6B
1843 * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
1844 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1845 */
1846 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
1847 ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U )))
1848
1849 /**
1850 * @brief Helper macro to select the ADC common instance
1851 * to which is belonging the selected ADC instance.
1852 * @note ADC common register instance can be used for:
1853 * - Set parameters common to several ADC instances
1854 * - Multimode (for devices with several ADC instances)
1855 * Refer to functions having argument "ADCxy_COMMON" as parameter.
1856 * @param __ADCx__ ADC instance
1857 * @retval ADC common register instance
1858 */
1859 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
1860 (ADC1_COMMON)
1861
1862 /**
1863 * @brief Helper macro to check if all ADC instances sharing the same
1864 * ADC common instance are disabled.
1865 * @note This check is required by functions with setting conditioned to
1866 * ADC state:
1867 * All ADC instances of the ADC common group must be disabled.
1868 * Refer to functions having argument "ADCxy_COMMON" as parameter.
1869 * @note On devices with only 1 ADC common instance, parameter of this macro
1870 * is useless and can be ignored (parameter kept for compatibility
1871 * with devices featuring several ADC common instances).
1872 * @param __ADCXY_COMMON__ ADC common instance
1873 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1874 * @retval Value "0" if all ADC instances sharing the same ADC common instance
1875 * are disabled.
1876 * Value "1" if at least one ADC instance sharing the same ADC common instance
1877 * is enabled.
1878 */
1879 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
1880 LL_ADC_IsEnabled(ADC1)
1881
1882 /**
1883 * @brief Helper macro to define the ADC conversion data full-scale digital
1884 * value corresponding to the selected ADC resolution.
1885 * @note ADC conversion data full-scale corresponds to voltage range
1886 * determined by analog voltage references Vref+ and Vref-
1887 * (refer to reference manual).
1888 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1889 * @arg @ref LL_ADC_RESOLUTION_12B
1890 * @arg @ref LL_ADC_RESOLUTION_10B
1891 * @arg @ref LL_ADC_RESOLUTION_8B
1892 * @arg @ref LL_ADC_RESOLUTION_6B
1893 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
1894 */
1895 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
1896 (((uint32_t)0xFFFU) >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U)))
1897
1898 /**
1899 * @brief Helper macro to convert the ADC conversion data from
1900 * a resolution to another resolution.
1901 * @param __DATA__ ADC conversion data to be converted
1902 * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
1903 * This parameter can be one of the following values:
1904 * @arg @ref LL_ADC_RESOLUTION_12B
1905 * @arg @ref LL_ADC_RESOLUTION_10B
1906 * @arg @ref LL_ADC_RESOLUTION_8B
1907 * @arg @ref LL_ADC_RESOLUTION_6B
1908 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
1909 * This parameter can be one of the following values:
1910 * @arg @ref LL_ADC_RESOLUTION_12B
1911 * @arg @ref LL_ADC_RESOLUTION_10B
1912 * @arg @ref LL_ADC_RESOLUTION_8B
1913 * @arg @ref LL_ADC_RESOLUTION_6B
1914 * @retval ADC conversion data to the requested resolution
1915 */
1916 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__) \
1917 (((__DATA__) \
1918 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U))) \
1919 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U)) \
1920 )
1921
1922 /**
1923 * @brief Helper macro to calculate the voltage (unit: mVolt)
1924 * corresponding to a ADC conversion data (unit: digital value).
1925 * @note Analog reference voltage (Vref+) must be either known from
1926 * user board environment or can be calculated using ADC measurement
1927 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1928 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
1929 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
1930 * (unit: digital value).
1931 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1932 * @arg @ref LL_ADC_RESOLUTION_12B
1933 * @arg @ref LL_ADC_RESOLUTION_10B
1934 * @arg @ref LL_ADC_RESOLUTION_8B
1935 * @arg @ref LL_ADC_RESOLUTION_6B
1936 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
1937 */
1938 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
1939 __ADC_DATA__,\
1940 __ADC_RESOLUTION__) \
1941 ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
1942 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
1943 )
1944
1945 /**
1946 * @brief Helper macro to calculate analog reference voltage (Vref+)
1947 * (unit: mVolt) from ADC conversion data of internal voltage
1948 * reference VrefInt.
1949 * @note Computation is using VrefInt calibration value
1950 * stored in system memory for each device during production.
1951 * @note This voltage depends on user board environment: voltage level
1952 * connected to pin Vref+.
1953 * On devices with small package, the pin Vref+ is not present
1954 * and internally bonded to pin Vdda.
1955 * @note On this STM32 serie, calibration data of internal voltage reference
1956 * VrefInt corresponds to a resolution of 12 bits,
1957 * this is the recommended ADC resolution to convert voltage of
1958 * internal voltage reference VrefInt.
1959 * Otherwise, this macro performs the processing to scale
1960 * ADC conversion data to 12 bits.
1961 * @param __VREFINT_ADC_DATA__: ADC conversion data (resolution 12 bits)
1962 * of internal voltage reference VrefInt (unit: digital value).
1963 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1964 * @arg @ref LL_ADC_RESOLUTION_12B
1965 * @arg @ref LL_ADC_RESOLUTION_10B
1966 * @arg @ref LL_ADC_RESOLUTION_8B
1967 * @arg @ref LL_ADC_RESOLUTION_6B
1968 * @retval Analog reference voltage (unit: mV)
1969 */
1970 #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
1971 __ADC_RESOLUTION__) \
1972 (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
1973 / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
1974 (__ADC_RESOLUTION__), \
1975 LL_ADC_RESOLUTION_12B) \
1976 )
1977
1978 /**
1979 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
1980 * from ADC conversion data of internal temperature sensor.
1981 * @note Computation is using temperature sensor calibration values
1982 * stored in system memory for each device during production.
1983 * @note Calculation formula:
1984 * Temperature = ((TS_ADC_DATA - TS_CAL1)
1985 * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
1986 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
1987 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
1988 * Avg_Slope = (TS_CAL2 - TS_CAL1)
1989 * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
1990 * TS_CAL1 = equivalent TS_ADC_DATA at temperature
1991 * TEMP_DEGC_CAL1 (calibrated in factory)
1992 * TS_CAL2 = equivalent TS_ADC_DATA at temperature
1993 * TEMP_DEGC_CAL2 (calibrated in factory)
1994 * Caution: Calculation relevancy under reserve that calibration
1995 * parameters are correct (address and data).
1996 * To calculate temperature using temperature sensor
1997 * datasheet typical values (generic values less, therefore
1998 * less accurate than calibrated values),
1999 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
2000 * @note As calculation input, the analog reference voltage (Vref+) must be
2001 * defined as it impacts the ADC LSB equivalent voltage.
2002 * @note Analog reference voltage (Vref+) must be either known from
2003 * user board environment or can be calculated using ADC measurement
2004 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2005 * @note On this STM32 serie, calibration data of temperature sensor
2006 * corresponds to a resolution of 12 bits,
2007 * this is the recommended ADC resolution to convert voltage of
2008 * temperature sensor.
2009 * Otherwise, this macro performs the processing to scale
2010 * ADC conversion data to 12 bits.
2011 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
2012 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
2013 * temperature sensor (unit: digital value).
2014 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
2015 * sensor voltage has been measured.
2016 * This parameter can be one of the following values:
2017 * @arg @ref LL_ADC_RESOLUTION_12B
2018 * @arg @ref LL_ADC_RESOLUTION_10B
2019 * @arg @ref LL_ADC_RESOLUTION_8B
2020 * @arg @ref LL_ADC_RESOLUTION_6B
2021 * @retval Temperature (unit: degree Celsius)
2022 */
2023 #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
2024 __TEMPSENSOR_ADC_DATA__,\
2025 __ADC_RESOLUTION__) \
2026 (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
2027 (__ADC_RESOLUTION__), \
2028 LL_ADC_RESOLUTION_12B) \
2029 * (__VREFANALOG_VOLTAGE__)) \
2030 / TEMPSENSOR_CAL_VREFANALOG) \
2031 - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
2032 ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
2033 ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
2034 ) + TEMPSENSOR_CAL1_TEMP \
2035 )
2036
2037 /**
2038 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
2039 * from ADC conversion data of internal temperature sensor.
2040 * @note Computation is using temperature sensor typical values
2041 * (refer to device datasheet).
2042 * @note Calculation formula:
2043 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
2044 * / Avg_Slope + CALx_TEMP
2045 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
2046 * (unit: digital value)
2047 * Avg_Slope = temperature sensor slope
2048 * (unit: uV/Degree Celsius)
2049 * TS_TYP_CALx_VOLT = temperature sensor digital value at
2050 * temperature CALx_TEMP (unit: mV)
2051 * Caution: Calculation relevancy under reserve the temperature sensor
2052 * of the current device has characteristics in line with
2053 * datasheet typical values.
2054 * If temperature sensor calibration values are available on
2055 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
2056 * temperature calculation will be more accurate using
2057 * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
2058 * @note As calculation input, the analog reference voltage (Vref+) must be
2059 * defined as it impacts the ADC LSB equivalent voltage.
2060 * @note Analog reference voltage (Vref+) must be either known from
2061 * user board environment or can be calculated using ADC measurement
2062 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2063 * @note ADC measurement data must correspond to a resolution of 12bits
2064 * (full scale digital value 4095). If not the case, the data must be
2065 * preliminarily rescaled to an equivalent resolution of 12 bits.
2066 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
2067 * On STM32L1, refer to device datasheet parameter "Avg_Slope".
2068 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
2069 * On STM32L1, refer to device datasheet parameter "V110" (corresponding to TS_CAL2).
2070 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
2071 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
2072 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
2073 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
2074 * This parameter can be one of the following values:
2075 * @arg @ref LL_ADC_RESOLUTION_12B
2076 * @arg @ref LL_ADC_RESOLUTION_10B
2077 * @arg @ref LL_ADC_RESOLUTION_8B
2078 * @arg @ref LL_ADC_RESOLUTION_6B
2079 * @retval Temperature (unit: degree Celsius)
2080 */
2081 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
2082 __TEMPSENSOR_TYP_CALX_V__,\
2083 __TEMPSENSOR_CALX_TEMP__,\
2084 __VREFANALOG_VOLTAGE__,\
2085 __TEMPSENSOR_ADC_DATA__,\
2086 __ADC_RESOLUTION__) \
2087 ((( ( \
2088 (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
2089 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
2090 * 1000) \
2091 - \
2092 (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
2093 * 1000) \
2094 ) \
2095 ) / (__TEMPSENSOR_TYP_AVGSLOPE__) \
2096 ) + (__TEMPSENSOR_CALX_TEMP__) \
2097 )
2098
2099 /**
2100 * @}
2101 */
2102
2103 /**
2104 * @}
2105 */
2106
2107
2108 /* Exported functions --------------------------------------------------------*/
2109 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
2110 * @{
2111 */
2112
2113 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
2114 * @{
2115 */
2116 /* Note: LL ADC functions to set DMA transfer are located into sections of */
2117 /* configuration of ADC instance, groups and multimode (if available): */
2118 /* @ref LL_ADC_REG_SetDMATransfer(), ... */
2119
2120 /**
2121 * @brief Function to help to configure DMA transfer from ADC: retrieve the
2122 * ADC register address from ADC instance and a list of ADC registers
2123 * intended to be used (most commonly) with DMA transfer.
2124 * @note These ADC registers are data registers:
2125 * when ADC conversion data is available in ADC data registers,
2126 * ADC generates a DMA transfer request.
2127 * @note This macro is intended to be used with LL DMA driver, refer to
2128 * function "LL_DMA_ConfigAddresses()".
2129 * Example:
2130 * LL_DMA_ConfigAddresses(DMA1,
2131 * LL_DMA_CHANNEL_1,
2132 * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
2133 * (uint32_t)&< array or variable >,
2134 * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
2135 * @note For devices with several ADC: in multimode, some devices
2136 * use a different data register outside of ADC instance scope
2137 * (common data register). This macro manages this register difference,
2138 * only ADC instance has to be set as parameter.
2139 * @rmtoll DR DATA LL_ADC_DMA_GetRegAddr
2140 * @param ADCx ADC instance
2141 * @param Register This parameter can be one of the following values:
2142 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
2143 * @retval ADC register address
2144 */
2145 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
2146 {
2147 /* Retrieve address of register DR */
2148 return (uint32_t)&(ADCx->DR);
2149 }
2150
2151 /**
2152 * @}
2153 */
2154
2155 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
2156 * @{
2157 */
2158
2159 /**
2160 * @brief Set parameter common to several ADC: Clock source and prescaler.
2161 * @note On this STM32 serie, HSI RC oscillator is the only clock source for ADC.
2162 * Therefore, HSI RC oscillator must be preliminarily enabled at RCC top level.
2163 * @note On this STM32 serie, some clock ratio constraints between ADC clock and APB clock
2164 * must be respected:
2165 * - In all cases: if APB clock frequency is too low compared ADC clock frequency, a delay between conversions must be inserted.
2166 * - If ADC group injected is used: ADC clock frequency should be lower than APB clock frequency /4 for resolution 12 or 10 bits, APB clock frequency /3 for resolution 8 bits, APB clock frequency /2 for resolution 6 bits.
2167 * Refer to reference manual.
2168 * @rmtoll CCR ADCPRE LL_ADC_SetCommonClock
2169 * @param ADCxy_COMMON ADC common instance
2170 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2171 * @param CommonClock This parameter can be one of the following values:
2172 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
2173 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
2174 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
2175 * @retval None
2176 */
2177 __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
2178 {
2179 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE, CommonClock);
2180 }
2181
2182 /**
2183 * @brief Get parameter common to several ADC: Clock source and prescaler.
2184 * @rmtoll CCR ADCPRE LL_ADC_GetCommonClock
2185 * @param ADCxy_COMMON ADC common instance
2186 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2187 * @retval Returned value can be one of the following values:
2188 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
2189 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
2190 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
2191 */
2192 __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
2193 {
2194 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE));
2195 }
2196
2197 /**
2198 * @brief Set parameter common to several ADC: measurement path to internal
2199 * channels (VrefInt, temperature sensor, ...).
2200 * @note One or several values can be selected.
2201 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2202 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2203 * @note Stabilization time of measurement path to internal channel:
2204 * After enabling internal paths, before starting ADC conversion,
2205 * a delay is required for internal voltage reference and
2206 * temperature sensor stabilization time.
2207 * Refer to device datasheet.
2208 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
2209 * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
2210 * @note ADC internal channel sampling time constraint:
2211 * For ADC conversion of internal channels,
2212 * a sampling time minimum value is required.
2213 * Refer to device datasheet.
2214 * @rmtoll CCR TSVREFE LL_ADC_SetCommonPathInternalCh
2215 * @param ADCxy_COMMON ADC common instance
2216 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2217 * @param PathInternal This parameter can be a combination of the following values:
2218 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2219 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2220 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2221 * @retval None
2222 */
2223 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
2224 {
2225 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE, PathInternal);
2226 }
2227
2228 /**
2229 * @brief Get parameter common to several ADC: measurement path to internal
2230 * channels (VrefInt, temperature sensor, ...).
2231 * @note One or several values can be selected.
2232 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2233 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2234 * @rmtoll CCR TSVREFE LL_ADC_GetCommonPathInternalCh
2235 * @param ADCxy_COMMON ADC common instance
2236 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2237 * @retval Returned value can be a combination of the following values:
2238 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2239 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2240 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2241 */
2242 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
2243 {
2244 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE));
2245 }
2246
2247 /**
2248 * @}
2249 */
2250
2251 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
2252 * @{
2253 */
2254
2255 /**
2256 * @brief Set ADC resolution.
2257 * Refer to reference manual for alignments formats
2258 * dependencies to ADC resolutions.
2259 * @rmtoll CR1 RES LL_ADC_SetResolution
2260 * @param ADCx ADC instance
2261 * @param Resolution This parameter can be one of the following values:
2262 * @arg @ref LL_ADC_RESOLUTION_12B
2263 * @arg @ref LL_ADC_RESOLUTION_10B
2264 * @arg @ref LL_ADC_RESOLUTION_8B
2265 * @arg @ref LL_ADC_RESOLUTION_6B
2266 * @retval None
2267 */
2268 __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
2269 {
2270 MODIFY_REG(ADCx->CR1, ADC_CR1_RES, Resolution);
2271 }
2272
2273 /**
2274 * @brief Get ADC resolution.
2275 * Refer to reference manual for alignments formats
2276 * dependencies to ADC resolutions.
2277 * @rmtoll CR1 RES LL_ADC_GetResolution
2278 * @param ADCx ADC instance
2279 * @retval Returned value can be one of the following values:
2280 * @arg @ref LL_ADC_RESOLUTION_12B
2281 * @arg @ref LL_ADC_RESOLUTION_10B
2282 * @arg @ref LL_ADC_RESOLUTION_8B
2283 * @arg @ref LL_ADC_RESOLUTION_6B
2284 */
2285 __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
2286 {
2287 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_RES));
2288 }
2289
2290 /**
2291 * @brief Set ADC conversion data alignment.
2292 * @note Refer to reference manual for alignments formats
2293 * dependencies to ADC resolutions.
2294 * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment
2295 * @param ADCx ADC instance
2296 * @param DataAlignment This parameter can be one of the following values:
2297 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
2298 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
2299 * @retval None
2300 */
2301 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
2302 {
2303 MODIFY_REG(ADCx->CR2, ADC_CR2_ALIGN, DataAlignment);
2304 }
2305
2306 /**
2307 * @brief Get ADC conversion data alignment.
2308 * @note Refer to reference manual for alignments formats
2309 * dependencies to ADC resolutions.
2310 * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment
2311 * @param ADCx ADC instance
2312 * @retval Returned value can be one of the following values:
2313 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
2314 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
2315 */
2316 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
2317 {
2318 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_ALIGN));
2319 }
2320
2321 /**
2322 * @brief Set ADC low power mode auto wait.
2323 * @note Description of ADC low power modes:
2324 * - ADC low power mode "auto wait": Dynamic low power mode,
2325 * ADC conversions occurrences are limited to the minimum necessary
2326 * in order to reduce power consumption.
2327 * New ADC conversion starts only when the previous
2328 * unitary conversion data (for ADC group regular)
2329 * or previous sequence conversions data (for ADC group injected)
2330 * has been retrieved by user software.
2331 * In the meantime, ADC remains idle: does not performs any
2332 * other conversion.
2333 * This mode allows to automatically adapt the ADC conversions
2334 * triggers to the speed of the software that reads the data.
2335 * Moreover, this avoids risk of overrun for low frequency
2336 * applications.
2337 * How to use this low power mode:
2338 * - Do not use with interruption or DMA since these modes
2339 * have to clear immediately the EOC flag to free the
2340 * IRQ vector sequencer.
2341 * - Do use with polling: 1. Start conversion,
2342 * 2. Later on, when conversion data is needed: poll for end of
2343 * conversion to ensure that conversion is completed and
2344 * retrieve ADC conversion data. This will trig another
2345 * ADC conversion start.
2346 * - ADC low power mode "auto power-off":
2347 * refer to function @ref LL_ADC_SetLowPowerModeAutoPowerOff().
2348 * @note With ADC low power mode "auto wait", the ADC conversion data read
2349 * is corresponding to previous ADC conversion start, independently
2350 * of delay during which ADC was idle.
2351 * Therefore, the ADC conversion data may be outdated: does not
2352 * correspond to the current voltage level on the selected
2353 * ADC channel.
2354 * @rmtoll CR2 DELS LL_ADC_SetLowPowerModeAutoWait
2355 * @param ADCx ADC instance
2356 * @param LowPowerModeAutoWait This parameter can be one of the following values:
2357 * @arg @ref LL_ADC_LP_AUTOWAIT_NONE
2358 * @arg @ref LL_ADC_LP_AUTOWAIT
2359 * @arg @ref LL_ADC_LP_AUTOWAIT_7_APBCLOCKCYCLES
2360 * @arg @ref LL_ADC_LP_AUTOWAIT_15_APBCLOCKCYCLES
2361 * @arg @ref LL_ADC_LP_AUTOWAIT_31_APBCLOCKCYCLES
2362 * @arg @ref LL_ADC_LP_AUTOWAIT_63_APBCLOCKCYCLES
2363 * @arg @ref LL_ADC_LP_AUTOWAIT_127_APBCLOCKCYCLES
2364 * @arg @ref LL_ADC_LP_AUTOWAIT_255_APBCLOCKCYCLES
2365 * @retval None
2366 */
2367 __STATIC_INLINE void LL_ADC_SetLowPowerModeAutoWait(ADC_TypeDef *ADCx, uint32_t LowPowerModeAutoWait)
2368 {
2369 MODIFY_REG(ADCx->CR2, ADC_CR2_DELS, LowPowerModeAutoWait);
2370 }
2371
2372 /**
2373 * @brief Get ADC low power mode auto wait.
2374 * @note Description of ADC low power modes:
2375 * - ADC low power mode "auto wait": Dynamic low power mode,
2376 * ADC conversions occurrences are limited to the minimum necessary
2377 * in order to reduce power consumption.
2378 * New ADC conversion starts only when the previous
2379 * unitary conversion data (for ADC group regular)
2380 * or previous sequence conversions data (for ADC group injected)
2381 * has been retrieved by user software.
2382 * In the meantime, ADC remains idle: does not performs any
2383 * other conversion.
2384 * This mode allows to automatically adapt the ADC conversions
2385 * triggers to the speed of the software that reads the data.
2386 * Moreover, this avoids risk of overrun for low frequency
2387 * applications.
2388 * How to use this low power mode:
2389 * - Do not use with interruption or DMA since these modes
2390 * have to clear immediately the EOC flag to free the
2391 * IRQ vector sequencer.
2392 * - Do use with polling: 1. Start conversion,
2393 * 2. Later on, when conversion data is needed: poll for end of
2394 * conversion to ensure that conversion is completed and
2395 * retrieve ADC conversion data. This will trig another
2396 * ADC conversion start.
2397 * - ADC low power mode "auto power-off":
2398 * refer to function @ref LL_ADC_SetLowPowerModeAutoPowerOff().
2399 * @note With ADC low power mode "auto wait", the ADC conversion data read
2400 * is corresponding to previous ADC conversion start, independently
2401 * of delay during which ADC was idle.
2402 * Therefore, the ADC conversion data may be outdated: does not
2403 * correspond to the current voltage level on the selected
2404 * ADC channel.
2405 * @rmtoll CR2 DELS LL_ADC_GetLowPowerModeAutoWait
2406 * @param ADCx ADC instance
2407 * @retval Returned value can be one of the following values:
2408 * @arg @ref LL_ADC_LP_AUTOWAIT_NONE
2409 * @arg @ref LL_ADC_LP_AUTOWAIT
2410 * @arg @ref LL_ADC_LP_AUTOWAIT_7_APBCLOCKCYCLES
2411 * @arg @ref LL_ADC_LP_AUTOWAIT_15_APBCLOCKCYCLES
2412 * @arg @ref LL_ADC_LP_AUTOWAIT_31_APBCLOCKCYCLES
2413 * @arg @ref LL_ADC_LP_AUTOWAIT_63_APBCLOCKCYCLES
2414 * @arg @ref LL_ADC_LP_AUTOWAIT_127_APBCLOCKCYCLES
2415 * @arg @ref LL_ADC_LP_AUTOWAIT_255_APBCLOCKCYCLES
2416 */
2417 __STATIC_INLINE uint32_t LL_ADC_GetLowPowerModeAutoWait(ADC_TypeDef *ADCx)
2418 {
2419 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_DELS));
2420 }
2421
2422 /**
2423 * @brief Set ADC low power mode auto power-off.
2424 * @note Description of ADC low power modes:
2425 * - ADC low power mode "auto wait":
2426 * refer to function @ref LL_ADC_SetLowPowerModeAutoWait().
2427 * - ADC low power mode "auto power-off":
2428 * the ADC automatically powers-off after a conversion and
2429 * automatically wakes up when a new conversion is triggered
2430 * (with startup time between trigger and start of sampling).
2431 * This feature can be combined with low power mode "auto wait".
2432 * @rmtoll CR1 PDI LL_ADC_GetLowPowerModeAutoPowerOff\n
2433 * CR1 PDD LL_ADC_GetLowPowerModeAutoPowerOff
2434 * @param ADCx ADC instance
2435 * @param LowPowerModeAutoPowerOff This parameter can be one of the following values:
2436 * @arg @ref LL_ADC_LP_AUTOPOWEROFF_NONE
2437 * @arg @ref LL_ADC_LP_AUTOPOWEROFF_IDLE_PHASE
2438 * @arg @ref LL_ADC_LP_AUTOPOWEROFF_AUTOWAIT_PHASE
2439 * @arg @ref LL_ADC_LP_AUTOPOWEROFF_IDLE_AUTOWAIT_PHASES
2440 * @retval None
2441 */
2442 __STATIC_INLINE void LL_ADC_SetLowPowerModeAutoPowerOff(ADC_TypeDef *ADCx, uint32_t LowPowerModeAutoPowerOff)
2443 {
2444 MODIFY_REG(ADCx->CR1, (ADC_CR1_PDI | ADC_CR1_PDD), LowPowerModeAutoPowerOff);
2445 }
2446
2447 /**
2448 * @brief Get ADC low power mode auto power-off.
2449 * @note Description of ADC low power modes:
2450 * - ADC low power mode "auto wait":
2451 * refer to function @ref LL_ADC_SetLowPowerModeAutoWait().
2452 * - ADC low power mode "auto power-off":
2453 * the ADC automatically powers-off after a conversion and
2454 * automatically wakes up when a new conversion is triggered
2455 * (with startup time between trigger and start of sampling).
2456 * This feature can be combined with low power mode "auto wait".
2457 * @rmtoll CR1 PDI LL_ADC_GetLowPowerModeAutoPowerOff\n
2458 * CR1 PDD LL_ADC_GetLowPowerModeAutoPowerOff
2459 * @param ADCx ADC instance
2460 * @retval Returned value can be one of the following values:
2461 * @arg @ref LL_ADC_LP_AUTOPOWEROFF_NONE
2462 * @arg @ref LL_ADC_LP_AUTOPOWEROFF_IDLE_PHASE
2463 * @arg @ref LL_ADC_LP_AUTOPOWEROFF_AUTOWAIT_PHASE
2464 * @arg @ref LL_ADC_LP_AUTOPOWEROFF_IDLE_AUTOWAIT_PHASES
2465 */
2466 __STATIC_INLINE uint32_t LL_ADC_GetLowPowerModeAutoPowerOff(ADC_TypeDef *ADCx)
2467 {
2468 return (uint32_t)(READ_BIT(ADCx->CR1, (ADC_CR1_PDI | ADC_CR1_PDD)));
2469 }
2470
2471 /**
2472 * @brief Set ADC sequencers scan mode, for all ADC groups
2473 * (group regular, group injected).
2474 * @note According to sequencers scan mode :
2475 * - If disabled: ADC conversion is performed in unitary conversion
2476 * mode (one channel converted, that defined in rank 1).
2477 * Configuration of sequencers of all ADC groups
2478 * (sequencer scan length, ...) is discarded: equivalent to
2479 * scan length of 1 rank.
2480 * - If enabled: ADC conversions are performed in sequence conversions
2481 * mode, according to configuration of sequencers of
2482 * each ADC group (sequencer scan length, ...).
2483 * Refer to function @ref LL_ADC_REG_SetSequencerLength()
2484 * and to function @ref LL_ADC_INJ_SetSequencerLength().
2485 * @note On this STM32 serie, setting of this feature is conditioned to
2486 * ADC state:
2487 * ADC must be disabled or enabled without conversion on going
2488 * on either groups regular or injected.
2489 * @rmtoll CR1 SCAN LL_ADC_SetSequencersScanMode
2490 * @param ADCx ADC instance
2491 * @param ScanMode This parameter can be one of the following values:
2492 * @arg @ref LL_ADC_SEQ_SCAN_DISABLE
2493 * @arg @ref LL_ADC_SEQ_SCAN_ENABLE
2494 * @retval None
2495 */
2496 __STATIC_INLINE void LL_ADC_SetSequencersScanMode(ADC_TypeDef *ADCx, uint32_t ScanMode)
2497 {
2498 MODIFY_REG(ADCx->CR1, ADC_CR1_SCAN, ScanMode);
2499 }
2500
2501 /**
2502 * @brief Get ADC sequencers scan mode, for all ADC groups
2503 * (group regular, group injected).
2504 * @note According to sequencers scan mode :
2505 * - If disabled: ADC conversion is performed in unitary conversion
2506 * mode (one channel converted, that defined in rank 1).
2507 * Configuration of sequencers of all ADC groups
2508 * (sequencer scan length, ...) is discarded: equivalent to
2509 * scan length of 1 rank.
2510 * - If enabled: ADC conversions are performed in sequence conversions
2511 * mode, according to configuration of sequencers of
2512 * each ADC group (sequencer scan length, ...).
2513 * Refer to function @ref LL_ADC_REG_SetSequencerLength()
2514 * and to function @ref LL_ADC_INJ_SetSequencerLength().
2515 * @rmtoll CR1 SCAN LL_ADC_GetSequencersScanMode
2516 * @param ADCx ADC instance
2517 * @retval Returned value can be one of the following values:
2518 * @arg @ref LL_ADC_SEQ_SCAN_DISABLE
2519 * @arg @ref LL_ADC_SEQ_SCAN_ENABLE
2520 */
2521 __STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx)
2522 {
2523 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_SCAN));
2524 }
2525
2526 #if defined(ADC_CR2_CFG)
2527 /**
2528 * @brief Set ADC channels bank.
2529 * @note Bank selected applies to ADC scope, on all channels
2530 * (independently of channel mapped on ADC group regular
2531 * or group injected).
2532 * @note Banks availability depends on devices categories.
2533 * @note On this STM32 serie, setting of this feature is conditioned to
2534 * ADC state:
2535 * ADC must be disabled or enabled without conversion on going
2536 * on either groups regular or injected.
2537 * @rmtoll CR2 ADC_CFG LL_ADC_SetChannelsBank
2538 * @param ADCx ADC instance
2539 * @param ChannelsBank This parameter can be one of the following values:
2540 * @arg @ref LL_ADC_CHANNELS_BANK_A
2541 * @arg @ref LL_ADC_CHANNELS_BANK_B
2542 * @retval None
2543 */
2544 __STATIC_INLINE void LL_ADC_SetChannelsBank(ADC_TypeDef *ADCx, uint32_t ChannelsBank)
2545 {
2546 MODIFY_REG(ADCx->CR2, ADC_CR2_CFG, ChannelsBank);
2547 }
2548
2549 /**
2550 * @brief Get ADC channels bank.
2551 * @note Bank selected applies to ADC scope, on all channels
2552 * (independently of channel mapped on ADC group regular
2553 * or group injected).
2554 * @note Banks availability depends on devices categories.
2555 * @rmtoll CR2 ADC_CFG LL_ADC_GetChannelsBank
2556 * @param ADCx ADC instance
2557 * @retval Returned value can be one of the following values:
2558 * @arg @ref LL_ADC_CHANNELS_BANK_A
2559 * @arg @ref LL_ADC_CHANNELS_BANK_B
2560 */
2561 __STATIC_INLINE uint32_t LL_ADC_GetChannelsBank(ADC_TypeDef *ADCx)
2562 {
2563 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_CFG));
2564 }
2565 #endif
2566
2567 /**
2568 * @}
2569 */
2570
2571 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
2572 * @{
2573 */
2574
2575 /**
2576 * @brief Set ADC group regular conversion trigger source:
2577 * internal (SW start) or from external IP (timer event,
2578 * external interrupt line).
2579 * @note On this STM32 serie, setting of external trigger edge is performed
2580 * using function @ref LL_ADC_REG_StartConversionExtTrig().
2581 * @note Availability of parameters of trigger sources from timer
2582 * depends on timers availability on the selected device.
2583 * @rmtoll CR2 EXTSEL LL_ADC_REG_SetTriggerSource\n
2584 * CR2 EXTEN LL_ADC_REG_SetTriggerSource
2585 * @param ADCx ADC instance
2586 * @param TriggerSource This parameter can be one of the following values:
2587 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
2588 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
2589 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3
2590 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
2591 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
2592 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1
2593 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH3
2594 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
2595 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
2596 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
2597 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM9_CH2
2598 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM9_TRGO
2599 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
2600 * @retval None
2601 */
2602 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
2603 {
2604 /* Note: On this STM32 serie, ADC group regular external trigger edge */
2605 /* is used to perform a ADC conversion start. */
2606 /* This function does not set external trigger edge. */
2607 /* This feature is set using function */
2608 /* @ref LL_ADC_REG_StartConversionExtTrig(). */
2609 MODIFY_REG(ADCx->CR2, ADC_CR2_EXTSEL, (TriggerSource & ADC_CR2_EXTSEL));
2610 }
2611
2612 /**
2613 * @brief Get ADC group regular conversion trigger source:
2614 * internal (SW start) or from external IP (timer event,
2615 * external interrupt line).
2616 * @note To determine whether group regular trigger source is
2617 * internal (SW start) or external, without detail
2618 * of which peripheral is selected as external trigger,
2619 * (equivalent to
2620 * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
2621 * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
2622 * @note Availability of parameters of trigger sources from timer
2623 * depends on timers availability on the selected device.
2624 * @rmtoll CR2 EXTSEL LL_ADC_REG_GetTriggerSource\n
2625 * CR2 EXTEN LL_ADC_REG_GetTriggerSource
2626 * @param ADCx ADC instance
2627 * @retval Returned value can be one of the following values:
2628 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
2629 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
2630 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3
2631 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
2632 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
2633 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1
2634 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH3
2635 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
2636 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
2637 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
2638 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM9_CH2
2639 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM9_TRGO
2640 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
2641 */
2642 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
2643 {
2644 register uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL | ADC_CR2_EXTEN);
2645
2646 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
2647 /* corresponding to ADC_CR2_EXTEN {0; 1; 2; 3}. */
2648 register uint32_t ShiftExten = ((TriggerSource & ADC_CR2_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U));
2649
2650 /* Set bitfield corresponding to ADC_CR2_EXTEN and ADC_CR2_EXTSEL */
2651 /* to match with triggers literals definition. */
2652 return ((TriggerSource
2653 & (ADC_REG_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_EXTSEL)
2654 | ((ADC_REG_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_EXTEN)
2655 );
2656 }
2657
2658 /**
2659 * @brief Get ADC group regular conversion trigger source internal (SW start)
2660 or external.
2661 * @note In case of group regular trigger source set to external trigger,
2662 * to determine which peripheral is selected as external trigger,
2663 * use function @ref LL_ADC_REG_GetTriggerSource().
2664 * @rmtoll CR2 EXTEN LL_ADC_REG_IsTriggerSourceSWStart
2665 * @param ADCx ADC instance
2666 * @retval Value "0" if trigger source external trigger
2667 * Value "1" if trigger source SW start.
2668 */
2669 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
2670 {
2671 return (READ_BIT(ADCx->CR2, ADC_CR2_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN));
2672 }
2673
2674 /**
2675 * @brief Get ADC group regular conversion trigger polarity.
2676 * @note Applicable only for trigger source set to external trigger.
2677 * @note On this STM32 serie, setting of external trigger edge is performed
2678 * using function @ref LL_ADC_REG_StartConversionExtTrig().
2679 * @rmtoll CR2 EXTEN LL_ADC_REG_GetTriggerEdge
2680 * @param ADCx ADC instance
2681 * @retval Returned value can be one of the following values:
2682 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
2683 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
2684 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
2685 */
2686 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
2687 {
2688 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EXTEN));
2689 }
2690
2691
2692 /**
2693 * @brief Set ADC group regular sequencer length and scan direction.
2694 * @note Description of ADC group regular sequencer features:
2695 * - For devices with sequencer fully configurable
2696 * (function "LL_ADC_REG_SetSequencerRanks()" available):
2697 * sequencer length and each rank affectation to a channel
2698 * are configurable.
2699 * This function performs configuration of:
2700 * - Sequence length: Number of ranks in the scan sequence.
2701 * - Sequence direction: Unless specified in parameters, sequencer
2702 * scan direction is forward (from rank 1 to rank n).
2703 * Sequencer ranks are selected using
2704 * function "LL_ADC_REG_SetSequencerRanks()".
2705 * - For devices with sequencer not fully configurable
2706 * (function "LL_ADC_REG_SetSequencerChannels()" available):
2707 * sequencer length and each rank affectation to a channel
2708 * are defined by channel number.
2709 * This function performs configuration of:
2710 * - Sequence length: Number of ranks in the scan sequence is
2711 * defined by number of channels set in the sequence,
2712 * rank of each channel is fixed by channel HW number.
2713 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
2714 * - Sequence direction: Unless specified in parameters, sequencer
2715 * scan direction is forward (from lowest channel number to
2716 * highest channel number).
2717 * Sequencer ranks are selected using
2718 * function "LL_ADC_REG_SetSequencerChannels()".
2719 * @note On this STM32 serie, group regular sequencer configuration
2720 * is conditioned to ADC instance sequencer mode.
2721 * If ADC instance sequencer mode is disabled, sequencers of
2722 * all groups (group regular, group injected) can be configured
2723 * but their execution is disabled (limited to rank 1).
2724 * Refer to function @ref LL_ADC_SetSequencersScanMode().
2725 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
2726 * ADC conversion on only 1 channel.
2727 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
2728 * @param ADCx ADC instance
2729 * @param SequencerNbRanks This parameter can be one of the following values:
2730 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
2731 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
2732 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
2733 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
2734 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
2735 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
2736 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
2737 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
2738 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
2739 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
2740 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
2741 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
2742 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
2743 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
2744 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
2745 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
2746 * @retval None
2747 */
2748 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
2749 {
2750 MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
2751 }
2752
2753 /**
2754 * @brief Get ADC group regular sequencer length and scan direction.
2755 * @note Description of ADC group regular sequencer features:
2756 * - For devices with sequencer fully configurable
2757 * (function "LL_ADC_REG_SetSequencerRanks()" available):
2758 * sequencer length and each rank affectation to a channel
2759 * are configurable.
2760 * This function retrieves:
2761 * - Sequence length: Number of ranks in the scan sequence.
2762 * - Sequence direction: Unless specified in parameters, sequencer
2763 * scan direction is forward (from rank 1 to rank n).
2764 * Sequencer ranks are selected using
2765 * function "LL_ADC_REG_SetSequencerRanks()".
2766 * - For devices with sequencer not fully configurable
2767 * (function "LL_ADC_REG_SetSequencerChannels()" available):
2768 * sequencer length and each rank affectation to a channel
2769 * are defined by channel number.
2770 * This function retrieves:
2771 * - Sequence length: Number of ranks in the scan sequence is
2772 * defined by number of channels set in the sequence,
2773 * rank of each channel is fixed by channel HW number.
2774 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
2775 * - Sequence direction: Unless specified in parameters, sequencer
2776 * scan direction is forward (from lowest channel number to
2777 * highest channel number).
2778 * Sequencer ranks are selected using
2779 * function "LL_ADC_REG_SetSequencerChannels()".
2780 * @note On this STM32 serie, group regular sequencer configuration
2781 * is conditioned to ADC instance sequencer mode.
2782 * If ADC instance sequencer mode is disabled, sequencers of
2783 * all groups (group regular, group injected) can be configured
2784 * but their execution is disabled (limited to rank 1).
2785 * Refer to function @ref LL_ADC_SetSequencersScanMode().
2786 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
2787 * ADC conversion on only 1 channel.
2788 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
2789 * @param ADCx ADC instance
2790 * @retval Returned value can be one of the following values:
2791 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
2792 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
2793 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
2794 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
2795 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
2796 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
2797 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
2798 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
2799 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
2800 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
2801 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
2802 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
2803 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
2804 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
2805 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
2806 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
2807 */
2808 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
2809 {
2810 return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
2811 }
2812
2813 /**
2814 * @brief Set ADC group regular sequencer discontinuous mode:
2815 * sequence subdivided and scan conversions interrupted every selected
2816 * number of ranks.
2817 * @note It is not possible to enable both ADC group regular
2818 * continuous mode and sequencer discontinuous mode.
2819 * @note It is not possible to enable both ADC auto-injected mode
2820 * and ADC group regular sequencer discontinuous mode.
2821 * @rmtoll CR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n
2822 * CR1 DISCNUM LL_ADC_REG_SetSequencerDiscont
2823 * @param ADCx ADC instance
2824 * @param SeqDiscont This parameter can be one of the following values:
2825 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
2826 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
2827 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
2828 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
2829 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
2830 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
2831 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
2832 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
2833 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
2834 * @retval None
2835 */
2836 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
2837 {
2838 MODIFY_REG(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM, SeqDiscont);
2839 }
2840
2841 /**
2842 * @brief Get ADC group regular sequencer discontinuous mode:
2843 * sequence subdivided and scan conversions interrupted every selected
2844 * number of ranks.
2845 * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n
2846 * CR1 DISCNUM LL_ADC_REG_GetSequencerDiscont
2847 * @param ADCx ADC instance
2848 * @retval Returned value can be one of the following values:
2849 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
2850 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
2851 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
2852 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
2853 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
2854 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
2855 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
2856 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
2857 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
2858 */
2859 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
2860 {
2861 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM));
2862 }
2863
2864 /**
2865 * @brief Set ADC group regular sequence: channel on the selected
2866 * scan sequence rank.
2867 * @note This function performs configuration of:
2868 * - Channels ordering into each rank of scan sequence:
2869 * whatever channel can be placed into whatever rank.
2870 * @note On this STM32 serie, ADC group regular sequencer is
2871 * fully configurable: sequencer length and each rank
2872 * affectation to a channel are configurable.
2873 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
2874 * @note Depending on devices and packages, some channels may not be available.
2875 * Refer to device datasheet for channels availability.
2876 * @note On this STM32 serie, to measure internal channels (VrefInt,
2877 * TempSensor, ...), measurement paths to internal channels must be
2878 * enabled separately.
2879 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
2880 * @rmtoll SQR5 SQ1 LL_ADC_REG_SetSequencerRanks\n
2881 * SQR5 SQ2 LL_ADC_REG_SetSequencerRanks\n
2882 * SQR5 SQ3 LL_ADC_REG_SetSequencerRanks\n
2883 * SQR5 SQ4 LL_ADC_REG_SetSequencerRanks\n
2884 * SQR5 SQ5 LL_ADC_REG_SetSequencerRanks\n
2885 * SQR5 SQ6 LL_ADC_REG_SetSequencerRanks\n
2886 * SQR4 SQ7 LL_ADC_REG_SetSequencerRanks\n
2887 * SQR4 SQ8 LL_ADC_REG_SetSequencerRanks\n
2888 * SQR4 SQ9 LL_ADC_REG_SetSequencerRanks\n
2889 * SQR4 SQ10 LL_ADC_REG_SetSequencerRanks\n
2890 * SQR4 SQ11 LL_ADC_REG_SetSequencerRanks\n
2891 * SQR4 SQ12 LL_ADC_REG_SetSequencerRanks\n
2892 * SQR3 SQ13 LL_ADC_REG_SetSequencerRanks\n
2893 * SQR3 SQ14 LL_ADC_REG_SetSequencerRanks\n
2894 * SQR3 SQ15 LL_ADC_REG_SetSequencerRanks\n
2895 * SQR3 SQ16 LL_ADC_REG_SetSequencerRanks\n
2896 * SQR3 SQ17 LL_ADC_REG_SetSequencerRanks\n
2897 * SQR3 SQ18 LL_ADC_REG_SetSequencerRanks\n
2898 * SQR2 SQ19 LL_ADC_REG_SetSequencerRanks\n
2899 * SQR2 SQ20 LL_ADC_REG_SetSequencerRanks\n
2900 * SQR2 SQ21 LL_ADC_REG_SetSequencerRanks\n
2901 * SQR2 SQ22 LL_ADC_REG_SetSequencerRanks\n
2902 * SQR2 SQ23 LL_ADC_REG_SetSequencerRanks\n
2903 * SQR2 SQ24 LL_ADC_REG_SetSequencerRanks\n
2904 * SQR1 SQ25 LL_ADC_REG_SetSequencerRanks\n
2905 * SQR1 SQ26 LL_ADC_REG_SetSequencerRanks\n
2906 * SQR1 SQ27 LL_ADC_REG_SetSequencerRanks\n
2907 * SQR1 SQ28 LL_ADC_REG_SetSequencerRanks
2908 * @param ADCx ADC instance
2909 * @param Rank This parameter can be one of the following values:
2910 * @arg @ref LL_ADC_REG_RANK_1
2911 * @arg @ref LL_ADC_REG_RANK_2
2912 * @arg @ref LL_ADC_REG_RANK_3
2913 * @arg @ref LL_ADC_REG_RANK_4
2914 * @arg @ref LL_ADC_REG_RANK_5
2915 * @arg @ref LL_ADC_REG_RANK_6
2916 * @arg @ref LL_ADC_REG_RANK_7
2917 * @arg @ref LL_ADC_REG_RANK_8
2918 * @arg @ref LL_ADC_REG_RANK_9
2919 * @arg @ref LL_ADC_REG_RANK_10
2920 * @arg @ref LL_ADC_REG_RANK_11
2921 * @arg @ref LL_ADC_REG_RANK_12
2922 * @arg @ref LL_ADC_REG_RANK_13
2923 * @arg @ref LL_ADC_REG_RANK_14
2924 * @arg @ref LL_ADC_REG_RANK_15
2925 * @arg @ref LL_ADC_REG_RANK_16
2926 * @arg @ref LL_ADC_REG_RANK_17
2927 * @arg @ref LL_ADC_REG_RANK_18
2928 * @arg @ref LL_ADC_REG_RANK_19
2929 * @arg @ref LL_ADC_REG_RANK_20
2930 * @arg @ref LL_ADC_REG_RANK_21
2931 * @arg @ref LL_ADC_REG_RANK_22
2932 * @arg @ref LL_ADC_REG_RANK_23
2933 * @arg @ref LL_ADC_REG_RANK_24
2934 * @arg @ref LL_ADC_REG_RANK_25
2935 * @arg @ref LL_ADC_REG_RANK_26
2936 * @arg @ref LL_ADC_REG_RANK_27
2937 * @arg @ref LL_ADC_REG_RANK_28 (1)
2938 *
2939 * (1) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.3, Cat.4 and Cat.5.
2940 * @param Channel This parameter can be one of the following values:
2941 * @arg @ref LL_ADC_CHANNEL_0 (2)
2942 * @arg @ref LL_ADC_CHANNEL_1 (2)
2943 * @arg @ref LL_ADC_CHANNEL_2 (2)
2944 * @arg @ref LL_ADC_CHANNEL_3 (2)
2945 * @arg @ref LL_ADC_CHANNEL_4 (1)
2946 * @arg @ref LL_ADC_CHANNEL_5 (1)
2947 * @arg @ref LL_ADC_CHANNEL_6 (2)
2948 * @arg @ref LL_ADC_CHANNEL_7 (2)
2949 * @arg @ref LL_ADC_CHANNEL_8 (2)
2950 * @arg @ref LL_ADC_CHANNEL_9 (2)
2951 * @arg @ref LL_ADC_CHANNEL_10 (2)
2952 * @arg @ref LL_ADC_CHANNEL_11 (2)
2953 * @arg @ref LL_ADC_CHANNEL_12 (2)
2954 * @arg @ref LL_ADC_CHANNEL_13 (3)
2955 * @arg @ref LL_ADC_CHANNEL_14 (3)
2956 * @arg @ref LL_ADC_CHANNEL_15 (3)
2957 * @arg @ref LL_ADC_CHANNEL_16 (3)
2958 * @arg @ref LL_ADC_CHANNEL_17 (3)
2959 * @arg @ref LL_ADC_CHANNEL_18 (3)
2960 * @arg @ref LL_ADC_CHANNEL_19 (3)
2961 * @arg @ref LL_ADC_CHANNEL_20 (3)
2962 * @arg @ref LL_ADC_CHANNEL_21 (3)
2963 * @arg @ref LL_ADC_CHANNEL_22 (1)
2964 * @arg @ref LL_ADC_CHANNEL_23 (1)
2965 * @arg @ref LL_ADC_CHANNEL_24 (1)
2966 * @arg @ref LL_ADC_CHANNEL_25 (1)
2967 * @arg @ref LL_ADC_CHANNEL_26 (3)
2968 * @arg @ref LL_ADC_CHANNEL_27 (3)(4)
2969 * @arg @ref LL_ADC_CHANNEL_28 (3)(4)
2970 * @arg @ref LL_ADC_CHANNEL_29 (3)(4)
2971 * @arg @ref LL_ADC_CHANNEL_30 (3)(4)
2972 * @arg @ref LL_ADC_CHANNEL_31 (3)(4)
2973 * @arg @ref LL_ADC_CHANNEL_VREFINT (3)
2974 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)
2975 * @arg @ref LL_ADC_CHANNEL_VCOMP (3)
2976 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (3)(5)
2977 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (3)(5)
2978 * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)(5)
2979 *
2980 * (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n
2981 * (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n
2982 * (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n
2983 * (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n
2984 * (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5
2985 * @retval None
2986 */
2987 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
2988 {
2989 /* Set bits with content of parameter "Channel" with bits position */
2990 /* in register and register position depending on parameter "Rank". */
2991 /* Parameters "Rank" and "Channel" are used with masks because containing */
2992 /* other bits reserved for other purpose. */
2993 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
2994
2995 MODIFY_REG(*preg,
2996 ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
2997 (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
2998 }
2999
3000 /**
3001 * @brief Get ADC group regular sequence: channel on the selected
3002 * scan sequence rank.
3003 * @note On this STM32 serie, ADC group regular sequencer is
3004 * fully configurable: sequencer length and each rank
3005 * affectation to a channel are configurable.
3006 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
3007 * @note Depending on devices and packages, some channels may not be available.
3008 * Refer to device datasheet for channels availability.
3009 * @note Usage of the returned channel number:
3010 * - To reinject this channel into another function LL_ADC_xxx:
3011 * the returned channel number is only partly formatted on definition
3012 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
3013 * with parts of literals LL_ADC_CHANNEL_x or using
3014 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3015 * Then the selected literal LL_ADC_CHANNEL_x can be used
3016 * as parameter for another function.
3017 * - To get the channel number in decimal format:
3018 * process the returned value with the helper macro
3019 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3020 * @rmtoll SQR5 SQ1 LL_ADC_REG_GetSequencerRanks\n
3021 * SQR5 SQ2 LL_ADC_REG_GetSequencerRanks\n
3022 * SQR5 SQ3 LL_ADC_REG_GetSequencerRanks\n
3023 * SQR5 SQ4 LL_ADC_REG_GetSequencerRanks\n
3024 * SQR5 SQ5 LL_ADC_REG_GetSequencerRanks\n
3025 * SQR5 SQ6 LL_ADC_REG_GetSequencerRanks\n
3026 * SQR4 SQ7 LL_ADC_REG_GetSequencerRanks\n
3027 * SQR4 SQ8 LL_ADC_REG_GetSequencerRanks\n
3028 * SQR4 SQ9 LL_ADC_REG_GetSequencerRanks\n
3029 * SQR4 SQ10 LL_ADC_REG_GetSequencerRanks\n
3030 * SQR4 SQ11 LL_ADC_REG_GetSequencerRanks\n
3031 * SQR4 SQ12 LL_ADC_REG_GetSequencerRanks\n
3032 * SQR3 SQ13 LL_ADC_REG_GetSequencerRanks\n
3033 * SQR3 SQ14 LL_ADC_REG_GetSequencerRanks\n
3034 * SQR3 SQ15 LL_ADC_REG_GetSequencerRanks\n
3035 * SQR3 SQ16 LL_ADC_REG_GetSequencerRanks\n
3036 * SQR3 SQ17 LL_ADC_REG_GetSequencerRanks\n
3037 * SQR3 SQ18 LL_ADC_REG_GetSequencerRanks\n
3038 * SQR2 SQ19 LL_ADC_REG_GetSequencerRanks\n
3039 * SQR2 SQ20 LL_ADC_REG_GetSequencerRanks\n
3040 * SQR2 SQ21 LL_ADC_REG_GetSequencerRanks\n
3041 * SQR2 SQ22 LL_ADC_REG_GetSequencerRanks\n
3042 * SQR2 SQ23 LL_ADC_REG_GetSequencerRanks\n
3043 * SQR2 SQ24 LL_ADC_REG_GetSequencerRanks\n
3044 * SQR1 SQ25 LL_ADC_REG_GetSequencerRanks\n
3045 * SQR1 SQ26 LL_ADC_REG_GetSequencerRanks\n
3046 * SQR1 SQ27 LL_ADC_REG_GetSequencerRanks\n
3047 * SQR1 SQ28 LL_ADC_REG_GetSequencerRanks
3048 * @param ADCx ADC instance
3049 * @param Rank This parameter can be one of the following values:
3050 * @arg @ref LL_ADC_REG_RANK_1
3051 * @arg @ref LL_ADC_REG_RANK_2
3052 * @arg @ref LL_ADC_REG_RANK_3
3053 * @arg @ref LL_ADC_REG_RANK_4
3054 * @arg @ref LL_ADC_REG_RANK_5
3055 * @arg @ref LL_ADC_REG_RANK_6
3056 * @arg @ref LL_ADC_REG_RANK_7
3057 * @arg @ref LL_ADC_REG_RANK_8
3058 * @arg @ref LL_ADC_REG_RANK_9
3059 * @arg @ref LL_ADC_REG_RANK_10
3060 * @arg @ref LL_ADC_REG_RANK_11
3061 * @arg @ref LL_ADC_REG_RANK_12
3062 * @arg @ref LL_ADC_REG_RANK_13
3063 * @arg @ref LL_ADC_REG_RANK_14
3064 * @arg @ref LL_ADC_REG_RANK_15
3065 * @arg @ref LL_ADC_REG_RANK_16
3066 * @arg @ref LL_ADC_REG_RANK_17
3067 * @arg @ref LL_ADC_REG_RANK_18
3068 * @arg @ref LL_ADC_REG_RANK_19
3069 * @arg @ref LL_ADC_REG_RANK_20
3070 * @arg @ref LL_ADC_REG_RANK_21
3071 * @arg @ref LL_ADC_REG_RANK_22
3072 * @arg @ref LL_ADC_REG_RANK_23
3073 * @arg @ref LL_ADC_REG_RANK_24
3074 * @arg @ref LL_ADC_REG_RANK_25
3075 * @arg @ref LL_ADC_REG_RANK_26
3076 * @arg @ref LL_ADC_REG_RANK_27
3077 * @arg @ref LL_ADC_REG_RANK_28 (1)
3078 *
3079 * (1) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.3, Cat.4 and Cat.5.
3080 * @retval Returned value can be one of the following values:
3081 * @arg @ref LL_ADC_CHANNEL_0 (2)
3082 * @arg @ref LL_ADC_CHANNEL_1 (2)
3083 * @arg @ref LL_ADC_CHANNEL_2 (2)
3084 * @arg @ref LL_ADC_CHANNEL_3 (2)
3085 * @arg @ref LL_ADC_CHANNEL_4 (1)
3086 * @arg @ref LL_ADC_CHANNEL_5 (1)
3087 * @arg @ref LL_ADC_CHANNEL_6 (2)
3088 * @arg @ref LL_ADC_CHANNEL_7 (2)
3089 * @arg @ref LL_ADC_CHANNEL_8 (2)
3090 * @arg @ref LL_ADC_CHANNEL_9 (2)
3091 * @arg @ref LL_ADC_CHANNEL_10 (2)
3092 * @arg @ref LL_ADC_CHANNEL_11 (2)
3093 * @arg @ref LL_ADC_CHANNEL_12 (2)
3094 * @arg @ref LL_ADC_CHANNEL_13 (3)
3095 * @arg @ref LL_ADC_CHANNEL_14 (3)
3096 * @arg @ref LL_ADC_CHANNEL_15 (3)
3097 * @arg @ref LL_ADC_CHANNEL_16 (3)
3098 * @arg @ref LL_ADC_CHANNEL_17 (3)
3099 * @arg @ref LL_ADC_CHANNEL_18 (3)
3100 * @arg @ref LL_ADC_CHANNEL_19 (3)
3101 * @arg @ref LL_ADC_CHANNEL_20 (3)
3102 * @arg @ref LL_ADC_CHANNEL_21 (3)
3103 * @arg @ref LL_ADC_CHANNEL_22 (1)
3104 * @arg @ref LL_ADC_CHANNEL_23 (1)
3105 * @arg @ref LL_ADC_CHANNEL_24 (1)
3106 * @arg @ref LL_ADC_CHANNEL_25 (1)
3107 * @arg @ref LL_ADC_CHANNEL_26 (3)
3108 * @arg @ref LL_ADC_CHANNEL_27 (3)(4)
3109 * @arg @ref LL_ADC_CHANNEL_28 (3)(4)
3110 * @arg @ref LL_ADC_CHANNEL_29 (3)(4)
3111 * @arg @ref LL_ADC_CHANNEL_30 (3)(4)
3112 * @arg @ref LL_ADC_CHANNEL_31 (3)(4)
3113 * @arg @ref LL_ADC_CHANNEL_VREFINT (3)(6)
3114 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)(6)
3115 * @arg @ref LL_ADC_CHANNEL_VCOMP (3)(6)
3116 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (3)(5)
3117 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (3)(5)
3118 * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)(5)
3119 *
3120 * (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n
3121 * (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n
3122 * (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n
3123 * (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n
3124 * (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5.\n
3125 * (6) For ADC channel read back from ADC register,
3126 * comparison with internal channel parameter to be done
3127 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
3128 */
3129 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
3130 {
3131 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
3132
3133 return (uint32_t) (READ_BIT(*preg,
3134 ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
3135 >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)
3136 );
3137 }
3138
3139 /**
3140 * @brief Set ADC continuous conversion mode on ADC group regular.
3141 * @note Description of ADC continuous conversion mode:
3142 * - single mode: one conversion per trigger
3143 * - continuous mode: after the first trigger, following
3144 * conversions launched successively automatically.
3145 * @note It is not possible to enable both ADC group regular
3146 * continuous mode and sequencer discontinuous mode.
3147 * @rmtoll CR2 CONT LL_ADC_REG_SetContinuousMode
3148 * @param ADCx ADC instance
3149 * @param Continuous This parameter can be one of the following values:
3150 * @arg @ref LL_ADC_REG_CONV_SINGLE
3151 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
3152 * @retval None
3153 */
3154 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
3155 {
3156 MODIFY_REG(ADCx->CR2, ADC_CR2_CONT, Continuous);
3157 }
3158
3159 /**
3160 * @brief Get ADC continuous conversion mode on ADC group regular.
3161 * @note Description of ADC continuous conversion mode:
3162 * - single mode: one conversion per trigger
3163 * - continuous mode: after the first trigger, following
3164 * conversions launched successively automatically.
3165 * @rmtoll CR2 CONT LL_ADC_REG_GetContinuousMode
3166 * @param ADCx ADC instance
3167 * @retval Returned value can be one of the following values:
3168 * @arg @ref LL_ADC_REG_CONV_SINGLE
3169 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
3170 */
3171 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
3172 {
3173 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_CONT));
3174 }
3175
3176 /**
3177 * @brief Set ADC group regular conversion data transfer: no transfer or
3178 * transfer by DMA, and DMA requests mode.
3179 * @note If transfer by DMA selected, specifies the DMA requests
3180 * mode:
3181 * - Limited mode (One shot mode): DMA transfer requests are stopped
3182 * when number of DMA data transfers (number of
3183 * ADC conversions) is reached.
3184 * This ADC mode is intended to be used with DMA mode non-circular.
3185 * - Unlimited mode: DMA transfer requests are unlimited,
3186 * whatever number of DMA data transfers (number of
3187 * ADC conversions).
3188 * This ADC mode is intended to be used with DMA mode circular.
3189 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
3190 * mode non-circular:
3191 * when DMA transfers size will be reached, DMA will stop transfers of
3192 * ADC conversions data ADC will raise an overrun error
3193 * (overrun flag and interruption if enabled).
3194 * @note To configure DMA source address (peripheral address),
3195 * use function @ref LL_ADC_DMA_GetRegAddr().
3196 * @rmtoll CR2 DMA LL_ADC_REG_SetDMATransfer\n
3197 * CR2 DDS LL_ADC_REG_SetDMATransfer
3198 * @param ADCx ADC instance
3199 * @param DMATransfer This parameter can be one of the following values:
3200 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
3201 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
3202 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
3203 * @retval None
3204 */
3205 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
3206 {
3207 MODIFY_REG(ADCx->CR2, ADC_CR2_DMA | ADC_CR2_DDS, DMATransfer);
3208 }
3209
3210 /**
3211 * @brief Get ADC group regular conversion data transfer: no transfer or
3212 * transfer by DMA, and DMA requests mode.
3213 * @note If transfer by DMA selected, specifies the DMA requests
3214 * mode:
3215 * - Limited mode (One shot mode): DMA transfer requests are stopped
3216 * when number of DMA data transfers (number of
3217 * ADC conversions) is reached.
3218 * This ADC mode is intended to be used with DMA mode non-circular.
3219 * - Unlimited mode: DMA transfer requests are unlimited,
3220 * whatever number of DMA data transfers (number of
3221 * ADC conversions).
3222 * This ADC mode is intended to be used with DMA mode circular.
3223 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
3224 * mode non-circular:
3225 * when DMA transfers size will be reached, DMA will stop transfers of
3226 * ADC conversions data ADC will raise an overrun error
3227 * (overrun flag and interruption if enabled).
3228 * @note To configure DMA source address (peripheral address),
3229 * use function @ref LL_ADC_DMA_GetRegAddr().
3230 * @rmtoll CR2 DMA LL_ADC_REG_GetDMATransfer\n
3231 * CR2 DDS LL_ADC_REG_GetDMATransfer
3232 * @param ADCx ADC instance
3233 * @retval Returned value can be one of the following values:
3234 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
3235 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
3236 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
3237 */
3238 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
3239 {
3240 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_DMA | ADC_CR2_DDS));
3241 }
3242
3243 /**
3244 * @brief Specify which ADC flag between EOC (end of unitary conversion)
3245 * or EOS (end of sequence conversions) is used to indicate
3246 * the end of conversion.
3247 * @note This feature is aimed to be set when using ADC with
3248 * programming model by polling or interruption
3249 * (programming model by DMA usually uses DMA interruptions
3250 * to indicate end of conversion and data transfer).
3251 * @note For ADC group injected, end of conversion (flag&IT) is raised
3252 * only at the end of the sequence.
3253 * @rmtoll CR2 EOCS LL_ADC_REG_SetFlagEndOfConversion
3254 * @param ADCx ADC instance
3255 * @param EocSelection This parameter can be one of the following values:
3256 * @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV
3257 * @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV
3258 * @retval None
3259 */
3260 __STATIC_INLINE void LL_ADC_REG_SetFlagEndOfConversion(ADC_TypeDef *ADCx, uint32_t EocSelection)
3261 {
3262 MODIFY_REG(ADCx->CR2, ADC_CR2_EOCS, EocSelection);
3263 }
3264
3265 /**
3266 * @brief Get which ADC flag between EOC (end of unitary conversion)
3267 * or EOS (end of sequence conversions) is used to indicate
3268 * the end of conversion.
3269 * @rmtoll CR2 EOCS LL_ADC_REG_GetFlagEndOfConversion
3270 * @param ADCx ADC instance
3271 * @retval Returned value can be one of the following values:
3272 * @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV
3273 * @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV
3274 */
3275 __STATIC_INLINE uint32_t LL_ADC_REG_GetFlagEndOfConversion(ADC_TypeDef *ADCx)
3276 {
3277 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EOCS));
3278 }
3279
3280 /**
3281 * @}
3282 */
3283
3284 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
3285 * @{
3286 */
3287
3288 /**
3289 * @brief Set ADC group injected conversion trigger source:
3290 * internal (SW start) or from external IP (timer event,
3291 * external interrupt line).
3292 * @note On this STM32 serie, setting of external trigger edge is performed
3293 * using function @ref LL_ADC_INJ_StartConversionExtTrig().
3294 * @note Availability of parameters of trigger sources from timer
3295 * depends on timers availability on the selected device.
3296 * @rmtoll CR2 JEXTSEL LL_ADC_INJ_SetTriggerSource\n
3297 * CR2 JEXTEN LL_ADC_INJ_SetTriggerSource
3298 * @param ADCx ADC instance
3299 * @param TriggerSource This parameter can be one of the following values:
3300 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
3301 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM9_CH1
3302 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM9_TRGO
3303 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
3304 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
3305 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
3306 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
3307 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH1
3308 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH2
3309 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3
3310 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM10_CH1
3311 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
3312 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
3313 * @retval None
3314 */
3315 __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
3316 {
3317 /* Note: On this STM32 serie, ADC group injected external trigger edge */
3318 /* is used to perform a ADC conversion start. */
3319 /* This function does not set external trigger edge. */
3320 /* This feature is set using function */
3321 /* @ref LL_ADC_INJ_StartConversionExtTrig(). */
3322 MODIFY_REG(ADCx->CR2, ADC_CR2_JEXTSEL, (TriggerSource & ADC_CR2_JEXTSEL));
3323 }
3324
3325 /**
3326 * @brief Get ADC group injected conversion trigger source:
3327 * internal (SW start) or from external IP (timer event,
3328 * external interrupt line).
3329 * @note To determine whether group injected trigger source is
3330 * internal (SW start) or external, without detail
3331 * of which peripheral is selected as external trigger,
3332 * (equivalent to
3333 * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
3334 * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
3335 * @note Availability of parameters of trigger sources from timer
3336 * depends on timers availability on the selected device.
3337 * @rmtoll CR2 JEXTSEL LL_ADC_INJ_GetTriggerSource\n
3338 * CR2 JEXTEN LL_ADC_INJ_GetTriggerSource
3339 * @param ADCx ADC instance
3340 * @retval Returned value can be one of the following values:
3341 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
3342 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM9_CH1
3343 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM9_TRGO
3344 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
3345 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
3346 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
3347 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
3348 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH1
3349 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH2
3350 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3
3351 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM10_CH1
3352 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
3353 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
3354 */
3355 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
3356 {
3357 register uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL | ADC_CR2_JEXTEN);
3358
3359 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
3360 /* corresponding to ADC_CR2_JEXTEN {0; 1; 2; 3}. */
3361 register uint32_t ShiftExten = ((TriggerSource & ADC_CR2_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2U));
3362
3363 /* Set bitfield corresponding to ADC_CR2_JEXTEN and ADC_CR2_JEXTSEL */
3364 /* to match with triggers literals definition. */
3365 return ((TriggerSource
3366 & (ADC_INJ_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_JEXTSEL)
3367 | ((ADC_INJ_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_JEXTEN)
3368 );
3369 }
3370
3371 /**
3372 * @brief Get ADC group injected conversion trigger source internal (SW start)
3373 or external
3374 * @note In case of group injected trigger source set to external trigger,
3375 * to determine which peripheral is selected as external trigger,
3376 * use function @ref LL_ADC_INJ_GetTriggerSource.
3377 * @rmtoll CR2 JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart
3378 * @param ADCx ADC instance
3379 * @retval Value "0" if trigger source external trigger
3380 * Value "1" if trigger source SW start.
3381 */
3382 __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
3383 {
3384 return (READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN));
3385 }
3386
3387 /**
3388 * @brief Get ADC group injected conversion trigger polarity.
3389 * Applicable only for trigger source set to external trigger.
3390 * @rmtoll CR2 JEXTEN LL_ADC_INJ_GetTriggerEdge
3391 * @param ADCx ADC instance
3392 * @retval Returned value can be one of the following values:
3393 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
3394 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
3395 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
3396 */
3397 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)
3398 {
3399 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN));
3400 }
3401
3402 /**
3403 * @brief Set ADC group injected sequencer length and scan direction.
3404 * @note This function performs configuration of:
3405 * - Sequence length: Number of ranks in the scan sequence.
3406 * - Sequence direction: Unless specified in parameters, sequencer
3407 * scan direction is forward (from rank 1 to rank n).
3408 * @note On this STM32 serie, group injected sequencer configuration
3409 * is conditioned to ADC instance sequencer mode.
3410 * If ADC instance sequencer mode is disabled, sequencers of
3411 * all groups (group regular, group injected) can be configured
3412 * but their execution is disabled (limited to rank 1).
3413 * Refer to function @ref LL_ADC_SetSequencersScanMode().
3414 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
3415 * ADC conversion on only 1 channel.
3416 * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
3417 * @param ADCx ADC instance
3418 * @param SequencerNbRanks This parameter can be one of the following values:
3419 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
3420 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
3421 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
3422 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
3423 * @retval None
3424 */
3425 __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
3426 {
3427 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
3428 }
3429
3430 /**
3431 * @brief Get ADC group injected sequencer length and scan direction.
3432 * @note This function retrieves:
3433 * - Sequence length: Number of ranks in the scan sequence.
3434 * - Sequence direction: Unless specified in parameters, sequencer
3435 * scan direction is forward (from rank 1 to rank n).
3436 * @note On this STM32 serie, group injected sequencer configuration
3437 * is conditioned to ADC instance sequencer mode.
3438 * If ADC instance sequencer mode is disabled, sequencers of
3439 * all groups (group regular, group injected) can be configured
3440 * but their execution is disabled (limited to rank 1).
3441 * Refer to function @ref LL_ADC_SetSequencersScanMode().
3442 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
3443 * ADC conversion on only 1 channel.
3444 * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
3445 * @param ADCx ADC instance
3446 * @retval Returned value can be one of the following values:
3447 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
3448 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
3449 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
3450 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
3451 */
3452 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
3453 {
3454 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
3455 }
3456
3457 /**
3458 * @brief Set ADC group injected sequencer discontinuous mode:
3459 * sequence subdivided and scan conversions interrupted every selected
3460 * number of ranks.
3461 * @note It is not possible to enable both ADC group injected
3462 * auto-injected mode and sequencer discontinuous mode.
3463 * @rmtoll CR1 DISCEN LL_ADC_INJ_SetSequencerDiscont
3464 * @param ADCx ADC instance
3465 * @param SeqDiscont This parameter can be one of the following values:
3466 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
3467 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
3468 * @retval None
3469 */
3470 __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
3471 {
3472 MODIFY_REG(ADCx->CR1, ADC_CR1_JDISCEN, SeqDiscont);
3473 }
3474
3475 /**
3476 * @brief Get ADC group injected sequencer discontinuous mode:
3477 * sequence subdivided and scan conversions interrupted every selected
3478 * number of ranks.
3479 * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont
3480 * @param ADCx ADC instance
3481 * @retval Returned value can be one of the following values:
3482 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
3483 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
3484 */
3485 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
3486 {
3487 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JDISCEN));
3488 }
3489
3490 /**
3491 * @brief Set ADC group injected sequence: channel on the selected
3492 * sequence rank.
3493 * @note Depending on devices and packages, some channels may not be available.
3494 * Refer to device datasheet for channels availability.
3495 * @note On this STM32 serie, to measure internal channels (VrefInt,
3496 * TempSensor, ...), measurement paths to internal channels must be
3497 * enabled separately.
3498 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
3499 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
3500 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
3501 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
3502 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
3503 * @param ADCx ADC instance
3504 * @param Rank This parameter can be one of the following values:
3505 * @arg @ref LL_ADC_INJ_RANK_1
3506 * @arg @ref LL_ADC_INJ_RANK_2
3507 * @arg @ref LL_ADC_INJ_RANK_3
3508 * @arg @ref LL_ADC_INJ_RANK_4
3509 * @param Channel This parameter can be one of the following values:
3510 * @arg @ref LL_ADC_CHANNEL_0 (2)
3511 * @arg @ref LL_ADC_CHANNEL_1 (2)
3512 * @arg @ref LL_ADC_CHANNEL_2 (2)
3513 * @arg @ref LL_ADC_CHANNEL_3 (2)
3514 * @arg @ref LL_ADC_CHANNEL_4 (1)
3515 * @arg @ref LL_ADC_CHANNEL_5 (1)
3516 * @arg @ref LL_ADC_CHANNEL_6 (2)
3517 * @arg @ref LL_ADC_CHANNEL_7 (2)
3518 * @arg @ref LL_ADC_CHANNEL_8 (2)
3519 * @arg @ref LL_ADC_CHANNEL_9 (2)
3520 * @arg @ref LL_ADC_CHANNEL_10 (2)
3521 * @arg @ref LL_ADC_CHANNEL_11 (2)
3522 * @arg @ref LL_ADC_CHANNEL_12 (2)
3523 * @arg @ref LL_ADC_CHANNEL_13 (3)
3524 * @arg @ref LL_ADC_CHANNEL_14 (3)
3525 * @arg @ref LL_ADC_CHANNEL_15 (3)
3526 * @arg @ref LL_ADC_CHANNEL_16 (3)
3527 * @arg @ref LL_ADC_CHANNEL_17 (3)
3528 * @arg @ref LL_ADC_CHANNEL_18 (3)
3529 * @arg @ref LL_ADC_CHANNEL_19 (3)
3530 * @arg @ref LL_ADC_CHANNEL_20 (3)
3531 * @arg @ref LL_ADC_CHANNEL_21 (3)
3532 * @arg @ref LL_ADC_CHANNEL_22 (1)
3533 * @arg @ref LL_ADC_CHANNEL_23 (1)
3534 * @arg @ref LL_ADC_CHANNEL_24 (1)
3535 * @arg @ref LL_ADC_CHANNEL_25 (1)
3536 * @arg @ref LL_ADC_CHANNEL_26 (3)
3537 * @arg @ref LL_ADC_CHANNEL_27 (3)(4)
3538 * @arg @ref LL_ADC_CHANNEL_28 (3)(4)
3539 * @arg @ref LL_ADC_CHANNEL_29 (3)(4)
3540 * @arg @ref LL_ADC_CHANNEL_30 (3)(4)
3541 * @arg @ref LL_ADC_CHANNEL_31 (3)(4)
3542 * @arg @ref LL_ADC_CHANNEL_VREFINT (3)
3543 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)
3544 * @arg @ref LL_ADC_CHANNEL_VCOMP (3)
3545 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (3)(5)
3546 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (3)(5)
3547 * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)(5)
3548 *
3549 * (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n
3550 * (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n
3551 * (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n
3552 * (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n
3553 * (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5
3554 * @retval None
3555 */
3556 __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
3557 {
3558 /* Set bits with content of parameter "Channel" with bits position */
3559 /* in register depending on parameter "Rank". */
3560 /* Parameters "Rank" and "Channel" are used with masks because containing */
3561 /* other bits reserved for other purpose. */
3562 MODIFY_REG(ADCx->JSQR,
3563 ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),
3564 (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));
3565 }
3566
3567 /**
3568 * @brief Get ADC group injected sequence: channel on the selected
3569 * sequence rank.
3570 * @note Depending on devices and packages, some channels may not be available.
3571 * Refer to device datasheet for channels availability.
3572 * @note Usage of the returned channel number:
3573 * - To reinject this channel into another function LL_ADC_xxx:
3574 * the returned channel number is only partly formatted on definition
3575 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
3576 * with parts of literals LL_ADC_CHANNEL_x or using
3577 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3578 * Then the selected literal LL_ADC_CHANNEL_x can be used
3579 * as parameter for another function.
3580 * - To get the channel number in decimal format:
3581 * process the returned value with the helper macro
3582 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3583 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
3584 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
3585 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
3586 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
3587 * @param ADCx ADC instance
3588 * @param Rank This parameter can be one of the following values:
3589 * @arg @ref LL_ADC_INJ_RANK_1
3590 * @arg @ref LL_ADC_INJ_RANK_2
3591 * @arg @ref LL_ADC_INJ_RANK_3
3592 * @arg @ref LL_ADC_INJ_RANK_4
3593 * @retval Returned value can be one of the following values:
3594 * @arg @ref LL_ADC_CHANNEL_0 (2)
3595 * @arg @ref LL_ADC_CHANNEL_1 (2)
3596 * @arg @ref LL_ADC_CHANNEL_2 (2)
3597 * @arg @ref LL_ADC_CHANNEL_3 (2)
3598 * @arg @ref LL_ADC_CHANNEL_4 (1)
3599 * @arg @ref LL_ADC_CHANNEL_5 (1)
3600 * @arg @ref LL_ADC_CHANNEL_6 (2)
3601 * @arg @ref LL_ADC_CHANNEL_7 (2)
3602 * @arg @ref LL_ADC_CHANNEL_8 (2)
3603 * @arg @ref LL_ADC_CHANNEL_9 (2)
3604 * @arg @ref LL_ADC_CHANNEL_10 (2)
3605 * @arg @ref LL_ADC_CHANNEL_11 (2)
3606 * @arg @ref LL_ADC_CHANNEL_12 (2)
3607 * @arg @ref LL_ADC_CHANNEL_13 (3)
3608 * @arg @ref LL_ADC_CHANNEL_14 (3)
3609 * @arg @ref LL_ADC_CHANNEL_15 (3)
3610 * @arg @ref LL_ADC_CHANNEL_16 (3)
3611 * @arg @ref LL_ADC_CHANNEL_17 (3)
3612 * @arg @ref LL_ADC_CHANNEL_18 (3)
3613 * @arg @ref LL_ADC_CHANNEL_19 (3)
3614 * @arg @ref LL_ADC_CHANNEL_20 (3)
3615 * @arg @ref LL_ADC_CHANNEL_21 (3)
3616 * @arg @ref LL_ADC_CHANNEL_22 (1)
3617 * @arg @ref LL_ADC_CHANNEL_23 (1)
3618 * @arg @ref LL_ADC_CHANNEL_24 (1)
3619 * @arg @ref LL_ADC_CHANNEL_25 (1)
3620 * @arg @ref LL_ADC_CHANNEL_26 (3)
3621 * @arg @ref LL_ADC_CHANNEL_27 (3)(4)
3622 * @arg @ref LL_ADC_CHANNEL_28 (3)(4)
3623 * @arg @ref LL_ADC_CHANNEL_29 (3)(4)
3624 * @arg @ref LL_ADC_CHANNEL_30 (3)(4)
3625 * @arg @ref LL_ADC_CHANNEL_31 (3)(4)
3626 * @arg @ref LL_ADC_CHANNEL_VREFINT (3)(6)
3627 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)(6)
3628 * @arg @ref LL_ADC_CHANNEL_VCOMP (3)(6)
3629 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (3)(5)
3630 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (3)(5)
3631 * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)(5)
3632 *
3633 * (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n
3634 * (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n
3635 * (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n
3636 * (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n
3637 * (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5.\n
3638 * (6) For ADC channel read back from ADC register,
3639 * comparison with internal channel parameter to be done
3640 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
3641 */
3642 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
3643 {
3644 return (uint32_t)(READ_BIT(ADCx->JSQR,
3645 ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
3646 >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)
3647 );
3648 }
3649
3650 /**
3651 * @brief Set ADC group injected conversion trigger:
3652 * independent or from ADC group regular.
3653 * @note This mode can be used to extend number of data registers
3654 * updated after one ADC conversion trigger and with data
3655 * permanently kept (not erased by successive conversions of scan of
3656 * ADC sequencer ranks), up to 5 data registers:
3657 * 1 data register on ADC group regular, 4 data registers
3658 * on ADC group injected.
3659 * @note If ADC group injected injected trigger source is set to an
3660 * external trigger, this feature must be must be set to
3661 * independent trigger.
3662 * ADC group injected automatic trigger is compliant only with
3663 * group injected trigger source set to SW start, without any
3664 * further action on ADC group injected conversion start or stop:
3665 * in this case, ADC group injected is controlled only
3666 * from ADC group regular.
3667 * @note It is not possible to enable both ADC group injected
3668 * auto-injected mode and sequencer discontinuous mode.
3669 * @rmtoll CR1 JAUTO LL_ADC_INJ_SetTrigAuto
3670 * @param ADCx ADC instance
3671 * @param TrigAuto This parameter can be one of the following values:
3672 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
3673 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
3674 * @retval None
3675 */
3676 __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
3677 {
3678 MODIFY_REG(ADCx->CR1, ADC_CR1_JAUTO, TrigAuto);
3679 }
3680
3681 /**
3682 * @brief Get ADC group injected conversion trigger:
3683 * independent or from ADC group regular.
3684 * @rmtoll CR1 JAUTO LL_ADC_INJ_GetTrigAuto
3685 * @param ADCx ADC instance
3686 * @retval Returned value can be one of the following values:
3687 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
3688 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
3689 */
3690 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
3691 {
3692 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JAUTO));
3693 }
3694
3695 /**
3696 * @brief Set ADC group injected offset.
3697 * @note It sets:
3698 * - ADC group injected rank to which the offset programmed
3699 * will be applied
3700 * - Offset level (offset to be subtracted from the raw
3701 * converted data).
3702 * Caution: Offset format is dependent to ADC resolution:
3703 * offset has to be left-aligned on bit 11, the LSB (right bits)
3704 * are set to 0.
3705 * @note Offset cannot be enabled or disabled.
3706 * To emulate offset disabled, set an offset value equal to 0.
3707 * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_SetOffset\n
3708 * JOFR2 JOFFSET2 LL_ADC_INJ_SetOffset\n
3709 * JOFR3 JOFFSET3 LL_ADC_INJ_SetOffset\n
3710 * JOFR4 JOFFSET4 LL_ADC_INJ_SetOffset
3711 * @param ADCx ADC instance
3712 * @param Rank This parameter can be one of the following values:
3713 * @arg @ref LL_ADC_INJ_RANK_1
3714 * @arg @ref LL_ADC_INJ_RANK_2
3715 * @arg @ref LL_ADC_INJ_RANK_3
3716 * @arg @ref LL_ADC_INJ_RANK_4
3717 * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
3718 * @retval None
3719 */
3720 __STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel)
3721 {
3722 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
3723
3724 MODIFY_REG(*preg,
3725 ADC_JOFR1_JOFFSET1,
3726 OffsetLevel);
3727 }
3728
3729 /**
3730 * @brief Get ADC group injected offset.
3731 * @note It gives offset level (offset to be subtracted from the raw converted data).
3732 * Caution: Offset format is dependent to ADC resolution:
3733 * offset has to be left-aligned on bit 11, the LSB (right bits)
3734 * are set to 0.
3735 * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_GetOffset\n
3736 * JOFR2 JOFFSET2 LL_ADC_INJ_GetOffset\n
3737 * JOFR3 JOFFSET3 LL_ADC_INJ_GetOffset\n
3738 * JOFR4 JOFFSET4 LL_ADC_INJ_GetOffset
3739 * @param ADCx ADC instance
3740 * @param Rank This parameter can be one of the following values:
3741 * @arg @ref LL_ADC_INJ_RANK_1
3742 * @arg @ref LL_ADC_INJ_RANK_2
3743 * @arg @ref LL_ADC_INJ_RANK_3
3744 * @arg @ref LL_ADC_INJ_RANK_4
3745 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
3746 */
3747 __STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank)
3748 {
3749 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
3750
3751 return (uint32_t)(READ_BIT(*preg,
3752 ADC_JOFR1_JOFFSET1)
3753 );
3754 }
3755
3756 /**
3757 * @}
3758 */
3759
3760 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
3761 * @{
3762 */
3763
3764 /**
3765 * @brief Set sampling time of the selected ADC channel
3766 * Unit: ADC clock cycles.
3767 * @note On this device, sampling time is on channel scope: independently
3768 * of channel mapped on ADC group regular or injected.
3769 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
3770 * converted:
3771 * sampling time constraints must be respected (sampling time can be
3772 * adjusted in function of ADC clock frequency and sampling time
3773 * setting).
3774 * Refer to device datasheet for timings values (parameters TS_vrefint,
3775 * TS_temp, ...).
3776 * @note Conversion time is the addition of sampling time and processing time.
3777 * Refer to reference manual for ADC processing time of
3778 * this STM32 serie.
3779 * @note In case of ADC conversion of internal channel (VrefInt,
3780 * temperature sensor, ...), a sampling time minimum value
3781 * is required.
3782 * Refer to device datasheet.
3783 * @rmtoll SMPR0 SMP31 LL_ADC_SetChannelSamplingTime\n
3784 * SMPR0 SMP30 LL_ADC_SetChannelSamplingTime\n
3785 * SMPR1 SMP29 LL_ADC_SetChannelSamplingTime\n
3786 * SMPR1 SMP28 LL_ADC_SetChannelSamplingTime\n
3787 * SMPR1 SMP27 LL_ADC_SetChannelSamplingTime\n
3788 * SMPR1 SMP26 LL_ADC_SetChannelSamplingTime\n
3789 * SMPR1 SMP25 LL_ADC_SetChannelSamplingTime\n
3790 * SMPR1 SMP24 LL_ADC_SetChannelSamplingTime\n
3791 * SMPR1 SMP23 LL_ADC_SetChannelSamplingTime\n
3792 * SMPR1 SMP22 LL_ADC_SetChannelSamplingTime\n
3793 * SMPR1 SMP21 LL_ADC_SetChannelSamplingTime\n
3794 * SMPR1 SMP20 LL_ADC_SetChannelSamplingTime\n
3795 * SMPR2 SMP19 LL_ADC_SetChannelSamplingTime\n
3796 * SMPR2 SMP18 LL_ADC_SetChannelSamplingTime\n
3797 * SMPR2 SMP17 LL_ADC_SetChannelSamplingTime\n
3798 * SMPR2 SMP16 LL_ADC_SetChannelSamplingTime\n
3799 * SMPR2 SMP15 LL_ADC_SetChannelSamplingTime\n
3800 * SMPR2 SMP14 LL_ADC_SetChannelSamplingTime\n
3801 * SMPR2 SMP13 LL_ADC_SetChannelSamplingTime\n
3802 * SMPR2 SMP12 LL_ADC_SetChannelSamplingTime\n
3803 * SMPR2 SMP11 LL_ADC_SetChannelSamplingTime\n
3804 * SMPR2 SMP10 LL_ADC_SetChannelSamplingTime\n
3805 * SMPR3 SMP9 LL_ADC_SetChannelSamplingTime\n
3806 * SMPR3 SMP8 LL_ADC_SetChannelSamplingTime\n
3807 * SMPR3 SMP7 LL_ADC_SetChannelSamplingTime\n
3808 * SMPR3 SMP6 LL_ADC_SetChannelSamplingTime\n
3809 * SMPR3 SMP5 LL_ADC_SetChannelSamplingTime\n
3810 * SMPR3 SMP4 LL_ADC_SetChannelSamplingTime\n
3811 * SMPR3 SMP3 LL_ADC_SetChannelSamplingTime\n
3812 * SMPR3 SMP2 LL_ADC_SetChannelSamplingTime\n
3813 * SMPR3 SMP1 LL_ADC_SetChannelSamplingTime\n
3814 * SMPR3 SMP0 LL_ADC_SetChannelSamplingTime
3815 * @param ADCx ADC instance
3816 * @param Channel This parameter can be one of the following values:
3817 * @arg @ref LL_ADC_CHANNEL_0 (2)
3818 * @arg @ref LL_ADC_CHANNEL_1 (2)
3819 * @arg @ref LL_ADC_CHANNEL_2 (2)
3820 * @arg @ref LL_ADC_CHANNEL_3 (2)
3821 * @arg @ref LL_ADC_CHANNEL_4 (1)
3822 * @arg @ref LL_ADC_CHANNEL_5 (1)
3823 * @arg @ref LL_ADC_CHANNEL_6 (2)
3824 * @arg @ref LL_ADC_CHANNEL_7 (2)
3825 * @arg @ref LL_ADC_CHANNEL_8 (2)
3826 * @arg @ref LL_ADC_CHANNEL_9 (2)
3827 * @arg @ref LL_ADC_CHANNEL_10 (2)
3828 * @arg @ref LL_ADC_CHANNEL_11 (2)
3829 * @arg @ref LL_ADC_CHANNEL_12 (2)
3830 * @arg @ref LL_ADC_CHANNEL_13 (3)
3831 * @arg @ref LL_ADC_CHANNEL_14 (3)
3832 * @arg @ref LL_ADC_CHANNEL_15 (3)
3833 * @arg @ref LL_ADC_CHANNEL_16 (3)
3834 * @arg @ref LL_ADC_CHANNEL_17 (3)
3835 * @arg @ref LL_ADC_CHANNEL_18 (3)
3836 * @arg @ref LL_ADC_CHANNEL_19 (3)
3837 * @arg @ref LL_ADC_CHANNEL_20 (3)
3838 * @arg @ref LL_ADC_CHANNEL_21 (3)
3839 * @arg @ref LL_ADC_CHANNEL_22 (1)
3840 * @arg @ref LL_ADC_CHANNEL_23 (1)
3841 * @arg @ref LL_ADC_CHANNEL_24 (1)
3842 * @arg @ref LL_ADC_CHANNEL_25 (1)
3843 * @arg @ref LL_ADC_CHANNEL_26 (3)
3844 * @arg @ref LL_ADC_CHANNEL_27 (3)(4)
3845 * @arg @ref LL_ADC_CHANNEL_28 (3)(4)
3846 * @arg @ref LL_ADC_CHANNEL_29 (3)(4)
3847 * @arg @ref LL_ADC_CHANNEL_30 (3)(4)
3848 * @arg @ref LL_ADC_CHANNEL_31 (3)(4)
3849 * @arg @ref LL_ADC_CHANNEL_VREFINT (3)
3850 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)
3851 * @arg @ref LL_ADC_CHANNEL_VCOMP (3)
3852 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (3)(5)
3853 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (3)(5)
3854 * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)(5)
3855 *
3856 * (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n
3857 * (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n
3858 * (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n
3859 * (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n
3860 * (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5
3861 * @param SamplingTime This parameter can be one of the following values:
3862 * @arg @ref LL_ADC_SAMPLINGTIME_4CYCLES
3863 * @arg @ref LL_ADC_SAMPLINGTIME_9CYCLES
3864 * @arg @ref LL_ADC_SAMPLINGTIME_16CYCLES
3865 * @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES
3866 * @arg @ref LL_ADC_SAMPLINGTIME_48CYCLES
3867 * @arg @ref LL_ADC_SAMPLINGTIME_96CYCLES
3868 * @arg @ref LL_ADC_SAMPLINGTIME_192CYCLES
3869 * @arg @ref LL_ADC_SAMPLINGTIME_384CYCLES
3870 * @retval None
3871 */
3872 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
3873 {
3874 /* Set bits with content of parameter "SamplingTime" with bits position */
3875 /* in register and register position depending on parameter "Channel". */
3876 /* Parameter "Channel" is used with masks because containing */
3877 /* other bits reserved for other purpose. */
3878 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
3879
3880 MODIFY_REG(*preg,
3881 ADC_SMPR3_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK),
3882 SamplingTime << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK));
3883 }
3884
3885 /**
3886 * @brief Get sampling time of the selected ADC channel
3887 * Unit: ADC clock cycles.
3888 * @note On this device, sampling time is on channel scope: independently
3889 * of channel mapped on ADC group regular or injected.
3890 * @note Conversion time is the addition of sampling time and processing time.
3891 * Refer to reference manual for ADC processing time of
3892 * this STM32 serie.
3893 * @rmtoll SMPR0 SMP31 LL_ADC_GetChannelSamplingTime\n
3894 * SMPR0 SMP30 LL_ADC_GetChannelSamplingTime\n
3895 * SMPR1 SMP29 LL_ADC_GetChannelSamplingTime\n
3896 * SMPR1 SMP28 LL_ADC_GetChannelSamplingTime\n
3897 * SMPR1 SMP27 LL_ADC_GetChannelSamplingTime\n
3898 * SMPR1 SMP26 LL_ADC_GetChannelSamplingTime\n
3899 * SMPR1 SMP25 LL_ADC_GetChannelSamplingTime\n
3900 * SMPR1 SMP24 LL_ADC_GetChannelSamplingTime\n
3901 * SMPR1 SMP23 LL_ADC_GetChannelSamplingTime\n
3902 * SMPR1 SMP22 LL_ADC_GetChannelSamplingTime\n
3903 * SMPR1 SMP21 LL_ADC_GetChannelSamplingTime\n
3904 * SMPR1 SMP20 LL_ADC_GetChannelSamplingTime\n
3905 * SMPR2 SMP19 LL_ADC_GetChannelSamplingTime\n
3906 * SMPR2 SMP18 LL_ADC_GetChannelSamplingTime\n
3907 * SMPR2 SMP17 LL_ADC_GetChannelSamplingTime\n
3908 * SMPR2 SMP16 LL_ADC_GetChannelSamplingTime\n
3909 * SMPR2 SMP15 LL_ADC_GetChannelSamplingTime\n
3910 * SMPR2 SMP14 LL_ADC_GetChannelSamplingTime\n
3911 * SMPR2 SMP13 LL_ADC_GetChannelSamplingTime\n
3912 * SMPR2 SMP12 LL_ADC_GetChannelSamplingTime\n
3913 * SMPR2 SMP11 LL_ADC_GetChannelSamplingTime\n
3914 * SMPR2 SMP10 LL_ADC_GetChannelSamplingTime\n
3915 * SMPR3 SMP9 LL_ADC_GetChannelSamplingTime\n
3916 * SMPR3 SMP8 LL_ADC_GetChannelSamplingTime\n
3917 * SMPR3 SMP7 LL_ADC_GetChannelSamplingTime\n
3918 * SMPR3 SMP6 LL_ADC_GetChannelSamplingTime\n
3919 * SMPR3 SMP5 LL_ADC_GetChannelSamplingTime\n
3920 * SMPR3 SMP4 LL_ADC_GetChannelSamplingTime\n
3921 * SMPR3 SMP3 LL_ADC_GetChannelSamplingTime\n
3922 * SMPR3 SMP2 LL_ADC_GetChannelSamplingTime\n
3923 * SMPR3 SMP1 LL_ADC_GetChannelSamplingTime\n
3924 * SMPR3 SMP0 LL_ADC_GetChannelSamplingTime
3925 * @param ADCx ADC instance
3926 * @param Channel This parameter can be one of the following values:
3927 * @arg @ref LL_ADC_CHANNEL_0 (2)
3928 * @arg @ref LL_ADC_CHANNEL_1 (2)
3929 * @arg @ref LL_ADC_CHANNEL_2 (2)
3930 * @arg @ref LL_ADC_CHANNEL_3 (2)
3931 * @arg @ref LL_ADC_CHANNEL_4 (1)
3932 * @arg @ref LL_ADC_CHANNEL_5 (1)
3933 * @arg @ref LL_ADC_CHANNEL_6 (2)
3934 * @arg @ref LL_ADC_CHANNEL_7 (2)
3935 * @arg @ref LL_ADC_CHANNEL_8 (2)
3936 * @arg @ref LL_ADC_CHANNEL_9 (2)
3937 * @arg @ref LL_ADC_CHANNEL_10 (2)
3938 * @arg @ref LL_ADC_CHANNEL_11 (2)
3939 * @arg @ref LL_ADC_CHANNEL_12 (2)
3940 * @arg @ref LL_ADC_CHANNEL_13 (3)
3941 * @arg @ref LL_ADC_CHANNEL_14 (3)
3942 * @arg @ref LL_ADC_CHANNEL_15 (3)
3943 * @arg @ref LL_ADC_CHANNEL_16 (3)
3944 * @arg @ref LL_ADC_CHANNEL_17 (3)
3945 * @arg @ref LL_ADC_CHANNEL_18 (3)
3946 * @arg @ref LL_ADC_CHANNEL_19 (3)
3947 * @arg @ref LL_ADC_CHANNEL_20 (3)
3948 * @arg @ref LL_ADC_CHANNEL_21 (3)
3949 * @arg @ref LL_ADC_CHANNEL_22 (1)
3950 * @arg @ref LL_ADC_CHANNEL_23 (1)
3951 * @arg @ref LL_ADC_CHANNEL_24 (1)
3952 * @arg @ref LL_ADC_CHANNEL_25 (1)
3953 * @arg @ref LL_ADC_CHANNEL_26 (3)
3954 * @arg @ref LL_ADC_CHANNEL_27 (3)(4)
3955 * @arg @ref LL_ADC_CHANNEL_28 (3)(4)
3956 * @arg @ref LL_ADC_CHANNEL_29 (3)(4)
3957 * @arg @ref LL_ADC_CHANNEL_30 (3)(4)
3958 * @arg @ref LL_ADC_CHANNEL_31 (3)(4)
3959 * @arg @ref LL_ADC_CHANNEL_VREFINT (3)
3960 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (3)
3961 * @arg @ref LL_ADC_CHANNEL_VCOMP (3)
3962 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (3)(5)
3963 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (3)(5)
3964 * @arg @ref LL_ADC_CHANNEL_VOPAMP3 (3)(5)
3965 *
3966 * (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n
3967 * (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n
3968 * (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n
3969 * (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n
3970 * (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5
3971 * @retval Returned value can be one of the following values:
3972 * @arg @ref LL_ADC_SAMPLINGTIME_4CYCLES
3973 * @arg @ref LL_ADC_SAMPLINGTIME_9CYCLES
3974 * @arg @ref LL_ADC_SAMPLINGTIME_16CYCLES
3975 * @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES
3976 * @arg @ref LL_ADC_SAMPLINGTIME_48CYCLES
3977 * @arg @ref LL_ADC_SAMPLINGTIME_96CYCLES
3978 * @arg @ref LL_ADC_SAMPLINGTIME_192CYCLES
3979 * @arg @ref LL_ADC_SAMPLINGTIME_384CYCLES
3980 */
3981 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
3982 {
3983 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
3984
3985 return (uint32_t)(READ_BIT(*preg,
3986 ADC_SMPR3_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK))
3987 >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)
3988 );
3989 }
3990
3991 #if defined(COMP_CSR_FCH3)
3992 /**
3993 * @brief Set ADC channels routing.
3994 * @note Channel routing set configuration between ADC IP and GPIO pads,
3995 * it is used to increase ADC channels speed (setting of
3996 * direct channel).
3997 * @note This feature is specific to STM32L1, on devices
3998 * category Cat.3, Cat.4, Cat.5.
3999 * To use this function, COMP RCC clock domain must be enabled.
4000 * Refer to @ref LL_APB1_GRP1_PERIPH_COMP.
4001 * @rmtoll CSR FCH3 LL_ADC_SetChannelRouting
4002 * @rmtoll CSR FCH8 LL_ADC_SetChannelRouting
4003 * @rmtoll CSR RCH13 LL_ADC_SetChannelRouting
4004 * @param ADCx ADC instance
4005 * @param Channel This parameter can be one of the following values:
4006 * @arg @ref LL_ADC_CHANNEL_3_ROUTING (1)
4007 * @arg @ref LL_ADC_CHANNEL_8_ROUTING (2)
4008 * @arg @ref LL_ADC_CHANNEL_13_ROUTING (3)
4009 *
4010 * (1) Used as ADC direct channel (fast channel) if OPAMP1 is
4011 * in power down mode.\n
4012 * (2) Used as ADC direct channel (fast channel) if OPAMP2 is
4013 * in power down mode.\n
4014 * (3) Used as ADC re-routed channel if OPAMP3 is
4015 * in power down mode.
4016 * Otherwise, channel 13 is connected to OPAMP3 output and routed
4017 * through switches COMP1_SW1 and VCOMP to ADC switch matrix.
4018 * (Note: OPAMP3 is available on STM32L1 Cat.4 only).
4019 * @param Routing This parameter can be one of the following values:
4020 * @arg @ref LL_ADC_CHANNEL_ROUTING_DEFAULT
4021 * @arg @ref LL_ADC_CHANNEL_ROUTING_DIRECT
4022 */
4023 __STATIC_INLINE void LL_ADC_SetChannelRouting(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t Routing)
4024 {
4025 /* Note: Bit is located in comparator IP, but dedicated to ADC */
4026 MODIFY_REG(COMP->CSR, Channel, (Routing << POSITION_VAL(Channel)));
4027 }
4028
4029 /**
4030 * @brief Get ADC channels speed.
4031 * @note Channel routing set configuration between ADC IP and GPIO pads,
4032 * it is used to increase ADC channels speed (setting of
4033 * direct channel).
4034 * @note This feature is specific to STM32L1, on devices
4035 * category Cat.3, Cat.4, Cat.5.
4036 * To use this function, COMP RCC clock domain must be enabled.
4037 * Refer to @ref LL_APB1_GRP1_PERIPH_COMP.
4038 * @rmtoll CSR FCH3 LL_ADC_GetChannelRouting
4039 * @rmtoll CSR FCH8 LL_ADC_GetChannelRouting
4040 * @rmtoll CSR RCH13 LL_ADC_GetChannelRouting
4041 * @param ADCx ADC instance
4042 * @param Channel This parameter can be one of the following values:
4043 * @arg @ref LL_ADC_CHANNEL_3_ROUTING (1)
4044 * @arg @ref LL_ADC_CHANNEL_8_ROUTING (2)
4045 * @arg @ref LL_ADC_CHANNEL_13_ROUTING (3)
4046 *
4047 * (1) Used as ADC direct channel (fast channel) if OPAMP1 is
4048 * in power down mode.\n
4049 * (2) Used as ADC direct channel (fast channel) if OPAMP2 is
4050 * in power down mode.\n
4051 * (3) Used as ADC re-routed channel if OPAMP3 is
4052 * in power down mode.
4053 * Otherwise, channel 13 is connected to OPAMP3 output and routed
4054 * through switches COMP1_SW1 and VCOMP to ADC switch matrix.
4055 * (Note: OPAMP3 is available on STM32L1 Cat.4 only).
4056 * @retval Returned value can be one of the following values:
4057 * @arg @ref LL_ADC_CHANNEL_ROUTING_DEFAULT
4058 * @arg @ref LL_ADC_CHANNEL_ROUTING_DIRECT
4059 */
4060 __STATIC_INLINE uint32_t LL_ADC_GetChannelRouting(ADC_TypeDef *ADCx, uint32_t Channel)
4061 {
4062 /* Note: Bit is located in comparator IP, but dedicated to ADC */
4063 return (uint32_t)(READ_BIT(COMP->CSR, Channel) >> POSITION_VAL(Channel));
4064 }
4065 #endif
4066
4067 /**
4068 * @}
4069 */
4070
4071 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
4072 * @{
4073 */
4074
4075 /**
4076 * @brief Set ADC analog watchdog monitored channels:
4077 * a single channel or all channels,
4078 * on ADC groups regular and-or injected.
4079 * @note Once monitored channels are selected, analog watchdog
4080 * is enabled.
4081 * @note In case of need to define a single channel to monitor
4082 * with analog watchdog from sequencer channel definition,
4083 * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
4084 * @note On this STM32 serie, there is only 1 kind of analog watchdog
4085 * instance:
4086 * - AWD standard (instance AWD1):
4087 * - channels monitored: can monitor 1 channel or all channels.
4088 * - groups monitored: ADC groups regular and-or injected.
4089 * - resolution: resolution is not limited (corresponds to
4090 * ADC resolution configured).
4091 * @rmtoll CR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
4092 * CR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
4093 * CR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels
4094 * @param ADCx ADC instance
4095 * @param AWDChannelGroup This parameter can be one of the following values:
4096 * @arg @ref LL_ADC_AWD_DISABLE
4097 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
4098 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
4099 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
4100 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (2)
4101 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (2)
4102 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ (2)
4103 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (2)
4104 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (2)
4105 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ (2)
4106 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (2)
4107 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (2)
4108 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ (2)
4109 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (2)
4110 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (2)
4111 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ (2)
4112 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (1)
4113 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (1)
4114 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ (1)
4115 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (1)
4116 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (1)
4117 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ (1)
4118 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (2)
4119 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (2)
4120 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ (2)
4121 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (2)
4122 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (2)
4123 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ (2)
4124 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (2)
4125 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (2)
4126 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ (2)
4127 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (2)
4128 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (2)
4129 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ (2)
4130 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (2)
4131 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (2)
4132 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ (2)
4133 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (2)
4134 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (2)
4135 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ (2)
4136 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (2)
4137 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (2)
4138 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ (2)
4139 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (3)
4140 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (3)
4141 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ (3)
4142 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (3)
4143 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (3)
4144 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ (3)
4145 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (3)
4146 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (3)
4147 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ (3)
4148 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (3)
4149 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (3)
4150 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ (3)
4151 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (3)
4152 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (3)
4153 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ (3)
4154 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (3)
4155 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (3)
4156 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ (3)
4157 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG (3)
4158 * @arg @ref LL_ADC_AWD_CHANNEL_19_INJ (3)
4159 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ (3)
4160 * @arg @ref LL_ADC_AWD_CHANNEL_20_REG (3)
4161 * @arg @ref LL_ADC_AWD_CHANNEL_20_INJ (3)
4162 * @arg @ref LL_ADC_AWD_CHANNEL_20_REG_INJ (3)
4163 * @arg @ref LL_ADC_AWD_CHANNEL_21_REG (3)
4164 * @arg @ref LL_ADC_AWD_CHANNEL_21_INJ (3)
4165 * @arg @ref LL_ADC_AWD_CHANNEL_21_REG_INJ (3)
4166 * @arg @ref LL_ADC_AWD_CHANNEL_22_REG (1)
4167 * @arg @ref LL_ADC_AWD_CHANNEL_22_INJ (1)
4168 * @arg @ref LL_ADC_AWD_CHANNEL_22_REG_INJ (1)
4169 * @arg @ref LL_ADC_AWD_CHANNEL_23_REG (1)
4170 * @arg @ref LL_ADC_AWD_CHANNEL_23_INJ (1)
4171 * @arg @ref LL_ADC_AWD_CHANNEL_23_REG_INJ (1)
4172 * @arg @ref LL_ADC_AWD_CHANNEL_24_REG (1)
4173 * @arg @ref LL_ADC_AWD_CHANNEL_24_INJ (1)
4174 * @arg @ref LL_ADC_AWD_CHANNEL_24_REG_INJ (1)
4175 * @arg @ref LL_ADC_AWD_CHANNEL_25_REG (1)
4176 * @arg @ref LL_ADC_AWD_CHANNEL_25_INJ (1)
4177 * @arg @ref LL_ADC_AWD_CHANNEL_25_REG_INJ (1)
4178 * @arg @ref LL_ADC_AWD_CHANNEL_26_REG (3)
4179 * @arg @ref LL_ADC_AWD_CHANNEL_26_INJ (3)
4180 * @arg @ref LL_ADC_AWD_CHANNEL_26_REG_INJ (3)
4181 * @arg @ref LL_ADC_AWD_CHANNEL_27_REG (3)(4)
4182 * @arg @ref LL_ADC_AWD_CHANNEL_27_INJ (3)(4)
4183 * @arg @ref LL_ADC_AWD_CHANNEL_27_REG_INJ (3)(4)
4184 * @arg @ref LL_ADC_AWD_CHANNEL_28_REG (3)(4)
4185 * @arg @ref LL_ADC_AWD_CHANNEL_28_INJ (3)(4)
4186 * @arg @ref LL_ADC_AWD_CHANNEL_28_REG_INJ (3)(4)
4187 * @arg @ref LL_ADC_AWD_CHANNEL_29_REG (3)(4)
4188 * @arg @ref LL_ADC_AWD_CHANNEL_29_INJ (3)(4)
4189 * @arg @ref LL_ADC_AWD_CHANNEL_29_REG_INJ (3)(4)
4190 * @arg @ref LL_ADC_AWD_CHANNEL_30_REG (3)(4)
4191 * @arg @ref LL_ADC_AWD_CHANNEL_30_INJ (3)(4)
4192 * @arg @ref LL_ADC_AWD_CHANNEL_30_REG_INJ (3)(4)
4193 * @arg @ref LL_ADC_AWD_CHANNEL_31_REG (3)(4)
4194 * @arg @ref LL_ADC_AWD_CHANNEL_31_INJ (3)(4)
4195 * @arg @ref LL_ADC_AWD_CHANNEL_31_REG_INJ (3)(4)
4196 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (3)
4197 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (3)
4198 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (3)
4199 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (3)
4200 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (3)
4201 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (3)
4202 * @arg @ref LL_ADC_AWD_CH_VCOMP_REG (3)
4203 * @arg @ref LL_ADC_AWD_CH_VCOMP_INJ (3)
4204 * @arg @ref LL_ADC_AWD_CH_VCOMP_REG_INJ (3)
4205 * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG (3)(5)
4206 * @arg @ref LL_ADC_AWD_CH_VOPAMP1_INJ (3)(5)
4207 * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG_INJ (3)(5)
4208 * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG (3)(5)
4209 * @arg @ref LL_ADC_AWD_CH_VOPAMP2_INJ (3)(5)
4210 * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG_INJ (3)(5)
4211 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_REG (3)(5)
4212 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_INJ (3)(5)
4213 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_REG_INJ (3)(5)
4214 *
4215 * (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n
4216 * (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n
4217 * (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n
4218 * (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.\n
4219 * (5) On STM32L1, parameter not available on all devices: OPAMP1 and OPAMP2 available only on STM32L1 Cat.3, Cat.4 and Cat.5, OPAMP3 available only on STM32L1 Cat.4 and Cat.5
4220 * @retval None
4221 */
4222 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup)
4223 {
4224 MODIFY_REG(ADCx->CR1,
4225 (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH),
4226 AWDChannelGroup);
4227 }
4228
4229 /**
4230 * @brief Get ADC analog watchdog monitored channel.
4231 * @note Usage of the returned channel number:
4232 * - To reinject this channel into another function LL_ADC_xxx:
4233 * the returned channel number is only partly formatted on definition
4234 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
4235 * with parts of literals LL_ADC_CHANNEL_x or using
4236 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4237 * Then the selected literal LL_ADC_CHANNEL_x can be used
4238 * as parameter for another function.
4239 * - To get the channel number in decimal format:
4240 * process the returned value with the helper macro
4241 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4242 * Applicable only when the analog watchdog is set to monitor
4243 * one channel.
4244 * @note On this STM32 serie, there is only 1 kind of analog watchdog
4245 * instance:
4246 * - AWD standard (instance AWD1):
4247 * - channels monitored: can monitor 1 channel or all channels.
4248 * - groups monitored: ADC groups regular and-or injected.
4249 * - resolution: resolution is not limited (corresponds to
4250 * ADC resolution configured).
4251 * @rmtoll CR1 AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
4252 * CR1 AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
4253 * CR1 AWD1EN LL_ADC_GetAnalogWDMonitChannels
4254 * @param ADCx ADC instance
4255 * @retval Returned value can be one of the following values:
4256 * @arg @ref LL_ADC_AWD_DISABLE
4257 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
4258 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
4259 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
4260 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (2)
4261 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (2)
4262 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ (2)
4263 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (2)
4264 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (2)
4265 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ (2)
4266 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (2)
4267 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (2)
4268 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ (2)
4269 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (2)
4270 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (2)
4271 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ (2)
4272 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (1)
4273 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (1)
4274 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ (1)
4275 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (1)
4276 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (1)
4277 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ (1)
4278 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (2)
4279 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (2)
4280 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ (2)
4281 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (2)
4282 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (2)
4283 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ (2)
4284 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (2)
4285 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (2)
4286 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ (2)
4287 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (2)
4288 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (2)
4289 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ (2)
4290 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (2)
4291 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (2)
4292 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ (2)
4293 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (2)
4294 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (2)
4295 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ (2)
4296 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (2)
4297 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (2)
4298 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ (2)
4299 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (3)
4300 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (3)
4301 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ (3)
4302 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (3)
4303 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (3)
4304 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ (3)
4305 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (3)
4306 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (3)
4307 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ (3)
4308 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (3)
4309 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (3)
4310 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ (3)
4311 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (3)
4312 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (3)
4313 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ (3)
4314 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (3)
4315 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (3)
4316 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ (3)
4317 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG (3)
4318 * @arg @ref LL_ADC_AWD_CHANNEL_19_INJ (3)
4319 * @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ (3)
4320 * @arg @ref LL_ADC_AWD_CHANNEL_20_REG (3)
4321 * @arg @ref LL_ADC_AWD_CHANNEL_20_INJ (3)
4322 * @arg @ref LL_ADC_AWD_CHANNEL_20_REG_INJ (3)
4323 * @arg @ref LL_ADC_AWD_CHANNEL_21_REG (3)
4324 * @arg @ref LL_ADC_AWD_CHANNEL_21_INJ (3)
4325 * @arg @ref LL_ADC_AWD_CHANNEL_21_REG_INJ (3)
4326 * @arg @ref LL_ADC_AWD_CHANNEL_22_REG (1)
4327 * @arg @ref LL_ADC_AWD_CHANNEL_22_INJ (1)
4328 * @arg @ref LL_ADC_AWD_CHANNEL_22_REG_INJ (1)
4329 * @arg @ref LL_ADC_AWD_CHANNEL_23_REG (1)
4330 * @arg @ref LL_ADC_AWD_CHANNEL_23_INJ (1)
4331 * @arg @ref LL_ADC_AWD_CHANNEL_23_REG_INJ (1)
4332 * @arg @ref LL_ADC_AWD_CHANNEL_24_REG (1)
4333 * @arg @ref LL_ADC_AWD_CHANNEL_24_INJ (1)
4334 * @arg @ref LL_ADC_AWD_CHANNEL_24_REG_INJ (1)
4335 * @arg @ref LL_ADC_AWD_CHANNEL_25_REG (1)
4336 * @arg @ref LL_ADC_AWD_CHANNEL_25_INJ (1)
4337 * @arg @ref LL_ADC_AWD_CHANNEL_25_REG_INJ (1)
4338 * @arg @ref LL_ADC_AWD_CHANNEL_26_REG (3)
4339 * @arg @ref LL_ADC_AWD_CHANNEL_26_INJ (3)
4340 * @arg @ref LL_ADC_AWD_CHANNEL_26_REG_INJ (3)
4341 * @arg @ref LL_ADC_AWD_CHANNEL_27_REG (3)(4)
4342 * @arg @ref LL_ADC_AWD_CHANNEL_27_INJ (3)(4)
4343 * @arg @ref LL_ADC_AWD_CHANNEL_27_REG_INJ (3)(4)
4344 * @arg @ref LL_ADC_AWD_CHANNEL_28_REG (3)(4)
4345 * @arg @ref LL_ADC_AWD_CHANNEL_28_INJ (3)(4)
4346 * @arg @ref LL_ADC_AWD_CHANNEL_28_REG_INJ (3)(4)
4347 * @arg @ref LL_ADC_AWD_CHANNEL_29_REG (3)(4)
4348 * @arg @ref LL_ADC_AWD_CHANNEL_29_INJ (3)(4)
4349 * @arg @ref LL_ADC_AWD_CHANNEL_29_REG_INJ (3)(4)
4350 * @arg @ref LL_ADC_AWD_CHANNEL_30_REG (3)(4)
4351 * @arg @ref LL_ADC_AWD_CHANNEL_30_INJ (3)(4)
4352 * @arg @ref LL_ADC_AWD_CHANNEL_30_REG_INJ (3)(4)
4353 * @arg @ref LL_ADC_AWD_CHANNEL_31_REG (3)(4)
4354 * @arg @ref LL_ADC_AWD_CHANNEL_31_INJ (3)(4)
4355 * @arg @ref LL_ADC_AWD_CHANNEL_31_REG_INJ (3)(4)
4356 *
4357 * (1) On STM32L1, connection via routing interface (RI) specificity: fast channel (channel routed directly to ADC switch matrix).\n
4358 * (2) On STM32L1, for devices with feature 'channels banks' available: Channel different in bank A and bank B.\n
4359 * (3) On STM32L1, for devices with feature 'channels banks' available: Channel common to both bank A and bank B.\n
4360 * (4) On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5.
4361 */
4362 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx)
4363 {
4364 return (uint32_t)(READ_BIT(ADCx->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH)));
4365 }
4366
4367 /**
4368 * @brief Set ADC analog watchdog threshold value of threshold
4369 * high or low.
4370 * @note In case of ADC resolution different of 12 bits,
4371 * analog watchdog thresholds data require a specific shift.
4372 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
4373 * @note On this STM32 serie, there is only 1 kind of analog watchdog
4374 * instance:
4375 * - AWD standard (instance AWD1):
4376 * - channels monitored: can monitor 1 channel or all channels.
4377 * - groups monitored: ADC groups regular and-or injected.
4378 * - resolution: resolution is not limited (corresponds to
4379 * ADC resolution configured).
4380 * @rmtoll HTR HT LL_ADC_SetAnalogWDThresholds\n
4381 * LTR LT LL_ADC_SetAnalogWDThresholds
4382 * @param ADCx ADC instance
4383 * @param AWDThresholdsHighLow This parameter can be one of the following values:
4384 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
4385 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
4386 * @param AWDThresholdValue: Value between Min_Data=0x000 and Max_Data=0xFFF
4387 * @retval None
4388 */
4389 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
4390 {
4391 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
4392
4393 MODIFY_REG(*preg,
4394 ADC_HTR_HT,
4395 AWDThresholdValue);
4396 }
4397
4398 /**
4399 * @brief Get ADC analog watchdog threshold value of threshold high or
4400 * threshold low.
4401 * @note In case of ADC resolution different of 12 bits,
4402 * analog watchdog thresholds data require a specific shift.
4403 * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
4404 * @rmtoll HTR HT LL_ADC_GetAnalogWDThresholds\n
4405 * LTR LT LL_ADC_GetAnalogWDThresholds
4406 * @param ADCx ADC instance
4407 * @param AWDThresholdsHighLow This parameter can be one of the following values:
4408 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
4409 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
4410 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
4411 */
4412 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)
4413 {
4414 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
4415
4416 return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT));
4417 }
4418
4419 /**
4420 * @}
4421 */
4422
4423 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
4424 * @{
4425 */
4426
4427 /**
4428 * @brief Enable the selected ADC instance.
4429 * @note On this STM32 serie, after ADC enable, a delay for
4430 * ADC internal analog stabilization is required before performing a
4431 * ADC conversion start.
4432 * Refer to device datasheet, parameter tSTAB.
4433 * @note Due to the latency introduced by the synchronization between
4434 * two clock domains (ADC clock source asynchronous),
4435 * some hardware constraints must be respected:
4436 * - ADC must be enabled (@ref LL_ADC_Enable() ) only
4437 * when ADC is not ready to convert.
4438 * - ADC must be disabled (@ref LL_ADC_Disable() ) only
4439 * when ADC is ready to convert.
4440 * Status of ADC ready to convert can be checked using function
4441 * @ref LL_ADC_IsActiveFlag_ADRDY().
4442 * @rmtoll CR2 ADON LL_ADC_Enable
4443 * @param ADCx ADC instance
4444 * @retval None
4445 */
4446 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
4447 {
4448 SET_BIT(ADCx->CR2, ADC_CR2_ADON);
4449 }
4450
4451 /**
4452 * @brief Disable the selected ADC instance.
4453 * @note Due to the latency introduced by the synchronization between
4454 * two clock domains (ADC clock source asynchronous),
4455 * some hardware constraints must be respected:
4456 * - ADC must be enabled (@ref LL_ADC_Enable() ) only
4457 * when ADC is not ready to convert.
4458 * - ADC must be disabled (@ref LL_ADC_Disable() ) only
4459 * when ADC is ready to convert.
4460 * Status of ADC ready to convert can be checked using function
4461 * @ref LL_ADC_IsActiveFlag_ADRDY().
4462 * @rmtoll CR2 ADON LL_ADC_Disable
4463 * @param ADCx ADC instance
4464 * @retval None
4465 */
4466 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
4467 {
4468 CLEAR_BIT(ADCx->CR2, ADC_CR2_ADON);
4469 }
4470
4471 /**
4472 * @brief Get the selected ADC instance enable state.
4473 * @rmtoll CR2 ADON LL_ADC_IsEnabled
4474 * @param ADCx ADC instance
4475 * @retval 0: ADC is disabled, 1: ADC is enabled.
4476 */
4477 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
4478 {
4479 return (READ_BIT(ADCx->CR2, ADC_CR2_ADON) == (ADC_CR2_ADON));
4480 }
4481
4482 /**
4483 * @}
4484 */
4485
4486 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
4487 * @{
4488 */
4489
4490 /**
4491 * @brief Start ADC group regular conversion.
4492 * @note On this STM32 serie, this function is relevant only for
4493 * internal trigger (SW start), not for external trigger:
4494 * - If ADC trigger has been set to software start, ADC conversion
4495 * starts immediately.
4496 * - If ADC trigger has been set to external trigger, ADC conversion
4497 * start must be performed using function
4498 * @ref LL_ADC_REG_StartConversionExtTrig().
4499 * (if external trigger edge would have been set during ADC other
4500 * settings, ADC conversion would start at trigger event
4501 * as soon as ADC is enabled).
4502 * @rmtoll CR2 SWSTART LL_ADC_REG_StartConversionSWStart
4503 * @param ADCx ADC instance
4504 * @retval None
4505 */
4506 __STATIC_INLINE void LL_ADC_REG_StartConversionSWStart(ADC_TypeDef *ADCx)
4507 {
4508 SET_BIT(ADCx->CR2, ADC_CR2_SWSTART);
4509 }
4510
4511 /**
4512 * @brief Start ADC group regular conversion from external trigger.
4513 * @note ADC conversion will start at next trigger event (on the selected
4514 * trigger edge) following the ADC start conversion command.
4515 * @note On this STM32 serie, this function is relevant for
4516 * ADC conversion start from external trigger.
4517 * If internal trigger (SW start) is needed, perform ADC conversion
4518 * start using function @ref LL_ADC_REG_StartConversionSWStart().
4519 * @rmtoll CR2 EXTEN LL_ADC_REG_StartConversionExtTrig
4520 * @param ExternalTriggerEdge This parameter can be one of the following values:
4521 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
4522 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
4523 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
4524 * @param ADCx ADC instance
4525 * @retval None
4526 */
4527 __STATIC_INLINE void LL_ADC_REG_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
4528 {
4529 SET_BIT(ADCx->CR2, ExternalTriggerEdge);
4530 }
4531
4532 /**
4533 * @brief Stop ADC group regular conversion from external trigger.
4534 * @note No more ADC conversion will start at next trigger event
4535 * following the ADC stop conversion command.
4536 * If a conversion is on-going, it will be completed.
4537 * @note On this STM32 serie, there is no specific command
4538 * to stop a conversion on-going or to stop ADC converting
4539 * in continuous mode. These actions can be performed
4540 * using function @ref LL_ADC_Disable().
4541 * @rmtoll CR2 EXTEN LL_ADC_REG_StopConversionExtTrig
4542 * @param ADCx ADC instance
4543 * @retval None
4544 */
4545 __STATIC_INLINE void LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef *ADCx)
4546 {
4547 CLEAR_BIT(ADCx->CR2, ADC_CR2_EXTEN);
4548 }
4549
4550 /**
4551 * @brief Get ADC group regular conversion data, range fit for
4552 * all ADC configurations: all ADC resolutions and
4553 * all oversampling increased data width (for devices
4554 * with feature oversampling).
4555 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
4556 * @param ADCx ADC instance
4557 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
4558 */
4559 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
4560 {
4561 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
4562 }
4563
4564 /**
4565 * @brief Get ADC group regular conversion data, range fit for
4566 * ADC resolution 12 bits.
4567 * @note For devices with feature oversampling: Oversampling
4568 * can increase data width, function for extended range
4569 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
4570 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
4571 * @param ADCx ADC instance
4572 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
4573 */
4574 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
4575 {
4576 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
4577 }
4578
4579 /**
4580 * @brief Get ADC group regular conversion data, range fit for
4581 * ADC resolution 10 bits.
4582 * @note For devices with feature oversampling: Oversampling
4583 * can increase data width, function for extended range
4584 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
4585 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10
4586 * @param ADCx ADC instance
4587 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
4588 */
4589 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
4590 {
4591 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
4592 }
4593
4594 /**
4595 * @brief Get ADC group regular conversion data, range fit for
4596 * ADC resolution 8 bits.
4597 * @note For devices with feature oversampling: Oversampling
4598 * can increase data width, function for extended range
4599 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
4600 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8
4601 * @param ADCx ADC instance
4602 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
4603 */
4604 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
4605 {
4606 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
4607 }
4608
4609 /**
4610 * @brief Get ADC group regular conversion data, range fit for
4611 * ADC resolution 6 bits.
4612 * @note For devices with feature oversampling: Oversampling
4613 * can increase data width, function for extended range
4614 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
4615 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData6
4616 * @param ADCx ADC instance
4617 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
4618 */
4619 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
4620 {
4621 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
4622 }
4623
4624 /**
4625 * @}
4626 */
4627
4628 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
4629 * @{
4630 */
4631
4632 /**
4633 * @brief Start ADC group injected conversion.
4634 * @note On this STM32 serie, this function is relevant only for
4635 * internal trigger (SW start), not for external trigger:
4636 * - If ADC trigger has been set to software start, ADC conversion
4637 * starts immediately.
4638 * - If ADC trigger has been set to external trigger, ADC conversion
4639 * start must be performed using function
4640 * @ref LL_ADC_INJ_StartConversionExtTrig().
4641 * (if external trigger edge would have been set during ADC other
4642 * settings, ADC conversion would start at trigger event
4643 * as soon as ADC is enabled).
4644 * @rmtoll CR2 JSWSTART LL_ADC_INJ_StartConversionSWStart
4645 * @param ADCx ADC instance
4646 * @retval None
4647 */
4648 __STATIC_INLINE void LL_ADC_INJ_StartConversionSWStart(ADC_TypeDef *ADCx)
4649 {
4650 SET_BIT(ADCx->CR2, ADC_CR2_JSWSTART);
4651 }
4652
4653 /**
4654 * @brief Start ADC group injected conversion from external trigger.
4655 * @note ADC conversion will start at next trigger event (on the selected
4656 * trigger edge) following the ADC start conversion command.
4657 * @note On this STM32 serie, this function is relevant for
4658 * ADC conversion start from external trigger.
4659 * If internal trigger (SW start) is needed, perform ADC conversion
4660 * start using function @ref LL_ADC_INJ_StartConversionSWStart().
4661 * @rmtoll CR2 JEXTEN LL_ADC_INJ_StartConversionExtTrig
4662 * @param ExternalTriggerEdge This parameter can be one of the following values:
4663 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
4664 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
4665 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
4666 * @param ADCx ADC instance
4667 * @retval None
4668 */
4669 __STATIC_INLINE void LL_ADC_INJ_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
4670 {
4671 SET_BIT(ADCx->CR2, ExternalTriggerEdge);
4672 }
4673
4674 /**
4675 * @brief Stop ADC group injected conversion from external trigger.
4676 * @note No more ADC conversion will start at next trigger event
4677 * following the ADC stop conversion command.
4678 * If a conversion is on-going, it will be completed.
4679 * @note On this STM32 serie, there is no specific command
4680 * to stop a conversion on-going or to stop ADC converting
4681 * in continuous mode. These actions can be performed
4682 * using function @ref LL_ADC_Disable().
4683 * @rmtoll CR2 JEXTEN LL_ADC_INJ_StopConversionExtTrig
4684 * @param ADCx ADC instance
4685 * @retval None
4686 */
4687 __STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx)
4688 {
4689 CLEAR_BIT(ADCx->CR2, ADC_CR2_JEXTEN);
4690 }
4691
4692 /**
4693 * @brief Get ADC group regular conversion data, range fit for
4694 * all ADC configurations: all ADC resolutions and
4695 * all oversampling increased data width (for devices
4696 * with feature oversampling).
4697 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n
4698 * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n
4699 * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n
4700 * JDR4 JDATA LL_ADC_INJ_ReadConversionData32
4701 * @param ADCx ADC instance
4702 * @param Rank This parameter can be one of the following values:
4703 * @arg @ref LL_ADC_INJ_RANK_1
4704 * @arg @ref LL_ADC_INJ_RANK_2
4705 * @arg @ref LL_ADC_INJ_RANK_3
4706 * @arg @ref LL_ADC_INJ_RANK_4
4707 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
4708 */
4709 __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
4710 {
4711 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
4712
4713 return (uint32_t)(READ_BIT(*preg,
4714 ADC_JDR1_JDATA)
4715 );
4716 }
4717
4718 /**
4719 * @brief Get ADC group injected conversion data, range fit for
4720 * ADC resolution 12 bits.
4721 * @note For devices with feature oversampling: Oversampling
4722 * can increase data width, function for extended range
4723 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
4724 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n
4725 * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n
4726 * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n
4727 * JDR4 JDATA LL_ADC_INJ_ReadConversionData12
4728 * @param ADCx ADC instance
4729 * @param Rank This parameter can be one of the following values:
4730 * @arg @ref LL_ADC_INJ_RANK_1
4731 * @arg @ref LL_ADC_INJ_RANK_2
4732 * @arg @ref LL_ADC_INJ_RANK_3
4733 * @arg @ref LL_ADC_INJ_RANK_4
4734 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
4735 */
4736 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
4737 {
4738 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
4739
4740 return (uint16_t)(READ_BIT(*preg,
4741 ADC_JDR1_JDATA)
4742 );
4743 }
4744
4745 /**
4746 * @brief Get ADC group injected conversion data, range fit for
4747 * ADC resolution 10 bits.
4748 * @note For devices with feature oversampling: Oversampling
4749 * can increase data width, function for extended range
4750 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
4751 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n
4752 * JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n
4753 * JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n
4754 * JDR4 JDATA LL_ADC_INJ_ReadConversionData10
4755 * @param ADCx ADC instance
4756 * @param Rank This parameter can be one of the following values:
4757 * @arg @ref LL_ADC_INJ_RANK_1
4758 * @arg @ref LL_ADC_INJ_RANK_2
4759 * @arg @ref LL_ADC_INJ_RANK_3
4760 * @arg @ref LL_ADC_INJ_RANK_4
4761 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
4762 */
4763 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
4764 {
4765 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
4766
4767 return (uint16_t)(READ_BIT(*preg,
4768 ADC_JDR1_JDATA)
4769 );
4770 }
4771
4772 /**
4773 * @brief Get ADC group injected conversion data, range fit for
4774 * ADC resolution 8 bits.
4775 * @note For devices with feature oversampling: Oversampling
4776 * can increase data width, function for extended range
4777 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
4778 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n
4779 * JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n
4780 * JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n
4781 * JDR4 JDATA LL_ADC_INJ_ReadConversionData8
4782 * @param ADCx ADC instance
4783 * @param Rank This parameter can be one of the following values:
4784 * @arg @ref LL_ADC_INJ_RANK_1
4785 * @arg @ref LL_ADC_INJ_RANK_2
4786 * @arg @ref LL_ADC_INJ_RANK_3
4787 * @arg @ref LL_ADC_INJ_RANK_4
4788 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
4789 */
4790 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
4791 {
4792 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
4793
4794 return (uint8_t)(READ_BIT(*preg,
4795 ADC_JDR1_JDATA)
4796 );
4797 }
4798
4799 /**
4800 * @brief Get ADC group injected conversion data, range fit for
4801 * ADC resolution 6 bits.
4802 * @note For devices with feature oversampling: Oversampling
4803 * can increase data width, function for extended range
4804 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
4805 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData6\n
4806 * JDR2 JDATA LL_ADC_INJ_ReadConversionData6\n
4807 * JDR3 JDATA LL_ADC_INJ_ReadConversionData6\n
4808 * JDR4 JDATA LL_ADC_INJ_ReadConversionData6
4809 * @param ADCx ADC instance
4810 * @param Rank This parameter can be one of the following values:
4811 * @arg @ref LL_ADC_INJ_RANK_1
4812 * @arg @ref LL_ADC_INJ_RANK_2
4813 * @arg @ref LL_ADC_INJ_RANK_3
4814 * @arg @ref LL_ADC_INJ_RANK_4
4815 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
4816 */
4817 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank)
4818 {
4819 register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
4820
4821 return (uint8_t)(READ_BIT(*preg,
4822 ADC_JDR1_JDATA)
4823 );
4824 }
4825
4826 /**
4827 * @}
4828 */
4829
4830 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
4831 * @{
4832 */
4833
4834 /**
4835 * @brief Get flag ADC ready.
4836 * @rmtoll SR ADONS LL_ADC_IsActiveFlag_ADRDY
4837 * @param ADCx ADC instance
4838 * @retval State of bit (1 or 0).
4839 */
4840 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)
4841 {
4842 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY));
4843 }
4844
4845 /**
4846 * @brief Get flag ADC group regular end of unitary conversion
4847 * or end of sequence conversions, depending on
4848 * ADC configuration.
4849 * @note To configure flag of end of conversion,
4850 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4851 * @rmtoll SR EOC LL_ADC_IsActiveFlag_EOCS
4852 * @param ADCx ADC instance
4853 * @retval State of bit (1 or 0).
4854 */
4855 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCS(ADC_TypeDef *ADCx)
4856 {
4857 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_EOCS) == (LL_ADC_FLAG_EOCS));
4858 }
4859
4860 /**
4861 * @brief Get flag ADC group regular overrun.
4862 * @rmtoll SR OVR LL_ADC_IsActiveFlag_OVR
4863 * @param ADCx ADC instance
4864 * @retval State of bit (1 or 0).
4865 */
4866 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
4867 {
4868 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR));
4869 }
4870
4871
4872 /**
4873 * @brief Get flag ADC group injected end of sequence conversions.
4874 * @rmtoll SR JEOC LL_ADC_IsActiveFlag_JEOS
4875 * @param ADCx ADC instance
4876 * @retval State of bit (1 or 0).
4877 */
4878 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
4879 {
4880 /* Note: on this STM32 serie, there is no flag ADC group injected */
4881 /* end of unitary conversion. */
4882 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4883 /* in other STM32 families). */
4884 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS));
4885 }
4886
4887 /**
4888 * @brief Get flag ADC analog watchdog 1 flag
4889 * @rmtoll SR AWD LL_ADC_IsActiveFlag_AWD1
4890 * @param ADCx ADC instance
4891 * @retval State of bit (1 or 0).
4892 */
4893 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
4894 {
4895 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
4896 }
4897
4898 /**
4899 * @brief Clear flag ADC group regular end of unitary conversion
4900 * or end of sequence conversions, depending on
4901 * ADC configuration.
4902 * @note To configure flag of end of conversion,
4903 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4904 * @rmtoll SR EOC LL_ADC_ClearFlag_EOCS
4905 * @param ADCx ADC instance
4906 * @retval None
4907 */
4908 __STATIC_INLINE void LL_ADC_ClearFlag_EOCS(ADC_TypeDef *ADCx)
4909 {
4910 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_EOCS);
4911 }
4912
4913 /**
4914 * @brief Clear flag ADC group regular overrun.
4915 * @rmtoll SR OVR LL_ADC_ClearFlag_OVR
4916 * @param ADCx ADC instance
4917 * @retval None
4918 */
4919 __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
4920 {
4921 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_OVR);
4922 }
4923
4924
4925 /**
4926 * @brief Clear flag ADC group injected end of sequence conversions.
4927 * @rmtoll SR JEOC LL_ADC_ClearFlag_JEOS
4928 * @param ADCx ADC instance
4929 * @retval None
4930 */
4931 __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
4932 {
4933 /* Note: on this STM32 serie, there is no flag ADC group injected */
4934 /* end of unitary conversion. */
4935 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4936 /* in other STM32 families). */
4937 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_JEOS);
4938 }
4939
4940 /**
4941 * @brief Clear flag ADC analog watchdog 1.
4942 * @rmtoll SR AWD LL_ADC_ClearFlag_AWD1
4943 * @param ADCx ADC instance
4944 * @retval None
4945 */
4946 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
4947 {
4948 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_AWD1);
4949 }
4950
4951 /**
4952 * @}
4953 */
4954
4955 /** @defgroup ADC_LL_EF_IT_Management ADC IT management
4956 * @{
4957 */
4958
4959 /**
4960 * @brief Enable interruption ADC group regular end of unitary conversion
4961 * or end of sequence conversions, depending on
4962 * ADC configuration.
4963 * @note To configure flag of end of conversion,
4964 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
4965 * @rmtoll CR1 EOCIE LL_ADC_EnableIT_EOCS
4966 * @param ADCx ADC instance
4967 * @retval None
4968 */
4969 __STATIC_INLINE void LL_ADC_EnableIT_EOCS(ADC_TypeDef *ADCx)
4970 {
4971 SET_BIT(ADCx->CR1, LL_ADC_IT_EOCS);
4972 }
4973
4974 /**
4975 * @brief Enable ADC group regular interruption overrun.
4976 * @rmtoll CR1 OVRIE LL_ADC_EnableIT_OVR
4977 * @param ADCx ADC instance
4978 * @retval None
4979 */
4980 __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
4981 {
4982 SET_BIT(ADCx->CR1, LL_ADC_IT_OVR);
4983 }
4984
4985
4986 /**
4987 * @brief Enable interruption ADC group injected end of sequence conversions.
4988 * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
4989 * @param ADCx ADC instance
4990 * @retval None
4991 */
4992 __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
4993 {
4994 /* Note: on this STM32 serie, there is no flag ADC group injected */
4995 /* end of unitary conversion. */
4996 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4997 /* in other STM32 families). */
4998 SET_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
4999 }
5000
5001 /**
5002 * @brief Enable interruption ADC analog watchdog 1.
5003 * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
5004 * @param ADCx ADC instance
5005 * @retval None
5006 */
5007 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
5008 {
5009 SET_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
5010 }
5011
5012 /**
5013 * @brief Disable interruption ADC group regular end of unitary conversion
5014 * or end of sequence conversions, depending on
5015 * ADC configuration.
5016 * @note To configure flag of end of conversion,
5017 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
5018 * @rmtoll CR1 EOCIE LL_ADC_DisableIT_EOCS
5019 * @param ADCx ADC instance
5020 * @retval None
5021 */
5022 __STATIC_INLINE void LL_ADC_DisableIT_EOCS(ADC_TypeDef *ADCx)
5023 {
5024 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_EOCS);
5025 }
5026
5027 /**
5028 * @brief Disable interruption ADC group regular overrun.
5029 * @rmtoll CR1 OVRIE LL_ADC_DisableIT_OVR
5030 * @param ADCx ADC instance
5031 * @retval None
5032 */
5033 __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
5034 {
5035 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_OVR);
5036 }
5037
5038
5039 /**
5040 * @brief Disable interruption ADC group injected end of sequence conversions.
5041 * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
5042 * @param ADCx ADC instance
5043 * @retval None
5044 */
5045 __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
5046 {
5047 /* Note: on this STM32 serie, there is no flag ADC group injected */
5048 /* end of unitary conversion. */
5049 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
5050 /* in other STM32 families). */
5051 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
5052 }
5053
5054 /**
5055 * @brief Disable interruption ADC analog watchdog 1.
5056 * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
5057 * @param ADCx ADC instance
5058 * @retval None
5059 */
5060 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
5061 {
5062 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
5063 }
5064
5065 /**
5066 * @brief Get state of interruption ADC group regular end of unitary conversion
5067 * or end of sequence conversions, depending on
5068 * ADC configuration.
5069 * @note To configure flag of end of conversion,
5070 * use function @ref LL_ADC_REG_SetFlagEndOfConversion().
5071 * (0: interrupt disabled, 1: interrupt enabled)
5072 * @rmtoll CR1 EOCIE LL_ADC_IsEnabledIT_EOCS
5073 * @param ADCx ADC instance
5074 * @retval State of bit (1 or 0).
5075 */
5076 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCS(ADC_TypeDef *ADCx)
5077 {
5078 return (READ_BIT(ADCx->CR1, LL_ADC_IT_EOCS) == (LL_ADC_IT_EOCS));
5079 }
5080
5081 /**
5082 * @brief Get state of interruption ADC group regular overrun
5083 * (0: interrupt disabled, 1: interrupt enabled).
5084 * @rmtoll CR1 OVRIE LL_ADC_IsEnabledIT_OVR
5085 * @param ADCx ADC instance
5086 * @retval State of bit (1 or 0).
5087 */
5088 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
5089 {
5090 return (READ_BIT(ADCx->CR1, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR));
5091 }
5092
5093
5094 /**
5095 * @brief Get state of interruption ADC group injected end of sequence conversions
5096 * (0: interrupt disabled, 1: interrupt enabled).
5097 * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
5098 * @param ADCx ADC instance
5099 * @retval State of bit (1 or 0).
5100 */
5101 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
5102 {
5103 /* Note: on this STM32 serie, there is no flag ADC group injected */
5104 /* end of unitary conversion. */
5105 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
5106 /* in other STM32 families). */
5107 return (READ_BIT(ADCx->CR1, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS));
5108 }
5109
5110 /**
5111 * @brief Get state of interruption ADC analog watchdog 1
5112 * (0: interrupt disabled, 1: interrupt enabled).
5113 * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
5114 * @param ADCx ADC instance
5115 * @retval State of bit (1 or 0).
5116 */
5117 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
5118 {
5119 return (READ_BIT(ADCx->CR1, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1));
5120 }
5121
5122 /**
5123 * @}
5124 */
5125
5126 #if defined(USE_FULL_LL_DRIVER)
5127 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
5128 * @{
5129 */
5130
5131 /* Initialization of some features of ADC common parameters and multimode */
5132 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
5133 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
5134 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
5135
5136 /* De-initialization of ADC instance, ADC group regular and ADC group injected */
5137 /* (availability of ADC group injected depends on STM32 families) */
5138 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
5139
5140 /* Initialization of some features of ADC instance */
5141 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
5142 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
5143
5144 /* Initialization of some features of ADC instance and ADC group regular */
5145 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
5146 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
5147
5148 /* Initialization of some features of ADC instance and ADC group injected */
5149 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
5150 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
5151
5152 /**
5153 * @}
5154 */
5155 #endif /* USE_FULL_LL_DRIVER */
5156
5157 /**
5158 * @}
5159 */
5160
5161 /**
5162 * @}
5163 */
5164
5165 #endif /* ADC1 */
5166
5167 /**
5168 * @}
5169 */
5170
5171 #ifdef __cplusplus
5172 }
5173 #endif
5174
5175 #endif /* __STM32L1xx_LL_ADC_H */
5176
5177 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
5178