1 /* 2 * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <drivers/arm/tzc400.h> 11 #include <lib/utils_def.h> 12 #include <plat/arm/board/common/v2m_def.h> 13 #include <plat/arm/common/arm_def.h> 14 #include <plat/arm/common/arm_spm_def.h> 15 #include <plat/common/common_def.h> 16 17 #include "../fvp_def.h" 18 19 /* Required platform porting definitions */ 20 #define PLATFORM_CORE_COUNT (U(FVP_CLUSTER_COUNT) * \ 21 U(FVP_MAX_CPUS_PER_CLUSTER) * \ 22 U(FVP_MAX_PE_PER_CPU)) 23 24 #define PLAT_NUM_PWR_DOMAINS (U(FVP_CLUSTER_COUNT) + \ 25 PLATFORM_CORE_COUNT + U(1)) 26 27 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 28 29 /* 30 * Other platform porting definitions are provided by included headers 31 */ 32 33 /* 34 * Required ARM standard platform porting definitions 35 */ 36 #define PLAT_ARM_CLUSTER_COUNT U(FVP_CLUSTER_COUNT) 37 38 #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */ 39 40 #define PLAT_ARM_TRUSTED_ROM_BASE UL(0x00000000) 41 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x04000000) /* 64 MB */ 42 43 #define PLAT_ARM_TRUSTED_DRAM_BASE UL(0x06000000) 44 #define PLAT_ARM_TRUSTED_DRAM_SIZE UL(0x02000000) /* 32 MB */ 45 46 /* 47 * Max size of SPMC is 2MB for fvp. With SPMD enabled this value corresponds to 48 * max size of BL32 image. 49 */ 50 #if defined(SPD_spmd) 51 #define PLAT_ARM_SPMC_BASE PLAT_ARM_TRUSTED_DRAM_BASE 52 #define PLAT_ARM_SPMC_SIZE UL(0x200000) /* 2 MB */ 53 #endif 54 55 /* virtual address used by dynamic mem_protect for chunk_base */ 56 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 57 58 /* No SCP in FVP */ 59 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x0) 60 61 #define PLAT_ARM_DRAM2_BASE ULL(0x880000000) 62 #define PLAT_ARM_DRAM2_SIZE UL(0x80000000) 63 64 #define PLAT_HW_CONFIG_DTB_BASE ULL(0x82000000) 65 #define PLAT_HW_CONFIG_DTB_SIZE ULL(0x8000) 66 67 #define ARM_DTB_DRAM_NS MAP_REGION_FLAT( \ 68 PLAT_HW_CONFIG_DTB_BASE, \ 69 PLAT_HW_CONFIG_DTB_SIZE, \ 70 MT_MEMORY | MT_RO | MT_NS) 71 /* 72 * Load address of BL33 for this platform port 73 */ 74 #define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + UL(0x8000000)) 75 76 /* 77 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 78 * plat_arm_mmap array defined for each BL stage. 79 */ 80 #if defined(IMAGE_BL31) 81 # if SPM_MM 82 # define PLAT_ARM_MMAP_ENTRIES 10 83 # define MAX_XLAT_TABLES 9 84 # define PLAT_SP_IMAGE_MMAP_REGIONS 30 85 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 86 # else 87 # define PLAT_ARM_MMAP_ENTRIES 9 88 # if USE_DEBUGFS 89 # define MAX_XLAT_TABLES 8 90 # else 91 # define MAX_XLAT_TABLES 7 92 # endif 93 # endif 94 #elif defined(IMAGE_BL32) 95 # define PLAT_ARM_MMAP_ENTRIES 9 96 # define MAX_XLAT_TABLES 6 97 #elif !USE_ROMLIB 98 # define PLAT_ARM_MMAP_ENTRIES 11 99 # define MAX_XLAT_TABLES 5 100 #else 101 # define PLAT_ARM_MMAP_ENTRIES 12 102 # define MAX_XLAT_TABLES 6 103 #endif 104 105 /* 106 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 107 * plus a little space for growth. 108 */ 109 #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) 110 111 /* 112 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 113 */ 114 115 #if USE_ROMLIB 116 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) 117 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) 118 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0x5000) 119 #else 120 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) 121 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) 122 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0) 123 #endif 124 125 /* 126 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 127 * little space for growth. 128 */ 129 #if TRUSTED_BOARD_BOOT 130 #if COT_DESC_IN_DTB 131 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1E000) - FVP_BL2_ROMLIB_OPTIMIZATION) 132 #else 133 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - FVP_BL2_ROMLIB_OPTIMIZATION) 134 #endif 135 #else 136 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x13000) - FVP_BL2_ROMLIB_OPTIMIZATION) 137 #endif 138 139 #if RESET_TO_BL31 140 /* Size of Trusted SRAM - the first 4KB of shared memory */ 141 #define PLAT_ARM_MAX_BL31_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 142 ARM_SHARED_RAM_SIZE) 143 #else 144 /* 145 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 146 * calculated using the current BL31 PROGBITS debug size plus the sizes of 147 * BL2 and BL1-RW 148 */ 149 #define PLAT_ARM_MAX_BL31_SIZE UL(0x3D000) 150 #endif /* RESET_TO_BL31 */ 151 152 #ifndef __aarch64__ 153 /* 154 * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is 155 * calculated using the current SP_MIN PROGBITS debug size plus the sizes of 156 * BL2 and BL1-RW 157 */ 158 # define PLAT_ARM_MAX_BL32_SIZE UL(0x3B000) 159 #endif 160 161 /* 162 * Size of cacheable stacks 163 */ 164 #if defined(IMAGE_BL1) 165 # if TRUSTED_BOARD_BOOT 166 # define PLATFORM_STACK_SIZE UL(0x1000) 167 # else 168 # define PLATFORM_STACK_SIZE UL(0x500) 169 # endif 170 #elif defined(IMAGE_BL2) 171 # if TRUSTED_BOARD_BOOT 172 # define PLATFORM_STACK_SIZE UL(0x1000) 173 # else 174 # define PLATFORM_STACK_SIZE UL(0x440) 175 # endif 176 #elif defined(IMAGE_BL2U) 177 # define PLATFORM_STACK_SIZE UL(0x400) 178 #elif defined(IMAGE_BL31) 179 # define PLATFORM_STACK_SIZE UL(0x800) 180 #elif defined(IMAGE_BL32) 181 # define PLATFORM_STACK_SIZE UL(0x440) 182 #endif 183 184 #define MAX_IO_DEVICES 3 185 #define MAX_IO_HANDLES 4 186 187 /* Reserve the last block of flash for PSCI MEM PROTECT flag */ 188 #define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE 189 #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 190 191 #if ARM_GPT_SUPPORT 192 /* 193 * Offset of the FIP in the GPT image. BL1 component uses this option 194 * as it does not load the partition table to get the FIP base 195 * address. At sector 34 by default (i.e. after reserved sectors 0-33) 196 * Offset = 34 * 512(sector size) = 17408 i.e. 0x4400 197 */ 198 #define PLAT_ARM_FIP_OFFSET_IN_GPT 0x4400 199 #endif /* ARM_GPT_SUPPORT */ 200 201 #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE 202 #define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 203 204 /* 205 * PL011 related constants 206 */ 207 #define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE 208 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ 209 210 #define PLAT_ARM_RUN_UART_BASE V2M_IOFPGA_UART1_BASE 211 #define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 212 213 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 214 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ 215 216 #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE 217 #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ 218 219 #define PLAT_FVP_SMMUV3_BASE UL(0x2b400000) 220 221 /* CCI related constants */ 222 #define PLAT_FVP_CCI400_BASE UL(0x2c090000) 223 #define PLAT_FVP_CCI400_CLUS0_SL_PORT 3 224 #define PLAT_FVP_CCI400_CLUS1_SL_PORT 4 225 226 /* CCI-500/CCI-550 on Base platform */ 227 #define PLAT_FVP_CCI5XX_BASE UL(0x2a000000) 228 #define PLAT_FVP_CCI5XX_CLUS0_SL_PORT 5 229 #define PLAT_FVP_CCI5XX_CLUS1_SL_PORT 6 230 231 /* CCN related constants. Only CCN 502 is currently supported */ 232 #define PLAT_ARM_CCN_BASE UL(0x2e000000) 233 #define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11 234 235 /* System timer related constants */ 236 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 237 238 /* Mailbox base address */ 239 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 240 241 242 /* TrustZone controller related constants 243 * 244 * Currently only filters 0 and 2 are connected on Base FVP. 245 * Filter 0 : CPU clusters (no access to DRAM by default) 246 * Filter 1 : not connected 247 * Filter 2 : LCDs (access to VRAM allowed by default) 248 * Filter 3 : not connected 249 * Programming unconnected filters will have no effect at the 250 * moment. These filter could, however, be connected in future. 251 * So care should be taken not to configure the unused filters. 252 * 253 * Allow only non-secure access to all DRAM to supported devices. 254 * Give access to the CPUs and Virtio. Some devices 255 * would normally use the default ID so allow that too. 256 */ 257 #define PLAT_ARM_TZC_BASE UL(0x2a4a0000) 258 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 259 260 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 261 TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \ 262 TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \ 263 TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \ 264 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \ 265 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD)) 266 267 /* 268 * GIC related constants to cater for both GICv2 and GICv3 instances of an 269 * FVP. They could be overridden at runtime in case the FVP implements the 270 * legacy VE memory map. 271 */ 272 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 273 #define PLAT_ARM_GICR_BASE BASE_GICR_BASE 274 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 275 276 /* 277 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 278 * terminology. On a GICv2 system or mode, the lists will be merged and treated 279 * as Group 0 interrupts. 280 */ 281 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 282 ARM_G1S_IRQ_PROPS(grp), \ 283 INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 284 GIC_INTR_CFG_LEVEL), \ 285 INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 286 GIC_INTR_CFG_LEVEL) 287 288 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 289 290 #if SDEI_IN_FCONF 291 #define PLAT_SDEI_DP_EVENT_MAX_CNT ARM_SDEI_DP_EVENT_MAX_CNT 292 #define PLAT_SDEI_DS_EVENT_MAX_CNT ARM_SDEI_DS_EVENT_MAX_CNT 293 #else 294 #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS 295 #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS 296 #endif 297 298 #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ 299 PLAT_SP_IMAGE_NS_BUF_SIZE) 300 301 #define PLAT_SP_PRI PLAT_RAS_PRI 302 303 /* 304 * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes 305 */ 306 #ifdef __aarch64__ 307 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) 308 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) 309 #else 310 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 311 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 312 #endif 313 314 #endif /* PLATFORM_DEF_H */ 315