1 /*
2 * Copyright (c) 2018-2020, STMicroelectronics - All Rights Reserved
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <errno.h>
9 #include <string.h>
10
11 #include <libfdt.h>
12
13 #include <platform_def.h>
14
15 #include <arch.h>
16 #include <arch_helpers.h>
17 #include <common/debug.h>
18 #include <drivers/delay_timer.h>
19 #include <drivers/mmc.h>
20 #include <drivers/st/stm32_gpio.h>
21 #include <drivers/st/stm32_sdmmc2.h>
22 #include <drivers/st/stm32mp_reset.h>
23 #include <lib/mmio.h>
24 #include <lib/utils.h>
25 #include <plat/common/platform.h>
26
27 /* Registers offsets */
28 #define SDMMC_POWER 0x00U
29 #define SDMMC_CLKCR 0x04U
30 #define SDMMC_ARGR 0x08U
31 #define SDMMC_CMDR 0x0CU
32 #define SDMMC_RESPCMDR 0x10U
33 #define SDMMC_RESP1R 0x14U
34 #define SDMMC_RESP2R 0x18U
35 #define SDMMC_RESP3R 0x1CU
36 #define SDMMC_RESP4R 0x20U
37 #define SDMMC_DTIMER 0x24U
38 #define SDMMC_DLENR 0x28U
39 #define SDMMC_DCTRLR 0x2CU
40 #define SDMMC_DCNTR 0x30U
41 #define SDMMC_STAR 0x34U
42 #define SDMMC_ICR 0x38U
43 #define SDMMC_MASKR 0x3CU
44 #define SDMMC_ACKTIMER 0x40U
45 #define SDMMC_IDMACTRLR 0x50U
46 #define SDMMC_IDMABSIZER 0x54U
47 #define SDMMC_IDMABASE0R 0x58U
48 #define SDMMC_IDMABASE1R 0x5CU
49 #define SDMMC_FIFOR 0x80U
50
51 /* SDMMC power control register */
52 #define SDMMC_POWER_PWRCTRL GENMASK(1, 0)
53 #define SDMMC_POWER_DIRPOL BIT(4)
54
55 /* SDMMC clock control register */
56 #define SDMMC_CLKCR_WIDBUS_4 BIT(14)
57 #define SDMMC_CLKCR_WIDBUS_8 BIT(15)
58 #define SDMMC_CLKCR_NEGEDGE BIT(16)
59 #define SDMMC_CLKCR_HWFC_EN BIT(17)
60 #define SDMMC_CLKCR_SELCLKRX_0 BIT(20)
61
62 /* SDMMC command register */
63 #define SDMMC_CMDR_CMDTRANS BIT(6)
64 #define SDMMC_CMDR_CMDSTOP BIT(7)
65 #define SDMMC_CMDR_WAITRESP GENMASK(9, 8)
66 #define SDMMC_CMDR_WAITRESP_SHORT BIT(8)
67 #define SDMMC_CMDR_WAITRESP_SHORT_NOCRC BIT(9)
68 #define SDMMC_CMDR_CPSMEN BIT(12)
69
70 /* SDMMC data control register */
71 #define SDMMC_DCTRLR_DTEN BIT(0)
72 #define SDMMC_DCTRLR_DTDIR BIT(1)
73 #define SDMMC_DCTRLR_DTMODE GENMASK(3, 2)
74 #define SDMMC_DCTRLR_DBLOCKSIZE GENMASK(7, 4)
75 #define SDMMC_DCTRLR_DBLOCKSIZE_SHIFT 4
76 #define SDMMC_DCTRLR_FIFORST BIT(13)
77
78 #define SDMMC_DCTRLR_CLEAR_MASK (SDMMC_DCTRLR_DTEN | \
79 SDMMC_DCTRLR_DTDIR | \
80 SDMMC_DCTRLR_DTMODE | \
81 SDMMC_DCTRLR_DBLOCKSIZE)
82
83 /* SDMMC status register */
84 #define SDMMC_STAR_CCRCFAIL BIT(0)
85 #define SDMMC_STAR_DCRCFAIL BIT(1)
86 #define SDMMC_STAR_CTIMEOUT BIT(2)
87 #define SDMMC_STAR_DTIMEOUT BIT(3)
88 #define SDMMC_STAR_TXUNDERR BIT(4)
89 #define SDMMC_STAR_RXOVERR BIT(5)
90 #define SDMMC_STAR_CMDREND BIT(6)
91 #define SDMMC_STAR_CMDSENT BIT(7)
92 #define SDMMC_STAR_DATAEND BIT(8)
93 #define SDMMC_STAR_DBCKEND BIT(10)
94 #define SDMMC_STAR_DPSMACT BIT(12)
95 #define SDMMC_STAR_RXFIFOHF BIT(15)
96 #define SDMMC_STAR_RXFIFOE BIT(19)
97 #define SDMMC_STAR_IDMATE BIT(27)
98 #define SDMMC_STAR_IDMABTC BIT(28)
99
100 /* SDMMC DMA control register */
101 #define SDMMC_IDMACTRLR_IDMAEN BIT(0)
102
103 #define SDMMC_STATIC_FLAGS (SDMMC_STAR_CCRCFAIL | \
104 SDMMC_STAR_DCRCFAIL | \
105 SDMMC_STAR_CTIMEOUT | \
106 SDMMC_STAR_DTIMEOUT | \
107 SDMMC_STAR_TXUNDERR | \
108 SDMMC_STAR_RXOVERR | \
109 SDMMC_STAR_CMDREND | \
110 SDMMC_STAR_CMDSENT | \
111 SDMMC_STAR_DATAEND | \
112 SDMMC_STAR_DBCKEND | \
113 SDMMC_STAR_IDMATE | \
114 SDMMC_STAR_IDMABTC)
115
116 #define TIMEOUT_US_1_MS 1000U
117 #define TIMEOUT_US_10_MS 10000U
118 #define TIMEOUT_US_1_S 1000000U
119
120 #define DT_SDMMC2_COMPAT "st,stm32-sdmmc2"
121
122 static void stm32_sdmmc2_init(void);
123 static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd);
124 static int stm32_sdmmc2_send_cmd(struct mmc_cmd *cmd);
125 static int stm32_sdmmc2_set_ios(unsigned int clk, unsigned int width);
126 static int stm32_sdmmc2_prepare(int lba, uintptr_t buf, size_t size);
127 static int stm32_sdmmc2_read(int lba, uintptr_t buf, size_t size);
128 static int stm32_sdmmc2_write(int lba, uintptr_t buf, size_t size);
129
130 static const struct mmc_ops stm32_sdmmc2_ops = {
131 .init = stm32_sdmmc2_init,
132 .send_cmd = stm32_sdmmc2_send_cmd,
133 .set_ios = stm32_sdmmc2_set_ios,
134 .prepare = stm32_sdmmc2_prepare,
135 .read = stm32_sdmmc2_read,
136 .write = stm32_sdmmc2_write,
137 };
138
139 static struct stm32_sdmmc2_params sdmmc2_params;
140
141 #pragma weak plat_sdmmc2_use_dma
plat_sdmmc2_use_dma(unsigned int instance,unsigned int memory)142 bool plat_sdmmc2_use_dma(unsigned int instance, unsigned int memory)
143 {
144 return false;
145 }
146
stm32_sdmmc2_init(void)147 static void stm32_sdmmc2_init(void)
148 {
149 uint32_t clock_div;
150 uint32_t freq = STM32MP_MMC_INIT_FREQ;
151 uintptr_t base = sdmmc2_params.reg_base;
152
153 if (sdmmc2_params.max_freq != 0U) {
154 freq = MIN(sdmmc2_params.max_freq, freq);
155 }
156
157 clock_div = div_round_up(sdmmc2_params.clk_rate, freq * 2U);
158
159 mmio_write_32(base + SDMMC_CLKCR, SDMMC_CLKCR_HWFC_EN | clock_div |
160 sdmmc2_params.negedge |
161 sdmmc2_params.pin_ckin);
162
163 mmio_write_32(base + SDMMC_POWER,
164 SDMMC_POWER_PWRCTRL | sdmmc2_params.dirpol);
165
166 mdelay(1);
167 }
168
stm32_sdmmc2_stop_transfer(void)169 static int stm32_sdmmc2_stop_transfer(void)
170 {
171 struct mmc_cmd cmd_stop;
172
173 zeromem(&cmd_stop, sizeof(struct mmc_cmd));
174
175 cmd_stop.cmd_idx = MMC_CMD(12);
176 cmd_stop.resp_type = MMC_RESPONSE_R1B;
177
178 return stm32_sdmmc2_send_cmd(&cmd_stop);
179 }
180
stm32_sdmmc2_send_cmd_req(struct mmc_cmd * cmd)181 static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd)
182 {
183 uint64_t timeout;
184 uint32_t flags_cmd, status;
185 uint32_t flags_data = 0;
186 int err = 0;
187 uintptr_t base = sdmmc2_params.reg_base;
188 unsigned int cmd_reg, arg_reg;
189
190 if (cmd == NULL) {
191 return -EINVAL;
192 }
193
194 flags_cmd = SDMMC_STAR_CTIMEOUT;
195 arg_reg = cmd->cmd_arg;
196
197 if ((mmio_read_32(base + SDMMC_CMDR) & SDMMC_CMDR_CPSMEN) != 0U) {
198 mmio_write_32(base + SDMMC_CMDR, 0);
199 }
200
201 cmd_reg = cmd->cmd_idx | SDMMC_CMDR_CPSMEN;
202
203 if (cmd->resp_type == 0U) {
204 flags_cmd |= SDMMC_STAR_CMDSENT;
205 }
206
207 if ((cmd->resp_type & MMC_RSP_48) != 0U) {
208 if ((cmd->resp_type & MMC_RSP_136) != 0U) {
209 flags_cmd |= SDMMC_STAR_CMDREND;
210 cmd_reg |= SDMMC_CMDR_WAITRESP;
211 } else if ((cmd->resp_type & MMC_RSP_CRC) != 0U) {
212 flags_cmd |= SDMMC_STAR_CMDREND | SDMMC_STAR_CCRCFAIL;
213 cmd_reg |= SDMMC_CMDR_WAITRESP_SHORT;
214 } else {
215 flags_cmd |= SDMMC_STAR_CMDREND;
216 cmd_reg |= SDMMC_CMDR_WAITRESP_SHORT_NOCRC;
217 }
218 }
219
220 switch (cmd->cmd_idx) {
221 case MMC_CMD(1):
222 arg_reg |= OCR_POWERUP;
223 break;
224 case MMC_CMD(8):
225 if (sdmmc2_params.device_info->mmc_dev_type == MMC_IS_EMMC) {
226 cmd_reg |= SDMMC_CMDR_CMDTRANS;
227 }
228 break;
229 case MMC_CMD(12):
230 cmd_reg |= SDMMC_CMDR_CMDSTOP;
231 break;
232 case MMC_CMD(17):
233 case MMC_CMD(18):
234 cmd_reg |= SDMMC_CMDR_CMDTRANS;
235 if (sdmmc2_params.use_dma) {
236 flags_data |= SDMMC_STAR_DCRCFAIL |
237 SDMMC_STAR_DTIMEOUT |
238 SDMMC_STAR_DATAEND |
239 SDMMC_STAR_RXOVERR |
240 SDMMC_STAR_IDMATE;
241 }
242 break;
243 case MMC_ACMD(41):
244 arg_reg |= OCR_3_2_3_3 | OCR_3_3_3_4;
245 break;
246 case MMC_ACMD(51):
247 cmd_reg |= SDMMC_CMDR_CMDTRANS;
248 if (sdmmc2_params.use_dma) {
249 flags_data |= SDMMC_STAR_DCRCFAIL |
250 SDMMC_STAR_DTIMEOUT |
251 SDMMC_STAR_DATAEND |
252 SDMMC_STAR_RXOVERR |
253 SDMMC_STAR_IDMATE |
254 SDMMC_STAR_DBCKEND;
255 }
256 break;
257 default:
258 break;
259 }
260
261 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS);
262
263 /*
264 * Clear the SDMMC_DCTRLR if the command does not await data.
265 * Skip CMD55 as the next command could be data related, and
266 * the register could have been set in prepare function.
267 */
268 if (((cmd_reg & SDMMC_CMDR_CMDTRANS) == 0U) &&
269 (cmd->cmd_idx != MMC_CMD(55))) {
270 mmio_write_32(base + SDMMC_DCTRLR, 0U);
271 }
272
273 if ((cmd->resp_type & MMC_RSP_BUSY) != 0U) {
274 mmio_write_32(base + SDMMC_DTIMER, UINT32_MAX);
275 }
276
277 mmio_write_32(base + SDMMC_ARGR, arg_reg);
278
279 mmio_write_32(base + SDMMC_CMDR, cmd_reg);
280
281 status = mmio_read_32(base + SDMMC_STAR);
282
283 timeout = timeout_init_us(TIMEOUT_US_10_MS);
284
285 while ((status & flags_cmd) == 0U) {
286 if (timeout_elapsed(timeout)) {
287 err = -ETIMEDOUT;
288 ERROR("%s: timeout 10ms (cmd = %d,status = %x)\n",
289 __func__, cmd->cmd_idx, status);
290 goto err_exit;
291 }
292
293 status = mmio_read_32(base + SDMMC_STAR);
294 }
295
296 if ((status & (SDMMC_STAR_CTIMEOUT | SDMMC_STAR_CCRCFAIL)) != 0U) {
297 if ((status & SDMMC_STAR_CTIMEOUT) != 0U) {
298 err = -ETIMEDOUT;
299 /*
300 * Those timeouts can occur, and framework will handle
301 * the retries. CMD8 is expected to return this timeout
302 * for eMMC
303 */
304 if (!((cmd->cmd_idx == MMC_CMD(1)) ||
305 (cmd->cmd_idx == MMC_CMD(13)) ||
306 ((cmd->cmd_idx == MMC_CMD(8)) &&
307 (cmd->resp_type == MMC_RESPONSE_R7)))) {
308 ERROR("%s: CTIMEOUT (cmd = %d,status = %x)\n",
309 __func__, cmd->cmd_idx, status);
310 }
311 } else {
312 err = -EIO;
313 ERROR("%s: CRCFAIL (cmd = %d,status = %x)\n",
314 __func__, cmd->cmd_idx, status);
315 }
316
317 goto err_exit;
318 }
319
320 if ((cmd_reg & SDMMC_CMDR_WAITRESP) != 0U) {
321 if ((cmd->cmd_idx == MMC_CMD(9)) &&
322 ((cmd_reg & SDMMC_CMDR_WAITRESP) == SDMMC_CMDR_WAITRESP)) {
323 /* Need to invert response to match CSD structure */
324 cmd->resp_data[0] = mmio_read_32(base + SDMMC_RESP4R);
325 cmd->resp_data[1] = mmio_read_32(base + SDMMC_RESP3R);
326 cmd->resp_data[2] = mmio_read_32(base + SDMMC_RESP2R);
327 cmd->resp_data[3] = mmio_read_32(base + SDMMC_RESP1R);
328 } else {
329 cmd->resp_data[0] = mmio_read_32(base + SDMMC_RESP1R);
330 if ((cmd_reg & SDMMC_CMDR_WAITRESP) ==
331 SDMMC_CMDR_WAITRESP) {
332 cmd->resp_data[1] = mmio_read_32(base +
333 SDMMC_RESP2R);
334 cmd->resp_data[2] = mmio_read_32(base +
335 SDMMC_RESP3R);
336 cmd->resp_data[3] = mmio_read_32(base +
337 SDMMC_RESP4R);
338 }
339 }
340 }
341
342 if (flags_data == 0U) {
343 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS);
344
345 return 0;
346 }
347
348 status = mmio_read_32(base + SDMMC_STAR);
349
350 timeout = timeout_init_us(TIMEOUT_US_10_MS);
351
352 while ((status & flags_data) == 0U) {
353 if (timeout_elapsed(timeout)) {
354 ERROR("%s: timeout 10ms (cmd = %d,status = %x)\n",
355 __func__, cmd->cmd_idx, status);
356 err = -ETIMEDOUT;
357 goto err_exit;
358 }
359
360 status = mmio_read_32(base + SDMMC_STAR);
361 };
362
363 if ((status & (SDMMC_STAR_DTIMEOUT | SDMMC_STAR_DCRCFAIL |
364 SDMMC_STAR_TXUNDERR | SDMMC_STAR_RXOVERR |
365 SDMMC_STAR_IDMATE)) != 0U) {
366 ERROR("%s: Error flag (cmd = %d,status = %x)\n", __func__,
367 cmd->cmd_idx, status);
368 err = -EIO;
369 }
370
371 err_exit:
372 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS);
373 mmio_clrbits_32(base + SDMMC_CMDR, SDMMC_CMDR_CMDTRANS);
374
375 if ((err != 0) && ((status & SDMMC_STAR_DPSMACT) != 0U)) {
376 int ret_stop = stm32_sdmmc2_stop_transfer();
377
378 if (ret_stop != 0) {
379 return ret_stop;
380 }
381 }
382
383 return err;
384 }
385
stm32_sdmmc2_send_cmd(struct mmc_cmd * cmd)386 static int stm32_sdmmc2_send_cmd(struct mmc_cmd *cmd)
387 {
388 uint8_t retry;
389 int err;
390
391 assert(cmd != NULL);
392
393 for (retry = 0U; retry < 3U; retry++) {
394 err = stm32_sdmmc2_send_cmd_req(cmd);
395 if (err == 0) {
396 return 0;
397 }
398
399 if ((cmd->cmd_idx == MMC_CMD(1)) ||
400 (cmd->cmd_idx == MMC_CMD(13))) {
401 return 0; /* Retry managed by framework */
402 }
403
404 /* Command 8 is expected to fail for eMMC */
405 if (cmd->cmd_idx != MMC_CMD(8)) {
406 WARN(" CMD%u, Retry: %u, Error: %d\n",
407 cmd->cmd_idx, retry + 1U, err);
408 }
409
410 udelay(10U);
411 }
412
413 return err;
414 }
415
stm32_sdmmc2_set_ios(unsigned int clk,unsigned int width)416 static int stm32_sdmmc2_set_ios(unsigned int clk, unsigned int width)
417 {
418 uintptr_t base = sdmmc2_params.reg_base;
419 uint32_t bus_cfg = 0;
420 uint32_t clock_div, max_freq, freq;
421 uint32_t clk_rate = sdmmc2_params.clk_rate;
422 uint32_t max_bus_freq = sdmmc2_params.device_info->max_bus_freq;
423
424 switch (width) {
425 case MMC_BUS_WIDTH_1:
426 break;
427 case MMC_BUS_WIDTH_4:
428 bus_cfg |= SDMMC_CLKCR_WIDBUS_4;
429 break;
430 case MMC_BUS_WIDTH_8:
431 bus_cfg |= SDMMC_CLKCR_WIDBUS_8;
432 break;
433 default:
434 panic();
435 break;
436 }
437
438 if (sdmmc2_params.device_info->mmc_dev_type == MMC_IS_EMMC) {
439 if (max_bus_freq >= 52000000U) {
440 max_freq = STM32MP_EMMC_HIGH_SPEED_MAX_FREQ;
441 } else {
442 max_freq = STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ;
443 }
444 } else {
445 if (max_bus_freq >= 50000000U) {
446 max_freq = STM32MP_SD_HIGH_SPEED_MAX_FREQ;
447 } else {
448 max_freq = STM32MP_SD_NORMAL_SPEED_MAX_FREQ;
449 }
450 }
451
452 if (sdmmc2_params.max_freq != 0U) {
453 freq = MIN(sdmmc2_params.max_freq, max_freq);
454 } else {
455 freq = max_freq;
456 }
457
458 clock_div = div_round_up(clk_rate, freq * 2U);
459
460 mmio_write_32(base + SDMMC_CLKCR,
461 SDMMC_CLKCR_HWFC_EN | clock_div | bus_cfg |
462 sdmmc2_params.negedge |
463 sdmmc2_params.pin_ckin);
464
465 return 0;
466 }
467
stm32_sdmmc2_prepare(int lba,uintptr_t buf,size_t size)468 static int stm32_sdmmc2_prepare(int lba, uintptr_t buf, size_t size)
469 {
470 struct mmc_cmd cmd;
471 int ret;
472 uintptr_t base = sdmmc2_params.reg_base;
473 uint32_t data_ctrl = SDMMC_DCTRLR_DTDIR;
474 uint32_t arg_size;
475
476 assert(size != 0U);
477
478 if (size > MMC_BLOCK_SIZE) {
479 arg_size = MMC_BLOCK_SIZE;
480 } else {
481 arg_size = size;
482 }
483
484 sdmmc2_params.use_dma = plat_sdmmc2_use_dma(base, buf);
485
486 if (sdmmc2_params.use_dma) {
487 inv_dcache_range(buf, size);
488 }
489
490 /* Prepare CMD 16*/
491 mmio_write_32(base + SDMMC_DTIMER, 0);
492
493 mmio_write_32(base + SDMMC_DLENR, 0);
494
495 mmio_write_32(base + SDMMC_DCTRLR, 0);
496
497 zeromem(&cmd, sizeof(struct mmc_cmd));
498
499 cmd.cmd_idx = MMC_CMD(16);
500 cmd.cmd_arg = arg_size;
501 cmd.resp_type = MMC_RESPONSE_R1;
502
503 ret = stm32_sdmmc2_send_cmd(&cmd);
504 if (ret != 0) {
505 ERROR("CMD16 failed\n");
506 return ret;
507 }
508
509 /* Prepare data command */
510 mmio_write_32(base + SDMMC_DTIMER, UINT32_MAX);
511
512 mmio_write_32(base + SDMMC_DLENR, size);
513
514 if (sdmmc2_params.use_dma) {
515 mmio_write_32(base + SDMMC_IDMACTRLR,
516 SDMMC_IDMACTRLR_IDMAEN);
517 mmio_write_32(base + SDMMC_IDMABASE0R, buf);
518
519 flush_dcache_range(buf, size);
520 }
521
522 data_ctrl |= __builtin_ctz(arg_size) << SDMMC_DCTRLR_DBLOCKSIZE_SHIFT;
523
524 mmio_clrsetbits_32(base + SDMMC_DCTRLR,
525 SDMMC_DCTRLR_CLEAR_MASK,
526 data_ctrl);
527
528 return 0;
529 }
530
stm32_sdmmc2_read(int lba,uintptr_t buf,size_t size)531 static int stm32_sdmmc2_read(int lba, uintptr_t buf, size_t size)
532 {
533 uint32_t error_flags = SDMMC_STAR_RXOVERR | SDMMC_STAR_DCRCFAIL |
534 SDMMC_STAR_DTIMEOUT;
535 uint32_t flags = error_flags | SDMMC_STAR_DATAEND;
536 uint32_t status;
537 uint32_t *buffer;
538 uintptr_t base = sdmmc2_params.reg_base;
539 uintptr_t fifo_reg = base + SDMMC_FIFOR;
540 uint64_t timeout;
541 int ret;
542
543 /* Assert buf is 4 bytes aligned */
544 assert((buf & GENMASK(1, 0)) == 0U);
545
546 buffer = (uint32_t *)buf;
547
548 if (sdmmc2_params.use_dma) {
549 inv_dcache_range(buf, size);
550
551 return 0;
552 }
553
554 if (size <= MMC_BLOCK_SIZE) {
555 flags |= SDMMC_STAR_DBCKEND;
556 }
557
558 timeout = timeout_init_us(TIMEOUT_US_1_S);
559
560 do {
561 status = mmio_read_32(base + SDMMC_STAR);
562
563 if ((status & error_flags) != 0U) {
564 ERROR("%s: Read error (status = %x)\n", __func__,
565 status);
566 mmio_write_32(base + SDMMC_DCTRLR,
567 SDMMC_DCTRLR_FIFORST);
568
569 mmio_write_32(base + SDMMC_ICR,
570 SDMMC_STATIC_FLAGS);
571
572 ret = stm32_sdmmc2_stop_transfer();
573 if (ret != 0) {
574 return ret;
575 }
576
577 return -EIO;
578 }
579
580 if (timeout_elapsed(timeout)) {
581 ERROR("%s: timeout 1s (status = %x)\n",
582 __func__, status);
583 mmio_write_32(base + SDMMC_ICR,
584 SDMMC_STATIC_FLAGS);
585
586 ret = stm32_sdmmc2_stop_transfer();
587 if (ret != 0) {
588 return ret;
589 }
590
591 return -ETIMEDOUT;
592 }
593
594 if (size < (8U * sizeof(uint32_t))) {
595 if ((mmio_read_32(base + SDMMC_DCNTR) > 0U) &&
596 ((status & SDMMC_STAR_RXFIFOE) == 0U)) {
597 *buffer = mmio_read_32(fifo_reg);
598 buffer++;
599 }
600 } else if ((status & SDMMC_STAR_RXFIFOHF) != 0U) {
601 uint32_t count;
602
603 /* Read data from SDMMC Rx FIFO */
604 for (count = 0; count < 8U; count++) {
605 *buffer = mmio_read_32(fifo_reg);
606 buffer++;
607 }
608 }
609 } while ((status & flags) == 0U);
610
611 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS);
612
613 if ((status & SDMMC_STAR_DPSMACT) != 0U) {
614 WARN("%s: DPSMACT=1, send stop\n", __func__);
615 return stm32_sdmmc2_stop_transfer();
616 }
617
618 return 0;
619 }
620
stm32_sdmmc2_write(int lba,uintptr_t buf,size_t size)621 static int stm32_sdmmc2_write(int lba, uintptr_t buf, size_t size)
622 {
623 return 0;
624 }
625
stm32_sdmmc2_dt_get_config(void)626 static int stm32_sdmmc2_dt_get_config(void)
627 {
628 int sdmmc_node;
629 void *fdt = NULL;
630 const fdt32_t *cuint;
631
632 if (fdt_get_address(&fdt) == 0) {
633 return -FDT_ERR_NOTFOUND;
634 }
635
636 if (fdt == NULL) {
637 return -FDT_ERR_NOTFOUND;
638 }
639
640 sdmmc_node = fdt_node_offset_by_compatible(fdt, -1, DT_SDMMC2_COMPAT);
641
642 while (sdmmc_node != -FDT_ERR_NOTFOUND) {
643 cuint = fdt_getprop(fdt, sdmmc_node, "reg", NULL);
644 if (cuint == NULL) {
645 continue;
646 }
647
648 if (fdt32_to_cpu(*cuint) == sdmmc2_params.reg_base) {
649 break;
650 }
651
652 sdmmc_node = fdt_node_offset_by_compatible(fdt, sdmmc_node,
653 DT_SDMMC2_COMPAT);
654 }
655
656 if (sdmmc_node == -FDT_ERR_NOTFOUND) {
657 return -FDT_ERR_NOTFOUND;
658 }
659
660 if (fdt_get_status(sdmmc_node) == DT_DISABLED) {
661 return -FDT_ERR_NOTFOUND;
662 }
663
664 if (dt_set_pinctrl_config(sdmmc_node) != 0) {
665 return -FDT_ERR_BADVALUE;
666 }
667
668 cuint = fdt_getprop(fdt, sdmmc_node, "clocks", NULL);
669 if (cuint == NULL) {
670 return -FDT_ERR_NOTFOUND;
671 }
672
673 cuint++;
674 sdmmc2_params.clock_id = fdt32_to_cpu(*cuint);
675
676 cuint = fdt_getprop(fdt, sdmmc_node, "resets", NULL);
677 if (cuint == NULL) {
678 return -FDT_ERR_NOTFOUND;
679 }
680
681 cuint++;
682 sdmmc2_params.reset_id = fdt32_to_cpu(*cuint);
683
684 if ((fdt_getprop(fdt, sdmmc_node, "st,use-ckin", NULL)) != NULL) {
685 sdmmc2_params.pin_ckin = SDMMC_CLKCR_SELCLKRX_0;
686 }
687
688 if ((fdt_getprop(fdt, sdmmc_node, "st,sig-dir", NULL)) != NULL) {
689 sdmmc2_params.dirpol = SDMMC_POWER_DIRPOL;
690 }
691
692 if ((fdt_getprop(fdt, sdmmc_node, "st,neg-edge", NULL)) != NULL) {
693 sdmmc2_params.negedge = SDMMC_CLKCR_NEGEDGE;
694 }
695
696 cuint = fdt_getprop(fdt, sdmmc_node, "bus-width", NULL);
697 if (cuint != NULL) {
698 switch (fdt32_to_cpu(*cuint)) {
699 case 4:
700 sdmmc2_params.bus_width = MMC_BUS_WIDTH_4;
701 break;
702
703 case 8:
704 sdmmc2_params.bus_width = MMC_BUS_WIDTH_8;
705 break;
706
707 default:
708 break;
709 }
710 }
711
712 cuint = fdt_getprop(fdt, sdmmc_node, "max-frequency", NULL);
713 if (cuint != NULL) {
714 sdmmc2_params.max_freq = fdt32_to_cpu(*cuint);
715 }
716
717 return 0;
718 }
719
stm32_sdmmc2_mmc_get_device_size(void)720 unsigned long long stm32_sdmmc2_mmc_get_device_size(void)
721 {
722 return sdmmc2_params.device_info->device_size;
723 }
724
stm32_sdmmc2_mmc_init(struct stm32_sdmmc2_params * params)725 int stm32_sdmmc2_mmc_init(struct stm32_sdmmc2_params *params)
726 {
727 int rc;
728
729 assert((params != NULL) &&
730 ((params->reg_base & MMC_BLOCK_MASK) == 0U) &&
731 ((params->bus_width == MMC_BUS_WIDTH_1) ||
732 (params->bus_width == MMC_BUS_WIDTH_4) ||
733 (params->bus_width == MMC_BUS_WIDTH_8)));
734
735 memcpy(&sdmmc2_params, params, sizeof(struct stm32_sdmmc2_params));
736
737 if (stm32_sdmmc2_dt_get_config() != 0) {
738 ERROR("%s: DT error\n", __func__);
739 return -ENOMEM;
740 }
741
742 stm32mp_clk_enable(sdmmc2_params.clock_id);
743
744 rc = stm32mp_reset_assert(sdmmc2_params.reset_id, TIMEOUT_US_1_MS);
745 if (rc != 0) {
746 panic();
747 }
748 udelay(2);
749 rc = stm32mp_reset_deassert(sdmmc2_params.reset_id, TIMEOUT_US_1_MS);
750 if (rc != 0) {
751 panic();
752 }
753 mdelay(1);
754
755 sdmmc2_params.clk_rate = stm32mp_clk_get_rate(sdmmc2_params.clock_id);
756 sdmmc2_params.device_info->ocr_voltage = OCR_3_2_3_3 | OCR_3_3_3_4;
757
758 return mmc_init(&stm32_sdmmc2_ops, sdmmc2_params.clk_rate,
759 sdmmc2_params.bus_width, sdmmc2_params.flags,
760 sdmmc2_params.device_info);
761 }
762