1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef BOARD_CSS_DEF_H 8 #define BOARD_CSS_DEF_H 9 10 #include <lib/utils_def.h> 11 #include <plat/arm/board/common/v2m_def.h> 12 #include <plat/arm/soc/common/soc_css_def.h> 13 #include <plat/common/common_def.h> 14 15 /* 16 * Definitions common to all ARM CSS-based development platforms 17 */ 18 19 /* Platform ID address */ 20 #define BOARD_CSS_PLAT_ID_REG_ADDR 0x7ffe00e0 21 22 /* Platform ID related accessors */ 23 #define BOARD_CSS_PLAT_ID_REG_ID_MASK 0x0f 24 #define BOARD_CSS_PLAT_ID_REG_ID_SHIFT 0x0 25 #define BOARD_CSS_PLAT_ID_REG_VERSION_MASK 0xf00 26 #define BOARD_CSS_PLAT_ID_REG_VERSION_SHIFT 0x8 27 #define BOARD_CSS_PLAT_TYPE_RTL 0x00 28 #define BOARD_CSS_PLAT_TYPE_FPGA 0x01 29 #define BOARD_CSS_PLAT_TYPE_EMULATOR 0x02 30 #define BOARD_CSS_PLAT_TYPE_FVP 0x03 31 32 #ifndef __ASSEMBLER__ 33 34 #include <lib/mmio.h> 35 36 #define BOARD_CSS_GET_PLAT_TYPE(addr) \ 37 ((mmio_read_32(addr) & BOARD_CSS_PLAT_ID_REG_ID_MASK) \ 38 >> BOARD_CSS_PLAT_ID_REG_ID_SHIFT) 39 40 #endif /* __ASSEMBLER__ */ 41 42 43 #define MAX_IO_DEVICES 3 44 #define MAX_IO_HANDLES 4 45 46 /* Reserve the last block of flash for PSCI MEM PROTECT flag */ 47 #define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE 48 #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 49 50 #if ARM_GPT_SUPPORT 51 /* 52 * Offset of the FIP in the GPT image. BL1 component uses this option 53 * as it does not load the partition table to get the FIP base 54 * address. At sector 34 by default (i.e. after reserved sectors 0-33) 55 * Offset = 34 * 512(sector size) = 17408 i.e. 0x4400 56 */ 57 #define PLAT_ARM_FIP_OFFSET_IN_GPT 0x4400 58 #endif /* ARM_GPT_SUPPORT */ 59 60 #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE 61 #define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 62 63 /* UART related constants */ 64 #define PLAT_ARM_BOOT_UART_BASE SOC_CSS_UART0_BASE 65 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ SOC_CSS_UART0_CLK_IN_HZ 66 67 #define PLAT_ARM_RUN_UART_BASE SOC_CSS_UART1_BASE 68 #define PLAT_ARM_RUN_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ 69 70 #define PLAT_ARM_SP_MIN_RUN_UART_BASE SOC_CSS_UART1_BASE 71 #define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ 72 73 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 74 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ 75 76 #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART0_BASE 77 #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ 78 79 #endif /* BOARD_CSS_DEF_H */ 80