1 /*
2 * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
3 * Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <arch.h>
9 #include <arch_helpers.h>
10 #include <assert.h>
11 #include <common/bl_common.h>
12 #include <drivers/arm/gicv2.h>
13 #include <drivers/ti/uart/uart_16550.h>
14 #include <lib/mmio.h>
15 #include <lib/xlat_tables/xlat_tables.h>
16
17 #include "socfpga_mailbox.h"
18 #include "socfpga_private.h"
19
20 static entry_point_info_t bl32_image_ep_info;
21 static entry_point_info_t bl33_image_ep_info;
22
bl31_plat_get_next_image_ep_info(uint32_t type)23 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
24 {
25 entry_point_info_t *next_image_info;
26
27 next_image_info = (type == NON_SECURE) ?
28 &bl33_image_ep_info : &bl32_image_ep_info;
29
30 /* None of the images on this platform can have 0x0 as the entrypoint */
31 if (next_image_info->pc)
32 return next_image_info;
33 else
34 return NULL;
35 }
36
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)37 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
38 u_register_t arg2, u_register_t arg3)
39 {
40 static console_t console;
41
42 mmio_write_64(PLAT_SEC_ENTRY, PLAT_SEC_WARM_ENTRY);
43
44 console_16550_register(PLAT_UART0_BASE, PLAT_UART_CLOCK, PLAT_BAUDRATE,
45 &console);
46 /*
47 * Check params passed from BL31 should not be NULL,
48 */
49 void *from_bl2 = (void *) arg0;
50
51 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
52 assert(params_from_bl2 != NULL);
53
54 /*
55 * Copy BL32 (if populated by BL31) and BL33 entry point information.
56 * They are stored in Secure RAM, in BL31's address space.
57 */
58
59 if (params_from_bl2->h.type == PARAM_BL_PARAMS &&
60 params_from_bl2->h.version >= VERSION_2) {
61
62 bl_params_node_t *bl_params = params_from_bl2->head;
63
64 while (bl_params) {
65 if (bl_params->image_id == BL33_IMAGE_ID)
66 bl33_image_ep_info = *bl_params->ep_info;
67
68 bl_params = bl_params->next_params_info;
69 }
70 } else {
71 struct socfpga_bl31_params *arg_from_bl2 =
72 (struct socfpga_bl31_params *) from_bl2;
73
74 assert(arg_from_bl2->h.type == PARAM_BL31);
75 assert(arg_from_bl2->h.version >= VERSION_1);
76
77 bl32_image_ep_info = *arg_from_bl2->bl32_ep_info;
78 bl33_image_ep_info = *arg_from_bl2->bl33_ep_info;
79 }
80 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
81 }
82
83 static const interrupt_prop_t s10_interrupt_props[] = {
84 PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(GICV2_INTR_GROUP0),
85 PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(GICV2_INTR_GROUP0)
86 };
87
88 static unsigned int target_mask_array[PLATFORM_CORE_COUNT];
89
90 static const gicv2_driver_data_t plat_gicv2_gic_data = {
91 .gicd_base = PLAT_INTEL_SOCFPGA_GICD_BASE,
92 .gicc_base = PLAT_INTEL_SOCFPGA_GICC_BASE,
93 .interrupt_props = s10_interrupt_props,
94 .interrupt_props_num = ARRAY_SIZE(s10_interrupt_props),
95 .target_masks = target_mask_array,
96 .target_masks_num = ARRAY_SIZE(target_mask_array),
97 };
98
99 /*******************************************************************************
100 * Perform any BL3-1 platform setup code
101 ******************************************************************************/
bl31_platform_setup(void)102 void bl31_platform_setup(void)
103 {
104 socfpga_delay_timer_init();
105
106 /* Initialize the gic cpu and distributor interfaces */
107 gicv2_driver_init(&plat_gicv2_gic_data);
108 gicv2_distif_init();
109 gicv2_pcpu_distif_init();
110 gicv2_cpuif_enable();
111
112 /* Signal secondary CPUs to jump to BL31 (BL2 = U-boot SPL) */
113 mmio_write_64(PLAT_CPU_RELEASE_ADDR,
114 (uint64_t)plat_secondary_cpus_bl31_entry);
115
116 mailbox_hps_stage_notify(HPS_EXECUTION_STATE_SSBL);
117 }
118
119 const mmap_region_t plat_agilex_mmap[] = {
120 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS),
121 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_NS),
122 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
123 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE,
124 MT_NON_CACHEABLE | MT_RW | MT_SECURE),
125 MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE,
126 MT_DEVICE | MT_RW | MT_SECURE),
127 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, MT_DEVICE | MT_RW | MT_NS),
128 MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE, MT_DEVICE | MT_RW | MT_NS),
129 {0}
130 };
131
132 /*******************************************************************************
133 * Perform the very early platform specific architectural setup here. At the
134 * moment this is only intializes the mmu in a quick and dirty way.
135 ******************************************************************************/
bl31_plat_arch_setup(void)136 void bl31_plat_arch_setup(void)
137 {
138 const mmap_region_t bl_regions[] = {
139 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE,
140 MT_MEMORY | MT_RW | MT_SECURE),
141 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
142 MT_CODE | MT_SECURE),
143 MAP_REGION_FLAT(BL_RO_DATA_BASE,
144 BL_RO_DATA_END - BL_RO_DATA_BASE,
145 MT_RO_DATA | MT_SECURE),
146 #if USE_COHERENT_MEM
147 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE,
148 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
149 MT_DEVICE | MT_RW | MT_SECURE),
150 #endif
151 {0}
152 };
153
154 setup_page_tables(bl_regions, plat_agilex_mmap);
155 enable_mmu_el3(0);
156 }
157
158